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National Semiconductor LM1276 handbook

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1. RSV RSV CLMP sw OOR Bits 1 0 Reserved and should be set to zero Bit 2 This is the Vertical Blanking register When this bit is a 1 vertical blanking is gated to the video outputs When set to a 0 the video outputs do not have vertical blanking Bit 3 This is the OSD override bit This should be set to O for normal operation When set to a 1 the video outputs are disconnected and OSD only is displayed This is useful for the OSD display of special conditions such as No Signal and Input Signal Out of Range to avoid seeing unsynchronized video Bit 4 Setting this bit will internally tie the clamp pin to the horizontal sync pin and the clamp pin will not require an external input signal Bit 5 This is the Clamp Polarity bit When set to a 0 the LM1276 expects a positive going clamp pulse When set to a 1 the expected pulse is negative going Bits 7 6 Reserved and should be set to zero OSD Tone Transparency OSD TRANSP TONE 0x85C0 OSD TONE OSDTONE 6 0 Bits 6 0 These bits determine the transparency level of the OSD background Bit 7 Reserved and should be set to zero 39 www national com 9211 LM1276 Pre Amplifier Interface Registers Continued Center Frequency EMPHASIS_CENTF 0x85C1 Center Frequency Res d Res d Res d Res d CENTF 3 0 RSV RSV RSV RSV Bits 3 0 Reserved and should be set to zero Bits 7 4 These 4 bit
2. WAG RAGA SMES WWE eX National Semiconductor LM1276 DACs General Description The LM1276 pre amp is an integrated CMOS CRT preamp with an integrated Hi Brite Window generator 512 Character OSD generator and an auto size measurement circuit It has an 12 compatible interface which allows control of all the parameters necessary to directly setup and adjust the gain and contrast in the CRT display Brightness and bias can be controlled through the DAC outputs which are well matched to the LM2479 and LM2480 integrated bias clamp ICs The LM1276 preamp is also designed to be compatible with the LM247x high gain driver family Black level clamping of the video signal is carried out directly on the AC coupled input signal into the high impedance preamplifier input thus eliminating the need for additional clamp capacitors Horizontal and vertical blanking of the outputs is provided Vertical blanking is optional and its duration is register programmable The IC is packaged in an industry standard 28 lead narrow DIP molded plastic package Features Integrated Hi Brite Window Generator operation independent of the Microcontroller Programmable Video Emphasis Control 8 Programmable Hi Brite Windows Hi Brite Enhancement on full screen window only or outside of windows Fully addressable 512 Character OSD m Internal 512 character OSD ROM usable as either a 384 2 color plus 128 4 colo
3. VABL VABL MIN GAIN Beyond 5 dB the gain characteristics linearity and pulse response may depart from normal values Note 13 Machine Model ESD test is covered by specification EIAJ IC 121 1981 A 200 pF cap is charged to the specific voltage then discharged directly into the IC with no external series resistor resistance of discharge path must be under 500 Note 14 Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation Terminate the undriven amplifier inputs to simulate generator loading Repeat test at fiy 10 MHz for Vsgp 10 MHz Note 15 A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz This limit is guaranteed by design If a lower line rate is used then a longer clamp pulse may be required Note 16 Adjust input frequency from 10 MHz Ay max reference level to the 3 dB corner frequency f_3 Note 17 Once the spot killer has been activated the LM1276 remains in the off state until is cycled reduced below 0 5V and then restored to 5V register value For example the OSD contrast bits are the fourth fifth and sixth bits of register 0x8538 Since the first bit is bit 0 the OSD contrast register is 0x8538 5 3 Hexadecimal and Binary Notation Hexadecimal numbers appear frequently throughout this document representing slave and register addresses and register values These appear in the fo
4. Bits 6 0 This register determines the gain of the blue video channel This affects only the blue channel whereas the contrast register 0x8433 affects all channels Bit 7 Reserved and should be set to zero Green Channel Gain GGAINCTRL 0x8431 Green Gain RSV GGAIN 6 0 Bits 6 0 This register determines the gain of the green video channel This affects only the green channel whereas the contrast register 0x8433 affects all channels Bit 7 Reserved and should be set to zero Red Channel Gain RGAINCTRL 0x8432 Res d Red Gain RSV RGAIN 6 0 Bits 6 0 This register determines the gain of the red video channel This affects only the red channel whereas the contrast register 0x8433 affects all channels Bit 7 Reserved and should be set to zero Contrast Control CONTRCTRL 0x8433 CRed RSV CONTRAST 6 0 37 www national com 9211 LM1276 Pre Amplifier Interface Registers Continued Bits 6 0 This register determines the contrast gain and affects all three channels blue red and green Bit 7 Reserved and should be set to zero DAC 1 Output Level DAC1CTRL 0x8434 DAC 1 Output Level DAC1 7 0 Bits 7 0 DAC 2 Output Level This register determines the output of DAC 1 The full scale output is determined by bit 6 of the DAC Config OSD Contrast amp DC Offset Register 0 8438 DAC2CTRL
5. lt zs e 8 Nid ATA eza dVO J YdS e L 9 Nid LY 39008 uvas 28029 955 2 I mol 055 001 0 H3Qv3H m i gt 6L T6L XZPZW1 en OLLVIN3HOS OWJA XZvZ 9 2WW1 100 318 20096925 LM1276 LM2476 Demo Board Schematic continued FIGURE 10 18 www national com PCB Layout e 2 m x x O Lu z N N x x o N i N N 4 N a a m a csi T 227222 2 S ai 227 ce cm B38 2 5 9 O T 2 255000500000 National Semiconductor HS GND BL T 0 550 Qi ic SUSE UFB CLHP GND 210 HTR GND G1 Pisa 20096970 FIGURE 11 LM1276 LM2476 Demo Board Layout 19 www national com 9211 LM1276 Burn In Screen The LM1276 provides a Burn In Screen feature where a full screen of white video will be displayed without the need for any video input The Burn In Screen is enabled by setting bit 5 of register 0x8439 to 1 The contrast level of this Burn In display can be adjusted with a 2 Bit DAC over the range of 65 to 85 of normal white level video This adjustment is made with register 0X8439 7 6 Programmable Horizontal Blank The leading edge position of the internal horizontal blank can be p
6. TYP 09 15 0 014 0 35 0 006 0 15 0 144 3 65 0 128 3 25 0 133 3 4 0 118 3 0 280 20096968 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications For the most current product information visit us at www national com LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user BANNED SUBSTANCE COMPLIANCE 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification CSP 9 111C2 and the Ba
7. 20096944 FIGURE 19 ROM Bank 0 Two Color Character Font 20096945 FIGURE 20 ROM Bank 1 Two Color Character Font 47 www national com 9211 LM1276 Attribute Table and Enhanced Features Continued wT ee ee H LE us E uus an H H H H Pt iiu iiu n H H H H H1 HN m ip H H Bn H H B k H RR Hua i i i BO Cho Char 20096946 FIGURE 21 ROM Bank 2 Two Color Character Font 20096947 FIGURE 22 ROM Bank 3 Four Color Character Font 8 FERE E Er 20096948 FIGURE 23 ROM Bank 4 Two Color Character Font www national com 48 Attribute Table and Enhanced Features continued 20096949 FIGURE 24 ROM Bank 5 Two Color Character Font 11 SP Mh LL nil iFi LES Li Hoel t dH 3 20096950 FIGURE 25 ROM Bank 6 Two Color Character Font 20096951 FIGURE 26 ROM Bank 7 Four Color Character Font 49 www national com 921111 Character RAM and 4 DACs LM1276 150 MHz Compatible RGB Preamplifier with Internal 512 Character OSD ROM 512 Physical Dimensions inches millimeters unless otherwise noted 1 378 35 0 1 354 34 4 0 278 7 05 0 262 6 65 PIN 1 INDEX 0 144 3 65 0 128 3 25 0 100 2 54 0 022 0 56 0 014 0 36 0 300 7 62
8. 32 C W 3 Junction Temperature Ty 150 C If Military Aerospace specified devices are required ESD Susceptibility Note 4 3 0 kV please contact the National Semiconductor Sales Office ESD Machine Model Note 13 350V Distributors for availability and specifications Storage Temperature 65 C to 150 C Supply Voltage Vcc Pins 10 14 17 Lead Temperature Soldering 10 sec 265 C and 22 6 0V Peak Video DC Output Source Current Operating Ratings Note 2 Any One Amp Pins 23 24 or 25 1 5 mA Voltage at Any Input Pin Vi 0 5 lt Vin Vcc 0 5V Temperature Range 0 C to 70 C Video Inputs pk pk 0 0V lt Vin lt 1 2V Supply Voltage Voc 4 75 lt Voc lt 5 25V Thermal Resistance to Ambient 0 4 51 C W Video Inputs pk pk 0 0V lt Vin 1 0V Power Dissipation Pp Above 25 Derate Based 6 and T 2 4W Video Signal Electrical Characteristics Unless otherwise noted T4 25 C Vec 5 0V Vin 0 70 Vp p Voc C 8 pF Video Outputs 2 0 Vp p Setting numbers refer to the definitions in Table 1 See Note 7 for Min and Max parameters and Note 6 for Typicals Symbol Parameter Conditions i Typ Max Units 15 Supply Current Test Setting 1 both supplies no 220 300 m output loading See Note 8 15 Supply Current Power Save Test Setting 1 both supplies no 55 85 mA Mode output loading See Note 8 Vo BLK A B Typical Video Black Level No AC Input Signal Difference between Normal
9. Once measurement is completed and the auto size enable bit has cleared itself back to 0 the measured data is ready to be read by the microcontroller Reading this register before that may give erroneous results This register resets to default values ready to record new measured values when the auto size enable bit is set again 41 www national com LM1276 Auto Size Registers continued Horizontal Flyback or Sync Duration HF S1 0x8583 HF 50 0x8582 Reserved Horizontal Flyback or Sync Duration RSV Bits 9 0 This is a 10 bit wide register that records the measured value of the horizontal flyback or sync during video detect When no video is detected this register should return a value of zero Once measurement is completed and the auto size enable bit has cleared itself back to 0 the measured data is ready to be read by the microcontroller Reading this register before that may give erroneous results This register resets to default values ready to record new measured values when the auto size enable bit is set again Horizontal Back Porch Duration H_BP1 0x8585 H_BPO 0x8584 Reserved Horizontal Back Porch Duration RSV RSV RSV RSV RSV HBP 10 0 Bits 10 0 This is an 11 bit wide register that records the lowest measured value of the horizontal back porch during video detect When no video is detected the sum of this register and the horizontal flyback
10. 0x8435 DAC 2 Output Level DAC2 7 0 Bits 7 0 This register determines the output of DAC 2 The full scale output is determined by bit 6 of the DAC Config OSD Contrast amp DC Offset Register 0x8438 DAC 3 Output Level Bits 7 0 DAC 4 Output Level DAC3CTRL 0x8436 DAC 3 Output Level DAC3 7 0 This register determines the output of DAC 3 The full scale output is determined by bit 6 of the DAC Config OSD Contrast amp DC Offset Register 0x8438 DACACTRL 0x8437 DAC 4 Output Level DACA 7 0 Bits 7 0 This register determines the output of DAC 4 The output of this DAC can be scaled and mixed with the outputs of DACs 1 3 as determined by bit 7 of the DAC Config OSD Contrast amp DC Offset Register 0x8438 DAC Config OSD Contrast amp DC Offset DACOSDDCOFF 0x8438 DC DCF 1 0 OSD 2 0 DC 2 0 Bits 2 0 These determine the DC offset of the three video outputs blue red and green Bits 5 3 These determine the contrast of the internally generated OSD Bit 6 When this bit is a 0 the full scale outputs of DACs 1 3 are 0 5V to 4 5V When it is a 1 the full scale range is 0 5V to 2 5V Bit 7 When this bit is a 0 the DAC 4 output is independent When it is a 1 the DAC 4 output is scaled by 50 and added to the outputs of DACs 1 3 Global Video Control GLOBALCTRL 0 8439 Burn In Contrast Burn In www nation
11. G 2 0 R 2 0 B 2 0 Bits 8 0 These registers determine the heavy button box lowlight shading or shadow color Bits 15 9 Reserved These bits should be set to zero www national com 34 Control Register Definitions continued ROM Signature Control Register ROMSIGCTRL 0x840D Reserved Check X X X X X x CRS Bit 0 This controls the calculation of the ROM signature Setting this bit causes the ROM to be read sequentially and a 16 bit checksum calculated over the 256 characters The sum modulo 65535 is stored in the ROM Signature Data Register and this bit is then automatically cleared Bits 7 1 Reserved These should be set to zero ROM Signature Data ROMSIGDATAB1 0x840F ROMSIGDATABO 0x840E 16 Bit Checksum CRC 15 0 Bits 15 0 This is the checksum of the 256 ROM characters truncated to 16 bits modulo 65535 All devices with the same masked ROM will have the same checksum Display Window 1 Horizontal Start Address HSTRT1 0x8410 Window 1 Horizontal Start Location HPOS1 7 0 Bits 7 0 There are two possible OSD windows which can be displayed simultaneously or individually This register determines the horizontal start position of Window 1 in OSD pixels not video signal pixels The actual position to the right of the horizontal flyback pulse is determined by multiplying this register value by 4 and adding 30 Due to pipelin
12. OSD intensity will be higher than if the starting point is with the gains at 0x55 and the contrast at maximum 0x7F This tradeoff allows the fine tuning of the final OSD intensity relative to the video In addition the OSD contrast register 0 85 8 5 3 provides 8 major increments of intensity To gether these allow setting the OSD intensity to the most pleasing level ESD Protection The LM1276 features a 3 0 kV ESD protection level see Notes 4 13 This is provided by special internal circuitry which activates when the voltage at any pin goes beyond the supply rails by a preset amount This protection is applied to all the pins including SDA and SCL www national com 9 LM1276 Horizontal 500 nSecidev Vertical 1 Vidiv both 20096902 FIGURE 3 Logic Horizontal Blanking Horizontal 10 uSecidiv Vertical 1 1 Vidiv both 20096903 FIGURE 4 Logic Vertical Blanking Horizontal 1 1 Vertical 500 mV div 20096904 FIGURE 5 Deflection Horizonal Blanking Typical Performance Characteristics v sv 25 unless otherwise specified Horizontal 100 nSecidiv Vertical 1 Vidiv both 20096906 FIGURE 6 Logic Clamp Pulse Vertical 10 Vidiv 20096907 Horizontal 12 5 nSec div FIGURE 7 Red Cathode Response Reduction in dB x dB Pin 26 V 20096908 FIGURE 8 ABL Ga
13. Short pins 1 and 2 on JP2 see LM1276 pin 11 3 Open C24 C50 see LM1276 pin 14 4 Open JP3 R31 42 C17 1 R34 O 1uF nene 2 3 0 cs 20K 21 330pF c51 5 470pF 5 p HFLYBACK 3b V SYNC V SYNC ABL sv FB2 0 1uF 4 28 FERRITE BEAD VSYNC H FLYBACK C18 13 ANALOG 5V BRE R8 4TuF 0 1uF 3 eee A un 100 up 25 BLUEOUT gt 0047UF s 24 HEBOUT gt 33 ere ooru mae ul 6 23 GREEN OUT gt l R3 D1 Z cis o04zur R3 1N4148 00470 SRE CIN LM1276 22 21 045 D R9 27 Sur a I A 13 939 ali g RGB I2C PLL VCC pac2 12 Daca gt JUMPER Z lt GND pacs 8 f sacs 05 1 4148 ScL vec 17 6 sv 33 SDA 16 x C23 47uf D3 7 15 R4 1N4148 DIGITAL VCC HSYNC 75 5v A 45 ps 1N4148 33 R25 DEA 75 1N4148 gt 85v R14 2 2K NOTE 1 ALL RESISTORS 1 8 W NOTE 2 R34 amp C8 USED TO DAMP 100 V HFLYBACK PULSE 0 1uF 24K 5V LOGIC PULSE O tuF 1K EXCESSIVE FLYBACK RINGING LM1276 247X NECK REV 3 SCHEMATIC 20096924 FIGURE 9 LM1276 LM2476 Demo Board Schematic 17 www national com 9 Schematic Diagram sc
14. Skip Line Code In order to allow finer control of the vertical spacing of character lines each displayed line of characters may have up to 15 skipped i e blank lines between it and the line beneath it Each skipped line is treated as a single character pixel line so multiple scan lines may actually be displayed in order to maintain accurate size relative to the character cell An internal algorithm maintains vertical height proportionality see the section on Constant Character Height Mechanism To specify the number of skipped lines the first character in each new line of characters is interpreted differently than the others in the line Its data are interpreted as shown in Table 9 with the attribute bits setting the color of the skipped lines TABLE 9 Skipped Line Code ATTRIBUTE CODE NUMBER OF SKIPPED LINES ATTO S53 Bits 8 4 are reserved and should be set to zero Bits 3 0 determine how many blank pixel lines will be inserted between the present line of display characters and the next A range of 0 15 may be selected Bits 12 9 determine which attribute the pixels in the skipped lines will have which is always called from the two color attribute table The pixels will have the background color Color 0 of the selected attribute table entry Note that the pixels in the first line immediately below the character may be overwritten by the pixel override system that creates the button box Refer to the Button Box Formation Section for m
15. Video 0 TBD VDC and Hi Brite Video Vo BLK cH cH Typical Channel to Channel No AC Input Signal Video Black Level Difference between Normal Video and d Hi Brite Video Vo BLK Active Video Black Level Output Test Setting 4 no AC input signal DC 12 VDC Voltage offset register 0x8438 set to OxD5 Vo BLK STEP Active Video Black Level Step Test Setting 4 no AC input signal 100 5 Video Rise Time Vo Max Maximum Video Output Voltage Test Setting 3 Video in 0 70 Vp p 4 3 Test Setting 4 staircase input signal 5 9 Note 5 10 to 90 Test Setting 4 31 n AC input signal LE Linearity Error Rising Edge Overshoot Note 5 Test Setting 4 AC input 2 signal t Video Fall Time Note 5 90 to 10 Test Setting 4 29 ae AC input signal OS Falling Edge Overshoot Note 5 Test Setting 4 AC input signal BW Channel Bandwidth 3 dB Note 5 Test Setting 4 AC input MHz signal Vsep 10 kHz Video Amplifier 10 kHz Isolation Note 14 Test Setting 8 dB Vser 10 MHz Video Amplifier 10 MHz Isolation Note 14 Test Setting 8 50 Av Max Maximum Voltage Gain Test Setting 8 AC input signal 3 8 44 VN Ay C 50 Contrast Attenuation 50 Test Setting 5 AC input signal 52 dB Ay Min A Max Maximum Contrast Attenuation Test Setting 2 AC input signal 12 dB dB _ www national com 4 Video Signal Electrica
16. be opened or closed in the vertical direc tions horizontal direction or from the upper left to lower right corner Assuming the desired time to typically complete a full fade in or fade out is 0 5 seconds and if the vertical scan frequency is for example 60 Hz the number of steps is fade in fade out time _ 500ms 16 67 ms 30 steps V scan time With a typical OSD window that is 300 pixels wide and 180 video lines long the horizontal and vertical intervals would be 300 pixels _ Horizontal Interval 30 10 180 lines _ Vertical Interval 0 steps steps For a smooth fade in or fade out animation from the upper left corner to the lower right corner the horizontal to vertical interval ratio must be matched to the aspect ratio of the OSD window In the example above the 300 pixel wide by 180 lines long OSD window has an aspect ratio of 5 3 Thus the horizontal to vertical interval ratio should be set to 5 3 or 10 6 With an OSD window aspect ratio of 3 2 the H V intervals can be set to 3 2 6 4 9 6 12 8 or 15 10 for optimal operation If the calculated aspect ratio of an OSD window is a non integer ratio the H V interval ratio should meet or exceed the aspect ratio For example if the OSD aspect ratio is 3 7 2 or 1 85 1 the H V intervals should be set to 2 1 4 2 6 3 8 4 10 5 or 12 6 The fade in out speed increases as H V interval settings are increased The OSD window can also be faded in or o
17. bits determine the amount of Highlight Contrast for the TEXT mode Reserved and should be set to zero PEAKCNTLPIC 0x85CA Reserved PIC MODE OVERSHOOT RSV PM OVRSHT 2 0 These bits determine the amount of overshoot for the PIC mode Bits 7 3 Reserved and should be set to zero Highlight Contrast PIC RSV Res d HLCONTRPIC 0x85CB HILIGHT CONTRAST HILIGHT CONTRASTT 6 0 Bits 6 0 Bit 7 Peak Control MOVIE Bits 2 0 These bits determine the amount of Highlight Contrast for the PIC mode Reserved and should be set to zero PEAKCNTLMOV 0x85CC Reserved TEXT MODE OVERSHOOT RSV MM OVRSHT 2 0 These bits determine the amount of overshoot for the MOVIE mode Bits 7 3 Reserved and should be set to zero Highlight Contrast MOVIE HLCONTRTXT 0x85CD Bits 6 0 Bit 7 Res d HILIGHT CONTRAST HILIGHT CONTRAST 6 0 These bits determine the amount of Highlight Contrast for the MOVIE mode Reserved and should be set to zero Auto Size Registers Horizontal Front Porch Duration H_FP1 0x8581 0x8580 Reserved Horizontal Front Porch Duration RSV RSV RSV RSV RSV HFP 10 0 Bits 10 0 This is an 11 bit wide register that records the lowest measured value of the horizontal front porch during video detect When no video is detected this register should return a value of zero
18. display operation and auto size calculations Please see the instructions above for Auto Size calculations The following sequence which involves register OXFFFD and OxFFF8 must be done by the MCU when the OSD is en abled Register bits OXFFF8 5 4 control the PLL lock detect override function Before writing to memory to setup the OSD or enabling OSD Set register bit 0 8400 0 to high Set register bits OxFFF8 5 and OxFFF8 4 to high Set register bits OxFFFD 3 to low Initialize OSD and write to memory Set register bits 0x8400 1 and or 0x8400 2 to high Before disabling OSD Set register bits 0x8400 1 and or 0x8400 2 to low Set register bits OxFFFD 3 to high Set register bits OxFFF8 5 and OxFFF8 4 to low Set register bit 0 8400 0 to low Please see the OSD Programming section for more detailed information or displaying OSD pages and accessing the RAM Hi Brite Video Enhancement Functional Description The LM1276 enables a desired area of the CRT monitor display to be enhanced for vivid TV quality images The LM1276 along with the software that is provided by National Semiconductor is fully self sufficient and independent of the microcontroller in generating and controlling Hi Brite win dows HI BRITE VIDEO PROCESSING The enhancement is achieved with programmable empha sis programmable center frequency and an additional Con trast adjustment control that is separate from the norma
19. e color palette look up table value of 0x00 in the first 8 palette look up table address locations i e 7 will be interpreted as transparent When this bit is a one the color will be interpreted as black www national com 32 Control Register Definitions continued Bit 5 Fade In Out Enable When this bit is a 1 the OSD Fade In Fade Out function is enabled When this bit is a 0 the function is disabled Bit 6 Auto Size Enable When this bit is a 1 the Auto Size function is enabled Once video detection and measurement is completed the bit will automatically clear itself back to O Bit 7 Auto Size Done When the device has completed Auto Size calculations this bit will automatically be set high by the chip to indicate to the MCU that the Auto Size data registers are valid and available This bit is automatically cleared when the MCU sets the ASZEN bit 0x8400 6 or when the device programs a calibration sequence for the Windows HiBrite software Frame Control Register 2 FRMCTRL2 0x8401 Pixels per Line Blink Period Bits 4 0 Blink Period These five bits set the blink period of the blinking feature which is determined by mulitiplying the value of these bits by 8 and then multiplying the result by the vertical field rate Bits 7 5 Pixels per Line These three bits determine the number of pixels per line of OSD characters See Table 23 which gives the maximum horizontal scan rate Al
20. need for Software In the absence of Software this provides an alternative means of achieving emphasis and contrast boost on the picture through I C The contrast setting and overshoot that will be applied when this function is enabled will be that of the previously selected User mode during the last instance that the software was in operation For example if the user last selected the Picture Mode in the Software preference menu before exiting the program then the subsequent enabling of the Full Screen function through I C will result in the Picture Mode settings being in effect on the full screen The 2 bits that enable this function are 0x8590 5 4 Setting 0x8590 5 high will disable the HiBrite Window Generation circuit that works together with the Software and 0x8590 4 enables the Full Screen HiBrite The Window Generation Circuit must be shut off by 0 8590 5 in order for 0 8590 4 to have an effect Thus to activate the Full Screen feature simply set 0x8590 5 4 to high and to deactivate set 0x8590 5 4 to low HI BRITE WINDOW GENERATION OPTIONS Up to 8 separate windows can be drawn and enabled simul taneously with programmable sizes and coordinates The Hi Brite video enhancement can also be applied to the entire desktop rather than to a specific window area or it can be applied to everything outside of the drawn window s All of this window programming can be achieved with National Semiconductor s software and does
21. new transmission must be restarted to switch to another half of the Page RAM 31 www national com 9211 LM1276 Building Display Pages continued The Page RAM address is not automatically incremented in this mode This mode is very useful for modifying character codes and attributes in the first 256 locations of the Page RAM The attribute byte is shown in Table 19 and the sequence of transmitted bytes is shown in Table 20 Either another LSB address amp attribute amp character code or a STOP must follow after each character code TABLE 19 Half Random Address Mode ATTRIBUTE Byte X 1 0 8 3 0 TABLE 20 Sequence of Transmitted Bytes sen Tue asa woe naar T z ise naar um T z T sr REPEAT FULL RANDOM ADDRESS MODE The Full Random Address mode is very similar to the Half Random Address mode However the advantage is that the Page RAM addresses can now be entirely random There is no longer a restriction to only one half of the Page RAM The Page RAM address is not automatically incremented in this mode This is very useful for modifying character codes and attributes anywhere in the Page RAM without starting a new transmission sequence The Full Random Address mode is the most flexible mode of transmission The attribute byte is shown in Table 21 and the sequence of transmitted bytes is shown in Table 22 Either another LSB address amp MSB address amp attribute amp charac
22. or sync should be within 1 pixel of the total number of pixels per line Once measurement is completed and the auto size enable bit has cleared itself back to 0 the measured data is ready to be read by the microcontroller Reading this register before that may give erroneous results This register resets to default values ready to record new measured values when the auto size enable bit is set again Vertical Front Porch Duration V FP1 0x8587 V FPO 0x8586 Reserved Vertical Front Porch Duration RSV RSV RSV RSV RSV VFP 10 0 Bits 10 0 This is an 11 bit wide register that records the lowest measured value of the vertical front porch in terms of horizontal line periods during video detect When no video is detected this register should return a value of zero Once measurement is completed and the auto size enable bit has cleared itself back to 0 the measured data is ready to be read by the microcontroller Reading this register before that may give erroneous results This register resets to default values ready to record new measured values when the auto size enable bit is set again Vertical Sync Duration V SYN D 0x8588 Vertical Flyback or Sync Duration VSYNC 7 0 Bits 7 0 This is an 8 bit wide register that records the measured value of the vertical flyback or sync in terms of horizontal line periods during video detect Once measurement is completed and the auto size enable bit h
23. sequence begins with a start condition which consists of the master pulling SDA low while SCL is held high The Slave Device Write Address OxBA is sent next Each byte that is sent is followed by an acknowledge bit When SCL is high the master will release the SDA line The slave must pull SDA low to acknowledge The register to be www national com 24 Microcontroller Interface written to is next sent in two bytes the least significant byte being sent first The master can then send the data which consists of one or more bytes Each data byte is followed by an acknowledge bit If more than one data byte is sent the data will increment to the next address location See Figure 17 Continued READ SEQUENCE Read sequences are comprised of two I C compatible trans fer sequences The first is a write sequence that only trans fers the two byte address to be accessed The second is a read sequence that starts at the address transferred in the previous address only write access and increments to the next address upon every data byte read This is shown in Figure 18 The write sequence consists of the Start Pulse the Slave Device Write Address OxBA and the Acknowl edge bit the next byte is the least significant byte of the address to be accessed followed by its Acknowledge bit This is then followed by a byte containing the most signifi cant address byte followed by its Acknowledge bit Then a Stop bit indicates t
24. so the practical limit to the number of horizontal characters on a line is reduced by the number of characters within the horizontal blanking period The EOS code tells the OSD generator that the character codes following belong to another displayed window at the next window location An EOS code may follow normal characters or an SL code but never an EOL control code because EOL is always followed by an AC plus an SL code WRITING TO THE PAGE RAM The Display Page RAM can contain up to 512 of the above listed characters and control codes Each character or control code will consume one of the possible 512 locations For convenience writing a 1 to bit 3 of the Frame Control Register 0x8400 resets all page RAM values to zero This should be done at power up to avoid unpredictable behavior Display Window 1 will also start at the first location corresponding to the address 0x8000 This location must always contain the Skip Line SL code associated with the first line of Display Window 1 The attribute for this SL code must be written before the SL code itself and will be stored in the lower four bits of this memory location Subsequent locations should contain the characters to be displayed on line 1 of Display Window 1 until the EOL code or EOS code is written into the Display Page RAM The skip line parameters associated with the next line must always be written to the location immediately after the preceding line s End of Line character T
25. to zero Display Window 2 Column Width COLWIDTH2B3 0x841F COLWIDTH2B2 0x841E Window 2 Column Width High Bytes COL2 31 16 www national com 36 Control Register Definitions continued COLWIDTH2B1 0x841D COLWIDTH2BO 0x841C Window 2 Column Width Low Bytes COL2 15 0 Bits 31 0 These are the Display Window 2 Column Width 2x Enable Bits These thirty two bits correspond to columns 31 0 of Display Window 2 respectively A value of zero indicates the column will have normal width 12 OSD pixels A value of one indicates the column will be twice as wide as normal 24 OSD pixels For the double wide case each Character Font pixel location will be displayed twice in two consecutive horizontal pixel locations The user should note that if more than 32 display characters are programmed to reside on a line then all display characters after the first thirty two will have normal width 12 pixels Fade In Fade Out Interval Register FADE INTVL 0x8429 Vertical Interval Horizontal Interval V INTVL 3 0 INTVL 3 0 Bits 7 4 These three bits determine the interval for fading in or fading out the OSD window in the vertical direction Bits 3 0 These three bits determine the interval for fading in or fading out the OSD window in the horizontal direction Pre Amplifier Interface Registers Blue Channel Gain BGAINCTRL 0x8430 Res d Blue Gain RSV BGAIN 6 0
26. when the register is read Additional register detail is provided in the Control Register Definitions Section later in this document TABLE 11 OSD Control Register Detail FRMCTRE OSE FRMCTRL2 BLINK PERIOD 4 0 CHARFONTACC 0 00 SRST RSV RSV FONT4 VBLANKDUR 0x8403 VBLANK DURATION 6 0 CHARHTCTRL 0x8404 CHAR HEIGHT 7 0 BBHLCTRLBO 0x8405 G 1 0 R 2 0 B 2 0 BBHLCTRLB1 0x8406 2 BBLLCTRLBO 0 8407 G 1 0 R 2 0 2 0 BPLLCTRLBI x lt x CHSDWCTRLB0 M R 2 0 B 2 0 CHEDWCTRLB x x lt x ROMSIGCTRL Ox840D X X X X X X CRS ROMSIGDATABO Ox840E CRC 7 0 ROMSIGDATAB1 Ox840F CRC 15 8 HSTRT1 0x8410 HPOS1 7 0 VSTRT1 0x8411 VPOS1 7 0 W1STRTADRL ADDR1 7 0 WISTRTADRH 8 COLWIDTH1BO COL1 7 0 COLWIDTH1B1 0x8415 COL1 15 8 COLWIDTH1B2 0x8416 COL1 23 16 COLWIDTH1B3 0x8417 COL1 31 24 HSTRT2 0x8418 HPOS2 7 0 VSTRT2 0x8419 VPOS2 7 0 W2STRTADRL 0x841A ADDR2 7 0 W2STRTADRH ADDR COLWIDTH2B0 COL2 7 0 COLWIDTH2B1 COL2 15 8 COLWIDTH2B2 0 841 COL2 23 16 COLWIDTH2B3 Ox841F COL2 31 24 Any registers in the range of 0x8420 0x8426 are for National Semiconductor internal use only and should not be written to under application conditions FADE INTVL 0x8429 0x35 V INTVL 3 0 H INVTVL 3 0 PREAMPLIFIER CONTROL These registers shown in Table 12 c
27. 2 different colors using the 2 color characters with 2 different colors within any one character TRANSPARENT DISABLE In addition to the 9 lines of video data a tenth data line is generated by the transparent disable bit When this line is activated the black color code will be translated as trans parent or invisible This allows the video information from the PC system to be visible on the screen when this is present Note that this feature is enabled on any black color in any of the first 8 attribute table entries VARIABLE TONE TRANSPARENCY When the transparency is already in effect the tone of the transparency can be adjusted The contrast of the PC video that is visible in the transparent area can be varied from 100 fully transparent to 0 completely black For ex ample 50 reduction in contrast would provide a semi transparent effect Just as in the conventional transparency mode variable tone transparency is effective on back grounds or foregrounds with black color codes from only the first 8 attribute table entries This feature is controlled by 0 85 0 6 0 and is only available when the transparency mode is already enabled OSD WINDOW FADE IN FADE OUT The OSD window can be opened and closed with a fade in fade out effect The interval for fading in and fading out the OSD window in the horizontal and vertical direction is vari able and can be set by the microcontroller This allows the OSD window to
28. CED PAGE RAM ADDRESS MODES Since the LM1276 is able to support 9 bit character codes usually two bytes of Page RAM information has to be sent to every location To avoid this the LM1276 addressing control system has 3 additional addressing modes offering increased flexibility that may be helpful in sending data to the Page RAM Some of the left over bits in the Attribute byte are employed as data control bits to select the desired addressing mode as shown in Table 6 This is identified as the first byte sent in a write operation or the Page RAM s upper byte read Table 7 TABLE 15 Attribute Byte ATTRIBUTE Byte x 3 0 AUTO ATTRIBUTE MODE The Auto Attribute mode is the standard LM1247 mode that is described above in the WRITING TO THE PAGE RAM section The attribute byte is shown in Table 16 TABLE 16 Auto Attribute Mode ATTRIBUTE Byte 0 0 0 ATT 3 0 When bits 6 5 are 0 the 9th character code and the 4 bit attribute code will be automatically applied to all the character codes transmitted after this attribute byte as in the LM1237 and LM1247 This mode is useful for sending character codes that use the same attribute and which are in the same 4 out of 8 banks of the Page ROM A new transmission must be started to access another character that is not in the same 4 banks of the Page ROM and no further attribute codes can follow without stopping and restarting a ne
29. H Blank Time Delay Off Conditions Zero crossing of to 50 of output blanking start 124 1 5 Zero crossing of to 50 of output blanking end 14 100 Vai Maximum Video Blanking Level Test Setting 4 AC input signal feREERUN Free Run H Frequency Including H Blank tpw CLAMP Minimum Clamp Pulse Width See Note 15 Vc LAMP MAX VciAMP MIN Maximum Low Level Clamp Pulse Voltage Minimum High Level Clamp Pulse Voltage Video Clamp Functioning Video Clamp Functioning lei Low Clamp Gate Low Input Current Vos 2V High Clamp Gate High Input Current V54 0 4 AMP VIDEO Time from End of Clamp Pulse to Referenced to Blue Red and Green 50 i Start of Video inputs Note 1 Limits of Absolute Maximum Ratings indicate below which damage to the device must not occur Note 2 Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits Note 3 All voltages are measured with respect to GND unless otherwise specified Note 4 Human body model 100 pF discharged through a 1 5 KQ resistor Note 5 Input from signal generator t tp lt 1 ns Note 6 Typical specifications are specified at 25 C and represent the most likely parametric norm Note 7 Datasheet min max specification limits are guaranteed by design test or stati
30. HODE RESPONSE Figure 7 shows the response at the red cathode for the application circuit in Figures 9 10 The input video rise time is 1 5 ns The resulting leading edge has a 7 1 ns rise time and 7 6 overshoot while the trailing edge has a 7 1 ns rise time and 6 9 overshoot using an LM2467 driver ABL GAIN REDUCTION The ABL function reduces the contrast level of the LM1276 as the voltage on pin 26 is lowered from Vcc to around 2V Figure 8 shows the amount of gain reduction as the voltage is lowered from Vcc 5 0V to 2V The gain reduction is small until reaches the knee around 3 7V where the slope increases Many system designs will require about 3 dB to 5 dB of gain reduction in full beam limiting Additional attenu ation is possible and can be used in special circumstances However in this case video performance such as video linearity and tracking between channels will tend to depart from normal specifications The onset of ABL in the LM1276 is adjustable so that the amount of beam limiting can be varied especially for larger Hi Brite window displays where the contrast level is not desired to be reduced as much as a normal video display The beam current limiting is 4 bit adjustable in steps of 80 pA each all the way up to a delta of 1 2 mA The value of the ABL pull up resistor R2 to the external 80V supply must be selected carefully such that the ABL threshold current will be at the desired maximum i e 2 mA when reg
31. Ox858A 0x07 RSV VBP 10 8 0 8588 7 0 V_FP1_PRV 0 858 0x07 VFP PREV 10 8 V SYN PRV 0 8580 OxFF VSYNC PREV 7 0 V BPO Ox858E VBP PREV 7 0 V_BP1_PRV Ox858F VBP PREV 10 8 HB CONTROL 0 8590 INTR EN LIMIT WHLDIS FSHEN RSV RSV RSV RSV RSV RSV RSV RSV RSV STATUS 0x8591 0x00 INTR RSV MCU COMMAND 0x8592 OxFF MCU 7 0 SUB COMMAND 0x8593 OxFF SUB 7 0 SEQ NUM 0x859A OxFF SEQ NUM 7 0 PLL LOCK OxFFF8 0x00 RSV RSV psi pul RSV RSV RSV RSV SET ORR H INPUT SEL RSV Building Display Pages THE OSD WINDOW The Display Page RAM contains all of the 9 bit display character codes and their associated 4 bit attribute codes and the special 13 bit page control codes the End of Line skip line parameters and End of Screen characters The LM1276 has a distinct advantage over many OSD Generators in that it allows variable size and format windows The window size is not dictated by a fixed geometric area of RAM Instead 512 locations of 13 bit words are allocated in RAM for the definition of the windows with special control codes to define the window size and shape Window width can be any length supported by the number of pixels per line that is selected divided by the number of pixels in a character line It must be remembered that OSD characters displayed during the monitor blanking time will not be displayed on the screen
32. Please refer to the LM1247 datasheet for details Constant Character Height Mechanism Please refer to the LM1247 datasheet for details www national com 46 Attribute Table and Enhanced Features Continued Display Window 1 to Display Window 2 Spacing Please refer to the LM1247 datasheet for details Evaluation Character Fonts The character font for evaluation of the LM1276 is shown in Figure 19 through Figure 26 where each represents one of the 8 available ROM banks Each bank is shown with in creasing character address going from upper left to lower right The actual font will depend on customer customization requirements Note that the first two character codes of the two color font in ROM bank 4 0x00 and 0x01 are carried over from the LM1237 ROM where they were reserved for the End Of Screen EOS and End Of Line EOL codes respectively In the case of the LM1276 these two locations can be used for displayable characters as long as they are not needed when this bank is addressed from Bank Select Register 0 If it is addressed from Bank Select Registers 1 2 or 3 then these two lower characters will be usable Please see the section END OF LINE and END OF SCREEN CODES Similarly the first two characters in any bank which is ad dressed from Bank Select Register 0 will not be usable since those addresses will be interpreted as the EOL and EOS codes P 1 mm d mum ad
33. RAST 6 0 PEAKCNTLPIC 0 85 0x03 RSV PM OVRSHT 2 0 HLCONTRPIC Ox85CB 0x60 RSV HILIGHT_CONTRAST 6 0 PEAKCNTLMOV 0 85 0x03 RSV MM OVRSHT 2 0 HLCONTRTMOV 0 85 0 0x60 Rsv HILIGHT_CONTRAST 6 0 TWO COLOR ATTRIBUTE RAM This RAM is identical to that of the LM1247 Please refer to the LM1247 datasheet for details FOUR COLOR ATTRIBUTE RAM This RAM is identical to that of the LM1247 Please refer to the LM1247 datasheet for details AUTO SIZE AND HI BRITE REGISTERS These registers shown in Table 13 provide measured values for the Auto size function and control the Hi Brite function Registers 0x8580 0x858A are compatible to the LM1246 Auto Size Registers Reserved bits are for internal use and should not be written to and any value read should be ignored TABLE 13 LM1276 Auto Size Registers Register Address Default D7 D6 D5 D4 D3 D2 D1 DO H_FPO 0x8580 OxFF HFP 7 0 H_FP1 0x8581 0x07 RSV HFP 10 8 HF_SO 0x8582 OxFF HFL HS 7 0 HF 51 0x8583 0x03 RSV HFL HS 9 8 H_BPO 0x8584 OxFF HBP 7 0 H BP1 0x8585 0x07 RSV HBP 10 8 V FPO 0x8586 OxFF VFP 7 0 V_FP1 0x8587 0x07 RSV VFP 10 8 V SYN D 0x8588 OxFF VSYNC T7 0 29 www national com 9211 LM1276 LM1276 Address Map continued TABLE 13 LM1276 Auto Size Registers Continued Register Address Default D7 06 ps 04 13 D2 D1 DO V_BPO 0 8589 OxFF VBP 7 0 V BP1
34. VrerRexr Ground pin and power supply pin for the input analog portion of the LM1276 Note the recommended charge storage and high frequency capacitors which should be as close to pins 2 and 4 as possible External current set resistor 10k 1 sets the internal bias current level for optimum performance of the LM1276 This resistor should be placed as close to pin 3 and the pin 4 ground return as possible 5 Blue Video In 6 Red Video In T Green Video In ESD Protection These video inputs must be AC coupled with a 0047 pF cap Internal DC restoration is done at these inputs A series resistor of about 33Q and external ESD protection diodes should also be used for protection from ESD damage 8 PLL Ground 9 PLL Filter 6 2K 0 1 1000 R independent ground Recommended topology and values are shown to the left It is recommended that both filter branches be bypassed to the independent ground as close to pin 8 as possible Great care should be taken to prevent external signals from coupling into this filter from video I C etc 13 www national com 946 HINT LM1276 Pin Descriptions and Application Information Continued Pin No Pin Name Schematic Description 10 PLL Voc Voc Ferrite Bead 3 I 0 1pF 1 1 I The ground pin should be connected to the rest of the circuit ground by a short but independent PCB trace to prevent contamination by ext
35. al Characteristics Unless otherwise noted T4 25 C Vec 5 0V Vin 0 7V Vag C 8 pF Video Outputs 2 0 Vp p See Note 7 for Min and Max parameters and Note 6 for Typicals DAC parameters apply to all 4 DACs Symbol Parameter Conditions VFLYBACK Positive Switching Vertical Blanking triggered Guarantee Vspot Spot Killer Voltage Note 17 Adjusted to Activate Output Voltage pin 2 Vit SCL SDA Logic Low Input Voltage Vin SCL SDA Logic High Input Voltage SOL SDA ix SOL SDA SCL SDA Logic Low Output Voltage lo 3mA fa Min Minimum Horizontal Frequency PLL amp OSD Functioning f Maximum Horizontal Frequency PLL amp OSD Functioning in Max Horizontal Flyback Input Current Absolute Maximum during lin THRESHOLD lin H Blank Detection Threshold Flyback lin Peak Current during Flyback Design Value Horizontal Flyback Input Current Absolute Maximum during Scan 700 Peak Current during Scan Not exact Duty Cycle Dependent 1 0 0 www national com System Interface Signal Characteristics Continued Unless otherwise noted T4 25 C Voc 5 0V Vin 0 7V Voc C 8 pF Video Outputs 2 0 Vp p See Note 7 for Min and Max parameters and Note 6 for Typicals DAC parameters apply to all 4 DACs tH BLANK ON tH BLANK OFF Parameter H Blank Time Delay On
36. al com 38 Pre Amplifier Interface Registers Continued Bit 0 When this bit is a 1 the video outputs are blanked set to black level When it is a 0 video is not blanked Bit 1 When this bit is a 1 the analog sections of the preamplifier are shut down for low power consumption When it is a 0 the analog sections are enabled Bits 3 2 Reserved Bit 4 When this bit is set high the calibration sequence for the PLL Auto Mode is initiated the PLL Auto mode is activated and will unset itself upon completion Bit 5 This bit will enable the Burn In Screen Bits 7 6 These bits determine the contrast level of the Burn In Screen Auxiliary Control 1 AUXCTRL1 0 843 HBPOS 4 0 HBPOS EN Bit 0 When this bit is a 0 the horizontal blanking input at pin 28 is gated to the video outputs to provide horizontal blanking When it is a 1 the horizontal blanking at the outputs is disabled Bit 1 Reserved Bit 2 When this bit is a 1 the position of the Horizontal Blanking pulse can be programmably varied relative to the horizontal flyback in number of pixels When this bit is a 0 which is by default the horizontal blanking pulse position will not be programmable Bits 7 3 These 5 bits determine the position of the Horizontal Blanking Pulse with respect to the horizontal flyback in number of pixels Auxiliary Control 2 AUXCTRL2 0x843E Clamp Res d Clamp Switch VBlank VBL RSV RSV CLMP
37. are 64 total characters in this range 0x4000 0x6FFF R These are banks 4 5 and 6 of two color read only ROM character 0 0 4 fonts There are 192 characters in this range 0 5 0 6 0x7000 0x7FFF R This is bank 7 of four color read only ROM character fonts There 0 1 Ox7 are 64 total characters in this range When read back the low byte will contain the first eight pixels of the row with data bit O corresponding to the left most bit in the pixel row The high byte will contain the remaining four pixels in the least significant nibble The remaining 4 bits shown as X are don t care bits and should be discarded Bit 3 of the high byte corresponds to the right most pixel in the pixel row This is shown in Table 4 TABLE 4 Character ROM Read Data Register Address D7 D6 D5 D4 D3 D2 D1 DO Fonts 2 Color 0 0000 0 2 PIXEL 7 0 x Fonts 4 Color 0x3000 0x3FFE PIXEL 7 0 1 x x x x PIXEL 11 8 Fonts 2 Color 0x4000 0x6FFE PIXEL 7 0 1 x x x x PIXEL 11 8 Fonts 4 Color 0 7000 0 7 PIXEL 7 0 41 PIXEL 11 8 I CHAR_CODE 7 4 or CHAR 3 0 or Display Page 0x8000 0x83FF X ATTR CODE DISPLAY PAGE RAM Full 512 Displayable Character Access This address range 0 8000 0 81 contains the 512 characters which comprise the displayable OSD screens There must be at least one End Of Screen code 0x00 in this range to prevent unpredictable behavior NOTE To
38. as cleared itself back to 0 the measured data is ready to be read by the microcontroller Reading this register before that may give erroneous results This register resets to default values ready to record new measured values when the auto size enable bit is set again Vertical Back Porch Duration V BP1 0x858A V BPO 0x8589 Reserved Vertical Back Porch Duration RSV RSV RSV RSV RSV VBP 10 0 www national com 42 Auto Size Registers Continued Bits 10 0 This is an 11 bit wide register that records the lowest measured value of the vertical back porch in terms of horizontal line periods during video detect When no video is detected the sum of this register and the vertical flyback or sync should be within 1 line of the total number of lines per field Once measurement is completed and the auto size enable bit has cleared itself back to 0 the measured data is ready to be read by the microcontroller Reading this register before that may give erroneous results This register resets to default values ready to record new measured values when the auto size enable bit is set again Previous Field Vertical Front Porch Duration V 1 0x858C PREV V BPO 0x858B Reserved Previous Vertical Front Porch Duration RSV RSV RSV RSV RSV VFP PREV 10 0 Bits 10 0 This is an 11 bit wide register that retains the previous lowest measured value of the vertical front porch during video dete
39. avoid any unpredictable behavior this range should be cleared by writing a to bit 3 of the FRMCTRL1 Register 0x8400 immediately after power up There may also be one or more pairs of End Of Line and Skip Line codes The character code is 9 bits long The codes and characters are written as 8 bit bytes but are stored with their attributes in groups of 13 bits When writing one byte describes a displayed character CC Attribute Code AC End Of Screen EOS End Of Line EOL or Skip Line SL code When reading characters from RAM bit 1 of the Character Font Access Register 0x8402 determines whether the lower 8 bits or upper 5 bits of the Page RAM are returned Table 5 gives the lower byte read which is the first 8 character code bits when bit 1 of the Character Font Access Register is a 0 Table 6 gives the upper byte read which is the 9th character code bit and 4 attribute code bits when this bit is set to a 1 www national com 26 LM1276 Address Map Continueo TABLE 5 Page RAM Lower Byte Read Data Address Range D7 D6 D5 D4 D3 D2 D1 DO 0 8000 0 81 CHAR CODE 7 0 TABLE 6 Page RAM Upper Byte Read Data Address D7 D6 D5 D4 D3 D2 D1 DO 0 8000 0 81 X X X CC 8 3 0 RAM Data Format Each of the 512 locations in the page RAM is comprised of a 13 bit code consisting of an 9 bit character or control code and a 4 bit attribute code Each of the characters is stored i
40. ce pins Test Setting 4 20 MO 5 6 7 OSD Electrical Characteristics Unless otherwise noted T4 25 C Voc 5 0V See Note 7 for Min and Max parameters and Note 6 for Typicals Symbol VospHiGH Max 110 Parameter Maximum OSD Level with OSD Contrast 111 Maximum OSD Level with OSD Contrast 110 Conditions Palette Set at 111 OSD Contrast 111 Test Setting 3 Palette Set at 111 OSD Contrast 110 Test Setting 3 Min 101 Maximum OSD Level with OSD Contrast 101 Palette Set at 111 OSD Contrast 01 Test Setting 3 100 011 010 001 Maximum OSD Level with OSD Contrast 100 Maximum OSD Level with OSD Contrast 011 Maximum OSD Level with OSD Contrast 010 Maximum OSD Level with OSD Contrast 001 Palette Set at 111 OSD Contrast 100 Test Setting 3 Palette Set at 111 OSD Contrast 011 Test Setting 3 Palette Set at 111 OSD Contrast 010 Test Setting 3 Palette Set at 111 OSD Contrast 001 Test Setting 3 000 Maximum OSD Level with OSD Contrast 000 Palette Set at 111 OSD Contrast 000 Test Setting 3 AVosp Black Difference between OSD Black Level and Video Black Level same channel Register 0x8438 0x18 Input Video Black Same Channel Test Setting 8 www national com 9211 LM1276 OSD Electrical Charact
41. ct in horizontal line periods from the previous field It is used when interlace mode is present in order to accurately determine the correct parameter value for the frame When no video is detected this register should return a value of zero Reading this register within less than one complete field period after the Video Detect Reset may give erroneous results This register resets to zero after the Video Detect Reset has been written Previous Field Vertical Sync Duration V SYN 0 8580 Previous Vertical Sync Duration VSYNC PREV 7 0 Bits 7 0 This is an 8 bit wide register that records the previous measured value of the vertical sync during video detect in horizontal line periods from the previous field It is used when interlace mode is present in order to accurately determine the correct parameter value for the frame Reading this register within less than one complete field period after the Video Detect Reset may give erroneous results This register resets to zero after the Video Detect Reset has been written Previous Vertical Back Porch Duration PREV V BP1 0x858F PREV V BPO 0x858E Reserved Previous Vertical Back Porch Duration RSV RSV RSV RSV RSV VBP PREV 10 0 Bits 10 0 This is an 11 bit wide register that records the previous lowest measured value of the vertical back porch during video detect in horizontal line periods from the previous field It is used when interlace mode is p
42. d Sequence LM1276 Address 25 www national com 9211 LM1276 LM1276 Address Map Continued CHARACTER ROM The 512 font characters from 0x0000 to Ox7FFF can be read from ROM by addressing the individual pixel rows of the desired character Since the characters have 12 columns it takes two bytes to read a given row of pixels within one character Since the characters have 18 rows a total of 36 bytes are needed to read the entire character The 16 bit address for reading a row of pixels is formed as follows Address 0x1000 I 0x40 R 0x02 H where bank number 0x0 lt lt 0x7 Character Index within its respective bank 0x00 lt I lt Ox3F R row of pixels within the character 0x00 lt R lt 0x11 H 0 for low byte 1 for high byte Note that bit 0 of the Character Font Access Register 0x8402 needs to be set to 0 to read the 2 color fonts In order to read the four color fonts two complete reads are needed Set bit 0 of the Character Font Access Register 0x8402 to a 0 to read the least significant plane and to a 1 to read the most significant plane See Table 3 TABLE 3 Character ROM Addressing Address Range Description 0x8402 0 N 0x0000 0x2FFF These are the first 3 banks of two color read only ROM character 0 0x0 fonts There are 192 total characters in this range 0x1 0x2 0x3000 0x3FFF This is bank 3 of four color read only ROM character fonts There 0x3
43. e delays the first usable start location is approximately 42 OSD pixels following the horizontal flyback time For this reason we recommend this register be programmed with a number larger than 2 otherwise improper operation may result Display Window 1 Vertical Start Address VSTRT1 0x8411 Window 1 Vertical Start Address VPOS1 7 0 Bits 7 0 This register determines the Vertical start position of the Window 1 in constant height character lines not video scan lines The actual position is determined by multiplying this register value by 2 Note each character line is treated as a single auto height character pixel line so multiple scan lines may actually be displayed in order to maintain accurate position relative to the OSD character cell size See the Constant Character Height Mechanism section This register should be set so the entire OSD window is within the active video Display Window 1 Start Address W1STRTADRH 0 8413 W1STRTADRL 0x8412 Reserved Window 1 Start Address X ADDR1 8 0 Bits 8 0 This register determines the starting address of Display Window 1 in the Display Page RAM The power on default of 0x00 starts Window 1 at the beginning of the Page RAM 0x8000 This first address location always contains the SL code for the first line of Display Window 1 This register is new for the LM1276 and allows Window 1 to start anywhere in the Page RAM
44. e vertical blanking input to the neck board with Ry 4 7k These component values corre spond to the application circuit of Figure 9 Please note that the Horizontal Flyback signal to pin 28 MUST be continuously provided to the IC even during en ergy save or sleep modes In the application this signal should be always generated whether the VGA cable is dis connected the monitor is in energy save mofe or sleep mode Figure 5 show the case where the horizontal input is from deflection Figure 5 shows the pin 28 voltage which is de rived from a horizontal flyback pulse of 35 peak to peak with 8 2K and jumpered Figure 6 shows the pin 27 clamp input voltage superimposed on the neck board clamp logic input pulse R 1k and should be chosen to limit the pin 27 voltage to about 2 5V peak to peak This corresponds to the application circuit given in Figure 9 The clamp input pin can also be internally con nected to the Horizontal Sync pin thus eliminating the need for a Clamp signal supplied to the neckboard This can be enabled with register 0x853E 4 H SYNC amp V SYNC V Sync at pin 1 and H Sync at pin 15 must be supplied with logic level signals generated by the MCU In an application where a logic level clamp pulse is used the same signal can be used for the H Sync input It is important that both V Sync and H Sync are always receiving signals even during VGA cable disconnect energy save mode or sleep mode CAT
45. epts either TTL or CMOS logic levels This pin can also be internally connected to the Horizontal sync pin The internal switching threshold is approximately one half of Voc An external series resistor R of about 1k is recommended to avoid overdriving the input devices In any event R must be large enough to prevent the voltage at pin 27 from going higher than or below GND ESD Protection 15 www national com LM1276 Pin Descriptions and Application Information Continued ESD Protection Pin Schematic Description 28 H Flyback H Flyback Vec o Proper operation requires current reversal Ry should be large enough to limit the peak current at pin 28 to about 4 mA during blanking and 500 pA during scan is usually needed for logic level inputs and should be large enough to make the time constant significantly larger than the horizontal period R and are typically 300Q and 330 pF when the flyback waveform has ringing and needs filtering C4 may be needed to filter extraneous noise and can be up to 100 pF www national com Schematic Diagram LM1276 Preamp Usage 1 Short pins 2 and 3 on JP2 see LM1276 pin 11 2 Short JP3 see LM1276 pin 17 5 JP4 85 A ABL A LM123X 4X Preamp Usage 1 Open remove FB2 and C3 see LM1276 pin 2 R1 R2 in schematic 10K 130K 2
46. eristics Unless otherwise noted TA Continued 25 C 5 0V See Note 7 for Min and Max parameters and Note 6 for Typicals Parameter Difference between OSD Black Level and Video Black Level between any 2 channels Symbol AVosp black Track Conditions Register 0x8438 0x18 Input Video Black Same Channel Test Setting 8 Min Typ Max Units AVosp White Output Match between Channels Vosp out Track Palette Set at 111 OSD Contrast 11 Maximum difference between R GandB DAC Output Electrical Characteristics Unless otherwise noted T4 25 C Vec 5 0V Vin 0 7V Vast C 8 pF Video Outputs 2 0 Vp p See Note 7 for Min and Max parameters and Note 6 for Typicals DAC parameters apply to all 4 DACs Output Variation between Channels OSD contrast varied from max to min Symbol Parameter Conditions win Mex Unis Mode 00 DCF 1 0 00b Vmax DAC Max Output Voltage of DAC in Register Value OxFF 235 01 DCF Mode 01 DCF 1 0 01b Max DAC DAC Output Voltage Variation 0 lt T lt 70 C ambient 05 mV C Temp with Temperature AVmax pac Voc DAC Output Voltage Variation Voc varied from 4 75V to 5 25V DAC 50 mV with register set to mid range Ox7F Monotonicity Monotonicity of the DAC 05 LSB Excluding Dead Zones Load Current 1 0 1 0 System Interface Sign
47. frequency is mea sured The center frequency is expressed as the time it takes the overshoot to settle to within 5 of the DC level of the pulse t Center Freq 20096973 FIGURE 15 Center Frequency Measurement Bits 4 to 7 in register OX85C1 control the center frequency When 8 is programmed into 0x85C1 7 4 the tcenter Freq is typically 80 ns An will give about 145 ns A 0 will give no emphasis in the Hi Brite window HI BRITE USER MODES There are 3 different modes whose settings are to be preset by the MCU Text Mode Movie Mode and Picture Mode each have their own HiBrite Contrast and Overshoot regis ters See the Preamp Interface Registers Table When the user selects a particular mode the preset register settings of that mode become in effect There is also a 4th mode which is the Custom Mode The Custom Mode however can be adjusted by the user through the HiBrite Software and is not preset by the MCU These modes can ONLY be selected or changed from one to another through the HiBrite Software There is no I C register to select the effective mode The default mode for the LM1276 is the Movie Mode Thus the Contrast and Overshoot settings that will be in effect when a window is initially drawn or when the Full Screen HiBrite function is called will be that of the settings preset for the Movie Mode FULL SCREEN HI BRITE The LM1276 is capable of applying HiBrite on the entire screen without the
48. he end of the address only write access Next the read data access will be performed beginning with the Start Pulse the Slave Device Read Address OxBB and the Acknowledge bit The next 8 bits will be the read data driven out by the LM1276 preamp associated with the ad dress indicated by the two address bytes Subsequent read data bytes will correspond to the next increment address locations Data should only be read from the LM1276 when both OSD windows and the Fade In Fade Out are disabled SCL SDA 6 5 4 2 1 4 2 x stan 1090111014100 0 0 Condition V Slave Write Address 0xBA LSB Address MSB Address Acknowledge SCL SDA _ D7 D6 D5 D4 D3 D2 D1 D0 __ 57 06 05 04 03 02 01 00 __ 57 6 05 04 53 02 D1 00 0 Data Byte 1 0 0 Y Stop Data Byte 2 Data Byte n Condition Acknowledge 20096938 FIGURE 17 Compatible Write Sequence SCL SDA 1011 101 0 Slave Write Address 0xBA SCL SDA 1 01 1 A7 JA6 A5 A4 A3 A2 A1 A0 0 0 0 Start 2 JAN JAN J Condition Stop LSB Address MSB Address 97 D6 D5 04031021 01100 A7 6 2 Condition Acknowledge D7 D6 D5 D4 D3 D2 01 D0 101 1 O 0 0 Condition Slave Read Data Byte 1 Data Byten Address 0 Acknowledge 20096939 FIGURE 18 Compatible Rea
49. he only exception to this rule is when an End of Screen character value 0x0000 is encountered It is important to note that an End of Line character should not precede an End of Screen character otherwise the End of Screen character will be interpreted as the next line s skip line code Instead the End of Screen code will end the line and also end the window making it unnecessary to precede it with an EOL The I C Format for writing a sequence of display characters is minimized by allowing sequential characters with the same attribute code to send in a string as follows Byte 1 12 Slave Address Byte 42 LSB Register Address Byte 43 MSB Register Address Byte 4 Attribute Table Entry to use for the following s skip line code or characters Byte 5 First display character SL parameter EOL or EOS control code Byte 46 Second display character SL parameter EOL or EOS control code Byte 47 Third display character SL parameter EOL or EOS control code Byte n Last display character in this color sequence SL parameter EOL or EOS control code to use the associated Attribute Table Entry www national com 30 Building Display Pages Continued This communication protocol is known as the Auto Attribute Mode which is also used by the LM1237 and LM1247 Please see examples of usage for this mode in the LM1247 datasheet TABLE 14 Sequence of Transmitted Bytes zm ee 9 REPEAT ENHAN
50. iconductor Corporation DS200969 www national com SOV t pue I VH ZLS GSO 194921849 ZLS gou 92 ZHIN 081 9Zc LII LM1276 Internal Block Diagram R DACs Compatible Interface On Screen Display 512 Bytes RAM 512 Byte ROM H Sync Clamp Polarity H Sync V Sync H Flyback PLL Synchronization 8 V Blanking Window Generator Control Registers Video Out Output Buffer DC Offset RGB Gain Attenuation Burn In Switch OSD Video Auto Beam Limiter ABL Switch DC Restoration Contrast Atten uation Contrast Atten uation Switch Hi Brite Video Hi Brite Video Processor amp Window Generator Auto Center Size Measurement Video In 20096961 FIGURE 1 Block Diagram www national com Internal Block Diagram continued V Sync Analog Voc V REF GND Blue Viy Red Viy Green Viy PLL GND PLL Filter PLL Digital GND SCL SDA Digital FIGURE 2 LM1276 Pinout Order Number LM1276AAA NA See NS Package Number N28D H Flyback Clamp ABL Blue Red Green Analog GND DAC1 DAC2 DAC3 Digital Voc Digital GND H Sync 20096962 www national com 9 LM1276 Absolute Maximum Ratings Notes 1 Thermal Resistance to Case
51. in Reduction Curve www national com Typical Performance Characteristics ves sv 25 C unless otherwise specified Continued SYSTEM INTERFACE SIGNALS The Horizontal Sync Flyback Vertical Sync and the Clamp input signals are important for proper functionality of the LM1276 Both blanking inputs must be present for OSD synchronization In addition the Horizontal blanking input also assists in setting the proper cathode black level along with the Clamping pulse The Vertical blanking input initiates a blanking level at the LM1276 outputs which is program mable from 3 to 127 lines at least 10 is recommended This input is set up to only accept a vertical sync pulse and the leading edge is used to start the programmable vertical blanking signal directly The start position of the internal Horizontal blanking pulse is programmable from 0 to 64 pixels ahead of the start position of the Horizontal flyback input Both horizontal and vertical blanking can be individu ally disabled if desired Figure 3 and Figure 4 show the Horizontal Flyback input when it is logic level and the Vertical input which must always be logic level Figure 3 shows the smaller pin 28 voltage superimposed on the horizontal blanking pulse input to the neck board with 4 7k and 0 1 pF Note where the voltage at pin 28 is clamped to about 1V when the pin is sinking current Figure 4 shows the smaller pin 1 voltage superimposed on th
52. iod is calculated by the microcontroller with the measured periods above The analog front end video detection is also utilized by the Video Data Interface for decoding of color bar data It is critical to note again that the threshold for video detec tion is 80mV above the internal voltage and also the minimum rise time requirement of the driving PC video card must be at least 10 0ns Excessively slow rise times in the PC video card will prevent the video detect circuit from working properly To perform an auto size calculation the following instruction sequence must be done by the MCU www national com 20 Video Detection for Auto Sizing amp Auto Centering continued OF OSD PIXELS PER LINE SYNC PERIOD OR BLANKING PERIOD BACK PORCH PERIOD VIDEO PERIOD FRONT PORCH PERIOD 20096953 FIGURE 13 Timing Intervals Auto Size Calculation Instruction Sequence Set register bits OxFFF8 5 and OxFFF8 4 to high Set register bits OxFFFD 3 to low Set register bit 0 8400 6 to high Wait for 0x8400 7 to become high by itself When 0x8400 7 is high then read auto size data regis ters 0x8580 to 0x858F Set register bits OxFFFD 3 to high Set register bits OxFFF8 5 and OxFFF8 4 to low PLL Lock Detect and Horizontal Input Select During the monitor initialization routine by the MCU register bit OxFFFD 3 must be set high This bit is only set low during OSD
53. ister 0 85 4 is at the lowest setting 0x00 There are 4 different ABL current registers corresponding to 4 different ABL settings Each setting or register 0 85 4 0x85C7 can be assigned a different ABL current threshold ABL current register 0 can correspond to a minimal area of the screen being highlighted and ABL current register 4 can correspond to the maximum area of the screen being high lighted This area is calculated by the HiBrite software and the particular ABL register that is is to be activated is se lected by the software The values of each register are written by the MCU www national com 9211 LM1276 Typical Performance Characteristics v sv 25 C unless otherwise specified Continued VIDEO PROCESSING Emphasis Center Frequency at Maximum 2 35 2 25 2 15 2 05 1 95 1 85 1 75 1 65 100 mV DIV 1 55 1 45 1 35 0 50 100 150 200 250 300 350 400 450 500 50 ns DIV 20096963 Center Frequency Emphasis at Maximum 2 35 Ss 2 05 1 95 1 85 1 75 1 65 100 mV DIV 1 55 s H L LL lI L 0 50 100150 200 250 300 350 400 450 500 50 ns DIV 20096964 These two plots show the processing done by the LM1276 on the video input signal There are two variables for the video processing emphasis and center frequency Empha sis is controlled by bits 0 2 in registers 0x85C8 0x85CA or 0x85CC Thi
54. l Video Contrast Control of the preamp Having an indepen dent contrast control allows the user to adjust the video gain normally having the higher gain to have a brighter picture within the Hi Brite window The emphasis control is used to give more sparkle to the highlighted video Video that is processed by the emphasis control has peaking added to the video Both the amplitude and the duration of the peaking are adjustable through the NSC software optimizing the emphasis for different video resolutions Maximum peaking is 20 EMPHASIS Emphasis is the amount of overshoot on the video signal Referring to Figure 14 the overshoot is the ratio of the overshoot voltage to the video level after the emphasis has settled out of the output signal The typical overshoot is about 2096 The peak measurement is taken 9 ns from the rising edge This delay gives a more accurate peak mea surement by avoiding any ringing that may occur at the rising edge Overshoot is defined in percent as B A PP x 100 Overshoot www national com 9211 LM1276 Hi Brite Video Enhancement Functional Description continued 20096972 FIGURE 14 Overshoot Measurement Bits 0 to 2 in registers 0 85 8 85 or 0x85CC control the emphasis When a 4 is programmed into these bits the overshoot is typically 11 A 0 will give no overshoot in the Hi Brite window CENTER FREQUENCY Shown in Figure 15 is how the center
55. l Characteristics continue Unless otherwise noted T4 25 C Voc 5 0V Vin 0 70 Vp p Voc C 8 pF Video Outputs 2 0 Vp p Setting numbers refer to the definitions in Table 1 See Note 7 for Min and Max parameters and Note 6 for Typicals Symbol Parameter Conditions Units Ay G 50 Gain Attenuation 50 Test Setting 6 AC input signal dB Ay G Min Maximum Gain Attenuation Test Setting 7 AC input signal dB Ay Match Maximum Gain Match between Test Setting 3 AC input signal dB Channels Ay Track Gain Change between Channels Tracking when changing from Test Setting 8 to Test Setting 5 See Note dB 11 Video Threshold Normal Operation mV ABL Control Range Upper Limit Note 12 Test Setting 4 AC input V signal Range ABL Gain Reduction Range Note 12 Test Setting 4 AC input V signal Ay 3 5 Av ABL Gain Reduction at 3 5V Note 12 Test Setting 4 AC input dB signal Vag 3 5V Ay 2 0 Ay ABL Gain Reduction at 2 0V Note 12 Test Setting 4 AC input dB signal VAg 2 0V lap Max ABL Input Current Sink Capability Note 12 Test Setting 4 AC input mA signal Max Maximum ABL Input Voltage Note 12 Test Setting 4 AC input V during Clamping signal lag lag MAX Ay ABL Track ABL Gain Tracking Error Note 9 Test Setting 4 0 7 Vp p input signal ABL voltage set to 4 5V 5 0 and 2 5V Rip Minimum Input Resistan
56. lete and must be done while the video is blanked Table 2 shows the recommended horizontal scan rate ranges in kHz for each pixels per line register setting 0x8401 7 5 These ranges are recommended for chip ambient temperatures of 09 to 70 C and the recommended PLL filter values are 6 2 kQ 0 01 uF and 1000 pF While the OSD PLL will lock for other register combinations and at scan rates outside these ranges the performance of the loop will be improved if these recommendations are followed PLL AUTO MODE INITIALIZATION SEQUENCE e Blank video Set 0x8539 4 to 1 Wait for at least 2 4 vertical periods or vertical sync pulses to pass Unblank Video This sequence must be done by the microcontroller at sys tem power up as well as each time there is a horizontal line rate change from the video source for the PLL Auto mode to function properly www national com Typical Performance Characteristics sv 25 C unless otherwise specified Continued TABLE 2 OSD Register Recommendations PPL 0 PPL 1 PPL 2 PPL 3 PPL 4 PPL 5 PPL 6 PPL 7 PLL Auto 25 61 25 53 25 98 25 110 25 110 25 108 25 102 25 96 Pin Descriptions and Application Information Pin h ipti No Pin Name Schematic escription 1 V Sync Voc Logic level vertical sync signal received from the video card in the PC or sync stripper circuit V Sync 4 7K 2 2 Analog Voc 4 Analog Ground 3
57. linking 0010b Shadowing 0011b Bordering 0100b RESERVED 0101b RESERVED 0110b RESERVED 0111b RESERVED 1000b Raised Box 1001b Blinking and Raised Box 1010b Depressed Box 1011b Blinking and Depressed Box 1100b Heavy Raised Box 1101b Blinking and Heavy Raised Box 1110b Heavy Depressed Box 1111b Blinking and Heavy Depressed Box FOUR COLOR ATTRIBUTE FORMAT The address range for an attribute number 0 lt lt 15 is provided in Table 25 45 www national com 9211 LM1276 Attribute Table and Enhanced Features continued ATT4C7n 0 8507 4 ATT4C6n 0 8506 4 Reserved Color 3 X X X X X X X X X X X C3B 2 1 ATT4C5n 0 8505 4 ATT4C4n 0x8504 n 4 Blue Color 3 Green Color 2 Blue Color 2 Green Color 2 Red 0880 C3Gizo ATT4C3n 0 8503 4 ATT4C2n 0 8502 4 Reserved Enhanced Features Color 1 x EFB 3 0 1 2 1 ATT4C1n 0 8501 4 ATT4COn 0x8500 n 4 Blue Color 1 Green Color 1 Red Color 0 Blue Color 0 Green Color 0 Red CORTE Bits 8 0 These nine bits determine color 0 which is displayed when the corresponding OSD pixel code is 00b Bits 17 9 These nine bits determine color 1 which is displayed when the corresponding OSD pixel code is 010 Bits 21 18 These are the enhanced feature EF bits which determine which feature is applied to the displayed charac
58. n sequence in the page RAM in bits 8 0 Special codes are used between lines to show where one line ends and the next begins and also to allow blank or skipped single scan lines to be added between character lines Table 7 shows the format of a character stored in RAM Note that even though this is a 13 bit format reading and writing characters and codes is done in 8 bit bytes TABLE 7 Page RAM Format 9 bit mode ATTRIBUTE CODE CHARACTER CODE ATT 3 0 CC 8 0 Bits 8 0 determined which of the 512 characters is to be called from the character ROM Bits 12 9 address one of the 16 attributes in the table containing the colors and enhanced features to be used for this particular character Two separate attribute tables are used one for 2 color characters and the other for 4 color characters Note there are 16 available attributes for 2 color characters and a different set of 16 available attributes for 4 color characters End Of Line Code To signify the end of a line of characters a special End Of Line EOL code is used in place of a character code This code shown in Table 8 tells the OSD generator that the character and attribute codes which follow must be placed on a new line in the displayed window Bits 8 1 are zeros bit 0 is a one The attribute that is stored in Page RAM along with this code is not used TABLE 8 End Of Line Code ATTRIBUTE CODE END OF LINE CODE ATT 3 0 o 1
59. nal is required Default If bit 1 a negative V Sync input signal is required Bit 4 This bit limits the period during which video data may be detected If the bit is set to 1 then the valid data active period is limited to the vertical blanking time as set by the vertical blanking register If a string of 80 clock pulses is received during this time it is accepted as valid If a string of 80 pulses is not received until during the active video time then this data is ignored If the bit is set to 0 default then the first 80 pulse clock string that is detected is considered to be valid even if this is during the active video time 33 www national com 92111 LM1276 Control Register Definitions Continued Bit 5 Reserved This bit should be set to zero Bit 6 Reserved This bit should be set to zero Bit 7 Setting this bit will cause a software reset All registers except this one are loaded with their default values All operations currently in progress are aborted except for I C transactions This bit automatically clears itself when the reset has been completed Vertical Blank Duration Register VBLANKDUR 0x8403 Reserved Vertical Blanking Duration RSV VB 6 0 Bits 6 0 This register determines the duration of the vertical blanking signal in scan lines When vertical blanking is enabled it is recommended that this register be set to a number greater than OxOA Bit 7 Reser
60. ned by multiplying this register value by 4 and adding 30 Due to pipeline delays the first usable start location is approximately 42 OSD pixels following the horizontal flyback time For this reason we recommend this register be programmed with a number larger than 2 otherwise improper operation may result Display Window 2 Vertical Start Address VSTRT2 0x8419 Window 2 Vertical Start Address VPOS2 7 0 Bits 7 0 This register determines the Vertical start position of Window 2 in constant height character lines not video scan lines The actual position is determined by multiplying this register value by 2 Note each character line is treated as a single auto height character pixel line so multiple scan lines may actually be displayed in order to maintain accurate position relative to the OSD character cell size See the Constant Character Height Mechanism section This register should be set so the entire OSD window is within the active video Display Window 2 Start Address W2STRTADRH 0x841B W2STRTADRL 0x841A Reserved Window 2 Start Address X X X X X X 218 0 Bits 8 0 This register determines the starting address of Display Window 2 in the Display Page RAM The power on default of 0x10 starts Window 2 at the midpoint of the Page RAM 0x8100 This location always contains the SL code for the first line of Display Window 2 Bits 15 9 These bits are reserved and should be set
61. nned Substances and Materials of Interest Specification CSP 9 111S2 and contain no Banned Substances as defined in CSP 9 111S2 Leadfree products are RoHS compliant www national com National Semiconductor National Semiconductor Americas Customer Europe Customer Support Center Support Center Fax 49 0 180 530 85 86 Email new feedback nsc com Email europe support nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 69 9508 6208 English Tel 44 0 870 24 0 2171 Fran ais Tel 33 0 1 41 91 8790 National Semiconductor Japan Customer Support Center Fax 81 3 5639 7507 Email jpn feedback nsc com Tel 81 3 5639 7560 National Semiconductor Asia Pacific Customer Support Center Email ap support nsc com
62. not require any inter facing with a microcontroller www national com 22 OSD Generator Operation SCL 512 SDA Character Attribute Bank End of Line 2 color font ROM Pc Compatible Interface Row Column 3 banks 192 Address 4 color font ROM Control 1 bank 64 Enhanced Features Registers 2 color font ROM 3 banks 192 4 color font ROM 1 bank 64 Palette DAC 3 bits per video channel Box Generator Auto Height Shadow Generator PEL Filter Character Row Address HBlank Fade In Half Tone _ Fade Out Transparency Frame Line Counter Ly V Blank p Timer Video Preamp 20096927 FIGURE 16 OSD Generator Block Diagram PAGE OPERATION engineering purposes All other ROM addresses are usable Figure 16 shows the block diagram of the OSD generator and any that are unused must be filled with at least a OSD screens are created using any of the 512 predefined duplicate character Any other addresses except for those characters stored in the mask programmed ROM The listed above should not be left blank LM1276 offers a full 9 bit character code operation which allows the entire 512 ROM character set to be displayed at DISPLAYING AN OSD IMAGE once The 9 bit character code operation enables all 512 Consecutive lines of characters make up the displayed win character addresses t
63. o be independently accessed on one dow These characters are stored in the page RAM through page the I C compatible bus Each line can contain any number of characters up to the limit of the displayable line length de OSD ROM CONFIGURATION pendent on the pixels per line register although some re The OSD ROM is equivalent to two 256 character ROMs of strictions concerning the enhanced features apply on char the type used in the LM1253A and LM1237 Each ROM can acter lines longer than 32 characters The number of be considered as a group of 3 banks 192 two color char characters across the width and height of the page can be acters followed by 1 bank 64 four color characters Physi varied under I C compatible control but the total number of cally the combined ROM is then 192x2 64x4 192x2 characters that can be stored and displayed on the screen is 64x4 limited to 512 including any End of Line and End of Screen characters The horizontal and vertical start position can also END OF LINE AND END OF SCREEN CODES be programmed through the I C compatible bus Please refer to the LM1247 datasheet for details WINDOWS BLANK CHARACTER REQUIREMENT Please refer to the LM1247 datasheet for details Five of the 512 Character ROM should be reserved as blank ROM Addresses 0 and 1 are for the use of the End Of OSB VIDEO DAC Screen and End Of Line characters as mentioned above The Gain of the OSD DAC is now programmable by a 3 Bit ROM addresse
64. ontrol the gains DAC outputs PLL horizontal and vertical blanking OSD contrast and DC offset of the video outputs Registers 0x8430 0x8437 are compatible to the LM1246 Registers Any bits marked as X are reserved and should be written to with zeros and should be ignored when the register is read Additional register detail is provided in the Control Register Definitions Section later in this document www national com 28 LM1276 Address Map continued TABLE 12 LM1276 Preamplifier Interface Registers Register Address Default D7 D6 D5 D4 D3 D2 D1 DO BGAINCTRL 0 8430 0x60 X BGAIN 6 0 GGAINCTRL 0 8431 0x60 X GGAIN 6 0 RGAINCTRL 0 8432 0x60 X RGAIN 6 0 CONTRCTRL 0x8433 0x60 CONTRAST 6 0 DAC1CTRL 0 8434 0x80 DAC1 7 0 DAC2CTRL 0 8435 0x80 DAC2 7 0 DAC3CTRL 0 8436 0x80 DAC3 7 0 DACACTRL 0x8437 0x80 DACA 7 0 DACOSDDCOFF 0x8438 0x24 DC OFFSET 2 0 GLOBALCTRL 0x8439 BI 7 6 BI EN PLLCAL PS BV AUXCTRL1 Ox843A 0x03 HB POS 4 0 RSV HBD AUXCTRL2 Ox843E 0x06 CLMP ped RSV RSV oo Ox85CO Ox7F RSV OSD 6 0 tdi Ox85C1 0x80 3 0 RSV ABLCTRLO Ox85C4 RSV ABLO 3 0 ABLCTRL1 0 85 5 RSV ABL1 3 0 ABLCTRL2 85 6 RSV ABL2 3 0 ABLCTRL3 Ox85C7 RSV 3 3 0 PEAKCNTLTXT 0 85 8 0 30 RSV TM OVRSHT 2 0 HLCONTRTXT Ox85C9 0x60 RSV HILIGHT_CONT
65. ore information After the first line each new line always starts with an SL code even if the number of skipped lines to follow is zero This means an SL code must always follow an EOL code An EOL code may follow an SL code if several transparent lines are required between sections of the window See Example 3 in the LM1247 data sheet for a case where skipped lines of zero characters are displayed resulting in one window being displayed in two segments End Of Screen Code To signify the end of the window a special End Of Screen EOS code is used in place of a End Of Line EOL code There must be at least one EOS code in the Page RAM to avoid unpredictable behavior This can be accomplished by clearing the RAM by writing a O to bit 3 of the FRMCTRL1 Register 0x8400 immediately after power up 27 www national com 9211 LM1276 LM1276 Address Map continued TABLE 10 End Of Screen Code END OF SCREEN CODE ATTRIBUTE CODE ATT 3 0 0 0 0 0 0 0 0 0 0 Bits 8 0 are all zeros Bits 12 9 will have the previously entered AC but this is not used and so these bits are don t cares OSD CONTROL REGISTERS These registers shown in Table 11 control the size position enhanced features and ROM bank selection of up to two independent OSD windows These registers are compatible to the LM1246 OSD control Registers Any bits marked as X are reserved and should be written to with zeros and should be ignored
66. possible www national com Pin Descriptions and Application Information Continued Pin No Pin Name Schematic Description 18 DAC 3 Output 19 DAC 2 Output 20 DAC 1 Output DAC outputs for cathode cut off adjustments and brightness control The DAC values are set through the I C compatible bus A resistor of at least 1kQ should be connected in series with these outputs for additional ESD protection DAC Outputs 21 Analog Ground Ground and power supply pin for the output 22 Analog Vcc gs analog portion of the LM1276 Note the 0 1 47uF recommended charge storage and high 21 frequency capacitors which should be as close to pins 21 and 22 as possible 23 Green Output 24 Red Output 25 Blue Output These are the three video output pins They are intended to drive the LM2476 and LM246X family of cathode drivers Nominally about 2V peak to peak will produce 40V peak to peak of cathode drive Video Outputs ESD Protection 26 ABL 9 The Automatic Beam Limiter input is biased to the desired beam current limit by RAg and Veg and normally keeps forward biased When the current resupplying the CRT capacitance averaged by C4g exceeds this limit then Diy begins to turn off and the voltage at pin 26 begins to drop The LM1276 then lowers the gain of the three video channels until the beam current reaches an equilibrium value 27 CLAMP This pin acc
67. r characters b 640 2 color characters or some combination in between Internal 512 character RAM May 2005 150 MHz Compatible RGB Preamplifier with Internal 512 Character OSD ROM 512 Character RAM and 4 Enhanced compatible microcontroller interface to allow versatile Page RAM access OSD Window Fade In Fade Out OSD Variable Tone Transparency 3 Bit OSD Contrast Video Data detection for Auto Centering amp Sizing 2 Bit Adjustable Burn in screen Mode with no video input 4 DAC outputs 8 bit resolution for bus controlled CRT bias and brightness Spot killer which blanks the video outputs when Vec falls below the specified threshold Suitable for use with discrete or integrated clamp with software configurable brightness mixer Programmable ABL Onset for Multi Limit Applications 4 Bit Programmable start position for internal Horizontal Blanking Horizontal blanking and OSD synchronization directly from deflection signals The blanking can be disabled if desired Vertical blanking and OSD synchronization directly from sync signals The blanking width is register programmable and can be disabled if desired Power Saving Mode with 65 power reduction Matched to LM246x LM247x drivers and LM2479 80 bias IC s Applications Ideal preamplifier IC for total Hi Brite Solution 17 and 19 bus controlled monitors with OSD Low cost systems with LM247x drivers 2005 National Sem
68. raneous signals The PLL Vcc pin should be isolated from the rest of the Vcc line by a ferrite bead and bypassed to pin 8 with an electrolytic capacitor and a high frequency ceramic 11 14 Digital Ground Digital Voc Ground pin and power supply pin for the digital portion of the LM1276 Note the recommended charge storage and high frequency capacitors which should be as close to pins 11 and 14 as possible 12 SCL Vec 2 2K 100 SCL 5 ESD Protection The compatible clock line A pull up resistor of about 2 2 kQ should be connected between this pin and Voc A resistor of at least 1000 should be connected in series with the clock line for additional ESD protection 13 15 SDA H Sync Vec 2 2K Data In ESD Protection Vec H Sync 1k id ESD Protection The C compatible data line A pull up resistor of about 2 2 kQ should be connected between this pin and Vcc A resistor of at least 1000 should be connected in series with the data line for additional ESD protection Logic level horizontal sync signal received from the MCU or sync stripper circuit This input can also be derived from the clamp input as long as it is a logic level signal 16 17 Digital Ground Digital Voc Ground pin and power supply pin for the digital portion of the LM1276 Note the recommended charge storage and high frequency capacitors which should be as close to pins 16 and 17 as
69. rather than just at 0x8000 Note that the address this points to in Page RAM must always contain the SL code for the first line of the window Bits 15 9 These bits are reserved and should be set to zero 35 www national com 9 LM1276 Control Register Definitions continued Display Window 1 Column Width COLWIDTH1B3 0x8417 COLWIDTH1B2 0x8416 Window 1 Column Width High Bytes COL1 31 16 COLWIDTH1B1 0x8415 COLWIDTH1BO 0x8414 Window 1 Column Width Low Bytes COL1 15 0 Bits 31 0 These are the Display Window 1 Column Width 2x Enable Bits These 32 bits correspond to columns 31 0 of Display Window 1 respectively A value of zero indicates the column will have normal width 12 pixels A 1 indicates the column will be twice as wide as normal 24 pixels For the double wide case each Character Font pixel location will be displayed twice in two consecutive horizontal pixel locations The user should note that if more than 32 display characters are programmed to reside on a line then all display characters after the first thirty two will have normal width 12 pixels Display Window 2 Horizontal Start Address HSTRT2 0x8418 Window 2 Horizontal Start Address HPOS2 7 0 Bits 7 0 This register determines the horizontal start position of Window 2 in OSD pixels not video signal pixels The actual position to the right of the horizontal flyback pulse is determi
70. resent in order to accurately determine the correct parameter value for the frame When no video is detected this sum of this register and the VSYNC should be with 1 line of the total number of lines per field Reading this register within less than one complete field period after the Video Detect Reset may give erroneous results This register resets to zero after the Video Detect Reset has been written HiBrite Control Register HB CONTROL 0x8590 Bits 3 0 Reserved and should be set to zero Bit 4 This bit must be low for the device to display HiBrite Software driven windows This bit must be set high for Full Screen HiBrite by the MCU Bits 4 and 5 must be both high for Full Screen HiBrite Bit 5 This bit when set high will enable the Full Screen Hi Brite feature This bit can be used by the MCU to highlight the entire screen without the use of the HiBrite software Bit 6 This bit must be set to 1 at all times for proper color bar communication 43 www national com LM1276 Auto Size Registers continued Bits 7 Interrupt Enable This bit must be set to 1 to activate the use of the interrupt bit in 0x8591 HiBrite Status Register Bits 6 0 Reserved and should be set to zero Bits 7 This bit is the interrupt bit and must be frequently polled at least 480ms interval by the MCU for a value of 1 and must be also reset by the MCU thereafter The interrupt bit will automatically be se
71. rmat Ox For ex ample the slave address for writing the registers of the Register Test Settings LM1276 is hexadecimal BA written as OxBA On the other hand binary values where the individual bit values are shown are indicated by a trailing b For example OxBA is equal to 10111010b A subset of bits within a register is referred to by the bit numbers in brackets following the Table 1 shows the definitions of the Test Settings 1 8 re ferred to in the specifications sections Each test setting is a combination of five hexadecimal register values Contrast Gain Blue Red Green and DC offset www national com LM1276 Register Test Settings Continued TABLE 1 Test Settings Control No of Bits Test Settings 4 Contrast 7 Ox7F Max G 7 Set Vo to Gain 2 Vp p DC Offset 3 0x05 www national com OSD vs Video Intensity The OSD amplitude has been increased over the LM1237 level During monitor alignment the three gain registers are used to achieve the desired front of screen color balance This also causes the OSD channels to be adjusted accord ingly since these are inserted into the video channels prior to the gain attenuators This provides the means to fine tune the intensity of the OSD relative to the video as follows If a typical starting point for the alignment is to have the gains at maximum Ox7F and the contrast at 0x55 the resultant
72. rms of video pixels 1 Flyback or sync period The duration of either the sync input or the horizontal flyback in either horizontal lines vertical or pixels horizontal 2 Back porch period The duration between the trailing edge of the sync or flyback pulse and the leading edge of the first detected video in either lines vertical or pixels horizontal 3 Front porch The duration between the trailing edge of the last detected video and the leading edge of the sync or flyback pulse in either lines vertical or pixels hori zontal The video period is the duration between the leading edge of the first detected video and the trailing edge of the last detected video in either lines vertical or OSD pixels hori zontal This period is calculated by the microcontroller with the measured periods above As the video may start and finish at different positions on the screen depending upon the image the measured horizontal porches and video time may vary from line to line To over come this the periods should be measured over at least one entire field The hardware records the shortest back porch and front porch periods used over the measured period The possible error for the above measurements are within 1 to 2 OSD pixels The video period is the duration between the leading edge of the first detected video and the trailing edge of the last detected video in either lines vertical or OSD pixels hori zontal This per
73. rogrammed with respect to the horizontal flyback zero crossing leading edge in steps of 1 OSD pixel up to a maximum of 31 steps as shown below in Figure 12 This start position of the horizontal blanking pulse is only pro grammable to occur before the horizontal flyback zero cross ing edge and cannot be programmed in the opposite direc tion The trailing edge of the horizontal blanking pulse is independent of the programmable leading edge and its relativity to the Horizontal flyback trailing edge remains un changed To use this feature both Horizontal Blanking 0 843 0 and Programmable Horizontal Blanking 0x843A 2 must be enabled The number of steps is pro grammed with the bits in 0x843A 7 3 When this feature is disabled please refer to the H Blank Time Delay On specification Zero Crossing of to 50 of output blanking end listed under the System Interface Signal Char acteristics section H Flyback at Pin 24 I H 8 to 30 ws La gt I 12 5 Up to 16 steps boo 1 Internal H Blank 4 OSD Pixels per step 20096952 FIGURE 12 Programmable Internal H Blank Video Detection for Auto Sizing amp Auto Centering The LM1276 is capable of taking measurements necessary for the monitor s microcontroller to perform the auto sizing and auto centering operations The horizontal and vertical flybacks syncs are used as the reference for timing Ei
74. s 32 63 and 511 must be reserved for test OSD contrast register for 8 levels 23 www national com LM1276 OSD Generator Operation Continued OSD VIDEO TIMING Please refer to the LM1247 datasheet for details CHARACTER CELL Please refer to the LM1247 datasheet for details FOUR COLOR FONT AS TWO 2 COLOR Please refer to the LM1247 datasheet for details ATTRIBUTE TABLES Each character has an attribute value assigned to it in the page RAM The attribute value is 4 bits wide making each character entry in the RAM 13 bits wide in total The attribute value acts as an address which points to one of 16 entries in either the two color attribute table RAM or the four color attribute table RAM The attribute word in the table contains the coding information which defines which color is represented by color 0 and color 1 in the two color attribute table and color 0 color 1 color 2 color 3 in the four color attribute table Each color is defined by a 9 bit value with 3 bits assigned to each channel of RGB A dynamic look up table defines each of the 16 different color palettes As the look up table can be dynamically coded by the microcontrol ler over the I C compatible interface each color can be assigned to any one of 2 i e 512 choices This allows a maximum of 64 different colors to be used within one page using the 4 color characters with up to 4 different colors within any one character and 3
75. s control the Center Frequency adjustment of the Hi Brite window video signal for enhancement ABL Control 0 ABLCTRLO 0x85C4 Reserved ABL Current ABLO 3 0 Bits 3 0 These bits determine the ABL current limiting threshold for ABL setting 0 Bits 7 4 Reserved and should be set to zero ABL Control 1 ABLCTRL1 0x85C5 RSV ABL1 3 0 Bits 3 0 These bits determine the ABL current limiting threshold for ABL setting 1 Bits 7 4 Reserved and should be set to zero ABL Control 2 ABLCTRL2 0x85C6 ABL Current ABL2 3 0 Reserved RSV Bits 3 0 These bits determine the ABL current limiting threshold for ABL setting 2 Bits 7 4 Reserved and should be set to zero ABL Control 3 ABLCTRL3 0x85C7 RSV ABL3 3 0 Bits 3 0 These bits determine the ABL current limiting threshold for ABL setting 3 Bits 7 4 Reserved and should be set to zero Peak Control TEXT PEAKCNTLTXT 0x85C8 Reserved RSV TEXT MODE OVERSHOOT RSV RSV OVRSHT 2 0 Bits 2 0 These bits determine the amount of overshoot for the TEXT mode Bits 7 3 Reserved and should be set to zero www national com 40 Pre Amplifier Interface Registers Continued Highlight Contrast TEXT Res d HLCONTRTXT 0x85C9 HILIGHT_CONTRAST RSV HILIGHT CONTRASTT 6 0 Bits 6 0 Bit 7 Peak Control PIC Bits 2 0 These
76. s gives 8 different levels of emphasis In the top plot the center frequency is set at its maximum level and the 8 different levels of emphasis are measured The video with no emphasis is adjusted to a 0 7 level Using maximum emphasis the video is increased to a 0 9 Vp p level at the rising edge of the video If the falling edge was measured it would show a similar waveform but going in the negative direction Center frequency is shown in the bottom plot Control of the center frequency is done with bits 4 7 in register 0x85C1 This gives 16 adjustments for this feature Every other adjustment is shown in the bottom plot since showing all 16 adjustments would have made the plot too difficult to read The curves closely approximate the peaking of an RC network Therefore the term center frequency means the RC time constant that is approximated by each curve in the above plot A true RC peaking network would give very large overshoot The LM1276 has special circuitry to clip the very large overshoot yet has the complete benefit of the RC peaking This special circuitry allows for much more over shoot than one could do with RC peaking and still not saturate the video channel Note that the video channel with the emphasis also has its own independent contrast control This allows the user to adjust his monitor for a brighter picture within the Hi Brite window and optimize the emphasis for the resolution he is using with the monitor No
77. so see Table 2 TABLE 23 OSD Pixels per Line Bits 7 5 Description Max Horizontal Frequency kHz 0 0 704 pixels per line 110 0 1 768 pixels per line 110 0 2 832 pixels per line 110 0x3 896 pixels per line 110 960 pixels per line 110 1024 pixels per line 108 1088 pixels per line 102 0x7 1152 pixels per line 96 Character Font Access Register CHARFONTACC 0x8402 RESET Resene Resered v Syne Soret Piane SRST LIMIT VSYPOL HSYPOL ATTR FONT4 Bit 0 This is the Color Bit Plane Selector This bit must be set to O to read or write a two color attribute from the range 0x0000 to Ox2FFF When reading or writing four color attributes from the range 0x3000 to 0x3FFF this bit is set to 0 for the least significant plane and to 1 for the most significant plane It is also required to set this bit to read the individual bit planes of the four color character fonts in 0x3000 to Ox8FFF and 0x7000 to Ox7FFF Bit 1 This is the Character Attribute Selector This applies to reads from the Display Page RAM address range 0x8000 0x81 FF When 0 the character code is returned and when a 1 the attribute code is returned Bit 2 This selects the V input polarity If bit 0 a positive H Sync input signal is required Default If bit 1 a negative H Sync input signal is required Bit 3 This selects the V sync input polarity If bit O a positive V Sync input sig
78. stical analysis The guaranteed specifications apply only for the test conditions listed Some performance characteristics may change when the device is not operated under the listed test conditions Note 8 The supply current specified is the quiescent current for Voc 5V Dig with ce Load resistors are not required and are not used in the test circuit therefore all the supply current is used by the pre amp Note 9 Linearity Error is the maximum variation in step height of a 16 step staircase input signal waveform with a 0 7 Vp p level at the input All 16 steps equal with each at least 100 ns in duration Note 10 dt dVcc 200 t amp sy t4 5v ts 5v 5 V where ts sv is the rise or fall time at Voc 5 5V and t4 sv is the rise or fall time at 4 5V Note 11 AAy track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages It is the difference in gain change between any two amplifiers with the contrast set to AyC 50 and measured relative to the Ay max condition For example at Ay max the three amplifiers gains might be 12 1 dB 11 9 dB and 11 8 dB and change to 2 2 dB 1 9 dB and 1 7 dB respectively for contrast set to AyC 50 This yields a typical gain change of 10 0 dB with a tracking change of 0 2 dB Note 12 The ABL input provides smooth decrease in gain over the operational range of 0 dB to 5 dB A Vagi Vase max GAIN
79. t high when the software has attempted to send a command to the MCU with the chip as the messenger It must be set back to 0 by the MCU afterwards so that it can be set high the next time the MCU software makes another attempt to send a command MCU Command Register MCU COMMAND 0x8592 MCU 7 0 Bits 7 0 Command These bits are the MCU command bits The MCU must read a value of 0x80 from this register Sub Command Register SUB COMMAND 0x8593 SUB COMMANDI7 0 Bits 7 0 Sequence Number Sub Command These bits are the sub command bits If a value of this register is 0x01 This value corresponds to a HiBrite Software UP command 0x02 This value corresponds to a HiBrite Software DOWN command 0x01 This value corresponds to a prompt for the MCU to perform a V Blank Duration Adjustment SEQ NUM 0 859 SEQ NUM 7 0 Bits 7 0 Sequence These bits are the Sequence number command bits The MCU should read this register and take note of the sequence number to compare with the current sequence number Since an MCU sub command is continuously transmitted by the software for a duration of time the interrupt bit will be set back to high again redundantly which will falsely notify the MCU of another sub command To prevent this the sequence number which is only updated on truly new commands will prevent redundant commands and have the the MCU set the interrupt but lo
80. ter The features and their corresponding codes are shown in Table 24 Bits 31 22 Reserved and should be set to zero Bits 40 32 These nine bits determine color2 which is displayed when the corresponding OSD pixel code is 10b Bits 49 41 These nine bits determine color3 which is displayed when the corresponding OSD pixel code is 11b Bits 63 50 Reserved and should be set to zero TABLE 25 Attribute Tables and Corresponding Addresses Attribute Number n Two Color Attribute Table Address Four Color Attribute Table Address 0000b 0 8440 0 8443 0 8500 0 8507 00010 0 8444 0 8447 0 8508 0 850 00100 0 8448 0 844 0 8510 0 8517 00110 01000 01010 01100 01110 0x844C 0x844F 0 8450 0 8453 0x8454 0x8457 0 8458 0 845 0x845C 0x845F 0 8518 0 851 0 8520 0 8527 0 8528 0 852 0 8530 0 8537 0x8538 0x853F 1000b 0x8460 0x8463 0 8540 0 8547 10010 0 8464 0 8467 0 8548 0 854 10106 0x8468 0x846B 0 8550 0 8557 10110 11006 11016 11106 1111B 0x846C 0x846F 0x8470 0x8473 0x8474 0x8477 0 8478 0 847 0x847C 0x847F 0x8558 0x855F 0 8560 0 8567 0x8568 0x856F 0x8570 0x8577 0 8578 0 857 BUTTON BOX FORMATION Please refer to the LM1247 datasheet for details Operation of the Shadow Feature Please refer to the LM1247 datasheet for details Operation of the Bordering Feature
81. ter code or a STOP must follow after each character code TABLE 21 Full Random Address Mode ATTRIBUTE Byte 1 1 CC 8 ATT 3 0 TABLE 22 Sequence of Transmitted Bytes s Tie Tess e z Te T T REPEAT Control Register Definitions OSD INTERFACE REGISTERS Frame Control Register 1 FRMCTRL1 0x8400 Autosize done Autosize Bit 0 On Screen Display Enable The On Screen Display will be disabled when this bit is a zero When this bit is a one the On Screen Display will be enabled This controls both Window 1 and Window 2 Bit 1 Display Window 1 Enable When this bit and Bit 0 of this register are both ones Display Window 1 is enabled If either bit is a zero then Display Window 1 will be disabled Bit 2 Display Window 2 Enable When this bit and Bit 0 of this register are both ones Display Window 2 is enabled If either bit is a zero then Display Window 2 will be disabled Bit 3 Clear Display Page RAM Writing a one to this bit will result in setting all of the Display Page RAM values to zero This bit is automatically cleared after the operation is complete This bit is initially asserted by default at power up and will clear itself back to zero shortly after Thus the default value is one only momentarily and then will remain zero until manually asserted again or until the power is cycled Bit 4 Transparent Disable When this bit is a zero a palette color of black i
82. ther the flyback or sync signals may be used In this section the flyback signals will be considered although horizontal and vertical sync can be applied similarly The resultant outputs are the flyback time the position of the start of video relative to the flyback end and the time from the end of the active video to the start of the flyback time Since the total line time is known the microcontroller can calculate the active video time The microcontroller can center the video between the start and end of flyback for best image centering and to calculate the duty cycle of the video with respect to the forward scan time thus giving a measure of the relative size of the image VIDEO INPUT DETECTION The LM1276 will detect even low level video information to determine the video image size and position The video detect logic must also find the extreme points of the dis played image during each frame with respect to the horizon tal and vertical flyback pulses as measured using the internal PLL For best performance in the auto sizing mode it is recommended that the application use the maximum pixels per line mode is used when measurements are made The durations to be measured are shown generically in Figure 13 and apply to both horizontal and vertical timings Since measurements are made in terms of OSD pixels the ratio of OSD pixels per line to the video pixels per line must be applied to the data below to attain measure ments in te
83. und color Color 0 and the character s enhanced features Button Box Blinking Heavy Box Shadowing Bordering etc For four color characters the attribute contains the code for the 9 bit Color 0 the code for the 9 bit Color 1 the code for the 9 bit Color 2 the code for the 9 bit Color 3 and the character s enhanced features Button Box Blinking Heavy Box Shadowing Bordering etc TWO COLOR ATTRIBUTE FORMAT The address range for an attribute number 0 lt lt 15 is provided in Table 25 ATT2C3n 0x8443 n 4 Reserved ATT2C2n 0x8442 n 4 Enhanced Feature Color 1 C1B 2 1 ATT2C1n 0x8441 n 4 ATT2COn 0 8440 4 Blue Color 1 Green Color 1 Red Color 0 Blue Color 0 Green Color 0 Red C2BO C1G 2 0 C1R 2 0 COB 2 0 COG 2 0 COR 2 0 Bits 8 0 These nine bits determine the background color color1 which is displayed when the corresponding OSD pixel is a 0 Bits 17 9 These nine bits determine the foreground color color2 which is displayed when the corresponding OSD pixel is a 1 Bits 21 18 These are the enhanced feature EF bits which determine which feature is applied to the displayed character The features and their corresponding codes are shown in Table 24 Bits 31 22 Reserved and should be set to zero TABLE 24 Enhanced Feature Descriptions Bits 21 18 Feature Description 0000b Normal Display 0001b B
84. ut in only one direction if desired by setting the horizontal interval to 0 for fading in out strictly in the vertical direction or setting the vertical interval to 0 for fading in out in the horizontal direction In interlaced video formats it is not recommended to fade in and fade out the OSD in the vertical direction and should be only faded in the horizontal direction The fade in out function can be enabled disabled with bit 5 of the frame control register 0x8400 and the horizontal amp vertical intervals are controlled by setting register 0x8429 The OSD window fade in out feature can only be used with OSD window 1 ENHANCED FEATURES Please refer to the LM1247 datasheet for details Microcontroller Interface The microcontroller interfaces to the LM1276 preamp using the compatible interface The protocol of the interface begins with a Start Pulse followed by a byte comprised of a 7 bit Slave Device Address and a Read Write bit Since the first byte is composed of both the address and the read write bit the address of the LM1276 for writing is OxBA 10111010b and the address for reading is OxBB 10111011b The development software provided by Na tional Semiconductor will automatically take care of the dif ference between the read and write addresses if the target address under the communications tab is set to OxBA Fig ures 17 18 show a write and read sequence on the compatible interface WRITE SEQUENCE The write
85. ved This bit should be set to zero OSD Character Height Register Bits 7 0 CHARHTCTRL 0x8404 This register determines the OSD character height as described in the section Constant Character Height Mechanism The values of this register is equal to the approximate number of OSD height compensated lines required on the screen divided by 4 This value is not exact due to the approximation used in scaling the character Example If approximately 384 OSD lines are required on the screen regardless of the number of scan lines then the Character Height Control Register is programmed with 81 0x51 Enhanced Feature Register 1 Button Box Highlight Color BBHLCTRLB1 0 8406 BBHLCTRLBO 0x8405 Reserved Highlight Green Highlight Red Highlight Blue G 2 0 R 2 0 B 2 0 Bits 8 0 These determine the button box highlight color Bits 15 9 Reserved These bits should be set to zero Enhanced Feature Register 2 BBLLCTRLB1 0x8408 BBLLCTRLBO 0x8407 Button Box Lowlight Color Reserved Lowlight Green Lowlight Red Lowlight Blue G 2 0 R 2 0 B 2 0 Bits 8 0 These determine the button box lowlight color Bits 15 9 Reserved These bits should be set to zero Enhanced Feature Register 3 Heavy Button Box Lowlight Shading Shadow CHSDWCTRLB1 0x840A CHSDWCTRLBO 0x8409 Reserved Shadow Green Shadow Red Shadow Blue X X X X X X X
86. w the monitor user can give his pictures or video a special sparkle when using the capa bilities of the LM1276 OSD PHASE LOCKED LOOP The PLL in the LM1276 serves both the OSD as well as the Hi Brite Window generation The pixels per line range for the LM1276 OSD is from 704 to 1152 pixels per line in incre ments of 64 The maximum OSD pixel frequency available is 111 MHz For example if the horizontal scan rate is 106 kHz 1024 pixels per line would be acceptable to use since the OSD pixel frequency is Horizontal Scan Rate X PPL 106kHz X 1024 108 5 MHz If 1152 pixels per line is being used the horizontal scan rate would have to be lower than 106 kHz in order to not exceed the maximum OSD pixel frequency of 111 MHz The maxi mum number of video lines that may be used is 1536 lines as in a 2048x1536 display At this line rate using a PPL setting of 4 is recommended The LM1276 has a PLL Auto feature which will automatically select an internal PLL frequency range setting that will guarantee optimal OSD locking for any horizontal scan rate and for improved jitter performance over a wider temperature range This eliminates the need for PLL register settings determined by the user as well as improved PLL performance To initialize the PLL Auto feature set bit 0 8439 4 to 1 This will effectively perform all necessary calibrations and activate the PLL Auto mode which takes approximately 2 4 vertical scan period to comp
87. w accordingly Please see the MCU Programmer s Guide Applications note on more detailed information regarding the use of registers 0x8590 0x859A Internal PLL Lock Detect Control Register STATUS 0xFFF8 LOCK LOCK RSV RSV SET ORR RSV RSV RSV RSV Bits 3 0 Reserved and should be set to zero Bits 5 4 When enabling the OSD display these 2 bits must be enabled first and then disabled when the OSD display is disabled This should also be done before performing an auto size calculation Bits 7 6 Reserved and should be set to zero H INPUT SEL 0xFFFD RSV RSV RSV RSV HSEL RSV RSV RSV www national com 44 Auto Size Registers Continued Bits 2 0 Reserved and should be set to zero Bit 3 When enabling this bit the H Flyback input is internally received from the H Sync input Bits 7 4 Reserved and should be set to zero Attribute Table and Enhanced Features Each display character and SL in the Display Page RAM will have a 4 bit Attribute Table entry associated with it The user should note that two color display characters and four color display characters use two different Attribute Tables effectively providing 16 attributes for two color display characters and 16 attributes for four color display characters For two color characters the attribute contains the code for the 9 bit foreground color Color 1 the code for the 9 bit backgro
88. w transmission The Page RAM address is automatically incremented starting with the initial LSB and MSB address in the beginning of the sequence TWO BYTE COMMUNICATION MODE The Two Byte Communication mode allows different attribute and character codes to be sent within one transmission without stopping The entire 512 character Page ROM is also fully accessible in this mode without the need to stop and restart transmission The attribute byte is shown in Table 17 and the sequence of transmitted bytes is shown in Table 18 Either another attribute amp character code pair or a STOP must follow after each character code The Page RAM address is automatically incremented just as in the Auto Attribute mode above TABLE 17 Two Byte Communication Mode ATTRIBUTE Byte Px c TABLE 18 Sequence of Transmitted Bytes Dese ame T Tom HALF RANDOM ADDRESS MODE The Half Random Address mode allows different attribute and character codes to be sent within one transmission in the same way as the Two Byte Communication mode The entire 512 character Page ROM is fully accessible in this mode without the need to stop and restart transmission The advantage of Half Random Addressing over the Two Byte mode is that the Page RAM addresses do not have to be written to in a sequential order However the Page RAM addresses cannot be entirely random as they must be within one half of the Page RAM A

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