samsung S3C72F5/P72F5 handbook
Contents
1. WARS RAGA BAER Ama PARRA S3C72F5 P72F5 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The S3C72F5 single chip CMOS microcontroller has been designed for high performance using Samsung s newest 4 bit CPU core SAM47 Samsung Arrangeable Microcontrollers With an up to 896 dot LCD direct drive capabilitv 8 bit and 16 bit timer counter and serial I O the S3C72F5 offers an excellent design solution for a wide varietv of applications which require LCD functions Up to 39 pins of the 100 pin QFP package can be dedicated to I O Eight vectored interrupts provide fast response to internal and external events In addition the S3C72F5 s advanced CMOS technology provides for low power consumption and a wide operating voltage range OTP The S3C72F5 microcontroller is also available in OTP One Time Programmable version S3P72F5 S3P72F5 microcontroller has an on chip 16K bvte one time programable EPROM instead of masked ROM The S3P72F5 is comparable to S3C72F5 both in function and in pin configuration PRODUCT OVERVIEW FEATURES SUMMARY Memory 544 x 4 bit RAM excluding LCD display RAM 16 384 x 8 bit ROM 39 VO Pins e 1 0 35 pins Input only 4 pins LCD Controller Driver 56 segments and 16 common terminals 8 And 16 common selectable Internal resistor circuit for LCD bias All dot can be switched on off 8 bit Basic Timer 4 interval timer functions Watch dog tim2. Figure 1 11 Pin Circuit Tvpe H 15 PRODUCT OVERVIEW S3C72F5 P72F5 PULL UP RESISTOR RESISTOR ENABLE COM SEG OUTPUT DISABLE DATA CIRCUIT TYPE A Figure 1 12 Pin Circuit Type H 13 PULL UP RESISTOR RESISTOR ENABLE SEG TYPE H 15 OUTPUT DISABLE DATA TYPEC GP SCHMITT TRIGGER Figure 1 13 Pin Circuit Type H 16 1 12 ELECTRONICS S3C72F5 P72F5 ELECTRICAL DATA OVERVIEW ELECTRICAL DATA In this section information on S3C72F5 electrical characteristics is presented as tables and graphics The information is arranged in the following order Standard Electrical Characteristics Absolute maximum ratings D C electrical characteristics Main system clock oscillator characteristics Subsystem clock oscillator characteristics IO capacitance A C electrical characteristics Operating voltage range Miscellaneous Timing Waveforms A C timing measurement point Clock timing measurement at Xin Clock timing measurement at XTin TCL timing Input timing for RESET Input timing for external interrupts Serial data transfer timing Stop Mode Characteristics and Timing Waveforms RAM data retention supply voltage in stop mode Stop mode release timing when initiated by RESET Stop mode release timing when initiated by an interrupt request ELECTRONICS 14 1 ELECTRICAL DATA S3C72F5 P72F5 Table 14 1
3. 14 9 ELECTRICAL DATA S3C72F5 P72F5 Table 14 8 RAM Data Retention Supply Voltage in Stop Mode Ta 40 Cto 85 C Baia retention sup votage vooor 55 v Oscillator stabilization wait tWAIT Released by RESET ms time 1 Released by interrupt 2 NOTES 1 During oscillator stabilization wait time all CPU operations must be stopped to avoid instability during oscillator start up 2 Use the basic timer mode register BMOD interval timer to delay execution of CPU instructions during the wait time 14 10 ELECTRONICS S3C72F5 P72F5 ELECTRICAL DATA TIMING WAVEFORMS INTERNAL RESET N i Ly W E STOP MODE IDLE MODE a DATA RETENTION MODE gt lt NORMAL MODE 4 EXECUTION OF STOP INSTRUCTION Figure 14 2 Stop Mode Release Timing When Initiated by RESET IDLE MODE lt SH STOP MODE gt 4 NORMAL MODE lt DATA RETENTION MODE gt A EXECUTION OF STOP INSTRUCTION POWER DOWN MODE TERMINATING SIGNAL INTERRUPT REQUEST Figure 14 3 Stop Mode Release Timing When Initiated by Interrupt Request ELECTRONICS 14 11 ELECTRICAL DATA S3C72F5 P72F5 0 8VDD 0 8Voo MEASUREMENT POINTS 0 2VDD 4 sa 0 2VDD Figure 14 4 A C Timing Measurement Points Except for Xin and XTin Figure 14 5 Clock Timing Measurement at Xin Figure 14 6 Clock Timing Measurement at XTin 14 12 ELECTRONICS S3C72F5 P72F5 ELECTRICAL DATA
4. 3 58 MHz 6 0 MHz CCR MC3 3 58 MHz 6 0 MHz mm 1 Please specify normal oscillator frequency 2 On chip 30pF built in 3 On chip C 38pF built in NOTES 14 6 ELECTRONICS S3C72F5 P72F5 ELECTRICAL DATA Table 14 5 Subsvstem Clock Oscillator Characteristics 40 C 85 C Vpp 1 8 V to 5 5 V Clock Parameter Test Condition Configuration Crystal XTin XTou Oscillation 32 768 KHz Oscillator freguency 1 T C1 T C2 s Stabilization time 2 Vpp 2 7 V to 5 5 V 10 2 SEI Eer External XTin XToutl XTin input Clock frequency 1 XTin input high and low level width txTL txTH NOTES 1 Oscillation frequency and XTin input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillating stabilization after a power on occurs Table 14 6 Input Output Capacitance TA 25 C Vpp 0 V Input CIN f 1 MHz Unmeasured pins Capacitance are returned to VSS Output COUT Capacitance VO Capacitance ELECTRONICS 14 7 ELECTRICAL DATA S3C72F5 P72F5 Table 14 7 A C Electrical Characteristics TA 40 C to 85 C Vpp 1 8 V to 5 5 V Parameter me Conditions Parameter Cycle T NG 2 7 V to 5 5 V Time note 2 0 V to 5 5 V TCLO TCL1 Input fTlo TH Voor ove BEN 2 7 V to 5 5 V Freguency Vpp 2 0 V to 5 5 V TCLO TCL1 Input trino trino Vpp 2 7 V to 5 5 V High Low Width tTIH1 t
5. NOTE Pull up resistors for all VO ports are automatically disabled if they are configured to output mode 1 6 ELECTRONICS S3C72F5 P72F5 PRODUCT OVERVIEW Table 1 2 Overview of S3C72F5 Pin Data PO 1 PO 3 SO K1 BUZ K3 PO 0 PO 2 SCK KO SI K2 VO VO P5 0 P5 3 COM12 COM15 P8 0 P8 3 SEG47 SEG44 P9 0 P9 3 SEG43 SEG40 VDD Vss 1 0 VO VO VO VO VO VO RESET EA 0 004 2 7 g8 Xin Xout XTin XTout TEST PRODUCT OVERVIEW S3C72F5 P72F5 PIN CIRCUIT DIAGRAMS PULL UP P CHANNEL RESISTOR N CHANNEL SCHMITT TRIGGER Figure 1 3 Pin Circuit Type A Figure 1 5 Pin Circuit Type B VDD l PULL UP RESISTOR P CHANNEL PULL UP P CHANNEL o RESISTOR ENABLE OUT N CHANNEL OUTPUT DISABLE SCHMITT TRIGGER Figure 1 4 Pin Circuit Type A 3 Figure 1 6 Pin Circuit Type C 1 8 ELECTRONICS S3C72F5 P72F5 PULL UP RESISTOR F lt RESISTOR ENABLE OUTPUT DISABLE CIRCUIT TYPE A Figure 1 7 Pin Circuit Type E PULL UP RESISTOR lt P CH RESISTOR ENABLE OUTPUT DISABLE SCHMITT TRIGGER Figure 1 8 Pin Circuit Type E 1 PRODUCT OVERVIEW PRODUCT OVERVIEW PULL UP RESISTOR lt RESISTOR ENABLE OUTPUT DISABLE SCHMITT TRIGGER Figure 1 9 Pin Circuit Type E 2 S3C72F5 P72F5 ELECTRONICS S3C72F5 P72F5 PRODUCT OVERVIEW COM DATA Figure 1 10 Pin Circuit Tvpe H 3 SEG DATA
6. Absolute Maximum Ratings Ta 25 C x Parameter Symbol Conditions Rating units nage Yoo ue v Input Voltage V Potsoo 03tVop 03 v ARR a I lon Output Current Low One VO pin active 30 Peak value 15 note Total for ports 0 2 9 100 100 Peak value value NOTE The values for Output Current Low lor are calculated as Peak Value x Duty Table 14 2 D C Electrical Characteristics Ta 40 C to 85 C Vpp 1 8 V to 5 5 V Input High V H1 All input pins except those 0 Voltage specified below for VIH2 VIH3 VIH2 Ports 0 1 6 P3 2 P3 3 and 0 8VDD RESET Xin Xout and XTin Input Low VILA All input pins except those Voltage specified below for V La VILa ViL2 Ports 0 1 6 P3 2 P3 3 and RESET Xin Xout and XTin VOH Vpp 4 5 V to 5 5 V Output High Voltage lon 1 mA Ports 0 2 9 Output Low Vpp 4 5 V to 5 5 V Voltage loL 15 mA Ports 0 2 9 i 14 2 ELECTRONICS S3C72F5 P72F5 ELECTRICAL DATA Table 14 2 D C Electrical Characteristics Continued TA 40 C to 85 C Vpp 1 8 V to 5 5 V Input High ILIHA VI Vpp Leakage All input pins except those Current specified below for IH2 ILIH2 Vi VDD Xin Xout XTin and RESET Input Low ILILA Vis 0 V Leakage Xin Xout and XTin Current ILIL2 V 0V Xin Xout and XTin Output High Vo VDD Leakage All output pins Current Output Low Vo 0V Le
7. Operating Voltage Range e 18V to 55V Package Type 100 pinQFP ELECTRONICS S3C72F5 P72F5 PRODUCT OVERVIEW BLOCK DIAGRAM Xin Xout XTin XTout BASIC WATCH TIMER TIMER P1 0 P1 3 INTO INT4 INPUT PORT 1 VLC1 VLC5 P2 0 CLO INTERRUPT INSTRUCTION COM0 COM7 P2 1LCDCKS VO PORT 2 CONTROL REGISTER LCD P2 2 LCDSY BLOCK DRIVER P4 0 P5 3 COM8 COM15 CONTROLLER P3 0 TCLOO A SEG0 SEG39 P327TCL0 1O PORT 8 COUNTER VO PORT 3 E P3 2 TCLO INTERNAL COUNTER P9 3 P6 0 P3 3 TCL1 INTERRUPTS SEG40 SEG55 P4 0 P4 3 4 VO PORT 4 PROGRAM SERIAL VO COM8 COM11 TAT INSTRUCTION N ka P5 O P5 3 a m O ARITHMETIC P6 0 P6 3 AND STACK SEG55 SEG52 IO PORT 6 LOGIC UNIT POINTER KS4 KS7 8 BIT TIMER P7 0 P7 3 gt SEG51 SEG48 O PORT COUNTER P0 2 SI K2 P0 3 BUZ K3 VO PORT 5 P0 0 SCK K0 COM12 COM15 ERA P0 1 SO K1 16 BIT TIMER x 6 HEL ER DATA PROGRAM P9 0 P9 3 MEMORY MEMORY lt P SEG43 SEG40 VO FORTS Figure 1 1 S3C72F5 Simplified Block Diagram PRODUCT OVERVIEW PIN ASSIGNMENTS SEG4 SEG3 SEG2 SEG1 SEGO VLC5 VLC4 VLC3 VLC2 VLC1 P0 0 SCK KO P0 1 SO K1 P0 2 SI K2 P0 3 BUZ K3 VDD VSS Xout Xin TEST XTin XTout RESET P1 0 INTO P1 1 INT1 P1 2 INT2 P1 3 INT4 P2 0 CLO P2 1 LCDCK P2 2 LCDSY P3 0 TCLOO C2 100 HI SEG5 O P3 1 TCLO1 431 P3 2 TCLO C132 Figure 1 2 P3 3 TCL1 C433 S3C72F5 100 QFP 1420C P4
8. 0 COM8 C142 P4 1 COM9 C143 P4 2 COM10 D 44 P4 3 COM11 C145 P5 0 COM12 C 46 P5 1 COM13 C147 P5 2 COM14 Cj48 P5 3 COM15 49 P6 0 SEG55 K4 C 50 81 DI SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P9 3 SEG40 P9 2 SEG41 P9 1 SEG42 P9 0 SEG43 P8 3 SEG44 P8 2 SEG45 P8 1 SEG46 P8 0 SEG47 P7 3 SEG48 P7 2 SEG49 P7 1 SEG50 P7 0 SEG51 P6 3 SEG52 K7 P6 2 SEG53 K6 P6 1 SEG54 K5 S3C72F5 100 QFP Pin Assignment Diagram S3C72F5 P72F5 S3C72F5 P72F5 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1 1 S3C72F5 Pin Descriptions PinName PinTyp Deseripion Number Share Pin VO 4 bit VO port 11 SCK KO 1 bit and 4 bit read write and test are possible SO K1 Individual pins are software configurable as input or SI K2 output Individual pins are software configurable as open drain or push pull output 4 bit pull up resistors are software assignable pull up resistors are automatically disabled for output pins 4 bit input port 1 bit and 4 bit read and test are possible 4 bit pull up resistors are assignable by software P2 0 VO Same as port 0 except that port 2 is 3 bit VO port 27 P2 1 28 LCDCK P2 2 29 LCDSY VO 4 bit VO ports 1 4 bit or 8 bit read write and test are possible P5 0 P5 3 Individual pins are software configurable as input or output 4 bit pull up resistors are software assignable pull up resistors are aut
9. ECTRONICS 14 21 S3C72F5 P72F5 ELECTRICAL DATA o es fe a O o LO N TA Figure 14 18 lo VS VoL P8 9 ELECTRONICS 14 22 S3C72F5 P72F5 MECHANICAL DATA OVERVIEW This section contains the following information about the device package Package dimensions in millimetersD Pad diagram Pad pin coordinate data table ELECTRONICS MECHANICAL DATA MECHANICAL DATA S3C72F5 P72F5 20 00 TVP 100 QFP Top View 14 00 TVP 0 65 TVP 0 30 0 1 pete til 0 e e a EE 100 QFP 1420A 25 00 0 3 19 00 0 3 2 45 MAX HE 1 20 0 2 100 QFP 1420C 23 20 0 3 17 20 0 3 3 00 MAX 0 15 401 0 80 02 NOTE Typical dimensions are in millimeters Figure 15 1 100 QFP Package Dimensions 15 2 ELECTRONICS S3C72F5 P72F5 S3P72F5 OTP S3P72F5 OTP OVERVIEW The S3P72F5 single chip CMOS microcontroller is the OTP One Time Programmable version of the S3C72F5 microcontroller It has an on chip OTP ROM instead of masked ROM The EPROM is accessed by serial data format The S3P72F5 is fullv compatible with the S3C72F5 both in function and in pin configuration Because of its simple programming requirements the S3P72F5 is ideal for use as an evaluation chip for the S3C72F5 ELECTRONICS 16 1 S3P72F5 OTP S3C72F5 P72F5 100 EI SEG5 92 DI SEG13 91 HSEG14 81 ED SEG24 SEG4 SEG3 SEG2 SEG1 SEGO VLC5 VLC4 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 VLC3 S
10. EG32 VLC2 SEG33 VLC1 SEG34 P0 0 S CK KO SEG35 P0 1 SO K1 SEG36 SDATP0 2 SI K2 SEG37 SCLK P0 3 BUZ K3 SEG38 VDD VDD S3P72F5 SEG39 VSS VSS 100 QFP 1420C P9 3 SEG40 Xout 7 P9 2 SEG41 Xin P9 1 SEG42 VPP TEST P9 0 SEG43 XTin P8 3 SEG44 XTout P8 2 SEG45 RESET RESET P8 1 SEG46 P1 0 INTO P8 0 SEG47 P1 1 INTI P7 3 SEG48 P1 2 INT2 P7 2 SEG49 P1 3 INT4 P7 1 SEG50 P2 0 CLO P7 0 SEG51 P2 1 LCDCK P6 3 SEG52 K7 P2 2 LCDSY P6 2 SEG53 K6 P3 0 TCLOO P6 1 SEG54 K5 O GO O O1 GQ P3 2 TCLO H32 P3 3 TCL1 133 P4 0 COM8 H 42 P4 1 COM9 43 P3 1 TCLO1 031 P4 2 COM10 F144 P4 3 COM11 F145 P5 0 COM12 H46 P5 1 COM13 H47 P5 2 COM14 P6 0 SEG55 K4 150 NOTE The bolds indicate an OTP pin name Figure 16 1 S3P72F5 Pin Assignments 100 QFP Package 16 2 ELECTRONICS S3C72F5 P72F5 S3P72F5 OTP Table 16 1 Descriptions of Pins Used to Read Write the EPROM Main Chip During Programming PO 2 SDAT 13 VO Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port SCLK 14 vo Serial clock pin Input only pin TEST Vpp TEST 19 Power supplv pin for EPROM cell writing indicates that OTP enters into the writing mode When 12 5 V is applied OTP is in writing mode and when 5 V is applied OTP is in reading mode Option RESET RESET 2 Chip initialization Vpp Vss Vpp Vss 15 16 Logic power supply pin VDD shou
11. Figure 14 7 TCL Timing Figure 14 8 Input Timing for RESET Signal INTO 1 2 4 KO to K7 Figure 14 9 Input Timing for External Interrupts and Quasi Interrupts ELECTRONICS 14 13 ELECTRICAL DATA S3C72F5 P72F5 OUTPUT DATA Figure 14 10 Serial Data Transfer Timing 14 14 ELECTRONICS S3C72F5 P72F5 ELECTRICAL DATA NOTES ELECTRONICS 14 15 ELECTRICAL DATA S3C72F5 P72F5 CHARACTERISTIC CURVES NOTE The characteristic values shown in the following graphs are based on actual test measurements Thev do not however represent guaranteed operating values Ta 25 C fx 4 2 MHz Figure 14 11 1001 19002 VS VDD 14 16 ELECTRONICS ELECTRICAL DATA S3C72F5 P72F5 N Z x co O E ci x X O o LO N SAL a Figure 14 12 Ipp3 IDD4 IDD5 VS VDD 14 17 ELECTRONICS ELECTRICAL DATA S3C72F5 P72F5 TA 25 C CPU CLOCK fx 4 2 5 3 0 Main Svstem Clock Frequencv MHz Figure 14 14 Ipp2 VS Main System Clock Frequency 14 18 ELECTRONICS S3C72F5 P72F5 ELECTRICAL DATA Ta 25 C Ports 0 2 3 4 5 6 7 Figure 14 15 lou VS Vou PO 2 3 4 5 6 7 ELECTRONICS 14 19 S3C72F5 P72F5 ELECTRICAL DATA o E fe a O o LO N TA Figure 14 16 lou VS Vou P8 9 ELECTRONICS 14 20 S3C72F5 P72F5 ELECTRICAL DATA Ta 25 C Ports 0 2 3 4 5 6 7 VoL V Figure 14 17 loL VS VoL PO 2 3 4 5 6 7 EL
12. TIL1 IVpp 20V to 55V JI 2 0 V to 5 5 V SCK Cycle Time iKCY CEE 2 7 V to 5 5 V Input Internal SCK source SCK High Low txH tk VDD 2 7 V to 55 V Input Width Internal SCK source ial ee 50 2 0 V to 5 5 V Vpp 2 0 V to 5 5 V Input 1600 Internal SC K source ren en at 150 SI Setup Time to tSIK 2 7 V to 5 5 V ARA SCK High Vpp 2 0 V to Wii Vpp 2 0 V to 5 5 V Output SI Hold Time to IKSI Vpp 2 7 V to 5 5 V Input SCK High VDD 2 7 V to 5 5 V Output 400 VDD 2 0 V to 5 5 V Input K Vpp 2 0 V to 5 5 V Output 500 NOTE Unless otherwise specified Instruction Cycle Time condition values assume a main system clock fx source 14 8 ELECTRONICS S3C72F5 P72F5 Output Delay for SCK to SO ELECTRICAL DATA Table 14 7 A C Electrical Characteristics Continued TA 40_C to 485 C Vpp 18 V to 5 5 V tkso Vpp 2 7 V to 5 5 V Input Vpp 2 7 V to 5 5 V Output Vpp 2 0 V to 5 5 V Input Vpp 2 0 V to 5 5 V Output Interrupt Input UNTH INTO INT1 INT2 INT4 10 High Low Width tINTL K0 K7 RESET Input Low tRSL INput 10 Width NOTE Minimum value for INTO is based on a clock of 2tcy or 128 fx as assigned by the IMODO register setting ELECTRONICS Main Oscillator Freguency Divided by 4 1 05 MHz 750 KHz 15 6 kHz SUPPLV VOLTAGE V CPU CLOCK 1 n x oscillator frequency n 4 8 or 64 Figure 14 1 Standard Operating Voltage Range
13. akage All output pins Current 3 20 3 20 3 3 Pull Up Vi 0V Vpp 5V 100 Resistor Port 0 9 200 RL2 Vi 0V Vpp 5V RESET 400 120 120 LCD Voltage Ta 25 C Dividing Resistor VDD COMi 15 HA per common pin Voltage Drop i 0 15 IVDD SEGxI 15 HA per segment pin Voltage Drop x 0 55 VLC1 Output Vict LCD clock 0 Hz Vics 0 V 0 8Vpp 0 8Vpp 0 2 Voltage VLC2 Output VLC2 0 6Vpp 0 6Vpp 0 2 Voltage VLC3 Output VLC3 0 4Vpp 0 4Vpp 0 2 Voltage VLC4 Output VLC4 0 2Vpp 0 2 0 2Vpp 0 2Vpp 0 2 Voltage w ELECTRONICS 14 3 ELECTRICAL DATA S3C72F5 P72F5 Table 14 2 D C Electrical Characteristics Concluded Ta 40 C to 85 Vpp 1 8 V to 5 5 V Parameter Parameter Symbol Conditions Conditions Supply Ibp 2 Vpp 5V 10 6 0 MHz Current Crystal oscillator 4 19 MHz C1 C2 22 oF Vpp 3 V 4 10 6 0 MHz 4 19 MHz Ipp2 2 Idle mode 6 0 MHz Vpp 5 V 10 4 19 MHz Crystal oscillator C1 C2 22 pF Vpp 3 V 10 6 0 MHz 0 5 4 19 MHz 0 44 IDD3 3 Vpp 3 V 10 15 3 32 kHz crystal oscillator 1 1 1 004 3 Idle mode Vpp 3 V 10 32 kHz crystal oscillator IDD5 ei mode LA ama 5V 4 10 mode EES 3 V 10 Stop mode SCMOD Vpp 5 V 10 0100B Stop mode Vpp 3 V 10 NOTES 1 Data includes power consumption for subsystem clock oscillation 2 When the system clock control register SCMOD is set to 1001B main syste
14. er 8 bit Timer Counter Programmable 8 bit timer External event counter Arbitrary clock frequency output External clock signal divider Serial VO interface clock generator 16 Bit Timer Counter Programmable 16 bit timer External event counter Arbitrary clock frequency output External clock signal divider 8 bit Serial VO Interface 8 bittransmit receive mode B Dit receive mode LSB first or MSB first transmission selectable Internal or external clock source Memory Mapped I O Structure Data memory bank 15 S3C72F5 P72F5 Watch Timer Time interval generation 0 5 s 3 9 ms at 32768 Hz Afrequencv outputs to BUZ pin Clock source generation for LCD Interrupts Four internal vectored interrupts Four external vectored interrupts Two quasi interrupts Bit Sequential Carrier Supports 16 bit serial data transfer in arbitrary format Power Down Modes Idle mode only CPU clock stops Stop mode main system oscillation stops Subsystem clock stop mode Oscillation Sources Crystal ceramic or RC for main system clock Crystal oscillator for subsystem clock e Main system clock frequency 0 4 6 MHz Subsystem clock frequency 32 768 kHz CPU clock divider circuit by 4 8 or 64 Instruction Execution Times 0 67 1 33 10 7 us at 6 MHz 0 95 1 91 15 3 us at 4 19 MHz 122 us at 32 768 kHz Operating Temperature e 40 C to 85 C
15. ld be tied to 5 V during programming Table 16 2 Comparison of S3P72F5 and S3C72F5 Features OTP Programming Mode Vpp 5 V Vpp TEST 12 5V A OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the Vpp TEST pin of the S3P72F5 the EPROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 16 3 below Table 16 3 Operating Mode Selection Criteria REG MEM Address A15 A0 NOTE 0 means Low level 1 means High level a ELECTRONICS 16 3 S3P72F5 OTP S3C72F5 P72F5 Table 16 4 D C Electrical Characteristics Ta 40 C to 85 C Vpp 1 8 V to 5 5 V Parameter Symbol min Typ Ma Supply 2 Vpp 5 V 10 6 0 MHz 3 9 Current Crystal oscillator 4 19 MHz 2 9 C1 C2 22 pF Vpp 3 V 10 6 0 MHz 1 4 19 MHz 1 1 IDD2 ldle mode 6 0 MHz Vpp 5 V 10 4 19 MHz 1 Crystal oscillator C1 C2 22 pF Vpp 3 V 10 6 0 MHz 0 5 4 19 MHz 0 44 32 kHz crystal oscillator Idle mode Vpp 3 V 10 32 kHz crystal oscillator IDD5 Stop mode Vpp 5 V 10 Stop mode Vpp 3 V 10 Stop mode SCMOD Vpp 5 V 10 0100B Stop mode Vpp 3 V 10 NOTES 1 Data includes power consumption for subsystem clock oscillation 2 When the system clock control register SCMOD is set to 1001B main system clock oscillation stops and the subsystem clock i
16. m clock oscillation stops and the subsystem clock is used 3 Currents in the following circuits are not included on chip pull up resistors internal LCD voltage dividing resistors output port drive currents 14 4 ELECTRONICS S3C72F5 P72F5 ELECTRICAL DATA Table 14 3 Main System Clock Oscillator Characteristics 40 C 85 C Vpp 1 8 V to 5 5 V Clock Parameter Test Condition Typ Configuration li gt Oscillator Stabilization time 2 Stabilization occurs 4 ms when Vpp is equal to the minimum oscillator voltage range Vpp 3 0 V Crystal i Oscillation frequency 1 Oscillator Stabilization time 2 voo 30v 3 0 V 10 ms wes External i Xin input frequency 1 0 4 MHz Clock Xin input high and low 83 3 1250 level width txH tXL RC Xin Xout Frequency MHz Oscillator R 39 kQ 1 Vpp 3 V NOTES 1 Oscillation frequency and Xin input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillator stabilization after a power on occurs or when stop mode is terminated ELECTRONICS 14 5 ELECTRICAL DATA S3C72F5 P72F5 Table 14 4 Recommended Oscillator Constants TA 40 C 85 C Vpp 1 8 V to 5 5 V Series Frequency Range Load Cap pF Oscillator Voltage Number 1 Range V er mm max 2 2 2 0 5 5 On chip Leaded Type 3 3 2 0 5 5 On chip SMD Type TDK FCR M 3 FOR MC5
17. omatically disabled for output pins P6 0 P6 3 VO Same as PA P5 SEG55 K4 SEG52 K7 P7 0 P7 3 SEG51 SEG48 P8 0 P8 3 Same as P4 P5 i Serial I O interface clock signal Serial data output VO 2 kHz 4 kHz 8 kHz or 16 kHz freguency output for P0 3 K3 buzzer signal External interrupts The triggering edge for INTO and 23 24 P1 0 P1 1 INTI is selectable P4 0 P4 3 P9 0 P9 3 INTO INTA P0 0 K0 P0 1 K1 Serial data input P0 2 K2 PRODUCT OVERVIEW S3C72F5 P72F5 Table 1 1 S3C72F5 Pin Descriptions Continued INT2 Quasi interrupt with detection of rising or 25 P1 2 falling edges INT4 External interrupt with detection of rising or 26 P1 3 falling edges LCDCK BECIE LCD clock output for display expansion LCDSY LCD synchronization clock output for display P2 2 expansion TO WO Timer counterO clock output Timer counter 0 clock output 0 clock output 30 PO motor vo Timeniccumtertclockoutpur a rai Tea tema sock input torimercomei aa f Pea ETS LCD segment signal output Fee External interrupt The triggering edge is 11 14 P0 0 P0 3 selectable ww amp a E ys ed CES ESQ SECC ik EE N 2 Micro tODpowersupy f06P Xin Xout Crystal Ceramic or RC oscillator pins for 18 17 system clock XTin XTout Crystal oscillator pins for subsystem clock 20 21 21 TEST un Test signal input must be connected to Vss eil
18. s used 3 Currents in the following circuits are not included on chip pull up resistors internal LCD voltage dividing resistors output port drive currents 16 4 ELECTRONICS S3C72F5 P72F5 S3P72F5 OTP Main Oscillator Frequency Divided bv 4 1 05 MHz 750 kHz 15 6 kHz 1 8V SUPPLY VOLTAGE V CPU CLOCK 1 n x oscillator frequency n 4 8 or 64 Figure 16 2 Standard Operating Voltage Range ELECTRONICS 16 5
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samsung S3C72F5/P72F5 handbook