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samsung S3C7044/C7048/P7048 handbook(1)(1)

1. DABS RAGA GAMER 3 7044 7048 7048 PRODUCT OVERVIEW ERR Sv SALIS PRODUCT OVERVIEW The S3C7044 C7048 single chip CMOS microcontroller has been designed for very high performance using Samsung s newest 4 bit CPU core SAM47 Samsung Arrangeable Microcontrollers The S3P7048 is the microcontroller which has 8K bytes one time programmable ROM and the functions are same to S3C7044 C7048 With two 8 bit timer counters an 8 bit serial I O interface and eight software n channel open drain pins the 3C7044 C7048 offers an excellent design solution for a wide variety of general purpose applications Up to 36 pins of the 42 pin SDIP or 44 pin QFP package can be dedicated to I O Seven vectored interrupts provide fast response to internal and external events In addition the S8C7044 C7048 s advanced CMOS technology provides for low power consumption and a wide operating voltage range ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES SUMMARY Memory 512 x 4 bit RAM 4096 x 8 bit ROM S3C7044 e 8192 x 8 bit ROM S3C7048 36 I O Pins e Input only 4 pins 1 0 24 pins e N channel open drain 8 pins Memory Mapped I O Structure e Data memory bank 15 8 Bit Basic Timer e 4 interval timer functions Two 8 Bit Timer Counters e Programmable interval timer e External event counter function Timer counters clock outputs to TCL
2. 009 185 870 4 Vss Vss P7 0 KS4 P7 1 KS5 P7 2 KS6 P7 3 KS7 P6 0 KSO P6 1 KS1 P6 2 KS2 P6 3 KS3 XIN XouT RESET RESET P5 0 P5 1 P4 3 TEST TEST The bolds indicate an OTP pin name Figure 15 1 S3P7048 Pin Assignments 42 SDIP Package ELECTRONICS 15 1 3 7048 15 2 P5 3 P5 2 P5 1 P5 0 RESET RESET XOUT XIN P6 3 KS3 P6 2 KS2 P6 1 KS1 P6 0 KSO m 3 m n 53 7048 38 012 1 064 4108 37 39 L3 44 QFP 1010B P7 3 KS7 4 12 P7 2 KS6 C3 13 P7 1 KS5 C4 14 P7 0 KS4 4 15 Vss Vss 1 16 P1 3 INT4 17 P1 2 INT2 4 18 19 P1 0 INTO C4 20 P2 3 BUZ 21 P2 2 CLO 4 22 The bolds indicate an OTP pin name NC P8 0 P8 1 P8 2 P8 3 0 5 P0 1 SO P0 2 SI PO S BTCO P2 0 TCLOO P2 1 TCLO1 Figure 15 2 S3P7048 Pin Assignments 44 QFP Package 53 7044 7048 7048 ELECTRONICS 53 7044 7048 7048 3 7048 Table 15 1 Descriptions of Pins Used to Read Write the EPROM Main Chip During Programming P3 1 SDAT 19 37 Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port SCLK 20 38 Serial clock pin Input only pin TEST Vpp TEST 22 40 Power supply pin for EPROM cell writing indicates that OTP enters into the
3. Vina Vie Ports 0 1 3 6 7 0 1 3 6 7 and RESET Ports 4 and 5 with pull up resistors eee Ports 4 and 5 are open drain 4 and 5 are open drain All input pins except those specified below for 4 Vi 4 Ports 0 1 3 6 7 and RESET ER 1 KRE except 1 4 and 5 Vout eee 4 5V to 5 5 V m 15 mA Ports 4 5 only 2 0 to 5 5 V Vpp 4 5 to 5 5 V All output ports except ports 4 5 Vpp 2 0 to 5 5 V L lip Vpp a input pins except those _ below for and All input pins except below and RESET 2 E Xour only 53 7044 7048 7048 ELECTRONICS 53 7044 7048 7048 53 7048 Table 15 4 D C Electrical Characteristics Continued TA 40 to 85 2 0 V to 5 5 V Symbol Conditions Output Low Vo 0 V All output pins Leakage Current LOL Pull Up Vi 0 V 5 V Resistor Ports 0 1 not P1 3 2 3 6 7 Rio Vo 2V 5 Ports 4 and 5 only 8 220 Resistor 3 V Supply 1551 mode 5 V 10 Current 1 Crystal oscillator C1 C2 22 pF 1502 mode Vpp 5 V t 10 crystal oscillator C1 C2 22 pF Stop mode Vpp 5 V 10 Stop mode Vpp 3 V 10 NOTES 1 D C electrical values for Supply Current 51 to do not include c
4. 7048 7048 PRODUCT OVERVIEW CONTROL REGISTERS Program Status Word The 8 bit program status word PSW controls ALU operation and instruction execution sequencing It is also used to restore a program s execution environment when an interrupt has been serviced Program instructions can always address the PSW regardless of the current value of data memory access enable flags Before an interrupt is processed the PSW is pushed onto the stack in data memory bank 0 When the routine is completed PSW values are restored Interrupt status flags 151 150 the enable memory bank and enable register bank flags EMB ERB and the carry C are 1 and 4 bit read write or 8 bit read only addressable Skip condition flags 5 0 5 2 can be addressed using 8 bit read instructions only Select Bank SB Register Two 4 bit location called the SB register store address values used to access specific memory and register banks the select memory bank register SMB and the select register bank register SRB SMB instructions select a data memory bank 0 1 or 15 and store the upper four bits of the 12 bit data memory address in the SMB register The SMB instruction is used to select register bank 0 1 2 or 3 and to store the address data in the SRB The instructions PUSH SB and POP SB move SMB and SRB values to and from the stack for interrupts and subroutines CLOCK CIRCUITS System oscillation circuit generates the
5. KS7 RESET Input Low tRsL Input 10 Width NOTES 1 100pF are the load resistance and load capacitance of the SO output 2 Minimum value for INTO is based on a clock of 2tcy or 128 fx as assigned by the IMODO register setting ELECTRONICS 15 7 3 7048 S3C7044 C7048 P7048 CPU CLOCK Main Osc Freq Divided by 4 1 05 kHz 15 625 kHz SUPPLY VOLTAGE V CPU CLOCK 1 n x oscillator frequency n 4 8 64 Figure 15 3 Standard Operating Voltage Range 15 8 ELECTRONICS 53 7044 7048 7048 53 7048 Verify Byte Verify 1 Byte Last Address Increment Address Compare All Byte Figure 15 4 OTP Programming Algorithm ELECTRONICS 15 9
6. S3C7404 8064 byte area for general purpose program memory S3C7408 The vector address area is used during reset operation and interrupts These 16 bytes can alternately be used as general purpose ROM The REF instruction references 2x1 byte or 2 byte instruction stored in reference area location 0020H 007FH REF can also reference three byte instruction such as JP or CALL So that a REF instruction can reference these instruction however the JP or CALL must be shortened to a 2 byte format To do this JP or CALL is written to the reference area with the format TJP or TCALL instead of the normal instruction name Unused location in the REF instruction look up area can be allocated to general purpose use ELECTRONICS 1 3 PRODUCT OVERVIEW 53 7044 7048 7048 Overview The 512 x 4bit data memory has five areas 32 4 bit working register area 224 x 4 bit general purpose area in bank 0 which is also used as the stack area 256 x 4 bit general purpose area in bank 1 128 x 4 bit area in bank 15 for memory mapped addresses The data memory area is also organized as three memory banks bank0 bank1 and bank15 You use the select memory bank instruction SMB to select one of the banks as working data memory Data stored in RAM location are 1 4 and 8 bit addressable After a hardware reset data memory initialization values must be defined by program code Data Memory a
7. a CPU clock of fx 4 LECTRONI 13 4 ELECTRONICS 53 7044 7048 7048 ELECTRICAL DATA Table 13 3 Main System Clock Oscillator Characteristics TA 40 85 1 8V to 5 5 V Clock Parameter Test Condition Typ Configuration Ceramic Xi Oscillation frequency 1 2 7 5 5 0 4 MHz Oscillator Noostevessv 42 o f Crystal Oscillation frequency 1 Vpp 2 7 V to 5 5 0 4 MHz Oscillator oa o f pu pm External X uinputirsquensi ANS Clock Xin input high and low 83 3 1250 level width txi NOTES 1 Oscillation frequency and Xy input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillating stabilization after a power on occurs or when stop mode is terminated ELECTRONICS 13 5 ELECTRICAL DATA 53 7044 7048 7048 Table 13 4 Input Output Capacitance TA 25 0 Input Capacitance f 1 MHz Unmeasured pins are returned to Vss Output Capacitance I O Capacitance Table 13 5 A C Electrical Characteristics 40 to 85 1 8 V to 5 5 V Instruction Cycle toy Vpp 2 7 V to 5 5 V 0 67 64 us Time 1 8 V to 5 5 V Frequency High Low Width SCK Cycle Time tkcy 2 7 V to 5 5 V 800 External SCK source Internal SC K source Vpp 1 8 V to 5 5 V 3200 Exter
8. as input or output 4 bit pull up resistors are software assignable pull up resistors are automatically disabled for output pins 4 bit input port 1 bit and 4 bit read and test is possible 3 bit pull up resistors are assignable by software to pins P1 0 P1 1 and 1 2 Same as port 0 4 0 4 3 4 bit I O ports N channel open drain output up to 9 volts 5 0 5 3 1 bit 4 bit read write and test is possible Ports 4 and 5 can be paired to support 8 bit data transfer 8 bit unit pull up resistors are assignable by mask option 4 bit I O ports KS0 KSS3 1 bit or 4 bit read write and test is possible Port 6 pins are individually software configurable as KS4 KS7 input or output 4 bit pull up resistors are software assignable pull up resistors are automatically disabled for output pins port 6 only Ports 6 and 7 can be paired to enable 8 bit data transfer 4 bit I O ports 1 bit and 4 bit read write and test is possible Pins are individually software configurable as input or output 4 bit pull down resistors are software assignable pull down resistors are automatically disabled for output pins NOTE Parentheses indicate pin number for 44 QFP package P6 0 P6 3 P7 0 P7 3 P8 0 P8 3 1 10 ELECTRONICS 53 7044 7048 7048 PRODUCT OVERVIEW Table 1 1 S3C7044 C7048 Pin Descriptions Continued SCK Serial I O interface clock signal Serial data input BTCO Basi
9. 4 7048 7048 OUTPUT DATA Figure 13 9 Serial Data Transfer Timing 13 12 ELECTRONICS 53 7044 7048 7048 ECHANICAL DATA MECHANICAL DATA This section contains the following information about the device package 42 SDIP 600 package dimensions in millimeters 44 QFP 1010B package dimensions in millimeters 14 00 0 2 39 10 02 ip 3 30 0 3 NOTE Dimensions are in millimeters Figure 14 1 42 SDIP 600 Package Dimensions ELECTRONICS 14 1 MECHANICAL DATA 53 7044 7048 7048 13 20 0 30 44 QFP 1010B 2 I N c 0 80 0 20 2 05 0 1 2 30 MAX NOTE Dimensions are in millimeters Figure 14 2 44 QFP 1010B Package Dimensions 14 2 ELECTRONICS 53 7044 7048 7048 53 7048 OVERVIEW 3 7048 OTP The S3P7048 single chip CMOS microcontroller is the OTP One Time Programmable version of the 53 7044 7048 microcontroller It has an on chip OTP ROM instead of masked ROM The EPROM is accessed by serial data format The S3P7048 is fully compatible with the 53C7044 C7048 both in function and in pin configuration Because of its simple programming requirements the S3P7048 is ideal for use as an evaluation chip for the 3C7044 C7048 P1 3 INT4 P1 2 INT2 P1 1 INT1 P1 0 INTO P2 3 BUZ P2 2 CLO P2 1 TCLO1 P2 0 TCLOO P0 3 BTCO P0 2 SI P0 1 SO 0 5 SDAT P3 1 TCL1 SCLK P3 0 TCLO VDD VDD
10. C stores addresses for instruction fetches during program execution Usually the PC is incremented by the number of bytes of the fetched instruction The one instruction fetch that does not increment the PC is the 1 byte REF instruction which references instruction stored in a look up table in the ROM Whenever a reset operation or an interrupt occurs bits PC12 though PCO are set to the vector address Stack pointer An 8 bit stack pointer SP stores addresses for stack operation The stack area is located in general purpose data memory bank 0 The SP is 8 bit read writeable and SP bit 0 must always be logic zero During an interrupt or a subroutine call the PC value and the PSW are written to the stack area When the service routine has completed the values referenced by the stack pointer are restored Then the next instruction is executed The stack pointer can access the stack despite data memory access enable flag status Since the reset value of the stack pointer is not defined in firmware you use program code to initialize the stack pointer to OOH This sets the first register of the stack area to data memory location OFFH PROGRAM MEMORY In its standard configuration the 4096 x 8 bit S3C7404 8192 x 8 bit 5320 7408 ROM is divided into four areas 16 byte area for vector addresses 96 byte instruction reference area 16 byte general purpose area 0010 001FH 3968 area for general purpose program memory
11. N gt SCHMITT TRIGGER SCHMITT TRIGGER Figure 1 5 Pin Circuit Type A 3 Figure 1 7 Pin Circuit Type B 4 ELECTRONICS 1 13 PRODUCT OVERVIEW 53 7044 7048 7048 VDD RESISTOR RESISTOR D gt P CHANNEL ENABLE P CHANNEL O OUT DATA CIRCUIT N CHANNEL ourpur TYPE DISABLE OUTPUT DISABLE SCHMITT TRIGGER Figure 1 8 Pin Circuit Type C Figure 1 10 Pin Circuit Type D 1 DATA CIRCUIT output PEC PULL UP DISABLE RESISTOR RESISTOR gt CIRCUIT ENABLE RESISTOR N CHANNEL DATA CIRCUIT ENABLE ourPUT 4 PULL DOWN DISABLE 515 CIRCUIT Figure 1 9 Pin Circuit Figure 1 11 Pin Circuit Type D 2 1 14 ELECTRONICS 53 7044 7048 7048 PRODUCT OVERVIEW DATA OUTPUT N CHANNEL DISABLE Figure 1 12 Pin Circuit Type E 2 ELECTRONICS 1 15 S3C7044 C7048 P7048 ELECTRICAL DATA ELECTRICAL DATA In this section information on S3C7044 C7048 electrical characteristics is presented as tables and graphics The information is arranged in the following order Standard Electrical Characteristics Absolute maximum ratings D C electrical characteristics System clock oscillator characteristics capacitance A C electrical characteristics O
12. OINTER 7 0 7 3 P3 0 TCLO lt gt KS4 KS7 PORT 7 PORT P31 TCL1 P3 2 P3 3 P8 0 P8 3 9 PORT 8 512 x 4 BIT PROGRAM MEMORY DATA 4 KBYTE 53 7404 MEMORY 8 KBYTE 5367408 Figure 1 1 53C7044 C7048 P0408 Block Diagram ELECTRONICS 1 7 PRODUCT OVERVIEW PIN ASSIGNMENTS 1 8 P1 3 INT4 P1 2 INT2 P1 1 INT1 P1 0 INTO P2 3 BUZ P2 2 CLO P2 1 TCLO1 P2 0 TCLOO P0 3 BTCO P0 2 SI P0 1 SO 0 5 P3 1 TCL1 P3 0 TCLO VDD Q 009 dlaS zv 87019 77019 Vss P7 0 KS4 P7 1 KS5 P7 2 KS6 P7 3 KS7 P6 0 KSO P6 1 KS1 P6 2 KS2 P6 3 KS3 53 7044 7048 7048 Figure 1 2 S3C7044 C7048 Pin Assignment Diagrams 42 SDIP Pakage ELECTRONICS 53 7044 7048 7048 PRODUCT OVERVIEW 8 0 8 1 8 2 53 7044 7048 2 ROR 44 QFP 1010B P0 1 SO 2 51 P2 0 TCLOO P2 1 TCLO1 P6 3 KS3 P6 2 KS2 P6 1 KS1 P6 0 KSO 1 2 3 4 5 6 7 8 9 1 1 P7 3 KS7 C3 12 P7 2 KS6 C3 13 P7 1 KS5 Cj 14 P7 0 KS4 15 P1 3 INT4 C3 17 P1 2 INT2 18 P1 1 INT1 C3 19 P1 0 INTO C 20 P2 3 BUZ 21 P2 2 CLO 22 Figure 1 3 53C7044 C7048 Pin Assignment Diagrams 44 QFP Pakage ELECTRONICS 1 9 PRODUCT OVERVIEW 53 7044 7048 7048 PIN DESCRIPTIONS Table 1 1 S3C7044 C7048 P0408 Pin Description 4 bit I O port 1 bit or 4 bit read write and test is possible Individual pins are software configurable
13. OO and TCLO1 pins Watch Timer e Time interval generation 0 5 s 3 9 ms at 4 19 MHz 4 frequency outputs to the BUZ pin 8 Bit Serial 1 Interface e 8 bit transmit receive mode e 8 bit receive mode e LSB first or MSB first transmission selectable 1 2 53 7044 7048 7048 Bit Sequential Carrier e Supports 16 bit serial data transfer in arbitrary format Interrupts e external interrupt vectors e internal interrupt vectors 2 quasi interrupts Power Down Modes e Idle Only CPU clock stops Stop System clock stops Oscillation Sources e Crystal or Ceramic for system clock e Oscillation frequency 0 4 6 0MHz CPU clock divider circuit by 4 8 or 64 Instruction Execution Times 0 95 1 91 15 3 at 4 19 MHz e 0 67 1 33 10 7 us at 6 0 MHz Operating Temperature e 40 C to 85 C Operating Voltage Range e 1 8V to 5 5 2 0V to 5 5 V OTP Package Types 42 SDIP 44 QFP ELECTRONICS 53 7044 7048 7048 PRODUCT OVERVIEW FUNCTION OVERVIEW SAM47 CPU All S3C7 series microcontrollers have the advanced SAM47 CPU core The SAM47 CPU can directly address up to 32K byte of program memory The arithmetic logic unit ALU performs 4 bit addition subtraction logical and shift and rotate operations in one instruction cycle and most 8 bit arithmetic and logical operation in two cycles CPU REGISTERS program counter A 12 bit program counter P
14. c timer clock output 2 Hz 16 Hz 64 Hz or 256 5 Hz at 4 19 9 INTO INT1 External interrupts The triggering edge for INTO and 4 3 INT1 is selectable INTO is synchronized to system 20 1 clock oio INT2 INT4 TCLOO TCLO1 CLO UZ TCLO TCL1 KS0 KS3 KS4 KS7 VDD Power supply 5 Xin Crystal ceramic RC oscillator signal for system clock For external clock input use Xin and input Xin s reverse phase to TEST C 2 NOTE Parentheses indicate pin number for 44 package ELECTRONICS 1 11 PRODUCT OVERVIEW 53 7044 7048 7048 Table 1 2 Overview of S3C7044 C7048 Pin Data Share Pins ResetValue CieutType propre i me wa gt m j 54 BUZ P3 0 P3 1 TCLO TCL1 D 1 P4 0 P4 3 NOTE E 2 P5 0 P5 3 P6 0 P6 3 KS0 KS3 Input D 1 P7 0 P7 3 KS4 KS7 RESET TEST NC Vss mw _ I NOTE When pull up resistors are provided port 4 and port 5 pins are reset to high level with no pull ups they are reset to high impedance 1 12 ELECTRONICS 53 7044 7048 7048 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD PULL UP RESISTOR SCHMITT TRIGGER P CHANNEL N CHANNEL Figure 1 4 Pin Circuit A Figure 1 6 Pin Circuit Type B VDD PULL UP RESISTOR I PULL UP RESISTOR P CHANNEL I
15. ddressing modes The enable memory bank EMB flag controls the addressing mode for data memory banks 0 1 or 15 When the EMB flag is logic zero only location 00H 7FH of bank 0 and bank 15 can be accessed When the EMB flag is set to logic one all three data memory banks can be accessed based on the current SMB value Working registers The RAM s working register area in data memory bank 0 is also divided into four register banks Each register bank has eight 4 bit registers Paired 4 bit registers are 8 bit addressable Register A can be used as a 4 bit accumulator and double register EA as an 8 bit extended accumulator double registers WX WL and HL are used as address pointers for indirect addressing To limit the possibility of data corruption due to incorrect register addressing it is advisable to use bank 0 for main programs and banks 1 2 and 3 for interrupt service routines Bit sequential carrier The bit sequential carrier BSC mapped in data memory bank 15 is a 16 bit general register that you can manipulate using 1 4 and 8 bit RAM control instructions Using the BSC register addresses and bit location can be specified sequentially using 1 bit indirect addressing instructions In this way a program can generate 16 bit data output by moving the bit location sequentially incrementing or decrementing the value of the L register You can also use direct addressing to manipulate data in the BSC 1 4 ELECTRONICS 53 7044
16. de TA 40 85 time 1 Released by interrupt 2 m NOTES 1 During oscillator stabilization wait time all CPU operations must be stopped to avoid instability during oscillator start up 2 Use the basic timer mode register BMOD interval timer to delay execution of CPU instructions during the wait time 13 8 ELECTRONICS 53 7044 7048 7048 ELECTRICAL DATA TIMING WAVEFORMS INTERNAL RESET OPERATION OPERATING DATA RETENTION MODE MODE STOP INSTRUCTION Figure 13 2 Stop Mode Release Timing When Initiated By RESET IDLE MODE STOP MODE DATA RETENTION MODE VDDDR EXECUTION OF STOP INSTRUCTION POWER DOWN MODE TERMINATING SIGNAL INTERRUPT REQUEST Figure 13 3 Stop Mode Release Timing When Initiated By Interrupt Request ELECTRONICS 13 9 ELECTRICAL DATA 53 7044 7048 7048 Timing Waveforms continued 0 8Vpp 0 8Vpp MEASUREMENT POINTS 02 4 0 2 Figure 13 4 A C Timing Measurement Points Except for Xy Vpp 0 1 V 0 1 V Figure 13 5 Clock Timing Measurement at Xy Figure 13 6 TCL Timing 13 10 ELECTRONICS 53 7044 7048 7048 ELECTRICAL DATA Figure 13 7 Input Timing for RESET Signal INTO 1 2 4 KSO to KS7 Figure 13 8 Input Timing for External Interrupts and Quasi Interrupts ELECTRONICS 13 11 ELECTRICAL DATA 53 704
17. except those specified below for Ports 0 1 3 6 7 1 3 6 7 Xin and Xot E 1 Ports except 1 4 5 Io LEN to 5 5 V 0 Vpp 4 5 V to 5 5 V All output ports except ports 4 5 Vpp 1 8 to 5 5 V L Vpp W input pins except those _ below for jy and 0 All input pins except below RESET le a Xour only ELECTRICAL DATA 13 3 ELECTRICAL DATA 53 7044 7048 7048 Table 13 2 D C Electrical Characteristics Continued TA 40 C to 85 1 8 V to 5 5 V Symbol Conditions Output High Vo All output pins Leakage Current Output Low Vo 0 V All output pins Leakage Current LOL Pull Up 0 Vpp 5V Resistor Ports 0 1 not P1 3 2 3 6 7 Rio Vo 2V 5V Ports 4 and 5 only eo N OV RESET Pull Down Port 8 Resistor 6 0 2 Crystal oscillator C1 C2 22 pF 4 19 MHz 3 V 10 6 0 MHz 4 19 MHz Run mode 5 V 10 6 0 MHz crystal oscillator C1 C22 22pF 4 19 MHz 3 V 10 6 0 MHz 4 19 MHz Stop mode 5 V 10 Stop mode 3 V 10 NOTES 1 D C electrical values for Supply Current Ipp4 to 1 do not include current drawn through internal pull up resistors 2 The supply current assumes
18. internal clock signals for the CPU and peripheral hardwares The system clock can use a crystal ceramic or RC oscillation source or an externally generated clock signal To drive 53 7044 07048 using an external clock source the external clock signal should be input to and its inverted signal to A 4 bit power control register is used to enable or disable oscillation and to select the CPU clock The internal system clock signal fx can be divided internally to produce three CPU clock frequencies fx 4 fx 8 or fx 64 INTERRUPTS Interrupt requests can be generated internally by on chip processes INTB INTTO INTT1 and INTS or externally by peripheral devices INTO INT1 and INT4 There are two quasi interrupts INT2 and INTW INT2 KSO KS7 detects rising falling edges of incoming signals and INTW detects time intervals of 0 5 seconds of 3 91 milliseconds at 4 19MHz The following components support interrupt processing Interrupt enable flags Interrupt request flags Interrupt priority registers Power down termination circuit ELECTRONICS 1 5 PRODUCT OVERVIEW 53 7044 7048 7048 POWER DOWN To reduce power consumption there are two power down modes idle and stop The IDLE instruction initiates idle mode and the STOP instruction initiates stop mode In idle mode only the CPU clock stops while peripherals and the oscillation source continue to operate normally Stop mode effects only the sys
19. mode register a clock selector and a frequency divider circuit Its functions include real time and watch time measurement and frequency outputs for buzzer sound SERIAL I O INTERFACE The serial I O interface supports the transmission or reception of 8 bit serial data with an external device The serial interface has the following functional components 8 bit mode register Clock selector circuit 8 bit buffer register 3 bit serial clock counter The serial I O circuit can be set either to transmit and receive or to receive only mode MSB first or LSB first transmission is also selectable The serial interface operates with an internal or an external clock source or using the clock signal generated by the 8 bit timer counter 0 To modify transmission frequency the appropriate bits in the serial mode register SMOD must be manipulated 1 6 ELECTRONICS S3C7044 C7048 P7048 PRODUCT OVERVIEW BLOCK DIAGRAM BASIC WATCH TIMER TIMER INTO INT1 INT2 INT4 RESET 8 BIT P0 0 sck TIMER P0 1 SO PORT COUNTER 0 INTERRUPT INSTRUCTION 0 2 1 CONTROL REGISTER P0 3 BLOCK 8 BIT TIMER SERIAL COUNTER 1 PROGRAM Vo COUNTER P1 0 INTO INTERNAL P1 1 INTERRUPTS P1 2 INT2 P4 0 P4 3 P1 3 INT4 P5 0 P5 3 gt PORTS STATUS WORD P2 0 TCLOO P2 1 TCLO1 ARITHMETIC PORT 2 P2 2 CLO AND P6 0 P6 3 STACK P2 3 BUZ Kso Ks3 l oPoRT6 LOGIC UNIT P
20. nal 5 source Internal SC K source 3800 Width External SCK source Internal SC K source tkcv 2 50 Vpp 1 8 V to 55 V 1600 External SC K source Internal SC K source tkcv 2 150 ELECTRONICS 13 6 53 7044 7048 7048 ELECTRICAL DATA Table 13 5 A C Electrical Characteristics Continued TA 40 to 85 Vpp 1 8 V to a Parameter oon SI Setup Time to tsik Vpp 2 7 V to 5 5 V SCK High External SCK source Vpp 1 8 V to 5 5 V External SCK source SI Hold Time to Vpp 2 7 V to 5 5 V SCK High External SCK source 1 8 V to 5 5 V n SCK source Internal SCK source SCK source Output Delay for tkso Vpp 2 7 V to 5 5 V SCK to SO source SCK source SCK source P 8 V to 55V ER _ 5 source SCK source SCK source Interrupt Input High Low Width RESET Input Low Input Width NOTES 1 R 1Kohm and are the load resistance and load capacitance of the SO output line 2 Minimum value for INTO is based on a clock of 2tcy or 128 fx as assigned by the IMODO register setting ELECTRONICS 13 7 ELECTRICAL DATA 53 7044 7048 7048 CPU CLOCK Main Osc Freq Divided by 4 1 05 kHz 15 625 kHz SUPPLY VOLTAGE V CPU CLOCK 1 n x oscillator frequency n 4 8 64 Figure 13 1 Standard Operating Voltage Range Table 13 6 RAM Data Retention Supply Voltage in Stop Mo
21. perating voltage range Miscellaneous Timing Waveforms A C timing measurement point Clock timing measurement at and TCL timing Input timing for RESET Input timing for external interrupts Serial data transfer timing Stop Mode Characteristics and Timing Waveforms RAM data retention supply voltage in stop mode Stop mode release timing when initiated by RESET Stop mode release timing when initiated by an interrupt request ELECTRONICS 13 1 ELECTRICAL DATA 53 7044 7048 7048 Table 13 1 Absolute Maximum Ratings TA 25 Parameter Symbol Conditions Unite y LE TTON v _ lon One I O port active mA All I O ports active lor One I O port active 30 Peak value mA All ports total 100 Peak value LX NOTE The values for output current low lo are calculated as peak value x A Duty LECTRONI 13 2 ELECTRONICS 53 7044 7048 7048 Table 13 2 D C Electrical Characteristics 40 C to 85 1 8 V to 5 5 V Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Leakage Current Input Low Leakage Current All input pins except those specified below for Vino Ving Ports 0 1 3 6 7 and RESET Ports 4 and 5 with pull up resistors assigned Ports 4 and 5 are open drain ams 15 mA Ports 4 5 only 2 ELECTRONICS All input pins
22. tem clock In stop mode system clock oscillation stops completely halting all operations except for a few basic peripheral functions RESET or an interrupt with the exception of INTO can be used to terminate either idle or stop mode RESET When a RESET signal occurs during normal operation or during power down mode the CPU enters idle mode when the reset operation is initiated When the standard oscillation stabilization interval 31 3 ms at 4 19 MHz has elapsed normal CPU operation resumes PORTS The S3C7044 C7048 has 9 I O ports Pin addresses for all ports are mapped to locations FFOH FFCH in bank 15 of the RAM There 4 input pins 24 configurable I O pins and 8 software n channel open drain pins for a total of 36 pins The contents of I O port pin latches can be read written or tested at the corresponding address using bit manipulation instructions TIMERS AND TIMER COUNTERS The timer function has four main components an 8 bit basic interval timer two 8 bit timer counters and a watch timer The 8 bit basic timer generates interrupt requests at precise intervals based on the selected CPU clock frequency The programmable 8 bit timer counters are used for external event counting generation of arbitrary clock frequencies for output and dividing external clock signals The 8 bit timer counter 0 generates a clock signal SCK for the serial I O interface The watch timer has an 8 bit watch timer
23. urrent drawn through internal pull up resistors 2 The supply current assumes a CPU clock of fx 4 ELECTRONICS 15 5 3 7048 Table 15 5 A C Electrical Characteristics TA 40 to 85 C 2 0 V to 5 5 V M Conditions Instruction Cycle Varese 2 7V to 5 5 V Time 2 0 V to 5 5 V TCLO TCL1 Input 2 7 V to 5 5 V Frequency 2 0 V to 5 5V TCLO Input trmo trio 2 7 V 5 5 V High Low Width e ae Vpp 20V to 55V Vpp 20V to 55V to 55V SCK Cycle Time tkcy oo 2 7V to 5 5 V oo SCK source SCK source 670 Vpp 2 0 V to 5 5 V 3200 EM SCK High Low Vpp 2 7 V to 5 5 V Width External 5 source SCK source _ 2 0 V to 5 5 V 1600 5 ae SCK source 15 6 53 7044 7048 7048 ELECTRONICS S3C7044 C7048 P7048 S3P7048 OTP Table 15 5 A C Electrical Characteristics Continued TA 2 40 to 85 Vpp 2 0 V to 5 5 V SI Setup Time to tsik 2 7 V to 5 5 V SCK High External SCK source Internal SCK source 2 0 V to 5 5 V SI Hold Time to Vpp 2 7 V to 55V 2 0 V to 55V Output Delay for Vpp 2 7V to 55V SCK to SO External SCK source Internal SCK source 2 0 V to 5 5 V External SCK source Internal SCK source Interrupt Input tintH tint INTO 2 High Low Width INT1 INT2 INT4 KSO
24. writing mode When 12 5 V is applied OTP is in writing mode and when 5 V is applied OTP is in reading mode Option i RESET RESET 31 5 Chip initialization Vpp Vss Vbo ss 21 42 39 16 Logic power supply pin Vpp should be tied to 5 V during programming NOTE means the 44 QFP OTP pin number Table 15 2 Comparison of S3P7048 and 53 7044 7048 Features S3P7048 3 7044 7048 8 K byte EPROM 4 K byte mask ROM S3C 7044 8 K byte mask ROM 53 7048 Operating Voltage Vpp 2 0V to 5 5 V 1 8 V to 5 5V Pin Configuration 42SDIP 44QFP 42SDIP 44QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the Vpp TEST pin of the S3P7048 the EPROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 15 3 below Table 15 3 Operating Mode Selection Criteria Vpp Address R W TEST MEM 15 0 NOTE 0 means Low 1 means High level ELECTRONICS 15 3 53 7048 Table 15 4 D C Electrical Characteristics 40 C to 85 _ 2 0 V to 5 5 V Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Leakage Current Input Low Leakage Current 15 4 KI All input pins except those specified below for eae NE

samsung S3C7044/C7048/P7048 handbook(1)(1)

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