ST L6569 L6569A HIGH VOLTAGE HALF BRIDGE DRIVER WITH OSCILLATOR Manual(1)(1)
Contents
1. RAGA Aman BAERS a L6569 YZ L6569A HIGH VOLTAGE HALF BRIDGE DRIVER WITH OSCILLATOR m HIGH VOLTAGE RAIL UP TO 600V m BCD OFF LINE TECHNOLOGY INTERNAL BOOTSTRAP DIODE STRUCTURE 15 6V ZENER CLAMP ON Vs DRIVER CURRENT CAPABILITY SINK CURRENT 270mA Minidip SOURCE CURRENT 170mA m VERY LOW START UP CURRENT 15 ORDERING NUMBERS L6569 L6569D m UNDER VOLTAGE LOCKOUT WITH L6569A L6569AD HYSTERESIS m PROGRAMMABLE OSCILLATOR FREQUENCY be programmed using external resistor and capaci m DEAD TIME 1 25us tor The internal circuitry of the device allows it to be m dV dt IMMUNITY UP TO 50V ns driven also by external logic signal m ESD PROTECTION The output drivers are designed to drive external n channel power MOSFET and IGBT The internal log ic assures a dead time typ 1 25us to avoid cross DESCRIPTION conduction of the power devices The device is high voltage half bridge driver with Two version are available 16569 and L6569A They built in oscillator The frequency of the oscillator can differ in the low voltage gate driver start up sequence BLOCK DIAGRAM BIAS REGULATOR D94IN058D June 2000 1 13 This is preliminary information on a new product now in development Details are subject to change without notice 6569 L6569A ABSOLUTE MAXIMUM RATINGS 40 to 150 Ambient Temperature Operative 40 to 125 device has an in2. us oss oo 00 Ls os ors foo fore oor oem 05 eee a 5 45 typ 1 D and F do not include mold flash or protrusions Mold flash potrusions shall not exceed 0 15mm 006inch 11 13 6569 L6569A Pu ne ma rv wc pee as Cs ss oss oe 0 204 EEE 0 304 0 008 0 012 9 75 0 313 fel fe 12 13 ky 1 6569 L6569A Information furnished is believed to be accurate and reliable However STMicroelectronics assumes responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia Brazil China Finland France
3. 20 V mains by means of a voltage doubler configuration at the bulk capacitor The ballast inductance and the operating fre quency are especially designed for a 18 W Sylvania De luxe T E type bulb The PTC for preheat at the start up and the two back to back synchronization diodes makes this application easy to implement and safe in opera tion e 6 13 Lyr 1 6569 L6569A Figure 2 Waveforms 116569 SUVP gt 1 1 1 1 1 1 1 1 1 1 l 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T 2 2 d 4 4 6V typ 4 D95IN250B Figure 3 Waveforms L6569A VOUT VBOOT gt LI 1 1 1 LI 1 1 1 LI 1 1 1 LI 1 1 1 1 1 1 1 Li T 1 1 LI 1 LI 1 1 1 T D95IN251B 7 13 6569 L6569A Figure 4 Typical Dead Time vs Temperature Dependency Dead time usec 17 D96IN378A 1 6 1 5 1 4 1 3 Temperature C Figure 5 Typical Frequency vs Temperature Dependency Frequency KHz 65 D961N379A 64 63 62 61 60 59 58 57 56 55 50 25 0 25 50 75 100 125 Temperature Figure 6 Typical and Theoretical Oscillator Frequency vs Resis
4. 569A Bootstrap Function The L6569 has an internal Bootstrap structure that enables the user to avoid the external diode needed in sim ilar devices to perform the charge of the bootstrap capacitor that in turns provide an appropriate driving to the Upper External Mosfet The operation is achieved with an unique structure patented that uses a High Voltage Lateral DMOS driven by an internal charge pump see Block Diagram and synchronized with a 50 nsec delay with the Low Side Gate driver LVG pin actually working as a synchronous rectifier The charging path for the Bootstrap capacitor is closed via the Lower External Mosfet that is driven ON i e LVG High for a time interval 12 1 1 starting from the time the Supply Voltage Vs has reached the On Voltage Vsuvp 9 V typical value After see waveform Diagram the LDMOS that charges the Bootstrap Capacitor is on with a Ron 1202 typical value In the L6569A a different start up procedure is followed see waveform Diagram The Lower External Mosfet is drive OFF until Vs has reached the Turn On Threshold VsUvPp then again the Tc time interval starts as above Being the LDMOS used to implement the bootstrap operation a bi directional switch the current flowing into the BOOT pin pin 8 can lead an undue stress to the LDMOS itself if a ZERO VOLTAGE SWITCHING opera tions is not ensured and then an high voltage is appli
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6. ed to the BOOT pin This condition can occur for example when the load is removed and an high resistive value is placed in series with the gate of the external Power Mos To help the user to secure his design a SAFE OPERATING AREA for the Bootstrap LDMOS is provided fig 7 Let s consider the steps that should be taken 1 Calculate the Turn on delay td of your Lower Power MOS ty Rig Ciss In 2 Calculate the Fall time tf of your Lower Power MOS where Hg External gate resistor Rig 500 typical equivalent output resistance of the driving buffer when sourcing current VTH Ciss and are Power MOS parameters Vs Low Voltage Supply 3 Sketch the VBOOT waveform using log log scales starting from the Drain Voltage of the Lower Power MOS remember to add the Vs your Low Voltage Supply value on the Bootstrap LDMOS SOA On fig 8 an example is given where Vs Low Voltage Supply High Voltage Supply Rail The voltage swing must fall below the curve identified by the actual operating frequency of your applica tion 5 13 6569 L6569A DEMO BOARD To allow an easy evaluation of the device a P C board dedicated to lamp ballast application has been de signed Fig 11 shows the electrical schematic of a typical ballast application while the PC and component layout is giv en in Fig12 This application has been designed to work with both the 110 20 V and the 220
7. ternal zener clamp between GND and VS typical 15 6V Therefore the circuit should not be driven by a DC low im pedance power source Note ESD immunity for pins 6 7 and 8 is guaranteed up to 900 V Human Body Model THERMAL DATA Symbol Parameter Rth jamb Thermal Resistance Junction Ambient RECOMMENDED OPERATING CONDITIONS mme Tow To wear ee ojemeem pe PIN CONNECTION D941N059 2 13 6569 L6569A PIN FUNCTION VS Supply input voltage with internal clamp typ 15 6V 2 Oscillator timing resistor pin A buffer set alternatively to Vs and GND can provide current to the external resistor RF connected between pin 2 and 3 Alternatively the signal on pin 2 can be used also to drive another IC i e another L6569 to drive a full H bridge Oscillator timing capacitor pin A capacitor connected between this pin and GND fixes together with Rp the oscillating frequency Alternatively an external logic signal can be applied to the pin to drive the IC Low side driver output The output stage can deliver 170mA source and 270mA sink typ values Upper driver floating reference High side driver output The output stage can deliver 170mA source and 270mA sink typ values Bootstrap voltage supply It is the upper driver floating supply The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named boo
8. tor Value 0961380 5 6 78910 15 20 30 40 50 Resistor Value Kohm 8 13 Figure 7 Vpoot pin SOA for different Operating Frequency Tj 125 C D96IN381 Se 4111111 IOS 20 50 100 200 500 1 000 2 000 5 000 10 000 Time ns from LVG Transition High Figure 8 Vboot pin SOA Tj 125 C D96IN416 so __ alt UM ACTUAL OPERTATING FREQUENCY f Lacs 20 50 100 200 500 1 000 2 000 5 000 10 000 Time ns from LVG Transition High Figure 9 Typical Rise and Fall Times vs Load Capacitance time nsec 3 C nF For both high and low side buffers 25 C Tamb 1 6569 L6569A Figure 10 Quiescent Current vs Supply Voltage Iq uA D96IN418 10 10 10 10 Figure 11 CFL Demoboard 110 220V Inputs C4100nF 50V BOOT STD2NB50 1 HVG b 22 1 4W 6569 id b 322 1 4 STD2NB50 1 C9 470pF 630V R7 180K 1 4W BYW100 100 02 CFL LAMP L1 2 4mH core E2006 B4 Ref also VOGH 575 0409200 2 4mH DS6INAT9B ByW100 100 SYLVANIA DELUX T E 18W C7 C8 PS8n2J 630 2A TH 9 13 6569 L6569A Figure 12 Board and Components Layout D9aROB 9 228 1013 1 6569 L6569A OUTLINE AND Pe cle jan MECHANICAL DATA CL e Per or 58 oo oro Pe pel
9. tstrap driver a patented structure This structure can replace the external bootstrap diode GND LVG OUT HVG Test Condition Leakage Current BOOT pin vs 580V GND Leakage Current OUT pin vs 562V GND IBOOTLK loUTLK SO 3 13 6569 L6569A ELECTRICAL CHARACTERISTCS continued RF Low Level Output Voltage Duty Cycle Ratio Between Dead Time Conduction Time of High Side and Low Side Drivers 5 R ON On resistance of Boostrap LDMOS VBC Boostrap Voltage before UVLO Vs 8 2 12K 1nF 7 3 4 0 1 2 0 5 120 2 3 6 1 2 lt N e o a 50 T 80 85 5 57 OSCILLATOR FREQUENCY The frequency of the internal oscillator can be programmed using external resistor and capacitor The nominal oscillator frequency can be calculated using the following equation 1 1 f OSC 2 Re Ce In2 1 2863 Rp Ce Where and are the external resistor and capacitor The device can be driven in shut down condition keeping the Cr pin close to GND but some cares have to be taken 1 When Cr is to GND the high side driver is off and the low side is on 2 The forced discharge of the oscillator capacitor must not be shorter than 1us a simple way to do this is to limit the current discharge with a resistive path imposing R Cr gt 1 see fig 1 Figure 1 fault signal 4 13 6569 L6
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