ST L6566B Multi-mode controller for SMPS Manual(1)(1)
Contents
1. MARE RAGA BREA Aman BAERS Ay L6566B Multi mode controller for SMPS Features m Selectable multi mode operation fixed frequency or quasi resonant On board 700 V high voltage start up Advanced light load management Low quiescent current 3 mA Adaptive UVLO Line feedforward for constant power capability vs mains voltage Applications Hi end AC DC adapter charger LCD TV monitor PDP digital consumer IT equipment m Pulse by pulse OCP shutdown on overload latched or autorestart m Transformer saturation detection m Programmable frequency modulation for EMI reduction Latched or autorestart OVP m Brownout protection single stage PFC 600 800 mA totem pole gate driver with active pull down during UVLO m SO16N package Figure 1 Block diagram LOW CLAMP amp DISABLE LINE VOLTAGE FEEDFORWARD erence gt vot Be internal supply REGULATOR amp ADAPTIVE UVLO Hiccup mode OCP logic BURST MODE LATOR MODE SELECTION TURN ON LOGIC OVERVOLTAGE PROTECTION LATCH IC LATCH DISABLE May 2008 Rev 2 1 51 www st com Contents L6566B Contents 1 Description surcar ee Nae REN Nau OR Du i a E 6 2 Pili2. with a temperature compensated current generator connected to its source Figure 5 High voltage start up generator internal schematic L6566B CONTROL 3 18 51 ky L6566B Application information With reference to the timing diagram of Figure 6 when power is first applied to the converter the voltage on the bulk capacitor Vin builds up and at about 80 V the HV generator is enabled to operate HV EN is pulled high so that it draws about 1 mA This current minus the device s consumption charges the bypass capacitor connected from pin Vcc 5 to ground and makes its voltage rise almost linearly Figure 6 Timing diagram normal power up and power down sequences Vin Vuvstart Vcc pin 5 Vecon Vecorr VeCrestart GD pin 4 HV_EN Vcc OK Icharge 0 85 mA Normal t le E re se Power off Power on operation OWer o As the Vcc voltage reaches the turn on threshold 14 V typ the device starts operating and the HV generator is cut off by the Vcc_OK signal asserted high The device is powered by the energy stored in the Vcc capacitor until the self supply circuit typically an auxiliary winding of the transformer and a steering diode develops a voltage high enough to sustain the operation The residual consumption of this circuit is just the one on the 15 MQ resistor 10 mW at 400 Vdc typically 50 70 times lower under the
3. with Cmop in nF and Ryon in KO will be selected by the user so to achieve the best compromise between attenuation of peak EMI emissions and clean converter operation Latched disable function The device is equipped with a comparator having the non inverting input externally available at the pin DIS 8 and with the inverting input internally referenced to 4 5 V As the voltage on the pin exceeds the internal threshold the device is immediately shut down and its consumption reduced to a low value The information is latched and it is necessary to let the voltage on the Vcc pin go below the UVLO threshold to reset the latch and restart the device To keep the latch supplied as long as the converter is connected to the input source the HV generator is activated periodically so that Vcc oscillates between the start up threshold V coy and Vecon 0 5 V Activating the HV generator in this way cuts its power dissipation approximately by three as compared to the case of continuous conduction and keeps peak silicon temperature close to the average value To let the L6566B restart it is then necessary to disconnect the converter from the input source Pulling pin 16 AC OK below the disable threshold see Section 5 12 Brownout protection on page 37 will stop the HV generator until Vcc falls below VCCrestart SO that the latch can be cleared and a quicker restart is allowed as the input source is removed This operation is shown in the timing diagr
4. 3 10 3 5 40 4 10 fsw Hz 5 12 Brownout protection Brownout protection is basically a not latched device shutdown function activated when a condition of mains undervoltage is detected There are several reasons why it may be desirable to shut down a converter during a brownout condition which occurs when the mains voltage falls below the minimum specification of normal operation Firstly a brownout condition may cause overheating of the primary power section due to an excess of RMS current Secondly spurious restarts may occur during converter power down hence causing the output voltage not to decay to zero monotonically L6566B shutdown upon brownout is accomplished by means of an internal comparator as shown in the block diagram of Figure 25 on page 38 which shows the basic usage The inverting input of the comparator available on the AC OK pin 16 is supposed to sense a voltage proportional to the RMS peak mains voltage the non inverting input is internally referenced to 0 485 V with 35 mV hysteresis If the voltage applied on the AC OK pin before the device starts operating does not exceed 0 485 V or if it falls below 0 45 V while the device is running the AC FAIL signal goes high and the device shuts down with the soft start capacitor discharged and the gate drive output low Additionally if the device has been latched off by some protection function testified by Vcc oscillating between Vecon and Vecon 0 5 V the AC OK vo
5. nF to prevent any malfunctioning of this kind The voltage on the pin is clamped upwards at about 3 15 V then if the function is not used the pin has to be connected to Vcc through a resistor 220 to 680 kQ 39 51 Application information L6566B 5 13 Note 40 51 Slope compensation The pin MODE SC 12 when not connected to VREF provides a voltage ramp during MOSFET s ON time synchronous to that of the internal oscillator sawtooth with 0 8 mA minimum current capability This ramp is intended for implementing additive slope compensation on current sense This is needed to avoid the sub harmonic oscillation that arises in all peak current mode controlled converters working at fixed frequency in continuous conduction mode with a duty cycle close to or exceeding 50 Figure 27 Slope compensation waveforms Mali al oi m G D pin 4 MODE SC pin 12 a pali The compensation will be realized by connecting a programming resistor between this pin and the current sense input pin 7 CS The CS pin has to be connected to the sense resistor with another resistor to make a summing node on the pin Since no ramp is delivered during MOSFET OFF time see Figure 27 no external component other than the programming resistor is needed to ensure a clean operation at light loads Internal oscillator t The addition of the slop
6. power capability change vs input voltage in QR flyback converters 2 5 k 0 2 System not compensated 3 1s x 8 lt a 3 system optimally compensated k Kopt 0 5 1 1 5 2 2 5 3 3 5 4 Vin Vinmin Note If the voltage on the pin exceeds 3 V switching ceases but the soft start capacitor is not discharged The schematic in Figure 17 on page 29 shows also how the function is included in the control loop With a proper selection of the external divider R1 R2 i e of the ratio k R2 R1 R2 it is possible to achieve the optimum compensation described by the lower curve in the diagram of Figure 16 The optimum value of k Kopt which minimizes the power capability variation over the input voltage range is the one that provides equal power capability at the extremes of the range The exact calculation is complex and non idealities shift the real world optimum value from the theoretical one It is therefore more practical to provide a first cut value simple to be calculated and then to fine tune experimentally Assuming that the system operates exactly at the boundary between DCM and CCM and neglecting propagation delays the following expression for Kopt can be found Equation 6 Va Vinmin Vinmax Viamin T Vomax Va Kopt 3 28 51 IST L6566B Application information Experience shows that this value is typically lower than the real one Once
7. same conditions as compared to a standard start up circuit made with external dropping resistors At converter power down the system will lose regulation as soon as the input voltage is so low that either peak current or maximum duty cycle limitation is tripped Vcc will then drop and stop IC activity as it falls below the UVLO threshold 10 V typ The Vcc OK signal is de asserted as the Vcc voltage goes below a threshold VCC est located at about 5V The HV generator can now restart However if Vin lt Vinsjan as illustrated in Figure 6 HV EN is de asserted too and the HV generator is disabled This prevents converter s restart attempts and ensures monotonic output voltage decay at power down in systems where brownout protection see the relevant section is not used The low restart threshold VCC ensures that during short circuits the restart attempts of the device will have a very low repetition rate as shown in the timing diagram of Figure 7 on page 20 and that the converter will work safely with extremely low power throughput 19 51 Application information L6566B 20 51 related logic Figure 7 Timing diagram showing short circuit behavior SS pin clamped at 5 V Vcc Short circuit occurs here pin 5 i Vecon Vecore i i i i i VCCrestart i 1 l cool xq rl pin 4 lt 0 03Trep Vcc OK i N l Icharge ti Figure 8 Zero current detection block triggering bloc
8. 0 V 0 0 1 Vosdis Hiccup mode OCP level 1 1 4 1 5 1 6 V PWM control Vcompu Upper clamp voltage lcomp 0 5 7 V VcompLo Lower clamp voltage Isource 1 mA 2 0 V VcowPsu Linear dynamics upper limit 1 Vver OV 4 8 5 5 2 V Icomp Max source current VcowP 3 3 V 320 400 480 pA Rcomp Dynamic resistance Vcomp 2 6 to 4 8 V 25 KQ 1 2 52 265 2 78 Vcomppm Burst mode threshold U MODE SC open T 3 V Hys Burst mode hysteresis 20 mV IcLampL Lower clamp capability Vcomp 2 V 3 5 1 5 mA Vcompore Disable threshold Voltage falling 1 4 V nd Level for lower UVLO off 2 61 2 75 2 89 V threshold voltage falling 3 MODE SC open 3 02 3 15 3 28 Vcomp Level for higher UVLO off d 29 30 gg threshold voltage rising 39 MODE SC open 3 41 3 55 3 69 14 51 2 L6566B Electrical characteristics Table 4 Electrical characteristics continued Symbol Parameter Test condition Min Typ Max Unit Zero current detector overvoltage protection VzcoH Upper clamp voltage lzcp 3 mA 5 4 5 7 6 V VzcDL Lower clamp voltage Izcp 3 mA 0 4 V VZCDA Arming voltage 1 positive going edge 85 100 115 mV VZCDT Triggering voltage 1 negative going edge 30 50 70 mV lzcD Internal pull up Vcomp lt VcoupsH YA Vzcp lt 2 V Vcomp VcoMPHI 130 100 70 IZcDsre Source current capability Vzcp VzcoL 3 mA lZCDsnk Sink cur
9. 566B Description Figure 2 Typical system block diagram a Rectified amp Filtered Mains Voltage TA COTON NON qM ir eh agt AO TREES 7 51 Pin settings L6566B 2 Pin settings 2 1 Connections Figure 3 Pin connection through top view 2 2 Pin description Table 1 Pin functions N Pin HVS Function High voltage start up The pin able to withstand 700 V is to be tied directly to the rectified mains voltage A 1 mA internal current source charges the capacitor connected between Vcc pin 5 and GND pin 3 until the voltage on the Vcc pin reaches the turn on threshold then it is shut down Normally the generator is re enabled when the Vcc voltage falls below 5 V to ensure a low power throughput during short circuit Otherwise when a latched protection is tripped the generator is re enabled 0 5 V below the turn on threshold to keep the latch supplied or when the IC is turned off by pin COMP 9 pulled low the generator is active just below the UVLO threshold to allow a faster restart N C Not internally connected Provision for clearance on the PCB to meet safety requirements GND Ground Current return for both the signal part of the IC and the gate drive All of the ground connections of the bias components should be tied to a track going to this pin and kept sepa
10. 66B regardless of the operating option selected makes it easier to handle such conditions the 2 V clamp on the SS pin is removed and a second internal current generator las lsg1 4 keeps on charging Css As the voltage reaches 5 V the device is disabled if it is allowed to reach 2 Vpg over 5 V the device will be latched off In the former case the resulting behavior will be identical to that under short circuit illustrated in Figure 7 on page 20 in the latter case the result will be identical to that of Figure 20 on page 33 See Section 5 9 Latched disable function on page 32 for additional details Soft start pin operation under different operating conditions and settings START UP Vcc falls below UVLO before latching off here the IC latches off here the IC shuts down NORMAL OPERATION TEMPORARY OVERLOAD NORMAL OPERATION t RESTART SHUTDOWN LATCHED AUTORESTART Note 34 51 A diode with the anode to the SS pin and the cathode connected to the VREF pin 10 is the simplest way to select either auto restart mode or latch mode behavior upon overcurrent If the overload disappears before the Css voltage reaches 5 V the Iss generator will be turned off and the voltage gradually brought back down to 2 V Refer to the Application examples and Ideas section Table 7 on page 45 for additional hints If latch mode behavior is desired also for converter s short cir
11. 9 5 1 V IREF Short circuit current Vrer 0 10 30 mA Sink capability in UVLO Vcc 6 V Isink 0 5 mA 0 2 0 5 V Voy Overvoltage threshold 5 3 5 7 V Internal oscillator Operating range 10 300 fow Oscillation frequency iii i i 3 100 199 kHz EEES Vosc _ Voltage reference 3 0 97 1 1 03 V Dia Maximum duty cycle Meo 70 75 Vcomp 5 V Brownout protection Voltage falling turn off 0 432 0 450 0 468 V Vth Threshold voltage Voltage rising turn on 0 452 0 485 0 518 V lHys Current hysteresis Vcc gt 5 V Vypp 0 3 V 12 15 18 pA Vac ok cL Clamp level Inc ok 100 pA 3 315 33 V Line voltage feedforward Iver Input bias current Wer 0103 V Vzop lt zontn ES Vzcp gt Vzcpth 0 7 1 mA VVFF Linear operation range 0to 3 V Vorr IC disable voltage 3 3 15 3 3 VvFFlatch Latch off clamp level Vzco gt Vzcbth 6 4 V Kc Control voltage gain 9 Vyrr 1 V Vcomp 4 V 0 4 V V KFF Feedforward gain 9 Vver 1 V Vcomp 4 V 0 04 VIN IST 13 51 Electrical characteristics L6566B Table 4 Electrical characteristics continued Symbol Parameter Test condition Min Typ Max Unit Current sense comparator lcs Input bias current Veg 20 1 pA ti Ep Leading edge blanking 150 250 300 ns ta H L Delay to output 100 ns Vcomp VcompHi Vver 0 V 0 92 1 1 08 Vosx Overcurrent setpoint Vcomp VcouPHi Vver 1 5 V 0 45 0 5 0 55 V Vcomp Vcowrur Vyrr 3
12. Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2008 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 51 51 2
13. MOSFET s conduction time increases gradually hence controlling the start up inrush current The time needed for the overcurrent setpoint to reach its steady state value referred to as soft start time is approximately Equation 12 Tss xi E Vosx Vver 3 Css Css i Wer Iss Issi During the ramp i e until Vss 2 V all the functions that monitor the voltage on pin COMP are disabled 33 51 Application information L6566B Figure 21 The soft start pin is also invoked whenever the control voltage COMP saturates high which reveals an open loop condition for the feedback system This condition very often occurs at start up but may be also caused by either a control loop failure or a converter overload short circuit A control loop failure results in an output overvoltage that is handled by the OVP function of the L6566B see next section In case of QR operation a short circuit causes the converter to run at a very low frequency then with very low power capability This makes the self supply system that powers the device unable to keep it operating so that the converter will work intermittently which is very safe In case of overload the system has a power capability lower than that at nominal load but the output current may be quite high and overstress the output rectifier In case of FF operation the capability is almost unchanged and both short circuit and overload conditions are more critical to handle The L65
14. SGUINGS socorrer e De CR RR E d d 8 2 1 Connections sacos ewe i P REP NORMEN AA 8 2 2 Pin description 0 000 8 3 Electrical data coimas 11 3 1 Ma xim m rating scesi dedo Rd oadine cea Ee SEE ERRORS d ERE AE 11 3 2 Thermal data 11 4 Electrical characteristics eee 12 5 Application information iii 17 5 1 High voltage start up generator 18 5 2 Zero current detection and triggering block oscillator block 21 5 3 Burst mode operation at no load or very lightload 24 54 Adaptive UVLO isses oy E ERRARE ve Pace hee WER eee SEN Eee OR RE 25 5 5 PWM control block LL 26 5 6 PWM comparator PWM latch and voltage feedforward blocks 27 5 7 Hiccup mode OCP carreras ir 30 5 8 Frequency modulation 31 5 9 Latched disable function 0 00 cee es 32 5 10 Soft start and delayed latched shutdown upon overcurrent 33 5 11 OVP BIODK ia ooo xao e ted oo o aae Ue heh es bee ed bees 35 5 12 Brownout protection one eid do d nac Hee pae eaten eee Whee 37 5 13 Slope compensation cee eee 40 5 14 Summary of L6566B power management functions 41 2 51 y L6566B Contents 6 Application examples and ideas 44 7 Package mechanical data 0000 47 8 Order codes AA m 49 9 REVISION history cirie REC CC CC Ce CR 50 r 3 51 Li
15. a resistor divider Its resistance ratio will be properly chosen see Section 5 11 OVP block on page 35 and the individual resistance values Rz4 Rz2 will be such that the current sourced and sunk by the pin be within the rated capability of the internal clamps 3 mA At converter power up when no signal is coming from the ZCD pin the oscillator starts up the system The oscillator is programmed externally by means of a resistor Ry connected from pin OSC 13 to ground With good approximation the oscillation frequency fosc will be Equation 2 2 10 fosc ME c with fosc in KHz and R7 in KO As the device is turned on the oscillator starts immediately at the end of the first oscillator cycle being zero the voltage on the ZCD pin the MOSFET will be turned on thus starting the first switching cycle right at the beginning of the second oscillator cycle At any switching cycle the MOSFET is turned off as the voltage on the current sense pin CS 7 hits an internal reference set by the line feedforward block and the transformer starts demagnetization If this completes hence a negative going edge appears on the ZCD pin after a time exceeding one oscillation period Tose 1 fosc from the previous turn on the MOSFET will be turned on again with some delay to ensure minimum voltage at turn on and the oscillator ramp will be reset If instead the negative going edge appears before Tos has elapsed it will be ignored and only th
16. am of Figure 20 on page 33 y L6566B Application information 5 10 This function is useful to implement a latched overtemperature protection very easily by biasing the pin with a divider from VREF where the upper resistor is an NTC physically located close to a heating element like the MOSFET or the transformer The DIS pin is a high impedance input thus it is prone to pick up noise which might give origin to undesired latch off of the device It is possible to bypass the pin to ground with a small film capacitor e g 1 10 nF to prevent any malfunctioning of this kind Figure 20 Operation after latched disable activation timing diagram Vcc HV generator is turned on Restart is quicker t VccoN 0 5 T Disable latch is reset here Vecore a ot I i I I I I Vecrestart mE GD pin 4 HV generator turn on is disabled here Input source is removed here ViVstart 1 I Vin AC OK pin 16 Vth N Soft start and delayed latched shutdown upon overcurrent At device start up a capacitor Cas connected between the SS pin 14 and ground is charged by an internal current generator 1554 from zero up to about 2 V where it is clamped During this ramp the overcurrent setpoint progressively rises from zero to the value imposed by the voltage on the VFF pin 15 see Section 5 6 PWM comparator PWM latch and voltage feedforward blocks on page 27
17. ax Figure 33 Package dimensions 0016020 D y L6566B Order codes 8 Order codes Table 9 Order codes Order codes Package Packaging L6566B SO16N Tube L6566BTR SO16N Tape and reel 49 51 Revision history L6566B 9 50 51 Revision history Table 10 Document revision history Date Revision Changes 20 Aug 2007 1 First release 29 May 2008 2 Updated Figure 29 on page 44 Table 2 on page 11 L6566B Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products o
18. blocks QR option active ZCD ZCD ZCD pin 11 pin 11 pin 11 pan ue TW TW LIA n pre Oscillator Oscillator i i i i i i i i i l i i i Oscillator i i i ZcD ZcD Imt mt HU ZCD i I blanking blanking ii nm m blanking Lf A time time pend irr b EA time i Arm Trigger Arm Trigger IU EE EU Arm Trigger bag ON enable ON enable l i ON enable PWM latch PWM latch i I i I PWM latch po I Set Set i i Set PWM latch PWM latch Fog e PWMlatch T E Reset Reset i e Reset l GD GD l GD pod e a full load b light load C start up 23 51 Application information L6566B 5 3 Burst mode operation at no load or very light load When the voltage at the COMP pin 9 falls 20 mV below a threshold fixed internally at a value Vcomppm depending on the selected operating mode the L6566B is disabled with the MOSFET kept in OFF state and its consumption reduced at a lower value to minimize Vcc capacitor discharge The control voltage now will increase as a result of the feedback reaction to the energy delivery stop the output voltage will be slowly decaying the threshold will be exceeded and the device will restart switching again In this way the converter will work in burst mode with a nearly constant peak current defined by the internal disable level A load decrease will then cause a frequency reduction which can go down even to few hundred hertz thus minimizing all frequenc
19. cuit make sure that the supply voltage of the device does not fall below the UVLO threshold before activating the latch Figure 21 shows soft start pin behavior under different operating conditions and with different settings latch mode or autorestart Unlike other PWM controllers provided with a soft start pin in the L6566B grounding the SS pin does not guarantee that the gate driver is disabled ky L6566B Application information 5 11 OVP block The OVP function of the L6566B monitors the voltage on the ZCD pin 11 in MOSFET s OFF time during which the voltage generated by the auxiliary winding tracks converter s output voltage If the voltage on the pin exceeds an internal 5 V reference a comparator is triggered an overvoltage condition is assumed and the device is shut down An internal current generator is activated that sources 1 mA out of the VFF pin 15 If the VFF voltage is allowed to reach 2 Vbe over 5 V the L6566B will be latched off See Section 5 9 Latched disable function on page 32 for more details on IC s behavior under these conditions If the impedance externally connected to pin 15 is so low that the 5 2 Vgg threshold cannot be reached or if some means is provided to prevent that the device will be able to restart after the Vcc has dropped below 5 V Refer to the Application examples and Ideas section Table 7 on page 45 for additional hints Figure 22 OVP function internal block diagram to t
20. d as long as the device is supplied While it is disabled however no energy is coming from the self supply circuit hence the voltage on the Vcc capacitor will decay and cross the UVLO threshold after some time which clears the latch The internal start up generator is still off then the Vcc voltage still needs to go below its restart voltage before the Vcc capacitor is charged again and the device restarted Ultimately this will result in a low frequency intermittent operation Hiccup mode operation with very low stress on the power circuit This special condition is illustrated in the timing diagram of Figure 18 on page 30 Frequency modulation To alleviate converter s EMI emissions and reduce cost and size of the line filter it is advantageous to modulate its switching frequency so that the resulting spread spectrum action distributes the energy of each harmonic of the switching frequency over a number of side band harmonics Their overall energy will be unchanged but the individual amplitudes will be smaller This is what naturally occurs with QR operation due to the twice mains frequency ripple appearing on the input bulk capacitor which translates into different DCM CCM boundary frequencies The L6566B is provided with a dedicated pin FMOD 6 to perform this function if FF mode is selected Figure 19 Frequency modulation circuit L6566B With reference to Figure 19 the capacitor Cyop is connec
21. driver VapH Output high voltage lGDsource 5 mA Vcc 12 V 9 8 11 V VapL Output low voltage lapsink 100 mA 0 75 V Isourcepk Output source peak current 0 6 A leinkpk Output sink peak current 0 8 A t Fall time 40 ns tr Rise time 50 ns VGDclamp Output clamp voltage lapsource 5 mA Vcc 20 V 10 11 3 15 V UVLO saturation Vcc 0 to Vccon Isink 1 mA 0 9 1 1 1 Parameters tracking one another 2 See Table 6 on page 41 and Table 7 on page 42 3 The voltage feedforward block output is given by Vos KC Vcomp 2 5 Kee VveF 16 51 ky L6566B Application information 5 Application information The L6566B is a versatile peak current mode PWM controller specific for offline flyback converters The device allows either fixed frequency FF or quasi resonant QR operation selectable with the pin MODE SC 12 forcing the voltage on the pin over 3 V e g by tying it to the 5 V reference externally available at pin VREF 10 will activate QR operation otherwise the device will be FF operated Irrespective of the operating option selected by pin 12 the device is able to work in different modes depending on the converter s load conditions If QR operation is selected see Figure 4 1 QR mode at heavy load Quasi resonant operation lies in synchronizing MOSFET s turn on to the transformer s demagnetization by detecting the resulting negative going edge of the voltage across any winding of the transformer Then the s
22. e and the unit to restart Optionally a restart can be forced by pulling the voltage of pin 16 AC OK below 0 45 V 43 51 Application examples and ideas L6566B 6 Application examples and ideas Figure 28 Typical low cost application schematic NTC1 Vin 8810 264 Vac o R3 470k C7 2 2nF Y1 A IC1 L6566B lt q Optional for Optional for QR operation QR operation NTC1 Vin 88 to cx T ow 264 Vac T mMm T o Lx cY1 D2 1N4148 R14 R13 2 44 51 L6566B Application examples and ideas Figure 30 Typical full feature application schematic FF operation Fi NTC1 fuse Vin cvi n Ur 88100 cx c E t P T Lx all E e Ri j C2 Il I D4 m 1i Vout D1 H nce H Il C8A B R15 H R4 Mind Ict me E me L6566B Ea R17 ve R18 J T Table 7 External circuits that determine IC behavior upon OVP and OCP OVP latched OVP auto restart i i Ru OCP latched Ru a 9341340 R Diode needed if lt gt 1 26 4 E 14 Buc Ria i 1N4148 RH OCP auto restart Ru Ri 3 3 841 310 R Diode needed if satis 3 64 14 UL Rio 45 51 a A
23. e compensation ramp will reduce the available dynamics of the current signal thereby the value of the sense resistor must be determined taking this into account Note also that the burst mode threshold in terms of power will be slightly changed If slope compensation is not required with FF operation the pin shall be left floating L6566B Application information 5 14 Summary of L6566B power management functions It has been seen that the device is provided with a number of power management functions multiple operating mode upon loading conditions and protection functions To help the designer familiarize with these functions in the following tables all of theme are summarized with their respective activation mechanism and the resulting status of the most important pins This can be useful not only for a correct use of the IC but also for diagnostic purposes especially at prototyping debugging stage it is quite common to bump into unwanted activation of some function and these tables can be used as a sort of quick troubleshooting guide Table 5 L6566B light load management features IC Vi tart C VREF VCOMP OSC Feature Description Caused g dici ee ss FMOD by behavior V Iqdis mA V V V Controlled ON OFF Burst operation for VcoMP Pulse VCcoMPBM d low power Vcompsm skipping N A 1 34 mA 5 unchanged ysto 0 1 0 moge consumptio Hys operation VCOMPBM n at light
24. e first negative going edge after Tos will turn on the MOSFET and synchronize the oscillator In this way one or more drain ringing cycles will be skipped valley skipping mode Figure 9 and the switching frequency will be prevented from exceeding fosc 21 51 Application information L6566B Figure 9 Drain ringing cycle skipping as the load is gradually reduced Vos Vos Vos Pin Pin limit condition Pin Pin lt Pin Pin Pin lt Pin Note 22 51 When the system operates in valley skipping mode uneven switching cycles may be observed under some line load conditions due to the fact that the OFF time of the MOSFET is allowed to change with discrete steps of one ringing cycle while the OFF time needed for cycle by cycle energy balance may fall in between Thus one or more longer switching cycles will be compensated by one or more shorter cycles and vice versa However this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is smaller than the arming threshold for some reason e g a heavy damping of drain oscillations like in some single stage PFC topologies or when a turn off snubber is used MOSFET s turn on cannot be triggered This case is identical to what happens at start up at the end of the next oscillato
25. ever no energy is coming from the self supply circuit thus the voltage on the Vcc capacitor will decay and cross the UVLO threshold after some time which clears the latch and lets the HV generator restart This function is intended for an externally controlled burst mode operation at light load with a reduced output voltage a technique typically used in multi output SMPS such as those for TVs or monitors see the timing diagram Figure 15 on page 27 L6566B Application information 5 6 Figure 15 Externally controlled burst mode operation by driving pin COMP timing diagram Vcc Standby is commanded here pin 5 Vecon VccorF VCCrestart COMP pin 9 GD pin 4 Vcc OK Icharge i E n n m n UO d d Vout PWM comparator PWM latch and voltage feedforward blocks The PWM comparator senses the voltage across the current sense resistor Rs and by comparing it to the programming signal delivered by the feedforward block determines the exact time when the external MOSFET is to be switched off Its output resets the PWM latch previously set by the oscillator or the ZCD triggering block which will assert the gate driver output low The use of PWM latch avoids spurious switching of the MOSFET that might result from the noise generated double pulse suppression Cycle by cycle current limitation is realized with a second comparator OCP comparator that senses the voltage ac
26. g block oscillator block and related logic 20 Drain ringing cycle skipping as the load is gradually reduced 22 Operation of ZCD triggering and oscillator blocks QR option active 23 Load dependent operating modes timing diagrams eee ee eee 24 Addition of an offset to the current sense lowers the burst mode operation threshold 25 Adaptive UVLO block LL 25 Possible feedback configurations that can be used with the L6566B 26 Externally controlled burst mode operation by driving pin COMP timing diagram 27 Typical power capability change vs input voltage in QR flyback converters 28 Left Overcurrent setpoint vs VFF voltage right Line Feedforward function block 29 Hiccup mode OCP timing diagram 30 Frequency modulation circuit llle 31 Operation after latched disable activation timing diagram 33 Soft start pin operation under different operating conditions and settings 34 OVP Function internal block diagram 35 OVP function timing diagram 36 Maximum allowed duty cycle vs switching frequency for correct OVP detection 37 Brownout protection internal block diagram and timing diagraM 38 Voltage sensing techniques to implement brownout protection with the L6566B 39 Slope compensation waveforms 00 cece nes 40 Typical low cost application schematic liliis 44 T
27. grounded directly or through a resistor see Section 5 11 OVP block on page 35 The overcurrent setpoint will be then fixed at the maximum value of 1V If a lower setpoint is desired to reduce the power dissipation on Rs the pin can be also biased at a fixed voltage using a divider from VREF pin 10 If the FF option is selected the line feedforward function can be still used to compensate for the total propagation delay Td of the current sense chain internal propagation delay tdi plus the turn off delay of the external MOSFET which in standard current mode PWM controllers is done by adding an offset on the current sense pin proportional to the input voltage In that case the divider ratio k which will be much smaller as compared to that used with the QR option selected can be calculated with the following equation 29 51 Application information L6566B 5 7 30 51 Equation 8 Td opt 3 RsLp where Lp is the inductance of the primary winding In case a constant maximum power capability vs the input voltage is not required the VFF pin can be grounded directly or through a resistor see Section 5 11 OVP block on page 35 hence fixing the overcurrent setpoint at 1 V or biased at a fixed voltage through a divider from VREF to get a lower setpoint It is possible to bypass the pin to ground with a small film capacitor e g 1 10 nF to ensure a clean operation of the IC even in a noisy environment The pin
28. ight load as the QR operating frequency equals the oscillator frequency a function valley skipping is activated to prevent further frequency rise and keep the operation as close to ZVS as possible With either FF or QR operation at very light load the ICs enter a controlled burst mode operation that along with the built in non dissipative high voltage start up circuit and the low quiescent current helps keep low the consumption from the mains and meet energy saving recommendations An innovative adaptive UVLO helps minimize the issues related to the fluctuations of the self supply voltage due to transformer s parasites The protection functions included in this device are not latched input undervoltage brownout output OVP auto restart or latch mode selectable a first level OCP with delayed shutdown to protect the system during overload or short circuit conditions auto restart or latch mode selectable and a second level OCP that is invoked when the transformer saturates or the secondary diode fails short A latched disable input allows easy implementation of OTP with an external NTC while an internal thermal shutdown prevents IC overheating Programmable soft start leading edge blanking on the current sense input for greater noise immunity slope compensation in FF mode only and a shutdown function for externally controlled burst mode operation or remote ON OFF control complete the equipment of this device 6 51 77 L6
29. is internally forced to ground during UVLO after activating any latched protection and when pin COMP is pulled below its low clamp voltage see Section 5 5 PWM control block on page 26 Hiccup mode OCP A third comparator senses the voltage on the current sense input and shuts down the device if the voltage on the pin exceeds 1 5 V a level well above that of the maximum overcurrent setpoint 1 V Such an anomalous condition is typically generated by either a short circuit of the secondary rectifier or a shorted secondary winding or a hard saturated flyback transformer Figure 18 Hiccup mode OCP timing diagram Vcc Secondary diode is shorted here pns a i VCCON VccorF VeCrestart Vcs pin 7 GD pin 4 OCP latch Vcc OK To distinguish an actual malfunction from a disturbance e g induced during ESD tests the first time the comparator is tripped the protection circuit enters a warning state If in the next switching cycle the comparator is not tripped a temporary disturbance is assumed and the protection logic will be reset in its idle state if the comparator will be tripped again a real malfunction is assumed and the L6566B will be stopped Depending on the time relationship ky L6566B Application information 5 8 between the detected event and the oscillator occasionally the device could stop after the third detection This condition is latche
30. istor s collector the emitter is grounded to GND to modulate the duty cycle Figure 14 left hand side circuit In applications where a tight output regulation is not required it is possible to use a primary sensing feedback technique In this approach the voltage generated by the self supply winding is sensed and regulated This solution shown in Figure 14 right hand side circuit is cheaper because no optocoupler or secondary reference is needed but output voltage regulation especially as a result of load changes is quite poor Figure 14 Possible feedback configurations that can be used with the L6566B L6566B Secondary feedback Primary feedback Ideally the voltage generated by the self supply winding and the output voltage should be related by the Naux Ns turn ratio only Actually numerous non idealities mainly transformer s parasites cause the actual ratio to deviate from the ideal one Line regulation is quite good in the range of 2 whereas load regulation is about 5 and output voltage tolerance is in the range of 10 The dynamics of the pin is in the 2 5 to 5 V range The voltage at the pin is clamped downwards at about 2 V If the clamp is externally overridden and the voltage on the pin is pulled below 1 4 V the L6566B will shut down This condition is latched as long as the device is supplied While the device is disabled how
31. k oscillator block and L6566B Rzi a BLANKING TIME blanking START TURN ON LOGIC 50 mV Strobe e MONO JL STABLE 100 mV Reset OSCILLATOR uL Counter AUXILIARY OSCILLATOR 2 L6566B Application information 5 2 Zero current detection and triggering block oscillator block The zero current detection ZCD and triggering blocks switch on the external MOSFET if a negative going edge falling below 50 mV is applied to the input pin 11 ZCD To do so the triggering block must be previously armed by a positive going edge exceeding 100 mV This feature is typically used to detect transformer demagnetization for QR operation where the signal for the ZCD input is obtained from the transformer s auxiliary winding used also to supply the L6566B The triggering block is blanked for Tg ank 2 5 us after MOSFET s turn off to prevent any negative going edge that follows leakage inductance demagnetization from triggering the ZCD circuit erroneously The voltage at the pin is both top and bottom limited by a double clamp as illustrated in the internal diagram of the ZCD block of Figure 8 on page 20 The upper clamp is typically located at 5 7 V while the lower clamp is located at 0 4 V The interface between the pin and the auxiliary winding will be
32. load ky 41 51 Application information L6566B Table 6 L6566B protections Vcc A IC IC Iq VREF VCOMP OSC Protection Description Caused by restart ss FMOD VFF behavior V mA V V V Vzcp Vzcpt for 4 h Aut Output consecutive ui 5 2 2 56 unchanged 0 0 O unchanged OVP overvoltage Switching protection Cycles VFF gt VFFlatch Latched 13 5 0 33 0 0 0 0 0 0 Vcomp VcoMPHi Auto V V i 1 4 6 SS COMPHi h d Vss gt tesa 5 6 5 Ves ar Y 0 0 unchange Output Vsspis OLP overload protection Vcomp V COMPH Latched 13 5 0 33 0 0 0 0 0 0 Vss gt VssLAT Vcomp VcoMPHi Auto Vss VcowPHi 1 4 i h d a restart 5 6 0 EON qu 0 unchange 4 Shortcircuit OUiPutshort Vsspis rotection circuit P protection Vcomp V COMPHI Latched 13 5 0 33 0 0 0 0 0 0 Vss gt Vssrar Transformer Ves gt saturation or Vcspis rd ocp _ Shorted for2 3 Latched 5 0 33 o 0 0 0 0 0 secondary consecutive diode switching protection cycles Externally settable overtempera Vpis gt Vorp Latched 13 5 0 33 0 0 0 0 0 0 ture OTP protection Internal M thermal Ti 160 C a NO 5 0 33 0 0 0 0 0 0 restart shutdown Mains Aut Brownout undervoltag Vac_oK lt e 5 0 33 0 0 0 0 O unchanged Vin restart e protection Reference Vper drift drift protection Vngr gt Voy Latched 13 5 0 33 0 0 0 0 0 0 Gate driver Au
33. long as the voltage on the pin is below 0 45 V and is OFF if this value is exceeded Bypass the pin with a capacitor to GND pin 3 to reduce noise pick up Tie to Vcc with a 220 to 680 kQ resistor if the function is not used 2 L6566B Electrical data 3 3 1 3 2 2 Electrical data Maximum rating Table 2 Absolute maximum ratings Symbol Pin Parameter Value Unit Vuvs 1 Voltage range referred to ground 0 3 to 700 V luvs 1 Output current Self limited Voc 5 IC supply voltage Icc 20 mA Self limited VrMOD 6 Voltage range 0 3 to 2 V V max 7 8 10 14 Analog inputs and outputs 0 3 to 7 V Vmax 9 15 16 Maximum pin voltage Ipin x 1 mA Self limited lzcD 11 Zero current detector max current 5 mA VMODE SC 12 Voltage range 0 3 to 5 3 Vosc 13 Voltage range 0 3 to 3 3 V Prot Power dissipation T 50 C 0 75 W TsTG Storage temperature 55 to 150 C Ty Junction operating temperature range 40 to 150 C Thermal data Table 3 Thermal data Symbol Parameter Value Unit Riha Thermal resistance junction to ambient 120 C W 11 51 Electrical characteristics L6566B 4 Electrical characteristics Tj 25 to 125 C Vcc 12 Co 1 nF MODE SC VREF RT 20 kO from OSC to GND unless otherwise specified Table 4 Electrical characteristic
34. ltage falling below 0 45 V clears the latch This may allow a quicker restart as the input source is removed While the brownout protection is active the start up generator keeps on working but being there no PWM activity the Vcc voltage continuously oscillates between the start up and the HV generator restart thresholds as shown in the timing diagram of Figure 25 37 51 Application information L6566B Figure 25 Brownout protection internal block diagram and timing diagram Sensed voltage VsenoN r VsenoFF VAC OK pin 16 Sensed voltage AC FAIL L6566B Hvs RH 15 pA AC_OK RL The brownout comparator is provided with current hysteresis in addition to voltage hysteresis an internal 15 pA current sink is ON as long as the voltage applied on the AC OK pin is such that the AC FAIL signal is high This approach provides an additional degree of freedom it is possible to set the ON threshold and the OFF threshold separately by properly choosing the resistors of the external divider see below With just voltage hysteresis instead fixing one threshold automatically fixes the other one depending on the built in hysteresis of the comparator With reference to Figure 25 the following relationships can be established for the ON Vsenon and OFF Vsenorp thresholds of the sensed voltage Equation 16 _ 0 485 Vsenorf 0 45 0 45 Ry RL Ry R which s
35. n The pin will be driven by the phototransistor emitter grounded of an optocoupler to modulate its voltage by modulating the current sunk A capacitor placed between the pin and GND 3 as close to the IC as possible to reduce noise pick up sets a pole in the output to control transfer function The dynamics of the pin is in the 2 5 to 5 V range A voltage below an internally defined threshold activates burst mode operation The voltage at the pin is bottom clamped at about 2 V If the clamp is externally overridden and the voltage is pulled below 1 4 V the IC will shut down 10 VREF An internal generator furnishes an accurate voltage reference 5 V 2 96 that can be used to supply few mA to an external circuit A small film capacitor 0 1 uF typ connected between this pin and GND 3 is recommended to ensure the stability of the generator and to prevent noise from affecting the reference This reference is internally monitored by a separate auxiliary reference and any failure or drift will cause the IC to latch off 9 51 Pin settings L6566B Table 1 Pin functions continued N 11 Pin ZCD Function Transformer demagnetization sensing input for quasi resonant operation and OVP input The pin is externally connected to the transformer s auxiliary winding through a resistor divider A negative going edge triggers MOSFET s turn on if QR mode is selected A voltage exceeding 5 V shuts
36. ntermittent which is undesired Furthermore this must be traded off against the need of generating a voltage not exceeding the maximum allowed by the control IC at full load To help the designer overcome this problem the device besides reducing its own consumption during burst mode operation also features a proprietary adaptive UVLO function It consists of shifting the UVLO threshold downwards at light load namely when the voltage at pin COMP falls below a threshold Vcompo internally fixed so as to have more headroom To prevent any malfunction during transients from minimum to maximum load the normal higher UVLO threshold is re established when the voltage at pin COMP exceeds Vcoyp and Vcc has exceeded the normal UVLO threshold see Figure 13 The normal UVLO threshold ensures that at full load the MOSFET will be driven with a proper gate to source voltage Adaptive UVLO block VeCorrs lt Veco is selected when Qis high t VCOMP pin 9 VCOMPL VCOMPO Vcc pin 5 Vecorr2 Q L6566B ky 25 51 Application information L6566B 5 5 26 51 PWM control block The device is specific for secondary feedback Typically there is a TL431 on the secondary side and an optocoupler that transfers output voltage information to the PWM control on the primary side crossing the isolation barrier The PWM control input pin 9 COMP is driven directly by the phototrans
37. olved for Ry and R yield Equation 17 _ Vsenon 1 078 Vsenorr 0 45 R R Ry 15 1078 H Vsenorr 0 45 38 51 IST L6566B Application information Figure 26 Voltage sensing techniques to implement brownout protection with the L6566B HV Input bus Be ga He AC mains L N ENYA AC mains N L RH RH les pees AC_OK RH R L6566B L6566B L1 RL RL HO RL2 a Optionalfor OVPsettings Optionalfor OVP settings b It is typically convenient to use a single divider to bias both the AC OK and the VFF pins as shown in Figure 26 this is possible because in all practical cases the voltage on the VFF pin is lower than that on the AC OK pin Once Ry and R have been found as suggested above and Kopt either calculated from 6 or 8 or experimentally found RL will be split as Equation 18 Ri ky Ri R4 Ru RL Rto Circuit a senses the input voltage bus across the bulk capacitor downstream the bridge rectifier in this case for a proper operation of the brownout function Vsenon must be lower than the peak voltage at minimum mains and Vsengpr lower than the minimum voltage on the input bulk capacitor at minimum mains and maximum load considering in case holdup requirements during mains missing cycles as well Brownout level will be load dependent In case of latched shutdown when the input source is removed it is nece
38. om zero to its final value thus causing the duty cycle to increase progressively starting from zero as well During soft start the adaptive UVLO function and all functions monitoring pin COMP are disabled The soft start capacitor is discharged whenever the supply voltage of the IC falls below the UVLO threshold The same capacitor is used to delay IC s shutdown latch off or auto restart mode selectable after detecting an overload condition OLP 15 VFF Line voltage feedforward input The information on the converter s input voltage is fed into the pin through a resistor divider and is used to change the setpoint of the pulse by pulse current limitation the higher the voltage the lower the setpoint The linear dynamics of the pin ranges from 0 to 3 V A voltage higher than 3 V makes the IC stop switching If feedforward is not desired tie the pin to GND pin 3 directly if a latch mode OVP is not required see pin 11 ZCD or through a 10 KQ min resistor if a latch mode OVP is required Bypass the pin with a capacitor to GND pin 3 to reduce noise pick up 16 AC OK Brownout protection input A voltage below 0 45 V shuts down not latched the IC lowers its consumption and clears the latch set by latched protections DIS 4 5 V SS gt 6 4 V VFF gt 6 4 V IC s operation is re enabled as the voltage exceeds 0 45 V The comparator is provided with current hysteresis an internal 15 pA current generator is ON as
39. p max where Vinmax is the maximum dc input voltage and Ns the turn number of the primary winding See Section 5 2 Zero current detection and triggering block oscillator block on page 21 for additional details To reduce sensitivity to noise and prevent the latch from being erroneously activated first the OVP comparator is active only for a small time window typically 0 5 us starting 2 us after MOSFET s turn off to reject the voltage spike associated to the positive going edges of the voltage across the auxiliary winding Vaux second to stop the L6566B the OVP comparator must be triggered for four consecutive switching cycles A counter which is reset every time the OVP comparator is not triggered in one switching cycle is provided to this purpose Figure 22 on page 35 shows the internal block diagram while the timing diagrams in Figure 23 illustrate the operation To use the OVP function effectively i e to ensure that the OVP comparator will be always interrogated during MOSFET s OFF time the duty cycle D under open loop conditions must fulfill the following inequality L6566B Application information Equation 15 D Tai awe few lt 1 where TeLanko 2 US this is also illustrated in the diagram of Figure 24 Figure 24 Maximum allowed duty cycle vs switching frequency for correct OVP detection 0 8 0 7 0 6 Dmax 0 5 0 4 0 3 0 2 5 104 1 10 15 10 2 10 2 540
40. pplication examples and ideas L6566B 46 51 Figure 31 Frequency foldback at light load FF operation R1 R2 MODE SC Vref COMP Lesson 2 pk aceso D m eo il Figure 32 Latched shutdown upon mains overvoltage Vin Le566B P5 E 10 o 15 ver 9 L6566B 15 Rq L6566B Package mechanical data 7 Package mechanical data In order to meet environmental requirements ST offers these devices in ECOPACK9 packages These packages have a lead free second level interconnect The category of second Level Interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com r 47 51 Package mechanical data L6566B 48 51 Table 8 SO16N mechanical data mm inch Dim Min Typ Max Min Typ Max A 1 75 0 069 al 0 1 0 25 0 004 0 009 a2 1 6 0 063 b 0 35 0 46 0 014 0 018 b1 0 19 0 25 0 007 0 010 C 0 5 0 020 ci 45 typ 9 8 10 0 386 0 394 5 8 6 2 0 228 0 244 e 1 27 0 050 e3 8 89 0 350 F 3 8 4 0 0 150 0 157 G 4 60 5 30 0 181 0 208 L 0 4 1 27 0 150 0 050 M 0 62 0 024 S 8 m
41. r divided by 128 Additionally to prevent malfunction at converter s start up the pull up is disabled during the initial soft start see the relevant section However to ensure a correct ky L6566B Application information start up at the end of the soft start phase the output voltage of the converter must meet the condition Equation 4 Ns Vout gt Ral Naux Z ZOD where Ns is the turn number of the secondary winding Naux the turn number of the auxiliary winding and lzcp the maximum pull up current 130 yA The operation described so far under different operating conditions for the converter is illustrated in the timing diagrams of Figure 10 If the FF option is selected the operation will be exactly equal to that of a standard current mode PWM controller It will work at a frequency fsw fosc both DCM and CCM transformer s operation are possible depending on the operating conditions input voltage and output load and on the design of the power stage The MOSFET is turned on at the beginning of each oscillator cycle and is turned off as the voltage on the current sense pin reaches an internal reference set by the line feedforward block The maximum duty cycle is limited at 70 minimum The signal on the ZCD pin in this case is used only for detecting feedback loop failures see Section 5 11 OVP block on page 35 Figure 10 Operation of ZCD triggering and oscillator
42. r cycle the MOSFET will be turned on and a new switching cycle will take place after skipping no more than one oscillator cycle The operation described so far does not consider the blanking time Tp ank after MOSFET s turn off and actually Tg AN does not come into play as long as the following condition is met Equation 3 D eda TBLANK 7 T osc where D is the MOSFET duty cycle If this condition is not met things do not change substantially the time during which MOSFET s turn on is inhibited is extended beyond Tosc by a fraction of Tg ank AS a consequence the maximum switching frequency will be a little lower than the programmed value fosc and valley skipping mode may take place slightly earlier than expected However this is quite unusual setting fosc 150 kHz the phenomenon can be observed at duty cycles higher than 60 See Section 5 11 OVP block on page 35 for further implications of Tg ANK If the voltage on the COMP pin 9 saturates high which reveals an open control loop an internal pull up keeps the ZCD pin close to 2 V during MOSFET s OFF time to prevent noise from false triggering the detection block When this pull up is active the ZCD pin might not be able to go below the triggering threshold which would stop the converter To allow auto restart operation however ensuring minimum operating frequency in these conditions the oscillator frequency that retriggers MOSFET s turn on is that of the external oscillato
43. r services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries
44. rate from any pulsed current return GD Gate driver output The totem pole output stage is able to drive power MOSFET s and IGBT s with a peak current capability of 800 mA source sink 8 51 L6566B Pin settings 2 Table 1 Pin functions continued N Pin Vcc Function Supply voltage of both the signal part of the IC and the gate driver The internal high voltage generator charges an electrolytic capacitor connected between this pin and GND pin 3 as long as the voltage on the pin is below the turn on threshold of the IC after that it is disabled and the chip is turned on The IC is disabled as the voltage on the pin falls below the UVLO threshold This threshold is reduced at light load to counteract the natural reduction of the self supply voltage Sometimes a small bypass capacitor 0 1 uF typ to GND might be useful to get a clean bias voltage for the signal part of the IC FMOD Frequency modulation input When FF mode operation is selected a capacitor connected from this pin to GND pin 3 is alternately charged and discharged by internal current sources As a result the voltage on the pin is a symmetrical triangular waveform with the frequency related to the capacitance value By connecting a resistor from this pin to pin 18 OSC it is possible to modulate the current sourced by the OSC pin and then the oscillator frequency This modulation is to reduce the peak value of EMI emi
45. rent capability Vzcp VzcpH 3 mA TeLank1 Turn on inhibit time After gate drive going low 2 5 us Vzcpth_ OVP threshold 4 85 5 5 15 V TeLank2 OVP strobe delay After gate drive going low 2 us Latched shutdown function lorp Input bias current Vpis 0 to Vorp 1 pA Votp Disable threshold 1 432 45 4 68 V Thermal shutdown Vth Shutdown threshold 160 C Hys Hysteresis 50 C External oscillator frequency modulation frmoD Oscillation frequency Cmop 0 1 pF 600 750 900 Hz Usable frequency range 0 05 15 kHz Vpk Peak voltage 3 1 5 V Vw Valley voltage 0 5 V IFEMOD Charge discharge current 150 yA Mode selection slope compensation MODE Threshold for QR operation 3 V SC Ramp peak Rs comp 3 KO to GND GD 17 V pk MODE SC open pin high Vcomp 5 V SC Ramp starting value Rs comP 3 KQ to GND 03 V MODE SC open GD pin high ose E GD pin low 0 V Mostra emen os ky 15 51 Electrical characteristics L6566B Table 4 Electrical characteristics continued Symbol Parameter Test condition Min Typ Max Unit Soft start lex v edo n ss 2 V 14 20 26 Charge current UA Isso v E Vss gt i 8 5 5 6 5 COMP V COMPHi Icsdis Discharge current Vas 22V 3 5 5 6 5 pA Vsscamp High saturation voltage Vcomp 4 V 2 V Vsspis Disable level MD Veome VcoMPHi 4 85 5 5 15 VssLar _ Latch off level Vcomp VcoMPHi 6 4 V Gate
46. riggering block L6566B PWM latch 2 bit counter x Counter reset Monostable M2 The ZCD pin will be connected to the auxiliary winding through a resistor divider Rz1 Rz gt see Figure 8 on page 20 The divider ratio Koyp Rz Rz Rz2 will be chosen equal to Equation 13 5 Ns k IS QUE Voutoyp Naux where Voutoyp is the output voltage value that is to activate the protection Ns the turn number of the secondary winding and Naux the turn number of the auxiliary winding 35 51 Application information L6566B Note 36 51 Figure 23 OVP function timing diagram di a lg E E a E 3 i a a l U V ZCD l pin 11 I I t 5V NAA l t COUT I I A E I D D STROBE jme 08s l l i l i l i t I I I l l l l l T T T T T T T ove I I l I l I t I I l I l I I I I I T T T T T T T COUNTER i t l l o Y LI COUNTER l l l I I t STATUS 0 0 0 091 152 250 0 031 122 258 334 f f t t t t t t t FAULT I I l I I t I I l I l I t NORMAL OPERATION TEMPORARY DISTURBANCE FEEDBACK LOOP FAILURE The value of Rz will be such that the current sourced by the ZCD pin be within the rated capability of the internal clamp Equation 14 1 Naux gt Vin 713 103 N
47. ross the current sense resistor Rs as well and compares this voltage to a reference value Vcsx Its output is or ed with that of the PWM comparator see the circuit schematic in Figure 17 on page 29 In this way if the programming signal delivered by the feedforward block and sent to the PWM comparator exceeds Vesx it will be the OCP comparator to reset first the PWM latch instead of the PWM comparator The value of Vcsx thereby determines the overcurrent setpoint along with the sense resistor Rs The power that QR flyback converters with a fixed overcurrent setpoint like fixed frequency systems are able to deliver changes with the input voltage considerably With wide range mains at maximum line it can be more than twice the value at minimum line as shown by the upper curve in the diagram of Figure 16 on page 28 The device has the line feedforward function available to solve this issue It acts on the overcurrent setpoint Vcsx so that it is a function of the converter s input voltage Vin sensed through a dedicated pin 15 VFF the higher the input voltage the lower the 27 51 Application information L6566B setpoint This is illustrated in the diagram on the left hand side of Figure 17 on page 29 it shows the relationship between the voltage on the pin VFF and Vesx with the error amplifier saturated high in the attempt of keeping output voltage regulation Equation 5 V CSX qo Wee op Kun 3 3 Figure 16 Typical
48. s Symbol Parameter Test condition Min Typ Max Unit Supply voltage V MP gt V MPL 10 6 23 Vcc Operating range after turn on im V Vcomp VcompPo 8 23 Vecon Turn on threshold 1 13 14 15 V My gt V 9 4 10 10 6 MP MPL Vccog Turn off threshold a V Hys Hysteresis Vcomp gt VcoMPL 4 V Vz Zener voltage Icc 20 MA IC disabled 23 25 27 V Supply current start up Start up current Before turn on Vcc 13 V 200 250 pA la Quiescent current After turn on Vzcp Vos 1V 2 6 2 8 mA Icc Operating supply current MODE SC open 4 4 6 mA IC disabled 2 330 2500 ladis Quiescent current yA IC latched off 440 500 High voltage start up generator Vuy Breakdown voltage luy lt 100 pA 700 Vuvstart Start voltage lycc lt 100 pA 65 80 100 V Icharge Vcc charge current Vuv gt Vhvstart Voc gt 3 V 0 55 0 85 1 mA Vuy gt VH Vcc 3V 1 6 lav oN ON state current mA Vuv gt Vuystart Vcc 0 0 8 luy ore OFF state leakage current Vuy 400 V 40 pA Vcc falling 4 4 5 5 6 1 IC latched off 12 5 135 14 5 Vocrestart Vcc restart voltage a V Disabl 33000 94 10 106 Vcomp lt VcoMPorF 12151 I L6566B Electrical characteristics Table 4 Electrical characteristics continued Symbol Parameter Test condition Min Typ Max Unit Reference voltage Vaer Output voltage MT 25 C Incr 1 mA 4 95 5 5 05 V VREF Total variation i Li 4
49. ssary to wait until the bulk capacitor voltage falls below the start voltage of the HV generator V4ystart in order for the unit to restart which may take even several seconds Circuit b senses the mains voltage directly upstream the bridge rectifier It can be configured either for half wave sensing only the line neutral wire is sensed or full wave sensing both neutral and line are sensed in the first case assuming Cr is large enough the sensed voltage will be equal to 1 7 the peak mains voltage while in the second case it will be equal to 2 7 the peak mains voltage Cp needs to be quite a big capacitor in the uF to have small residual ripple superimposed on the dc level as a rule of thumb use a time constant R Cp at least 4 5 times the maximum line cycle period in case of half wave sensing 2 3 times in case of full wave sensing Then fine tune if needed considering also transient conditions such as mains missing cycles Brownout level will not depend on the load When the input source is removed Cp will be discharged after some ten ms then this circuit is suitable to have a quick restart after a latched shutdown The AC OK pin is a high impedance input connected to high value resistors thus it is prone to pick up noise which might alter the OFF threshold when the converter is running or give origin to undesired switch off of the device during ESD tests It is possible to bypass the pin to ground with a small film capacitor e g 1 10
50. ssions by means of a spread spectrum action If the function is not used the pin will be left open CS Input to the PWM comparator The current flowing in the MOSFET is sensed through a resistor the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET s turn off The pin is equipped with 150 ns min blanking time after the gate drive output goes high for improved noise immunity A second comparison level located at 1 5 V latches the device off and reduces its consumption in case of transformer saturation or secondary diode short circuit The information is latched until the voltage on the Vcc pin 5 goes below the UVLO threshold hence resulting in intermittent operation A logic circuit improves sensitivity to temporary disturbances DIS IC s latched disable input Internally the pin connects a comparator that when the voltage on the pin exceeds 4 5 V latches off the IC and brings its consumption to a lower value The latch is cleared as the voltage on the Vcc pin 5 goes below the UVLO threshold but the HV generator keeps the Vcc voltage high see pin 1 description It is then necessary to recycle the input power to restart the IC For a quick restart pull pin 16 AC OK below the disable threshold see pin 16 description Bypass the pin with a capacitor to GND pin 3 to reduce noise pick up Ground the pin if the function is not used COMP Control input for loop regulatio
51. st of tables L6566B List of tables Table 2 Pin functions anus rm east ae heeded ewe yaw des ii be 8 Table 3 Absolute maximum ratings 11 Table 4 Thermal data z uui tein ea ia E a 11 Table 5 Electrical characteristics Ree 12 Table 6 L6566B light load management features 41 Table 7 L6566B protections 0 ee hh 42 Table 8 External circuits that determine IC behavior upon OVP and OCP 45 Table 9 SO16N mechanical data naaa aaea 48 Table 10 Order codes siiis rs is ad ade x E abea e te ds 49 Table 11 Revision history 50 4 51 I L6566B List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Block diagram 2 2 vezes ar dn a E evade a 1 Typical system block diagram 7 Pin connection through top view 8 Multi mode operation with QR option active 17 High voltage start up generator internal schematic eee eeee 18 Timing diagram normal power up and power down sequences 19 Timing diagram showing short circuit behavior SS pin clamped at 5V 20 Zero current detection block triggerin
52. ted from FMOD to ground and is alternately charged and discharged between 0 5 and 1 5 V by internal current generators sourcing and sinking the same current three times the current defined by the resistor Rr on pin OSC Hence the voltage across Cmop will be a symmetric triangle whose frequency fm is determined by Cyop By connecting a resistor Ryon from FMOD to OSC the current sourced by pin OSC will be modulated according a triangular profile at a frequency fm If Rmob is considerably higher than Ry as normally is both fm and the symmetry of the triangle will be little affected With this arrangement it is possible to set nearly independently the frequency deviation Afsy and the modulating frequency fm which define the modulation index 31 51 Application information L6566B 5 9 32 51 Equation 9 which is the parameter that the amplitude of the generated side band harmonics depends on The minimum frequency fs min occurring on the peak of the triangle and the maximum frequency fs max occurring on the valley of the triangle will be symmetrically placed around the centre value f y so that Equation 10 fsw_min few 2 Afs fsw_max fw gt Afsy Then Ry will be found from 5 see Section 5 2 Zero current detection and triggering block oscillator block on page 21 while Ryop and Cyop can be calculated as follows Equation 11 2 10 75 Cmop Tu Rmoo Afsw m where Af y and fm in kHz
53. the IC down and brings its consumption to a lower value OVP Latch off or auto restart mode is selectable externally This function is strobed and digitally filtered to increase noise immunity 10 51 12 MODE SC Operating mode selection If the pin is connected to the VREF pin 7 quasi resonant operation is selected the oscillator pin 18 OSC determines the maximum allowed operating frequency Fixed frequency operation is selected if the pin is not tied to VREF in which case the oscillator determines the actual operating frequency the maximum allowed duty cycle is set at 70 min and the pin delivers a voltage ramp synchronized to the oscillator when the gate drive output is high the voltage delivered is zero while the gate drive output is low The pin is to be connected to pin CS 7 via a resistor for slope compensation 13 OSC Oscillator pin The pin is an accurate 1 V voltage source and a resistor connected from the pin to GND pin 3 defines a current This current is internally used to set the oscillator frequency that defines the maximum allowed switching frequency of the L6566B if working in QR mode or the operating switching frequency if working in FF mode 14 SS Soft start current source At start up a capacitor Css between this pin and GND pin 3 is charged with an internal current generator During the ramp the internal reference clamp on the current sense pin 7 CS rises linearly starting fr
54. the maximum peak primary current Ipkpmax occurring at minimum input voltage Vinmin has been found the value of Rs can be determined from 5 Equation 7 1 foot y lPkp max inmin Rs 3 Figure 17 Left overcurrent setpoint vs VFF voltage right line feedforward function block LI P VOLTAGE i FEED FORWARD EHS Rectified Line Voltage Vesx V 1 2 Veowe Upper clamp R1 1 0 8 R2 i I 0 6 0 4 ST 0 2 0 0 0 5 1 1 5 2 2 5 3 3 5 WeF V Clock ZCD DISABLE The converter is then tested on the bench to find the output power level Pout where regulation is lost because overcurrent is being tripped both at Vin Vinmin and Vin Vinmax If POUtjim Vinmax gt POUtiim Vinmin the system is still undercompensated and k needs increasing if PoUtiim Vinmax lt POUtjim Vin min the system is overcompensated and k needs decreasing This will go on until the difference between the two values is acceptably low Once found the true Kopt in this way it is possible that Poutj turns out slightly different from the target to correct this the sense resistor Rs needs adjusting and the above tuning process will be repeated with the new Rs value Typically a satisfactory setting is achieved in no more than a couple of iterations In applications where this function is not wanted e g because of a narrow input voltage range the VFF pin can be simply
55. to unchang uncha Shutdown1 disable Ver gt Voti restant 5 2 5 5 unchanged ad 1 nged unchanged 42 51 IST L6566B Application information Table 6 L6566B protections continued IC Vee ic iq VREF VCOMP osc Protection Description Caused by restart ss FMOD VFF behavior v mA V V V Shutdown V 2 Shutdown2 by Vcomp COMP Latched 10 0 33 0 0 0 0 0 0 low VCOMPOFF Shutdown Vec lt 9 4V by Vec going vcomp gt ADAPTIVE Pelow Veco VooMPD Auto 0 18 UVLO lowering of restart 5V ma 0 0 0 0 0 0 Vecott Voc lt 7 2V threshold at vcomp gt light load VcowPo 1 Use One external diode from Ver 15 to AC OK 16 cathode to AC OK 2 Use one external diode from SS 14 to Vper 10 cathode to Vpef 3 If Css and the Voc capacitor are such that V falls below UVLO before latch tripping Figure 21 on page 34 4 f Css and the Vcc capacitor are such that the latch is tripped before Vec falls below UVLO Figure 21 on page 34 5 When Tj 110 C 6 Discharged to zero by Vec going below UVLO 2 It is worth reminding that Auto restart means that the device will work intermittently as long as the condition that is activating the function is not removed Latched means that the device is stopped as long as the unit is connected to the input power source and the unit must be disconnected for some time from the source in order for the devic
56. uasi resonant mode Pinmax e 0 e 0 0 0 e e e M H Burst mode O H of 0 17 51 Application information L6566B If FF operation is selected 1 FF mode from heavy to light load The system operates exactly like a standard current mode control at a frequency fw determined by the externally programmable oscillator both DCM and CCM transformer operation are possible depending on whether the power that it processes is greater or less than Equation 1 where Vin is the input voltage to the converter Vg the reflected voltage i e the regulated output voltage times the primary to secondary turn ratio and Lp the inductance of the primary winding Piny is the power level that marks the transition from continuous to discontinuous operation mode of the transformer Burst mode with no or very light load This kind of operation is activated in the same way and results in the same behavior as previously described for QR operation The L6566B is specifically designed for applications with no PFC front end pin 6 FMOD features an auxiliary oscillator that can modulate the switching frequency when FF operation is selected in order to mitigate EMI emissions by a spread spectrum action 5 1 High voltage start up generator Figure 5 shows the internal schematic of the high voltage start up generator HV generator It is made up of a high voltage N channel FET whose gate is biased by a 15 MQ resistor
57. y related losses and making it easier to comply with energy saving regulations This kind of operation shown in the timing diagrams of Figure 11 along with the others previously described is noise free since the peak current is low If itis necessary to decrease the intervention threshold of the burst mode operation this can be done by adding a small DC offset on the current sense pin as shown in Figure 12 on page 25 Note The offset reduces the available dynamics of the current signal thereby the value of the sense resistor must be determined taking this offset into account Figure 11 Load dependent operating modes timing diagrams COMP pin 9 VCOMPBM a pin 4 MODE SC Open a FF Mode se Burst mode po 8 FF Mode n a QR Mode gt Burst mode gt MODE SC VREF QR Mode gt t 7 LS Valley skipping Mode 24 51 ky L6566B Application information 5 4 Figure 13 Figure 12 Addition of an offset to the current sense lowers the burst mode operation threshold Adaptive UVLO A major problem when optimizing a converter for minimum no load consumption is that the voltage generated by the auxiliary winding under these conditions falls considerably as compared even to a few mA load This very often causes the supply voltage Vcc of the control IC to drop and go below the UVLO threshold so that the operation becomes i
58. ypical full feature application schematic QR operation 44 Typical full feature application schematic FF operation 45 Frequency foldback at light load FF operation LL 46 Latched shutdown upon mains overvoltage 2 auaa ee eee 46 5 51 Description L6566B 1 Description The L6566B is an extremely versatile current mode primary controller ICs specifically designed for high performance offline flyback converters It is also suited for single stage single switch input current shaping converters single stage PFC for applications supposed to comply with EN61000 3 2 or JEITA MITI regulations Both fixed frequency FF and quasi resonant QR operation are supported The user can pick either of the two depending on application needs The device features an externally programmable oscillator it defines converter s switching frequency in FF mode and the maximum allowed switching frequency in QR mode When FF operation is selected the ICs work like a standard current mode controller with a maximum duty cycle limited at 70 min The oscillator frequency can be modulated to mitigate EMI emissions QR operation when selected occurs at heavy load and is achieved through a transformer demagnetization sensing input that triggers MOSFET s turn on Under some conditions ZVS zero voltage switching can be achieved Converter s power capability rise with the mains voltage is compensated by line voltage feedforward At medium and l
59. ystem works close to the boundary between discontinuous DCM and continuous conduction CCM of the transformer As a result the switching frequency will be different for different line load conditions see the hyperbolic like portion of the curves in Figure 4 Minimum turn on losses low EMI emission and safe behavior in short circuit are the main benefits of this kind of operation Valley skipping mode at medium light load The externally programmable oscillator of the L6566B synchronized to MOSFET s turn on enables the designer to define the maximum operating frequency of the converter As the load is reduced MOSFET s turn on will not any more occur on the first valley but on the second one the third one and so on In this way the switching frequency will no longer increase piecewise linear portion in Figure 4 3 Burst mode with no or very light load When the load is extremely light or disconnected the converter will enter a controlled on off operation with constant peak current Decreasing the load will then result in frequency reduction which can go down even to few hundred hertz thus minimizing all frequency related losses and making it easier to comply with energy saving regulations or recommendations Being the peak current very low no issue of audible noise arises Multi mode operation with QR option active Figure 4 fosc 4 Input voltage 0 X e NL Valley skipping mode 4 N f Sw Q
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