ST VIPer20A-E Manual(1)(1)
Contents
1. Table 9 Pentawatt HV Mechanical data mm inch Dim Min Typ Max Min Typ Max A 4 30 4 80 0 169 0 189 C 1 17 1 37 0 046 0 054 D 2 40 2 80 0 094 0 11 E 0 35 0 55 0 014 0 022 F 0 60 0 80 0 024 0 031 G1 4 91 5 21 0 193 0 205 G2 7 49 7 80 0 295 0 307 H1 9 30 9 70 0 366 0 382 H2 10 40 0 409 H3 10 05 10 40 0 396 0 409 L 15 60 17 30 6 14 0 681 L1 14 60 15 22 0 575 0 599 L2 21 20 21 85 0 835 0 860 L3 22 20 22 82 0 874 0 898 L5 2 60 3 0 102 0 118 L6 15 10 15 80 0 594 0 622 L7 6 6 60 0 236 0 260 M 2 50 3 10 0 098 0 122 M1 4 50 5 60 0 177 0 220 R 0 50 0 02 V4 90 Diam 3 65 3 85 0 144 0 152 Figure 25 Package dimension i Ko 1 i i i T G S U 1 T o P023H3 24 34 SI VIPer20A E Package mechanical data Table 10 Pentawatt HV 022Y Vertical High Pitch Mechanical data mm inch Dim Min Typ Max Min Typ Max A 4 30 4 80 0 169 0 189 C 1 17 1 37 0 046 0 054 D 2 40 2 80 0 094 0 110 E 0 35 0 55 0 014 0 022 F 0 60 0 80 0 024 0 031 G1 4 91 5 21 0 193 0 205 G2 7 49 7 80 0 295 0 307 H1 9 30 9 70 0 366 0 382 H2 10 40 0 409 H3 10 05 10 40 0 396 0 409 L 16 42 17 42 0 646 0 686 L1 14 60 15 22 0 575 0 599 L3 20 52 21 52 0 808 0 847 L5 2 60 3 00 0 102 0 1182. Figure 28 Package dimension SEATING PLANE TA gt a 1 SEATING T PLANE N Ee L HE 210 RE T A1 DETAIL A 0068039 C 4 27 34 Package mechanical data VIPer20A E Figure 29 Power Pad layout 146 149 108 11 Figure 30 Tube shipment c pr iim All dimensions are in mm CASABLANCA J F TALI L MUAR Table 13 Tube shipment Base Q ty Bulk Q ty Tube length x 0 5 A B C x 0 1 Casablanca 50 1000 532 10 4 16 4 0 8 Muar 50 1000 532 4 9 17 2 0 8 28 34 ky VIPer20A E Package mechanical data Figure 31 Reel shipment 40mm min Access hole at slot location WA EN N N En EE ca ena See G measured N Full radius i AN IT athub N S Tape slot bow in core for W e m tape start i 2 5mm min width E Table 14 Reel dimension Base Q ty 600 Bulk Q ty 600 A
3. 13 5 5 External clock synchronization 14 5 6 Primary peak current limitation 14 5 7 Over temperature protection 14 5 8 Operation piCtUT S ax pelea bal tadaa ea b e DRDD GOD EKANA 15 2 34 4 VIPer20A E Contents 10 4 Electrical over Stress 21 6 1 Electrical over stress ruggedness 21 Lay EE 22 7 1 Layout considerations 22 Package mechanical data 23 Ordergode SIE aceeasi asa Me Ob ERA MES haha ka 32 Revisionhistory 33 3 34 Electrical data VIPer20A E 1 Electrical data 11 Maximum rating Table 1 Absolute maximum rating Symbol Parameter Value Unit Vps Continuous Drain Source Voltage Ty 25 to 125 C 0 3 to 700 V Ip Maximum Current Internally limited A VoD Supply Voltage 0 to 15 V Vosc Voltage Range Input 0 to Vpp V Vcomp Voltage Range Input 0 to 5 V lcoMP Maximum Continuous Current 2 mA Vesp Electrostatic Discharge R 1 5kQ C 100pF 4000 V pup a ON Curent Bene or Not Repetitive G n Tc 100 C Pulse width limited by Tj max 8 1 Pror Power Dissipation at To 25 C 57 W Ty Junction Operating Temperature Internally limited C Tera
4. I i li li t M en ENABLE ENABLE DISABLE Figure 9 Breakdown voltage vs temperature Figure 10 Typical freguency variation FC00180 FE 900 1 15 y 1 BVoss Normalized 0 1 1 1 1 05 2 3 1 4 5 L 1 L 1 L 0 95 N 1 L L L L L die 031 0035 0 20 u 80 su 120 140 Temperature C emperature C ky 15 34 Operation description VIPer20A E Figure 11 Behaviour of the high voltage current source at start up Auxiliary primary winding UNDERVOLTAGE LOCK OUT LOGIC viPer20 Start up duty cycle 12 SOURCE FC00101A Figure 12 Start up waveforms Vinput A gt Vpp t Yoo on VDD off gt Veomp A t gt Vosc t gt Voutput A t oo Kk Soft start i gt Start up action SC10290 16 34 lt viPer20A E Operation description Figure 13 Over temperature protection comp SC 101 91 4 17 34 Operation description VIPer20A E Figure 14 Oscillator For R gt 1 2kQ and C lt 40KHz FC00050 Ct Forbidden area KEN 880 UNE ee Forbidden area 40kHz SW Oscillator frequency vs Rt and Ct 1 000 FC00030 Ct 1 5 nF 500 Ct 2 7 nF 300 N I Ct 4 7 nF 200 gt o c 2 Ct 10nF 100 2 LL 50 30 2 3 5 10 20 30 50
5. Part number Package VIPer20A E PENTAWATT HV VIPer20A 22 E PENTAWATT HV 022Y VIPer20ADIP E DIP 8 VIPer20ASP E PowerSO 10 lt VIPer20A E Revision history 10 Revision history 4 Table 19 Revision history Date Revision Changes 28 Sep 2005 1 Initial release 21 Jun 2006 2 New template few updates 33 34 VIPer20A E Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the us
6. TR2 ct AC IN BR1 TR1 VIPer20 C5 cij FC00401 NA Figure 4 Offline power supply with optocoupler feedback F1 FN Haa BR1 x _ c1 k R TR1 N YA ES JE u Vee gt E cr coe VIPer20 10 34 FC00411 ky VIPer20A E Operation description 5 5 1 5 2 lt Operation description Current mode topology The current mode control method like the one integrated in the devices uses two control loops an inner current control loop and an outer loop for voltage control When the Power MOSFET output transistor is on the inductor current primary side of the transformer is monitored with a SenseFET technigue and converted into a voltage Vs proportional to this current When Vs reaches Vcomp the amplified output voltage error the power switch is switched off Thus the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer Excellent open loop D C and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control This results in improved line regulation instantaneous correc
7. 4 18 34 VIPer20A E Operation description Figure 15 Error amplifier freguency response FC00200 Freguency kHz 4 60 RCOMP RCOMP 270k m 40 RCOMP 82k c c O 20 o D S S o 20 0 001 0 01 0 1 1 10 100 1 000 Frequency kHz Figure 16 Error amplifier phase response FC00210 200 RCOMP e 150 RCOMP 270k RCOMP 82k RCOMP 27k 100 o RCOMP 12k n a 50 0 50 0 001 0 01 0 1 1 10 100 1 000 19 34 Operation description VIPer20A E Figure 17 Mixed soft start and compensation Figure 18 Latched shut down D2 VIPer20 DRAIN DOr COMP SOURCE JF AUXILIARY WINDING FC00431 VIPer20 COMP SOURCE FC00440 Figure 19 Typical compensation network VIPer20 FC00451 VIPer20 N Por H COMP SOURCE NZ FC00461 Figure 21 External clock sinchronisation Figure 22 Current limitation circuit examp
8. L6 15 10 15 80 0 594 0 622 L7 6 00 6 60 0 236 0 260 M 2 50 3 10 0 098 0 122 M1 5 00 5 70 0 197 0 224 R 0 50 0 02 0 020 V4 90 90 Diam 3 65 3 85 0 144 0 154 Figure 26 Package dimension r n m i i EE yi i F a i i 7 9 o ga g 8 i 5 C yA m i i a c iM 9 o V m Q I 3 5 h ET X15 I 9 r 5 T w N ky 25 34 Package mechanical data VIPer20A E Table 11 DIP 8 Mechanical data mm Inch Dim Min Typ Max Min Typ Max A 3 32 0 131 al 0 51 0 020 1 15 1 65 0 045 0 065 b 0 356 0 55 0 014 0 022 b1 0 204 0 304 0 008 0 012 D 10 92 0 430 E 7 95 9 75 0 313 0 384 2 54 0 100 e3 7 62 0 300 e4 7 62 0 300 F 6 6 0 260 5 08 0 200 L 3 18 3 81 0 125 0 150 1 52 0 060 Figure 27 Package dimensions 26 34 4 viPer20A E Package mechanical data Table 12 PowerSO 10 mechanical data mm Inch Dim Min Typ Max Min Typ Max A 3 35 3 65 0 132 0 144 Al 0 00 0 10 0 000 0 004 B 0 40 0 60 0 016 0 024 C 0 35 0 55 0 013 0 022 D 9 40 9 60 0 370 0 378 D1 7 40 7 60 0 291 0 300 e 1 27 0 050 9 30 9 50 0 366 0 374 E1 7 20 7 40 0 283 0 291 E2 7 20 7 60 0 283 0 300 E3 6 10 6 35 0 240 0 250 E4 5 90 6 10 0 232 0 240 F 1 25 1 35 0 049 0 053 h 0 50 0 002 H 13 80 14 40 0 543 0 567 L 1 20 1 80 0 047 0 071 q 1 70 0 067 0 8
9. LATCH OSCILLATOR LOGIC ms FF a OVERTEMP DETECTOR 05V 17 us delay osv 7 250 ns Hee Blanking CURRENT AMPLIFIER ERROR AMPLIFIER 13V H isv FC00491 June 2006 COMP SOURCI 1 34 www st com Contents VIPer20A E Contents 1 Electrical dala ee amamus OR ee m pa RR TJ 4 1 1 Maximum Tag ana PA KDI cages sede REM ed REIR RE E ee de 4 1 2 Electrical characteristics 5 2 Thermal data ce jelman l 7 3 Pin description s imussa aa ss kukaan koko ll SEs Vek ee sage ewe 8 3 1 Drain pin Integrated Power MOSFET drain 8 3 2 SOUrCepin 8 3 3 VDD pin power supply 8 34 Compensationpin 8 3 5 OSC pin oscillator frequency 9 4 Typical circuit sis ss a anne 10 5 Operation description 11 5 1 Current mode topology 11 5 2 Stand by mode 11 5 3 High voltage start up current suorce 12 5 4 X Transconductance error amplifier
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11. Figure 14 Voscm Oscillator Peak Voltage 7 1 V Voscu Oscillator Valley Voltage 3 7 IST 5 34 Electrical data VIPer20A E Table 5 Error amplifier section Symbol Parameter Test conditions Min Typ Max Unit Vpprec Vpp Regulation Point Icomp 0mA see Figure 5 12 6 13 13 4 V AVppreg Total Variation Ty 0 to 100 C 2 From Input Vpp to Gew Unity Gain Bandwidth Output Vcomp 150 KHz COMP pin is open Figure 15 Avo Open Loop Voltage Gain i 2 Sn 45 52 dB Gm DC Transconductance Vcomp 2 5V see Figure 5 11 1 5 1 9 mA V Vcomp o Output Low Level Icomp 4004A Vpp 14V 0 2 VcompHi Output High Level lcomp 400pA Vpp 12V 4 5 V IcompLo Output Low Current Capability Vcomp 2 5V Vpp 14V 600 UA ICOMPHI ur Ma Sumari Vcomp 2 5V Vpp 12V 600 JA Table 6 PWM comparator section Symbol Parameter Test conditions Min Typ Max Unit Hip 1AVcomp AlDPEAK Vcomp 1 to 3 V 4 2 6 7 8 V A Vcompott Vcomp Offset IDPEAK 10mA 0 5 V Ibpeak Peak Current Limitation Vpp 12V COMP pin open 0 5 0 67 0 9 A ty 5 Sense Delay to Turn Ip 1A 250 He th Blanking Time 250 360 ns ton min Minimum On Time 350 1200 ns Table 7 Shutdown and overtemperature section Symbol Parameter Test conditions Min Typ Max Unit Vcompth_ Restart Threshold see Figure 8 0 5 V toissu Disable Set Up Time see Figure 8 1 7 5 us Tisa Eel in
12. M ET KAAN ER ARAM ISE Ayr VIPer20A E SMPS primary I C General features Type Vpss In RDson VIPer20A E 700V 0 5A 180 VIPer20ASP E 700V 0 5A 180 VIPer20ADIP E 700V 0 5A 18Q Adjustable switching frequency up to 200 kHz Current mode control Soft start and shutdown control Automatic burst mode operation in stand by condition able to meet blue angel norm lt 1w total power consumption Internally trimmed zener reference Undervoltage lock out with hysteresis Integrated start up supply Over temperature protection Low stand by current Adjustable current limitation Block diagram POWERSO 10 PENTAWATT HV 022Y Description All the devices are made using VIPower MO Technology combines on the same silicon chip a state of the art PWM circuit together with an optimized high voltage Vertical Power MOSFET 700V 0 5A Typical applications cover offline power supplies with a secondary power capability of 10W in wide range condition and 20W in single range or with doubler configuration It is compatible from both primary or secondary regulation loop despite using around 50 less components when compared with a discrete solution Burst mode operation is an additional feature of this device offering the ability to operate in stand by mode without extra components osc DRAIN ON OFF SECURITY
13. Storage Temperature 65 to 150 C 4 34 4 VIPer20A E Electrical data 1 2 Electrical characteristics Ty 25 C Vpp 18V unless otherwise specified Table 2 Power section Symbol Parameter Test conditions Min Typ Max Unit BVps Drain Source Voltage p 1mA Vcomp OV 700 V Off State Drain Vcomp OV T 125 C DSS Current Vps 700V 1 0 mA Static Drain Source p 0 4A 15 5 18 Q DS on On Resistance Ip 0 4A Ty 100 C 32 Q t Fall Time Ip 0 2A Vin 300V Figure 7 100 ns tr Rise Time Ip 0 4A Vin 300V 1 Figure 7 50 ns Coss Output Capacitance Vps 25V 90 pF 1 On Inductive Load Clamped Table 3 Supply section Symbol Parameter Test conditions Min Typ Max Unit Start Up Charging Current Vpp 5V VDS 35V IpDch 2 mA Figure 6 Figure 11 Operating Supply Current Vpp 12V Fsw OkHz Ippo 12 16 mA Figure 6 Ipp1 Operating Supply Current Vpp 12V Fey 100kHz 13 mA Ipp2 Operating Supply Current Vpp 12V Fey 200kHz 14 mA VDDoff Undervoltage Shutdown Figure 6 75 8 9 V Vppon Undervoltage Reset Figure 6 11 12 Vpphyst Hysteresis Start up Figure 6 24 3 V Table 4 Oscillator section Symbol Parameter Test conditions Min Typ Max Unit Ry 8 2KQ Cr 2 4nF Oscillator Freguency Total Vpp 9 to 15V F dop SW Variation with Rtt 1 Cr 5 EE E see Figure see
14. V the shut down of the circuit occurs with a zero duty cycle for the power MOSFET This feature can be used to switch off the converter and is automatically activated by the regulation loop no matter what the configuration is to provide a burst mode operation in case of negligible output power or open load condition ky VIPer20A E Pin description 3 5 OSC pin oscillator frequency An R C network must be connected on that to define the switching frequency Note that despite the connection of R to Vpp no significant frequency change occurs for Vpp varying from 8V to 15V It provides also a synchronisation capability when connected to an external frequency source Figure 1 Connection diagrams top view Tab DRAIN x O RU LLL 1 SOURCE TT DRAIN Ym LII SC12510 PENTAWATT HV 1 DRAIN CI Yoo I ose SC10420 PENTAWATT HV 022Y K DIP 8 DRAIN i osc e s SOURCE Vo L OT SOURCE NCC FD NC NC EI SOURCE COMP LI 10 1 SOURCE PowerSO 10 Figure 2 Current and voltage convention VoD Vcomp FC00020 4 Typical circuit 4 VIPer20A E Typical circuit Figure 3 Offline power supply with auxiliary supply feedback F1 DN
15. cause of the output capacitors and low output current drawn in such conditions The normal operation resumes automatically when the power gets back to higher levels than Porgy High voltage start up current suorce An integrated high voltage current source provides a bias current from the DRAIN pin during the start up phase This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and also provided to the external capacitor connected to the Vpp pin As soon as the voltage on this pin reaches the high voltage threshold Vppon of the UVLO logic the device becomes active mode and starts switching The start up current generator is switched off and the converter should normally provide the needed current on the Vpp pin through the auxiliary winding of the transformer as shown on see Figure 11 In case there are abnormal conditions where the auxiliary winding is unable to provide the low voltage supply current to the Vpp pin i e short circuit on the output of the converter the external capacitor discharges to the low threshold voltage Vppog of the UVLO logic and the device goes back to the inactive state where the internal circuits are in standby mode and the start up current source is activated The converter enters a endless start up cycle with a start up duty cycle defined by the ratio of charging current towards discharging when the VIPer20 E tries to start This ratio is fix
16. coupler must be able to provide 20mA through the optotransistor Primary peak current limitation The primary Ibprak current and consequently the output power can be limited using the simple circuit shown in Figure 22 The circuit based on Q1 R4 and R clamps the voltage on the COMP pin in order to limit the primary peak current of the device to a value I _ Vcomp 05 DPEAK 7 HM where R R Vcomp 9 6 x R The suggested value for R R is in the range of 220KQ Over temperature protection Over temperature protection is based on chip temperature sensing The minimum junction temperature at which over temperature cut out occurs is 140 C while the typical value is 170 C The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40 C below the shutdown value see Figure 13 lt VIPer20A E Operation description 5 8 Operation pictures Figure 5 Vpp Regulation point Figure 6 Undervoltage lockout loave lop Pe Ippo VDDo anon PP Ippch FC00170 FO00150 Figure 7 Transition time Figure 8 Shutdown action D4 VOSC WAAN 1096 Ipea i U U U VCOMP i tDISsu VCOMPh AL et kooda a d ogg ID I li M U U U U FC00160 J
17. d see Figure 8 140 170 190 C Thyst Thermal Shutdown Hysteresis see Figure 8 40 C 6 34 Ky VIPer20A E Thermal data 2 Thermal data Table 8 Thermal data Symbol Parameter PENTAWATT PowerSO 10 DIP 8 Unit Ringa Thermal Resistance Junction pin Max 20 C W Ric Thermal Resistance Junction case Max 2 0 2 0 C W Rihuc Thermal Resistance Ambient case Max 70 60 35 2 C W 1 When mounted using the minimum recommended pad size on FR 4 board 2 Onmultylayer PCB 4 7 34 Pin description VIPer20A E 3 3 1 3 2 3 3 3 4 8 34 Pin description Drain pin Integrated Power MOSFET drain Integrated Power MOSFET drain pin It provides internal bias current during start up via an integrated high voltage current source which is switched off during normal operation The device is able to handle an unclamped current during its normal operation assuring self protection against voltage surges PCB stray inductance and allowing a snubberless operation for low output power Source pin Power MOSFET source pin Primary side circuit common ground connection Voo pin power supply This pin provides two functions e li corresponds to the low voltage supply of the control part of the circuit If Vpp goes below 8V the start up current source is activated and the output power MOSFET is switched off until the Vpp voltage reaches 11V Duri
18. e in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST ST PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2006
19. e sum of the blanking time and of the propagation time of the internal current sense and comparator and represents roughly the minimum on time of the device Note that Pstgy may be affected by the efficiency of the converter at low load and must include the power drawn on the primary auxiliary voltage 11 34 Operation description VIPer20A E 5 3 12 34 As soon as the power goes below this limit the auxiliary secondary voltage starts to increase above the 13V regulation level forcing the output voltage of the transconductance amplifier to low state Vcomp lt Vcomptn This situation leads to the shutdown mode where the power switch is maintained in the Off state resulting in missing cycles and zero duty cycle As soon as Vpp gets back to the regulation level and the Vcompm threshold is reached the device operates again The above cycle repeats indefinitely providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation The equivalent switching frequency is also lower than the normal one leading to a reduced consumption on the input main supply lines This mode of operation allows the VIPer20A E to meet the new German Blue Angel Norm with less than 1W total power consumption for the system when working in stand by mode The output voltage remains regulated around the normal level with a low frequency ripple corresponding to the burst mode The amplitude of this ripple is low be
20. ed by design to 2A to 15A which gives a 12 start up duty cycle while the power dissipation at start up is approximately 0 6W for a 230Vrms input voltage This low value start up duty cycle prevents the application of stress to the output rectifiers as well as the transformer when a short circuit occurs The external capacitor Cypp on the Vpp pin must be sized according to the time needed by the converter to start up when the device starts switching This time tss depends on many parameters among which transformer design output capacitors soft start feature and compensation network implemented on the COMP pin The following formula can be used for defining the minimum capacitor needed I DDSS where Cypp gt y DDhyst Ipp is the consumption current on the Vpp pin when switching Refer to specified lpp and Ipp2 values tss is the start up time of the converter when the device begins to switch Worst case is generally at full load Vpphyst is the voltage hysteresis of the UVLO logic refer to the minimum specified value SZA viPer20A E Operation description 5 4 lt The soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network In this case the regulation loop bandwidth is rather low because of the large value of this capacitor In case a large regulation loop bandwidth is mandatory the schematics of see Figure 17 can be used It mixe
21. le VIPer20 FC00470 VIPer20 FC00480 20 34 4 VIPer20A E Electrical over stress 6 Electrical over stress 6 1 Electrical over stress ruggedness The VIPer may be submitted to electrical over stress caused by violent input voltage surges or lightning Following the Layout Considerations is sufficient to prevent catastrophic damages most of the time However in some cases the voltage surges coupled through the transformer auxiliary winding can exceed the Vpp pin absolute maximum rating voltage value Such events may trigger the Vpp internal protection circuitry which could be damaged by the strong discharge current of the Vpp bulk capacitor The simple RC filter shown in Figure 23 can be implemented to improve the application immunity to such surges Figure 23 Input voltage surges protection Auxilliary winding j C1 O Bulk capacitor a PET i viPerxxo COMP SOURCE 21 34 4 Layout VIPer20A E 7 Layout 7 1 Layout considerations Some simple rules insure a correct running of switching power supplies They may be classified into two categories Minimizing power loops The switched power current must be carefully analysed and the corresponding paths must be as small an inner loop area as possible This avoids radiated EMC noises conducted EMC noises by magnetic coupling and provides a better efficiency by elimina
22. llowing equation very similar to the one above The error amplifier frequency response is reported in for different values of a simple resistance connected on the COMP pin The unloaded transconductance error amplifier shows an internal Zcomp Of about 330KQ More complex impedance can be connected on the COMP pin to achieve different compensation level A capacitor will provide an integrator function thus eliminating the DC static error and a resistance in series leads to a flat gain at higher frequency insuring a correct phase margin This configuration is illustrated in Figure 20 As shown in Figure 19 an additional noise filtering capacitor of 2 2nF is generally needed to avoid any high frequency interference Is also possible to implement a slope compensation when working in continuous mode with duty cycle higher than 50 Figure 21 shows such a configuration Note R1 and C2 build the classical compensation network and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth 13 34 Operation description VIPer20A E 5 5 5 6 5 7 14 34 External clock synchronization The OSC pin provides a synchronisation capability when connected to an external freguency source Figure 21 shows one possible schematic to be adapted depending the specific needs If the proposed schematic is used the pulse duration must be kept at a low value 500ns is sufficient for minimizing consumption The opto
23. max 330 B min 1 5 C 0 2 13 F 20 2 G 0 2 24 4 N min 60 T max 30 4 Note All dimensoin are in mm lt 29 34 Package mechanical data VIPer20A E Figure 32 Tape shipment r 0000000 User Direction of Feed User Direction of Feed au Top No components Components No components cover tape 500mm min Empty components pockets 500mm min saled with cover tape User direction of feed Table 15 Tape dimension Tape width W 24 Tape Hole Spacing PO x 0 1 4 Component Spacing P 24 Hole Diameter D x 0 1 0 1 5 Hole Diameter D1 min 1 5 Hole Position F 0 05 11 5 Compartment Depth K max 6 5 Hole Spacing P1 0 1 2 Note All dimensions are in mm lt 30 34 VIPer20A E Figure 33 Pentawatt HV tube shipment no suffix Package mechanical data Table 16 Base Q ty Bulk Q ty Tube length 0 5 A Tube dimension Note C 0 1 All dimensions are in mm Figure 34 Dip 8 Tube shipment no suffix A 4 vA 7 4 4 B anh rz rd Table 17 Tube dimension Base Q ty 20 Bulk Q ty 1000 Tube length 0 5 532 A 8 4 B 11 2 C 0 1 0 8 Note All dimensions are in mm Ky 31 34 Order code VIPer20A E 9 32 34 Order code Table 18 Order code
24. ng this phase the internal current consumption is reduced the Vpp pin is sourcing a current of about 2mA and the COMP pin is shorted to ground After that the current source is shut down and the device tries to start up by switching again e This pin is also connected to the error amplifier in order to allow primary as well as secondary regulation configurations In case of primary regulation an internal 13V trimmed reference voltage is used to maintain Vpp at 13V For secondary regulation a voltage between 8 5V and 12 5V will be put on Vpp pin by transformer design in order to stuck the output of the transconductance amplifier to the high state The COMP pin behaves as a constant current source and can easily be connected to the output of an optocoupler Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the Vpp voltage which cannot overpass 13V The output voltage will be somewhat higher than the nominal one but still under control Compensation pin This pin provides two functions e It is the output of the error transconductance amplifier and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop Its bandwidth can be easily adjusted to the needed value with usual components value As stated above secondary regulation configurations are also implemented through the COMP pin e When the COMP voltage is going below 0 5
25. s a high performance compensation network together with a separate high value soft start capacitor Both soft start time and regulation loop bandwidth can be adjusted separately If the device is intentionally shut down by tying the COMP pin to ground the device is also performing start up cycles and the Vpp voltage is oscillating between Vppon and Vpporr This voltage can be used for supplying external functions provided that their consumption does not exceed 0 5mA see Figure 18 shows a typical application of this function with a latched shutdown Once the Shutdown signal has been activated the device remains in the Off state until the input voltage is removed Transconductance error amplifier The VIPer20A E includes a transconductance error amplifier Transconductance Gm is the change in output current Icomp versus change in input voltage Vpp Thus ol G COMP n 0Vpp The output impedance Zcomp at the output of this amplifier COMP pin can be defined as V Z _ 9 come 1 COMP 7 I E x oV O COMP m DD This last equation shows that the open loop gain Ayo can be related to Gm and Zcomp Avot Gm X Zcomp where Gm value for VIPer20A E is 1 5 mA V typically Gm is defined by specification but Zcoyp and therefore Ayo are subject to large tolerances An impedance Z can be connected between the COMP pin and ground in order to define the transfer function F of the error amplifier more accurately according to the fo
26. ting parasitic inductances especially on secondary side Using different tracks for low level and power signals Interference due to mixing of signal and power may result in instabilities and or anomalous behaviour of the device in case of violent power surge Input overvoltages output short circuits In case of VIPer these rules apply as shown on see Figure 24 Loops C1 T1 U1 C5 D2 T1 and C7 D1 T1 must be minimized _ C6 must be as close as possible to T1 Signal components C2 ISO1 C3 and C4 are using a dedicated track connected directly to the power source of the device Figure 24 Recommended layout lt e XR 5i p C e To secondary D2 d filtering and load 4 m et C5 From input diodes bridge C6 FC00500 lt 22 34 viPer20A E Package mechanical data 8 Package mechanical data In order to meet environmental requirements ST offers these devices in ECOPACK packages These packages have a Lead free second level interconnect The category of second Level Interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com 4 23 34 Package mechanical data VIPer20A E
27. tion to line changes and better stability for the voltage regulation loop Current mode topology also ensures good limitation in case there is a short circuit During the first phase the output current increases slowly following the dynamic of the regulation loop Then it reaches the maximum limitation current internally set and finally stops because the power supply on Vpp is no longer correct For specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the COMP pin An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on This function prevents anomalous or premature termination of the switching pulse in case there are current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time Stand by mode Stand by operation in nearly open load conditions automatically leads to a burst mode operation allowing voltage regulation on the secondary side The transition from normal operation to burst mode operation happens for a power Pgrgy given by Where Porgy IL STBY SW Lp is the primary inductance of the transformer Fay is the normal switching frequency Istpy is the minimum controllable current corresponding to the minimum on time that the device is able to provide in normal operation This current can be computed as ty ty Vin I STBY L tp ty is th
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