ST VIPER17 Manual(2)
Contents
1. Table 6 Power section Symbol Parameter Test condition Min Typ Max Unit I 1 mA Veg GND Vevpss Break down voltage T a25 sc re 800 V VpRAIN max rating lorr OFF state drain current Vgs GND 60 pA IDRAIN 0 2 A VEB 3 V 20 24 Q R Drain source on state Ver GND Ty 25 C DS on i resistance IbRAIN 0 2A Vep 3V 40 48 O Ver GND Tj 125 C Effective energy related _ Coss output capacitance VDRAIN 0 to 640 V 10 pF Table 7 Supply section Symbol Parameter Test condition Min Typ Max Unit Voltage VpRAIN_start Drain source start voltage 60 80 100 V VBR GND VE GND 2 3 4 mA I Start up chargi TEC art up charging curren PEER VDRAIN 120V VBR GND Vrp GND 0 4 0 6 0 8 mA Vpp 4 V after fault Vpp Operating voltage range After turn on 8 5 23 5 V Vppclamp Vpp clamp voltage Ipp 20 mA 23 5 V V Vpp start up threshold 13 14 15 V DDon i VEAIN 120 V pp Under voltage V GND Ver GND VDDof shutdown threshold RR E 7 3 Bo Y Vpp restart voltage VpnaiN 120 V VDD RESTART threshold Ver GND Veg GND b m 3 Y Current I Operating supply current Veg GND Fswy 0KkHz 0 9 mA DDO not switching Ver GND Vpp 10 V i Operating supply current VpRain 120 V loo switching Fsw 60 kHz TB janie Fsw 115 kHz MIB Operating supply current ID FAULT with protection tripping LN2. Table 8 Controller section continued Ty 25 to 125 C Vpp 14 V unless otherwise specified Symbol Parameter Test condition Min Typ Max Unit Over current protection 2 9 OCP Second over current IDMAX threshold 0 6 A Over voltage protection Over voltage protection Vove threshold Ef 3 xcu Over voltage protection TSTROBE Strobe time es m Brown out protection Vanth Brown out threshold 0 41 0 45 0 49 V Voltage hysteresis above VBR Hyst y SR 50 mV BRth Voltage falling IBR Hyst Current hysteresis 7 10 uA VBR Operating range 0 15 2 V Vpis Brown out disable voltage 50 150 mV Thermal shutdown Tam Thermal shutdown 150 170 C temperature Thermal shutdown B Tuvsr hysteresis m j 9 31 Electrical data VIPER17 10 31 Figure 4 Minimum turn on time test circuit VDD 16V BR CONTROL CONT FB A Figure 5 Brown out threshold test circuits Brasi 16V CONTROL Figure 6 OVP threshold test circuits CONTROL 7 VIPER17 Typical electrical characteristics 5 Typical electrical characteristics Figure 7 Current limit vs Ty Figure 8 Switching frequency vs T IDLIM IDLIM 25 C 1 02 FOSG FOSC 92979 1 02 1 00 1 00 9 95 0 98 mE 0 96 094 0 94 0 92 50 00 0 00 50 00 400 00 150 00 2000 mE 30 00 100 00
3. Table 10 DIP 7 mechanical data mm Dim Typ Min Max A 5 33 Al 0 38 A2 3 30 2 92 4 95 b 0 46 0 36 0 56 b2 1 52 1 14 1 78 0 25 0 20 0 36 D 9 27 9 02 10 16 7 87 7 62 8 26 E1 6 35 6 10 7 11 e 2 54 eA 7 62 eB 10 92 L 3 30 2 92 3 81 M 6 8 2 508 N 0 50 0 40 0 60 N1 0 60 o 70 0 548 1 The leads size is comprehensive of the thickness of the leads finishing material 2 Dimensions do not include mold protrusion not to exceed 0 25 mm in total both side 3 Package outline exclusive of metal burrs dimensions 4 Datum plane H coincident with the bottom of lead where lead exits body 5 Ref POA MOTHER doc 0037880 6 Creepage distance gt 800 V 7 Creepage distance 250 V 8 Creepage distance as shown in the 664 1 CEI IEC standard VIPER17 Package mechanical data Figure 33 Package dimensions se GAUGE PLANE 0 38 notes 7 8 L 29 31 Revision history VIPER17 9 30 31 Revision history Table 11 Document revision history Date Revision Changes 14 Feb 2008 1 Initial release 19 Feb 2008 2 Updated Figure 1 on page 1 Figure 8 on page 5 VIPER17 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to
4. 19 7 8 Over Voltage Protection OVP 19 79 Abou CONT DI ig URL cue Ra ous ERN E eset BC e hee aig Re RC 21 7 10 Feed back and Over Load Protection OLP 21 7 11 Burst mode operation at no load or very light load 24 7 12 Brown out protection sc suc bises bem RUE EROR nah aed ee on OR d 25 7 13 2ndlevel over current protection and hiccup mode 27 2 31 ky VIPER17 Contents 8 Package mechanical data 28 9 Revision historV isthe usus T RCRCRCACR R D ae E a RR ON RC RU RIO es 30 3 31 Block diagram VIPER17 1 Figure 2 Block diagram Block diagram CONT BR VDD CD DRAIN Internal Supply bus Reference Voltages HV ON OSCILLATOR pias Istart up THERMAL SHUTDOWN TURN ON LOGIC OLP OVP OTP BURST MODE LOGIC Rsense GND 2 Table 2 Typical power Typical power Part number VIPER17 230 Vac 85 265 Vac Adapter 9W Open frame 12W Adapter 5W Open frame 7W 1 Typical continuous power in non ventilated enclosed adap
5. 7 7 7 8 Current mode conversion with adjustable current limit set point The device is a current mode converter the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator This voltage is compared with the one on the feedback pin through a voltage divider on cycle by cycle basis The VIPER17 has a default current limit value Ip iy that the designer can adjust according the electrical specification by the R jy resistor connected to the CONT see Figure 8 on page 11 The CONT pin has a minimum current sunk needed to activate the Ip jy adjustment without Rim or with high R iv i e 100 KO the current limit is fixed to the default value see lp iy Table 8 on page 8 Over Voltage Protection OVP The device can monitor the converter output voltage This operation is done by CONT pin during power MOSFET OFF time when the voltage generated by the auxiliary winding tracks converter s output voltage through turn ratio Naux See Figure 26 Nsec In order to perform the output voltage monitor the CONT pin has to be connected to the aux winding through a resistor divider made up by Riu and Rovp see Figure 21 and Figure 27 If the voltage applied to the CONT pin exceeds the internal 3 V reference for four consecutive times the controller recognizes an over voltage condition This special feature uses an internal counter that is to reduce sensitivity to noise and prevent t
6. Table 1 Device summary Order codes Package Packaging VIPER17LN DIP 7 Tube VIPER17HN February 2008 Rev 2 1 31 www st com Contents VIPER17 Contents 1 Block diagram eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee 4 2 Typical POWE iude Rs dox sprue a aa RT s O Rd ao a 4 3 Pin settings aaa yam wk eR E ndadani Ya E732 80A 7 64809 e RR 5 3 1 Connection diagram isis ro se RR nee ee in ee ne RE P EERECRS 5 3 2 Pin description ssr AE ACC RCB goh NCCA 9 rao ge gearra hi ek Bh AN eo Ah ex en 5 4 Electrical Gala 5433 ai aca ka m seen eect aca Rc ERROR LR RC eR a aca ara 6 4 1 Maximum ratings see eeeee ee x EE ee ee ee ee eee ede aid 6 4 2 Thermal data a5 uu ertesi strn snt E E E Race dp EP BAR sare 6 4 3 Electrical characteristics tuer EROR HE RE R e Ba ROTER ox 7 5 Typical electrical characteristics 11 6 Typical circuit sise sinc iss a a waasaxwutaeasrradbe eR aa pausa d a 14 7 Operation descriptions 15 7 1 Power section and gate driver 15 7 2 High voltage startup generator 15 7 3 Power up and soft startup 16 7 4 Power down operation da ER RUE RERO CROR EUROPA LO nee ie einne 18 7 5 Auto restart operation susc ea pr RR IR eu EC RR nine ee EORR 18 76 Oscillator ER 18 7 7 Current mode conversion with adjustable current limit set point
7. VrBIi _ p FBlin ToLP delay Crp x 3nA In the Figure 28 the capacitor connected to FB pin Crg is used as part of the circuit to compensate the feedback loop but also as element to delay the OLP shut down owing to the time needed to charge the capacitor see equation 5 After the start up time 8 5 ms typ value during which the feedback voltage is fixed at Veg lin the output capacitor could not be at its nominal value and the controller interpreter this situation as an over load condition In this case the OLP delay helps to avoid an incorrect device shut down during the start up Owing to the above considerations the OLP delay time must be long enough to by pass the initial output voltage transient and check the over load condition only when the output voltage is in steady state The output transient time depends from the value of the output capacitor and from the load When the value of the Crg capacitor calculated for the loop stability is too low and cannot ensure enough OLP delay an alternative compensation network can be used and it is showed in Figure 29 on page 24 Using this alternative compensation network two poles fpeg fppg and one zero fzpg are introduced by the capacitors Cfg and Crp and the resistor Rep The capacitor Crp introduces a pole fpeg at higher frequency than fzp and fppg This pole is usually used to compensate the high frequency zero due to the ESR Equivalent Series Resistor of the o
8. Operating supply current _ Ipp OFF with Vpp Vpp oFr Vpp 27M 270 uA 7 31 Electrical data VIPER17 Table 8 Controller section Ty 25 to 125 C Vpp 14 V unless otherwise specified Symbol Parameter Test condition Min Typ Max Unit Feedback pin Over load shut down VFB olp threshold 4 7 4 8 5 2 V VEB in Linear dynamics upper limit 3 2 3 3 3 4 V VFB bm Burst mode threshold Voltage falling 0 5 V VrB pm nys Burst mode hysteresis Voltage rising 50 mV Veg 0 3 V 150 200 280 uA leg Feedback sourced current 3 3 V lt VEB lt 4 8 V 3 uA RrEB DYN Dynamic resistance Vrp lt 3 3V 14 19 kQ Hep AVreg Alp 4 9 V A CONT pin VCONT Low level clamp voltage Icont 100 uA 0 5 V Current limitation Veg 4 V Ipiim Max drain current limitation lconr 10 HA 0 38 0 4 0 42 A Ty 25 C tss Soft start time 8 5 ms TON MIN Minimum turn ON time 400 ns td Propagation delay 150 ns li Ep Leading edge blanking 300 ns Peak drain current during i Ip BM burst mode Vrp 0 6 V 90 mA Oscillator section VIPER17L Vpp operating 54 60 66 kHz Fosc voltage range VIPER17H Vrg 2 1 V 103 115 127 kHz VIPER17L 4 kHz FD Modulation depth VIPER17H 8 kHz FM Modulation frequency 250 Hz Dax Maximum duty cycle 70 80 So 8 31 VIPER17 Electrical data 4
9. restarts as the voltage exceeds 0 45 V plus hysteresis voltage It can be connected to ground when not used 78 DRAIN High voltage drain pin The built in high voltage switched start up bias current is drawn from this pin too 5 31 Electrical data VIPER17 4 Electrical data 4 1 Maximum ratings Table 4 Absolute maximum ratings Symbol Pin Parameter Value Unit VDRAIN 7 8 Drain to source ground voltage 800 V Eav 7 8 Repetitive avalanche energy limited by Tj 150 C 2 mJ IAR 7 8 Repetitive avalanche current limited by Ty 150 C 0 6 A IDRAIN 7 8 Pulse drain current 0 7 A VCONT 3 Control input pin voltage with Iconr 1 mA Self limited V VfB 4 Feedback voltage 0 3 to 5 5 V Ver 5 Brown out input pin voltage 2 V Vpp 2 Supply voltage Ipp 25 mA Self limited V Pror Power dissipation at TA lt 50 C 1 W Ty Operating junction temperature range 40 to 150 C TsrG Storage temperature 55 to 150 C 4 2 Thermal data Table 5 Thermal data Parameter Max value Unit Rap Thermal resistance junction pin 40 C W 90 C W Ringa Thermal resistance junction ambient am ON 1 When mounted on a standard single side FR4 board whit 200 mm 0 31 sq in Of Cu 35 m thick 7 6 31 VIPER17 Electrical data 4 3 Electrical characteristics Ty 25 to 125 C Vip 14 V unless otherwise specified
10. 1350 00 TJ C TJ C Figure 9 Drain start voltage vs Tj Figure 10 HFB vs Ty VSTART VSTART 25 C HFB HFB 25 C 1 02 1 20 1 01 1 10 1 00 1 00 1 00 0 90 0 99 0 80 0 98 0 70 50 00 0 00 50 00 100 00 150 00 50 0 50 100 150 TJ C TJ C Figure 11 Brown out threshold vs Ty Figure 12 Brown out hysteresis vs T VBRth VBRth 25 C VBR_Hyst VBR_Hyst 25 C 1 05 1 20 1 03 1 12 1 01 1 04 0 99 Eee 0 96 0 97 0 88 0 95 T T 0 80 50 00 0 00 50 00 100 00 150 00 50 00 0 00 50 00 400 00 150 00 TJ C TJ C ky 11 31 Typical electrical characteristics VIPER17 12 31 Figure 13 Brown out hysteresis current vs Ty Figure 14 Operating supply current no switching vs Ty IBR Hyst IBR Hyst 25 C 1 10 1 06 1 02 0 98 0 94 0 90 i 50 00 0 00 50 00 100 00 150 00 TJ C IDDO IDDO 25 C 1 01 0 99 0 96 0 94 T T T 50 00 0 00 50 00 100 00 150 00 TJ C Figure 15 Operating supply current switching vs Ty Figure 16 current limit vs Rj jw IDD1 IDD1 25 C 1 06 1 04 1 01 0 99 0 96 0 94 t 50 00 0 00 50 00 100 00 150 00 TJ C IDLIM IDLIM 100 kOhm 0 20 40 60 80 100 RLIM kOhm Figure 17 Power MOSFET on resistance vs Ty Figure 18 Power MOSFET break down voltag
11. DABS BAS ER ARAM MACE AY VIPER17 Off line high voltage converters Features 800 V avalanche rugged power section m PWM operation with frequency jittering for low EMI m Operating frequency 60 kHz for L type 115 kHz for H type m Standby power 50 mW at 265 Vac Limiting current with adjustable set point m Adjustable and accurate over voltage protection m On board soft start m Safe auto restart after a fault condition Hysteretic thermal shutdown Application m Adapters for PDA camcorders shavers cellular phones videogames m Auxiliary power supply for LCD PDP TV monitors Audio systems computer industrial m SMPS for set top boxes DVD players and recorders white goods Description The device is an off line converter with an 800 V rugged power section a PWM control two levels of over current protection over voltage and overload protections hysteretic thermal protection soft start and safe auto restart after any fault condition removal Burst mode operation and device very low consumption helps to meet the standby energy saving regulations Advance frequency jittering reduces EMI filter cost Brown out function is embedded into the high voltage start up Figure 1 Typical topology 0 o DC input high voltage wide range DC Output voltage
12. MMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2008 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 31 31 4
13. NCE FEEDBACK LOOP FAILURE 20 31 ky VIPER17 Operation descriptions 7 9 About CONT pin Referring to the Figure 27 through the CONT PIN the below features can be implemented 1 Current Limit set point 2 Over Voltage Protection on the converter output voltage The Table 9 on page 21 referring to the Figure 27 lists the external resistance combinations needed to activate one or plus of the CONT pin functions Figure 27 CONT pin configuration a OCP Comparator Curr Lim E BLOCK To PWM Logic d OVP DETECTION LOGIC From SenseFET gt To OVP Protection Table 9 CONT pin configurations Function component Rum Rovp Daux Ipiim reduction See Figure 8 No No OVP gt 80 KQ See Equation 4 Yes Iplim reduction OVP See Figure 8 See Equation 4 Yes 1 Ry have to be fixed before RFF and Royp 7 10 Feed back and Over Load Protection OLP The VIPER17 is a current mode converter the feedback pin controls the PWM operation controls the burst mode and actives the overload protection of the device Figure 28 on page 23 and Figure 29 show the internal current mode structure With the feedback pin voltage between Veg pm and Veg jin respectively 0 5 V and 3 3 V typical values the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator This voltage is compared with the one on the feedback pin through a voltage divider on cycle b
14. Vpprestart threshold 4 5 V typical This means that the HV start up current generator restarts the Vpp capacitor charging only when the Vpp voltage drops below Vpprestart The scenario above described is for instance a power down because of a fault condition After a fault condition the charging current is 0 6 mA typ instead of the 3 mA typ of a normal start up converter phase This feature together with the low Vpprestart threshold 4 5 V ensures that after a fault the restart attempts of the IC has a very long repetition rate and the converter works safely with extremely low power throughput The Figure 25 shows the IC behavioral after a short circuit event Figure 25 Timing diagram behavior after short circuit Vo dem Short circuit occurs here Vopos VppOFF Voprest i i M UE VDS P Ter m p i RO lt 0 03Trep Ipp CH H 0 6 mA i rt ia FB Pin i i H i ZEN 48V i i 33V i Oscillator The switching frequency is internally fixed to 60 kHz or 115 kHz In both case the switching frequency is modulated by approximately 4 kHz 60 kHz version or x8 kHz 115 kHz version at 250 Hz typical rate so that the resulting spread spectrum action distributes the energy of each harmonic of the switching frequency over a number of side band harmonics having the same energy on the whole but smaller amplitudes y VIPER17 Operation descriptions
15. e vs Ty RDSON RDSON 25 C 2 5 2 1 17 1 3 0 9 0 5 50 00 0 00 50 00 100 00 150 00 TJ C VBVDSS VBVDSS 25 C 1 10 1 06 1 02 0 98 0 94 0 90 T T T 50 00 0 00 50 00 100 00 150 00 TJ C y VIPER17 Typical electrical characteristics Figure 19 Thermal shutdown V DD RESTART ky 13 31 Typical circuit VIPER17 6 14 31 Typical circuit Figure 20 Flyback application basic D3 Vout GND Figure 21 Flyback application Vout C1 C3 VIPER17 Operation descriptions 7 7 1 7 2 Operation descriptions VIPER17 is a high performance low voltage PWM controller chip with an 800 V avalanche rugged Power section The controller includes the oscillator with jittering feature the start up circuits with soft start feature the PWM logic the current limit circuit with adjustable set point the second over current circuit the burst mode management the brown out circuit the UVLO circuit the auto restart circuit and the thermal protection circuit The current limit set point is set by the CONT pin The burst mode operation guaranties high performance in the stand by mode and helps in the energy saving norm accomplishment All the fault
16. gain if the voltage on feedback pin exceeds Vrprppm The voltage on PWM comparator non inverting internal input connected to feedback pin through a resistive voltage divider is lower clamped to a certain value leading to a minimum value of 90 mA typ for the drain peak current When the load decrease the feedback loop reacts lowering the feedback pin voltage As the voltage goes 50mV below Vegpn MOSFET stops switching After the MOSFET stops as a result of the feedback reaction to the energy delivery stop the feedback pin voltage increases and exceeding Vegpm threshold MOSFET the power device start switching again Figure 30 shows this behavior called burst mode Systems alternates period of time where power MOSFET is switching to period of time where power MOSFET is not switching The power delivered to output during switching periods exceeds the load power demands the excess of power is balanced from not switching period where no power is processed The advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency up to some hundred of hertz minimizing all frequency related losses VIPER17 Operation descriptions Figure 30 Burst mode timing diagram light load management FB VFBBM v hyster I ps Le Normal mode Burst mode LL E i t 7 12 Brown out protection Brown out protection is a not latched shutdown function activated when a conditio
17. he latch from being erroneously activated see Figure 26 on page 20 The counter is reset every time the OVP signal is not triggered in one oscillator cycle Referring to the Figure 21 the resistors divider ratio koyp will be given by Equation 2 Vovp Kovp Naux Na ourovP Vosec Voaux SEC Equation 3 k Rum ove Riim Rove 19 31 Operation descriptions VIPER17 Where Vovr is the OVP threshold see Table 8 on page 8 Vout ovp is the converter output voltage value to activate the OVP set by designer Naux is the auxiliary winding turns Nscc is the secondary winding turns Vpsgc is the secondary diode forward voltage Vpaux is the Auxiliary diode forward voltage Royp together R jy make the Output Voltage divider Than fixed R jy according to the desired Ip y the Royp can be calculating by Equation 4 1 kovyp Kovp Rove Rum X The resistor values will be such that the current sourced and sunk by the CONT pin be within the rated capability of the internal clamp Figure 26 OVP timing diagram VAUX N o JV CONT i i i pin 4 i i N F in 1 p i t pA I ALL FA V nV jM n E d LH E ii T t ii ii E ii E T ii STROBE Fu HS n E i i t i L il i i i i t COUNTER i i i i i sega f pop COUNTER i i i i i i i i T i STATUS 0 0 o l 021 422 220 0 t ool 1 422 228 go4 FAULT i T t i t NORMAL OPERATION TEMPORARYDISTURBA
18. make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECO
19. n of mains under voltage is detected The Brown out comparator is internally referenced to Vppip 0 45 V typ value and disables the PWM if the voltage applied at the BR pin is below this internal reference Under this condition the power MOSFET is turned off Until the Brown out condition is present the VDD voltage continuously oscillates between the Vppon and the UVLO thresholds as shown in the timing diagram of Figure 31 on page 26 A voltage hysteresis is present to improve the noise immunity The switching operation is restarted as the voltage on the pin is above the reference plus the before said voltage hysteresis See Figure 31 The Brown out comparator is provided also with a current hysteresis IBrhyst With this approach is possible to set the VIN threshold and V nog thresholds separately by properly choosing the resistors of the divider connect to the BR pin 25 31 Operation descriptions VIPER17 Figure 31 Brown out protection BR external setting and timing diagram HV Input bus VinON VinoFF BR HV Input bus Disable VDS Vout Fixed the Vinon and the Vins levels with reference to Figure 31 the following relationships can be established for the calculation of the resistors Ry and R Equation 9 R VBRHYST d Vinon ViNott i VBRHYST x Ver IBRHYST Mot Ver IBRHYST Equation 10 R ViNon B Vinoft VBRHYST x Ri y Nen Nof BRHYST lennv V ST BRHYST BRHYST For a p
20. protections are built in Auto Restart Mode with very low repetition rate to prevent IC s over heating Power section and gate driver The Power section is implemented with an avalanche ruggedness N channel MOSFET which guarantees safe operation within the specified energy rating as well as high dv dt capability The Power section has a BVpgg of 800 V min and a typical Rpsxon of 20 O at 25 C The integrated SenseFET structure allows a virtually loss less current sensing The gate driver is designed to supply a controlled gate current during both turn on and turn off in order to minimize common mode EMI Under UVLO conditions an internal pull down circuit holds the gate low in order to ensure that the Power section cannot be turned on accidentally High voltage startup generator The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor voltage is higher than Vprain start Threshold 80 Vpc typically When the HV current generator is ON the Ipp ch current 3 mA typical value is delivered to the capacitor on the Vpp pin In case of Auto Restart mode after a fault event the Ipp cn Current is reduced to 0 6 mA typ in order to have a slow duty cycle during the restart phase 15 31 Operation descriptions VIPER17 7 3 16 31 Power up and soft start up If the input voltage rises up till the device start level VpRain start the Vpp voltage begins to grow due to the Ipp eh c
21. rent 1 mA Ipp rauLT Ipp orr Ts CH FAUDT Nonna Mim am ea ee ge 1 mA VIPER17 Operation descriptions Figure 23 Timing diagram normal power up and power down sequences Vin regulation is lost here VDDon VDD or Vp D restart VpRAIN Ipp cH 3mA Normal t e Power on 3e 35 operation 71 Power off Figure 24 Soft start timing diagram IDRAIN lt s IDLIM VFB VFB OLP VFB lin 17 31 Operation descriptions VIPER17 7 4 7 5 7 6 18 31 Power down operation At converter power down the system loses regulation as soon as the input voltage is so low that the peak current limitation is reached The Vpp voltage drops and when it falls below the Vppog threshold 8 V typical the power MOSFET is switched OFF the energy transfers to the IC interrupted and consequently the Vpp voltages decreases Figure 23 on page 17 Later if the Vij is lower than Vprain start 80 V typical the start up sequence is inhibited and the power down completed This feature is useful to prevent converter s restart attempts and ensures monotonic output voltage decay during the system power down Auto restart operation If after a converter power down the Viy is higher than Vprain_start the start up sequence is not inhibited and will be activated only when the Vpp voltage drops down the
22. roper operation of this function ViN on must be less than the peak voltage at minimum mains and Viy or less than the minimum voltage on the input bulk capacitor at minimum mains and maximum load The BR pin is a high impedance input connected to high value resistors thus it is prone to pick up noise which might alter the OFF threshold when the converter operates or gives origin to undesired switch off of the device during ESD tests It is possible to bypass the pin to ground with a small film capacitor e g 1 10 nF to prevent any malfunctioning of this kind If the Brown out function is not used the pin has to be connected to GND 26 31 ky VIPER17 Operation descriptions 7 13 2d level over current protection and hiccup mode The VIPER17 is protected against short circuit of the secondary rectifier short circuit on the secondary winding or a hard saturation of fly back transformer Such as anomalous condition is invoked when the drain current exceed 0 6 A typical To distinguish a real malfunction from a disturbance e g induced during ESD tests a warning state is entered after the first signal trip If in the subsequent switching cycle the signal is not tripped a temporary disturbance is assumed and the protection logic will be reset in its idle state otherwise if the 2 OCP threshold is exceeded for two consecutive switching cycles a real malfunction is assumed and the power MOSFET is turned OFF The shutdown condi
23. ter measured at 50 C ambient 2 Maximum practical continuous power in an open frame design at 50 C ambient with adequate heat sinking 4 31 7 VIPER17 Pin settings 3 3 1 3 2 Pin settings Connection diagram Figure 3 Connection diagram top view GND DRAIN VDD DRAIN CONT FB BR Pin description Table 3 Pin description N Name Function 1 GND This pin represents the device ground and the source of the power section Supply voltage of the control section This pin also provides the charging VDD current of the external capacitor during start up time Control pin The following functions can be selected 1 current limit set point adjustment The internal set default value of the cycle by cycle current limit can be reduced by connecting to ground an external 3 CONT resistor 2 output voltage monitoring A voltage exceeding 3V shuts the IC down reducing the device consumption This function is strobed and digitally filtered for high noise immunity Control input for duty cycle control Internal current generator provides bias current for loop regulation A voltage below 0 5 V activates the burst mode operation A level close to 3 3 V means that we are approaching the cycle by cycle over current set point Brownout protection input with hysteresis A voltage below 0 45 V shuts down not latch the device and lowers the power consumption Device operation
24. tion is latched as long as the device is supplied While it is disabled no energy is transferred from the auxiliary winding hence the voltage on the Vpp capacitor decays till the Vpp under voltage threshold Vppor which clears the latch The start up HV current generator is still off until Vpp voltage goes below its restart voltage Vppresr After this condition the Vpp capacitor is charged again by 600 mA current and the converter switching restart if the Vppon occurs If the fault condition is not removed the device enters in auto restart mode This behavioral results in a low frequency intermittent operation Hiccup mode operation with very low stress on the power circuit See the timing diagram of Figure 32 Figure 32 Hiccup mode OCP timing diagram Von Secondar i i ee y diode is shorted here 27 31 Package mechanical data VIPER17 8 28 31 Package mechanical data In order to meet environmental requirements ST offers these devices in ECOPACK packages These packages have a lead free second level interconnect The category of second Level Interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com
25. urrent see Table 6 on page 7 coming from the internal high voltage start up circuit If the Vpp voltage reaches Vppon threshold 14 V the power MOSFET starts switching and the HV current generator is turned OFF See Figure 23 on page 17 The IC is powered by the energy stored in the capacitor on the VDD Pin Cypp until when the self supply circuit typically an auxiliary winding of the transformer and a steering diode develops a voltage high enough to sustain the operation Cypp capacitor must be sized enough to avoid fast discharge and keep the needed voltage value higher than Vpp rr threshold In fact a too low capacitance value could terminate the switching operation before the controller receives any energy from the auxiliary winding The following formula can be used for the Vpp capacitor calculation Equation 1 Ippch tssaux Cypp VDD VpDon Vppott The tssaux is the time needed for the steady state of the auxiliary voltage This time is estimated by applicator according to the output stage configurations transformer output capacitances etc During the converter start up time the drain current limitation is progressively increased to the maximum value In this way the stress on the secondary diode is considerably reduced It also helps to prevent transformer saturation The soft start time lasts 8 5 ms and the feature is implemented for every attempt of start up converter or after a fault Figure 22 Start up Ipp cur
26. utput capacitance of the fly back converter The mathematical expressions of these poles and zero frequency considering the scheme in Figure 29 are reported by the equations below Equation 6 4 2 7 Cregi Res tra VIPER17 Operation descriptions Equation 7 Reson Res bre 2 n Cgg Resipyw Peg Equation 8 1 ret Cr Bart 2 1 Cr Res Reson The Rrgpyny is the dynamic resistance seen by the FB pin and reported on Figure 4 on page 10 The Crp capacitor fixes the OLP delay and usually Ces results much higher than Crp The equation 5 can be still used to calculate the OLP delay time but Cfg has to be considered instead of Crp Using the alternative compensation network the designer can satisfy in all case the loop stability and the enough OLP delay time alike Figure 28 FB pin configuration From sense FET PWM To PWM Logic PWM CONTROL BURST MODE BURST MODE LOGIC REFERENCES OLP comparator To disable logic ky 23 31 Operation descriptions VIPER17 7 11 24 31 Figure 29 FB pin configuration From sense FET PWM To PWM Logic PWM CONTROL BURST MODE BURST MODE LOGIC REFERENCES OLP comparator To disable logic Burst mode operation at no load or very light load When the voltage on feedback pin falls down 50 mV below the burst mode threshold Vegpm power MOSFET is not more allowed to be switched on It can be switched on a
27. y cycle basis When these two voltages are equal the PWM logic orders the switch off of the power MOSFET The drain current is always limited to Ip jy value In case of overload the feedback pin increases in reaction to this event and when it goes higher than Veg jin the drain current is limited or to the default Ip iy value or the one 21 31 Operation descriptions VIPER17 22 31 imposed through a resistor at the CONT pin using the R jy see Figure 8 on page 11 the PWM comparator is disabled At the same time an internal current generator starts to charge the feedback capacitor Crp and when the feedback voltage reaches the Vrg ojp threshold the converter is turned off and the start up phase is activated with reduced value of Icharge to 0 6 mA During the first start up phase of the converter after the soft start up time typical value is 8 5 ms the output voltage could force the feedback pin voltage to rise up to the Veg olp threshold that switches off the converter itself To avoid this event the appropriate feedback network has to be selected according to the output load More the network feedback fixes the compensation loop stability The Figure 28 on page 23 and Figure 29 show the two different feedback networks The time from the over load detection VFB Vrg ii to the device shutdown VFB Veg oi can be calculating by Cpg value see Figure 28 on page 23 and Figure 29 using the formula Equation 5 VeBolp
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ST VIPER17 Manual(2)