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TEXAS INSTRUMENTS TMS320VC5421 DATA SHEET(1)(1)

1. 4 D E Buses and Control Signa 54X cLEAD Core B o of wo 3 B 3 2 2 JO jw MBus 32K RAM 32K RAM Dual Access Program Data Single Access Data Pbus MBus 4 TI Bus RHEA Bus MBus Host Access Bus RHEA bus DSP Subsystem B 16 Figure 1 Functional Block Diagram 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 memory Each 5421 DSP subsystem maintains the peripheral register memory map and interrupt location priorities of the standard 5420 Figure 2 shows the size of the required memory blocks and their link map within the program and data space of the core The total on chip memory for the 5421 devices is 256K word data program Hex Data Hex Program Page 0 Hex Program Page 1 Program Page 2 Hex Program Page 3 Hex Program Pagen 00 0000 Memory 00 0000 01 0000 03 0000 On 0000 Mapped Reserved Reserved Reserved Reserved Reserved Registers 00 005 g 00 005F 03 005 On 005F 00 0060 00 0060 03 0060 On 0060 On Chip DARAM A B 32K Words Prog Data 00 7FFF 00 8000 On Chip SARAM A B 32K Words Data Only DROM 1 External DROM 0 00 FFFF On Chip DARAM A B 32K Words Pr
2. 0 5 V to 4 0 V Supply voltage core range CVppt 0 5 V to 2 4 V Supply voltage analog PLL AVppt 0 5 V to 2 4 V Input voltage range 0 5 V to DVpp 0 5 V Output voltage range Vo 0 5 V to DVpp 0 5 V Operating case temperature range 0 C to 85 C Storage temperature range Tstg 4 65 C to 150 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability t All voltage values are with respect to Vgs recommended operating conditions DVpp Device supply voltage I O 3 0 3 3 CVDD Device supply voltage core 1 71 1 80 AVDD Device supply voltage PLL 1 71 1 80 Vss Supply voltage GND Schmitt triggered inputs VIH High level input voltage I O DVpp 3 3 0 3V All other input Schmitt triggered inputs VIL Low level input voltage DVpp 3 3 0 3V All other inputs loH High level output current loL Low leve
3. ICONE td CLKH A lt gt ta CLKL A td CLKL D W TT th D MSH M tsu D MSH lt td CLKL MSL lt 1 tsu AW gt td CLKL MSH MSTRB td CLKH RWL gt td CLKH RWH lt tw sL MS gt gt td RWL MSTRBL R W PS DS Figure 25 Memory Write MSTRB 0 35 TEXAS INSTRUMENTS 58 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 ready timing for externally generated wait states timing requirements for externally generated wait states H 0 5 see Figure 26 and Figure 27 IN UNT tsu RDY Setup time READY before CLKOUT low th BDY Hold time READY after CLKOUT low __ 5 i RDYMSTRB Valid time READY after MSTRB low hnRDY MSTRB Hold time READY after MSTRB t The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles To generate wait states by READY at least two software wait states must be programmed READY is not sampled until the completion of the internal software wait states t These timings are included for reference only The critical timings for READY are those referenced to CLKOUT tsu RDY 4 gt 4 9 th RDY READY d v tv RDY MSTR
4. see Figure 46 and Figure 53 5 UNIT tsu HBV DSL Setup time HAD valid before DS falling edgett th DSL HBV Hold time HAD valid after DS falling edgett n tsu HBV HSL Setup time HAD valid before HAS falling edget n tsu HAV DSH Setup time address valid before DS rising edge nonmultiplexed write 2 o A ite tsu HAV DSL Setup time address valid before DS falling edge nonmultiplexed mode 4H tsu HSL DSL Setup time HAS low before DS falling edget th HSL DSL Hold time HAS low after DS falling edget tw DSL Pulse duration DS low tw DSH Pulse duration DS hight Nonmultiplexed or multiplexed mode Reads no increment with no DMA activity Writes Cycle time DS rising edge to next DS Nonmultiplexed or multiplexed mode Reads rising edget increment with 16 bit DMA activity Writes Nonmultiplexed or multiplexed mode Reads increment with 32 bit DMA activity Writes c DSH DSH Multiplexed autoincrement with no DMA Cycle time DS rising edge to next DS activity rising edget Multiplexed autoincrement with 16 bit DMA In autoincrement mode WRITE activity timings are the same as READ Multiplexed autoincrement with 32 bit DMA timings activity Cycle time DS rising edge to next DS rising edge writes to DSPINT and HINT th DSH HAV Hold time address valid after DS rising edge nonmultiplexed mode o z3 gt 2 2 5 5 5 5 5 5 5 5 o
5. BFSR ext th BCKRL BDRV tsu BDRV BCKR RDATDLY 00b n 2 n 3 n 4 tsu BDRV BCKRL th BCKRL BDRV RDATDLY 011 b 2 3 i 2 EN 1 th BCKRL BDRV RDATDLY 10b e Figure 39 McBSP Receive Timings h tc BCKRX h tw BCKRXH tw BCKRXL Z lt N Ny td BCKXH BFXV td BCKXH BFXV t BCKRX BFSX int th BCKXL BFXH BFSX ext lt td BFXH BDXV ten BDFXH BDX td BCKXH BDXV reel XDATDLY 00b Bito n 4 M F td BCKXH BDXV ten BCKXH BDX BDX XDATDLY 01b C Bto RY Bit 1 n 3 tdis BCKXH BDXAZ td BCKXH BDXV ten BCKXH BDX 10b lt XDATDLY 10b _____ 000 Bit 1 n 2 Figure 40 McBSP Transmit Timings 35 TEXAS INSTRUMENTS 72 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 multichannel buffered serial port timing continued timing requirements for McBSP general purpose I O see Figure 41 IN MAX UNIT tsu BGPIO COH Setup time BGPIOx input mode before CLKOUT hight n th COH BGPIO Hold time BGPIOx input mode after CLKOUT hight BGPIOx refers to BCLKRx BFSRx BDRx BCLKXx or BFSXx when configured as a general purpose input switching
6. gt 6 tdis BFXH BDXHZ gt d BFXL BDXV tdis BCKXH BDXHZ le td BCKXL BDXV Bio C Bin n X n3 na X tsu BDRV BCKXH f th BCKXH BDRV BDR Bin 2 X n X n X Figure 44 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 1 TEXAS INSTRUMENTS 76 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 multichannel buffered serial port timing continued timing requirements for McBSP as SPI master or slave H 0 5t o CLKSTP 110 CLKXP 11 see Figure 45 MASTER SLAVE UNIT tsu BDRV BCKXL Setup time BDR valid before BCLKX low 2 12 th BCKXL BDRV Hold time BDR valid after BCLKX low 6 12H Ic BCKX Cycle time BCLKX t For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 switching characteristics for McBSP as SPI master or slave 0 5 CLKSTP 11b CLKXP 11 see Figure 45 MASTER SLAVE th BCKXH BFXL Hold time BFSX low after BCLKX high D 5 D 5 td BEXL BCKXL Delay time BFSX low to BCLKX low T 5 T 5 m td BCKXH BDXV Delay time BCLKX high to valid 6H 4 10H 19 Disable time BDX high impedance following last data bit from BCLKX tdis BCKXH BDXHZ high P 6H 4 10H 17 td BFXL BDXV Delay time BFSX low to BDX valid C 2 6 10 4H 4 8H 17 T For all SPI slave modes CLKG is program
7. FIAN YN ora E 200 MIPS Dual Core DSP Consisting of Two Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16 Bit Data Memory Buses and One Program Bus 40 Bit Arithmetic Logic Unit ALU Including a 40 Bit Barrel Shifter and Two 40 Bit Accumulators Per Core Each Core Has a 17 Bit x 17 Bit Parallel Multiplier Coupled to a 40 Bit Adder for Non Pipelined Single Cycle Multiply Accumulate MAC Operations Each Core Has a Compare Select and Store Unit CSSU for the Add Compare Selection of the Viterbi Operator Each Core Has an Exponent Encoder to Compute an Exponent Value of a 40 Bit Accumulator Value in a Single Cycle Each Core Has Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units ARAUs 16 Bit Data Bus With Data Bus Holder Feature 512K Word x 16 Bit Extended Program Address Space Total of 256K Word x 16 Bit Dual and Single Access On Chip RAM 128K Word x 16 Bit Shared Memory Single Instruction Repeat and Block Repeat Operations Instructions With 32 Bit Long Word Operands Instructions With 2 or 3 Operand Reads Fast Return From Interrupts Arithmetic Instructions With Parallel Store and Parallel Load description TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 Conditional Store Instructions Output Control of CLKOUT Output Control of TOUT Power Consumption Conirol With IDLE1 IDLE2 and IDLES Instruct
8. 5 5098 DECEMBER 1999 externally generated wait states timing continued cum NO N NZ NZ XZ NZ th RDY gt lt gt tsu RDY READY lt p tv RDY IOSTRB f th RDY IOSTRB PJ IOSTRB N 4 Wait States K Generated Internally Wait State Generated by READY Figure 31 Port Write With Externally Generated Wait States 64 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 reset BIO interrupt and XIO timings timing requirements for reset BIO interrupt and XIO H 0 5 tc co see Figure 32 Figure 33 and Figure 34 Runs Reime Py a masma BO afer GOUT lw E Hosime NTH Nae KOT ew uxo XO ater GKOUTIgw I 9 tw INTH A Pulse duration INTn NMI high asynchronous t whi Pus duran NTR wr tsu XIO Setup time XIO before CLKOUT lowt T The external interrupts INTO INT1 NMI are synchronized to the core CPU by way of a two flip flop synchronizer which samples these inputs with consecutive falling edges of CLKOUT The input to the interrupt pins is required to represent a 1 0 0 sequence at the timing that is corresponding to a three CLKOUT sampling sequence t f the PLL mode is selected then at power on
9. 5421 device Alternately the PLL circuit can be used PLL mode to generate the device clock by multiplying the reference clock frequency by a scale factor allowing use of a clock source with a lower frequency than that of the CPU The PLL is an adaptive circuit that once synchronized locks onto and tracks an input clock signal When the PLL is initially started it enters a transitional mode during which the PLL acquires lock with the input signal Once the PLL is locked it continues to track and maintain synchronization with the input signal Then other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5421 device Only subsystem A controls the PLL Subsystem B cannot access the PLL registers The software programmable PLL features a high level of flexibility and includes a clock scaler that provides various clock multiplier ratios capability to directly enable and disable the PLL and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved Devices that have a built in software programmable PLL can be configured in one of two clock modes PLL mode The input clock CLKIN is multiplied by 1 of 31 possible ratios These ratios are achieved using the PLL circuitry DIV divider mode The input clock is divided by 2 or 4 Note that when DIV mode is used the PLL can be completely disabled in order to minimize power dissipation
10. HA 17 0 Valid Address s Valid Address ta DSL HDVTJ lt th DSH HDV R V V V V V W V V Horis gt valid Data M tyHYH HDV K td DSH HYH HRDY x N tg DSL HYL Figure 50 Nonmultiplexed Read Timings 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 83 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 16 timing continued HCS K tw DSH Pl lt te DSH DSH HDS NN K tsu HBV DSL lwDSL ym th DSL HBV HR W N N F tsu HAV DSH gt K th DSH HAV HA 17 0 Valid Address T Valid Address tsu HDV DSH lt th DSH HDV W 4 td DSH HYH MN HRDY lt ta DSL HYL Figure 51 Nonmultiplexed Write Timings 84 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR HPI16 timing continued HRDY CLKOUT td COH HTX Figure 52 HRDY and HINT Relative to CLKOUT HCS tsu DSL SELV tn DSH SELVJ ER SELA B HDS x Figure 53 SELA B Timing SPRS098 DECEMBER 1999 5 TEXAS INSTRUMENTS POST OFFI
11. The software programmable PLL is controlled using the 16 bit memory mapped address 0058h clock mode register CLKMD The CLKMD register is used to define the clock configuration of the PLL clock module Figure 19 shows the bit layout of the clock mode register and Table 14 describes the bit functions 15 12 11 10 3 2 1 0 PLLMULT PLLDIVT PLLCOUNTT PLLON OFF PLLNDIV STATUS R W R W R W R W R W R W T When in DIV mode PLLSTATUS is low PLLMUL PLLDIV PLLCOUNT and PLLON OFF are don t cares and their contents are indeterminate LEGEND R Read W Write Figure 19 Clock Mode Register CLKMD 35 TEXAS INSTRUMENTS 38 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 software programmable phase locked loop PLL continued Table 14 Clock Mode Register CLKMD Bit Functions BIT BIT 15 12 PLLMULT PLL multiplier PLLMUL defines the frequency multiplier in conjunction with PLLDIV and PLLNDIV See Table 15 PLL divider PLLDIV defines the frequency multiplier in conjunction with PLLMUL and PLLNDIV See Table 15 11 PLLDIVT PLLDIV 20 Means that an integer multiply factor is used PLLDIV 1 Means that a noninteger multiply factor is used PLL counter value PLLCOUNT specifies the number of input clock cycles in increments of16 cycles for the PLL lock timer to count before the PLL begins clocking the processor after the PLL is started The PLL counter T
12. 0 H 0 5 see Figure 28 UNIT ta AJIO Access time read data access from address valid ta ISTRBL IO Access time read data access from IOSTRB low tsu D IOR Setup time read data before CLKOUT high th D IOR Hold time read data after CLKOUT high O n th ISTRBH D R Hold time read data after IOSTRB high T Address and IS timings are included in timings referenced as address NA Z S t td CLKL A ki th A IOR gt th D IOR lt tsu D IOR lt ta AJlo th ISTRBH D R t a ISTRBL IO 7 td CLKH ISTRBH lt td CLKH ISTRBL IOSTRB N Figure 28 Parallel 1 0 Port Read IOSTRB 0 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 61 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 parallel I O interface timing continued switching characteristics over recommended operating conditions for a parallel I O port write IOSTRB 0 H 0 5 see Figure 29 RETEST tsu A IOSTRBL Setup time address valid before IOSTRB low T Address and IS timings are included in timings referenced as address lt gt tsu A IOSTRBL 7 h A IOW 1 9 ta CLKH D low 1 gt lt th D IOW PPD 15 0 td CLKH ISTSRBEjq4 td CLKH ISTRBH 4 pl le gt tsu D IOSTRBH
13. 03 8000 On Chip On Chip On Chip SARAM A B 32K Words Shared Data Only Shared 32K Words Data Only DARAM 1 DARAM 3 Data Only 32K Words 32K Words Program Program Only Only Shared 1 Shared 3 00 FFFF 00 FFFF 01 FFFF 02 FFFF 03 FFFF t DMD DMS 01 DMD DMS 00 NOTES A All local memory is available to the DMA B memory accesses by the DMA DMD DMS 10 are mapped to the core to core FIFO C In pages 00 and 02 in the range of 0020 005 only the following memory mapped registers are accessible 20 21 30 31 40 41 read only 22 23 32 33 42 43 write only Figure 13 On Chip Memory Map Relative to DMA DLAXS SLAXS 0 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 31 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 direct memory access DMA controller continued 00 0000 Page 0 Lower 32KT External 00 7FFF 00 8000 Page 0 Upper 32K External 00 FFFF 00 0000 Page 0 Lower 32KT External 00 7FFF 00 8000 Page 0 Upper 32K External 00 FFFF 01 0000 01 01 8000 01 FFFF 01 0000 01 7FFF 01 8000 01 FFFF xDMA External Program Memory 02 0000 1 Lower 32KT External 02 7FFF 02 8000 Page 1 Upper 32K External 02 FFFF Page 2 Lower 32KT External Page 2 Upper 32K External
14. CPU clock by setting CLKSM CLKGDV 1 th BCKXH BDRV switching characteristics for McBSP as SPI master or slave 0 5 CLKSTP 10b CLKXP 111 see Figure 44 MIN MAX T 5 D 5 D 5 PARAMETER Hold time BFSX low after BCLKX high Delay time BFSX low to BCLKX low l Delay time BCLKX low to BDX valid td BFXL BCKXL td BCKXL BDXV tdis BCKXH BDXHZ tdis BFXH BDXHZ td BFXL BDXV high impedance following last data bit from BCLKX D 2 D410 Disable time BDX high impedance following last data bit from BFSX high Delay time BFSX low to BDX valid 4H 4 8H 17 ns T For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 tT BCLKX period 1 CLKGDV 2H D BCLKX high pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 1 2H when CLKGDV is even 8 FSRP FSXP 1 Asa SPI master BFSX is inverted to provide active low slave enable output As a slave the active low signal input on BFSX and BFSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP 1 BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock BCLKX LSB isuBFXL BCKXb le MSB I 9 teBcKx BCLKX I th BCKXH BFXL td BFXL BCKXL 2
15. Delay time CLKOUT low to MSTRB high 1 _ 4 ns th CLKL A R Hold time address valid after CLKOUT lowt 4 ns th CLKH A R_ Hold time address valid after CLKOUT high T Address PS and DS timings are all included in timings referenced as address In the case of a memory read preceded by a memory read In the case of a memory read preceded by a memory write timing requirements for a memory read MSTRB 0 H 0 5 see Figure 24 aa M UNIT ta A M Access time read data access from address valid ta MSTRBL Access time read data access from MSTRB low wp Hoa ime read data ater CLKOUTIow __ 0 wpwerm tme read aata ater MSTAS mon fre T Address PS and DS timings are all included in timings referenced as address 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 55 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 external memory interface timing continued gt td CLKL A a th CLKL A R th A D R tsu D R 4 4 gt th D R 4 th D MSTRBH td CLKL MSL lt gt lt ta CLKL MSH ta MSTRBL d MSTRB N RW PS DS N Figure 24 Memory Read MSTRB 0 35 TEXAS INSTRUMENTS 56 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77
16. Register Bit Functions BIT BIT BIT NAME VALUE FUNCTION 0 Timer output disable Uses GPIO3 as general purpose I O TOUT Timer output enable Overrides DIR3 Timer output is driven on GPIO3 and readable in 0413 a Register bit is reserved Read 0 write has no effect GPIO pin is used as an input DIRnt 1 GPIOn pin is used as an output gt ROM is mapped out 1 ROMI is mapped in cLEAD core is selected for REQ bit DSP subsystem is tied low internally for this bit cLEAD core B is selected for XIO REQ bit DSP subsystem B is tied high internally for this bit EMIF is not available to the cLEAD core determined by the CORE SEL bit EMIF is granted to the cLEAD core determined by the CORE SEL bit EMIF is not requested for the cLEAD core indicated by the CORE SEL bit Request EMIF for the cLEAD core indicated by the CORE SEL bit GPIOn is driven with a 0 DIRn 1 GPIOn is read as 0 DIRn 0 GPIOn is driven with a 1 DIRn 1 GPIOn is read as 1 DIRn 0 Tn 3 2 1 0r0 Register bit 7 is used as ROMEN to enable and disable ROM space In XIO mode ROM enable ROMEN reflects the state of the A GPIOO and B GPIOO pins GPIODATO input to enable the applicable on chip ROM after reset Register bits 6 4 are used for XIO arbitration of external memory interface EMIF control between DSP subsystems The timer out TOUT bit is used to multiplex the output of the timer and GPIOS All GPIO pins are
17. SIGNAL PROCESSOR SPRS098 DECEMBER 1999 general purpose input output GPIO timing ra mm _____ requirements for GPIO see Figure 38 t time GPIOx input valid before CLKOUT high GPIOx configured as su GPIO COH general purpose input Hold time GPIOx input valid after CLKOUT high GPIOx configured as general purpose th GPIO COH input switching characteristics for GPIO see Figure 38 PARAMETER Delay time CLKOUT high to GPIOx output change GPIOx configured as general purpose output CLKOUT tsu GPIO COH 0 h GPIO COH td COH GPIO GPIOx Input Mode td COH GPIO GPIOx Output Mode Y Figure 38 GPIO Timings 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 69 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 multichannel buffered serial port timing timing requirements for the McBSPt Hz0 5tc co see Figure 39 and Figure 40 1 UNIT Ic BCKRX Cycle time BCLKR X BCLKR X ext tw BCKRX Pulse duration BCLKR X low or BCLKR X high BCLKRXex 6 ns 0 IBOLKRint 0 ec eames scum 01 s tsu BFRH BCKRL Setup time external high before BCLKR low tsu BDRV BCKRL Setup time BDR valid before BCLKR low 3 tsu BFXH BCKXL Setup time external BFSX hi
18. affects external CPU transfers as well as external DMA transfers When an external processor asserts the HOLD pin to gain control of the memory interface the HOLDA signal is not asserted until all pending DMA transfers are completed To prevent a DMA from blocking outthe CPUs or HOLD HOLDA feature from accessing the external bus uninterrupted burst transfers are not supported by the DMAs Subsequently CPU and DMA arbitration testing is performed for each external bus cycle regardless of the bus activity With the completion of each block the highest priority will be swapped For arbitration atthe DSP subsystem level the DMA requests DMA REQ AorDMA REQ B fromeither DMA will be sent to both CPUs as shown in Figure 15 Regardless of which CPU controls the external pin interface XIO both CPUs must send a grant GRANT A GRANT_B for control of the bus to be released to the DMAs Arbitration between CPUS is done using a request grant scheme Prior to accessing XIO of one of the CPUS software is responsible for asserting a request for access to the device pins and polling grant status until the pins are granted to the requestor If both CPUs request the bus simultaneously subsystem A is granted priority For details on memory mapped register bits pertaining to CPU XIO arbitration see the general purpose control register bits 6 4 CORE SEL XIO GRANT XIO REQ in Table 13 At reset the default is that subsystem A has access to the device pi
19. and the ROM are disabled A combination of interrupt flags and the bit values of an external memory location determine the selection of the various boot options external interface XIO The external interface XIO supports the 5421 master boot modes and other external accesses Its features include e Multiplexed with the HPI pins Selection of XIO or HPI mode is determined by a dedicated pin XIO Provides 512K words of external program space 64K words of external data space and 64K words of external I O space Different boot modes are selectable by the XIO HMODE and RS A B pins e After reset the control register bit ROMEN is always preset to 1 While XIO 0 during reset host HPI mode is on the host sees all RAM and ROM is disabled A host write to 002Fh releases the CPUs from reset the 002Fh write by the host clears the ROMEN bit in the GPIO register While XIO 1 and ROMEN 1 during reset the CPU starts from ROM OFF80h to do boot selection After branching to non ROM area the code changes the ROMEN bitto enable the RAM area occupied by ROM While XIO 1 and ROMEN 0 during reset the CPU starts from external OFF80h to do boot selection Table 3 provides a complete description of HMODE SELA B and XIO pin functionality Table 3 XIO HPI Modes HMODE SELA B HPI MODES XIO 0 XIO MODES XIO 1 HPI non muxed address data subsystem B slave to host on chip peripherals All the 54x device
20. associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1999 Texas Instruments Incorporated
21. co l see Figure 46 and Figure 53 PARAMETER UNIT Delay time DS low to HD driven Case 1a Memory accesses when DMAC is active in 16 bit mode and 18H 20 tw psH tw DSH lt 18H Case 1b Memory accesses when DMAC is active in 16 bit mode and tw DSH 2 18H Case 1c Memory access when DMAC is active in 32 bit mode and 26H 20 tw DSH Delay time DS low to HD valid for first tw DSH lt 26H d DSL HDV1 byte of an HPI read Case 1d Memory access when DMAC is active in 32 bit mode and 20 tw DSH 2 26H Case 2a Memory accesses when is inactive and tw DSH lt 10H ns 10H 20 tw DSH Case 2b Memory accesses when is inactive and ty psH 2 Case 3 Register accesses Delay time DS high to HRDY high d DSH HYH writes and autoincrement reads td COH HYH Delay time CLKOUT rising edge to HRDY high MDSLHVL Delay time HDS low to HRDY td COH HTX Delay time CLKOUT rising edge to HINT change THAD stands for HCNTLO HCNTL1 and t HDS refers to either HDS1 or HDS2 DS refers to the logical OR of HCS and HDS tv HYH HDV Valid time HD valid after HRDY high ns th DSH HDV R Hold time HD valid after DS rising edge read 35 TEXAS INSTRUMENTS 78 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 HPI16 timing continued timing requirements H 0 5
22. events 35 TEXAS INSTRUMENTS 26 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 multichannel buffered serial port McBSP The 5421 device provides high speed full duplex serial ports that allow direct interface to other C54x LC54x devices codecs and other devices in a system There are six multichannel buffered serial ports McBSPs on board three per subsystem The McBSP provides Full duplex communication Double buffer data registers which allow a continuous data stream Independent framing and clocking for receive and transmit In addition the McBSP has the following capabilities Direct interface to 1 1 framers switching compatible and ST BUS compliant devices 1 2 compliant device AC97 compliant device Serial port interface SPI Multichannel transmit and receive of up to 128 channels A wide selection of data sizes including 8 12 16 20 24 or 32 bits u law and A law companding Programmable polarity for both frame synchronization and data clocks Programmable internal clock and frame generation The 5421 McBSPs have been enhanced to provide more flexibility in the choice of the sample rate generator input clock source On previous C5000 devices the McBSP sample rate input clock can be driven from one of two possible choices the internal CPU clock or the external CLKS pin However m
23. input Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA register This signal is only used in HPI multiplexed address data mode HMODE pin is low This pin is shared with the external memory interface and is only used by the HPI when the interface is in mode XIO pin is low This pin is placed into the high impedance state when OFF is low HPI chip select signal This signal must be active during HPI transfers and can remain active between concurrent transfers This pin is shared with the external memory interface and is only used by the HPI when the interface is HPI mode XIO pin is low This pin is placed into the high impedance state when OFF is low HPI data strobes HDS1 and HDS2 are driven by the host read and write strobes to control HPI transfers These pins are shared with the external memory interface and are only used by the HPI when the interface is in HPI mode pin is low ___ These pins are placed into the high impedance state when OFF is low HPI read write signal This signal is used by the hostto control the direction of an HPI transfer This pin is shared with the external memory interface and is only used by the HPI when the interface is in HPI mode XIO pin is low P This pin is placed into the high impedance state when OFF is low HPI data ready output The ready output informs the host when the HPI is ready for the next transfer This pin is shared wi
24. instructions Actual operating current varies with the program being executed This value was obtained using the following conditions external memory writes at a rate of 20 million writes per second CLKOFF 0 full duplex operation of all six McBSPs at a rate of 10 million bits per second each and 15 pF loads on all outputs For more details on how this calculation is performed refer to the Calculation of TMS320LC54x Power Dissipation Application Report literature number SPRA164 m m PLL x n mode 20 MHz input PLL x n mode 20 MHz input m u Vgs to V Vss to PPD 15 0 V Vss to VDD 175 All other input only pins 10 A A A A A A A F F ojo PARAMETER MEASUREMENT INFORMATION C O ho 50 0 Output Tester Pin VLoad o Under Electronics Test lt CT gh Yon Where 1 5 all outputs loH 300 uA all outputs 1 5 V CT 40 pF typical load circuit capacitance Figure 21 3 3 V Test Load Circuit 35 TEXAS INSTRUMENTS 52 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 divide by two divide by four and bypass clock option PLL Disabled The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four to generate the internal machine cycle The selection of the clock mode is described in the soft
25. low Test mode select Pin with internal pullup device This serial control input is clocked into the TAP controller on the rising edge of TCK Test reset When high TRST gives the scan system control of the operations of the device If TRST is driven low the device operates in its functional mode and the IEEE 1149 1 signals are ignored Pin with internal pulldown device High Impedance This pin has an internal pullup resistor These pins are Schmitt triggered inputs 1 This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A This pin is used by Texas Instruments for device testing and should be left unconnected This pin has an internal pulldown resistor 14 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 Signal Descriptions Continued wa eet 7 EMULATION TEST PINS CONTINUED Emulator interrupt 0 pin When TRST is driven low EMU0 must be high for the activation of the EMU0 VO Z EMU1 OFF condition When TRST is driven high EMUO is used as an interrupt to or from the emulator system and is defined as I O Emulator interrupt 1 pin When TRST is driven high EMU1 OFF is used as an interrupt to or from the emulator system and is defined as I O When TRST transitions from high to low then EMU1 operates as OFF EMU OFF 0 puts all output driv
26. n X Figure 42 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 0 35 TEXAS INSTRUMENTS 74 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 multichannel buffered serial port timing continued timing requirements for McBSP as SPI master or slave H 0 5t o CLKSTP 110 CLKXP ot see Figure 43 MASTER SLAVE tsu BDRV BCKXH Setup time BDR valid before BCLKX high 2 12H th BCKXH BDRV Hold time BDR valid after BCLKX high 5 12H Cycle time BCLKX T For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 switching characteristics for McBSP as SPI master or slave 0 CLKSTP 110 CLKXP Ot see Figure 43 MASTER SLAVE th BCKXL BFXL Hold time BFSX low after BCLKX low C 5 C 5 td BEXL BCKXH Delay time BFSX low to BCLKX T 5 1 td BCKXL BDXV Delay time BCLKX low to BDX valid 6H 4 10H 19 Disable time BDX high impedance following last data bit from BCLKX tdis BCKXL BDXHZ low 8 6H 4 10H 17 td BFXL BDXV Delay time BFSX low to BDX valid D 2 D 0 4H 4 8H 17 T For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 tT BCLKX period 1 CLKGDV 2H BCLKX low pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 2H when CLKGDV is even D BCLKX hig
27. one instruction fetch from any location in shared memory each cycle Neither subsystem CPU can write to the shared memory as only the DMA can write to shared memory on chip boot ROM The 5421 subsystems A and B each have 2K 16 bit words of on chip ROM This ROM is used for bootloading functions only Enabling the ROM maps out one 8K word block of the shared program memory The ROM can be disabled by clearing bit 7 ROMEN of the general purpose I O GPIO register Table 1 shows the XIO ROMEN modes The ROM is enabled or disabled at reset for each subsystem depending on the state of the GPIOO pin for that subsystem Table 1 XIO ROMEN Modes _______ ____ gt Fenman _ Fetch external ROM enabled extended program memory The program memory space on the 5421 device addresses up to 512K 16 bit words The 5421 device uses a paged extended memory scheme in program space to allow access of up to 512K of program memory This extended program memory each subsystem is organized into eight pages 0 7 pages 0 3 are internal pages 4 7 are external each 64K in length Pages 8 127 as defined by the program counter extension register XPC are aliases for pages 4 7 Access to the extended program memory is similar to the 5420 To implement the extended program memory scheme the 5421 device includes the following feature Two 54x instructions are extended to use the additional two bits in t
28. register SPSDx is used to access read or write the selected register Table 20 shows the McBSP control registers and their corresponding subaddresses Table 20 McBSP Control Registers and Subaddresses wes SUB NAME ADDRESS NAME ADDRESS NAME ADDRESS ADDRESS DESCRIPTION SPCR10 39h SPCR11 49h SPCR12 35h SPCR20 39h SPCR21 49h SPCR22 35h Oth SRGRTI as MCR20 39h MCR21 49h MCR22 35h RCERAO 39h RCERA1 49h RCERA2 35h RCERBO 39h RCERB1 49h RCERB2 35h OBh XCERBO 39h XCERB1 49h XCERB2 35h ODh Transmit channel enable register partition B RCERCO 39h 49h RCERC2 35h 010h XCERCO 39h XCERC1 49h XCERC2 35h 012h Transmit channel enable register partition C RCEREO 39h RCERE1 49h RCERE2 35h 014h XCEREO 39h XCERE1 49h XCERE2 35h 016h Transmit channel enable register partition E RCERGO 39h RCERG1 49h RCERG2 35h 018h XCERGO 39h XCERG1 49h XCERG2 35h 01Ah Transmit channel enable register partition G XCERHO 39h XCERH1 49h XCERH2 35h 01Bh Transmit channel enable register partition H DMA subbank addressed registers The direct memory access DMA controller has several control registers associated with it The main control register DMPREC is a standard memory mapped register However the other registers are accessed using the subbank addressing scheme This allows a set or subbank of registers to be accessed through a single memory location The DMA subbank address DMSA register is
29. sequence or at wakeup from IDLE3 RS must be held low for at least 50 us to ensure synchronization and lock in of the PLL SRS can cause change in clock frequency changing the value of H see the software programmable phase locked loop PLL section gt lt tsu RS tw RSL gt 5 RS INTn NMI 7 tsu INT gt tn RS lt tsu BIO k th BIO Ss Figure 32 Reset and BIO Timings 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 65 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 reset BIO interrupt and XIO timings continued GF ARUM s tsu INT lt gt tsu INT gt thant INTn NMI N y 4 tw INTH A k tw INTL A Figure 33 Interrupt Timing CLKOUT _ N XO 4 x th XIO tsu XIO gt YY YY NE NC NN NO NE NEN NN NC NC NN N N NUNC N N YY NC X Figure 34 XIO Timing Xl 35 TEXAS INSTRUMENTS 66 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 HOLD and HOLDA timing switching characteristics over recommended operating conditions for memory control signals and HOLDA H 0 5
30. te co see Figure 35 PARAMETER Valid time HOLDA low after CLKOUT low t v HOLDA Valid time HOLDA high after CLKOUT low tw HOLDA Pulse duration HOLDA low duration timing requirements for HOLD H 0 5 te co see Figure 35 tw HOLD Pulse duration HOLD low duration tsu HOLD Setup time HOLD low high before CLKOUT low ekot N NAF N N Z N Z N XZ NC gt 14 tsu HOLD tsu HOLDy tw HOLD HOLD N tv HOLDA tv HOLDA M lt GALA lt tw HOLDA HOLDA Figure 35 HOLD and HOLDA Timing HM z 1 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 67 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 external flag and timer output timing switching characteristics over recommended operating conditions for external flag XF and TOUT H 0 5 tc co see Figure 36 and Figure 37 PARAMETER Delay time CLKOUT low to XF high Delay time CLKOUT low low td TOUTH Delay time CLKOUT low to TOUT high td TOUTL Delay time CLKOUT low to TOUT low tw TOUT Pulse duration TOUT Figure 36 External Flag XF Timing CLKOUT Y NX NK NK Id TOUTH gt ta TOUTL TOUT N 4 tw TouT Figure 37 Timer TOUT Timing 35 TEXAS INSTRUMENTS 68 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL
31. the HPI16 include 16 bit bidirectional data bus Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts Multiplexed and nonmultiplexed address data modes 18 bit address bus used in nonmultiplexed mode to allow access to all internal memory including internal extended address pages 18 bit address register used in multiplexed mode Includes address autoincrement feature for faster accesses to sequential addresses Interface to on chip DMA module to allow access to entire internal memory space HRDY signal to hold off host accesses due to DMA latency Control register available in multiplexed mode only Accessible by either host or DSP to provide host DSP interrupts extended addressing and data prefetch capability Maximum data rate of 33 megabytes per second MBps at 100 MHz DSP clock rate no other DMA channels active The HPI16 acts as a slave to a 16 bit host processor and allows access to the on chip memory of the DSP There are two modes of operation as determined by the HMODE signal multiplexed mode and nonmultiplexed mode multiplexed mode In multiplexed mode 16 operation is very similar to that of the standard 8 bit HPI which is available with other C54x products A host with a multiplexed address data bus can access the HPI16 data register HPID address register HPIA or control register HPIC via the HD bidirectional data bus The host initi
32. 03 0000 Page 3 Lower 32KT External 03 7FFF 03 8000 Page 3 Upper 32K External 03 FFFF xDMA External Data Memory Mapt 02 0000 Page 1 Lower 32KT External 02 7FFF 02 8000 Page 1 Upper 32K External 02 FFFF t Pages 8 127 are overlaid over pages 0 7 Figure 14 DMA External Program Memory Map Page 2 Lower 32KT External Page 2 Upper 32K External 03 0000 Page 3 Lower 32KT External 03 7FFF 03 8000 Page 3 Upper 32K External 03 FFFF 07 0000 Page7 Lower 32KT External 07 7FFF 07 8000 Page 7 Upper 32K External 07 FFFF 07 0000 Page 7 Lower 32KT External 07 7FFF 07 8000 Page 7 Upper 32K External 07 FFFF 32 Ji TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 DMA controller features The 5421 DMA has the following features The DMA operates independently of the CPU The DMA has six channels The DMA can keep track of the contexts of six independent block transfers Two channels are available for external accesses one for reads and one for writes The DMA has higher priority than the CPU for internal accesses Each channel has independently programmable priorities Each channel s source and destination address registers include configurable indexing modes The address can be held constant postincremented postdecremented or adjusted by a programm
33. 251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 external memory interface timing for a memory write switching characteristics over recommended operating conditions for a memory write MSTRB 0 H 0 5 tc co see Figure 25 PARAMETER td CLKH A Delay time CLKOUT high to address validt td CLKL A Delay time CLKOUT low to address valid td CLKL MSL Delay time CLKOUT low to MSTRB low tq CLKL D W Delay time CLKOUT low to data valid td CLKL MSH Delay time CLKOUT low to MSTRB high 0 T Address PS and DS timings all included in timings referenced as address In the case of a memory write preceded by a memory write In the case of a memory write preceded by an I O cycle I mi N 1 A timing requirements for a memory write MSTRB 0 H 0 5 see Figure 25 s D A M ns ns tsu A W Setup time address valid before MSTRB low 44 ____ tsu D MSH Setup time write data valid before MSTRB high 4H 5 4H 58 t Address PS and DS timings are all included in timings referenced as address In the case of a memory write preceded by an I O cycle 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 57 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 external memory interface timing for a memory write continued
34. A BFSRO B BFSRO BFSR1 A BFSR2 B BFSR2 5 0 B BFSX1 2 B 8 2 lt 4 Receive clocks BCLKR serves as the serial shift clock for the buffered serial port receiver Input from an external clock source for clocking data into the McBSP When not being used as a clock these pins can be used as general purpose I O by setting RIOEN 1 BCLKR can be configured as an output by the way of the CLKRM bit in the PCR register These pins are placed into the high impedance state when OFF is low Transmit clocks Clock signal used to clock data from the transmit register This pin can also be configured as an input by setting the CLKXM 0 in the PCR register BCLKX can be sampled as an input by way of the IN1 bit in the SPC register When not being used as a clock these pins can be used as general purpose I O by setting XIOEN 1 These pins are placed into the high impedance state when OFF is low Buffered serial data receive input pin When not being used as data receive pins these pins can be used as general purpose I O by setting RIOEN 1 Buffered serial port transmit output pin When not being used as data transmit pins these pins can be used as general purpose I O by setting XIOEN 1 These pins are placed into the high impedance state when OFF is low Frame synchronization pin for buffered serial port input data The BFSR pulse initiates the receive data proce
35. B 2 2 2 3 3 L3 a 4 A BFSXO DVpp A BCLKXO B BFSRO PPD3 HD3 2 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 e BALL NO B1 gt x Gl O lt 1012 wj gt co Br D EN UN NN e pum N XN ELLE ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 Pin Assignments for the TMS320VC5421GGU 144 Pin MicroStar Ball Grid Array Continued DVpp EMU1 OFF Ws gt U gt o ejm ISIS z Em Piss m Mw 9 Le BDR2 o6 o9 Dio Ho _ lt ml gt 2 o col 35 TEXAS INSTRUMENTS B POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 Signal Descriptions name mer DEPO PPA18 MSB Parallel port address bus The DSP can access the external memory locations by way of the external PPA17 memory interface using PPA 18 0 in external memory interface EMIF mode when the XIO pin is logic PPA16 high PPA18 is a secondary output function of the SELA B pin PPA15 PPA14 The P
36. B gt x lt gt th RDY MSTRB MSTRB Wait State Generated gt Wait States by READY lt Generated Internally Figure 26 Memory Read With Externally Generated Wait States 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 59 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 ready timing for externally generated wait states continued 4 th RDY tsu RDY READY N tv RDY MSTRB th RDY MSTRB 3 MSTRB Wait States Generated Internally gt Wait State Generated by READY Figure 27 Memory Write With Externally Generated Wait States 35 TEXAS INSTRUMENTS 60 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 parallel I O interface timing switching over recommended operating conditions for a parallel I O port read IOSTRB 0 see Figure 28 PARAMETER MIN UNIT td CLKL A Delay time CLKOUT low to address valid 4 ns Delay time CLKOUT high to IDSTRB low td CLKH ISTRBH Delay time CLKOUT high to IOSTRB high th A IOR Hold time address after CLKOUT low T Address and IS timings are included in timings referenced as address timing requirements for a parallel port read IOSTRB
37. CE BOX 1443 9 HOUSTON TEXAS 77251 1443 85 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 MECHANICAL DATA PGE S PQFP G144 PLASTIC QUAD FLATPACK 0 13 NOM ane Y Gage Planet 20 20 19 80 22 20 0 05 MIN 21 80 sa 0 75 0 45 Seating Plane 1 60 MAX 0 08 4040147 C 10 96 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MO 136 Thermal Resistance Characteristics 35 TEXAS INSTRUMENTS 86 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 MECHANICAL DATA GGU S PBGA N144 PLASTIC BALL GRID ARRAY PACKAGE 13 1211109 8 7654321 6 6 pO O O O O O DOOOOOO DOOOOOO OOOO OOOOOOQ OOOO OOOO OOOO OOOO OOOOOOQ 6 OOOOOOQq OOOOOOQ VM NN OOOO DOOOOOO DOOOOOO p O O O O O O DOOOOOO 257 0 1 40 MAX TE 0 08 ve 4073221 11 96 NOTES A All linear dimensions millimeters B This drawing is subject to change without notice Thermal Resistance Characteristics 4 TEXAS INSTRUMENTS
38. Continued wwe eet S INITIALIZATION INTERRUPT AND RESET OPERATIONS CONTINUED A GPIOO B GPIOO A GPIO1 B GPIOS A TOUT 0 2 6803 TOUT T Input Output S Supply Z High Impedance t This pin has an internal pullup resistor These pins are Schmitt triggered inputs T This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem This pin is used by Texas Instruments for device testing and should be left unconnected This pin has an internal pulldown resistor The pin is used to configure the parallel port as a host port interface HPI mode when XIO pin is low or as an asynchronous memory interface EMIF mode when XIO pin is high At device reset the XIO pin level determines the initialization value of the MP MC bit a bit in the processor mode status PMST register Refer to the memory section for details GENERAL PURPOSE PINS External flag output latched software programmable output only signal Bit addressable A_XF and B XF are placed into the high impedance state when OFF is low A ROMEN General purpose I O pins The secondary function of these pins In XIO mode the ROM enable ROMEN pins are used to enable the applicable on chip ROM B ROMEN after reset General purpose pins software programmable I O signal Values can be latched output by writing into the GPIO regis
39. DMA channel 4 global source address reload register DMGCR4 56h 57h 38h DMA channel 4 global count reload register DMGSA5 56h 57h 3Ah DMA channel 5 global source address reload register DMGCR5 56h 57h 3Ch DMA channel 5 global count reload register DMGFR5 56h 57h 3Dh DMA channel 5 global frame count reload register TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 4 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 interrupts Vector relative locations and priorities for all internal and external interrupts are shown in Table 22 Table 22 5421 Interrupt Locations and Priorities for Each DSP Subsystem LOCATION DECIMAL HEX PRIORITY FUNCTION RS SINTR Reset Hardware and Software Reset FI 35 TEXAS INSTRUMENTS 46 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 interrupts continued The interprocessor interrupt IPINT bit of the interrupt mask register IMR and the interrupt flag register IFR allows the subsystem to perform interrupt service routines based on the other subsystem activity Incoming IPINT interrupts are latched in IFR 14 Generating an interprocessor interrupt is performed by writing a 1 to the IPIRQ field of the bank switching control register BSCR Subsequent interrupts must first clear the interrupt by writing 0 to
40. For a description of the remaining bits see TMS320C54x DSP Reference Set Volume 5 Enhanced Peripherals literature number SPRU302 15 4 13 12 d 1 9 7 6 5 4 3 2 4 0 AUTO CT Figure 16 DMA Transfer Mode Control Register DMMCRn TEXAS INSTRUMENTS 34 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 DMA accesses to external memory continued These new bit fields were created to allow the user to define the space select for the DMA internal external Also a new extended destination data page XDSTDP 6 0 subaddress 029h and extended source data page XSRCDP 6 0 subaddress 028h have been created DLAXS DMMCRn 5 0 No external access default internal Destination 1 External access SLAXS DMMCRn 11 0 No external access default internal Source 1 External access For the CPU external access software can configure the memory cells to reside inside or outside the program address map When the cells are mapped into program space the device automatically accesses them when their addresses are within bounds When the program address generation PAGEN logic generates an address outside its bounds the device automatically generates an external access All DMA I O space accesses are mapped to the core to core FIFO DMA controller synchronization events The transfers associated with each DMA channel can be synchronized to one of several even
41. GITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 Signal Descriptions Continued TvPFf DESCRIPTION HOST PORT INTERFACE HPI SIGNALS CONTINUED PRIMARY HD 15 0 0 2 PPDI159 HCNTLO PPA3 HCNTL1 PPA2 439 HDS21 0515 T Input Output S Supply Z High Impedance t This pin has an internal pullup resistor These pins are Schmitt triggered inputs Parallel bidirectional data bus These pins are multiplexed with the external interface pins and are used as an HPI interface when XIO 0 The data bus includes bus holders to reduce power dissipation caused by floating unused pins The bus holders also eliminate the need for external pullup resistors on unused pins When the data bus is not being driven by the 5421 the bus holders keep address pins at the last driven logic level The data bus keepers are disabled at reset and can be enabled disabled via the BH bit of the BSCR register Seethe PPD signal descriptions These pins are placed into the high impedance state when OFF is low HPI control inputs Use PPA3 and PPA2 for the HCNTLO and HCNTL1 values during the HPI HPIC HPIA and HPID reads writes Only used in multiplexed address data mode HMODE 0 These pins are shared with the external memory interface and are only used by the HPI when the interface is in HPI mode XIO pin is low These pins are placed into the high impedance state when OFF is low Address strobe
42. HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 HPI16 timing continued tsu HBV HSL th HSL DSL M tsu HSL DSL HR W P th HSL HBV K tc DSH DSH P twDsH lt tsu HDV DSH 080 ome KX gt lt th DSH HDV W HRDY f td DSL HYLjj4 9 td DSH HYH Figure 48 Multiplexed Write Timings Using HAS 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 81 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 16 timing continued HCS N K te DSH DSH tw DSH A A tsu HBV DSL tw DSL gt th DSL HBV HCNTLI4 0 Com X X m tsu HDV DSHJff K th DSH HDV W 4 td DSL HYL HRDY N td DSH HYH Figure 49 Multiplexed Write Timings With HAS Held High 35 TEXAS INSTRUMENTS 82 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 HPI16 timing continued HCS 4 tw DSH M lt te DSH DSH P HDS NN LAE N Z K tsu HBV DSL tw DSL lt th DSL HBV tsu HAV DSL gt y th DSH HAV
43. I file that can be modified with most editors This provides the emulator with a description of the JTAG chain The board cfg file must identify two processors when using the 5421 The file contents would look something like this CPU B TIS20C5xx CPU A TIS20C5xx Use the compose program to make this file into a binary file board dat readable by the emulation tools Place the board dat file in the directory that contains the emulator software The subsystems are serially connected together internally Emulation information is serially transmitted into the device using TDI The device responds with serial scan information transmitted out the TDO pin TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 49 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 documentation support Extensive documentation supports all TMS320 family generations of devices from product announcement through applications development The following types of documentation are available to support the design and use of the C5000 family of DSPs TMS320C5000 DSP Family Functional Overview literature number SPRU307 Device specific data sheets such as this document Complete User Guides Development support tools Hardware and software application reports The five volume TMS320C54x DSP Reference Set literature number SPRU210 consists of Volume 1 CPU and Peripherals lit
44. IFR IMR Timer has no interrupt pending is disabled masked IFR IMR Timer has an interrupt pending is enabled Register bit is reserved IFR IMR Ext user interrupt pin 1 has no interrupt pending is disabled masked IFR IMR Ext user interrupt pin 1 has an interrupt pending is enabled IFR IMR Ext user interrupt pin O has no interrupt pending is disabled masked IFR IMR Ext user interrupt pin O has an interrupt pending is enabled 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 IDLE3 power down mode The IDLE1 IDLE2 power down modes operate as described in the TMS320C54x DSP Reference Set Volume 1 CPU and Peripherals literature number SPRU131 The IDLE3 mode is special in that the clocking circuitry is shut off to conserve power The 5421 cannot enter an IDLE3 mode unless both subsystems execute an IDLE instruction The power reduced benefits of IDLE3 cannot be realized until both subsystems enter the IDLES state and the internal clocks are automatically shut off The order in which subsystems enter IDLE3 does not matter emulating the 5421 device The 5421 is a single device but actually consists of two independent subboundary systems that contain register status information used by the emulator tools The emulator tools must be informed of the multicore device by modifying the board cfg file The board cfg file is an ASCI
45. IOSTRB Z t td CLKL RWL c td CLKL RWH RV N Figure 29 Parallel I O Port Write IOSTRB 0 35 TEXAS INSTRUMENTS 62 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 externally generated wait states timing timing requirements for externally generated wait states H 0 5 see Figure 30 and Figure 31 fC tsu RDY Setup time READY before CLKOUT low th RDY Hold time READY after CLKOUT low tv RDY IOSTRB Valid time READY after IOSTRB lowt _____5 8 ns th RDY IOSTRB Hold time READY after IOSTRB lowt T The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles To generate wait states using READY at least two software wait states must be programmed These timings are included for reference only The critical timings for READY are those referenced to CLKOUT Nf XZ RS th RDY lt E tsu RDY READY tv RDY IOSTRB th RDY IOSTRB 1 IOSTRB x gt Wait State Generated Wait by READY 8 States gt gt Generated Internally Figure 30 I O Port Read With Externally Generated Wait States 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 63 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR
46. K words Access is always external D All internal memory is divided into 8K blocks Figure 2 Memory Map Relative to CPU Subsystems A and B on chip dual access RAM DARAM The 5421 subsystems A and B each have 32K 16 bit words of on chip DARAM 4 blocks of 8K words Each of these DARAM blocks can be accessed twice per machine cycle This memory is intended primarily to store data values however it can be used to store program as well At reset the DARAM is mapped into data memory space The DARAM can be mapped into program data memory space by setting the OVLY bit in the processor mode status PMST register of the 54X cLEAD CPU in each DSP subsystem 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 17 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 on chip single access RAM SARAM The 5421 subsystems A and B each have 32K 16 bit words of on chip SARAM 4 blocks of 8K words Each of these SARAM blocks can be accessed once per machine cycle This memory is intended to store data values only At reset the SARAM is disabled The SARAM can be enabled in data memory space by setting the DROM bit in the PMST register on chip shared RAM DARAM The 5421 has 128K 16 bit words of on chip DARAM 16 blocks of 8K words that is shared between the two DSP subsystems This memory is intended to store program only Each subsystem is able to make
47. MA destination program page address common channel DMIDXO 56h 57h 20h DMA element index address register 0 56h 57h 4 5 INSTRUMENTS 44 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 DMA subbank addressed registers continued Table 21 DMA Subbank Addressed Registers Continued SUB NAME ADDRESS ADDRESS DESCRIPTION DMGSAO 56h 57h 24h DMA channel 0 global source address reload register DMGDAO 56h 57h 25h DMA channel 0 global destination address reload register DMGCRO 56h 57h DMA channel 0 global count reload register XSRCDP 56h 57h 28h DMA extended source data page DMGSA1 56h 57h 2Ah DMA channel 1 global source address reload register DMGDA1 56h 57h DMA channel 1 global destination address reload register 56h 57h DMA channel 1 global count reload register DMGFR1 56h 57h 2Dh DMA channel 1 global frame count reload register DMGSA2 56h 57h 2bEh DMA channel 2 global source address reload register DMGDA2 56h 57h 2Fh DMA channel 2 global destination address reload register DMGCR2 56h 57h DMA channel 2 global count reload register DMGFR2 56h 57h DMA channel 2 global frame count reload register DMGSA3 56h 57h 32h DMA channel 3 global source address reload register DMGDA3 56h 57h 33h DMA channel 3 global destination address reload register DMGCR3 56h 57h 34h DMA channel 3 global count reload register DMGSA4 56h 57h 36h
48. MS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 PLL clock programmable timer During the lockup period the PLL should not be used to clock the 5421 The PLLCOUNT programmable lock timer provides a convenient method of automatically delaying clocking of the device by the PLL until lock is achieved The PLL lock timer is a counter loaded from the PLLCOUNT field in the CLKMD register that decrements from its preset value to 0 The timer can be preset to any value from 0 to 255 and its input clock is CLKIN divided by 16 The resulting lockup delay can therefore be set from 0 to 255 x 16 CLKIN cycles The lock timer is activated when the operating mode of the clock generator is switched from DIV to PLL During the lockup period the clock generator continues to operate in DIV mode after the PLL lock timer decrements to zero the PLL begins clocking the 5421 Accordingly the value loaded into PLLCOUNT is chosen based on the following formula Lockup Time PLLCOUNT 16 x where Tc is the input reference clock period and lockup time is the required VCO lockup time as shown Table 17 Table 17 VCO Lockup Time CLKOUT FREQUENCY MHz LOCKUP TIME us 40 Ji TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 memory mapped registers Table 18 Processor Memory Mapped Registers for Each DSP S
49. PA 17 0 pins are also multiplexed with the HPI interface In HPI mode is low the external PPA13 address pins PPA 17 0 are used by a host processor for access to the memory map by way of the PPA12 on chip HPI Refer to the Host Port Interface HPI Signals section of this table for details on the PPA11 secondary functions of these pins PPA10 These pins are placed into the high impedance state when OFF is low PPA9 PPA8 PPA7 PPA6 PPA5 PPA4 PPA3 PPA2 PPA1 PPA0 LSB PPD15 MSB Parallel port data bus The DSP uses this bidirectional data bus to access external memory when the PPD14 device is in external memory interface EMIF mode the XIO pin is logic high PPD13 PPD12 This data bus is also multiplexed with the 16 bit HPI data bus When in HPI mode the bus is used to PPD11 transfer data between the host processor and internal DSP memory via the HPI Refer to the HPI section PPD10 of this table for details on the secondary functions of these pins PPD9 PPD8 24 The data bus includes bus holders to reduce power dissipation caused by floating unused pins The bus PPD7 holders also eliminate the need for external pullup resistors on unused pins When the data bus is not PPD6 being driven by the 5421 the bus holders keep data pins at the last driven logic level The data bus PPD5 keepers are disabled at reset and can be enabled disabled via the BH bit of the BSCR register PPD4 PPD3 These pins are pla
50. PLEXED MULTIPLEXED A8 D1 6 2 IOSTRB GPIO2 BIO H H 1 k 00 15 HD12 po 15 ss PPA10 HA10 11 HA11 HA13 4 22 26 30 3 38 42 46 50 5 58 62 70 7 78 82 9 4 4 4 4 102 106 H 110 B_HINT HA1 114 118 Ee HD5 142 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 Pin Assignments for the TMS320VC5421 PGE 144 Pin Thin Quad Flatpack Continued NONMULTIPLEXED MULTIPLEXED NONMULTIPLEXED MULTIPLEXED 55 S C S 2 A BDX1 A BCLKX1 HOLDA TC TRST EMU1 OFF EMUO HD14 AB o E Bs Fas seso o PPD11 HD11 DVDD 5 _______ HPIRS HMODE 6155 eT EE 2 2 42 da lt B_BCLKR1 B_BFSR1 Rem BCLKX1 B BDR1 LL HRDY lt TEXAS INSTRUMENTS B POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 Pin Assignments for the TMS320VC5421GGU 144 Pin MicroStar Ball Grid Array NONMULTIPLEXED MULTIPLEXED NO NONMULTIPLEXED 05 J N D H M C G
51. POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 87 ADVANCE INFORMATION IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks
52. RR22 SPSA2 SPSD2 s MeBSP 0 Subbank Register SPSD0 57 39 McBSP0Subbank 58 59 s __ General Purpose WO Register SSCS 5 Reewd 2222 Chip Subsystem pene 5 4 oam GPIO CSIDR er 4 47 1 Subbank Address Regie r WssPisumemDamRedet O se DMAProriyand Enable _ DVA Subba Adcress Register SOS ee 58 DMA Subbank Data Register with Autoneremen DMSON e7 57 _ DMASubbankDataRegster SSCS f feanen T See Table 20 for a detailed description of the McBSP control registers and their subaddresses See Table 21 for a detailed description of the DMA subbank addressed registers 35 TEXAS INSTRUMENTS 42 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 McBSP control registers and subaddresses The control registers for the multichannel buffered serial port McBSP are accessed using the subbank addressing scheme This allows a set or subbank of registers to be accessed through a single memory location The McBSP subbank address register SPSA is used as a pointer to select a particular register within the subbank The McBSP data
53. Ryz1 XCERyzo RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read W Write 0 Value at reset Partition A B C D E F G or H z McBSP 0 1 or 2 Figure 12 Transmit Channel Enable Registers Bit Layout for Partitions A to H Table 9 Transmit Channel Enable Registers for Partitions A to H Bit Name Function 15 0 XCERyz 15 0 Transmit Channel Enable Register XCERyzn 0 Disables transmit of nth channel in partition y XCERyz n 1 Enables transmit of nth channel in partition y Note Partition A B C D E F G or H z McBSP 0 1 or 2 bit 15 0 The clock stop mode CLKSTP in the McBSP provides compatibility with the serial port interface SPI protocol Clock stop mode works with only single phase frames and one word per frame The word sizes supported by the McBSP are programmable for 8 12 16 20 24 or 32 bit operation When the McBSP is configured to operate in SPI mode both the transmitter and the receiver operate together as a master or as a slave The McBSP is fully static and operates at arbitrarily low clock frequencies The maximum McBSP multichannel operating frequency on the 5421 is 9 MBps Nonmultichannel operation is limited to 38 MBps direct memory access DMA controller The 5421 includes two 6 channel direct memory access DMA controllers for performing data transfers independent of the CPU one for each subsystem The DMA controller controls accesses to off chip program data IO
54. able value For internal accesses each read or write transfer can be initialized by selected events Supports 32 bit transfers for internal accesses only Single word 16 bit transfers are supported for external accesses The DMA does not support transfers from peripherals to external memory The DMA does not support transfers from external memory to the peripherals The DMA does not support external to external transfers A 16 bit DMA transfer requires four CPU clock cycles to complete two cycles for reads and two cycles for writes This gives a maximum DMA throughput of 50 MBps Since the DMA controller shares the DMA bus with the HPI module the DMA access rate is reduced when the HPI is active DMA accesses to external memory The 5421 DMAs supports external accesses to extended program extended data and extended I O memory These overlay pages are only visible to the DMA controller A maximum of two channels one for reads one for writes per DMA can be used for external memory accesses The DMA external accesses require 9 cycles minimum for external writes and 13 cycles minimum for external reads The control ofthe bus is arbitrated between the two CPUs and the two DMAs While one DMA or CPU is in control of the external bus the other three components will be held off via wait states until the current transfer is complete The DMA takes precedence over XIO requests The HOLD HOLDA feature of the 5421
55. aining bits see TMS320C54x DSP Reference Set Volume 5 Enhanced Peripherals literature number SPRU302 Inthe first mode when RMCME 0 and XMCME 0 there are two partitions A and B with each containing 16 channels as shown in Figure 9 and Figure 10 This is compatible with the McBSPs used in the 5420 where only 32 channel selection is enabled default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XMC R 0 RW 0 RW 0 RW 0 R 0 RW 0 Note R Read W Write 0 Value at reset McBSP 0 1 or 2 Figure 9 Multichannel Control Register 2x MCR2x 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMC R 0 RW 0 RW 0 RW 0 R 0 RW 0 Note R Read W Write 0 Value at reset x McBSP 0 1 or 2 Figure 10 Multichannel Control Register 1x MCR1x 35 TEXAS INSTRUMENTS 8 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 multichannel buffered serial port McBSP continued Inthe second mode with RMCME 1 and XMCME 1 the McBSPs have 128 channel selection capability Twelve new registers RCERCx RCERHx and XCERCx XCERHx are used to enable the 128 channel selection The subadresses of the new registers are shown in Table 20 These new registers functionally equivalent to the RCERAO RCERB1 and XCERAO XCERB1 registers the 5420 are used to enable disable the transmit and receive of additional channel partitions C D E F G and H in th
56. am space The field value 0 7 corresponds to the base number of wait states for external program Space accesses within the following addresses 1 0 x0000 x7FFFh XPA 1 00000 3FFFFh The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states ili Upper program space The field value 0 7 corresponds to the base number of wait states for external program space accesses within the following addresses 5 3 Program 1 0 x8000 xFFFFh 1 The upper program space bit field has no effect on wait states The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states The software wait state multiplier bit of the software wait state control register SWCR is used to extend the base number of wait states selected by the SWWSR The SWCR bit fields are shown in Figure 4 and described in Table 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 21 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 software programmable wait state generators continued 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SWSM R W 0 R W 0 LEGEND R Read W Write Figure 4 Software Wait State Control Register SWCR MMR Address 002Bh Table 5 Software Wait State Control Register SWCR Bit Fields RESET 15 1 Reserved These bit
57. and internal data program memory The primary function of the 5421 DMA controller is to provide code overlays and manage data transfers between on chip memory the peripherals and off chip memory In the background of CPU operation the 5421 DMA allows movement of data between internal and external program data memory and internal peripherals such as the McBSPs and the HPI Each subsystem has its own independent DMA with six programmable channels which allows for six different contexts for DMA operation The HPI has a dedicated auxiliary DMA channel Figure 13 illustrates the memory map accessible by the DMA 35 TEXAS INSTRUMENTS 30 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 direct memory access DMA controller continued Hex Datat Hex Program Page ot Hex Program Page 1t Hex Program Page 2t Hex Program Page 3t 00 0000 00 0000 01 0000 02 0000 03 0000 Reserved Reserved Reserved 00 001F 00 001F 00 0020 000020 _McBSP 92 0020 McBSP DXR DRR DXR DRR 00 005F 0056 MMRegs Only 02 0056 MMRegs Only 02 0060 n Chip 00 0060 00 0060 On Chip Shared Shared DARAM 2 On Chip DARAM 0 32K Words DARAM A B DARAM A 32K Words 32K Word Program 32K Words 32K Words Program E n s Only Prog Data Prog Data Only rogiData 00 7FFF 00 7FFF Subsystem A ppp Shared 0 02 7FFF Subsystem 03 7 Shared 2 00 8000 00 8000 01 8000 02 8000
58. ates the access with the strobe signals HDS1 HDS2 HCS and controls the type of access with the HCNTL HR W and HAS signals The DSP can interrupt the host via the HINT signal and can stall host accesses via the HRDY signal host DSP interrupts In multiplexed mode the 16 offers the capability for the host and DSP to interrupt each other through the HPIC register For host to DSP interrupts the host must write a 1 to the DSPINT bit of the HPIC register This generates an interrupt to the DSP This interrupt can also be used to wake the DSP from any of the IDLE 1 2 or 3 states Note that the DSPINT bit is always read as 0 by both the host and DSP The DSP cannot write to this bit see Figure 7 For DSP to host interrupts the DSP must write a 1 to the HINT bit of the HPIC register to interrupt the host via the HINT pin The host acknowledges and clears this interrupt by also writing a 1 to the HINT bit of the HPIC register Note that writing a O to the HINT bit by either host or DSP has no effect TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 25 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 HPI nonmultiplexed mode In nonmultiplexed mode a host with separate address data buses can access the HPI16 data register HPID viathe HD 16 bit bidirectional data bus and the address register HPIA via
59. both the I O pins and the core CPU Pin configuration shown for nonmultiplexed mode only See the pin assignments table for the TMS320VC5421 PGE for multiplexed functions of specific pins and for specific pin numbers The TMS320VC5421PGE 144 pin thin quad flatpack TQFP is footprint and pin compatible with the 5420 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 3 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 GGU PACKAGE BOTTOM VIEW 13 12 110 9 8 7 6 5 4 3 2 1 OOOOOOOOOOOOO OQ O O OOOOOOOOOOOOO OOOOOOOOOOOOO OOOO O O OO OOOO OOOO OOOO OOOO OOOO O O O O OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO z Z T m gt pin assignments table for the TMS320VC5421GGU lists each name and its associated pin number for this 144 pin ball grid array BGA package which is footprint pin compatible with the 5420 The signal descriptions table lists each pin name function and operating mode s for the 5421 device 35 TEXAS INSTRUMENTS s POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 Pin Assignments for the TMS320VC5421PGE 144 Pin Thin Quad Flatpack SIGNAL NAME SIGNAL NAME SIGNAL NAME SIGNAL NAME NONMULTIPLEXED MULTIPLEXED NONMULTI
60. ced into high impedance state when OFF is low PPD2 PPD1 PPDO LSB INITIALIZATION INTERRUPT AND RESET OPERATIONS A INTOS B INTOS INT1 B 19 Nonmaskable interrupt NMI is an external interrupt that cannot be masked by way of the INTM or the IMR When NMI is activated the processor traps to the appropriate vector location Reset RS causes the digital signal processor DSP to terminate execution and causes a reinitialization of the CPU and peripherals When RS is brought to a high level execution begins at location OFF80h of program memory RS affects various registers and status bits External user interrupts A INTO B INTO are prioritized and are maskable by the interrupt mask register IMR and the interrupt mode bit INT1 B INT1 can be polled and reset by way of the interrupt flag register IFR T Input O Output S Supply Z High Impedance t This pin has an internal pullup resistor These pins are Schmitt triggered inputs 1 This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A This pin is used by Texas Instruments for device testing and should be left unconnected This pin has an internal pulldown resistor 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 9 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 Signal Descriptions
61. characteristics for McBSP general purpose I O see Figure 41 PARAMETER MIN MAX UNIT td COH BGPIO Delay time CLKOUT high to BGPIOx output modet 10 10 5 BGPIOx refers to BCLKRx BFSRx BCLKXx BFSXx BDXx when configured as a general purpose output td COH BGPIO HN on Ne SU lt th COH BGPIO BGPIOx Input Modet BGPIOx Output Modet T BGPIOx refers to BCLKRx BFSRx BDRx BCLKXx or BFSXx when configured as a general purpose input BGPIOx refers to BCLKRx BFSRx BCLKXx BFSXx or BDXx when configured as a general purpose output Figure 41 McBSP General Purpose I O Timings 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 73 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 multichannel buffered serial port timing continued timing requirements for McBSP as SPI master or slave H 0 5te co CLKSTP 10b CLKXP ot see Figure 42 Setup time BDR valid before BCLKX low th BCKXL BDRV Hold time BDR valid after BCLKX low tsu BFXL BCKXH Setup time BFSX low before BCLKX high tc BCKX Cycle time BCLKX t For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 switching characteristics for McBSP as SPI master or slave 0 5 CLKSTP 10b CLKXP Ot see Figure 42 MASTER SLAVE PARAMETER Hold time BFSX low af
62. ctrically readable device identification The ChipID bits identify the type of 54x device 21h for 5421 The ChipRev bits contain the revision number of the device Lastly the SubSysID contains a unique subsystem identifier 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip ID Chip Rev SubSysID Figure 17 Chip subsystem ID Register Table 12 Chip subsystem ID Register Bit Functions FUNCTION 35 TEXAS INSTRUMENTS 36 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 general purpose I O In addition to the A_XF and B XF pins the 5421 has eight general purpose I O pins These pins are A_GPIOO A GPIO1 A GPIO2 A_GPIO3 B GPIOO B GPIO1 B GPIO2 B GPIO3 Four general purpose I O pins are available to each core Each GPIO pin can be individually selected as either an input or an output Additionally the timer output is selectable on GPIO pin 3 At core reset all GPIO pins are configured as inputs GPIO data and control bits are accessible through a memory mapped register at 3Ch with the format shown in Figure 18 XIO GPIO GPIO cPIo CORE GPIO TOUT DiR2 DiR1 DIRO JHR uon JDE DATS 0412 0411 DATO R W R W R W R W R W RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 Note R Read W Write 0 Value at reset Figure 18 General Purpose I O Control Register Table 13 General Purpose I O Control
63. d internally from local SARAM memory The I O space is a single page of 64K Access is always external When XIO 0 and an access to external memory is attempted any write is ignored and any read is an unknown value multicore reset signals The 5421 device includes three reset signals A RS B RS and HPIRS The RS and B RS pins function as the CPU reset signal for subsystem A and subsystem B respectively These signals reset the state of the CPU registers and upon release initiate the reset function Additionally the RS signal resets the on chip PLL and initializes the CLKMD register to bypass mode The HPI reset signal HPIRS places the HPI peripheral into a reset state It is necessary to wait three clock cycles after the rising edge of HPIRS before performing an HPI access The HPIRS signal also resets the PLL by turning off the PLL and initializing the CLKMD register to bypass mode bootloader The on chip bootloader is used to automatically transfer user code from an external source to anywhere in program memory after reset The XIO pin is sampled during a hardware reset and the results indicate the operating mode as shown in Table 2 Table 2 Bootloader Operating Modes HPI mode bootload is controlled by host The external host holds the 5421 in reset while it loads the on chip memory of one or both subsystems as determined by the SELA B pin The host can release the 5421 from reset by either of the follow
64. e 128 channel stream For example XCERH1 is the transmit enable for channel partition H channels 112 to 127 of MCBSP1 for each DSP subsystem See Figure 11 Table 8 Figure 12 and Table 9 for bit layout and function of the receive and transmit registers 15 14 13 12 11 10 9 8 RCERyz15 RCERyz14 RCERyz13 RCERyz12 RCERyz11 RCERyz10 RCERyz9 RCERyz8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Note R Read W Write 0 Value at reset Partition A B C D E F G or H z McBSP 0 1 or 2 Figure 11 Receive Channel Enable Registers Bit Layout for Partitions A to H Table 8 Receive Channel Enable Registers for Partitions A to H Function 15 0 RCERyz 15 0 Receive Channel Enable Register 0 Disables reception of nth channel in partition y 1 Enables reception of nth channel in partition y Note Partition A B C D E F G or H z McBSP 0 1 or 2 n bit 15 0 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 29 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 multichannel buffered serial port McBSP continued 15 14 13 12 11 10 9 8 XCERyz15 XCERyz14 XCERyz13 XCERyz12 XCERyz11 XCERyz10 XCERyz9 XCERyz8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 XCERyz7 XCERyz6 XCERyz5 XCERy4 XCERyz3 XCERyz2 XCE
65. ed The selection of the sample rate generator SRG clock input source is made by the combination of the CLKSM and SCLKME bit values as shown in Table 7 Table 7 Sample Rate Generator Clock Source Selection SCLKME CLKSM SRG Clock Source When either of the bidirectional pins BCLKR or BCLKX is configured as the clock input its output buffer is automatically disabled For example with SCLKME 1 and CLKSM 0 the BCLKR pin is configured as the SRG input In this case both the transmitter and receiver circuits can be synchronized to the SRG output by setting the PCR bits 9 8 for CLKXM 1 and CLKRM 1 However the SRG output is only driven onto the BCLKX pin because the BCLKR output is automatically disabled The McBSP supports independent selection of multiple channels for the transmitter and receiver When multiple channels are selected each frame represents a time division multiplexed TDM data stream In using time division multiplexed data streams the CPU may only need to process a few of them Thus to save memory and bus bandwidth multichannel selection allows independent enabling of particular channels for transmission and reception Up to a maximum of 128 channels in a bit stream can be enabled or disabled The 5421 McBSPs have two working modes that are selected by setting the RMCME and XMCME bits in the multichannel control registers MCR1x and MCR2x respectively See Figure 9 and Figure 10 For a description of the rem
66. ed pin location The McBSPs have been updated with a new mode that allows 128 channel selection capability McBSP CLKX R pins can be used as inputs to internal clock rate generator for CLKS like function without the penalty of extra pins The SELA B pin on 5421 is changed to type l O Z for added functionality NOTE For more detailed information see the 5420 to 5421 migration issues document 35 TEXAS INSTRUMENTS 2 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 IOSTRB EMU1 OFF DVpp A INTO EMUO TDO WD PPDO PPD5 PPD4 PPD6 A_BFSX2 PGE TOP VIEW A BDX2 A BFSR2 A BDR2 A BCLKR2 READY DVpp B BDX2 B 2 B BCLKR2 PPD2 A BCLKX2 PPD3 CLKIN HOLD B BCLKX2 B BFSR2 B BFSX1 55 B BDX1 B BCLKX1 CVpp Vss TEST XIO B RS B_CLKOUT HMODE HPIRS PPA13 PPA12 Vss DYDD PPA11 PPA10 Vss PPD15 PPD14 2 gt PPD13 PPD12 A BFSRO Vss CVpD _ DS PS B BCLKXO Vss B_BFSX0 R W PPA2 PPA3 SELA B B BCLKRO Vss B_BFSRO PPD8 PPD9 PPD10 PPD11 0 e gt A BDRO A BCLKRO A A BCLKXO MSTRB 8070 DVpD B_BDR0 CVDD t DVpp is the power supply for the I O pins while CVpp is the power supply for the core CPU Vssis the ground for
67. erature number SPRU131 Volume 2 Mnemonic Instruction Set literature number SPRU172 Volume 3 Algebraic Instruction Set literature number SPRU179 Volume 4 Applications Guide literature number SPRU173 Volume 5 Enhanced Peripherals literature number SPRU302 The reference set describes in detail the 54x TMS320 products currently available and the hardware and software applications including algorithms for fixed point TMS320 devices For general background information on DSPs and Texas Instruments TI devices see the three volume publication Digital Signal Processing Applications with the TMS320 Family literature numbers SPRAO012 SPRAO016 and SPRAO17 A series of DSP textbooks is published by Prentice Hall and John Wiley amp Sons to support digital signal processing research and education The TMS320 newsletter Details on Signal Processing is published quarterly and distributed to update TMS320 customers on product information Information regarding DSP products is also available on the Worldwide Web at http www ti com uniform resource locator URL Tl is a trademark of Texas Instruments Incorporated 50 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 absolute maximum ratings over specified temperature range unless otherwise Supply voltage I O range DVppt
68. ernal bus interface functions as usual EXIO EXIO 1 The address bus data bus and control signals become inactive after completing the current bus cycle Note that the DROM MP MC and OVLY bits in the PMST and the HM bit of ST1 cannot be modified when the interface is disabled parallel I O ports The 5421 has a total of 64K words of I O port address space These ports can be addressed by PORTR and PORTW The IS signal indicates the read write access through an I O port The devices can interface easily with external devices through the I O ports while requiring minimal off chip address decoding logic The SELA B pin selects which subsystem is accessing the external I O space TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 23 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 16 bit bidirectional host port interface HPI16 16 memory map The 16 is an enhanced 16 bit version of the C54x 8 host port interface HPI The 16 is designed to allow a 16 bit host to access the DSP on chip memory with the host acting as the master of the interface Figure 6 illustrates the available memory accessible by the HPI Neither the CPU DMA I O spaces be accessed using the host port interface Hex 00 0000 00 001F 00 0020 00 005F 00 0060 00 7FFF 00 8000 00 FFFF NOTES A B C Page 0 Rese
69. ers into the high impedance state EMUT IOFF Note that OFF is used exclusively for testing and emulation purposes and not for multiprocessing applications Therefore for the OFF condition the following conditions apply TRST 0 1 EMU1 0 T Input Output S Supply Z High Impedance t This pin has an internal pullup resistor These pins are Schmitt triggered inputs 1 This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem This pin is used by Texas Instruments for device testing and should be left unconnected This pin has an internal pulldown resistor TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 15 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PR 5 5098 DECEMBER 1999 functional overview OCESSOR P C D E Buses and Control Signals Arbitrator DSP Subsystem A X cL Core 54 EAD A Cbus Dbus Ebus 32K RAM Dual Access Program Data 6 32K RAM Single Access Data a 2K Program ROM bus MBus RHEA P bus RHEA bus MBus Arbitrator pene XIO 16HPI Interprocessor IRQs Core to Core FIFO Interface Dual Access PRAM Cycle Arrangmnt MBus
70. for the number of wait states At reset the wait state generator is initialized to provide seven wait states on all external memory accesses The SWWSR bit fields are shown in Figure 3 and described in Table 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 ea pa R W 0 R W 111 R W 111 R W 111 R W 111 R W 111 LEGEND R Read W Write Figure 3 Software Wait State Register SWWSR Memory Mapped Register MMR Address 0028h Table 4 Software Wait State Register SWWSR Bit Fields Extended program address control bit XPA is used in conjunction with the program space fields bits 0 through 5 to select the address range for program space wait states space The field value 0 7 corresponds to the base number of wait states for I O space accesses within addresses 0000 FFFFh SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states Upper data space The field value 0 7 corresponds to the base number of wait states for external data space accesses within addresses 8000 FFFFh The SWSM bit of the defines a multiplication factor of 1 or 2 for the base number of wait states 11 9 Data Lower data space The field value 0 7 corresponds to the base number of wait states for external data Space accesses within addresses 0000 7FFFh The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states Progr
71. gh before BCLKX low oe BCKRX Rise time BCLKR X efons t BCKRX Fall time BCLKR X BCLKRXex 8 ns 1 Polarity bits CLKRP CLKXP FSRP FSXP 0 If the polarity of any of the signals is inverted then the timing references of that signal are also inverted Ji TEXAS INSTRUMENTS 70 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 multichannel buffered serial port timing continued switching characteristics for the McBSPT H 0 5tc co see Figure 39 and Figure 40 te BCKRX Cycle time BCLKR X tw BCKRXH Pulse duration BCLKR X high tw BCKRXL Pulse duration BCLKR X low td BCKRH BERV Delay time BCLKR high to internal BFSR valid td BCKXH BFXV Delay time BCLKX high to internal BFSX valid BCLKX ext 2 15 tdis BCKXH BDXHZ Disable time BCLKX high to BDX high impedance following last data bit BCLKX ext Delay time BCLKX high to BDX valid This applies to all bits except the first BCLKX int bit transmitted BCLKX ext i 1 1 BCLKX int Id BCKXH BDXV Delay time BCLKX high to valid DXENA 0 Only applies to first bit transmitted when in Data Delay 1 2 XDATDLY 01b 10b modes DXENA 1 BCLKX int BCLKX ext Enable time BCLKX high to BDX driven DXENA 0 Boxxet 2 ten BCKXH BDX Only applies to first bit transmitted when in Data Delay 1 BCLKX int 6 or 2 XDATDLY 01b or 10b modes DXENA 1 Delay t
72. gic one timer one APLL and other miscellaneous circuitry Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet MicroStar is a trademark of Texas Instruments Incorporated t IEEE Standard 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan Architecture ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development Characteristic data and other Specifications are subject to change without notice 35 TEXAS Copyright 1999 Texas Instruments Incorporated INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 1 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 description continued The 5421 also contains a host port interface HPI that allows the 5421 to be viewed as a memory mapped peripheral to a host processor The 5421 is pin compatible with the TMS320VC5420 Each subsystem has its separate program and data spaces allowing simultaneous accesses to program instructions and data Two read operations and one write operation can be performed in one cycle Instructions with parallel store and application specific instructions can fully utilize this architecture Furthermore data can be transferred between program and data spaces Such parallelism su
73. h DSP Subsystem BIT BIT RESET NAME VALUE FUNCTION Bank compare BNKCMP determines the external memory bank size BNKCMP is used to mask the four 15 12 BNKCMP 1111 most significant bits MSBs of an address For example if BNKCMP 1111b the four MSBs bits 12 15 are compared resulting in a bank size of 4K words Bank sizes of 4K words to 64K words are allowed Program read data read access PS DS inserts an extra cycle between consecutive accesses of 11 PS DS 1 program read and data read or data read and program read PS DS 0 No extra cycles are inserted by this feature PS DS 1 One extra cycle is inserted between consecutive data and program reads 10 9 Reserved 0 These bits are reserved and are unaffected by writes The IPIRQ bit is used to send an interprocessor interrupt to the other subsystem IPIRQ 1 sends the interrupt IPIRQ must be cleared before subsequent interrupts can be made Refer to the interrupts section for more details 7 3 Reserved 0 These bits are reserved and are unaffected by writes Bus holder BH controls the data bus holder feature BH is cleared to 0 at reset 2 BH BH 0 The bus holder is disabled 1 The bus holder is enabled When not driven the data bus PPD 15 0 is held in the previous logic level 1 Reserved 0 This bit is reserved and is unaffected by writes External bus interface off The EXIO bit controls the external bus off function EXIO 0 The ext
74. h pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 1 2H when CLKGDV is even FSRP FSXP 1 Asa SPI master BFSX is inverted to provide active low slave enable output As a slave the active low signal input on BFSX and BFSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock BCLKX LSB isu BFXL BCKXH MSB lt h te Bckx BCLKX teis BCKXL BDXHZ td BFXL BDXV gt ta BCKXL BDXV BDX Bin X n2 X 3 X na X tsu BDRV BCKXH 7 gt th BCKXH BDRV C Bi X n X X Figure 43 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 0 le th BCKXL BFXL td BFXL BCKXH BFSX BDR 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 75 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 multichannel buffered serial port timing continued timing requirements for McBSP as SPI master or slave H 0 5te co CLKSTP 106 CLKXP 11 see Figure 44 Hold time BDR valid after BCLKX high tsu BFXL BCKXL Setup time BFSX low before BCLKX low tc BCKX Cycle time BCLKX T For all SPI slave modes CLKG is programmed as 1 2 of the
75. he 5421 device READA Read program memory addressed by accumulator A and store data memory WRITA Write data to program memory addressed by accumulator A Writes not allowed for CPUs to shared program memory program memory The program memory is accessible on multiple pages depending on the XPC value Within these pages memory is accessible depending on the address range Access in the lower 32K of each page is dependent on the state of OVLY OVLY 0 Program memory is accessed externally for all values of XPC 1 Program memory is accessed from local data program DARAM for all values of XPC Access in the upper 32K of each page is dependent on the state of MP MC and the value of XPC MP NC 0 Program memory is accessed internally from shared DARAM for XPC 0 3 Program memory is accessed externally for XPC 4 127 1 Program memory is accessed externally for all values of XPC 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 data memory The data memory space is a single page of 64K Access is dependent on the address range Access in the lower 32K of data memory is always from local DARAM Access in the upper 32K of data memory is dependent on the state of DROM DROM 0 Data memory is accessed externally DROM 1 Data memory is accesse
76. he secondary function of this pin space select signal The is signal is asserted during external I O space accesses This pin is placed into the high impedance state when OFF is low This pin is also multiplexed with the general purpose I O feature and functions as the B_GPIO3 B TOUT input output signal in HPI mode Refer to the General Purpose section of this table for details on the secondary function of this pin Program and data memory strobe active in EMIF mode This pin is placed into the high impedance state when OFF is low 10 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 mee PPA18 A CLKOUT B CLKOUT ums o T Input Output S Supply 2 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 Signal Descriptions Continued MEMORY CONTROL SIGNALS CONTINUED Data ready input signal READY indicates that the external device is prepared for a bus transaction to be completed If the device is not ready READY 0 the processor waits one cycle and checks READY again The processor performs the READY detection if at least two software wait states are programmed This pin is also multiplexed with the HPI and functions as the host port data ready output in HPI mode Refer to the HPI section of this table for details on the secondary function of this pin Read write output signal R W indicates transfer direction during communicati
77. hold state and that the address data and control lines are in the high impedance state allowing them to be available to the external circuitry HOLDA also goes into the high impedance state when OFF is low CLOCKING SIGNALS Master clock output signal CLKOUT cycles at the machine cycle rate of the CPU The internal machine cycle is bounded by the falling edges of this signal The CLKOUT pin can be turned off by writing a 1 to the CLKOFF bit of the PMST register CLKOUT goes into the high impedance state when EMU1 OFF is low Input clock to the device CLKIN connects to an oscillator circuit device PLL High Impedance t This pin has an internal pullup resistor These pins are Schmitt triggered inputs This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A This pin is used by Texas Instruments for device testing and should be left unconnected This pin has an internal pulldown resistor 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 11 ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 Signal Descriptions Continued x NE met DERT MULTICHANNEL BUFFERED SERIAL PORT 0 1 AND 2 SIGNALS ADVANCE INFORMATION A BCLKROtS B BCLKROtS A BCLKR11 B BCLKR1t8 A BCLKR2t B BCLKR2t BCLKXOt B BCLKXO0t BCLKX1t B 139 A BCLKX2t8 B 238
78. ime BFSX high to BDX valid DXENA 0 Srsxed 12 td BFXH BDXV Only applies to first bit transmitted when in Data Delay 0 XDATDLY 00b mode BFSX int i DXENA 1 BFSX ext BFSX int Enable time BFSX high to BDX driven DXENA 0 ten BFXH BDX Only applies to first bit transmitted when in Data Delay 0 XDATDLY 00b mode DXENA 4 BFSX int BFSX T Polarity bits CLKRP CLKXP FSRP FSXP 0 If the polarity of any of the signals is inverted then the timing references of that signal are also inverted t T BCLKRX period 1 CLKGDV 2H C BCLKRX low pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 2H when CLKGDV is even D BCLKRX high pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 1 2H when CLKGDV is even See the TMS320C54x Enhanced Peripherals Reference Set Volume 5 literature number SPRU302 for a description of the DX enable DXENA and data delay features of the McBSP 19 1 0 1 0 5 7 2 5 6 2 2 2 4 2 2 2 2 1 2 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 71i ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 multichannel buffered serial port timing continued te BCKRX tw BCKRXH tr BCKRX tw BCKRXL BCLKR td BCKRH BFRVJ td BCKRH BFRY BFSR int th BCKRL BFRH
79. ing methods 1 If the RS pins are held low while HPIRS transitions from low to high the subsystem cores reset will be controlled by the RS A B pins When the host has finished downloading code it drives RS A B high to release the cores from reset If the RS pins are held high while HPIRS transitions from low to high the subsystems stay in reset until a HPI data write to address Ox2F occurs This means the host can download code to subsystem A and then release core A from reset by writing any data to core A address Ox2F via the HPI The host can then repeat the sequence for core B This mode allows the host to control the 5421 reset without additional hardware XIO mode ROM is mapped in if ROMEN pin 1 during reset The 5421 bootloader provides the following options for the source of code to download Parallel from 8 bit or 16 bit wide EPROM Serial boot from McBSPs 8 bit mode TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 19 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 bootloader continued GPIO register bit 7 ROMEN is used to enable disable the ROM after reset The ROMEN bit reflects the status of the ROMEN GPIOO pin for each core ROMEN 1 indicates that the ROM and the 8K word program memory block 00 E000h 00 FFFFh are not available for the CPU When ROMEN 0 this 8K word program memory is available
80. ions Dual 1 8 V Core and 3 3 V I O Power Supplies for Low Power Fast Operations 10 ns Single Cycle Fixed Point Instruction Interprocessor Communication via Two Internal 8 Element FIFOs Twelve Channels of Direct Memory Access DMA for Data Transfers With No CPU Loading Six Channels Per Subsystem With External Access Six Multichannel Buffered Serial Ports McBSPs With 128 Channel Selection Capability 3 McBSPs per Subsystem 16 Bit Host Port Interface HPI Multiplexed With External Memory Interface Pins Software Programmable Phase Locked Loop APLL Provides Several Clocking Options Requires External TTL Oscillator Includes JTAG Functionality for In Circuit Emulation On Chip Scan Based Emulation Logic IEEE Standard 1149 17 JTAG Boundary Scan Logic Two Software Programmable Timers One Per Subsystem Software Programmable Wait State Generator 14 Wait States Maximum Provided in 144 pin MicroStar Ball Grid Array GGU Suffix and 144 pin Thin Quad Flatpack TQFP PGE Suffix Packages The TMS320VC5421 fixed point digital signal processor DSP is a dual core solution running at 200 MIPS performance The 5421 consists of two DSP subsystems capable of core to core communications and a 128K word zero wait state on chip program memory shared by the two DSP subsystems Each subsystem consists of one 54x DSP core 32K word program data DARAM 32K word data SARAM 2K word ROM three multichannel serial interfaces lo
81. is a down counter which is driven by the input clock divided by 16 therefore for every 16 input clocks the PLL n PLLCOUNTT counter decrements by one The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked so that only valid clock signals are sent to the device PLL on off PLLON OFF enables or disables the PLL part of the clock generator in conjunction with the PLLNDIV PLLON OFFT bit see Table 16 Note that PLLON OFF and PLLNDIV can both force the PLL to run when PLLON OFF is high the PLL runs independently of the state of PLLNDIV 1 PLLNDIV PLLNDIV configures PLL mode when high or DIV mode when low PLLNDIV defines the frequency multiplier in conjunction with PLLDIV and PLLMUL See Table 15 Indicates the PLL mode STATUS STATUS 0 Indicates DIV mode STATUS 1 Indicates PLL mode Twhenin DIV mode PLLSTATUS is low PLLMUL PLLDIV PLLCOUNT and PLLON OFF are don t cares and their contents are indeterminate Table 15 Multiplier Related to PLLNDIV PLLDIV and PLLMUL x o x e x J 5 o Pm x 1 m hpsesmunpyo 5 1 t CLKOUT CLKIN Multiplier Indicates the default clock mode after reset Table 16 VCO Truth Table PLLON OFF PLLNDIV VCO STATE 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 39 ADVANCE INFORMATION ADVANCE INFORMATION T
82. l output current Tc Operating case temperature See Figure 21 for 3 3 V device test load circuit values 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 51 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 electrical characteristics over recommended operating case temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN UNIT V High level output voltaget Vpp 3 3 0 3 V MAX VoL Low level output voltaget loL liz Input current in high impedance Vpp Vo Vss to Vpp TRST With internal pulldown See pin descriptions With internal pullups Bus holders enabled Vpp MAX gt 0 4 35 L o Input current co CVpp 1 8 V fy 100 MHz Ippc Supply current both core CPUs Tc 25 C m i DVpp 3 3 V fclock 100 MHz Ippp Supply current pins Tc Desc IDDA Supply current PLL IDLE2 Ippc Supply current standby IDLE3 Ci Input capacitance Output capacitance All values are typical unless otherwise specified ___ __ t All input and output voltage levels except RS INTO NMI CLKIN BCLKX BCLKR HAS 5 HDS1 HDS2 and HPIRS LVTTL compatible Clock mode PLL x 1 with external source T This value is based on 50 usage of MAC and 50 usage of NOP
83. le The selection of the clock mode and the value of N is described in the software programmable phase locked loop PLL section switching characteristics over recommended operating conditions 0 5 60 see Figure 23 PARAMETER MN 4 ic CO Cycle time CLKOUT 10 terc NT ns T Multiplication factor timing requirements see Figure 23 1 5421 200 2 Integer PLL multiplier 1 15 20t 200 tec Cycle time CLKIN PLL multiplier N x 5 20 100 ns PLL multiplier N x 25 x 75 20t 50 Pulse duration CLKIN low tw CIH Pulse duration CLKIN high Multiplication factor t The multiplication factor and minimum CLKIN cycle time should be chosen such thatthe resulting CLKOUT cycle time is within the specified range tc CO t tc gt lt tw ciL 5 td CI CO 9 4 d d esse co E g tp ESES cor Figure 23 External Multiply by One Clock Timing 35 TEXAS INSTRUMENTS 54 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 external memory interface timing switching characteristics over recommended operating conditions for a memory read MSTRB 0 f see Figure 24 acuer Delay ime CLKOUT igh Delay tine td CLKL MSH
84. med as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 tT BCLKX period 1 CLKGDV 2H BCLKX low pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 2H when CLKGDV is even D BCLKX high pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 1 2H when CLKGDV is even FSRP FSXP 1 Asa SPI master BFSX is inverted to provide active low slave enable output As a slave the active low signal input on BFSX and BFSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock BCLKX LSB tsu BFXL BCKXL gt MSB gt te BCKX BR X N 4004 th BCKXH BFXL lt td BFXL BCKXL BFSX leis BCKXH BDXHZ ta BFXL BDXV gt k td BCKXH BDXV BDX C Binz n2 X n3 X n X tsu BDRV BCKXL k BDR _Bito C Bini 20 X n X n Figure 45 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 1 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 77 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 HPI16 timing switching characteristics over recommended operating conditionsti H 0 5te
85. n this mode When HMODE is high it selects the HPI nonmultiplexed mode HPI nonmultiplexed mode allows hosts with separate address data buses to access the HPI address range by way of the 18 bit address bus and the HPI data HPID register via the 16 bit data bus Host to DSP and DSP to host interrupts are not supported in this mode SUPPLY PINS Dedicated power supply that powers the PLL AVpp 1 8 V AVpp can be connected to CVpp Dedicated clean power supply that powers the core CPUs CVpp 1 8 V Dedicated dirty power supply that powers the I O pins DVpp 3 3 V Digital ground Dedicated ground plane for the device TEST PIN No connection T Input O Output S Supply Z EMULATION TEST PINS Standard test clock This is normally a free running clock signal with a 50 duty cycle Changes on the test access port TAP of input signals TMS and TDI are clocked into the TAP controller instruction register or selected test data register on the rising edge of TCK Changes at the TAP output signal TDO occur on the falling edge of TCK Test data input Pin with an internal pullup device TDI is clocked into the selected register instruction or data on a rising edge of TCK Test data pin The contents of the selected register is shifted out of TDO on the falling edge of TCK TDO is in high impedance state except when the scanning of data is in progress These pins are placed into high impedance state when OFF is
86. ns Accesses without a grant will be allowed but do not show up on the device pins TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 33 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 DMA accesses to external memory continued 54x cLEAD CPU DSP Subsystem B NEED INE XIO Core feq 55 DMA_REQUEST DMA_REQUEST lt 54x cLEAD CPU DSP Subsystem B IEEE XIO Core IEEE GRANT GRANT B GPIO Control GPIO Control Register Register DSP Subsystem A DSP Subsystem B EMIF Controller U DMA REQ A e 4 XDMA DS DMA ARB DSP Subsystem A Subsystem B DMA GRANT A DMA GRANT B XHOLDA Figure 15 Arbitration Between XIO and xDMA for External Access The HM bit in the ST1 indicates whether the processor continues internal execution when acknowledging an active HOLD signal HM 0 the processor continues execution from internal program memory but places its external interface in the high impedance state When 1 the processor halts internal execution To ensure that proper arbitration occurs the HM bit should be set to 0 in the memory mapped ST1 registers for both CPUs To allow the DMA access to extended data pages the SLAXS DLAXs bits are added to the DMMCRn register
87. o o 5 o 1 5 2 30 th HSL HBV Hold time HAD valid after HAS falling edget 12H 14H 18H 20H 6H 8H 2 2 12H 18H 26H 8H ojo 5 THAD stands for HCNTLO HCNTL1 and HR W t DS refers to the logical OR of HCS and HDS gt 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 79 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 16 timing continued y tsu HSL DSL t tsu HBV HSL ha tc DSH DSH WS No No 4 twDSH th HSL HBV lt tw DSL gt HR W HCNTL 1 0 HD 15 0 HRDY HR W HCNTL 1 0 HD 15 0 HRDY td DSL HDV1 T td DSL HDDj lt h th DSH HDV R td DSL HDV2 EE tv HYH HDV td DSH HYH td DSL HYL P Figure 46 Multiplexed Read Timings Using HAS tsu HBV DSL P th DSL HBV td DSL HDV1 T ta DsL HDDj k tv HYH HDV 4 tc DSH DSH t 4 iw psi K th DSH HDV R td DSL HDV2 XD td DSH HYH ta DSL HYL gt Figure 47 Multiplexed Read Timings With HAS Held High 80 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9
88. obal memory transfer FIFO data communications The subsystems FIFO communications interface is shown in the 5421 functional block diagram Figure 1 Two unidirectional 8 word deep FIFOs are available in the device for efficient interprocessor communication one configured for core A to core B data transfers and the other configured for core B to core A data transfers Each subsystem by way of DMA control can write to its respective output data FIFO and read from its respective input data FIFO The FIFOs are accessed using the DMAs I O space which is completely independent of the CPU I O space The DMA transfers to or from the FIFOs be synchronized to receive FIFO not empty and transmit FIFO not full events providing protection from overflow and underflow Subsystems can interrupt each other to flag when the FIFOs are either full or empty The interprocessor interrupt request bit IPIRQ bit 8 in the BSCR register BSCR 8 is set to 1 to generate a PINT in the other subsystem s IFR 14 See the interrupts section for more information DMA global memory transfers The 5421 enables each subsystem to transfer data directly between the memories that are CPU local DMA global memory transfers The DMA global memory map is shown in Figure 13 chip subsystem ID Register The chip subsystem ID Register CSIDR is a read only memory mapped register located at 3Eh within each DSP subsystem This register contains three elements for ele
89. og Data OVLY 1 External OVLY 0 00 7FFF On Chip DARAM A B 32K Words Prog Data OVLY 1 External OVLY 0 01 7FFF 00 8000 On Chip Shared DARAM 0 24K Words Prog Only Shared 0 00 DFFF 00 E000 Reserved 00 F7FF 00 FFFF _ ROMEN 1 t 01 FFFF 01 8000 On Chip Shared DARAM 1 32K Words Prog Only Shared 1 extended On Chip DARAM 5 32K Words Prog Data OVLY 1 External OVLY 0 On Chip DARAM 85 32K Words Prog Data OVLY 1 Externalt External OVLY 0 03 Shared DARAM 2 32K Words Prog Only Shared 2 extended 03 8000 On 8000 On Chip Shared DARAM 3 32K Words t Prog Only External Shared 3 03 FFFF On FFFF extended 4 127 T ROM enabled after reset When cLEAD PMST register bit MP MC 0 and an address is generated outside the on chip memory bound or the address reach i e XPC gt 3h access is always external if XIO 1 Pages 8 127 are mapped over pages 4 7 When XIO 1 and MP MC 1 program pages 0 1 2 and 3 are external Pages 4 127 are mapped over pages 0 3 On chip DARAM A and SARAM A are for core A Likewise on chip DARAM B and SARAM B are for core B NOTES A Clearing the ROMEN bit GPIO 7 enables 8K word block 0 000 OFFFFh of DARAM B All external accesses require the XIO pin to be high C CPU I O space is a single page of 64
90. on to an external device R W is normally in the read mode high unless it is asserted low when the DSP performs a write operation This pin is also multiplexed with the HPI and functions as the host port read write input in HPI mode Refer to the HPI section of this table for details on the secondary function of this pin This pin is placed into the high impedance state when OFF is low I O space memory strobe External I O space is accessible by the CPU and the direct memory access DMA controller The DMA has its own dedicated I O space that is not accessible by the CPU This pin is also multiplexed with the general purpose I O feature and functions as the TOUT signal in HPI mode Refer to the General Purpose section of this table for details on the secondary function of this pin This pin is placed into the high impedance state when OFF is low PRIMARY For HPI access 0 SELA B is an input See Table 3 for a truth table of SELA B HMODE and XIO pins and functionality SELA B For externalmemory accesses XIO 1 SELA B is multiplexed as output PPA18 See the PPA signal descriptions These pins are placed into the high impedance state when OFF is low Hold HOLD is asserted to request control of the address data and control lines When acknowledged these lines go into the high impedance state Hold acknowledge HOLDA indicates to the external circuitry that the processor is in a
91. ost C5000 devices have only the internal CPU clock as a possible source because the CLKS pin is not implemented on most device packages To accomodate applications that require an external reference clock for the sample rate generator the 5421 McBSPs allow either the receive clock pin BCLKR or the transmit clock pin BCLKX to be configured as the input clock to the sample rate generator This enhancement is enabled through two register bits pin control register PCR bit 7 enhanced sample clock mode SCLKME and sample rate generator register 2 SRGR2 bit 13 McBSP sample rate generator clock mode CLKSM SCLKME is an addition to the PCR contained in the McBSPs on previous C5000 devices The new bit layout of the PCR is shown in Figure 8 For a description of the remaining bits see TMS320C54x DSP Reference Set Volume 5 Enhanced Peripherals literature number SPRU302 15 14 13 12 11 10 9 8 R 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 SCLKME CLKS STAT Dx STAT DR_STAT FsxP FSR CLKXP CLKRP RW 0 R 0 R 0 R 0 RW 0 RW 0 RW 0 RW 0 Note R Read W Write 0 Value at reset Figure 8 Pin Control Register PCR SPI is a trademark of Motorola Incorporated TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 27 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 multichannel buffered serial port McBSP continu
92. pports a powerful set of arithmetic logic and bit manipulation operations that can all be performed in a single machine cycle The 5421 includes the control mechanisms to manage interrupts repeated operations and function calls In addition the 5421 has 128K words of on chip program memory that can be shared between the two subsystems The 5421 is intended as a high performance low cost high density DSP for remote data access or voice over IP subsystems It is designed to maintain the current modem architecture with minimal hardware and software impacts thus maximizing reuse of existing modem technologies and development efforts NOTE This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview literature number SPRU307 migration from the 5420 to the 5421 Customers who are migrating from the 5420 to the 5421 need to take into account the following differences between the two devices The memory structure of the 5421 has been changed to incorporate 128K x 16 bit words of shared memory The DMA of the 5421 has been enhanced to provide access to external as well as internal memory The HPI and DMA memory maps have been changed to incorporate the new memory 5421 2K x 16 bit words of ROM have been added to the 5421 for bootloading purposes only The VCO pin on the 5420 has been replaced with the HOLDA pin on the 5421 and the HOLD pin was added to the 5421 at a previously unus
93. programmable as an input or output by the direction bit DIRn Data is either driven or read from the data bit field DATn DIR3 has no affect when TOUT 1 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 37 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 general purpose I O continued 2 is a special case where the logic level determines the operation of BIO conditional instructions on the CPU GPIO2 is always mapped as a general purpose I O the BIO function exists when this pin is configured as an input hardware timer The 54x devices feature a 16 bit timing circuit with a 4 bit prescaler The timer counter decrements by one at every CLKOUT cycle Each time the counter decrements to zero a timer interrupt is generated The timer can be stopped restarted reset or disabled by specific status bits The timer output pulse is driven on GPIO3 when the TOUT bit is set to one in the general purpose I O control register The device must be in HPI mode XIO 0 to drive TOUT on the GPIOS pin software programmable phase locked loop PLL The clock generator provides clocks to the 5421 device and consists of a phase locked loop PLL circuit The clock generator requires a reference clock input which must be provided by using an external clock source The reference clock input is then divided by two DIV mode to generate clocks for the
94. rved McBSP DXR DRR MMRegs Only On Chip DARAM A 32K Words Prog Data Subsystem A On Chip SARAM A 32K Words Data Only Subsystem A Hex 01 0000 017FFF 01 8000 01 FFFF Page 1 On Chip Shared DARAM 0 32K Words Program Only Shared 0 On Chip Shared DARAM 1 32K Words Program Only Shared 1 All local memory is available to the HPI The encoder maps CPU A Data Page 0 into the HPI Page 0 CPU B Data Page 0 is mapped into the HPI Page 2 Pages 1 and 3 are the on chip shared program memory Hex 02 0000 02 001F 02 0020 02 005F 02 0060 02 7FFF 02 8000 02 FFFF Page 2 Reserved McBSP DXR DRR MMRegs Only On Chip DARAM B 32K Words Prog Data Subsystem B On Chip SARAM B 32K Words Data Only Subsystem B Hex 03 0000 03 7FFF 03 8000 03 FFFF Page 3 On Chip Shared DARAM 2 32K Words Program Only Shared 2 On Chip Shared DARAM 3 32K Words Program Only Shared 3 In pages 00 and 02 in the range of 0020 005F only the following memory mapped registers are accessible 20 21 30 31 40 41 read only 22 23 32 33 42 43 write only Figure 6 Memory Map Relative to Host Port Interface HPI16 24 Ji TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 16 memory map continued HP Some of the features of
95. s are reserved and are unaffected by writes Software wait state multiplier Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2 WSM 0 SMS SWSM 0 wait state base values are unchanged multiplied by 1 SWSM 1 wait state base values are multiplied by 2 for a maximum of 14 wait states programmable bank switching Programmable bank switching can be used to insert one cycle automatically when crossing memory bank boundaries inside program memory or data memory space One cycle can also be inserted when crossing from program memory space to data memory space 54x one program memory page to another program memory page This extra cycle allows memory devices to release the bus before other devices start driving the bus thereby avoiding bus contention The size of the memory bank for the bank switching is defined by the bank switching control register BSCR as shown in Figure 5 The BSCR of a particular DSP subsystem A or B is used for the external memory interface based on the xDMA XIO arbitration logic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W LEGEND R Read W Write Figure 5 BSCR Register Bit Layout for Each DSP Subsystem 35 TEXAS INSTRUMENTS 22 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 programmable bank switching continued Table 6 BSCR Register Bit Functions for Eac
96. s have the same CPU structure however they have different on chip peripherals connected to their CPUs The on chip peripheral options provided are Software programmable wait state generator Programmable bank switching Parallel I O ports Multichannel buffered serial ports McBSPs A hardware timer A software programmable clock generator using a phase locked loop PLL 20 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 software programmable wait state generators The software programmable wait state generator can be used to extend external bus cycles up to fourteen machine cycles to interface with slower off chip memory and I O devices The software wait state register SWWSR controls the operation of the wait state generator The SWWSR of a particular DSP subsystem A or B is used for the external memory interface depending on the state of the xDMA XIO arbitration logic see Direct Memory Access DMA Controller section and Table 13 The 14 least significant bits LSBs of the SWWSR specify the number of wait states 0 7 to be inserted for external memory accesses to five separate address ranges This allows a different number of wait states for each of the five address ranges Additionally the software wait state multiplier SWSM bit of the software wait state control register SWCR defines a multiplication factor of 1 or 2
97. ss over the BDR pin When not being used as data receive synchronization pins these pins can be used as general purpose I O by setting RIOEN 1 These pins are placed into the high impedance state when OFF is low Buffered serial port frame synchronization pin for transmitting data The BFSX pulse initiates the transmit data process over the BDX pin If RS is asserted when BFSX is configured as output then BFSX is turned into input mode by the reset operation When not being used as data transmit synchronization pins these pins can be used as general purpose I O by setting XIOEN 1 These pins are placed into the high impedance state when OFF is low HOST PORT INTERFACE HPI SIGNALS PRIMARY These pins are multiplexed with the external interface pins and are used by the PPA 17 0 HPI when the subsystem is in HPI mode XIO 0 MP MC 0 See the PPA signal descriptions These pins are placed into the high impedance state when OFF is low T Input O Output S Supply Z High Impedance This pin has an internal pullup resistor These pins are Schmitt triggered inputs This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A This pin is used by Texas Instruments for device testing and should be left unconnected This pin has an internal pulldown resistor 12 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS320VC5421 DI
98. t pending is disabled masked IFR IMR McBSP_1 has a transmit interrupt pending is enabled IFR IMR DMA Channel 3 has no interrupt pending is disabled masked IFR IMR DMA Channel 3 has an interrupt pending is enabled IFR IMR McBSP_1 has no receive interrupt pending is disabled masked IFR IMR McBSP_1 has a receive interrupt pending is enabled IFR IMR DMA Channel 2 has no interrupt pending is disabled masked IFR IMR DMA Channel 2 has an interrupt pending is enabled IFR IMR Host port interface has no DSPINT interrupt pending is disabled masked IFR IMR Host port interface has an DSPINT interrupt pending is enabled Register bit is reserved IFR IMR McBSP_2 has no transmit interrupt pending is disabled masked IFR IMR McBSP_2 has a transmit interrupt pending is enabled IFR IMR DMA Channel 1 has no interrupt pending is disabled masked IFR IMR DMA Channel 1 has an interrupt pending is enabled IFR IMR McBSP_2 has no receive interrupt pending is disabled masked IFR IMR McBSP_2 has a receive interrupt pending is enabled IFR IMR DMA Channel 0 has no interrupt pending is disabled masked IFR IMR DMA Channel 0 has an interrupt pending is enabled IFR IMR McBSP_0 has no receive interrupt pending is disabled masked IFR IMR McBSP 0 has a receive interrupt pending is enabled IFR IMR McBSP_0 has no receive interrupt pending is disabled masked IFR IMR McBSP 0 has a receive interrupt pending is enabled
99. ter The states of GPIO pins inputs can be read by reading the GPIO register The GPIO direction is also programmable by way of the DIRn field in the GPIO register General purpose I O These pins can be configured like GPIO0 GPIO1 however as an input the pins operate as the traditional branch control bit BIO If application code does not perform BIO conditional instructions these pins operate as general inputs PRIMARY When the device is in HPI mode and HMODE 0 multiplexed these pins act IOSTRB according to the general purpose I O control register TOUT bit must be to 1 to drive the timer output on the pin IF TOUT 0 then these pins are general purpose I Os In EMIF mode XIO 1 these signals are active during I O space accesses s LE CONTROL SIGNALS Program space select signal The PS signal is asserted during external program space accesses This pin is placed into the high impedance state when OFF is low This pin is also multiplexed with the HPI andfunctions asthe HDS1 data strobe input signalin HPI mode Refer to the HPI section of this table for details on the secondary function of this pin Data space select signal The DS signal is asserted during external data space accesses This pin is placed into the high impedance state when OFF is low This pin is also multiplexed with the HPI andfunctions as the HDS2 data strobe input signalin HPI mode Refer to the HPI section of this table for details on t
100. ter BCLKX low T 5 T 5 Delay time BFSX low to BCLKX high C 5 C 5 Delay time BCLKX high to BDX valid 12 dis BCKXL BDXHZ low C 2 C 10 Disable time BDX high impedance following last data bit from BFSX tdis BFXH BDXHZ high td BFXL BDXV Delay time BFSX low to BDX valid 4 4 8H 17 T For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 tT BCLKX period 1 CLKGDV 2H low pulse width T 2 when CLKGDV is odd or zero and CLKGDV 2 2H when CLKGDV is even FSRP FSXP 1 As a SPI master BFSX is inverted to provide active low slave enable output As a slave the active low signal input on BFSX and BFSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP 1 BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock BCLKX Disable time BDX high impedance following last data bit from BCLKX o 2 LSB tsu BFXL BCKXH gt MSB BCLKX k 4 V th BCKXL BFXL gt td BFXL BCKXH 1 1 BFSX gt tdis BFXH BDXHZ td BFXL BDXV e tdis BCKXL BDXHZ e td BCKXH BDXV BDX C Bin X n2 X n X na X t lt th BCKXL BDRV BDR C Bin n2 X X
101. th the external memory interface and is only used by the HPI when the interface is in HPI mode XIO pin is low HRDY is placed into the high impedance state when OFF is low This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A This pin is used by Texas Instruments for device testing and should be left unconnected This pin has an internal pulldown resistor 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 13 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 C wwe 11 E Signal Descriptions Continued DESCRIPTION HOST PORT INTERFACE HPI SIGNALS CONTINUED PRIMARY Host interrupt pin HPI can interrupt the host by asserting this low The host can PPAO clear this interrupt by writing a 1 to the HINT bit of the HPIC register Only PPA1 supported in HPI multiplexed address data mode HMODE pin is low These pins are placed into the high impedance state when OFF is low Host port interface HPI reset pin This signal resets the host port interface and both subsystems Host mode select When this pin is low it selects the HPI multiplexed address data mode The multiplexed address data mode allows hosts with multiplexed address data lines access to the HPI registers HPIC HPIA and HPID Host to DSP and DSP to host interrupts are supported i
102. the 18 bit HA address bus The host initiates the access with the strobe signals HDS1 HDS2 HCS and controls the direction of the access with the HR W signal The 16 can stall host accesses via the HRDY signal Note that the HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available All host accesses initiate a DMA read or write access Figure 7 shows a block diagram of the 16 in nonmultiplexed mode HOST HD 15 0 Data 15 0 HPID 15 0 Address n 0 Internal memory R W 54x Data strobes CPU Ready Figure 7 Interfacing to the HPI 16 in Non Multiplexed Mode other 16 system considerations operation during IDLE The 16 can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns on relevant clocks to perform a synchronous memory access and then turns the clocks back off to save power The DSP CPU does not wake up from the IDLE mode during this process downloading code during reset The 16 can download code while the DSP is in reset However the system provides a pin HPIRS that provides a way to take the HPI16 module out of reset while leaving the DSP in reset The maximum HPI16 data rate is 33 MBps assuming no other DMA activity 100 MIPS DSP subsystem emulation considerations The HPI16 can continue operation even when the DSP CPU is halted due to debugger breakpoints or other emulation
103. the IPIRQ field Figure 20 shows the bit layout of the IMR and the IFR Table 23 describes the bit functions For example if subsystem A is required to notify subsystem B of a completed task subsystem A must write a 1 to the IPIRQ field to generate a IPINT interrupt on subsystem B On subsystem B the IPINT interrupt is latched in IFR 14 Figure 5 shows the bit layout of the BSCR and Table 6 describes the bit functions 15 14 13 12 11 10 9 8 XINT1 or RINT1 or R W R W R W R W R W 7 6 5 4 3 2 1 0 XINT2 or RINT2 or INT1 INTO R W R W R W R W R W R W R W LEGEND R Read W Write Figure 20 Bit Layout of the IMR and IFR Registers for Subsystems A and B 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 47 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 interrupts continued Table 23 Bit Functions for IMR and IFR Registers for Each DSP Subsystem IFR IMR Interprocessor IRQ has no interrupt pending is disabled masked IFR IMR Interprocessor IRQ has an interrupt pending is enabled IFR IMR DMA Channel 5 has no interrupt pending is disabled masked IFR IMR DMA Channel 5 has an interrupt pending is enabled IFR IMR DMA Channel 4 has no interrupt pending is disabled masked IFR IMR DMA Channel 4 has an interrupt pending is enabled IFR IMR McBSP_1 has no transmit interrup
104. ts The DSYN bit field of the DMA channel x sync select and frame count DMSFOx register selects the synchronization event for a channel The list of possible events and the DSYN values are shown in Table 10 Table 10 DMA Synchronization Events DMA channel interrupt selection The DMA controller can generate a CPU interrupt for each of the six channels However channels 0 1 2 and3 are multiplexed with other interrupt sources DMA channels 0 and 1 share an interrupt line with the receive and transmit portions of McBSP2 IMR IFR bits 6 and 7 and DMA channels 2 and 3 share an interrupt line with the receive and transmit portions of McBSP1 IMR IFR bits 10 and 11 When the 5421 is reset the interrupts from these four DMA channels are deselected The INTSEL bit field in the DMA channel priority and enable control DMPREC register can be used to select these interrupts as shown in Table 11 Table 11 DMA Channel Interrupt Selection INTSEL Value IMR IFR 6 IMR IFR 7 IMR IFR 10 IMR IFR 11 00b reset BRINT2 BXINT2 BRINT1 BXINT1 BRINT2 BXINT2 DMAC2 DMAC3 DMACO DMAC1 DMAC2 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 35 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 DECEMBER 1999 subsystem communications The 5421 device provides two options for efficient core to core communications Core to core FIFO communications DMA gl
105. ubsystem ADDRESS DEC HEX DESCRIPTION TREG Temporary Register PMST Processor Mode Status Register 1 jReevd D 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 41 ADVANCE INFORMATION xao mo PD o 7 SCR SWR 7 gt Rm EI 5 sese E Srs 7 SPS 5 Srs gt 7 co lt a lt pran xm 7 _ T OMPREC EU EXT NIMM TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 memory mapped registers continued Table 19 Peripheral Memory Mapped Registers for Each DSP Subsystem ADDRESS DEC HEX DESCRIPTION wesp Daa 21 Receive Register O 22 McBSP 0 Data TransmitRegister2 35 2 MSP 0 Data TransmitRegister 11111111 35 24 25 38 WmerGoweRegser se 2 ns _ o Software WaitSialeRegsier 29 Bank Switching Convoi Register lt 7A Reewd _ _ 25 Software WaitState 26 HPI Register HMODE 0ony s ess 2 bata s SWWSR BSCR SWCR HPIC D
106. used as a pointer to select a particular register within the subbank while the DMA subbank data DMSD register or the DMA subbank data register with autoincrement DMSDI is used to access read or write the selected register 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 43 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 DMA subbank addressed registers continued When the DMSDI register is used to access the subbank the subbank address is automatically postincremented so that a subsequent access affects the next register within the subbank This autoincrement feature is intended for efficient successive accesses to several control registers If the autoincrement feature is not required the DMSDN register should be used to access the subbank Table 21 shows the DMA controller subbank addressed registers and their corresponding subaddresses Table 21 DMA Subbank Addressed Registers DMSFCO 56h 57h 03h DMA channel 0 sync select and frame count register DMCTR2 56h 57h 0Ch DMA channel 2 element count register DMDST3 56h 57h 10h DMA channel 3 destination address register DMSRC4 56h 57h 14h DMA channel 4 source address register DMMCR4 56h 57h 18h DMA channel 4 transfer mode control register DMSFC5 56h 57h 1Ch DMA channel 5 sync select and frame count register DMSRCP 56h 57h 1Eh DMA source program page address common channel DMDSTP 56h 57h D
107. ware programmable phase locked loop PLL section switching characteristics over recommended operating conditions H 0 5 60 see Figure 22 and the recommended operating conditions table 5421 200 PARAMETER UNIT MIN TYP MAX Cycle time CLKOUT 40 2tc Cl Cycle time CLKOUT bypass mode 40 2tc Cl t 1 s tw COH Pulse duration CLKOUT high H 2 H H ns t This device utilizes a fully static design and therefore can operate with approaching ee The device is characterized at frequencies approaching 0 Hz timing requirements see Figure 22 tw CIL Pulse duration CLKIN low tw CIH Pulse duration CLKIN high T This device utilizes a fully static design and therefore can operate with approaching The device is characterized at frequencies approaching 0 Hz tw CIH rl gt lt 6 lt tec gt n Bs CLKIN t taco tco DNE td CIH CO TNI u tr CO oor N Ny N Z N Figure 22 External Divide by Two Clock Timing 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 53 ADVANCE INFORMATION ADVANCE INFORMATION TMS320VC5421 DIGITAL SIGNAL PROCESSOR 5 5098 DECEMBER 1999 multiply by N clock option PLL Enabled The frequency of the reference clock provided at the CLKIN pin can be multiplied by a factor of N to generate the internal machine cyc

TEXAS INSTRUMENTS TMS320VC5421 DATA SHEET(1)(1)

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