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TEXAS INSTRUMENTS TMS320DM642 datasheet

1. HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0184 8244 MAR145 Controls EMIFA CE1 range 9100 0000 91FF FFFF 0184 8248 MAR146 Controls EMIFA CE1 range 9200 0000 92FF FFFF 0184 824C MAR147 Controls EMIFA CE1 range 9300 0000 93FF FFFF 0184 8250 MAR148 Controls EMIFA CE1 range 9400 0000 94FF FFFF 0184 8254 MAR149 Controls EMIFA CE1 range 9500 0000 95FF FFFF 0184 8258 MAR150 Controls EMIFA CE1 range 9600 0000 96FF FFFF 0184 825C MAR151 Controls EMIFA CE1 range 9700 0000 97FF FFFF 0184 8260 MAR152 Controls EMIFA CE1 range 9800 0000 98FF FFFF 0184 8264 MAR153 Controls EMIFA CE1 range 9900 0000 99FF FFFF 0184 8268 MAR154 Controls EMIFA CE1 range 9A00 0000 9AFF FFFF 0184 826C MAR155 Controls EMIFA CE1 range 9800 0000 9BFF FFFF 0184 8270 MAR156 Controls EMIFA CE1 range 9C00 0000 9CFF FFFF 0184 8274 MAR157 Controls EMIFA CE1 range 9D00 0000 9DFF FFFF 0184 8278 MAR158 Controls CE1 range 9 00 0000 9EFF FFFF 0184 827C MAR159 Controls EMIFA CE1 range 9F00 0000 9FFF FFFF 0184 8280 MAR160 Controls EMIFA CE2 range A000 0000 AOFF FFFF 0184 8284 MAR161 Controls EMIFA CE2 range A100 0000 A1FF FFFF 0184 8288 MAR162 Controls EMIFA CE2 range A200 0000 A2FF FFFF 0184 828C MAR163 Controls EMIFA CE2 range A300 0000 A3FF FFFF 0184 8290 MAR164 Controls EMIFA CE2 range A400
2. SIGNAL IPD NAME wo weus DESCRIPTION EMIFA 64 bit DATA AED63 AF24 AED62 AF23 AED61 AE23 AED60 AD23 AED59 AD22 AED58 AE22 AED57 AD21 AED56 AE21 AED55 AC21 AED54 AF21 AED53 AD20 AED52 AE20 AED51 AC20 AED50 AF20 AED49 AC19 AED48 AD19 AED47 W23 AED46 Y26 AED45 Y23 AED44 Y25 AED43 Y24 AED42 AA26 2 IPU EMIFA external data AED41 AA23 AED40 AA25 AED39 AA24 AED38 AB23 AED37 AB25 AED36 AB24 AED35 AC26 AED34 AC25 AED33 AD25 AED32 AD26 AED31 C26 AED30 C25 AED29 D26 AED28 D25 AED27 E24 AED26 E25 AED25 F24 AED24 F25 AED23 F23 AED22 F26 AED21 G24 AED20 G25 Submit Documentation Feedback Device Overview 35 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL TYPE PD DESCRIPTION NAME NO IPU AED19 G23 AED18 G26 AED17 H23 AED16 H24 AED15 C19 AED14 D19 AED13 A20 AED12 D20 AED11 B20 AED10 C20 2 external data AED9 A21 AED8 D21 AED7 B21 AED6 C21 AED5 A23 AED4 C22 AED3 B22 AED2 B23 AED1 A24 AED0 B24 MANAGEMENT DATA INPUT OUTPUT MDIO R5 2 IPD PCI serial interface clock
3. MULTIPLEXED PINS DEFAULT DEFAULT NAME NO FUNCTION SETTING DESCRIPTION VP1D 8 CLKR1 AD8 VP1D 7 FSR1 By default the McBSP1 peripheral function is enabled VP1DIGJ DR1 S pasa VP1EN bit 0 disabled upon reset MCBSP1EN bit 1 VP1D S CLKS1 AE7 function MCBSP1EN bit 1 EE enabled o enable the Video Port 1 data pins the it in the VP1D 4 DX1 AC6 PERCFG register must be set to a 1 VP1D S FSX1 AD6 VP1D 2 CLKX1 AE6 VPOD 19 AHCLKXO AC12 VPOD 18 AFSXO AD12 By default no function is enabled upon reset VPOD 17 ACLKXO AB13 To enable the Video Port 0 data pins the VPOEN bit in the VPOD 16J AMUTEO AC13 VPOEN bit 0 disabled PERCFG register must be set to a 1 McASPO control MCASPOEN bit 0 pins are disabled VPOD 15 AMUTEINO AD13 disabled VPODI14 AHCLKRO AB14 To enable the McASPO control pins the MCASPOEN bit in 14 the PERCFG register must be set to a 1 VPO upper data VPOD 13 AFSRO AC14 pins are disabled VPOD 12 ACLKRO AD14 VPOD 8 CLKRO AE15 VPOD 7 FSRO AB16 C By default the McBSPO peripheral function is enabled VPODI6 DRO eee VPOEN bit 0 disabled upon reset MCBSPOEN bit 1 VPOD S CLKSO AD16 functions MCBSPOEN bit 1 M enabled o enable the Video Port 0 data pins the it in the VPODIA4J DXO AE16 PERCFG register must be set to a
4. VPO VP1 ACRONYM DESCRIPTION 01C4 0108 01C4 4108 01C4 8108 ASTRTx Video Capture Channel A Field 1 Start Register 01C4 010C 01C4 410C 01C4 810C ASTOPx Video Capture Channel A Field 1 Stop Register 0104 0110 01C4 4110 01C4 8110 ASTRTx Video Capture Channel A Field 2 Start Register 0104 0114 0104 4114 0104 8114 ASTOPx Video Capture Channel A Field 2 Stop Register 0104 0118 01C4 4118 01C4 8118 AVINTx Video Capture Channel A Vertical Interrupt Register 0104 011C 0104 411C 01C4 811C VC ATHRLDx Video Capture Channel A Threshold Register 0104 0120 01 4 4120 01C4 8120 AEVTCTx Video Capture Channel A Event Count Register 0104 0140 01 4 4140 01C4 8140 VC BSTATx Video Capture Channel B Status Register 0104 0144 0104 4144 01C4 8144 VC BCTLx Video Capture Channel B Control Register 0104 0148 0104 4148 01C4 8148 VC BSTRTx Video Capture Channel B Field 1 Start Register 0104 014C 01 4 414C 01C4 814C BSTOPx Video Capture Channel B Field 1 Stop Register 01C4 0150 01C4 4150 01C4 8150 VC BSTRTx Video Capture Channel B Field 2 Start Register 0104 0154 01 4 4154 01C4 8154 BSTOPx Video Capture Channel B Field 2 Stop Register 0104 0158 0104 4158 01C4 8158 VC BVINTx Video Capture Channel B Vertical Interrupt Register 01C4 015C 01C4 415C 01C4 815C VC BTHRLDx Video Capture Channel B Threshold Register 01C4 0160 01
5. SIGNAL IPD TYPE 2 DESCRIPTION NAME NO IPU HD31 AD31 MRCLK 9 G1 HD30 AD30 MCRS 9 H3 HD29 AD29 MRXER 9 G2 HD28 AD28 MRXDV 9 J4 HD27 AD27 MRXD3 9 H2 HD26 AD26 MRXD2 9 J3 HD25 AD25 MRXD1 9 J1 HD24 AD24 MRXDO 9 C C 5 3G Host port data 1 0 2 default or PCI data address bus I O Z or EMA HD23 AD23 9 K1 transmit receive or control pins CLK SE As HPI data bus PCI EN pin 0 HD21 AD21 MCOL 9 K2 e Used for transfer of data address and control HD20 AD20 MTXEN 9 L3 e Host Port bus width user configurable at device reset via a 10 resistor HD19 AD19 MTXD3 9 L2 pullup pulldown resistor on the HD5 pin HD18 AD18 MTXD2 3 M4 As PCI data address bus PCI EN pin 1 HD17 AD17 MTXD1 3 M2 e Used for transfer of data and address HD16 AD16 MTXDO0 3 M3 Boot Configuration HD15 AD15 9 13 10 2 e HD5 pin 0 HPI operates as 16 HPI bus is 16 bits wide HD 15 0 pins are used and the remaining HD14 AD140 Ui HD 31 16 pins are reserved pins in the high impedance state HD13 AD13 9 U3 e HD5 pin 1 HPI operates as HPI32 HD12 AD12 9 U2 HPI bus is 32 bits wide All HD 31 0 pins are used for host port operations HD11 AD11 9 U4 For superset devices like DM642 the HD31 AD31 through HD16 AD16 pins can HD10 AD10 9 V1 also function as EMAC transmit receive or control pins when PCI EN pin 0 3 3
6. NO C W AIR FLOW m s 1 1 Junction to case 3 3 N A 2 Junction to board 7 46 N A 3 17 4 00 J 4 14 0 0 5 ROJA Junction to free air 5 12 3 1 0 6 10 8 2 00 7 0 37 000 8 T mem 0 47 0 5 Si unction to package to 0 57 1 0 10 0 7 2 00 11 11 4 oo 12 11 0 5 Junction to board 13 10 7 1 0 14 10 2 2 00 1 m s meters per second 6 2 Packaging Information The following packaging information and addendum reflect the most current released data available for the designated device s This data is subject to change without notice and without revision of this document Submit Documentation Feedback Mechanical Data 169 X3 Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 2 Feb 2008 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan 2 Lead Ball Finish MSL Peak Temp 9 Type Drawing Qty TMS320DM642AGDK5 ACTIVE FCBGA GDK 548 60 TBD SNPB Level 4 220C 72 HR TMS320DM642AGDK6 ACTIVE FCBGA GDK 548 60 TBD SNPB Level 4 220C 72 HR TMS320DM642AGDK7 ACTIVE FCBGA GDK 548 60 TBD SNPB Level 4 220C 72 HR TMS320DM642AGDKA5 ACTIVE FCBGA GDK 548 60 TBD SNPB Level 4 220C 72 HR TMS320DM642AGDKA6 ACTIVE FCBGA GDK 548 60 TBD SNPB Level 4 220C 72 HR TMS320DM642AGNZ5 ACTIVE FCBGA
7. NO C W AIR FLOW m s 1 1 38 Junction to case 3 3 N A 2 Junction to board 7 46 N A 3 17 4 00 4 14 0 0 5 Junction to free air 5 12 3 1 0 6 10 8 2 00 7 0 37 00 8 Psi indus kanei 0 47 0 5 si unction to package to ag ME 0 57 1 0 10 0 7 2 00 11 11 4 oo 12 11 0 5 Psijg Junction to board 13 10 7 1 0 14 10 2 2 00 1 m s meters per second Table 6 3 Thermal Resistance Characteristics S PBGA Package ZDK NO C W AIR FLOW m s 1 38 Junction to case 3 3 N A 2 Junction to board 7 92 N A 1 m s meters per second 168 Mechanical Data Submit Documentation Feedback d Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 6 3 Thermal Resistance Characteristics S PBGA Package ZDK continued NO C W AIR FLOW m s 3 18 2 00 4 15 3 0 5 ROJA Junction to free air 5 13 7 1 0 26 12 2 2 00 7 0 37 00 8 Psi p kadet 0 47 0 5 si unction to package to 9 0 57 1 0 10 0 7 2 00 11 11 4 00 12 11 0 5 Psijg Junction to board 13 10 7 1 0 14 10 2 2 00 Table 6 4 Thermal Resistance Characteristics S PBGA Package ZNZ
8. 500 600 720 UNIT MAX MAX 1 Lcu MDCLK Cycle time MDCLK 400 ns 2 twMDCLK Pulse duration MDCLK high low 180 ns 3 tsu MDIO MDCLKH Setup time MDIO data input valid before MDCLK high 10 ns 4 tn MDCLKH MDIO Hold time MDIO data input valid after MDCLK high 0 ns MDCLK YYYYYY YY YY NAN N N N N NA WM MM NM N N NM WM NM MM VN NN NANA MM YY YY NA MM N MDIO 550005005060 Figure 5 67 MDIO Input Timing Table 5 80 Switching Characteristics Over Recommended Operating Conditions for MDIO Output see Figure 5 68 500 600 720 UNIT MN MAX MAX 7 la MDCLKL MDIO Delay time MDCLK low to MDIO data output valid 10 100 ns e a MDCLK _7 _ gt kl NNN wl NN VY YY VY NC NC wl VY YO YY Y Y NN Y V N N NN N N WW WW ww ww NM N ORR KN Figure 5 68 MDIO Output Timing Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 159 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 5 18 Timer The C6000 DSP device has 32 bit general purpose timers that can be used to e Time events e Count events e Generate pulses e Interrupt the CPU e Send synchronization events to the DMA da TEXAS
9. 152 66 5 17 Management Data Input Output MDIO 158 70 EE 160 5 19 General Purpose Input Output GPIO 162 70 5 20 TAG 165 70 Revision History 167 6 Mechanical Data 168 6 1 Thermal Data 168 n 6 2 Packaging Information 169 Contents 5 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 2 Device Overview 2 1 Device Characteristics da TEXAS INSTRUMENTS www ti com Table 2 1 provides an overview of the DM642 DSP The table shows significant features of the DM642 device including the capacity of on chip RAM the peripherals the CPU frequency and the package type with pin count Table 2 1 Characteristics of the DM642 Processor HARDWARE FEATURES 1 DM amp 89O EMIFA 64 bit bus width clock source AECLKIN EDMA 64 independent channels uses Peripheral Clock AUXCLK 12 0 uses Peripheral Clock 1 HPI 32 or 16 bit user selectable 1 HPI16 or 2 Peripherals PCI 32 bit 66 MHz 33 MHz DevicelD Register value 0x9065 Not all peripherals pins are available at the same time For more detail see the McBSPs internal clock source CPU A clock frequency Device Configuratio
10. HINT PFRAME 3 N4 0 2 Host interrupt from DSP to host default or PCI frame 1 0 2 PDEVSEL Host control selects between control address or data registers default or 3 HCNTL1 PDEVSEL P1 2 PCI device select I O Z HCNTLO PSTOP 9 R3 0 7 Host control selects between control address data registers 1 default or PCI stop 0 2 Host half word select first or second half word not necessarily high or low HHWIL PTRDY 9 N3 VO Z order For HPI16 bus width selection only I default or PCI target ready I O Z HR W PCBE2 M1 2 Host read write select I default or PCI command byte enable 2 0 2 HAS PPAR P3 2 Host address strobe default or PCI parity 1 2 Host chip select I default or PCI parity error 0 2 ae di Host data strobe 1 default or PCI system error 1 2 HDS1 PSER R2 VO Z Host data strobe 2 default or PCI command byte enable 1 2 HDS2 PCBE1 9 T2 VO Z Note If unused the following HPI control signals should be externally pulled high HRDY PIRDY 9 N1 2 Host ready from DSP to host O default or PCI initiator ready 0 2 Submit Documentation Feedback Device Overview 31 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued
11. ies La 1 AED 63 0 Write Data AAOE ASDRAS ASOE i 10 6 gt l P wisi mo NN NE A AAOE ASDRAS ASOE AARE ASDCAS ASADS ASRE and AAWE ASDWE ASWE operate as AAOE identified under select signals AARE and AAWE respectively during asynchronous memory accesses gt k 10 i AAWE ASDWE ASWE X pud E ke 7 4 7 Figure 5 18 Asynchronous Memory Write Timing for EMIFA Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 97 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor da TEXAS INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 8 3 2 Programmable Synchronous Interface Timing Table 5 24 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module see Figure 5 19 600 500 A 600 e 720 UNIT MN MAX MAX MN MAX MAX tsu EDV EKOxH Setup time read AEDx valid before AECLKOUTx high 3 1 2 ns th EKOxH EDV Hold time read AEDx valid after AECLKOUTx high 1 8 1 5 ns Table 5 25 Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for EMIFA see Figure 5 19 5 21 500 A 600 000 e PARAMETER 720 UNIT
12. Delay time AECLKOUTx high to ASDCKE valid 1 3 6 4 1 3 4 9 ns 14 1 Delay time AECLKOUTx high to APDT valid 1 3 6 4 1 3 4 9 ns 102 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 READ acko f AA A A A A A __ 1 1 N wd 2 lest 3 ABE 7 0 A X BE BE X BEA 4 4 5 SE AEA 22 14 X Bank X 4 5 AEA Z3 AOOO j 4 5 aean N 7 l 6340 X Ds X D AAOE ASDRAS ASOE A 8 coe 8 AARE ASDCAS ASADS ASRE 4 A Geen AAWE ASDWE ASWE k 14 k gt 14 ufo A AARE ASDCAS ASADS ASRE AAWE ASDWE ASWE and AAOE ASDRAS ASOE operate as ASDCAS ASDWE and ASDRAS respectively during SDRAM accesses B APDT signal is only asserted when the EDMA is in PDT mode set the PDTS bit to 1 in the EDMA options parameter RAM For APDT read data is not latched into EMIF The PDTRL field in the PDT control register PDTCTL configures the latency of the APDT signal with respect to the data phase of a read transaction The latency of the signal for a read can be programmed to 0 1 2 or by setting PDTRL to 00 01 10
13. _ se NM p 7 GEN k 2 27 Ly 18 4 17 tol 18 M Stop Start Repeated Stop tart Figure 5 37 2 Transmit Timings 122 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback 49 Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 11 Host Port Interface HPI The HPI is a parallel port through which a host processor can directly access the CPU memory space The host device functions as a master to the interface which increases ease of access The host and CPU can exchange information via internal or external memory The host also has direct access to memory mapped peripherals Connectivity to the CPU memory space is provided through the enhanced DMA EDMA controller Both the host and the CPU can access the HPI control register HPIC and the HPI address register HPIA The host can access the HPI data register HPID and the HPIC by using the external data and interface control signals For more detailed information on the HPI peripheral see the TMS320C6000 DSP Host Port Interface HPI Reference Guide literature number SPRU578 5 11 1 HPI Peripheral Register Description s Table 5 38 HPI Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 2 HPID HPI data register Host read write access only 0188 0000 HPIC HPI
14. pin 1 For more details on the EMAC pin functions see the Ethernet HD9 AD9 V MAC EMAC peripheral section of this table and for more details on how to HD8 AD8 3 v2 configure the EMAC pin functions see the device configuration section of this 3 data sheet HD7 AD76G W2 HD6 AD6 9 W4 HD5 AD5 Y1 HD4 AD4 9 W3 HD3 AD36G Y2 HD2 AD2 9 Y4 HD1 AD1 AA1 HD0 AD0 9 PCBEO PCI command byte enable 0 2 TEBEO ya cin When PCI is disabled PCI EN 0 this pin is tied off C PCI serial interface chip select O XSP_CS n When PCI is disabled PCI EN 0 this pin is tied off XSP CLK MDCLK 9 R5 0 2 PPD PCI serial interface clock O default MDIO serial clock input output I O Z PCI serial interface data in I default SEH d NN FH In PCI mode this pin is connected to the output data pin of the serial PROM PCI serial interface data out O default or MDIO serial data input output DO MDIO 9 P5 V O Z IPU VO Z In PCI mode this pin is connected to the input data pin of the serial PROM 32 Device Overview Submit Documentation Feedback 4 TEXAS TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL PD DESCRIPTION NAME NO IPU
15. Eight Serial Data Pins Wide Variety of PS and Similar Bit Stream Format Integrated Digital Audio I F Transmitter Supports S PDIF IEC60958 1 AES 3 CP 430 Formats Inter Integrated Circuit 20 Bus Two Multichannel Buffered Serial Ports Three 32 Bit General Purpose Timers Sixteen General Purpose I O GPIO Pins Flexible PLL Clock Generator IEEE 1149 1 JTAG Boundary Scan Compatible 548 Pin Ball Grid Array BGA Package GDK and ZDK Suffixes 0 8 mm Ball Pitch 548 Pin Ball Grid Array BGA Package GNZ and ZNZ Suffixes 1 0 mm Ball Pitch 0 13 um 6 Level Cu Metal Process CMOS 3 3 V I O 1 2 V Internal 500 3 3 V I O 1 4 V Internal A 500 A 600 600 720 Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document Copyright 2002 2007 Texas Instruments Incorporated TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 1 2 Description TMS320C64x DSPs including the TMS320DM642 device are the highest performance fixed point DSP generation in the TMS320C6000 DSP platform The TMS320DM642 DM642 device is based on the second generation high performance advanced VelociTI very long instruction word VLIW architecture VelociTl
16. default or MDIO serial clock input output 1 2 PCI serial interface data out O default or MDIO serial data input output XSP_DO MDIO P5 0 2 IPU VO Z In PCI mode this pin is connected to the input data pin of the serial PROM VCXO INTERPOLATED CONTROL PORT VIC VCXO Interpolated Control Port VIC single bit digital to analog converter VDAO output output only default or this pin can be programmed as 8 pin 1 2 PCIE Boot Configuration PCI frequency selection PCI66 If the PCI peripheral is enabled PCI EN pin 1 then press 0 PCI operates at 66 MHz default VDAC GPO 8 PCI66 9 AD1 VO Z 1 PCI operates at 33 MHz The 500 device supports PCI at 33 MHz only For proper 500 device operation when the PCI peripheral is enabled PCI EN 1 this pin must be pulled up with 1 resistor at device reset Note If the PCI peripheral is disabled PCI EN pin 0 this pin must not be pulled up VIDEO PORTS VPO VP1 AND VP2 STCLK AC1 The STCLK signal drives the hardware counter on the video ports 36 Device Overview Submit Documentation Feedback 4 TEXAS TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued a NG TYPE ue DESCRIPTION VIDEO PORT 2 VP2 VP2D 19
17. OOOOOOOOOOOOO OOOOOOOOOOOOO 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 Bottom View Seating Plane f 0 10 9 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Flip chip application only E 0 40 4203481 3 07 02 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 MECHANICAL DATA MPBG314A OCTOBER 2002 REVISED DECEMBER 2002 PLASTIC BALL GRID ARRAY GNZ S PBGA N548 A1 GER 0 50 NOM UoommorcarzzuxmxAc z 25 00 TYP Bid OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOO 3000000 3000000 3000000 OOOOOOO 0000000 0000000 0000000 0000000 0000000 0000000 3000000 0000000 OOOOOOO OOOOOOO 3000000 OOOOOOO OOOOOOOOOOOOO0 OOOOOOOOOOOOO OOOOOOOOOOOOO0 OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO 3000000 3000000 0300000 00 OOOOOOO 3000000 0300000 00 OOOOOOOOOOOOO Qoooooooooooo OOOOOOOOOOOOO OOOOOOOOOOOOO 11 13 15 17 19 21 23 25 10 1
18. A AARE ASDCAS ASADS ASRE AAWE ASDWE ASWE and AAOE ASDRAS ASOE operate as ASDCAS ASDWE and ASDRAS respectively during SDRAM accesses Figure 5 28 SDRAM MRS Command for EMIFA gt TRAS cycles Self Refresh End Self Refresh AECLKOUTx pou ME _ Z Xy 60 22222 25 ABE 7 0 AEA 22 14 12 3 EE AEA13 AED 63 0 s AAOE ASDRAS ASOE 4 y AARE ASDCAS ASADS ASRE 4 n LE gt AAWE ASDWE ASWE lt 13 lt 13 ASDCKE 7 and ASDRAS respectively during SDRAM accesses Figure 5 29 SDRAM Self Refresh Timing for EMIFA Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 107 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 8 3 4 HOLD HOLDA Timing Table 5 28 Timing Requirements for the HOLD HOLDA Cycles for EMIFA Module see Figure 5 30 600 500 A 600 e 720 UNIT MIN MAX MAX MIN MAX 3 th HOLDAL HOLDL Hold time HOLD low after HOLDA low E E ns 1 E the EMIF input clock ECLKIN CPU 4 clock or CPU 6 clock period ns for EMIFA Table 5 29 Switching Characteristics Over Recommended Operating Conditions for the HOLD HOLDA Cycles for EMIFA
19. 11 MAC EN 0 EMAC is disabled and the module is powered down default 1 EMAC is enabled This bit has no effect if the PCI peripheral is enabled PCI EN 1 HPI bus width control bit Shows the status of whether the HPI bus operates in 32 bit mode or in 16 bit mode default 10 HPI WIDTH 0 HPI operates in 16 bit mode default 1 operates 32 bit mode PCI EEPROM auto initialization bit PCI auto initialization via external EEPROM Shows the status of whether the PCI module initializes internal registers via external EEPROM or if the internal PCI default values are used instead default PCI EEAI 0 PCI auto initialization through EEPROM is disabled the PCI peripheral uses the specified PCI default values default 1 PCI auto initialization through EEPROM is enabled the PCI peripheral is configured through EEPROM provided the PCI peripheral pin is enabled PCI EN 1 PCI enable bit Shows the status of whether the PCI peripheral is enabled or disabled default PCI EN 0 PCI disabled default 1 PCI enabled Global select for the PCI vs HPI EMAC MDIO GPIO peripherals Reserved Reserved Read only writes have no effect 26 CLKMODE 1 Clock mode select bits Shows the status of whether the CPU clock frequency equals the input clock frequency X1 Bypass x6 or x12 Clock mode select for CPU clock frequency CLKMODE 1 0 00 Bypass x1 default mode 5 CLKMODEO 01 x6 10 x12 11 Reserved Fo
20. Do not oppose the internal pullup pulldown resistors on these non configuration pins with external pullup pulldown resistors If an external controller provides signals to these non configuration pins these signals must be driven to the default state of the pins at reset or not be driven at all For the internal pullup pulldown resistors for all device pins see the terminal functions table Device Configurations 65 TMS320DM642 d Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 3 7 Configuration Examples Figure 3 6 through Figure 3 8 illustrate examples of peripheral selections that are configurable on the DM642 device 66 Device Configurations Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 AED 63 0 AECLKIN AARDY AHOLD AEA 22 3 ACE 3 0 ABE 7 0 AECLKOUT1 AECLKOUT2 16 ASDCKE 5 APDT HD 15 0 Clock AHOLDA ABUSREQ HRDY HINT and AARE ASDCAS ASADS ASRE 16 Bit System AAOE ASDRAS ASOE AAWE ASDWE ASWE L CLKIN CLKMODEO CLKMODE1 TIMER2 CLKOUTA CLKOUT6 PLLV TINP1 TIMER1 TOUT1 LENDIAN HCNTLO HCNTL 1 HHWIL HAS HR W HCS HDS1 HDS2 MTXD 3 0 MTXEN e MRXD 3 0 MRXER MRXDV MCOL MCRS MTCLK MRCLK MDIO MDCLK STCLK A TINP
21. and Vue MIN 2 P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns 3 Select the parameter value whichever is larger 0 4 DVpp V MIN e 1 gt Peak to Peak for lt 2 3 3V signaling gt ech 7M ch EE ud lt 3 4 9 le Figure 5 46 PCLK Timing Table 5 43 Timing Requirements for PCI Reset see Figure 5 47 500 600 720 UNIT MN MAX 1 lw PRST Pulse duration PRST 1 ms 2 tsuPCLKA PRSTH Setup time PCLK active before PRST high 100 Hs PCLK N PEE IE EIER H pesto 0 Hf 5 52 Figure 5 47 PCI Reset PRST Timing Table 5 44 Timing Requirements for PCI Inputs see Figure 5 48 600 500 A 600 720 aous 66MHz UNT MN MAX MAX MIN MAX MAX lsu IV PCLKH Setup time input valid before PCLK high 7 3 ns 5 th IV PCLKH Hold time input valid after PCLK high ioe O ns 130 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback XB Texa TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 N N 5 Pol input 500 Figure 5 48 PCI Input Timing 33 66 MHz Table 5 45 Switching Characteristics Over Recommended Op
22. 11 respectively PDTRL equals 00 zero latency in Figure 5 22 Figure 5 22 SDRAM Read Command CAS Latency 3 for EMIFA Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 103 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 AECLKOUTx ACEx ABE 7 0 AEA 22 14 AEA 12 3 AEA13 AED 63 0 AAOE ASDRAS ASOE AARE ASDCAS ASADS ASRE AAWE ASDWE ASWE APDT __ WRITE 2 da TEXAS INSTRUMENTS www ti com f XA X A 7 NA f XJ 2 E 4 4 4 4 4 3 BE1 C X BE X BE A AARE ASDCAS ASADS ASRE AAWE ASDWE ASWE and AAOE ASDRAS ASOE operate as ASDCAS ASDWE and ASDRAS respectively during SDRAM accesses B APDT signal is only asserted when the EDMA is in PDT mode set the PDTD bit to 1 in the EDMA options parameter RAM For APDT write data is not driven in High Z The PDTWL field in the PDT control register PDTCTL configures the latency of the APDT signal with respect to the data phase of a write transaction The latency of the APDT signal for a write transaction can be programmed to 0 1 2 or 3 by setting PDTWL to 00 01 10 or 11 respectively PDTWL equals 00 zero latency in Figure 5 23 Figure 5 23 SDRAM Write Command for EMIFA 104 DM642 Peripheral Information and Electr
23. 6 Vss AEA5 N CVpp Vss Vss DVpp APDT 4 2 M CVpp Vss AARDY ABE1 ABEO ASDCKE L AAWE K Vi DV ACE2 ACEO ASDWE DD ss DD ASWE AAOE AARE ASDCAS C Vss DVpp Vss AECLKOUT4 ASDRAS ASADS J ASOE ASRE CVpp Vss DVpp AED17 AED16 AECLKIN Vss H CVpp Vss CVpp CVpp Vss CVpp CVpp CVpp DVpp AED19 AED21 AED20 AED18 G Vss DVpp Vss Vss DVpp Vss CVpp CVpp Vss AED23 AED25 AED24 AED22 F RSV TMS Vss DVpp Vss DVpp DVpp Vss DVpp Vss AED27 AED26 Vss E TRST EMU4 EMU8 EMU11 Vss AED14 AED12 AED8 Vss DVpp Vss AED28 AED29 D EMU1 EMU3 EMU6 EMU10 Vss AED15 AED10 AED6 AED4 Vss DVpp AED30 AED31 DVpp EMU2 EMU5 EMU9 TDO Vss AED11 AED7 AED3 AED2 AEDO DVpp DVpp B Vss EMUO TCK EMU7 TDI Vss AED13 AED9 Vss AED5 AED1 DVpp Vss A 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 2 6 DM642 Pin Map Quadrant D 20 Device Overview Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 2 5 2 Signal Groups Description 4 RESET CLKIN 4 NMI CLKOUT4 GP0 1 A 4 Resetand 4 GP0 7 EXT_INT7 B CLKOUTS6 GPO 2 4 Clock PLL Interrupts 4 GPO 6 EXT_INT6 B CLKMODE1 Eb GPO B EXT INT5 B CLKMODEO GPO 4 EXT_INT4 8 PLLV RSV08 TMS gt RSV07 RSV0
24. AARDY as an asynchronous input the pulse width of the AARDY signal should be wide enough e g pulse width 2E to ensure setup and hold time is met 2 RS Read setup RST Read strobe RH Read hold WS Write setup WST Write strobe WH Write hold These parameters are programmed via the EMIF CE space control registers Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 95 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 23 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module 99 see Figure 5 17 and Figure 5 18 500 600 720 UNIT MIN MAX 1 tosu SELV AREL Output setup time select signals valid to AARE low RS E 1 8 n 2 ton AREH SELIV Output hold time AARE high to select signals invalid RH E 1 9 ns 5 la EKO1H AREV Delay time high to AARE valid 1 7 ns 8 losu SELV AWEL Output setup time select signals valid to AAWE low WS E 2 0 ns 9 toh AWEH SELIV Output hold time AAWE high to select signals invalid WH E 2 5 ns 10 tia EKO1H AWEV Delay time AECLKOUTx high to AAWE valid 1 3 7 1 ns 1 RS Read setup RST Read strobe RH Read hold WS Write setup WST Write strobe WH Write hold These parameters are
25. PARAMETER 720 UNIT MAX lw GPOH Pulse duration GPOx high 24P 80 ns 4 lw GPOL Pulse duration GPOx low 24 8 2 ns 1 P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns 2 This parameter value should not be used as a maximum performance specification Actual performance of back to back accesses of the GPIO is dependent upon internal bus activity ES 24 1 J GPIx 7 X K 2 WEE A 3 5 _ ___ Y N Figure 5 72 GPIO Port Timing 164 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 5 20 JTAG The JTAG interface is used for BSDL testing and emulation of the DM642 device Note IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture 5 20 1 JTAG Device Specific Information 5 20 1 1 IEEE 1149 1 JTAG Compatibility Statement The TMS320DM642 DSP requires that both TRST and RESET be asserted upon power up to be properly initialized While RESET initializes the DSP core TRST initializes the DSP s emulation logic Both resets are required for proper operation Note TRST is synchronous and must be clocked by TCLK otherwise BSCAN may not respond as expected after TRST is asserted While both TRST an
26. Table 5 37 Switching Characteristics for 2 Timings see Figure 5 37 500 600 720 PARAMETER STANDARD PREFHOBE UNIT MODE MIN MAX MN MAX MAX 16 Cycle time SCL 10 2 5 us Delay time SCL high to SDA low for a repeated START 17 ta ScLH SDAL condition 47 oe us Delay time SDA low to SCL low for a START and a repeated 18 taspaL scLL START condition ae us 19 tw SCLL Pulse duration SCL low 4 7 1 3 us 20 tw SCLH Pulse duration SCL high 4 op us 21 la SDAV SDLH Delay time SDA valid to SCL high 250 100 ns 22 tv SDLL SDAV Valid time SDA valid after SCL low For bus devices o0 0 09 0 9 us Pulse duration SDA high between STOP and START 3 23 conditions 4 7 1 us 24 t sp Rise time SDA 1000 20 0 1C 300 ns 25 sci Rise time SCL 1000 20 0 107 300 ns 26 504 Fall time SDA 300 20 0 16400 300 ns 27 Fall time SCL 300 20 0 10400 300 ns 28 la SCLH SDAH Delay time SCL high to SDA high for STOP condition 4 ose us 29 Cp Capacitance for each 2 pin 10 10 pF 1 total capacitance of one bus line in pF If mixed with HS mode devices faster fall times are allowed ps 26 24 34 k X H 4 721 H 1 son LT K 7 LX t 4 23 4 21 19 28 le 25 A 20
27. da TEXAS Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 49 McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA controller 0190 0000 DRR1 McBSP1 data receive register via Configuration Bus can only read this register they cannot write to it 0x3400 0000 0x37FF FFFF DRR1 McBSP1 data receive register via peripheral bus 0190 0004 DXR1 McBSP1 data transmit register via configuration bus 0x3400 0000 Ox37FF FFFF DXR1 McBSP1 data transmit register via peripheral bus 0190 0008 SPCR1 McBSP1 serial port control register 0190 000C RCR1 McBSP1 receive control register 0190 0010 XCR1 transmit control register 0190 0014 SRGR1 McBSP1 sample rate generator register 0190 0018 MCR1 McBSP1 multichannel control register 0190 001C RCEREO01 McBSP1 enhanced receive channel enable register 0 0190 0020 XCEREO01 McBSP1 enhanced transmit channel enable register 0 0190 0024 PCR1 McBSP1 pin control register 0190 0028 RCERE 1 1 McBSP1 enhanced receive channel enable register 1 0190 002C XCERE11 McBSP1 enhanced transmit channel enable register 1 0190 0030 RCERE21 McBSP1 enhanced receive channel enable register 2 0190 0034 XCERE21 McBSP1 enhanced transmit channel enable register 2 0190 0038 McBSP1 enhanced receive channel enable register 3 0190 003C XCERE31 McBSP1 enhanced transmit chann
28. 0 disabled To enable the PCI peripheral an external pullup resistor 1 must be provided on the PCI EN pin setting PCI EN 1 at reset HD31 AD31 MRCLK G1 HD31 HD30 AD30 MCRS H3 HD30 HD29 AD29 MRXER G2 HD29 HD28 AD28 MRXDV J4 HD28 HD27 AD27 MRXD3 H2 HD27 By default HPI is enabled upon reset PCI is disabled HD26 AD26 MRXD2 J3 HD26 To enable the PCI peripheral an external pullup resistor HD25 AD25 MRXD1 Ji HD25 PCI EN 0 disabled 1 kQ must be provided on the PCI EN pin setting HD24 AD24 MRXDO K4 HD24 MAC EN 0 PCI_EN 1 at reset C disabled 1 HD22 AD22 MTCLK L4 HD22 disabled To enable the EMAC peripheral an external pullup resistor HD21 AD21 MCOL K2 HD21 1 must be provided on the MAC EN pin setting MAC EN 1 at reset HD20 AD20 MTXEN L3 HD20 HD19 AD19 MTXD3 L2 HD19 HD18 AD18 MTXD2 M4 HD18 HD17 AD17 MTXD1 M2 HD17 HD16 AD16 MTXDO M3 HD16 3 6 Debugging Considerations Submit Documentation Feedback It is recommended that external connections be provided to device configuration pins including TOUT1 LENDIAN AEA 22 19 3 VDAC GPO B8 PCI66 HD5 AD5 PCI EN and TOUTO MAC EN Although internal pullup pulldown resistors exist on these pins providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes Internal pullup pulldown resistors also exist on the non configuration pins on the AEA bus AEA 18 0
29. 01C8 012C RXSFLOWTHRESH 01C8 0130 RX4FLOWTHRESH Reserved Do not write 01C8 0134 RX5FLOWTHRESH 01C8 0138 RX6FLOWTHRESH 01C8 013C RX7FLOWTHRESH 01C8 0140 RXOFREEBUFFER Receive Channel 0 Free Buffer Count Register 01C8 0144 RX1FREEBUFFER 01C8 0148 RX2FREEBUFFER 01C8 014C RXSFREEBUFFER 01C8 0150 RX4FREEBUFFER Reserved Do not write 01C8 0154 RX5FREEBUFFER 01C8 0158 RX6FREEBUFFER 01C8 015C RX7FREEBUFFER 01C8 0160 MACCONTROL MAC Control Register 01C8 0164 MACSTATUS MAC Status Register RXQOSACT field is reserved 01C8 0168 0108 016C Po Reserved 01C8 0170 TXINTSTATRAW Transmit Interrupt Status Unmasked Register 01C8 0174 TXINTSTATMASKED Transmit Interrupt Status Masked Register 01C8 0178 TXINTMASKSET Transmit Interrupt Mask Set Register 01C8 017C TXINTMASKCLEAR Transmit Interrupt Mask Clear Register 01C8 0180 MACINVECTOR MAC Input Vector Register 01C8 0184 01C8 018F Reserved Receive Interrupt Status Unmasked Register 01C8 0190 RXINTSTATRAW Bits 7 1 are reserved C Receive Interrupt Status Masked Register 01C8 0194 RXINTSTATMASKED Bits 7 1 are reserved 01C8 0198 RXINTMASKSET Receive Interrupt Mask Set Register Bits 7 1 are reserved and only support writes of 0 01C8 019C RXINTMASKCLEAR Receive Interrupt Mask Clear Register Bits 7 1 are reserved and only support writes of 0 01C8 01A0 MACINTSTATRAW MAC Interrupt Sta
30. 16K Byte L1D Data Cache 2 Way Set Associative 2M Bit 256K Byte L2 Unified Mapped RAM Cache Flexible RAM Cache Allocation Endianess Little Endian Big Endian 64 Bit External Memory Interface EMIF Glueless Interface to Asynchronous Memories SRAM and EPROM and Synchronous Memories SDRAM SBSRAM ZBT SRAM and FIFO Windows is a registered trademark of Microsoft Corporation Bus is a trademark of Philips Electronics N V PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters 1024M Byte Total Addressable External Memory Space Enhanced Direct Memory Access EDMA Controller 64 Independent Channels 10 100 Mb s Ethernet MAC EMAC IEEE 802 3 Compliant Media Independent Interface MII 8 Independent Transmit TX Channels and 1 Receive RX Channel Management Data Input Output MDIO Three Configurable Video Ports Providing a Glueless I F to Common Video Decoder and Encoder Devices Supports Multiple Resolutions Video Stds VCXO Interpolated Control Port VIC Supports Audio Video Synchronization Host Port Interface HPI 32 16 Bit 32 Bit 66 MHz 3 3 V Peripheral Component Interconnect PCI Master Slave Interface Conforms to PCI Specification 2 2 Multichannel Audio Serial Port McASP
31. EK 10 TOUTO MACEN VPOCTL 2 0 VPOD 19 10 GPO McBSPO and EXT_INT CLKRO FSRO DRO CLKSO FSXO0 CLKXO GP0 15 9 3 0 GPO 7 4 McASPO Control SCLO DCH McASPO Data SDAO CLKR1 FSR1 DR1 CLKS1 DX1 FSX1 McBSP1 VIC VDAC GPO 8 PCI66 CLKX1 STCLK A STCLK A VP1CLKO Wee VP2 VP2CLKO E 10 Bit 20 Bit BOCK 1 1 VP2CTL 2 0 VP1CTL 2 0 VP2D 19 0 VP1D 19 10 PERCFG Register Value 0x0000 007E Extenal Pins PCI EN 0 0 HD5 0 TOUTO MAC 1 0 Shading denotes a peripheral module not available for this configuration A STCLK supports all three video ports VP2 VP1 and VPO Figure 3 7 Configuration Example B 2 10 Bit Video Ports 2 McBSPs EMAC MDIO 12 0 EMIF Possible Video IP Phone Application 68 Device Configurations Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 AED 63 0 AECLKIN AARDY AHOLD AEA 22 3 ACE 3 0 ABE 7 0 AECLKOUT1 AECLKOUT2 16 ASDCKE 5 APDT HD 15 0 ipi Clock AHOLDA ABUSREQ HRDY HINT and AARE ASDCAS ASADS ASRE 16 Bit System AAOE ASDRAS ASOE AAWE ASDWE ASWE L CLKIN CLKMODEO CLKMODE1 TIMER2 L p CLKOUTA CLKOUTS TINP1 TIMER1 TOUT1 LENDIAN TINPO 4 TIMERO 10 51 TOUTO MACEN GP0 15 9 3 0 HCNTLO HCNTL
32. F18 G5 G22 H5 H22 J6 921 K5 K22 M6 M21 N2 25 R21 U5 U22 V21 w5 W22 W25 Y5 Y22 3 3 V supply voltage see the Power Supply Decoupling section of this data sheet Submit Documentation Feedback Device Overview 43 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 da TEXAS INSTRUMENTS www ti com Table 2 4 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU DESCRIPTION AA9 AA12 AA15 AA18 AB5 AB7 AB8 AB10 AB17 AB19 AB20 AB22 AC23 AD24 AE1 AE2 AE13 AE25 AE26 AF2 AF25 3 3 V supply voltage see the Power Supply Decoupling section of this data sheet 44 Device Overview Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL NAME NO E D F6 F7 F20 F21 G6 G7 G8 G10 G11 G13 G14 G16 G17 G19 G20 G21 H20 K7 K20 L7 L20 Mig 1 2 V supply voltage 500 device CVpp M14 S 1 4 V supply voltage A 500 A 600 600 720 devices N7 see the Power Supply Decoupling section of thi
33. Figure 1 1 Functional Block Diagram 4 53200 642 Video Imaging Fixed Point Digital Signal Processor Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 1 TMS320DM642 Video Imaging Fixed Point Digital Signal PFOGeSSOr 5 0 ecco reci amen 1 1 g uP 1 2 IBesctiptlOnu 1 2 1 Device Compatibility 1 3 Functional Block Diagram 2 Device Overview 2 1 Device 22 DSP Core Description 23 Memory Map Summary 2 4 Bootmode 16 2 5 Pin Assignments 16 2 6 Development 3 Device Conttourations 3 1 Configurations at Reset 3 2 Configurations After 3 3 Peripheral Configuration 3 4 Device Status Register Description 3 5 Multiplexed Pin Configurations 3 6 Debugging Considerations 3 7 Configuration Examples 4 Device Operating Conditions 4 1 Absolute Maximum Ratings Over Operating Cas
34. K AD21 AD24 DVpp Vss CVpp AD23 COL PIDSEL HD25 HD26 HD28 J 25 TOUR AD26 AD28 Ve DVpp Vss MRXD1 MRXD2 MRXDV HD27 HD30 3 GPO 12 H Vss AD27 AD30 DVpp Vss RSV MRXD3 MCRS jen HD29 aponsy G AD31 AD29 PRST PINTA DVpp CVpp CVpp CVpp Vss CVpp CVpp Vss CVpp MRCLK MRXER GPO My GPO G GPosy F C PREQ EXT INT6 EXT INT amp EXT INT Vss Vos VoD Vss Vss Vss DVop Vss 7 E PCI EN Vss SCLO DVpp Vss DVpp DVpp Vss DVpp P2D 2018 VP2D 19 CLKOUT4 D Vss Vss SDAO DVpp Vss Geop VPACTL VP2DH VP2DB 2 P2D 13 VP2D 17 Vss P0 14J TOUTO CLKOUT6 Vss DVpp Vss MAC EN ao VP2CTL2 VPaD o VP2DM VP2D 8 P2D VP2D 16 Vss TOUT1 B Dvpp DVpp Vss D Vss Vss 2 VP2D 3 27 P2D VP2D 15 Vss LENDIAN Vss DVpp Vss TINPO Vss VP2CLKO Vss VP2D 2 296 P2D Vss VP2CLK1 1 2 3 4 5 6 7 8 9 10 1 12 18 Figure 2 5 DM642 Pin Map Quadrant C Submit Documentation Feedback Device Overview 19 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 14 15 16 17 18 19 20 21 22 23 04 25 26 Mun m Vss CVpp CVpp Vss AHOLDA AEA7
35. MN MAX MAX MN MAX MAX 1 la EKOxH CEV Delay time AECLKOUTx high to ACEx valid 1 1 6 4 1 1 4 9 ns 2 la EKOxH BEV Delay time AECLKOUTx high to ABEx valid 6 4 4 9 ns 3 la EKOxH BEIV Delay time AECLKOUTx high to ABEx invalid 14 14 ns 4 la EKOxH EAV Delay time AECLKOUTx high to AEAx valid 6 4 4 9 ns 5 la EKOxH EAIV Delay time AECLKOUTx high to AEAx invalid 14 14 5 la EKOxH ADSV Delay time AECLKOUTx high to ASADS ASRE valid 1 1 6 4 1 1 4 9 ns la EKOxH OEV Delay time AECLKOUTx high to ASOE valid 1 1 6 4 1 1 4 9 ns 10 tyekoxH EDVv Delay time AECLKOUTx high to AEDx valid 6 4 4 9 ns 11 la EKOxH EDIV Delay time AECLKOUTx high to AEDx invalid 1 1 1 1 ns 12 la EKOxH WEV Delay time high to ASWE valid 1 1 6 4 1 1 4 9 ns 1 The following parameters are programmable via the CE Space Secondary Control register CExSEC 98 Read latency SYNCRL 0 1 2 or 3 cycle read latency Write latency SYNCWL 0 1 2 or 3 cycle write latency ACEx assertion length CEEXT For standard SBSRAM or ZBT SRAM goes inactive after the final command has been issued CEEXT 0 For synchronous FIFO interface with glue ACEx is active when ASOE is active CEEXT 1 Function of ASADS ASRE RENEN For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles RENEN 0 For FIFO interface ASADS ASRE acts as ASRE with NO deselect
36. SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 55 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 0 79 see Figure 5 54 500 600 SC UNIT MASTER SLAVE MIN MAX MIN MAX 4 tsu DRV CKXH Setup time DR valid before CLKX high 12 2 12P ns 5 th CKXH DRV Hold time DR valid after CLKX high 4 5 24 ons 1 CPU clock frequency in ns For example when running parts at 720 MHz use 1 39 ns For all SPI Slave modes CLKG is programmed as 1 4 of the CPU clock by setting CLKSM CLKGDV 1 Table 5 56 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 0 see Figure 5 54 500 600 PARAMETER UNIT MASTER SLAVE MIN MAX MAX MN MAX MAX 1 th CKXL FXL Hold time FSX low after CLKX low 4 L 2 L 3 ns 2 taexL ckxH Delay time FSX low to CLKX high 9 T 25 T 3 ns 3 la CKXL DXV Delay time CLKX low to DX valid 2 4 12P 3 20P 17 ns Disable time DX high impedance following last data bit from 3 e ldis CKXL DXHZ CLKX low 9 P 9 2 4 12P 3 20P 17 ns 7 ta EXL DXV Delay time FSX low to DX valid H 2 4 8P 2 16P 17 ns 1 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns 2 For al SPI Slave modes CLKG is programmed as 1 4 of the CPU clock by setting CLKSM CLKGDV 1 Submit Do
37. and 1 logic levels Vret 1 5 V Figure 5 2 Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to MAX and Vj MIN for input clocks MAX and Voy MIN for output clocks Vi gt and Vipp MIN for PCI input clocks and Vo p and MIN for PCI output clocks Vret Vin MIN or MIN or Vinp MIN or Voup MIN Vret Vip MAX or MAX or Vii p MAX or Voip MAX Figure 5 3 Rise and Fall Transition Time Voltage Reference Levels 5 1 1 2 Signal Transition Rates All timings are tested with an input edge rate of 4 Volts per nanosecond 4 V ns Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 73 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 1 1 3 Timing Parameters and Board Routing Analysis 74 A The timing parameter values specified in this data sheet do not include delays by board routings As a good board design practice such delays must always be taken into account Timing values may be adjusted by increasing decreasing such delays recommends utilizing the available buffer information specification IBIS models to analyze the timing characteristics correctly To properly use IBIS models to attain accurate timing analysis for a given system see the Using IB
38. see the EMIF device speed portion of this data sheet 2 PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 2 2 CPU DSP Core Description The CPU fetches VelociTI advanced very long instruction words VLIWs 256 bits wide to supply up to eight 32 bit instructions to the eight functional units during every clock cycle The VelociTIT M VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute The first bit of every 32 bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction or whether it should be executed in the following clock as a part of the next execute packet Fetch packets are always 256 bits wide however the execute packets can vary in size The variable length execute packets are a key memory saving feature distinguishing the C64x CPUs from other VLIW architectures The C64x VelociTl 2 extensions add enhancements to the TMS320C62x DSP architecture These enhancements include e Register file enhancements e Data pa
39. www ti com 1 2 1 SPRS200L JULY 2002 REVISED JANUARY 2007 The VCXO interpolated control VIC port provides digital to analog conversion with resolution from 9 bits to up to 16 bits The output of the VIC is a single bit interpolated D A output For more details on the VIC port see the TMS320C64x DSP Video Port VCXO Interpolated Control VIC Port Reference Guide literature number SPRU629 The ethernet media access controller EMAC provides an efficient interface between the DM642 DSP core processor and the network The DM642 EMAC support both 10Base T and 100Base TX or 10 Mbits second Mbps and 100 Mbps in either half or full duplex with hardware flow control and quality of service QOS support The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception For more details on the EMAC see the TMS320C6000 DSP Ethernet Media Access Controller EMAC Management Data Input Output MDIO Module Reference Guide literature number SPRU628 The management data input output MDIO module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system Once a PHY candidate has been selected by the DSP the MDIO module transparently monitors its link state by reading the PHY status register Link change events are stored in the MDIO module and can optionally interrupt the DSP allowing the DSP to poll the link status of the device without continuously perform
40. 0000 A4FF FFFF 0184 8294 MAR165 Controls EMIFA CE2 range A500 0000 5 FFFF 0184 8298 MAR166 Controls EMIFA range A600 0000 A6FF FFFF 0184 829C MAR167 Controls EMIFA CE2 range A700 0000 A7FF FFFF 0184 82A0 MAR168 Controls EMIFA CE2 range A800 0000 A8FF FFFF 0184 82A4 MAR169 Controls EMIFA CE2 range A900 0000 A9FF FFFF 0184 82A8 MAR170 Controls EMIFA CE2 range AA00 0000 AAFF FFFF 0184 82AC MAR171 Controls range 0000 ABFF FFFF 0184 8280 MAR172 Controls EMIFA CE2 range 0000 ACFF FFFF 0184 82B4 MAR173 Controls EMIFA range ADOO 0000 ADFF FFFF 0184 82B8 MAR174 Controls EMIFA CE2 range AE00 0000 AEFF FFFF 0184 82BC MAR175 Controls EMIFA CE2 range AF00 0000 AFFF FFFF 0184 82 0 MAR176 Controls EMIFA 63 range 8000 0000 BOFF FFFF 0184 82C4 MAR177 Controls EMIFA range 8100 0000 B1FF FFFF 0184 82C8 MAR178 Controls EMIFA range 8200 0000 B2FF FFFF 0184 82CC MAR179 Controls EMIFA range 8300 0000 B3FF FFFF 0184 8200 80 Controls EMIFA range B400 0000 B4FF FFFF 0184 8204 MAR181 Controls EMIFA range 8500 0000 B5FF FFFF 0184 82D8 MAR182 Controls EMIFA range 8600 0000 6 FFFF 0184 82DC MAR183 Controls EMIFA range 8700 0000 B7FF FFFF 0184 82 0 MAR184 Controls EMIFA range 8800 0000 B8FF FFFF 0184 82 4 MAR185 Controls EMIFA CE3 range B900 0000 B9FF FFFF 0184 82bE8 MAR186 Con
41. 1 VPOD S FSXO AF16 VPOD 2 CLKXO AF17 XSP CLK MDCLK R5 By default no functions enabled upon reset PCI is disabled To enable the PCI peripheral an external pullup resistor PCI EN 0 disabled 1 must be provided on the PCI EN pin setting None MAC EN 0 PCI EN 1 at reset DO MDIO P5 disabled 1 To enable the MDIO peripheral which also enables the EMAC peripheral an external pullup resistor 1 must be provided on the MAC EN pin setting MAC EN 1 at reset HAS PPAR P3 HAS HCNTL1 PDEVSEL P1 HCNTL1 HCNTLO PSTOP R3 HCNTLO HDS1 PSERR R2 HDST HDSZ PCBET T2 HDS2 By default HPI is enabled upon reset PCI is disabled W PCBED W PCI EN 0 disabled To enable the PCI peripheral an external pullup resistor Mi REAN 1 kO must be provided on the PCI EN pin setting 3 HHWIL PCI EN 1 at reset HHWIL PTRDY N 16 only HINT PFRAME N4 HINT HCS PPERR R1 HCS HRDY PIRDY N1 HRDY 64 Device Configurations Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 3 8 DM642 Device Multiplexed Pin Configurations continued MULTIPLEXED PINS DEFAULT DEFAULT NAME NO FUNCTION SETTING DESCRIPTION By default HPI is enabled upon reset PCI is disabled HD 23 15 0 AD 23 15 0 2 HD 23 15 0 PCI EN
42. ASRE acts as ASADS with deselect cycles RENEN 0 For FIFO interface ASADS ASRE acts as ASRE with NO deselect cycles RENEN 1 Synchronization clock SNCCLK Synchronized to AECLKOUT1 or AECLKOUT2 C AARE ASDCAS ASADS ASRE AAOE ASDRAS ASOE and AAWE ASDWE ASWE operate as ASADS ASRE ASOE and ASWE respectively during programmable synchronous interface accesses Figure 5 19 Programmable Synchronous Interface Read Timing for EMIFA With Read Latency 2 4 8 Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 99 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 AELKOUX N _ N NA AJ N 1 1 A T 2 3 ABE 7 0 AEA 22 3 K 10 k 11 AED 63 0 Q1 Q X X Q 8 VR 8 AARE ASDCAS ASADS ASRE O TU 1 AAOE ASDRAS ASOE k 12 12 AAWE ASDWEASWE O A write latency and the length of ACEN assertion are programmable via the SYNCWL CEEXT fields respectively in the EMIFA CE Space Secondary Control register CExSEC In this figure SYNCWL 0 and CEEXT 0 B The following parameters are programmable via the EMIF CE Space Secondary Control register CExSEC e Read latency SYNCRL 0 1 2 or 3 cycle read latency e Write latency SYNCWL 0 1 2 or 3 cycle w
43. B CLKSQ McBSPs Multichannel Buffered Serial Ports TOUT1 LENDIAN TOUTO MACEN Timers SCLO zx pn DCH A These McBSP1 and McBSPO pins are muxed with the Video Port 1 VP1 and Video Port 0 VPO peripherals respectively By default these signals function as VP1 and VPO respectively For more details on these muxed pins see the Device Configurations section of this data sheet Figure 2 10 McBSP Timer I2CO Peripheral Signals 24 Device Overview Submit Documentation Feedback TMS320DM642 49 4 EXAS INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 HD16 AD16 MTXDO A HD17 AD17 MTXD1 A Transmit HD18 AD18 MTXD2 A HD19 AD19 MTXD3 HD24 AD24 MRXDO HD25 AD25 MRXD1 A HD26 AD26 MRXD2 A Receive XSP DO MDIO B HD27 AD27 MRXD3 A 20 020 4 XSP_CLK MDCLK HD29 AD29 MRXER A Error Detect HD28 AD28 MRXDV A ementi HD21 AD21 MCOL A HD30 AD30 MCRS A HD22 AD22 MTCLK A gt Clocks HD31 AD31 MRCLK A gt Ethernet MAC EMAC and MDIO These EMAC pins are muxed with the upper data pins of the HPI or PCI peripherals By default these signals function as HPI For more details on these muxed pins see the Device Configurations section of this data sheet These MDIO pins are muxed with the PCI peripherals By default these signals function as PCI For more d
44. Bypass UNIT MN MAX MN MN MAX 1 Lc CLKIN Cycle time CLKIN 24 33 3 13 3 33 3 13 3 33 3 ns 2 twCLKINH Pulse duration CLKIN high 0 45C 0 45C 0 45C ns 3 Iw CLKINL Pulse duration CLKIN low 0 45C 0 45C 0 45C ns 4 ty CLKIN Transition time CLKIN 5 5 1 ns 5 Period jitter CLKIN 0 02C 0 02C 0 02C ns 1 The reference points for the rise and fall transitions are measured at Vi MAX and Vu MIN 2 For more details on the PLL multiplier factors x6 x12 see the Clock PLL section of this data sheet 3 C CLKIN cycle time in ns For example when CLKIN frequency is 50 MHz use C 20 ns Table 5 14 Timing Requirements for CLKIN for 600 Devices see Figure 5 11 o PLL MODE x12 PLL MODE x6 x1 Bypass UNIT MN MAX MN MN MAX 1 Cycle time CLKIN 20 33 3 13 3 33 3 13 3 33 3 ns 2 twCLKINH Pulse duration CLKIN high 0 45C 0 45C 0 45C ns 3 Iw CLKINL Pulse duration CLKIN low 0 45C 0 45C 0 45C ns 4 ty CLKIN Transition time CLKIN 5 5 1 ns D Period jitter CLKIN 0 02C 0 02C 0 02C ns 1 The reference points for the rise and fall transitions are measured at Vu MAX and Vu MIN 2 For more details on the PLL multiplier factors x6 x12 see the Clock PLL section of this data sheet 3 C CLKIN cycle time in ns For example when CLKIN frequency is 50 MHz use C 20
45. Digital Signal Processor Silicon Errata literature number SPRZ196 describes the known exceptions to the functional specifications for particular silicon revisions of the TMS320DM642 device The TMS320DM64x Power Consumption Summary application report literature number SPRA962 discusses the power consumption for user applications with the TMS320DM642 DSP devices TMS320DM642 Hardware Designer s Resource Guide literature number SPRAA51 is organized by development flow and functional areas to make design efforts as seamless as possible This document includes getting started board design system testing and checklists to aid in initial designs and debug efforts Each section of this document includes pointers to valuable information including technical documentation models symbols and reference designs for use in each phase of design Particular attention is given to peripheral interfacing and system level design concerns The Using IBIS Models for Timing Analysis application report literature number SPRA839 describes how to properly use IBIS models to attain accurate timing analysis for a given system The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment IDE For a complete listing of 60007 DSP latest documentation visit the Texas Instruments web site the Worldwide Web at hitp www ti com uniform resource locator URL 2 6 2 3 Device Silicon
46. Ff m AFSR X Slot Width 1 Bit Delay DEP i Slot Width 2 Bit Delay NO y gt 8 7 AXR n Data In Receive A0 Ai A30 A31 BO B1 B30B31 CO C1 C2 C3 C31 t For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out and the McASP receiver is configured for falling edge to shift data in t For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift data out and the McASP receiver is configured for rising edge to shift data in Figure 5 33 McASP Input Timings 116 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback 49 Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 gt l 14 10 a A WP 10 ace ning cago oy acukan ising Edge eon HUDD 4 12 6 kl scum EVA VAYA VAVA IIIS EENS Bia 6 13 133 le AFSR X Bit Width 0 Bit Delay X if AFSR X Bit Width 1 Bit Delay OIN N d AFSR X Bit Width 2 Bit Delay N JSN N ZG UL 4 1 AFSR X Slot Width 0 Bit Delay W A AFSR X Slot Width 1 Bit Delay N 4 83 7 AFSR X Sl
47. GPINT6 EXT_INT6 GPO interrupt 6 External interrupt pin 6 INT 0702 MUXL 20 16 00111 GPINT7 EXT_INT7 interrupt 7 External interrupt pin 7 INT 08 2 MUXL 25 21 01000 EDMA INT EDMA channel 0 through 63 interrupt INT 0902 MUXL 30 26 01001 EMU DTDMA EMU DTDMA INT 100 MUXH 4 0 00011 SD INTA EMIFA SDRAM timer interrupt INT 110 MUXH 9 5 01010 EMU RTDXRX EMU real time data exchange RTDX receive INT 1200 MUXH 14 10 01011 EMU RTDXTX EMU RTDX transmit INT 130 MUXH 20 16 00000 DSP INT HPI PCI to DSP interrupt INT 140 MUXH 25 21 00001 TINTO Timer 0 interrupt INT 152 MUXH 30 26 00010 TINT1 Timer 1 interrupt fo 01100 XINTO McBSPO transmit interrupt NENNEN o 01101 RINTO McBSPO receive interrupt NENNEN fo 01110 XINT1 McBSP1 transmit interrupt ES 01111 RINT1 receive interrupt r 10000 GPINTO interrupt 0 10001 Reserved Reserved Do not use r 01 10010 Reserved Reserved Do not use 10011 TINT2 Timer 2 interrupt NENNEN fo 10100 Reserved Reserved Do not use NENNEN o 10101 Reserved Reserved Do not use fo 10110 ICINTO 12 0 interrupt 10111 Reserved Reserved Do not use NENNEN r 11000 EMAC MDIO INT EMAC MDIO interrupt 11001 VPINTO VPO interrupt 01 11010 VPINT1 VP1 interrupt NENNEN 11011 VPINT2 VP2 interrupt 1 Interrupts INT 00 through INT 03 are non mas
48. GPO 9 PIDSEL HCNTL1 PDEVSEL HINT PFRAME GPO 13 PINTA HAS PPAR GPO 15 PRST HRDY PIRDY HCNTLO PSTOP HHWIL PTRDY HDS1 PSERR HCS PPERR XSP_DO MDIO XSP_CS XSP_CLK MDCLK XSP_DI A These HPI pins are muxed with the PCI peripheral By default these signals function as HPI For more details on these muxed pins see the Device Configurations section of this data sheet B These PCI pins excluding PCBEO and XSP CS are muxed with the HPI MDIO peripherals By default these signals function as HPI and no function respectively For more details on these muxed pins see the Device Configurations section of this data sheet C These HPI PCI data pins HD 31 16 AD 31 16 are muxed with the EMAC peripheral By default these pins function as HPI For more details on the EMAC pin functions see the Ethernet MAC EMAC peripheral signals section and the terminal functions table portions of this data sheet Figure 2 9 HPI PCI Peripheral Signals Submit Documentation Feedback Device Overview 23 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 McBSP0 VP0D 2 CLKX0 A VPOD 3 FSX0 A gt VPOD 4 DXOA VP1D 2 CLKX1 A 4 VP1D 3 FSX1 A 4 Transmit R 10 4 0 1 4 VP1D 8 CLKR1 4 A VPOD 8 CLKRO A VP1D 7 FSR10 4 VPOD 7 FSROU VP1D G DR1 VPOD G DRO A VP1D B CLKS1 VPOD
49. I2C peripheral see the TMS320C6000 DSP Inter Integrated Circuit I2C Module Reference Guide literature number SPRU175 Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 119 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 5 10 2 12 Peripheral Register Description s Table 5 35 2 0 Registers da TEXAS INSTRUMENTS www ti com HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 0000 I2COARO 1200 own address register 01B4 0004 I2CIERO 12 0 interrupt enable register 01B4 0008 I2ZCSTRO I2CO0 interrupt status register 01B4 000C I2CCLKLO 2 0 clock low time divider register 01B4 0010 I2CCLKHO 1260 clock high time divider register 01B4 0014 2 0 12 0 data count register 0184 0018 I2CDRRO 1200 data receive register 01B4 001C I2ZCSARO 12 0 slave address register 01B4 0020 I2CDXRO 12 0 data transmit register 01B4 0024 I2CMDRO I2C0 mode register 0184 0028 I2CISRCO 1200 interrupt source register 0184 002C NENNEN Reserved 01B4 0030 I2CPSCO 12 0 prescaler register 01B4 0034 I2CPID10 12 0 Peripheral Identification register 1 Value 0x0000 0101 01B4 0038 I2CPID20 12 0 Peripheral Identification register 2 Value 0x0000 0005 0184 003C 01 4 3FFF Reserved 120 DM642 Peripheral Information and Electrical Specifications Submit Documentation F
50. INSTRUMENTS www ti com The timers have two signaling modes and can be clocked by an internal or an external source The timers have an input pin and an output pin The input and output pins TINP and TOUT can function as timer clock input and clock output They can also be respectively configured for general purpose input and output With an internal clock for example the timer can signal an external A D converter to start a conversion or it can trigger the DMA controller to begin a data transfer With an external clock the timer can count external events and interrupt the CPU after a specified number of events 5 18 1 Timer Device Specific Information The DM642 device has total of three 32 bit general purpose timers TimerO and Timer2 Timer2 is not externally pinned out For more detailed information see the TMS320C6000 DSP 32 Bit Timer Reference Guide literature number SPRU582 5 18 2 Timer Peripheral Register Description s Table 5 81 Timer 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Determines the operating mode of the timer monitors the 9194 0000 SES Timer 0 contiol regisler timer status and controls the function of the TOUT pin Contains the number of timer input clock cycles to count 9191 0001 SES panies This number controls the TSTAT signal frequency 0194 0008 CNTO Timer 0 cou
51. MII data clocks and control pins for Transmit Receive e transmit clock MTCLK HD31 AD31 MRCLK 9 G1 HD30 AD30 MCRS 9 H3 HD29 AD29 MRXER 9 G2 HD28 AD28 MRXDV 9 J4 1 SS 3 Ir 1 e transmit data MTXD S3 0 o o o HD27 AD27 MRXD3 9 H2 Transmit clock source from the attached PHY HD26 AD26 MRXD2 3 J3 25 MRXD16 1 Transmit data nibble synchronous with transmit clock MTCLK FIDA 2 e Mil transmit enable MTXEN HD24 AD24 MRXDO K4 This signal indicates a valid transmit data on the transmit data pins HD22 AD22 MTCLK 9 L4 MTDX 3 0 HD21 AD21 MCOL K2 MII collision sense MCOL HD20 AD20 MTXENO L3 O Z of this signal during half duplex operation indicates network HD19 AD19 MTXD3 9 L2 O Z During full duplex operation transmission of new frames will not begin if this HD18 AD18 MTXD2 4 0 2 G I asserted me carrier sense HD17 AD17 MTXD1 3 M2 O Z Indicates a frame carrier signal is being received e MII receive data MRXD S3 0 Receive data nibble synchronous with receive clock MRCLK Mil receive clock MRCLK Receive clock source from the attached PHY HD16 AD16 MTXDO 0 2 receive data valid This signal indicates a valid data nibble the receive data pins 0 and receive error MRXER Indicates reception of a coding error on the receive d
52. McBSP 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA controller 018C 0000 DRRO McBSPO data receive register via Configuration Bus can only read this register they cannot write to it 0x3000 0000 0x33FF FFFF DRRO McBSPO data receive register via Peripheral Bus 018C 0004 DXRO McBSPO data transmit register via Configuration Bus 0x3000 0000 0x33FF FFFF DXRO McBSPO data transmit register via Peripheral Bus 018C 0008 SPCRO McBSPO serial port control register 018C 000C RCRO McBSPO receive control register 018C 0010 XCRO McBSPO transmit control register 018C 0014 SRGRO McBSPO sample rate generator register 018C 0018 MCRO McBSP0 multichannel control register 018C 001C RCEREO0 McBSPO enhanced receive channel enable register 0 018C 0020 McBSPO enhanced transmit channel enable register 0 018C 0024 PCRO McBSPO pin control register 018C 0028 RCERE10 McBSPO0 enhanced receive channel enable register 1 018C 002C XCERE10 McBSPO enhanced transmit channel enable register 1 018C 0030 RCERE20 McBSPO enhanced receive channel enable register 2 018C 0034 XCERE20 McBSPO0 enhanced transmit channel enable register 2 018C 0038 McBSPO enhanced receive channel enable register 3 018C 003C XCERE30 McBSPO enhanced transmit channel enable register 3 018C 0040 018F FFFF Reserved Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 133 TMS320DM642
53. Module 9 see Figure 5 30 500 A 600 Eos e PARAMETER 720 UNIT MIN MAX MAX MIN MAX MAX 1 la HOLDL EMHZ Delay time HOLD low to EMIFA Bus high impedance 2E 4 2E 4 ns 2 tgEMHZ HOLDAL Delay time EMIF Bus high impedance to HOLDA low 0 2E 0 2E ns 4 tsHoLpH EMLZ Delay time HOLD high to EMIF Bus low impedance 2E 7E 2E 7E ns D tyeEMLz HOLDAH Delay time EMIFA Bus low impedance to HOLDA high 0 2E 0 2E ns 6 la HOLDL EKOHZ Delay time HOLD low to AECLKOUTx high impedance 2E 4 2E 4 ns 7 tyHOLDH EKOLZ Delay time HOLD high to AECLKOUTx low impedance 2E 7E 2E 7E ns 1 E the EMIF input clock ECLKIN CPU 4 clock or CPU 6 clock period in ns for EMIFA 2 EMIFA Bus consists of ACE 3 0 ABE 7 0 AED 63 0 AEA 22 3 AARE ASDCAS ASADS ASRE AAOE ASDRAS ASOE and AAWE ASDWE ASWE ASDCKE 5 APDT 0 ECLKOUTx continues clocking during Hold mode If EKxHZ 1 ECLKOUTx goes to high impedance during Hold mode as shown in Figure 5 30 minimum delay time can be achieved Also bus hold can be indefinitely delayed by setting NOHOLD 1 External Requestor DSP Owns Bus DSP Owns Bus 5 2 Owns Bus 8 emgeet HOLD Kabel EMIF Bus AECLKOUTXx B EKxHZ 0 AECLKOUTx we A UU NA V E EKxHZ 1 VS L N Z N A EMIFA Bus consists of 3 0 ABE 70 AED 63 0 AEA 22 3
54. REVISED JANUARY 2007 5 12 Peripheral Component Interconnect PCI The PCI port for the TMS320C600 supports connection of the DSP to a PCI host via the integrated PCI master slave bus interface For the C64x devices like the DM642 the PCI port interfaces to the DSP via the EDMA internal address generation hardware This architecture allows for both PCI Master and Slave transactions while keeping the EDMA channel resources available for other applications 5 12 1 PCI Device Specific Information On the DM642 device the PCI interface is multiplexed with the 32 bit Host Port Interface HPI or with a combination of 16 bit HPI and EMAC MDIO This provides the following flexibility options to the user 32 01 66 MHz PCI bus e 32 bit HPI e Combination of 16 bit HPI and EMAC MDIO For more detailed information on the PCI port peripheral module see the TMS320C6000 DSP Peripheral Component Interconnect PCI Reference Guide literature number SPRU581 5 12 2 PCI Peripheral Register Description s Table 5 41 PCI Peripheral Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01 0 0000 RSTSRC DSP Reset source status register 0100 0004 Reserved 01C0 0008 PCIIS PCI interrupt source register 01C0 000G PCIIEN PCI interrupt enable register 01C0 0010 DSPMA DSP master address register 01C0 0014 PCIMA PCI master address register 01C0 0018 PCIMG PCI master control register 01
55. Register 01C4 0028 01C4 4028 01C4 8028 PDINx Video Port Pin Data Input Register 01C4 002C 01C4 402C 01C4 802C VP PDOUTx Video Port Pin Data Output Register 01C4 0030 01C4 4030 01C4 8030 PDSETx Video Port Pin Data Set Register 01C4 0034 01C4 4034 01C4 8034 VP PDCLRx Video Port Pin Data Clear Register 01C4 0038 01C4 4038 01C4 8038 VP Video Port Pin Interrupt Enable Register 01C4 003C 01C4 403C 01C4 803C VP PIPOx Video Port Pin Interrupt Polarity Register 01C4 0040 01C4 4040 01C4 8040 VP PISTATx Video Port Pin Interrupt Status Register 0104 0044 0104 4044 01C4 8044 VP PICLRx Video Port Pin Interrupt Clear Register 01C4 00 0 01C4 4000 0104 80 0 CTLx Video Port Control Register 01C4 00C4 01C4 40C4 01C4 80 4 VP STATx Video Port Status Register 01C4 00C8 01C4 40C8 01C4 80C8 VP IEx Video Port Interrupt Enable Register 01C4 00CC 01C4 40CC 01C4 80CC 15 Video Port interrupt Status Register 01C4 0100 01C4 4100 01C4 8100 VC STATx Video Capture Channel A Status Register 0104 0104 01C4 4104 01C4 8104 VC CTLx Video Capture Channel A Control Register 142 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 61 Video Port 0 1 and 2 VPO VP1 and VP2 Control Registers continued HEX ADDRESS RANGE
56. Revision The device silicon revision can be determined by the Die PG code marked on the top of the package For more detailed information on the DM642 silicon revision package markings and the known exceptions to the functional specifications as well as any usage notes refer to the device specific silicon errata TMS320DM642 Digital Signal Processor Silicon Errata literature number SPRZ196 Submit Documentation Feedback Device Overview 53 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 3 Device Configurations On the DM642 device bootmode and certain device configurations peripheral selections are determined at device reset while other device configurations peripheral selections are software configurable via the peripheral configurations register PERCFG address location 0x01B3F000 after device reset 3 1 Configurations at Reset For DM642 proper device operation GP0 0 pin M5 must remain low do not oppose the internal pulldown IPD 3 1 1 Peripheral Selection at Device Reset Some DM642 peripherals share the same pins internally muxed and are mutually exclusive e HPI general purpose input output pins GPO 15 9 PCI and its internal EEPROM EMAC MDIO Other DM642 peripherals e the Timers 2 0 and the GPO 7 0 pins are always available e HPI GPO 15 9 PCI EEPROM internal to PCI EMAC and MDIO peripherals The PCI EN
57. SBSRAM Cur L1P Cache ZBT SRAM Direct Mapped M pe i E Bytes Total ecu 0 E SRAM VCXO Interpolated C64x DSP Core ROM FLASH ISCH Port VIC zx Fetch Control UO Devices Registers Instruction Dispatch Advanced Instruction Packet Control Instruction Decode Logic Data Path A Data Path B 1 est A Register File B Register File A31 A16 B31 B16 Advanced A15 A0 15 0 mid Emulation OR ven BI Espere Enhanced L2 Control DMA Cache Controller Memory Video Port 1 EDMA 256kBytes VP1 OR L1D Cache 2 Way Set Associative 16K Bytes Total B McBSP1 A OR PLL Power Down McASPO x1 x6 x12 Logic Data B OR HPI32 OR 16 AND OR EMAC Boot Configuration 16 2 LS 1200 E A McBSPs Framing Chips 100 MVIP SCSA E1 AC97 Devices SPI Devices Codecs B The Video Port 0 VPO peripheral is muxed with the McBSPO peripheral and the McASPO control pins The Video Port 1 VP1 peripheral is muxed with the McBSP1 peripheral and the McASPO data pins The PCI peripheral is muxed with the HPI 32 16 EMAC MDIO peripherals For more details on the multiplexed pins of these peripherals see the Device Configurations section of this data sheet
58. TMS320DM642 PLL Multiply Factor Options Clock Frequency Ranges and Typical Lock Time GDK and ZDK PACKAGES 23 x 23 mm BGA GNZ and ZNZ PACKAGES 27 x 27 mm BGA CLKMODE CLKIN CPU CLOCK TYPICAL CLKMODE1 CLKMODEO PLLMULTIPLY RANGE FREQUENCY x ANGE MES B ANGE GIES LOCK TIME FACTORS MHz RANGE MHz us 9 o Bypass xt 30 75 30 75 7 5 18 8 5 12 5 N A 0o 1 x6 30 75 180 450 45 112 5 30 75 1 0 x12 30 50 360 600 90 150 60 100 1 1 Reserved e e 1 These clock frequency range values are applicable to a DM642 600 speed device For 500 and 720 device speed values see the CLKIN timing requirements table for the specific device speed 2 Use external pullup resistors on the CLKMODE pins CLKMODE1 and CLKMODEO to set the DM642 device to one of the valid PLL multiply clock modes x6 or x12 With internal pulldown resistors on the CLKMODE pins CLKMODE1 CLKMODEO the default clock mode is x1 bypass 3 Under some operating conditions the maximum PLL lock time may vary by as much as 150 from the specified typical value For example if the typical lock time is specified as 100 us the maximum value may be as long as 250 us 5 7 2 Clock PLL Electrical Data Timing Input and Output Clocks Table 5 13 Timing Requirements for CLKIN for 500 Devices 9 9 see Figure 5 11 o PLL MODE x12 PLL MODE x6 x1
59. Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 2 2 1 CPU Core Registers Table 2 2 L2 Cache Registers C64x HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0184 0000 CCFG Cache configuration register 0184 0004 0184 e Reserved 0184 1000 EDMAWEIGHT L2 EDMA access control register 0184 1004 0184 1FFC o Reserved 0184 2000 L2ALLOCO L2 allocation register 0 0184 2004 L2ALLOC1 L2 allocation register 1 0184 2008 L2ALLOC2 L2 allocation register 2 0184 200C L2ALLOC3 L2 allocation register 3 0184 2010 0184 3FFC o Reserved 0184 4000 L2WBAR L2 writeback base address register 0184 4004 L2WWC L2 writeback word count register 0184 4010 L2WIBAR L2 writeback invalidate base address register 0184 4014 L2WIWC L2 writeback invalidate word count register 0184 4018 L2IBAR L2 invalidate base address register 0184 401C L2IWC L2 invalidate word count register 0184 4020 L1PIBAR L1P invalidate base address register 0184 4024 L1PIWC L1P invalidate word count register 0184 4030 L1DWIBAR L1D writeback invalidate base address register 0184 4034 L1DWIWC L1D writeback invalidate word count register 0184 4038 0184 4044 o Reserved 0184 4048 L1DIBAR L1D invalidate base address register 0184 404C L1DIWC L1D invalidate word count register 0184 4050 0184 4FFC o Reserved 0184 5000 L2WB L2 writeback all register 0184 5004 L2WBINV L2 writeback invalidate all register 0184 5008 0184
60. are generated from a single source through the CLKIN pin This source clock either drives the PLL which multiplies the source clock frequency to generate the internal CPU clock or bypasses the PLL to become the internal CPU clock To use the PLL to generate the CPU clock the external PLL filter circuit must be properly designed Figure 5 10 shows the external PLL circuitry for either x1 PLL bypass or other PLL multiply modes To minimize the clock jitter a single clean power supply should power both the C64x DSP device and the external clock oscillator circuit The minimum CLKIN rise and fall times should also be observed For the input clock timing requirements see the input and output clocks electricals section Rise fall times duty cycles high low pulse durations and the load capacitance of the external clock source must meet the DSP requirements in this data sheet see the electrical characteristics over recommended ranges of supply voltage and operating case temperature table and the input and output clocks electricals section DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 3 3 V A 2 CPU Clock C1 C2 Peripheral Bus EDMA lock 10 0 1 uF SES Timer Internal Clock V
61. be pulled up GPO 9 PIDSEL K3 PCBES To use GP0 15 9 as GPIO pins the PCI needs to be SC BE disabled PCI EN 0 the GPxEN bits in the GPIO GPO 11 PREQ FA GE Enable Register and the GPxDIR bits in the GPIO PGNT 158018 Direction Register must be properly configured GPO 12 PGNT H4 None PCI EN 0 disabled G4 1 GPx pin enabled C C GPxDIR 0 GPx pin is an input GPO 14 PCLK 1 GPxDIR 1 GPx is an output GPO 15 PRST G3 VP1D 19 AXRO 7 AB12 VP1D 18 AXRO 6 AB11 By default no function is enabled upon reset VP1D 17 AXRO 5 AC11 To enable the Video Port 1 data pins the VP1EN bit in the VP1D 16 AXRO 4 AD11 VP1EN bit 0 disabled PERCFG register must be set to a 1 McASPO data pins MCASPOEN bit 0 are disabled VP1D 15J AXRO 3 AE11 disabled To enable the McASPO 7 0 data pins the MCASPOEN bit VPTELTAAXROIE AC10 in the PERCFG register must be set to a 1 VP1 upper VP1D 13 AXRO 1 AD10 data pins are disabled VP1D 12 AXRO 0 AC9 1 All other standalone PCI pins are tied off internally pins in Hi Z when the peripheral is disabled PCI EN 0 Submit Documentation Feedback Device Configurations 63 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 da TEXAS INSTRUMENTS www ti com Table 3 8 DM642 Device Multiplexed Pin Configurations continued
62. bits in the GPDIR register This register determines if a given GPIO pin is an input an output providing the corresponding GPxEN bit is enabled set to 1 in the GPEN register By default all the GPIO pins are configured as input pins 162 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP15 GP14 GP13 GP12 GP11 GP10 GP9 GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R W Readable Writable n value after reset x undefined value after reset Figure 5 71 GPIO Direction Register GPDIR Hex Address 01BO 0004 For more detailed information on general purpose inputs outputs GPIOs see the TMS320C6000 DSP General Purpose Input Output GPIO Reference Guide literature number SPRU584 5 19 2 GPIO Peripheral Register Description s Table 5 86 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0000 GPEN enable register 0180 0004 GPDIR GPO direction register 0180 0008 GPVAL GPO value register 01
63. continued SIGNAL NAME NO TYPE IPD Ipu DESCRIPTION F8 F10 F11 F13 F14 F16 F17 F19 F22 G9 G12 G15 G18 H1 H6 H21 H26 J5 J7 J20 J22 K6 Vss K21 L1 L6 L21 M7 M13 M15 M20 N5 N6 N12 N14 N21 N25 P2 P6 P13 P15 P21 R7 R12 R14 R20 Ground pins Submit Documentation Feedback Device Overview 47 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 da TEXAS INSTRUMENTS www ti com Table 2 4 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU DESCRIPTION Ti T5 T6 T21 T26 06 021 V5 V7 V20 V22 Wi W6 W21 W26 Y9 Y12 Y15 Y18 AA4 AA5 AA8 AA10 AA11 AA13 AA14 AA16 AA17 AA19 AA22 AB1 AB2 AB4 AB6 AB9 AB18 AB21 AB26 AC3 AC5 AC18 AC22 AC24 AD2 AD4 Ground pins 48 Device Overview Submit Documentation Feedback K Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Proces
64. control register HPIC has both Host CPU read write access 0188 0004 ELSE register HPIA HPI address register HPIA has both Host CPU read write access 9180 0008 HPIAR Read 0188 000C 0189 FFFF Reserved 018A 0000 e request control 018A 0004 018B FFFF Reserved 1 m the register updates both the HPIAW registers The CPU can access HPIAW HPIAR independently Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 123 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 5 11 2 Host Port Interface HPI Electrical Data Timing da TEXAS INSTRUMENTS www ti com Table 5 39 Timing Requirements for Host Port Interface Cycles see Figure 5 38 through Figure 5 45 HSTBL HASL 500 600 720 UNIT MIN MAX 1 tsu SELV HSTBL Setup time select signals 9 valid before HSTROBE low 5 ns 2 tnHsTBL SELV Hold time select signals valid after HSTROBE low 2 4 ns 3 tuHsrBL Pulse duration HSTROBE low 4 ns 4 Pulse duration HSTROBE high between consecutive accesses 4P ns 10 Isu SELV HASL Setup time select signals valid before HAS low 5 ns 11 tniisL sELV Hold time select signals 9 valid after HAS low 2 ns 12 Lsu HDV HSTBH Setup time host data valid before HSTROBE
65. cycles RENEN 1 Synchronization clock SNCCLK Synchronized to AECLKOUT1 or AECLKOUT2 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 READ latency 2 aeoo VS LP LS mar 1 m1 ACEx W d a 3 ABE 7 0 BEI X BE Y X BE4 AEA 22 3 6 AED 63 0 02 X 03 X Q 7 AARE ASDCAS ASADS ASRE mp EE DE E weem pot 9 9 AAOE ASDRAS ASOE O AAWE ASDWE ASWE O A The read latency and the length of ACEx assertion are programmable via the SYNCRL and CEEXT fields respectively in the EMIFA CE Space Secondary Control register CExSEC In this figure SYNCRL 2 and CEEXT 0 B The following parameters are programmable via the EMIF CE Space Secondary Control register CExSEC Read latency SYNCRL 0 1 2 or 3 cycle read latency Write latency SYNCWL 0 1 2 or 3 cycle write latency ACEx assertion length CEEXT For standard SBSRAM or ZBT SRAM interface ACEx goes inactive after the final command has been issued CEEXT 0 For synchronous FIFO interface with glue ACEx is active when ASOE is active CEEXT 1 Function of ASADS ASRE RENEN For standard SBSRAM or ZBT SRAM interface ASADS
66. down the EMU1 and EMUO pins with a dedicated 1 kQ resistor 30 Device Overview Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL PD DESCRIPTION NAME NO IPU GPO 15 PRST G3 General purpose input output 15 pin I O Z or PCI reset 3 14 pin 2 or PCI clock SC et 13 pin 2 or PCI interrupt A O Z GPO 13 PINTA G4 GPO 12 1 0 2 or PCI bus grant POM2VPGNT H4 11 pin 0 2 or PCI bus request 0 2 PM a 10 I O Z or PCI command byte enable I O Z GPO 11 PRE F1 9 l O Z or PCI initialization device select GPO 10JPCBE3 6 J2 Voz Note By default no function is enabled upon reset To configure these pins see GPO 9 PIDSEL K3 the Device Configuration section of this data sheet 3 pin 2 Boot Configuration PCI EEPROM Auto Initialization EEAI 0 PCI auto initialization through EEPROM is disabled default 1 PCI auto initialization through EEPROM is enabled General purpose 0 pin GPO 0 1 2 default This pin can be programmed as GPIO 0 input only default or as GPO 0 0 5 VO Z output only pin or output as general purpose interrupt GPOINT signal output onl
67. duration XSP high 2046P ns D Pulse duration low 2046P ns 6 tosu DOV CLKH Output setup time XSP_DO valid before XSP_CLK high 2046P ns 7 ton CLKH DOV Output hold time XSP DO valid after high 2046P ns 1 P 1t CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns pus 1 Figure 5 50 PCI Serial EEPROM Interface Timing 132 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 13 Multichannel Buffered Serial Port McBSP The McBSP provides these functions Full duplex communication Double buffered data registers which allow a continuous data stream Independent framing and clocking for receive and transmit Direct interface to industry standard codecs analog interface chips and other serially connected analog to digital A D and digital to analog D A devices External shift clock or an internal programmable frequency shift clock for data transfer For more detailed information on the McBSP peripheral see the TMS320C6000 DSP Multichannel Buffered Serial Port McBSP Reference Guide literature number SPRU580 5 13 1 McBSP Peripheral Register Description s Table 5 48
68. hardware flow control and quality of service QOS support The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception The EMAC controls the flow of packet data from the DSP to the PHY The MDIO module controls PHY configuration and status monitoring Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows efficient data transmission and reception This custom interface is referred to as the EMAC control module and is considered integral to the EMAC MDIO peripheral The control module is also used to control device reset interrupts and system priority The TMS320C6000 DSP Ethernet Media Access Controller EMAC Management Data Input Output MDIO Module Reference Guide literature number SPRUG28 describes the DM642 EMAC peripheral in detail Some of the features documented in this peripheral reference guide are not supported on the DM642 at this time The DM642 supports one receive channel and does not support receive quality of service QOS For a list of supported registers and register fields see Table 5 70 Ethernet MAC EMAC Control Registers and Table 5 71 EMAC Statistics Registers in this data manual 5 16 2 EMAC Peripheral Register Description s Table 5 70 Ethernet MAC EMAC Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 0000 TXIDVER Transmit Identific
69. high ns 13 tnusrBH Hbv Hold time host data valid after HSTROBE high 2 8 ns 34 Hold time HSTROBE low after HRDY low HSTROBE should not be inactivated 2 ge until HRDY is active low otherwise HPI writes will not complete properly 18 lsu HASL HSTBL Setup time HAS low before HSTROBE low 2 ns 19 t Hold time HAS low after HSTROBE low 2 1 ns RON Q HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 52 OR HCS P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns Select signals include HONTL 1 0 and HR W For 16 mode only select signals also include HHWIL Select the parameter value of 4P or 12 5 ns whichever is larger Table 5 40 Switching Characteristics Over Recommended Operating Conditions During Host Port Interface Cycles see Figure 5 38 through Figure 5 45 500 600 PARAMETER 720 UNIT MN MAX 6 la HSTBL HRDYH Delay time HSTROBE low HRDY high 9 1 3 4 8 ns 7 la HSTBL HDL2 Delay time HSTROBE low to HD low impedance for an HPI read 2 ms 8 ta HDV HRDYL Delay time HD valid to HRDY low 3 ns 9 toh HSTBH HDV Output hold time HD valid after HSTROBE high 1 5 ns 15 tyHsTBH HDHz Delay time HSTROBE high to HD high impedance 12 ns 16 tyHsTBL HDVv Delay time HSTROBE low to HD valid 16 mode 2nd half w
70. ns For example when running parts at 720 MHz use P 1 39 ns 4 N the PCI input clock PCLK period in ns When PCI is enabled PCI EN 1 this parameter must be met Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 85 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 www ti com Table 5 11 Switching Characteristics Over Recommended Operating Conditions During Reset see Figure 5 9 500 600 PARAMETER 720 UNIT MIN MAX 2 la RSTL ECKI Delay time RESET low to AECLKIN synchronized internally 2E 3P 20E ns 3 la RSTH ECKI Delay time RESET high to AECLKIN synchronized internally 2E 8P 20E ns 4 ta RSTL ECKO1HZ Delay time RESET low to AECLKOUT1 high impedance 2E ns 5 ta RSTH ECKO1V Delay time RESET high to AECLKOUT1 valid 8P 20E ns 6 la RSTL EMIFZHZ Delay time RESET low to EMIF Z high impedance 2E 3P 4E ns 7 ta RSTH EMIFZV Delay time RESET high to EMIF Z valid 16E 8P 20E ns ta RSTL EMIFHIV Delay time RESET low to EMIF high group invalid 2E ns 9 la RSTH EMIFHV Delay time RESET high to EMIF high group valid 8P 20E ns 10 Iq WSTL EMIFLIV Delay time RESET low to EMIF low group invalid 2 ns 11 la RSTH EMIFLV Delay time RESET high to EMIF low group valid 8P 20E ns 12 lamsTL LOWIV Delay time RESET low to lo
71. state of the input by reading the state of an internal register In addition the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt event generation modes 5 19 1 GPIO Device Specific Information To use the GP 15 0 software configurable GPIO pins the GPxEN bits in the GP Enable GPEN Register and the GPxDIR bits in the GP Direction GPDIR Register must be properly configured GPxEN 1 GP x pin is enabled GPxDIR 0 GP x pin is an input GPxDIR 1 GP x pin is an output where x represents one of the 15 through 0 GPIO pins Figure 5 70 shows the GPIO enable bits in the GPEN register for the DM642 device To use any of the GPx pins as general purpose input output functions the corresponding GPxEN bit must be set to 1 enabled Default values are device specific so refer to Figure 5 70 for the DM642 default configuration 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP15 GP14 GP13 GP12 GP11 GP10 GP9 GP8 GP7 GP6 GP5 GP3 GP2 GP1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 1 R W 1 R W 1 R W 1 R W 1 R W 0 R W 0 R W 1 Legend R W Readable Writable n value after reset undefined value after reset Figure 5 70 GPIO Enable Register GPEN Hex Address 0180 0000 Figure 5 71 shows the GPIO direction
72. subject to change without notice C Flip chip application only D This package is lead free 35 TEXAS INSTRUMENTS www ti com MECHANICAL DATA ZNZ S PBGA N548 PLASTIC BALL GRID ARRAY 25 00 TYP 1 00 OOOOOOOOOO OOOOOOO OOOOOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOOO000000 0000000000000 gt gt T gt gt lt lt lt OOOOOOOOO0000000000 9 11 15 15 17 19 21 23 25 8 10 12 14 16 18 20 22 24 26 Bottom View 2 80 MAX 0 50 NOM C Set Pes f 0 10 251915 4206182 5 06 04 NOTES All linear dimensions are in millimeters B This drawing is subject to change without notice C Flip chip application only D Substrate color may vary E This package is lead free 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to disconti
73. the non aligned load and store instructions allow the D units to access words and doublewords on any byte boundary The C64x CPU supports a variety of indirect addressing modes using either linear or circular addressing with 5 or 15 bit offsets All instructions are conditional and most can access any one of the 64 registers Some registers however are singled out to support specific addressing modes or to hold the condition for conditional instructions if the condition is not automatically true Submit Documentation Feedback Device Overview 7 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 The two M functional units perform all multiplication operations Each of the C64x M units can perform two 16 x 16 bit multiplies or four 8 x 8 bit multiplies per clock cycle The M unit can also perform 16 x 32 bit multiply operations dual 16 x 16 bit multiplies with add subtract operations and quad 8 x 8 bit multiplies with add operations In addition to standard multiplies the C64x M units include bit count rotate Galois field multiplies and bidirectional variable shift hardware The two S and L functional units perform a general set of arithmetic logical and branch functions with results available every clock cycle The arithmetic and logical functions on the C64x CPU include single 32 bit dual 16 bit and quad 8 bit operations The processin
74. 0 DSP platform visit the Texas Instruments web site on the Worldwide Web at http www ti com uniform resource locator URL For information on pricing and availability contact the nearest TI field sales office or authorized distributor Device Overview Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 2 6 2 Device Support 2 6 2 1 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle TI assigns prefixes to the part numbers of all DSP devices and support tools Each DSP commercial family member has one of three prefixes TMX TMP or TMS e g TMS320DM642AGDKA5 Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow TMDX Development support product that has not yet completed Texas Ins
75. 0 2 or McBSP1 data VP1D 11 AD9 input output 1 0 2 default VP1D 10 AE9 By default standalone VP1 data input output pins have no function enabled I O Z upon reset To configure these pins see the Device Configuration section of this VP1D 9 AC8 data sheet 3 VP1D B CLKR19 Bg For more details on the McBSP1 pin functions or the McASPO data pin functions VP1D 7 FSR1 AC7 see McBSP1 McASPO data sections of this table and the Device VP1D 6 DR10 AD7 Configurations section of this data sheet VP1D B CLKS1 9 AE7 VP1D 4 Dx1 AC6 VP1D 3 FSX1 AD6 VP1D 2 CLKxX1 9 AE6 VP1D 1 AF6 VP1D 0 AF5 VP1CLK1 AF10 2 PPD VP1 clock 1 2 VP1CLK0 AF8 II PPD VP1 clock 0 I VP1CTL2 AD5 VP1 control 2 I O Z VP1CTL1 AE5 V O Z D VP1 control 1 2 VP1CTLO AF4 VP1 control 0 I O Z 38 Device Overview Submit Documentation Feedback 4 TEXAS TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL TYPE PD DESCRIPTION NAME NO IPU VIDEO PORT 0 OR McASPO CONTROL OR McBSPO VPOD 19 AHCLKXO 9 AC12 VPOD 18 AFSX0 AD12 VPOD 17 ACLKXO AB13 VPOD 16 AMUTEOO AC13 VPOD 15 y 3 AMUTEINO ech VPOD 14 AHCLKRO AB14 VPOD 13J AFSRO AC14 Video port 0 dat
76. 00 01C8 3FFF Reserved 3 5M 01C8 4000 01FF FFFF QDMA Registers 52 0200 0000 0200 0033 Reserved 736M 52 0200 0034 2FFF FFFF McBSP 0 Data 64M 3000 0000 FFFF McBSP 1 Data 64M 3400 0000 37FF FFFF Reserved 64M 3800 0000 3BFF FFFF McASPO Data 1M 3000 0000 3COF FFFF Reserved 64M 1M 3C10 0000 3FFF FFFF Reserved 832M 4000 0000 73FF FFFF Submit Documentation Feedback Device Overview 13 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 3 TMS320DM642 Memory Map Summary continued MEMORY BLOCK DESCRIPTION SES HEX ADDRESS RANGE VPO Channel A Data 32M 7400 0000 75FF FFFF VP0 Channel B Data 32M 7600 0000 77FF FFFF VP1 Channel A Data 32M 7800 0000 79FF FFFF VP1 Channel B Data 32M 7 00 0000 7BFF FFFF VP2 Channel A Data 32M 7C00 0000 7DFF FFFF VP2 Channel B Data 32M 7 00 0000 7FFF FFFF EMIFA CEO 256M 8000 0000 8FFF FFFF EMIFA CE1 256M 9000 0000 9FFF FFFF EMIFA CE2 256M A000 0000 AFFF FFFF EMIFA 256M B000 0000 BFFF FFFF Reserved 1G C000 0000 FFFF FFFF 14 Device Overview Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 2 3 1 L2 Architecture Expanded Figure 2 2 shows the detail of the L2 arc
77. 01C8 0670 RX4INTACK Reserved Do not write 01C8 0674 RX5INTACK 01C8 0678 RX6INTACK 01C8 067C RX7INTACK 01C8 0680 0108 OFFF e Reserved 154 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 71 EMAC Statistics Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 0200 RXGOODFRAMES Good Receive Frames Register 01C8 0204 RXBCASTFRAMES Broadcast Receive Frames Register 01C8 0208 RXMCASTFRAMES Multicast Receive Frames Register 01C8 020C RXPAUSEFRAMES Pause Receive Frames Register 01C8 0210 RXCRCERRORS Receive CRC Errors Register 01C8 0214 RXALIGNCODEERRORS Receive Alignment Code Errors Register 01C8 0218 RXOVERSIZED Receive Oversized Frames Register 01C8 021C RXJABBER Receive Jabber Frames Register 01C8 0220 RXUNDERSIZED Receive Undersized Frames Register 01C8 0224 RXFRAGMENTS Receive Frame Fragments Register 01C8 0228 RXFILTERED Filtered Receive Frames Register 01C8 022C RXQOSFILTERED Reserved 01C8 0230 RXOCTETS Receive Octet Frames Register 01C8 0234 TXGOODFRAMES Good Transmit Frames Register 01C8 0238 TXBCASTFRAMES Broadcast Transmit Frames Register 01C8 023C TXMCASTFRAMES Multicast Transmit Frames Register 01C8 0240
78. 02 REVISED JANUARY 2007 Table 5 19 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the EMIFA Module 99 see Figure 5 15 500 UNIT MIN MAX 1 tw EKO1H Pulse duration AECLKOUT1 high 07 EH 0 7 2 twEKOIL Pulse duration AECLKOUT1 low EL 07 EL 07 S 3 tekon Transition time AECLKOUT1 1 Ge 4 Delay time AECLKIN high to AECLKOUT1 high 1 8 ns 5 Hla EKIL EKO1L Delay time AECLKIN low to AECLKOUT1 low 1 8 ns 1 EMIF input clock AECLKIN CPU 4 clock or CPU 6 clock period in ns for EMIFA 2 The reference points for the rise and fall transitions are measured at MAX and Vor MIN 3 EHis the high period of E EMIF input clock period in ns and EL is the low period of E EMIF input clock period in ns for EMIFA Al Al f C XA A 2 4 1 tne 3 soom mmn mmm _ J _ Figure 5 15 AECLKOUT1 Timing for the EMIFA Module Table 5 20 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module see Figure 5 16 500 600 PARAMETER 720 UNIT MIN MAX 1 tweKo2H Pulse duration AECLKOUT2 high 0 5NE 0 7 0 5NE 0 7 ns 2 twEKO2L Pulse duration AECLKOUT2 low 0 5NE 0 7 0 5NE 0 7 ns 3 Transition time AECLKOUT2 1 ns 4 la EKIH EKO2
79. 1 HHWIL HAS HR W HCS HDS1 HDS2 MTXD 3 0 MTXEN MRXD 3 0 MRXER MRXDV MCOL MCRS MTCLK MRCLK MDIO MDCLK STCLK A VPOCLKO VPOCLK1 VPOCTL 2 0 VPOD 9 0 E McBSPO AHCLKXO AFSXO ACLKXO AMUTEO AMUTEINO AHCLKRO AFSRO ACLKRO GPO 7 4 McASPO Control c ontro SCLO DCH McASPO Data SDAO AXRO 7 0 McBSP1 VDAC GPO 8 PCIGG STCLK A STCLK A VP1CLKO ud VE s VP2CLKO 10 80 26 810 VP2CLK1 VP1CTL 2 0 VP2CTL 2 0 VP1D 9 0 VP2D 19 0 PERCFG Register Value 0x0000 0079 Extenal Pins PCI EN 0 2 0 HD5 0 TOUTO MAC 1 mi Shading denotes a peripheral module not available for this configuration A STCLK supports all three video ports VP2 VP1 and VPO Figure 3 8 Configuration Example C 1 20 Bit Video Port 2 10 Bit Video Ports 1 McASP0 VIC I2CO EMIF Possible Set Top Box Application Submit Documentation Feedback Device Configurations 69 TMS320DM642 da TEXAS Operating case temperature ranges Tc 40 C to 105 C Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 m 4 Device Operating Conditions 4 1 Absolute Maximum Ratings Over Operating Case Temperature Range Unless Otherwise Noted CVpp 2 0 3 V to 1 8 V voltage ranges 2 9 DVpp 2 0 3Vto 4 V except PCI Vi 0 3 V to 4 V Inp
80. 1 data cache L1D is a 128 Kbit 2 way set associative cache The Level 2 memory cache L2 consists of an 2 Mbit memory space that is shared between program and data space L2 memory can be configured as mapped memory cache or combinations of the two The peripheral set includes three configurable video ports a 10 100 Mb s Ethernet MAC EMAC a management data input output MDIO module a VCXO interpolated control port VIC one multichannel buffered audio serial port McASPO an inter integrated circuit 2 Bus module two multichannel buffered serial ports McBSPs three 32 bit general purpose timers a user configurable 16 bit or 32 bit host port interface 16 2 a peripheral component interconnect PCI a 16 pin general purpose input output port with programmable interrupt event generation modes and a 64 bit glueless external memory interface EMIFA which is capable of interfacing to synchronous and asynchronous memories and peripherals The DM642 device has three configurable video port peripherals VP1 and VP2 These video port peripherals provide a glueless interface to common video decoder and encoder devices The DM642 video port peripherals support multiple resolutions and video standards e g CCIR601 ITU BT 656 BT 1120 SMPTE 125M 260M 274M and 296M These three video port peripherals are configurable and can support either video capture and or video display modes Each video port consis
81. 13 VPOD 6 3 AC AFSRO VPOD 10 DRO VPOCTL1 Vss AED49 AED51 AED55 Vss DVpp Vss AED34 AED35 VPOD 14 VPOD 7Y AHCLKRO VPOD 11 FSRO DVpp Vss DVpp DVpp Vss DVpp AED38 AED36 AED37 Vss AB Vss DVpp Vss Vss DVpp Vss CVpp CVpp Vss AED41 AED39 AED40 AED42 AA CVpp Vss CVpp CVpp Vss CVpp CVpp CVpp DVpp AED45 AED43 AED44 AED46 Y CVpp Vss DVpp AED47 AHOLD DVpp Vss W Vss DVpp Vss AEA18 21 20 19 V CVpp Vss DVpp AEA22 AEA17 AEA16 AEA15 U CVpp Vss ABE7 ABE6 AEA14 AEA13 Vss T Vss CVpp Vss DVpp 5 12 AEA11 5 4 R CVpp Vss CVpp Vss ABUSREQ AEA10 AEA9 DVpp AEA8 P N Le 14 15 16 17 18 19 20 21 22 23 24 2 26 Pu d Es N p Sii Figure 2 4 DM642 Pin Map Quadrant B 18 Device Overview Submit Documentation Feedback 4 TEXAS TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 SES ue s Lebe NE 1 2 8 4 5 6 7 8 9 10 11 12 13 HRDY en HHWIL AINT en e T PIRDY PTRDY PFRAME 55 55 pp HD17 HD16 HD18 M PCBED AD17 AD16 AD18 GPO 0 DVpp Vss CVpp Vss MTXD1 MTXD2 HD19 HD20 HD22 L Vss AD19 AD20 AD22 GE Vss CVpp MTXD3 MTXEN MTCLK ius HD21 HD24
82. 19F FFFF Reserved 5 5 3 External Interrupts Electrical Data Timing Table 5 9 Timing Requirements for External Interrupts see Figure 5 8 500 600 720 UNIT MIN MAX 1 Width of the NMI interrupt pulse low 4P ns MOST Width of the EXT INT interrupt pulse low ns 2 i Width of the NMI interrupt pulse high 4P ns Width of the EXT INT interrupt pulse high 89 ns 1 P 1t CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns 2 1 4 EXT_INTx NM Nf Figure 5 8 External NMI Interrupt Timing 84 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 6 Reset A hardware reset RESET is required to place the DSP into a known good state out of power up The RESET signal can be asserted pulled low prior to ramping the core and I O voltages or after the core and I O voltages have reached their proper operating conditions As a best practice reset should be held low during power up Prior to deasserting RESET low to high transition the core and I O voltages should be at their proper operating conditions and CLKIN should also be running at the correct frequency When PCI is enabled the PCI input clock PCLK must be running prior to deassert
83. 2 developed by Texas Instruments TI making these DSPs an excellent choice for digital media applications The C64x is a code compatible member of the C6000 DSP platform With performance of up to 5760 million instructions per second MIPS at a clock rate of 720 MHz the DM642 device offers cost effective solutions to high performance DSP programming challenges The DM642 DSP possesses the operational flexibility of high speed controllers and the numerical capability of array processors The C64x DSP core processor has 64 general purpose registers of 32 bit word length and eight highly independent functional units two multipliers for a 32 bit result and six arithmetic logic units ALUs with VelociTl 2 extensions The VelociTI 27M extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI architecture The DM642 can produce four 16 bit multiply accumulates MACs per cycle for a total of 2880 million MACs per second MMACS or eight 8 bit MACs per cycle for a total of 5760 MMACS The DM642 DSP also has application specific hardware logic on chip memory and additional on chip peripherals similar to the other C6000 DSP platform devices The DM642 uses a two level cache based architecture and has a powerful and diverse set of peripherals The Level 1 program cache L1P is a 128 Kbit direct mapped cache and the Level
84. 2 14 16 18 20 22 24 26 Bottom View 2 80 MAX 2 Seating Plane 0 50 NOTES Alllinear dimensions are millimeters This drawing is subject to change without notice Flip chip application only Substrate color may vary com E 0 15 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 4202595 5 E 12 02 MECHANICAL DATA ZDK 5 548 PLASTIC BALL GRID ARRAY 20 00 TYP 0 80 gt I OOOOOOOO000000 0000000000000 OOOOOOOOOOOOO0j0000000000000 A1 Corner ooooooi 000000 OOOOOOOO OOOOOO 0000000000 OOOOOOOOO W U R N L J G E C OOOOOOOOOO 15 17 19 21 25 25 14 16 18 20 22 24 26 Bottom View MAX 0 50 NOM 55 eg 0 55 1 95 emer 0 45 251012 0 35 4205951 A 04 04 NOTES All linear dimensions are in millimeters B This drawing is
85. 20 2 JTAG Peripheral Register Description s Table 5 90 JTAG ID Register HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS S Read only Provides 32 bit 01B3 F008 JTAGID JTAG Identification Register JTAG ID of the device 5 20 3 JTAG Test Port Electrical Data Timing Table 5 91 Timing Requirements for JTAG Test Port see Figure 5 74 500 600 720 UNIT MN MAX MAX 1 time 35 ns 3 tsu TDIV TCKH Setup time TDI TMS TRST valid before TCK high 10 ons 4 tnTCKH TDIV Hold time TDI TMS TRST valid after TCK high 9 ns Table 5 92 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port see Figure 5 74 500 600 720 UNIT MN MAX MAX 2 ta TCKL TDOV Delay time TCK low to TDO valid 0 18 ns k _ _ 1 gt JE 2e r TDO 4 4 XX X X 166 DM642 Peripheral Information and Electrical Specifications Figure 5 74 JTAG Test Port Timing Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Revision History This data sheet revision history highlights the technical changes made to the SPRS200K device specific data sheet to make it an SPRS200L revision Scope App
86. 2002 REVISED JANUARY 2007 HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 COCC 0184 COFC e Reserved 0184 C100 DITCSRAO Left even TDM slot channel status register file 0184 C104 DITCSRA1 Left even TDM slot channel status register file 0184 C108 DITCSRA2 Left even TDM slot channel status register file 01B4 C10C DITCSRA3 Left even TDM slot channel status register file 0184 C110 DITCSRA4 Left even TDM slot channel status register file 01B4 0114 DITCSRA5 Left even TDM slot channel status register file 0184 C118 DITCSRBO Right odd TDM slot channel status register file 0184 C11C DITCSRB1 Right odd TDM slot channel status register file 01B4 C120 DITCSRB2 Right odd TDM slot channel status register file 01B4 C124 DITCSRB3 Right odd TDM slot channel status register file 01B4 C128 DITCSRB4 Right odd TDM slot channel status register file 0184 C12C DITCSRB5 Right odd TDM slot channel status register file 01B4 C130 DITUDRAO Left even TDM slot user data register file 01B4 C134 DITUDRA1 Left even TDM slot user data register file 0184 C138 DITUDRA2 Left even TDM slot user data register file 0184 C13C DITUDRA3 Left even TDM slot user data register file 01B4 C140 DITUDRA4 Left even TDM slot user data register file 01B4 C144 DITUDRA5 Left even TDM slot user data register file 01B4 C148 DITUDR
87. 3 V 0 9DVpp 2 V VoL Low level output voltage except PCI DVpp MIN MAX 0 4 V Voip Low level output voltage PCI 1 5 mA DVpp 3 3 V 0 1DVpp 2 V bi to DVpp no opposing internal 10 uA Input current except PCI 2 00 50 100 150 uA opposing internal 150 100 250 uA lip Input leakage current PCI 4 0 lt Vip lt DVpp 3 3 V 10 uA CLKOUT4 CLKOUT6 EMUx 16 mA lou High level output current 11110 1 8 mA PCI HPI 0 5 0 CLKOUT4 CLKOUT6 EMUx 16 mA Video Ports Timer TDO GPIO 8 mA lo Low level output current Excluding 15 9 2 1 McBSP SCLO and SDAO 3 mA PCI HPI 1 5 mA loz Off state output current Vo DVpp or 0 V 10 uA 1 4 V CPU clock 720 MHz 1090 mA lcpp Core supply current CVpp 1 4 V CPU clock 600 MHz 890 mA CVpp 1 2 V CPU clock 500 MHz 620 mA DVpp 3 3 V CPU clock 720 MHz 210 mA looo UO supply current DVpp 3 3 V CPU clock 600 MHz 210 mA DVpp 3 3 V CPU clock 500 MHz 165 mA Input capacitance 10 pF Co Output capacitance 10 pF 1 For test conditions shown as MIN MAX or NOM use the appropriate value specified in the recommended operating conditions table 2 These rated numbers are from the PCI specification version 2 3 The DC specification and AC specification are defined in Table 5 3 and Table 5 4 respectively Applies only to pins with an internal pullup IPU or pulldown IPD re
88. 4 CLKOUT6 A A Internal Clock Tree Clock Distribution and Dividers Internal Peripherals TMS320DM642 CLKIN RESET External input clocks with the exception of CLKIN are not gated by the power down mode logic Figure 5 6 Power Down Mode Logic DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 3 6 Triggering Wake up and Effects The power down modes and their wake up methods are programmed by setting the PWRD field bits 15 10 of the control status register CSR The PWRD field of the CSR is shown in Figure 5 7 and described in Table 5 2 When writing to the CSR all bits of the PWRD field should be set at the same time Logic 0 should be used when writing to the reserved bit bit 15 of the PWRD field The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 31 16 See NOTE 15 14 13 12 11 10 9 8 Enable or Reserved Non Enabled ke PD3 PD2 PD1 See NOTE Interrupt Wake p R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 0 See NOTE Legend R W Readable Writable n value after reset NOTE The shaded bits are not part of the power down logic discussion and therefore are n
89. 5 Schottky Diode Diagram Core and UO supply voltage regulators should be located close to the DSP or DSP array to minimize inductance and resistance in the power delivery path Additionally when designing for high performance applications utilizing the 60007 platform of DSPs the PC board should include separate power planes for core I O and ground all bypassed with high quality low ESL ESR capacitors 5 3 3 Power Supply Decoupling In order to properly decouple the supply planes from system noise place as many capacitors caps as possible close to the DSP Assuming 0603 caps the user should be able to fit a total of 60 caps 30 for the core supply and 30 for the I O supply These caps need to be close to the DSP power pins no more than 1 25 cm maximum distance to be effective Physically smaller caps such as 0402 are better because of their lower parasitic inductance Proper capacitance values are also important Small bypass caps near 560 pF should be closest to the power pins Medium bypass caps 220 nF or as large as can be obtained in a small package should be next closest recommends no less than 8 small and 8 medium caps per supply 32 total be placed immediately next to the BGA vias using the interior BGA space and at least the corners of the exterior Eight larger caps 4 for each supply can be placed further away for bulk decoupling Large bulk caps on the order of 100 should be furthest away but still a
90. 6 TDI RSV05 4 Reserved RSV04 TRST RSV03 EMUO 4 5 02 EMU1 lt gt IEEE Standard RSV01 EMU2 4 gt 1149 1 RSV00 EMU3 lt gt JTAG EMU4 lt Emulation EMU5 lt gt EMU6 4 EE EMU7 4 EMUS 4 EMU9 lt gt Peripheral PCI EN EMU10 4 Control Status TOUTO MAC EN EMU11 Control Status GPO 15 PRST O 4 B 4 gt GPO 7 EXT INT7 8 22 4 gt 6 6 8 GPO 13 PINTA CO 4 gt D GP0 5 EXT_INT5 B GPO 12 PGNT O 4 gt lt GPO A EXT INTA4 B GPO 11 PREQ 4 gt GPO 3 PCIEEAI GPO 10JPCBE3 O lt EE GPO 9 PIDSEL O lt gt lt CLKOUTA GPO 1 VDAC GPO S PCI66 O lt gt lt gt GPO 0 General Purpose Input Output 0 GPO Port A These pins are muxed with the GPO pins by default these signals function as clocks CLKOUT4 or CLKOUT6 To use these muxed pins as GPIO signals the appropriate GPIO register bits GPxEN and GPxDIR must be properly enabled and configured For more details see the Device Configurations section of this data sheet B These pins are GPO pins that can also function as external interrupt sources EXT INT 7 4 Default after reset is EXT INTx or GPIO as input only C These pins are muxed with the PCI peripheral pins and by default these signals are set up to no function with both the GPIO and PCI pin functions disabled For
91. 72 Device Operating Conditions Submit Documentation Feedback d TEXAS INSTRUMENTS TMS320DM642 IBUMER Video Imaging Fixed Point Digital Signal Processor Gen SPRS200L JULY 2002 REVISED JANUARY 2007 5 DM642 Peripheral Information and Electrical Specifications 5 1 Parameter Information 5 1 1 Parameter Information Device Specific Information Tester Pin Electronics Data Sheet Timing Reference Point 420 3 5 nH Output gom O Under E Z0 500 Est see note Device Pin 4 0 pF T 1 85 pF see note NOTE The data sheet provides timing at the device pin For output timing analysis the tester pin electronics and its transmission line effects must be taken into account A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect The transmission line is intended as a load only It is not necessary to add or subtract the transmission line delay 2 ns or longer from the data sheet timings Input requirements in this data sheet are tested with an input slew rate of 4 Volts per nanosecond 4 V ns at the device pin Figure 5 1 Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals This load capacitance value does not indicate the maximum load the device is capable of driving 5 1 1 1 Signal Transition Levels All input and output timing parameters are referenced to 1 5 V for both 0
92. 7FFC Reserved 0184 8000 0184 81FC de d Reserved 0184 8200 MAR128 Controls EMIFA CEO range 8000 0000 80FF FFFF 0184 8204 MAR129 Controls EMIFA CEO range 8100 0000 81FF FFFF 0184 8208 MAR130 Controls EMIFA CEO range 8200 0000 82FF FFFF 0184 820C MAR131 Controls EMIFA CEO range 8300 0000 83FF FFFF 0184 8210 MAR132 Controls EMIFA CEO range 8400 0000 84FF FFFF 0184 8214 MAR133 Controls EMIFA CEO range 8500 0000 85FF FFFF 0184 8218 MAR134 Controls EMIFA CEO range 8600 0000 86FF FFFF 0184 821C MAR135 Controls EMIFA CEO range 8700 0000 87FF FFFF 0184 8220 MAR136 Controls EMIFA CEO range 8800 0000 88FF FFFF 0184 8224 MAR137 Controls EMIFA CEO range 8900 0000 89FF FFFF 0184 8228 MAR138 Controls EMIFA CEO range 8A00 0000 8AFF FFFF 0184 822C MAR139 Controls EMIFA CEO range 8B00 0000 8BFF FFFF 0184 8230 MAR140 Controls EMIFA CEO range 8C00 0000 8CFF FFFF 0184 8234 MAR141 Controls EMIFA CEO range 8D00 0000 8DFF FFFF 0184 8238 MAR142 Controls EMIFA range 8 00 0000 GEFF FFFF 0184 823C MAR143 Controls EMIFA CEO range 8F00 0000 8FFF FFFF 0184 8240 MAR144 Controls EMIFA CE1 range 9000 0000 90FF FFFF 10 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Table 2 2 L2 Cache Registers C64x continued TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007
93. 80 000C Reserved 01B0 0010 GPDH GP0 delta high register 01B0 0014 GPHM GP0 high mask register 01B0 0018 GPDL GP0 delta low register 01B0 001C GPLM GP0 low mask register 01B0 0020 GPGC GP0 global control register 01B0 0024 GPPOL GPO interrupt polarity register 0180 0028 0183 EFFF Reserved Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 163 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 19 3 General Purpose Input Output GPIO Electrical Data Timing Table 5 87 Timing Requirements for GPIO Inputs 2 see Figure 5 72 500 600 720 UNIT MN MAX 1 tw GPIH Pulse duration GPIx high ns 2 Pulse duration GPIx low 8P ns 1 P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns 2 The pulse width given is sufficient to generate a CPU interrupt or an EDMA event However if a user wants to have the DSP recognize the changes through software polling of the GPIO register the duration must be extended to at least 12 to allow the DSP enough time to access the GPIO register through the CFGBUS Table 5 88 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs see Figure 5 72 500 600
94. 9 104 1 Z HCNTL 1 0 X X X X 1 1 11 kH 11 je 10 HR W H11 HHWIL w A SS Y HSTROBE n HCS N HD 15 0 output gt HRDY __ SE d A For correct operation strobe the HAS signal only once per HSTROBE active cycle B HSTRCBE refers to the following logical operation on HCS HDS1 HDS2 NOT HDS1 XOR HDS2 OR HCS Figure 5 39 16 Read Timing HAS Used Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 125 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 HAS 5 1 mam ja ks s HCNTL 1 0 X X X X 1 p l 2 2 HR W L 2 1 2 HHWIL O O 7 Lk 3 gt SENE 3 k 4 HSTROBE A 1 N HCS N x 12 EE 3 12 13 HD 15 0 input BE 1st half word 2nd half word 6 gt l l 14 EH A HSTROBE refers to the following logical operation on HCS HDS1 HDS2 NOT HDS1 XOR 52 OR HCS Figure 5 40 HPI16 Write Timing HAS Not Used Tied High gt 1 19 19 8 _ 1 E eet 11 _ 11 mam O x 104 k HON
95. AARE ASDCAS ASADS ASRE AAOE ASDRAS ASOE and AAWE ASDWE ASWE ASDCKE ASOE3 and APDT B The EKxHZ bits in the EMIF Global Control register GBLCTL determine the state of the ECLKOUTx signals during HOLDA If EKxHZ 0 ECLKOUTx continues clocking during Hold mode If EKxHZ 1 ECLKOUTx goes to high impedance during Hold mode as shown in Figure 5 30 Figure 5 30 HOLD HOLDA Timing for EMIFA 108 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 8 3 5 BUSREQ Timing Table 5 30 Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module see Figure 5 31 600 500 A 600 e PARAMETER 720 UNIT MN MAX MAX MIN MAX MAX 1 la AEKO1H ABUSRV Delay time AECLKOUTx high to ABUSREQ valid 0 6 7 1 1 5 5 ns AECLKOUTx jJ NL X A 2 ke 1 1 y ___ a ABUSREQ f Figure 5 31 BUSREQ Timing for EMIFA Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 109 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 5 9 Multichannel Audio Serial Port McASPO Peripheral 5 9 1 5 9 1 1 110 www ti com The McASP func
96. BO Right odd TDM slot user data register file 01B4 C14C DITUDRB1 Right odd TDM slot user data register file 01B4 C150 DITUDRB2 Right odd TDM slot user data register file 01B4 C154 DITUDRB3 Right odd TDM slot user data register file 01B4 C158 DITUDRB4 Right odd TDM slot user data register file 0184 C15C DITUDRB5 Right odd TDM slot user data register file 01B4 C160 01B4 C17C e Reserved 0184 C180 SRCTLO Serializer 0 control register 0184 C184 SRCTL1 Serializer 1 control register 0184 C188 SRCTL2 Serializer 2 control register 01B4 C18C SRCTL3 Serializer 3 control register 01B4 C190 SRCTL4 Serializer 4 control register 01B4 C194 SRCTL5 Serializer 5 control register 01B4 C198 SRCTL6 Serializer 6 control register 0184 C19C SRCTL7 Serializer 7 control register 01B4 C1A0 01B4 C1FC e Reserved 0184 C200 XBUFO Transmit Buffer for Serializer 0 0184 C204 XBUF1 Transmit Buffer for Serializer 1 0184 C208 XBUF2 Transmit Buffer for Serializer 2 01B4 C20C XBUF3 Transmit Buffer for Serializer 3 01B4 C210 XBUF4 Transmit Buffer for Serializer 4 01B4 C214 XBUF5 Transmit Buffer for Serializer 5 01B4 C218 XBUF6 Transmit Buffer for Serializer 6 01B4 C21C XBUF7 Transmit Buffer for Serializer 7 01B4 C220 01B4 C27C e Reserved 0184 C280 RBUFO Receive Buffer for Serializer 0 0184 C284 RBUF1 Receive Buffer for Serializer 1 0184 C288 RBUF2 Receive Buffer for Serializer 2 Submit Documentation Feedback DM642 Peripheral Information an
97. BSPO is disabled the remaining VPO 1 MCBSPOEN upper data pins are dependent on the MCASPOEN bit and the VP1EN bit settings 1 McBSPO is enabled VPO lower data pin functions are disabled default For a graphic logic representation of this Peripheral Configuration PERCFG Register selection bit and the signal pins controlled selected see Figure 3 2 vs VPO VP1 upper data pins select bit Selects whether the peripheral or the VPO and VP1 upper data pins are enabled 0 McASPO is disabled VPO and VP1 upper data pins are enabled and the VPO and VP1lower data pins are dependent on the MCBSPOEN and VPOEN and MCSBP1EN and VP1EN bits respectively 1 McASPO is enabled VPO and VP1 upper data pins are disabled and the VPO and VP1lower data pins are dependent on the MCBSPOEN and VPOEN and MCSBP1EN andVP1EN bits respectively For a graphic logic representation of this Peripheral Configuration Register selection bit and the signal pins controlled selected see Figure 3 2 Submit Documentation Feedback Device Configurations 57 TMS320DM642 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 un McBSPOEN PERCFG 1 McBSPO VPO Lower Data 10 pins VPO Channel A VPOD 8 2 Muxed VPOD 9 1 0 Standalone McBSP1EN PERCFG 2 McBSP1 VP1 Lower Data 10 pins VP1 Cha
98. BT 656 Y C raw video and TSI modes For video capture operation the video port may operate as two 8 10 bit channels of BT 656 or raw video capture or as a single channel of 8 10 bit BT 656 8 10 bit raw video 16 20 bit Y C video 16 20 bit raw video or 8 bit TSI For video display operation the video port may operate as a single channel of 8 10 bit BT 656 or as a single channel of 8 10 bit BT 656 8 10 bit raw video 16 20 bit Y C video or 16 20 bit raw video It may also operate in a two channel 8 10 bit raw mode in which the two channels are locked to the same timing Channel B is not used during single channel operation For more detailed information on the DM642 Video Port peripherals see the TMS320C64x DSP Video Port VCXO Interpolated Control VIC Port Reference Guide literature number SPRUG29 5 14 2 Video Port Peripheral Register Description s Table 5 61 Video Port 0 1 and 2 VPO VP1 and VP2 Control Registers HEX ADDRESS RANGE VPO VP1 VP2 ACRONYM DESCRIPTION 01C4 0000 01C4 4000 01C4 8000 VP_PIDx Video Port Peripheral Identification Register 01C4 0004 01C4 4004 01C4 8004 VP_PCRx Video Port Peripheral Control Register 01C4 0008 01C4 4008 01C4 8008 Reserved 01C4 000C 01C4 400C 01C4 800C e Reserved 01C4 0020 01C4 4020 01C4 8020 VP PFUNCx Video Port Pin Function Register 01C4 0024 01C4 4024 01C4 8024 VP PDIRx Video Port Pin Direction
99. C0 001G CDSPA Current DSP address register 01C0 0020 CPCIA Current PCI address register 01C0 0024 CCNT Current byte count register 01C0 0028 o Reserved 01C0 002C 01C1 FFEF o 0 7 Reserved 0x01C1 FFF0 HSR Host status register 0x01C1 FFF4 HDCR Host to DSP control register 0x01C1 FFF8 DSPP DSP page register 0x01C1 FFFG o Reserved 01C2 0000 EEADD EEPROM address register 01C2 0004 EEDAT EEPROM data register 01C2 0008 EECTL EEPROM control register 01C2 000C 01C2 FFFF Reserved 01C3 0000 PCI transfer request control register 01C3 0004 01C3 FFFF o Reserved Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 129 TMS320DM642 d TEXAS Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 5 12 3 Electrical Data Timing 5 12 3 1 Peripheral Component Interconnect PCI Timing Table 5 42 Timing Requirements for PCLK see Figure 5 46 500 A 600 600 720 33 MHz 66 MHz UNIT MN MAX MAX 1 Cycle time PCLK 30 4P 3 15 9 ns 2 lw PCLKH Pulse duration PCLK high 11 e mns 3 twPCLKL Pulse duration PCLK low 11 e ns 4 01 Av At slew rate PCLK 1 4 1 5 4 Vins 1 For 3 3 V operation the reference points for the rise and fall transitions are measured at Vi
100. C4 4160 01C4 8160 VC BEVTCTx Video Capture Channel B Event Count Register 0104 0180 01 4 4180 01C4 8180 TSI CTLx TCI Capture Control Register 01C4 0184 01C4 4184 01C4 8184 TSI CLKINITLx TCI Clock Initialization LSB Register 01C4 0188 01C4 4188 01C4 8188 TSI CLKINITMx TCI Clock Initialization MSB Register 01C4 018C 01C4 418C 01C4 818C TSI STCLKLx TCI System Time Clock LSB Register 0104 0190 01C4 4190 01C4 8190 TSI STCLKMx TCI System Time Clock MSB Register 0104 0194 01C4 4194 01C4 8194 TSI STCMPLx TCI System Time Clock Compare LSB Register 0104 0198 01 4 4198 01C4 8198 TSI STCMPMx System Time Clock Compare MSB Register 01C4 019C 01C4 419C 01C4 819C TSI STMSKLx TCI System Time Clock Compare Mask LSB Register 01C4 01A0 01C4 41A0 01C4 81A0 TSI STMSKMx TCI System Time Clock Compare Mask MSB Register 0104 01A4 01C4 41A4 0104 81A4 TSI TICKSx TCI System Time Clock Ticks Interrupt Register 01C4 0200 01C4 4200 01C4 8200 VD STATx Video Display Status Register 0104 0204 01 4 4204 01C4 8204 VD CTLx Video Display Control Register 01C4 0208 01C4 4208 01C4 8208 VD FRMSZx Video Display Frame Size Register 01C4 020C 01C4 420C 01C4 820C VD HBLNKx Video Display Horizontal Blanking Register 01C4 0210 01C4 4210 01C4 8210 VD VBLKS1x Video Display Field 1 Vertical Blanking Start Register 01C4 0214 01C4 4214 01 4 8214 VD VBLKE1x Video Display Field 1 Vertical Blanking End Register 01C4 0218 01C4 4218 01C4 8218 VD VBLKS2x Video Display Field 2 Vertic
101. CLKOUTA Peripheral Clock 4 AUXCLK for McASP McBSP Internal Clock CLKMODEO CLKOUT6 CLKMODE1 PLL X6 x12 CLKIN PLLCLK ECLKIN AEA 20 19 m 0116 EK2RATE GBLCTL 19 18 Internal to DM642 v ECLKOUT1 ECLKOUT2 For the PLL Options CLKMODE Pins Setup and PLL Clock Frequency Ranges see the TMS320DM642 PLL Multiply Factor Options Clock Frequency Ranges and Typical Lock Time table NOTES Place all PLL external components C1 C2 and the EMI Filter as close to the C6000 DSP device as possible For the best performance TI recommends that all the PLL external components be on a single side of the board without jumpers switches or components other than the ones shown For reduced PLL jitter maximize the spacing between switching signals and the PLL external components C1 C2 and the EMI Filter The 3 3 V supply for the EMI filter must be from the same 3 3 V power plane supplying the I O voltage Dypp EMI filter manufacturer part number ACF451832 333 223 153 103 Panasonic part number 1030 Figure 5 10 External PLL Circuitry for Either PLL Multiply Modes or x1 Bypass Mode Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 89 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 12
102. CLKX period 1 CLKGDV S CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd or zero FSRP FSXP 1 As a SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX Figure 5 55 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 1 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 59 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 1 see Figure 5 56 500 600 SC UNIT MASTER SLAVE MIN MAX MIN MAX tsu DRV CKXH Setup time DR valid before CLKX high 12 2 12P ns 5 th CKXH DRV Hold time DR valid after CLKX high 4 5 24 ons 2 Table 5 60 Switching Characteristics Over Recommended Master or Slave CLKSTP gt 11b CL
103. D 7 FSR1 TOUTO TOUT1 VDAC GPO 8J PCI66 GPO 7 0 GPO 10 PCBES HR W PCBE2 HDS2 PCBEi PCBEO GPO 13 PINTA GPO 11 PREQ HDS1 PSERR HCS PPERR HCNTL1 PDEVSEL HAS PPAR HCNTLO PSTOP HHWIL PTRDY 16 bit HPI mode only HRDY PIRDY HINT PFRAME VPOD 19 9 6 5 1 0 VP1D 19 9 6 5 1 0 and VP2D 19 0 B If AEA 22 19 LENDIAN PCIEEAI and HD5 ADS pins are actively driven care must be taken to ensure no timing contention between parameters 6 7 14 15 16 and 17 C Boot and Device Configurations Inputs during reset include AEA 22 19 LENDIAN PCIEEAI and HD5 AD5 The PCI EN pin must be driven valid at all times and the user must not switch values throughout device operation Figure 5 9 Reset Timing Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 87 TMS320DM642 K Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 5 7 Clock PLL 5 7 1 88 www ti com The PLL controller features hardware configurable PLL multiplier controller dividers 2 4 6 and 8 and reset controller The PLL controller accepts an input clock as determined by the logic state on the CLKMODE 1 0 pins from the CLKIN pin The resulting clock outputs are passed to the DSP core peripherals and other modules inside the C6000 DSP Clock PLL Device Specific Information Most of the internal C64x DSP clocks
104. E VR Mes ICC ka INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 1 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor 1 1 Features High Performance Digital Media Processor 2 3 1 67 1 39 ns Instruction Cycle Time 500 600 720 MHz Clock Rate Eight 32 Bit Instructions Cycle 4000 4800 5760 MIPS Fully Software Compatible With C64x VelociTl 2 Extensions to VelociTI Advanced Very Long Instruction Word VLIW TMS320C64x DSP Core Eight Highly Independent Functional Units With VelociTl 2 Extensions Six ALUs 32 40 Bit Each Supports Single 32 Bit Dual 16 Bit or Quad 8 Bit Arithmetic per Clock Cycle Two Multipliers Support Four 16 x 16 Bit Multiplies 32 Bit Results per Clock Cycle or Eight 8 x 8 Bit Multiplies 16 Bit Results per Clock Cycle Load Store Architecture With Non Aligned Support 6432 Bit General Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Instruction Set Features Byte Addressable 8 16 32 64 Bit Data 8 Bit Overflow Protection Bit Field Extract Set Clear Normalization Saturation Bit Counting VelociTI 27 Increased Orthogonality L1 L2 Memory Architecture 128K Bit 16K Byte L1P Program Cache Direct Mapped 128K Bit
105. E13 VP2D 18 E12 VP2D 17 D12 VP2D 16 C12 VP2D 15 B12 VP2D 14 E11 VP2D 13 D11 VP2D 12 C11 VP2D 11 B11 VP2D 10 M1 Video port 2 VP2 data input output 1 2 VP2D 9 D10 VO Z Note By default no function is enabled upon reset To configure these pins see the Device Configuration section of this data sheet VP2D 8 C10 VP2D 7 B10 VP2D 6 A10 VP2D 5 D9 VP2D 4 C9 VP2D 3 B9 VP2D 2 A9 VP2D 1 D8 VP2D 0 C8 VP2CLK1 A13 2 PPD VP2 clock 1 2 VP2CLKO A7 or PPD VP2 clock 0 1 VP2CTL2 C7 VP2 control 2 I O Z VP2CTL1 D7 2 D VP2 control 1 1 0 2 VP2CTLO B8 VP2 control 0 I O Z Submit Documentation Feedback Device Overview 37 TMS320DM642 da TEXAS Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 www ti com Table 2 4 Terminal Functions continued SIGNAL IPD TYPE 2 DESCRIPTION NAME NO IPU VIDEO PORT 1 VP1 OR McASPO DATA OR McBSP1 VP1D 19J AXRO 7 9 AB12 VP1D 18J AXRO 6 9 AB11 VP1D 17 AXRO 5 AC11 VP1D 16J AXRO 4 9 AD11 VP1D 15J AXRO 3 AE11 VP1D 14J AXRO 2 9 AC10 3 3 0910 Video port 1 VP1 data input output 2 or McASPO data pins 2 VP1D 12 J AXRO 0 9 AC9 default and Video port 1 1 data input output
106. EEXT 0 B The following parameters are programmable via the EMIF CE Space Secondary Control register CExSEC Read latency SYNCRL 0 1 2 or 3 cycle read latency Write latency SYNCWL 0 1 2 or 3 cycle write latency ACEx assertion length CEEXT For standard SBSRAM or ZBT SRAM interface ACEx goes inactive after the final command has been issued CEEXT 0 For synchronous FIFO interface with glue is active when ASOE is active CEEXT 1 Function of ASADS ASRE RENEN For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles RENEN 0 For FIFO interface ASADS ASRE acts as ASRE with NO deselect cycles RENEN 1 Function of ASADS ASRE RENEN For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles RENEN 0 For FIFO interface ASADS ASRE acts as ASRE with NO deselect cycles RENEN 1 Synchronization clock SNCCLK Synchronized to ECLKOUT1 or ECLKOUT2 C AARE ASDCAS ASADS ASRE AAOE ASDRAS ASOE and AAWE ASDWE ASWE operate as ASADS ASRE ASOE and ASWE respectively during programmable synchronous interface accesses Figure 5 21 Programmable Synchronous Interface Write Timing for EMIFA With Write Latency 1 AB Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 101 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200
107. Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 14 3 5 Video Dual Display Sync Mode Timing With Respect to VPxCLKINx Table 5 67 Timing Requirements for Dual Display Sync Mode for VPxCLKINx see Figure 5 61 500 600 720 UNIT MN MAX MAX 1 sk vKD Skew rate VPXCLKINx before VPyCLKINy 500 ps wene N00 98N TT 1 H ZE Figure 5 61 Video Port Dual Display Sync Timing Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 149 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 5 15 VCXO Interpolated Control VIC www ti com The VIC can be used in conjunction with the Video Ports VPs to maintain synchronization of a video stream The VIC can also be used to control a VCXO to adjust the pixel clock rate to a video port 5 15 1 Device Specific Information The VCXO interpolated control VIC port provides digital to analog conversation with resolution from 9 bits to up to 16 bits The output of the VIC is a single bit interpolated D A output VDAC pin Typical D A converters provide a discrete output level for every value of the digital word that is being converted This is a problem for dig
108. FSR X input valid before ACLKR X latches data ACLKRIX ext A a C ACLKR X int 5 ln CKRX FRX Hold time AFSR X input valid after ACLKR X latches data ACLKR X ext 5 SS 7 lsu AXR CKRX Setup time AXR input valid before ACLKR X latches data EE 2 ns ACLKR X ext 5 ns C ACLKR X int 5 ns n ln CKRX AXR Hold time AXR input valid after ACLKR X latches data ACLKR X ext 5 1 ACLKX internal ACLKXCTL CLKXM 1 PDIR ACLKX 1 ACLKX external input ACLKXCTL CLKXM 0 PDIR ACLKX 0 ACLKX external output ACLKXCTL CLKXM 0 PDIR ACLKX 1 ACLKR internal ACLKRCTL CLKRM 1 PDIR ACLKR 1 ACLKR external input ACLKRCTL CLKRM 0 PDIR ACLKR 0 ACLKR external output ACLKRCTL CLKRM 0 PDIR ACLKR 1 114 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback wy TEXAS INSTRUMENTS www ti com Table 5 34 Switching Characteristics Over Recommended Operating Conditions for McASP see Figure 5 33 and Figure 5 34 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 500 600 PARAMETER 720 UNIT MN MAX MAX Cycle time AHCLKR X 20 ns 10 twAHCKRX Pulse duration AHCLKR X high or low 10 ns 11 Cycle time ACLKR X int 33 12 Pulse duration ACLKR X high or low ACLKR X int 16 5 ns 13 la cKRX FR
109. GNZ 548 40 TBD SNPB Level 4 220C 72 HR TMS320DM642AGNZ6 ACTIVE FCBGA GNZ 548 40 TBD SNPB Level 4 220C 72 HR TMS320DM642AGNZ7 ACTIVE FCBGA GNZ 548 40 TBD SNPB Level 4 220C 72 HR TMS320DM642AGNZA5 ACTIVE FCBGA GNZ 548 40 TBD SNPB Level 4 220C 72 HR TMS320DM642AGNZA6 ACTIVE FCBGA GNZ 548 40 TBD SNPB Level 4 220C 72 HR TMS320DM642AZDK5 ACTIVE FCBGA ZDK 548 60 Pb Free RoHS SNAGCU Level 4 260C 72HR Exempt TMS320DM642AZDK6 ACTIVE FCBGA ZDK 548 60 Pb Free ROHS SNAGCU Level 4 260C 72HR Exempt TMS320DM642AZDK7 ACTIVE FCBGA ZDK 548 60 Pb Free ROHS SNAGCU Level 4 260C 72HR Exempt TMS320DM642AZDKA5 ACTIVE FCBGA ZDK 548 60 Pb Free RoHS SNAGCU Level 4 260C 72HR Exempt TMS320DM642AZDKA6 ACTIVE FCBGA ZDK 548 60 Pb Free RoHS SNAGCU Level 4 260C 72HR Exempt TMS320DM642AZNZ5 ACTIVE FCBGA ZNZ 548 40 Pb Free RoHS SNAGCU Level 4 260C 72HR Exempt TMS320DM642AZNZ6 ACTIVE FCBGA ZNZ 548 40 Pb Free RoHS SNAGCU Level 4 260C 72HR Exempt TMS320DM642AZNZ7 ACTIVE FCBGA ZNZ 548 40 Pb Free RoHS SNAGCU Level 4 260C 72HR Exempt TMS320DM642AZNZA5 ACTIVE FCBGA ZNZ 548 40 Pb Free RoHS SNAGCU Level 4 260C 72HR Exempt TMS320DM642AZNZA6 ACTIVE FCBGA ZNZ 548 40 Pb Free ROHS SNAGCU Level 4 260C 72HR Exempt TMS320DM642GDK500 ACTIVE FCBGA GDK 548 TBD Call TI Call TI TMS320DM642GDK600 OBSOLETE FCBGA GDK 548 TBD Call TI Call TI TMS320DM642GDK720 OBSOLETE FCBGA GDK 548 TBD Call TI Call TI TMS320DM642GDKA500 OBSOLETE FCBGA GDK 548 TBD Call TI Call TI TMS320DM642GNZ500 OB
110. GPO 15 PRST G3 General purpose input output 15 pin I O Z or PCI reset 3 14 pin 2 or PCI clock e e atn et 13 pin 2 or PCI interrupt A O Z GPO 13 PINTA G4 12 pin I O Z or PCI bus grant POM 2VPGNT H4 0 2 11 pin 1 0 2 or PCI bus request O Z GP0 a 10 I O Z or PCI command byte enable I O Z GPO 11 PRE F1 9 l O Z or PCI initialization device select GPO 10 PCBE3 Je Note By default no function is enabled upon reset To configure these pins see GPO 9 PIDSEL K3 the Device Configuration section of this data sheet GPO pin 0 2 3 Boot Configuration PCI EEPROM Auto Initialization EEAI GPO 3 5 Vorz D 0 PCI auto initialization through EEPROM is disabled default 1 PCI auto initialization through EEPROM is enabled VCXO Interpolated Control Port VIC single bit digital to analog converter VDAC output output only default or this pin can be programmed as a GPO 8 pin 2 EOS Boot Configuration PCI frequency selection PCI66 If the PCI peripheral is enabled PCI EN pin 1 then SEA 0 PCI operates at 66 MHz default VDAC GPO 8 PCI66 9 AD1 2 1 PCI operates at 33 MHz The 500 device supports PCI at 33 MHz only For proper 500 device operation when the PCI peripheral is enabled PCI EN 1 this pin must be pulled up with 1 resistor at device reset Note If the PCI peripheral is dis
111. H Delay time AECLKIN high to AECLKOUT2 high 1 8 ns 5 lq EKIL EKO2L Delay time AECLKIN low to AECLKOUT2 low 1 8 ns 1 The reference points for the rise and fall transitions are measured at Vo MAX and Voy MIN 2 E the EMIF input clock AECLKIN CPU 4 clock or CPU 6 clock period in ns for EMIFA N the EMIF input clock divider 1 2 or 4 AELKN Af CHofy wu Nw A oe Oe N je 5 A 1 2 7 z ck agcukoUT2 Jf Fd TN Figure 5 16 AECLKOUT2 Timing for the EMIFA Module Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 93 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 5 8 External Memory Interface EMIF 5 8 1 94 www ti com EMIF supports a glueless interface to a variety of external devices including e Pipelined synchronous burst SRAM SBSRAM e Synchronous DRAM SDRAM e Asynchronous devices including SRAM ROM and FIFOs e An external shared memory device EMIF Device Specific Information EMIF Device Speed The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets the following requirements e 1 chip enable CE space maximum of 2 chips of SDRAM connected to EMIF e upto 1 CE space of buffers connected to trace lengths between 1 3 inches e 166 MHz SDRAM for 133 MHz
112. HPI operates as an 16 HPI bus is 16 bits wide HD 15 0 pins used and the remaining HD 31 16 pins are reserved pins in HD5 AD5 Y1 the Hi Z state 1 HPI operates as an 2 HPI bus is 32 bits wide All HD 31 0 pins are used for host port operations Also see the PCI EN TOUTO MAC EN functional description in this table Submit Documentation Feedback Device Configurations 55 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 3 3 DM642 Device Configuration Pins TOUT1 LENDIAN AEA 22 19 GPO 3 PCIEEAI VDAC GPO S8 PCI66 HD5 AD5 PCI EN MAC EN continued E AUN wm FUNCTIONAL DESCRIPTION Peripheral Selection PCI EN 00 HPI default mode 2 if HD5 1 HPI16 if HD5 0 TOUTOMAC EN 20 8 01 and MDIO HPI16 if HD5 0 HPI disabled if HD5 1 in Ge 3 2 Configurations After Reset 3 2 1 Peripheral Selection After Device Reset Video Ports McBSP1 McBSPO McASPO and 2 0 The DM642 device has designated registers for peripheral configuration PERCFG device status DEVSTAT and JTAG identification JTAGID These registers are part of the Device Configuration module and are mapped to a 4K block memory starting at 0x01B3F000 The CPU accesses these registers via the CFGBUS The peripheral configuration register PERCFG allows the us
113. IFA 64 bit ASYNCHRONOUS SYNCHRONOUS MEMORY CONTROL EMIFA external input clock The EMIFA input clock AECLKIN CPU 4 clock or C CPUJ 6 clock is selected at reset via the pullup pulldown resistors on the AECLKIN H25 D AEA 20 19 pins AECLKIN is the default for the EMIFA input clock C EMIFA output clock 2 Programmable to be EMIFA input clock AECLKIN AECLKOUT2 J23 0 2 CPU 4 clock or CPU 6 clock frequency divided by 1 2 or A C EMIFA output clock 1 at EMIFA input clock AECLKIN CPU 4 clock or CPU 6 AECLKOUT1 J26 O Z ES clock frequency EMIFA asynchronous memory read enable SDRAM column address AARE strobe programmable synchronous interface address strobe or read enable ASDCAS J25 O Z IPU e For programmable synchronous interface the RENEN field in the Se ASADS ASRE Secondary Control Register CExSEC selects between ASADS and ASRE If RENEN 0 then the ASADS ASRE signal functions as the ASADS signal If RENEN 1 then the ASADS ASRE signal functions as the ASRE signal EE J24 O Z IPU EMIFA asynchronous memory output enable SDRAM row address ASOE strobe programmable synchronous interface output enable AAWE EMIFA asynch ite enable SDRAM write enable bl ASDWE K26 O Z IPU asynchronous memory write enable write enable programmable ASWE synchronous interface write enable EMIFA SDRAM clock enable used for self refresh mode ASDCKE L25 O Z IPU e SDRAM is not in system ASDCKE can be used as a general purpose output ASOE
114. IN for EMIFA 999 see Figure 5 14 500 600 720 UNIT MN MAX MAX 1 lc EKI Cycle time AECLKIN eo 16P ns 2 Lw EKIH Pulse duration AECLKIN high 2 7 ns 3 tw EKIL Pulse duration AECLKIN low 2 7 ns 4 tekn Transition time AECLKIN 3 5 Period jitter AECLKIN 0 02 ns P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns The reference points for the rise and fall transitions are measured at Vu MAX and MIN E the EMIF input clock AECLKIN CPU 4 clock or CPU 6 clock period in ns for EMIFA Minimum AECLKIN cycle times must be met even when AECLKIN is generated by an internal clock source Minimum AECLKIN times are based on internal logic speed the maximum useable speed of the EMIF may be lower due to AC timing requirements On the 600 and 720 devices 133 MHz operation is achievable if the requirements of the EMIF Device Speed section are met On the 500 devices 100 MHz operation is achievable if the requirements of the EMIF Device Speed section are met ww C 5 1 i Te 2 d AECLKIN ag E k 3 u 4 3 le Figure 5 14 AECLKIN Timing for EMIFA 92 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 20
115. IS Models for Timing Analysis application report literature number SPRA839 If needed external logic hardware such as buffers may be used to compensate any timing differences For inputs timing is most impacted by the round trip propagation delay from the DSP to the external device and from the external device to the DSP This round trip delay tends to negatively impact the input setup time margin but also tends to improve the input hold time margins see Table 5 1 and Figure 5 4 Figure 5 4 represents a general transfer between the DSP and an external device The figure also represents board route delays and how they are perceived by the DSP and the external device Table 5 1 Board Level Timing Example see Figure 5 4 z o DESCRIPTION Clock route delay Minimum DSP hold time Minimum DSP setup time External device hold time requirement External device setup time requirement Control signal route delay External device hold time External device access time CO OO a DSP hold time requirement DSP setup time requirement Data route delay ICH 2 2 Output from DSP 1 ECLKOUTx Z ia NIY N Z N Input to External Device a 2 Control Signals Output from DSP xd t 5 Control Signals 6 _ Input to External Device k 7 Data Signals B ee 6 Output from Ex
116. Ir Device reset Nonmaskable interrupt edge driven rising edge NMI B4 Note Any noise on the NMI pin may trigger an NMI interrupt therefore if the NMI pin is not used it is recommended that the NMI pin be grounded versus relying on the IPD GPO 7 EXT INT7 E1 VO Z IPU General purpose input output GPIO pins 1 2 or external interrupts input GPO 6 EXT_INT6 F2 7 IPU only The default after reset setting is GPIO enabled as input only e When these pins function as External Interrupts by selecting the GPO SVEXT_INTS F3 0 2 IPU corresponding interrupt enable register bit IER 7 4 they are edge driven GPO AVEXT INT4 F4 O Z IPU 1 5 selected via the External Interrupt 1 I Input Output Z High impedance S Supply voltage GND Ground A Analog signal 2 IPD Internal pulldown Internal pullup These IPD IPU signal pins feature a 30 or resistor To pull up a signal to the opposite supply rail 1 resistor should be used These pins are multiplexed pins For more details see the Device Configurations section of this data sheet 4 PLLV is not part of external voltage supply See the Clock PLL section for information on how to connect this pin The EMUO EMU1 pins are internally pulled up with 30 kQ resistors therefore for emulation and normal operation no external pullup pulldown resistors are necessary However for boundary scan operation pull
117. KXP i P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns For all SPI Slave modes CLKG is programmed as 1 4 of the CPU clock by setting CLKSM CLKGDV 1 erating Conditions for McBSP as SPI see Figure 5 56 500 600 PARAMETER Een UNIT MASTER SLAVE MN MAX MAX MIN MAX 1 th CKXH FXL Hold time FSX low after CLKX high H 2 H 3 ns 2 taexL ckxL Delay time FSX low to CLKX low T 25 T 15 ns 3 la CKXH DXV Delay time CLKX high to DX valid 2 4 12P 3 20P 17 ns s ee occ high impedance following last data bit 2 4 12 3 20 17 n 7 la FXL DXV Delay time FSX low to DX valid L 2 1 4 8P 2 16 17 ns P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns For all SPI Slave modes CLKG is programmed as 1 4 of the CPU clock by setting CLKSM CLKGDV 1 S Sample rate generator input clock 4P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock clks if CLKSM 0 P clks CLKS period T CLKX period 1 CLKGDV S CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd or zero on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master M
118. L JULY 2002 REVISED JANUARY 2007 5 8 3 3 Synchronous DRAM Timing Table 5 26 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module see Figure 5 22 600 e M 720 UNIT MIN MAX MAX MIN MAX 6 tsu EDV EKO1H Setup time read AEDx valid before AECLKOUTx high 2 1 06 ns th EKO1H EDV Hold time read AEDx valid after AECLKOUTx high 2 8 2 1 ons Table 5 27 Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM Cycles for EMIFA Module see Figure 5 22 Figure 5 29 500 A 600 00 e PARAMETER 720 UNIT MIN MAX MIN MAX 1 la EKO1H CEV Delay time AECLKOUTx high to ACEN valid 1 3 6 4 1 3 4 9 ns 2 la EKO1H BEV Delay time AECLKOUTx high to ABEx valid 6 4 4 9 ns 3 la EKO1H BEIV Delay time AECLKOUTx high to ABEx invalid 1 3 1 3 ns 4 la EKO1H EAV Delay time AECLKOUTx high to AEAx valid 6 4 4 9 ns 5 la EKO1H EAIV Delay time AECLKOUTx high to AEAx invalid 1 3 1 3 ns 8 la EKO1H CASV Delay time AECLKOUTx high to ASDCAS valid 1 3 6 4 1 3 4 9 ns 9 la EKO1H EDV Delay time AECLKOUTx high to AEDx valid 6 4 4 9 ns 10 tia EKO1H EDIV Delay time AECLKOUTx high to AEDx invalid 1 3 1 3 ns 11 tyexo1H wev Delay time AECLKOUTx high to ASDWE valid 1 3 6 4 1 3 4 9 ns 12 tyexo1H Ras Delay time AECLKOUTx high to ASDRAS valid 1 3 6 4 1 3 4 9 ns 13 1
119. MODEO AA2 D Bypass x8 e For more details on the CLKMODE pins and the PLL multiply factors see the Clock PLL section of this data sheet PLLV 4 V AU PLL voltage supply JTAG EMULATION TMS E15 1 IPU JTAQ test port mode select TDO B18 O Z IPU JTAG test port data out TDI A18 o IPU JTAG test port data in TCK A16 1 IPU JTAQ test port clock TRST D14 mu JTAG test port reset For IEEE 1149 1 JTAG compatibility see the IEEE 1149 1 JTAG compatibility statement portion of this data sheet EMU11 D17 VO Z IPU Emulation pin 11 Reserved for future use leave unconnected EMU10 C17 VO Z IPU Emulation pin 10 Reserved for future use leave unconnected EMU9 817 I O Z IPU Emulation pin 9 Reserved for future use leave unconnected EMU8 D16 2 Emulation pin 8 Reserved for future use leave unconnected EMU7 A17 VO Z IPU Emulation pin 7 Reserved for future use leave unconnected EMU6 C16 VO Z IPU Emulation pin 6 Reserved for future use leave unconnected EMU5 B16 VO Z IPU Emulation pin 5 Reserved for future use leave unconnected EMU4 D15 2 IPU Emulation pin 4 Reserved for future use leave unconnected EMU3 C15 VO Z IPU Emulation pin 3 Reserved for future use leave unconnected EMU2 815 VO Z IPU Emulation pin 2 Reserved for future use leave unconnected EMU1 C14 2 IPU Emulation pin 1 5 EMUO A15 2 IPU Emulation pin 0 5 RESETS INTERRUPTS AND GENERAL PURPOSE INPUT OUTPUTS RESET P4
120. O VPO 2080 VPOCLK1 TOUTO MACEN 2 01 VPOD 19 0 GP0 15 9 3 0 McBSPO GPO 7 4 McASPO Control SCLO I2CO McASPO Data SDAO VDAC GP0 8 PCI66 STCLK A STCLK A VP1CLKO p VP1 Sue VP2CLKO VP1CLK1 20 Bit 20 20 VP2CLK1 VP1CTL 2 0 VP2CTL 2 0 VP1D 19 0 VP2D 19 0 PERCFG Register Value 0x0000 0078 External Pins PCI EN 0 GPO S PCIEEAI 0 HD5 0 TOUTO MAC EN 1 Shading denotes a peripheral module not available for this configuration A STCLK supports all three video ports VP2 VP1 and VPO Figure 3 6 Configuration Example A 3 20 Bit Video Ports HPI EMAC NDIO DCH EMIF Timers Submit Documentation Feedback Device Configurations 67 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 AED 63 0 AECLKIN AARDY AHOLD AEA 22 3 ACE 3 0 ABE 7 0 AECLKOUT1 AECLKOUT2 ASDCKE ASOE3 APDT Clock AHOLDA ABUSREQ and AARE ASDCAS ASADS ASRE System AAOE ASDRAS ASOE AAWE ASDWE ASWE L CLKIN CLKMODEO CLKMODE1 TIMER2 L CLKOUTA CLKOUT6 PLLV TINP1 TIMER1 TOUT1 LENDIAN HD 15 0 HRDY HINT HCNTLO HCNTL 1 HHWIL HAS HR W HCS HDS1 HDS2 MTXD 3 0 MTXEN HPI 16 Bit o MRXD 3 0 MRXER MRXDV MCOL MCRS MTCLK MRCLK MDIO MDCLK A STCLK A E TINPO VPOCLKO been TIMERO VPOCLK1
121. O 3 4 AXRO 5 E AXRO 6 a ae z AXRO 7 a 2 2 Receive GPIO Data Control lt Formatter D Figure 5 32 McASPO Configuration Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 111 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 9 2 MCcASPO Peripheral Register Description s Table 5 31 McASPO Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 C000 PD Peripheral Identification register Register value 0x0010 0101 0184 C004 PWRDEMU Power down and emulation management register 0184 C008 e Reserved 0184 COOC e Reserved 0184 C010 PFUNC Pin function register 0184 C014 PDR Pin direction register 01B4 C018 PDOUT Pin data out register 0184 C01C PDIN PDSET Pin data in data set registerRead returns PDINWrites affect PDSET 0184 C020 PDCLR Pin data clear register 0184 C024 0184 C040 e Reserved 0184 C044 GBLCTL Global control register 0184 C048 AMUTE Mute control register 01B4 C04C DLBCTL Digital Loop back control register 0184 C050 DITCTL DIT mode control register 0184 C054 0184 C05C e Reserved 0184 C060 RGBLCTL 2 only Receiver Reset bits allows transmit to be reset 01B4 C064 RMASK Receiver format UNIT bit mask register 0184 C068 RFMT Receive bit str
122. Operating case temperature A version A 500 and A 600 40 105 C 1 Future variants of the C64x DSPs may operate at voltages ranging from 0 9 V to 1 4 V to provide a range of system power performance options TI highly recommends that users design in a supply that can handle multiple voltages within this range i e 1 2 V 1 25 V 1 3 V 1 35 V 1 4 V with 3 tolerances by implementing simple board changes such as reference resistor values or input pin configuration modifications Examples of such supplies include the PT4660 PT5500 PT5520 PT6440 and PT6930 series from Power Trends a subsidiary of Texas Instruments Not incorporating a flexible supply may limit the system s ability to easily adapt to future versions of C64x devices 2 The absolute maximum ratings should not be exceeded for more than 30 of the cycle period 70 Device Operating Conditions Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 4 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Unless Otherwise Noted PARAMETER TEST CONDITIONS 1 MIN TYP MAX UNIT Vou High level output voltage except PCI DVpp MIN lop MAX 2 4 V High level output voltage PCI loup 0 5 mA DVpp 3
123. P1D 18 VP1D 19y VPOD 17y Vss Vss RSV Vss DVpp Vss DVpp 0 50 Vss Diop AXRO 7 ACLKXO HD1 AA ADI CLKMODEO RSV Vss Vss CVpp CVpp Vss DVpp Vss Vss DVpp Vss Y HD5 HD3 HDO HD2 Bj o en y Bs AD5 AD3 ADO AD2 DD DD DD DD 55 DD DD 55 DD T y HD7 HD4 HD6 BEN ss AD7 AD4 AD6 DD Vss 5 HD10 HD8 HD9 V AD10 ADS ADS PCBEO Vss Vss HD14 HD12 HD13 HD11 U AD14 AD12 AD13 AD11 Vss T HDS 2 eg XSP CS V V S9 PCBE1 AD15 Ss 55 HCS HDS1 HCNTLO XSP_CLK R m PPERR PSERR PSTOP SE MDCLK RSV Vss Vss CVpp HCNTL1 HAS XSP_DO P PDEVSEL Ss PPAR RESET MDIO Vss VoD Vss 1 RENE NE 6 7 8 9 10 11 12 13 E e 7 Submit Documentation Feedback Figure 2 3 DM642 Pin Map Quadrant A Device Overview 17 TMS320DM642 d Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 E 14 15 16 17 18 19 20 21 22 23 24 25 26 VPOD Sy VPOD 2 VPOCLKO Vss GE VPOD O0 Vss AED50 AED54 Vss AED62 AED63 DVpp Vss AF VPOD 8 VPOD 4 AE Vss CLKRO DXO VPOCTLO VPOD 1 Vss AED52 AED56 AED58 AED61 Vss DVpp DVpp VPOD 12 VPOD S C 33 AD ACLKRO VPOD 9 CLKSO VPOCTL2 Vss AED48 AED53 AED57 AED59 AED60 DVpp AED AED32 VPOD
124. REVTEO MCcASPO receive even event 36 AREVTOO receive odd event 37 AREVTO McASPO receive event 38 VP1bEVTYB VP1 Channel B Y event DMA request 39 VP1EVTUB VP1 Channel B Cb event DMA request 40 VP1EVTVB VP1 Channel B Cr event DMA request 41 VP2bEVTYB VP2 Channel B Y event DMA request 42 VP2EVTUB VP2 Channel B Cb event DMA request 43 VP2EVTVB VP2 Channel B Cr event DMA request 44 ICREVTO 1200 receive event 45 ICXEVTO 12 0 transmit event 46 47 2 21 48 GPINT8 event 8 49 GPINT9 GPO event 9 50 GPINT10 GPO event 10 51 GPINT11 GPO event 11 52 GPINT12 GPO event 12 53 GPINT13 GPO event 13 54 GPINT14 GPO event 14 55 GPINT15 GPO event 15 56 VP1bEVTYA VP1 Channel A Y event DMA request 57 VP1EVTUA VP1 Channel A Cb event DMA request 58 VP1EVTVA VP1 Channel A Cr event DMA request 59 VP2EVTYA VP2 Channel A Y event DMA request 6 VP2EVTUA VP2 Channel A Cb event DMA request 61 VP2EVTVA VP2 Channel A Cr event DMA request 62 63 U None 80 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 5 4 2 EDMA Peripheral Register Description s Table 5 4 EDMA Registers C64x HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0800 01A0 FF98 NENNEN Reser
125. RS200L JULY 2002 REVISED JANUARY 2007 EE NJ N NV NV coe VS LOS XZ N 7 NZ N 0 Z N Z Hr 1 Z NZ NZ NO A No LF S VZ N NZ VZ I NZ A ANA ANZA NN AEcLKouT1 N N c Xu NZ NZ AECLKOUT2 2212 Z x 6 4 7 gt mrzeo 0 e 3 8 9 EMIF High Group e r EMIF 9 Low Group 2012 ee O uh Boot and Device pp Configuration Inputs A EMIF Z group consists of AEA 22 3 AED 63 0 ACE 3 0 ABE 7 0 AARE ASDCAS ASADS ASRE AAWE ASDWE ASWE AAOE ASDRAS ASOE ASOES3 ASDCKE and APDT high group consists of AHOLDA when the corresponding HOLD input is high EMIF low group consists of ABUSREQ AHOLDA when the corresponding HOLD input is low Low group consists of XSP CS XSP CLK MDCLK and XSP DO MDIO all of which apply only when PCI EEPROM is enabled with PCI EN 1 and MCBSP2 EN 0 Otherwise the XSP CLK MDCLK and XSP DO MDIO pins are in the Z group For more details on the PCI configuration pins see the Device Configurations section of this data sheet Z group consists of HD 31 0 AD 31 0 and the muxed EMAC output pins CLK MDCLK XSP DO MDIO VPOD 2 CLKXO VP1D 2 CLKX1 VPOD S FSXO VP1D S FSX1 VPOD A DXO VP1D 4 DX1 VPOD 8 CLKRO VP1D S CLKR1 VPOD 7 FSRO VP1
126. RY BLOCK DESCRIPTION HEX ADDRESS RANGE Internal RAM L2 256 0000 0000 0003 FFFF Reserved 768K 0004 0000 000F FFFF Reserved 23M 0010 0000 017F FFFF External Memory Interface A EMIFA Registers 256K 0180 0000 0183 FFFF L2 Registers 256K 0184 0000 0187 FFFF HPI Registers 256K 0188 0000 0188 FFFF McBSP 0 Registers 256K 018C 0000 018F FFFF McBSP 1 Registers 256 0190 0000 0193 FFFF Timer 0 Registers 256K 0194 0000 0197 FFFF Timer 1 Registers 256K 0198 0000 019B FFFF Interrupt Selector Registers 256K 019C 0000 019F FFFF EDMA RAM and EDMA Registers 256K 01A0 0000 0183 FFFF Reserved 512K 01A4 0000 01AB FFFF Timer 2 Registers 256K 01AC 0000 01AF FFFF GPO Registers 256K 4K 0180 0000 0183 EFFF Device Configuration Registers 4K 0183 F000 0183 FFFF 12 0 Data and Control Registers 16K 0184 0000 01B4 3FFF Reserved 32K 01B4 4000 01B4 BFFF McASPO Control Registers 16K 01B4 C000 01B4 FFFF Reserved 192K 01B5 0000 01B7 FFFF Reserved 256K 01B8 0000 01BB FFFF Emulation 256K 01BC 0000 01BF FFFF PCI Registers 256K 01C0 0000 01C3 FFFF VPO Control 16K 01C4 0000 0104 3FFF VP1 Control 16K 01C4 4000 01C4 7FFF VP2 Control 16K 01C4 8000 01C4 BFFF VIC Control 16K 01C4 C000 01C4 FFFF Reserved 192K 01C5 0000 01C7 FFFF EMAC Control 4K 01C8 0000 01C8 OFFF EMAC Wrapper 8K 01C8 1000 01C8 2FFF EWRAP Registers 2K 01C8 3000 01C8 37FF MDIO Control Registers 2K 01C8 38
127. S EMIFA synchronous memory output enable for for glueless FIFO ASOE R22 O Z IPU interface AARDY L22 IPU Asynchronous memory ready input EMIFA 64 bit ADDRESS AEA22 U23 21 V24 AEA20 25 EMIFA external address doubleword address AEA19 V26 EMIFA address numbering for the DM642 device starts with AEAS to maintain AEA18 V23 signal name compatibility with other C64x devices e g C6414 C6415 and C6416 see the 64 bit EMIF addressing scheme in the TMS320C6000 DSP AEA17 U24 External Memory Interface EMIF Reference Guide literature number AEA16 U25 SPRU266 AEA15 U26 Boot Configuration AEA14 T24 e Controls initialization of DSP modes at reset via pullup pulldown resistors Boot mode AEA 22 21 AEA13 T25 O Z 00 No boot default mode AEA12 R23 01 HPI PCI boot based on PCI EN pin 10 Reserved BERT Bs 11 EMIFA boot AEA10 P23 EMIF clock select AEA 20 19 AEA9 P24 Clock mode select for EMIFA AECLKIN SEL 1 0 00 AECLKIN default mode AEA8 P26 01 CPU 4 Clock Rate AEA7 N23 10 CPU 6 Clock Rate AEAG N24 11 Reserved 5 N26 For more details see the Device Configurations section of this data sheet AEA4 M23 AEA3 M24 34 Device Overview Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued
128. SOLETE GNZ 548 TBD Call TI Call TI TMS320DM642ZDK500 ACTIVE FCBGA ZDK 548 TBD Call TI Call TI TMS320DM642ZDK600 ACTIVE FCBGA ZDK 548 TBD Call TI Call TI TMS320DM642ZNZ500 ACTIVE FCBGA ZNZ 548 TBD Call TI Call TI The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check Addendum Page 1 X3 Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 2 Feb 2008 http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free p
129. TL 1 0 1i 11 10 100 HRW i 11 v d 11 10 10 lt mum ww HHWIL 3 4 y HSTROBE e UU E MN 1d f j MNA gt F 18 18 RE rem HCS N 13 12 13 HD 15 0 input EE half word 2nd half word 6 gt k 14 HRDY eee Se ee A For correct operation strobe the HAS signal only once per HSTROBE active cycle B HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS Figure 5 41 HPI16 Write Timing HAS Used 126 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com HAS HCNTL 1 0 HR W HSTROBE TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 HS 1 4 77 HD 31 0 output HRDY e 8 0 A HSTROBE refers to the following logical operation HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS Figure 5 42 HPI32 Read Timing HAS Not Used Tied High HAS HCNTL 1 0 mas I i A HR W HSTROBE B HS No HD 31 0 output HRDY 6 k L8 X m MM M o A For correct operation strobe the HAS signal only once per HSTROBE active cycle B HSTROBE refers t
130. TXPAUSEFRAMES Pause Transmit Frames Register 01C8 0244 TXDEFERRED Deferred Transmit Frames Register 01C8 0248 TXCOLLISION Collision Register 01C8 024C TXSINGLECOLL Single Collision Transmit Frames Register 01C8 0250 TXMULTICOLL Multiple Collision Transmit Frames Register 01C8 0254 TXEXCESSIVECOLL Excessive Collisions Register 01C8 0258 TXLATECOLL Late Collisions Register 01C8 025C TXUNDERRUN Transmit Underrun Register 01C8 0260 TXCARRIERSLOSS Transmit Carrier Sense Errors Register 01C8 0264 TXOCTETS Transmit Octet Frames Register 01C8 0268 FRAME64 Transmit and Receive 64 Octet Frames Register 01C8 026C FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register 01C8 0270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register 01C8 0274 FRAME256T51 1 Transmit and Receive 256 to 511 Octet Frames Register 01C8 0278 FRAMES512T1023 Transmit and Receive 512 to 1023 Octet Frames Register 01C8 027C FRAME1024TUP Transmit and Receive 1024 or Above Octet Frames Register 01C8 0280 NETOCTETS Network Octet Frames Register 01C8 0284 RXSOFOVERRUNS Receive Start of Frame Overruns Register 01C8 0288 RXMOFOVERRUNS Receive Middle of Frame Overruns Register 01C8 028C RXDMAOVERRUNS Receive DMA Overruns Register 01C8 0290 01C8 05FF Reserved Table 5 72 EMAC Wrapper HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 1000 01C8 1FFF EMAC Control Module Descriptor Memory 01C8 2000 01C8 2FFF Reser
131. Transition time VPxCLKOUTx 1 8 ns 5 LatvKIH VKOH Delay time VPXCLKINx high to VPxCLKOUTx high 9 1 1 57 ns 6 ta VKIL VKOL Delay time VPXCLKINx low to VPxCLKOUTx low 9 1 1 57 ns 7 la VKIH VKOL Delay time VPxCLKINx high to VPXCLKOUTx low 1 1 5 7 ns 8 la VKIL VKOH Delay time VPxCLKINx low to high 1 1 5 7 ns 9 la VKIH VPOUTV Delay time VPXCLKINx high to VPxOUT valid 4 ns 10 la VKIH VPOUTIV Delay time VPXCLKINx high to VPxOUT invalid 9 1 7 ns 11 tatvkon vPoUTV Delay time VPXCLKOUTx high to VPxOUT valid 1 4 4 3 ns 12 tawvkon vPouriv Delay time VPXCLKOUTXx high to VPxOUT invalid 4 0 2 ns 1 V the video input clock VPxCLKINx period in ns 2 VHis the high period of V video input clock period in ns and VL is the low period of V video input clock period in ns 3 Assuming non inverted VPXCLKOUTx signal 4 VPxOUT consists of VPxCTLx and VPxD 19 0 c e E 1 py ac kl 6 VPxCLKOUTx VCLK2P 0 7 4 k 4 VPxCLKOUTx ee ee 8 Inverted ee ye VCLK2P 1 I t 34 12 VPxCTLx V 4 9 10 PxD 19 0 0000000000000 T Outputs VPxCTLx Input E DEE DEE AAA Figure 5 60 Video Port Display Data Output Timing and Control Input Output Timing With Respect to VPxCLKINx and VPXCLKOUTx 148 DM642 Peripheral Information and
132. V x s AEA 22 14 X Bank X AEA 12 3 KH AEA33 0 AED 63 0 El k 12 12 AAOE ASDRAS ASOE A 42 400 AARE ASDCAS ASADS ASRE 11 lt 11 AAWE ASDWEASWE A and ASDRAS respectively during SDRAM accesses Figure 5 26 SDRAM DEAC Command for EMIFA REFR AECDROUTR N A r Tel 1 ACEx 577 sss AEA 22 14 12 3 ER AEA13 ue ro iu p AED 63 0 12 12 AAOE ASDRAS ASOE 5666 8 8 AARE ASDCAS ASADS ASRE i fe i E E AAWE ASDWE ASWE A AARE ASDCAS ASADS ASRE AAWE ASDWE ASWE and AAOE ASDRAS ASOE operate as ASDCAS ASDWE and ASDRAS respectively during SDRAM accesses Figure 5 27 SDRAM REFR Command for EMIFA 106 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 MRS AELKOUX ZA m T 7 1 1 N _ OO k 4 k 5 AEA 2 3 MHRSvadue X VPVMVM jj AED 63 0 r s 12 12 AAOE ASDRAS ASOE 4 ULL eege k 8 k 8 AARE ASDCAS ASADS ASREA N 1 7 11 lt 11 AAWE ASDWE ASWEU
133. VP1D 19J AXRO 7 9 AB12 VP1D 18 AXRO 6 9 AB11 VP1D 17J AXRO 5 AC11 VP1D 16 AXRO 4 9 AD11 oz VP1 input output data pins 19 12 l O Z McASPO TX RX data pins 7 0 VP1D 15 AXRO 3 AE11 0 2 default VP1D 14 J AXRO 2 9 AC10 VP1D 13J AXRO 1 9 AD10 VP1D 12 AXRO 0 9 AC9 RESERVED FOR TEST Reserved This pin must be connected directly to CVpp for proper device RSV07 id operation Reserved This pin must be connected directly to DVpp for proper device 8 ES A operation RSV05 E14 1 IPD RSV06 W7 A RSV00 AAS a AL Reserved leave unconnected do not connect to power or ground If the signal RSV01 AB3 Ir must be routed out from the device the internal pull up down resistance should 15 02 ACH 0 7 not be relied upon and an external pull up down should be used RSVO03 AD3 O Z RSV04 AF3 o IPU 42 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU DESCRIPTION SUPPLY VOLTAGE PINS DVpp A2 A25 B1 B2 814 825 826 3 24 04 D23 E5 7 8 E10 E17 E19 E20 E22 F9 F12 F15
134. Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 76 Timing Requirements for EMAC MII Receive 10 100 Mbit s see Figure 5 65 500 600 720 UNIT MIN MAX tsu MRXD MRCLKH Setup time receive selected signals valid before MRCLK high 8 ns 2 th MRCLKH MRXD Hold time receive selected signals valid after MRCLK high 8 ns 1 Receive selected signals include MRXD3 MRXDO MRXDV and MRXER MRCLK Input dE MRXD3 MRXDO MRXER inputs RAK ARK REX X RK Figure 5 65 EMAC Receive Interface Timing Table 5 77 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10 100 Mbit s see Figure 5 66 500 600 720 UNIT MN MAX MAX 1 a MTCLKH MTXD Delay time MTCLK high to transmit selected signals valid 5 25 ns 1 Transmit selected signals include MTXD3 MTXDO and MTXEN 1 MTCLK Input CH MTXD3 MTXDO YY MTXEN Outputs EE ROKK Figure 5 66 EMAC Transmit Interface Timing Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 157 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 5 17 Management Data Input Output MDIO www ti com The MDIO module controls PHY configuration
135. X Delay time ACLKR X transmit edge to AFSX R output valid AGLKR X int a 5 ns ACLKR X ext 0 10 ns 14 taciocAxnv Delay time ACLKX transmit edge to AXR output valid BEIM 5 ns ACLKX ext 0 10 ns 15 t Disable time AXR high impedance following last data bit from ACLKR X int 10 ns 2 ACLKR X transmit edge ACLKRIX ext 1 ACLKX internal ACLKXCTL CLKXM 1 PDIR ACLKX 1 ACLKX external input ACLKXCTL CLKXM 0 PDIR ACLKX 0 ACLKX external output ACLKXCTL CLKXM 0 PDIR ACLKX 1 ACLKR internal ACLKRCTL CLKRM 1 PDIR ACLKR 1 ACLKR external input ACLKRCTL CLKRM 0 PDIR ACLKR 0 ACLKR external output ACLKRCTL CLKRM 0 PDIR ACLKR 1 Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 115 TMS320DM642 43 Texa Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 lle 2 19 le al ld AHCLKRA Fating Edge LUTTER S AHCLKRIX Rising Edge Polarity 164 she a acu oue cuo o A JAVVVVAVNVAV AVUAVJVAA AA AAA AVVNA 6 E mr 5 AFSR X Bit Width 0 Bit Delay AFSR X Bit Width 1 Bit Delay E x Ea a Bit Width 2 Bit Delay E Ioe u opw n b AFSR X Slot Width 0 Bit Delay NEN uxo RNC _
136. a input output 0 2 or McASPO control pins 1 0 2 C 3 default and Video port 0 data input output 1 0 2 or McBSPO data ER BUS input output 0 2 default VPOD 1 1 AB15 C By default standalone VPO data input output pins have no function enabled VPOD 10 AC15 2 upon reset To configure these pins see the Device Configuration section of this VPOD 9 AD15 data sheet VPOD 8 CLKRO 9 AE15 For more details on the McBSPO pin functions or the McASPO control pin functions see 5 0 or McASPO control sections of this table and the Device 3 VPODI VFSRO AB16 Configurations section of this data sheet VPOD 6 DRO AC16 VPOD B CLKSO 9 AD16 VP0D 4 DX0 9 AE16 VPOD 3J FSX0 9 AF16 VPOD 2V CLKXO 9 AF17 VPOD 1 AE18 VPOD 0 AF18 VPOCLK1 AF12 VO Z IPD VPO clock 1 2 VPOCLKO AF14 o IPD VPO clock 0 I VPOCTL2 AD17 VPO control 2 I O Z VPOCTL1 AC17 V O Z D VPO control 1 I O Z VPOCTLO AE17 VPOcontrol 0 1 2 TIMER 2 Po No external pins The timer 2 peripheral pins are not pinned out as external pins TIMER 1 Timer 1 output O Z Boot Configuration Device endian mode LENDIAN I Controls initialization of DSP modes at reset via pullup pulldown resistors IP e Device Endian mode TOUT1 B5 O Z U 0 Big Endlan 1 Little Endian default For more details on LENDIAN see the Device Configurations section of this data sheet TINP1 A5 PD Timer 1 or general purpose input TIMER 0 Timer 0 out
137. abled PCI EN pin 0 this pin must not be pulled up EMIFA 64 bit CONTROL SIGNALS COMMON ALL TYPES OF MEMORY 126 O Z IPU ACEZ K23 0 7 IPU EMIFA memory space enables K24 OZ IPU e Enabled by bits 28 through 31 of the word address AED Only one pin is asserted during any external data access EO K25 O Z IPU ABE7 T22 O Z IPU ABE6 T23 O Z IPU ABE5 R25 O Z IPU EMIFA byte enable control ABE4 R26 O Z IPU e Decoded from the low order address bits The number of address bits or byte enables used depends on the width of external memory ABES M25 0 2 Byte write enables for most types of memory 2 26 0 2 IPU e Can be directly connected to SDRAM read and write mask signal SDQM ABE1 L23 O Z IPU ABEO L24 O Z IPU EMIFA peripheral data transfer allows direct transfer between external APDT M22 O Z IPU peripherals EMIFA 64 bit BUS ARBITRATION AHOLDA N22 9 IPU EMIFA hold request acknowledge to the host AHOLD W24 1 IPU EMIFA hold request from the host ABUSREQ P22 IPU EMIFA bus request output Submit Documentation Feedback Device Overview 33 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL wo TYPE DESCRIPTION EM
138. al Blanking Start Register 01C4 021C 01C4 421C 01C4 821C VD VBLKE2x Video Display Field 2 Vertical Blanking End Register 01C4 0220 01C4 4220 01C4 8220 VD IMGOFF1x Video Display Field 1 Image Offset Register 01C4 0224 01C4 4224 01C4 8224 VD IMGSZ1x Video Display Field 1 Image Size Register 01C4 0228 01C4 4228 01C4 8228 VD IMGOFF2x Video Display Field 2 Image Offset Register 01C4 022C 01C4 422C 01C4 822C VD IMGSZ2x Video Display Field 2 Image Size Register 01C4 0230 01C4 4230 01C4 8230 VD FLDT1x Video Display Field 1 Timing Register 01C4 0234 01C4 4234 01C4 8234 VD FLDT2x Video Display Field 2 Timing Register 01C4 0238 01C4 4238 01C4 8238 VD THRLDx Video Display Threshold Register 01C4 023C 01C4 423C 01C4 823C VD HSYNOCx Video Display Horizontal Synchronization Register 01C4 0240 01C4 4240 01C4 8240 VD VSYNS1x Video Display Field 1 Vertical Synchronization Start Register 01C4 0244 01C4 4244 01C4 8244 VD VSYNE1x Video Display Field 1 Vertical Synchronization End Register 01C4 0248 01C4 4248 01C4 8248 VD VSYNS2x Video Display Field 2 Vertical Synchronization Start Register 01C4 024C 01C4 424C 01C4 824C VD VSYNE2x Video Display Field 2 Vertical Synchronization End Register Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 143 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 61 Vi
139. alid before CLKX high 12 2 12 ns 5 th CKXH DRV Hold time DR valid after CLKX high 4 5 24 ons 2 1 CPU clock frequency in ns For example when running parts at 720 MHz use 1 39 ns For all SPI Slave modes CLKG is programmed as 1 4 of the CPU clock by setting CLKSM CLKGDV 1 Table 5 58 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave CLKSTP 10b CLKXP 1 see Figure 5 55 500 600 PARAMETER 720 UNIT MASTER SLAVE MIN MAX MAX MIN MAX 1 th CKXH FXL Hold time FSX low after CLKX high T 2 T 3 ns 2 Lla FXL CKXL Delay time FSX low to CLKX low 9 H 25 H 3 ns 3 la CKXL DXV Delay time CLKX low to DX valid 2 4 12P 3 20P 17 ns Disable time DX high impedance following last data bit 3 e tdis CKXH DXHZ from CLKX high is He ns Disable time DX high impedance following last data bit 3 7 tdis FXH DXHZ from FSX high g p g 4P 3 12P 17 ns la FXL DXV Delay time FSX low to DX valid 8 2 16 17 ns 140 P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns For all SPI Slave modes CLKG is programmed as 1 4 of the CPU clock by setting CLKSM CLKGDV 1 S Sample rate generator input clock 4P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock clks if CLKSM 0 clks CLKS period T
140. and MAC EN pins are latched at reset They determine specific peripheral selection summarized in Table 3 1 For further clarification of the HPI vs EMAC configuration see Table 3 2 Table 3 1 PCI EN HD5 MAC EN Peripheral Selection HPI 15 9 PCI EMAC and PERIPHERAL SELECTION PERIPHERALS SELECTED D Tele Meta ege np o 00 Y Hi Z Disabled N A Disabled np o o 1 Hi Z Disabled N A Y Y 0 o 1 00 d Y Disabled N A Disabled np o 1 1 Disabled Disabled N A Enabled 1 1 D Disabled via External Disabled Disabled EEPROM 1 x x Disabled Tu Disabled Disabled e Ifthe PCI is disabled PCI EN 0 the HPI peripheral is enabled and based on the HD5 and MAC pin configuration at reset 16 mode or and MDIO can be selected When the PCI is disabled PCI EN 0 the GPO 15 9 pins can also be programmed as GPIO provided the GPxEN and GPxDIR bits are properly configured This means all multiplexed HPI PCI pins function as HPI and all standalone PCI pins PCBEO and CS are tied off Hi Z Also the multiplexed GPO PCI pins can be used as GPIO with the proper software configuration of the GPIO enable and direction registers for more details see Table 3 8 e Ifthe PCI is enabled PCI EN 1 the HPI peripheral is disabled This means al
141. and status monitoring 5 17 1 Device Specific Information The management data input output MDIO module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system The management data input output MDIO module implements the 802 3 serial management interface to interrogate and control Ethernet PHY s using a shared two wire bus Host software uses the MDIO module to configure the auto negotiation parameters of each PHY attached to the retrieve the negotiation results and configure required parameters in the EMAC module for correct operation The module is designed to allow almost transparent operation of the MDIO interface with very little maintenance from the core processor TMS320C6000 DSP Ethernet Media Access Controller EMAC Management Data Input Output MDIO Module Reference Guide literature number SPRU628 describes the DM642 MDIO peripheral in detail Some of the features documented in this peripheral reference guide are not supported on the DM642 at this time The DM642 only supports one EMAC module For a list of supported registers and register fields see Table 5 78 MDIO Registers in this data manual 5 17 2 Peripheral Register Description s Table 5 78 MDIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 3800 VERSION MDIO Version Register 01C8 3804 CONTROL MDIO Control Register 01C8 3808 ALIVE MDIO PHY Alive I
142. annel B supports BT 656 8 10 bit RAW Video 8 10 bit capture modes and can display synchronized RAW Video data with Channel A C The same STCLK signal is used for all three video ports VP1 and VP2 Figure 2 14 Video Port 2 Peripheral Signals 28 Device Overview Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Transmit Receive Data Pins Transmit Receive Data Pins VP1D 12 AXRO 0 4 8 Serial Ports gt VP1D 16J AXR0 4 VP1D 13JAXRO0 1 lt Flexible VP1D 17 AXRO 5 VP1D 14yAXRO 2 lt Partitioning VP1D 18 AXRO 6 VP1D 15 AXRO 3 lt Tx Rx OFF VP1D 19 AXRO 7 Receive Bit Clock Transmit Bit Clock VPOD 12 ACLKRO Receive Clock pd VPOD 17 ACLKXO VPOD 14JAHCLKRO Generator VPOD 19 AHCLKXO Generator Receive Master Clock Transmit Master Clock Transmit Check Circuit Receive Clock Check Circuit VPOD 13 AFSRO Frame VPOD 18 AFSXO Receive Frame Sync or ync Syne Transmit Frame Sync or Left Right Clock Left Right Clock Auto Mute VPOD 16JAMUTEO Error Detect 4 Logic lt VPOD 15J AMUTEINO McASPO Multichannel Audio Serial Port 0 NOTES On multiplexed pins bolded text denotes the active function of the pin for that particular peripheral module Bolded and Italicized text within parentheses denotes the function o
143. arameters for Event 12 6 words 01A0 0138 01A0 014F Parameters for Event 13 6 words 01A0 0150 01A0 0167 01A0 0168 01A0 017F Parameters for Event 15 6 words 01A0 0180 01A0 0197 Parameters for Event 16 6 words 01A0 0198 01 0 01AF KS JH JH Je JS JS Parameters for Event 14 6 words Parameters for Event 17 6 words 01A0 05D0 01A0 05E7 Parameters for Event 62 6 words 01A0 05E8 01A0 05FF Parameters for Event 63 6 words 01A0 0600 01A0 0617 Reload link parameters for Event 0 6 words Reload Link Parameters for other Event 0 15 01A0 0618 01A0 062F Reload link parameters for Event 1 6 words 01A0 0760 0180 07F7 Reload link parameters for Event 20 6 words 01A0 07F8 01A0 080F Reload link parameters for Event 21 6 words 01A0 0810 01A0 0827 Reload link parameters for Event 22 6 words 01A0 13C8 01A0 13DF Reload link parameters for Event 147 6 words 01A0 13E0 0180 13F7 Reload link parameters for Event 148 6 words 01A0 13F8 01A0 13FF Scratch pad area 2 words 01A0 1400 01A3 FFFF Reserved 1 The DM642 device has 213 EDMA parameters total 64 Event Reload channels and 149 Reload only parameter sets six 6 words each that can be used to reload link EDMA transfers 82 DM642 Peripheral Information and Elect
144. ary through the host interface including internal configuration registers such as those that control the EMIF or other peripherals For the DM642 device the HPI peripheral is used for host boot if PCI_EN 0 and the PCI peripheral is used if PCI_EN 1 Once the host is finished with all necessary initialization it must set the DSPINT bit in the HPIC register to complete the boot process This transition causes the boot configuration logic to bring the CPU out of the stalled state The CPU then begins execution from address 0 The DSPINT condition is not latched by the CPU because it occurs while the CPU is still internally stalled Also DSPINT brings the CPU out of the stalled state only if the host boot process is selected All memory may be written to and read by the host This allows for the host to verify what it sends to the DSP if required After the CPU is out of the stalled state the CPU needs to clear the DSPINT otherwise no more DSPINTs can be received EMIF boot using default ROM timings Upon the release of RESET the 1K Byte ROM code located in the beginning of is copied to address 0 by the EDMA using the default ROM timings while the CPU is internally stalled The data should be stored in the endian format that the system is using In this case the EMIF automatically assembles consecutive 8 bit bytes to form the 32 bit instruction words to be copied The transfer is automatically done by the EDMA as a single frame
145. ata Submit Documentation Feedback Device Overview 41 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL IPD TYPE 2 DESCRIPTION NAME NO IPU MULTICHANNEL AUDIO SERIAL PORT 0 McASPO CONTROL VPOD 19 AHCLKX0 AC12 0 7 EM VPO input output data 19 pin 2 or McASPO transmit high frequency master clock I O Z VPO input output data 18 pin 2 or McASPO transmit frame sync or left right 3 VPOD 18 AFSXO AD12 2 clock LRCLK l O Z VPOD 17 ACLKXO AB13 VO Z IPD VPO input output data 17 pin 0 2 or McASPO transmit bit clock 2 VPOD 16 AMUTEO 9 AC13 O Z PD VPO input output data 16 1 2 or McASPO mute output 0 2 VPOD 15 3 AMUTEINO AD1 VO Z ES VPO input output data 15 pin 0 2 or McASPO mute input 1 0 2 VPOD 14J AHCLKROO 14 0 7 NN VPO input output data 14 pin 0 2 or McASPO receive high frequency master clock 1 0 2 3 3 C VPO input output data 13 0 2 or McASPO receive frame sync or left right 3 VPOD 13 AFSRO AC14 VO Z ES clock LRCLK I O 2 VPOD 12 ACLKRO AD14 VO Z IPD VPO input output data 12 pin 0 2 or McASPO receive bit clock 1 0 2 MULTICHANNEL AUDIO SERIAL PORT 0 McASPO DATA
146. ation and Version Register 01C8 0004 TXCONTROL Transmit Control Register 01C8 0008 TXTEARDOWN Transmit Teardown Register 01C8 000C Po Reserved 01C8 0010 RXIDVER Receive Identification and Version Register 01C8 0014 RXCONTROL Receive Control Register 200170200 EE writes of 0 0108 001C 01C8 00FF 2 J Reserved Receive Multicast Broadcast Promiscuous Channel Enable Register 01C8 0100 RXMBPENABLE The RXQOSEN field is reserved and only supports writes of 0 The PROMCH BROADCH and MUCTCH bit fields only support writes of 0 01C8 0104 RXUNICASTSET Si rie bpm support writes of 0 01C8 0108 RXUNICASTCLEAR 111 Se 2 ger uem support writes of 0 01C8 010C RXMAXLEN Receive Maximum Length Register 01C8 0110 RXBUFFEROFFSET Receive Buffer Offset Register 01C8 0114 RXFILTERLOWTHRESH Receive Filter Low Priority Packets Threshold Register 01C8 0118 01C8 011F Reserved 01C8 0120 RXOFLOWTHRESH Receive Channel 0 Flow Control Threshold Register 152 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 70 Ethernet MAC EMAC Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 0108 0124 RX1FLOWTHRESH 01C8 0128 RX2FLOWTHRESH
147. ay time FSX low to DX valid 8P 1 8 16P 17 ns 138 P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns For all SPI Slave modes CLKG is programmed as 1 4 of the CPU clock by setting CLKSM CLKGDV 1 S Sample rate generator input clock 4P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period T CLKX period 1 CLKGDV S H CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd or zero FSRP FSXP 1 As a SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX CLKX VLA N N N i i LS LS V Figure 5 53 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 0 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor
148. bit and TSI 8 bit capture modes B Channel B supports BT 656 8 10 bit RAW Video 8 10 bit capture modes and can display synchronized RAW Video data with Channel A C The same STCLK signal is used for all three video ports VP0 VP1 and VP2 Figure 2 13 Video Port 1 Peripheral Signals Submit Documentation Feedback Device Overview 27 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 STCLK O des VP2CLKO VP2CLK1 4 E Timing and VP2CTLO Control Logic VP2CTL1 VP2CTL2 lt gt VP2D 0 4 gt lt gt VP2D 10 VP2D 1 4 E 4 p VP2D 11 VP2DI 2 4 4 p gt VP2D 12 VP2D 3 4 lt gt VP2D 13 Displ VP2D 4 lt s lt p VP2D 14 20 5 4 gt 2560 Bytes 4 p VP2D 15 VP2D 6 4 gt VP2D 16 VP2D 7 4 gt VP2D 17 VP2D 8 4 lt p VP2D 18 VP2D 9 lt gt 4 gt VP2D 19 Channel A A 4 gt 4 Ch IB 4 annel B uses only EE 4 p the VP2D 19 10 Greg 4 bidirectional pins lt lt gt Channel B Video Port 2 VP2 A Channel A supports BT 656 8 10 bit Y C Video 16 20 bit RAW Video 16 20 bit display modes and BT 656 8 10 bit Y C Video 16 20 bit RAW Video 16 20 bit and TSI 8 bit capture modes B Ch
149. block transfer from the ROM to address 0 After completion of the block transfer the CPU is released from the stalled state and starts running from address 0 No boot With no boot the CPU begins direct execution from the memory located at address 0 Note operation is undefined if invalid code is located at address 0 2 5 Pin Assignments 16 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 2 5 1 Pin Map TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Figure 2 3 through Figure 2 6 show the DM642 pin assignments in four quadrants A B C and D 2 3 4 5 6 7 8 9 10 11 12 13 AF Vss DVpp RSV VPICTLO VP1D 0 VPi1D Vss VP1CLKO Vss VP1CLK1 Vss VPOCLK1 Vss AE DV DV V FID GEN V VP1D 10 V DV DD DD Ss CLKMODE1 CLKX1 CLKS1 ES 10 55 AXRO 3 ss DD DAG VP1D Sy VP1D 6y 10 13 10 16 VPOD 18 5 AD 2 Vss RSV Vss SEI FSX1 D I CLKR1 VP1D01 AMUTEINO AC rele IKN VPIDUY VP1D 12 VP1D 14y VP1D 17 VPOD 19y VPOD 16y E u ss 5 55 DX FSR1 91 AXROD AXRO 2 5 AHCLKXO AMUTEO V
150. cBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP clock CLKX Figure 5 56 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 1 Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications FSRP FSXP 1 As a SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master 141 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 14 Video Port Each Video Port is capable of sending and receiving digital video data The Video Ports are also capable of capturing displaying RAW data The Video Port peripherals follow video standards such as BT 656 and SMPTE296 5 14 1 Video Port Device Specific Information The TMS320DM642 device has three video port peripherals The video port peripheral can operate as a video capture port video display port or as a transport stream interface TSI capture port The port consists of two channels A and B A 5120 byte capture display buffer is splittable between the two channels The entire port both channels is always configured for either video capture or display only Separate data pipelines control the parsing and formatting of video capture or display data for each of the
151. ctrical Data Timing Table 5 84 Timing Requirements for Timer Inputs see Figure 5 69 500 600 720 UNIT MN MAX MAX 1 tw TINPH Pulse duration TINP high Hs 2 tw TINPL Pulse duration TINP low 8 ons 1 P 1t CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns Table 5 85 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs see Figure 5 69 500 600 720 UNIT MN MAX 3 tw TOUTH Pulse duration TOUT high 8 3 5 lw TOUTL Pulse duration TOUT low 8P 3 ons 1 P 1t CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns 2 4 1 TINPx MED A 2 4 w 3 TOUTx LLLA Figure 5 69 Timer Timing Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 161 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 19 General Purpose Input Output GPIO The GPIO peripheral provides dedicated general purpose pins that can be configured as either inputs or outputs When configured as an output you can write to an internal register to control the state driven on the output pin When configured as an input you can detect the
152. cumentation Feedback S Sample rate generator input clock 4P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock clks if CLKSM 0 P clks CLKS period T CLKX period 1 CLKGDV S CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero FSRP FSXP 1 As a SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX CLKX N XJ X j a Figure 5 54 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 0 DM642 Peripheral Information and Electrical Specifications 139 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 www ti com Table 5 57 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 10b CLKXP 147 see Figure 5 55 500 600 SC UNIT MASTER SLAVE MIN MAX MIN MAX tsu DRV CKXH Setup time DR v
153. d Electrical Specifications 113 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 31 McASPO Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B4 C28C RBUF3 Receive Buffer for Serializer 3 01B4 C290 RBUF4 Receive Buffer for Serializer 4 01B4 C294 RBUF5 Receive Buffer for Serializer 5 01B4 C298 RBUF6 Receive Buffer for Serializer 6 01B4 C29C RBUF7 Receive Buffer for Serializer 7 0184 C2A0 01B4 FFFF e Reserved Table 5 32 McASPO Data Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Used when RSEL or XSEL C 3C McASPx receive buffers or McASPx transmit buffers via bits 0 these bits are located 0 SOUP EREE ees the Peripheral Data Bus in the RFMT or XFMT registers respectively 5 9 3 MCcASPO Electrical Data Timing 5 9 3 1 Multichannel Audio Serial Port McASP Timing Table 5 33 Timing Requirements for McASP see Figure 5 33 and Figure 5 34 500 600 u 720 UNIT MIN MAN MAX 1 c AHCKRX Cycle time AHCLKR X 20 ns 2 tw AHCKRX Pulse duration AHCLKR X high or low 10 ns 3 te CKRX Cycle time ACLKR X ACLKR X ext 33 ns 4 lw CKRX Pulse duration ACLKR X high or low ACLKR X ext 16 5 ns ACLKR X int 5 ns 5 tsu FRX CKRX Setup time A
154. d RESET need to be asserted upon power up only RESET needs to be released for the DSP to boot properly TRST may be asserted indefinitely for normal operation keeping the JTAG port interface and DSP s emulation logic in the reset state TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP s boundary scan functionality RESET must be released only in order for boundary scan JTAG to read the variant field of IDCODE correctly Other boundary scan instructions work correctly independent of current state of RESET For maximum reliability the TMS320DM642 DSP includes an internal pulldown IPD on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP s internal emulation logic will always be properly initialized JTAG controllers from Texas Instruments actively drive TRST high However some third party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST When using this type of JTAG controller assert TRST to intialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations Following the release of RESET the low to high transition of TRST must be seen to latch the state of EMU1 and EMUO The EMU 1 0 pins configure the device for either Boundary Scan mode or Emulation mode For more detailed information see the terminal functions section of th
155. deo Port 0 1 and 2 VPO VP1 and VP2 Control Registers continued HEX ADDRESS RANGE VPO VP1 ACRONYM DESCRIPTION 01C4 0250 01C4 4250 01C4 8250 VD RELOADx Video Display Counter Reload Register 01C4 0254 01C4 4254 01C4 8254 VD DISPEVTx Video Display Display Event Register 01C4 0258 01C4 4258 01C4 8258 VD CLIPx Video Display Clipping Register 01C4 025C 01C4 425C 01C4 825C VD DEFVALx Video Display Default Display Value Register 01C4 0260 01C4 4260 01C4 8260 VD VINTx Video Display Vertical Interrupt Register 01C4 0264 01C4 4264 01C4 8264 VD FBITx Video Display Field Bit Register 01C4 0268 01C4 4268 01C4 8268 VD VBIT1x Video Display Field 1 Vertical Blanking Bit Register 01C4 026C 01C4 426C 01C4 826C VD VBIT2x Video Display Field 2Vertical Blanking Bit Register 7400 000 7800 0000 7 00 0000 Y RSCA Y FIFO Source Register A 7400 0008 7800 0008 7 00 0008 CB SRCA CB FIFO Source Register A 7400 0010 7800 0010 7 00 0010 CR SRCA CR FIFO Source Register A 7400 0020 7800 0020 7 00 0020 Y DSTA Y FIFO Destination Register A 7400 0028 7800 0028 7 00 0028 CB DST CB FIFO Destination Register 7400 0030 7800 0030 7 00 0030 CR DST CR FIFO Destination Register 7600 0000 7800 0000 7 00 0000 Y SRCB Y FIFO Source Register B 7600 0008 7 00 0008 7 00 0008 CB SRCB CB FIFO Source Register b 7600 0010 7A00 0010 7 00 0010 CR SRCB CR FIFO Source Register B 7600 0020 7400 0020 7 00 0020 Y DSTB Y FIFO D
156. ducts and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by as military grade or enhanced plastic Only products designated by as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Auto
157. e Temperature Range Unless Otherwise Noted 42 Recommended Operating Conditions 4 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Unless Otherwise Noted Submit Documentation Feedback TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Contents 5 DM642 Peripheral Information and Electrical 1 Specifications sorore tror e 73 i 5 1 Parameter Information 13 2 5 2 Recommended Clock and Control Signal Transition 3 ENEE zb 4 5 3 Power 75 6 5 4 Enhanced Direct Memory Access pi eg sanaaa 79 s 55 Interrupts 83 i 5 6 EE 85 42 bur Glock PEL ET 88 16 5 8 External Memory Interface EMIF 94 16 5 9 Multichannel Audio Serial Port McASPO 50 Peripheral ve ENKER KEEN KEES nnn 110 54 5 10 Inter Integrated Circuit I2C 118 54 5 11 Host Port Interface 1 123 56 5 12 Peripheral Component Interconnect PCI 129 59 5 13 Multichannel Buffered Serial Port McBSP 133 61 5 14 Video Port 142 63 5 15 VCXO Interpolated Control VIC 150 65 5 16 Ethernet Media Access Controller
158. e version of the GDK and GNZ packages respectively with Pb free balls For more detailed information see the Mechanical Data section of this document For actual device part numbers P Ns and ordering information see the TI website www ti com Figure 2 16 TMS320DM64x DSP Device Nomenclature Including the TMS320DM642 Device 2 6 2 2 Documentation Support 52 Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development The types of documentation available include data sheets such as this document with design specifications complete user s reference guides for all devices and tools technical briefs development support tools on line help and hardware and software applications The following is a brief descriptive list of support documentation specific to the 600010 DSP devices TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 describes the C6000 DSP CPU core architecture instruction set pipeline and associated interrupts The TMS320C6000 DSP Peripherals Overview Reference Guide literature number SPRU190 provides an overview and briefly describes the functionality of the peripherals available on the 60007 DSP platform of devices This document also includes a table listing the peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated peripheral docume
159. eam format register 0184 06 AFSRCTL Receive frame sync control register 0184 C070 ACLKRCTL Receive clock control register 0184 C074 AHCLKRCTL High frequency receive clock control register 0184 C078 RTDM Receive TDM slot 0 31 register 01B4 C07C RINTCTL Receiver interrupt control register 01B4 C080 RSTAT Status register Receiver 0184 C084 RSLOT Current receive TDM slot register 0184 C088 RCLKCHK Receiver clock check control register 0184 C08C 0184 09 Reserved Alias of GBLCTL containing only Transmitter Reset bits allows transmit to be reset 01B4 C0A0 XGBLGTL independently from receive 01B4 C0A4 XMASK Transmit format UNIT bit mask register 01B4 C0A8 XFMT Transmit bit stream format register 01B4 C0AC AFSXCTL Transmit frame sync control register 01B4 C0B0 ACLKXCTL Transmit clock control register 01B4 C0B4 AHCLKXCTL High frequency Transmit clock control register 01B4 C0B8 XTDM Transmit TDM slot 0 31 register 01B4 C0BG XINTCTL Transmit interrupt control register 01B4 C0C0 XSTAT Status register Transmitter 01B4 C0C4 XSLOT Current transmit TDM slot 01B4 C0C8 XCLKCHK Transmit clock check control register 112 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com Table 5 31 McASPO Control Registers continued TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY
160. eedback d Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 5 10 3 12 Electrical Data Timing 5 10 3 1 Inter Integrated Circuits I2C Timing Table 5 36 Timing Requirements for I2C Timings see Figure 5 36 500 600 720 STANDARD oer wen MIN MAX MN MAX MAX 1 Cycle time SCL 10 2 5 us 2 Ee SCL high before SDA low for a repeated START 47 os us 3 Keng SCH after SDA low for START and a repeated 4 oe 6 us 4 tw SCLL Pulse duration SCL low 4 7 1 3 us 5 tw SCLH Pulse duration SCL high 4 op us 6 tsuspav spLH Setup time SDA valid before SCL high 250 10002 ns 7 th SDA SDLL Hold time SDA valid after SCL low For 2 bus devices 0 3 09 090 us SDA high between STOP and START 47 13 us 9 504 Rise time SDA 1000 20 0 1C 300 ns 10 Rise time SCL 1000 20 0 1C 300 ns 11 t DA Fall time SDA 300 20 0 10 300 ns 12 Fall time SCL 300 20 0 1C 300 ns 13 tsu SCLH SDAH Setup time SCL high before SDA high for STOP condition 4 06 us 14 tw SP Pulse duration spike must be suppressed 0 50 ns 15 C Capacitive load for each bus line 400 400 pF 1 Psi I2C pins SDA and SCL do not feature fail safe I O buffers These pins could potentially draw current when the device is powe
161. el enable register 3 0190 0040 0193 FFFF Reserved 134 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Wa TEXAS INSTRUMENTS www ti com 5 13 2 McBSP Electrical Data Timing 5 13 2 1 Multichannel Buffered Serial Port McBSP Timing Table 5 50 Timing Requirements for McBSP see Figure 5 51 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 500 600 720 UNIT MIN MAX Cycle time CLKR X CLKR X ext or 6 67 2 3 ns 0 Pulse duration CLKR X high or CLKR X low CLKR X ext 0 5 1 ns f CLKR int 5 lsuFRH CKRL Setup time external FSR high before CLKR low GKR G 13 ES CLKR int 6 n th CKRL FRH Hold time external FSR high after CLKR low CLKR ext 3 e CLKR int 8 7 tsu DRV CKRL Setup time DR valid before CLKR low CLKR ext 0 9 e n CLKR int 3 th CKRL DRV Hold time DR valid after CLKR low CLKR ext 34 Eg CLKX int 9 10 tsyEXxH CKXL Setup time external FSX high before CLKX low CLKX ext 13 ES CLKX int 6 11 th CKXL FXH Hold time external FSX high after CLKX low CLKX ext 3 Eg 1 CLKRP CLKXP FSRP FSXP 0 If polarity of any of the signals is inverted then the timing references of that signal are also nverted P 1 CPU clock f
162. ense from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their pro
163. er to control the peripheral selection of the Video Ports VP1 VP2 McBSPO McBSP1 McASPO and DCD peripherals For more detailed information on the PERCFG register control bits see Figure 3 1 and Table 3 4 31 24 Reserved R 0 23 16 Reserved R 0 15 8 Reserved R 0 7 6 5 4 3 2 1 0 Reserved VP2EN VP1EN VPOEN I2COEN MCBSP1EN MCBSPOEN MCASPOEN R 0 R W 0 R W 0 R W 0 R W 0 R W 1 R W 1 R W 0 Legend R Read only R W Read Write n value after reset Figure 3 1 Peripheral Configuration Register PERCFG Address Location 0x01B3F000 0x01B3F003 Table 3 4 Peripheral Configuration PERCFG Register Selection Bit Descriptions BIT NAME DESCRIPTION 31 7 Reserved Reserved Read only writes have no effect VP2 Enable bit Determines whether the VP2 peripheral is enabled or disabled B VP2EN This feature allows power savings by disabling the peripheral when not in use 0 VP2 is disabled and the module is powered down default 1 VP2 is enabled 56 Device Configurations Submit Documentation Feedback 49 Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 3 4 Peripheral Configuration PERCFG Register Selection Bit Descriptions continued BIT DESCRIPTION VP1 Enable bit Determines whether the VP1 periphe
164. erating Conditions for PCI Outputs see Figure 5 49 600 500 A 600 720 parameter 38MHz MHz 66MHz MHz UNIT MIN MAX MIN MAX 1 ta PCLKH OV Delay time PCLK high to output valid 2 11 2 6 ns 2 ta PCLKH OLZ Delay time PCLK high to output low impedance 2 2 ns 3 ta PCLKH OHZ Delay time PCLK high to output high impedance 8 14 ns 13 k 1 PCI Output OO X99 k 2 3 Figure 5 49 PCI Output Timing 33 66 MHz Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 131 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 46 Timing Requirements for Serial EEPROM Interface see Figure 5 50 500 600 720 UNIT MIN MAX MAX 8 tsu DIV CLKH Setup time XSP_DI valid before XSP_CLK high 50 ns th CLKH DIV Hold time XSP_DI valid after XSP_CLK high O ns Table 5 47 Switching Characteristics Over Recommended Operating Conditions for Serial EEPROM Interface see Figure 5 50 500 600 PARAMETER 720 UNIT MIN 1 twosty Pulse duration XSP_CS low 4092P ns 2 taCLKL CSL Delay time XSP_CLK low to XSP_CS low 09 ns 3 la CSH CLKH Delay time XSP CS high to high 2046P ns 4 beten Pulse
165. es Table 3 5 PCFGLOCK Register Selection Bit Descriptions Read Accesses BIT NAME DESCRIPTION 31 1 Reserved Reserved Read only writes have no effect Lock status bit Determines whether the PERCFG register is locked or unlocked LOCKSTAT 0 Unlocked read accesses to the PERCFG register allowed 1 Locked write accesses to the PERCFG register do not modify the register state default Reads are unaffected by Lock Status Table 3 6 PCFGLOCK Register Selection Bit Descriptions Write Accesses BIT NAME DESCRIPTION Lock bits 0x10C0010C Unlocks PERCFG register accesses 31 0 LOCK Any write to the PERCFG register will automatically relock the register In order to avoid the unnecessary overhead of multiple unlock enable sequences all peripherals should be enabled with a single write to the PERCFG register with the necessary enable bits set Prior to waiting 128 CPU cycles the PERCFG register should be read There is no direct correlation between the CPU issuing a write to the PERCFG register and the write actually occurring Reading the PERCFG register after the write is issued forces the CPU to wait for the write to the PERCFG register to Once peripheral is enabled the DSP or other peripherals such as the HPI must wait a minimum of 128 CPU cycles before accessing the enabled peripheral The user must ensure that no accesses are performed to a
166. escriptor Pointer Register 01C8 0604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register 01C8 0608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register 01C8 060C TXSHDP Transmit Channel 3 DMA Head Descriptor Pointer Register 01C8 0610 Transmit Channel 4 Head Descriptor Pointer Register 01C8 0614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register 01C8 0618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register 01C8 061C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register 01C8 0620 RXOHDP Receive Channel 0 DMA Head Descriptor Pointer Register 01C8 0624 RX1HDP 01C8 0628 RX2HDP 01C8 062C 01C8 0630 Reserved Do not write 01C8 0634 RX5HDP 01C8 0638 RX6HDP 01C8 063C RX7HDP 01C8 0640 TXOINTACK Transmit Channel 0 Interrupt Acknowledge Register 01C8 0644 TX1INTACK Transmit Channel 1 Interrupt Acknowledge Register 01C8 0648 TX2INTACK Transmit Channel 2 Interrupt Acknowledge Register 01C8 064C Transmit Channel 3 Interrupt Acknowledge Register 01C8 0650 TX4INTACK Transmit Channel 4 Interrupt Acknowledge Register 01C8 0654 TXSINTACK Transmit Channel 5 Interrupt Acknowledge Register 01C8 0658 TX6INTACK Transmit Channel 6 Interrupt Acknowledge Register 01C8 065C TX7INTACK Transmit Channel 7 Interrupt Acknowledge Register 01C8 0660 RXOINTACK Receive Channel 0 Interrupt Acknowledge Register 01C8 0664 RX1INTACK 01C8 0668 RX2INTACK 01C8 066C RXSINTACK
167. estination Register B 144 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com TMS320D M642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 5 14 3 Video Port VP1 VP2 Electrical Data Timing 5 14 3 1 VCLKIN Timing Video Capture Mode Table 5 62 Timing Requirements for Video Capture Mode for VPxCLKINx see Figure 5 57 500 600 720 UNIT MIN MAX MAX 1 Cycle time VPXCLKINx 12 5 ns 2 twvkiH Pulse duration VPXCLKINx high 5 4 ns 3 Pulse duration VPXCLKINx low 5 4 ns 4 ven Transition time VPxCLKINx 3 ns 1 The reference points for the rise and fall transitions are measured at Vu MAX and Vu MIN P 2 K 3 _ Ld k4 Figure 5 57 Video Port Capture VPxCLKINx Timing Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 145 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 5 14 3 2 Video Data and Control Timing Video Capture Mode da TEXAS INSTRUMENTS www ti com Table 5 63 Timing Requirements in Video Capture Mode for Video Data and Control Inputs see Figure 5 58 500 600 720 UNIT MIN MAX MAX 1
168. etails on these muxed pins see the Device Configurations section of this data sheet Figure 2 11 EMAC MDIO Peripheral Signals Submit Documentation Feedback Device Overview 25 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 STCLK O VPOCLKO VPOCLK1 4 VPOCTLO lt VPOCTL1 lt VPOCTL2 VPOD 0 4 wwwwvwv VPOD 1 4 VPOD 2 CLKXO 4 VPOD 3 FSX0 4 VPOD 4 DX0 lt VPOD B CLKSO 4 VPOD G DRO 4 VPOD 7 FSRO lt VPOD 8 CLKRO 4 des and Control Logic Capture Display Buffer 2560 Bytes p gt VPOD 10 gt VPOD 11 p VPOD 12 ACLKRO gt VPOD 13 AFSRO VPOD 14 AHCLKRO VPOD 15 AMUTEINO gt VPOD 16 AMUTEO VPOD 17 ACLKXO gt VPOD 18 AFSXO AA A A A A A A A A A VPOD 9 4 p gt VPOD 19 AHCLKXO Channel A A Channel B uses only the VPOD 19 10 bidirectional pins Capture Display Buffer 2560 Bytes AA A A A A A A A A A Channel B B Video Port 0 VPO A Channel A supports BT 656 8 10 bit Y C Video 16 20 bit RAW Video 16 20 bit display modes and BT 656 8 10 bit Y C Video 16 20 bit RAW Video 16 20 bit and TSI 8 bit capture modes B Channel B supports BT 656 8 10 b
169. event 0 9 GPINT1 GPO event 1 10 GPINT2 GPO event 2 11 GPINT3 GPO event 3 12 XEVTO McBSPO transmit event 13 REVTO McBSPO receive event 14 XEVT1 McBSP1 transmit event 15 REVT1 receive event 16 VPOEVTYA VP0 Channel A Y event request 17 VPOEVTUA VP0 Channel A Cb event request 18 VPOEVTVA VP0 Channel A Cr event request 19 TINT2 Timer 2 interrupt 20 23 None 24 VPOEVTYB VPO Channel B Y event DMA request 25 VPOEVTUB VPO Channel B Cb event DMA request 26 VPOEVTVB VPO Channel B Cr event DMA request 27 31 L QG None 32 AXEVTE0 McASPO0 transmit even event 1 In addition to the events shown in this table each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events For more detailed information on EDMA event transfer chaining see the TMS320C6000 DSP Enhanced Direct Memory Access EDMA Controller Reference Guide literature number SPRU234 Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 79 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 3 TMS320DM642 EDMA Channel Synchronization Events continued EDMA CHANNEL EVENT NAME EVENT DESCRIPTION 33 AXEVTOO McASPO transmit odd event 34 AXEVTO McASPO transmit event 35 A
170. evice Configuration Pins TOUT1 LENDIAN AEA 22 19 GPO 3 PCIEEAI VDAC GPO 8 PCI66 HD5 AD5 PCI EN and EN CONFIGURATION PIN ES FUNCTIONAL DESCRIPTION Device Endian mode LEND TOUT1 LENDIAN BS 0 System operates in Big Endian mode 1 System operates in Little Endian mode default Bootmode 1 0 f U23 00 No boot default mode AEA 22 21 V24 01 boot based on PCI EN pin 10 Reserved 11 EMIFA boot EMIFA input clock select Clock mode select for EMIFA AECLKIN SEL 1 0 AEA 20 19 V25 00 AECLKIN default mode V26 01 CPU 4 Clock Rate 10 CPU 6 Clock Rate 11 Reserved PCI EEPROM Auto Initialization PCIEEAI PCI auto initialization via external EEPROM GPO 3 PCIEEAI L5 0 PCI auto initialization through EEPROM is disabled the PCI peripheral uses the specified PCI default values default 1 PCI auto initialization through EEPROM is enabled the PCI peripheral is configured through EEPROM provided the PCI peripheral pin is enabled PCI EN 1 EE 0 PCI operates at 66 MHz default VDAC GPO 8 PCI66 AD1 1 PCI operates at 33 MHz The 500 speed device supports PCI at 33 MHz only For proper 500 device operation when the PCI is enabled PCI_EN 1 this pin must be pulled up with a 1 kQ resistor at device reset Note If the PCI peripheral is disabled PCI EN pin 0 this pin must not be pulled up HPI peripheral bus width HPI_WIDTH 0
171. execute packet All functional units in the C64x CPU can access operands via the data cross path Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle On the C64x CPU a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle In addition to the C62x DSP fixed point instructions the C64x DSP includes a comprehensive collection of quad 8 bit and dual 16 bit instruction set extensions These VelociT 2 extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency This is a key factor for video and imaging applications Another key feature of the C64x CPU is the load store architecture where all instructions operate on registers as opposed to data in memory Two sets of data addressing units D1 and D2 are responsible for all data transfers between the register files and the memory The data address driven by the D units allows data addresses generated from one register file to be used to load or store data to or from the other register file The C64x D units can load and store bytes 8 bits half words 16 bits and words 32 bits with a single instruction And with the new data path extensions the C64x D unit can load and store doublewords 64 bits with a single instruction Furthermore
172. f the pins in an audio system A McASPs Error Detect function detects underruns overruns early late frame syncs DMA errors and external mute input Figure 2 15 McASPO Peripheral Signals 2 5 3 Terminal Functions Table 2 4 the terminal functions table identifies the external signal names the associated pin ball numbers along with the mechanical package designator the pin type O Z or 1 2 whether the pin has any internal pullup pulldown resistors and a functional pin description For more detailed information on device configuration peripheral selection multiplexed shared pins and debugging considerations see the Device Configurations section of this data sheet Submit Documentation Feedback Device Overview 29 TMS320DM642 da TEXAS Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 www ti com Table 2 4 Terminal Functions TYPE Pu DESCRIPTION CLOCK PLL CONFIGURATION CLKIN AC2 Clock Input This clock is the input to the PLL CLKOUT4 GPO 1 9 D6 VO Z IPU EE 11 EE O Z default or this pin can be CLKOUT6 GPO 2 C6 0 7 IPU 2 e 1 1 ds 2 0 2 default or this pin can be CLKMODE1 AE4 Ir IPD Clock mode select e Selects whether the CPU clock frequency input clock frequency x1 CLK
173. g flow begins when a 256 bit wide instruction fetch packet is fetched from a program memory The 32 bit instructions destined for the individual functional units are linked together by 1 bits in the least significant bit LSB position of the instructions The instructions that are chained together for simultaneous execution to eight in total compose an execute packet A 0 in the LSB of instruction breaks the chain effectively placing the instructions that follow it in the next execute packet A C64x DSP device enhancement now allows execute packets to cross fetch packet boundaries In the TMS320C62x TMS320C67x DSP devices if an execute packet crosses the fetch packet boundary 256 bits wide the assembler places it in the next fetch packet while the remainder of the current fetch packet is padded with NOP instructions In the C64x DSP device the execute boundary restrictions have been removed thereby eliminating all of the NOPs added to pad the fetch packet and thus decreasing the overall code size The number of execute packets within a fetch packet can vary from one to eight Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256 bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched After decoding the instructions simultaneously drive all active functional units for a maximum execution rate of e
174. h functionalities during run time Care should also be taken to ensure that no accesses are being performed before disabling the peripherals To help minimize power consumption in the DM642 device unused peripherals may be disabled Figure 3 3 shows the flow needed to enable or disable a given peripheral on the DM642 device Unlock the PERCFG Register Using the PCFGLOCK Register Write to PERCFG Register to Enable Disable Peripherals Read from PERCFG Register Wait 128 CPU Cycles Before Accessing Enabled Peripherals Figure 3 3 Peripheral Enable Disable Flow Diagram Submit Documentation Feedback Device Configurations 59 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 A 32 bit key value 0x10C0010C must be written to the Peripheral Configuration Lock register PCFGLOCK in order to unlock access to the PERCFG register Reading the PCFGLOCK register determines whether the PERCFG register is currently locked LOCKSTAT bit 1 or unlocked LOCKSTAT bit 0 see Figure 3 4 A peripheral can only be enabled when the PERCFG register is unlocked LOCKSTAT bit 0 Read Accesses 31 1 0 Reserved LOCKSTAT R 0 R 1 Write Accesses 31 0 LOCK W 0 Legend R Read only R W Read Write n value after reset Figure 3 4 PCFGLOCK Register Diagram Address Location 0x01B3 F018 Read Write Access
175. hitecture on the TMS320DM642 device For more information on the L2MODE bits see the cache configuration CCFG register bit field descriptions in the TMS320C64x Two Level Internal Memory Reference Guide literature number SPRU610 L2MODE L2 Memory Block Base Address 000 001 010 011 111 0x0000 0000 128K Byte SRAM lt 2 6 x a A s 5 0 0002 0000 z o 5 8 64K Byte RAM 2 0 0003 0000 32K Byte RAM 2 5 0x0003 8000 ss xz 32K Byte RAM 9 0x0003 FFFF 0x0004 0000 Figure 2 2 TMS320DM642 L2 Architecture Memory Configuration Submit Documentation Feedback Device Overview TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 2 4 Bootmode The DM642 device resets using the active low signal RESET While RESET is low the device is held in reset and is initialized to the prescribed reset state Refer to reset timing for reset timing characteristics and states of device pins during reset The release of RESET starts the processor running with the prescribed device configuration and boot mode www ti com The DM642 has three types of boot modes Host boot If host boot is selected upon release of RESET the CPU is internally stalled while the remainder of the device is released During this period an external host can initialize the CPU s memory space as necess
176. ical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 ACTV AELKOUX Ten lt srrnrrTY sssi ABE 7 0 4 ki 5 AEA 22 14 AEA 12 3 Row Address k 4 ZEE 5 AEA13 X Row Address X 63 0 E 12 12 90 4 AARE ASDCAS ASADS ASRE AAWE ASDWE ASWE A AARE ASDCAS ASADS ASRE AAWE ASDWE ASWE and AAOE ASDRAS ASOE operate as ASDCAS ASDWE and ASDRAS respectively during SDRAM accesses Figure 5 24 SDRAM ACTV Command for EMIFA DCAB AECLKOUTX ZA ZA ZA A N EE 1 Wee 1 ACEx v j ABE 7 0 AEA 22 14 12 3 L k 4 k 5 AEA13 1 1 12 FH 12 AAOE ASDRAS ASOE AARE ASDCAS ASADS ASRE 11 E 11 AAWE ASDWE ABWEU Figure 5 25 SDRAM DCAB Command for EMIFA Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 105 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 AEcLKOUTx _ Nf XA AA _yz ACEN ES EE ABE 7 0 Gs rrsx
177. ical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 15 3 VIC Electrical Data Timing 5 15 3 1 STCLK Timing Table 5 69 Timing Requirments for STCLK see Figure 5 62 500 600 720 UNIT MIN MAX MAX 1 lc STCLK Cycle time STCLK 33 3 ns 2 twsrCLKH Pulse duration STCLK high 16 ns 3 Iw STCLKL Pulse duration STCLK low 16 ns 4 Transition time STCLK 3 ns 1 The reference points for the rise and fall transitions are measured at Vu MAX and Vu MIN 4 2 M9 3 mm cM zx A anu E am STCLK ON Uf k4 Figure 5 62 STCLK Timing Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 151 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor da TEXAS INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 16 Ethernet Media Access Controller EMAC 5 16 1 The EMAC controls the flow of packet data from the DSP to the PHY EMAC Device Specific Information The ethernet media access controller EMAC provides an efficient interface between the DM642 DSP core processor and the network The DM642 EMAC support both 10Base T and 100Base TX or 10 Mbits second Mbps and 100 Mbps in either half or full duplex with
178. ight instructions every clock cycle While most results are stored in 32 bit registers they can be subsequently moved to memory as bytes half words or doublewords All load and store instructions are byte half word word or doubleword addressable For more details on the C64x CPU functional units enhancements see the following documents e TMSS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 e TMSS320C64x Technical Overview literature number SPRU395 8 Device Overview Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 32 MSBs 32 LSBs ST1b Store Data 4 ST1a Store Data Register File A A0 A31 Data Path A LD1b Load Data 32 MSBs LD1a Load Data 32 LSBs DA1 Address DA2 Address LD2a Load Data 32 LSBs LD2b Load Data MSB Register Data Path B f File B B0 B31 ST2a Store Data ee ST2b Store Data s Control Register File A M functional units the long dst is 32 MSBs and the dst is 32 LSBs Figure 2 1 TMS320C64x CPU DSP Core Data Paths Submit Documentation Feedback Device Overview 9 TMS320DM642 da TEXAS
179. ing RESET as well When the PCI peripheral is enabled a WARMRESET can be performed via the host A WARMRESET performs the same functionality as a hardware reset but does not relatch the boot configuration pins Whatever boot configuration that was latched on the previous hardware reset will be performed during the WARMRESET A hardware reset does not reset the PCI peripheral state machine The PCI state machine is reset via the PRST signal The PRST signal does not affect the DSP Emulation resets done using Code Composer Studio IDE have the same affect as a PCI WARMRESET For information on peripheral selection at the rising edge of RESET see the Device Configuration section of this data manual 5 6 1 Reset Electrical Data Timing Table 5 10 Timing Requirements for Reset see Figure 5 9 500 600 720 UNIT MN MAX MAX 1 tw RST Width of the RESET pulse 250 us 16 Setup time boot configuration bits valid before RESET high 1 4E or 4C 2 ns 17 tn boot Hold time boot configuration bits valid after RESET high 1 4P 3 ns 18 tsu PCLK RSTH Setup time PCLK active before RESET high 4 32N ons 1 AEA 22 19 LENDIAN PCIEEAI and HD5 AD5 are the boot configuration pins during device reset 2 1 clock frequency in ns C 1 CLKIN clock frequency in ns Select the MIN parameter value whichever value is larger 3 P 1 CPU clock frequency in
180. ing costly MDIO accesses For more details on the MDIO see the TMS320C6000 DSP Ethernet Media Access Controller EMAC Management Data Input Output MDIO Module Reference Guide literature number SPRU628 The 2 0 port on the TMS320DM642 allows the DSP to easily control peripheral devices communicate with a host processor In addition the standard multichannel buffered serial port McBSP may be used to communicate with serial peripheral interface SPI mode peripheral devices The DM642 has a complete set of development tools which includes a new C compiler an assembly optimizer to simplify programming and scheduling and a Windows debugger interface for visibility into source code execution Device Compatibility The DM642 device is a code compatible member of the C6000 DSP platform The C64x DSP generation of devices has a diverse and powerful set of peripherals For more detailed information on the device compatibility and similarities differences among the DM642 and other C64x devices see the TMS320DM642 Technical Overview literature number SPRU615 Submit Documentation Feedback TMS320DM642 Video Imaging Fixed Point Digital Signal Processor 3 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 1 3 Functional Block Diagram Figure 1 1 shows the functional block diagram of the DM642 device SDRAM 64 TMS320DM642
181. ion CLKOUT4 low 2P 0 7 2P 0 7 ns tycKo4 Transition time CLKOUT4 1 ns 1 The reference points for the rise and fall transitions are measured at Vo MAX and Vor MIN 2 is the high period of CLKIN in ns PL is the low period of CLKIN ns 3 P 1 CPU clock frequency in nanoseconds ns Wa 1 gt uom N 7 N f _ NL k 2 4 3 4 le Figure 5 12 CLKOUT4 Timing Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 91 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 17 Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 0 see Figure 5 13 500 600 PARAMETER 020 UNIT CLKMODE x1 x6 x12 MN MAX MAX 1 tw CKO6H Pulse duration CLKOUT6 high 3P 0 7 3P 0 7 ns 2 tw CKO6L Pulse duration CLKOUT6 low 0 7 0 7 ns tycKoe Transition time CLKOUT6 1 ns 1 The reference points for the rise and fall transitions are measured at Vo MAX and Voy MIN 2 PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns 3 P 1 CPU clock frequency in nanoseconds ns V 1 uom NO _ X4 _ NL k 2 3 4 le Figure 5 13 CLKOUT6 Timing Table 5 18 Timing Requirements for AECLK
182. is data sheet Note The DESIGN WARNING section of the TMS320DM642 BSDL file contains information and constraints regarding proper device operation while in Boundary Scan Mode 5 20 1 2 JTAG ID Register Description The JTAG ID register is a read only register that identifies to the customer the JTAG Device ID For the DM642 device the JTAG ID register resides at address location 0x01B3 F008 The register hex value for the DM642 device is 0x0007 902F For the actual register bit names and their associated bit field descriptions see Figure 5 73 and Table 5 89 31 28 27 12 11 1 0 VARIANT 4 Bit PART NUMBER 16 Bit MANUFACTURER 11 Bit LSB R 0000 R 0000 0000 0111 1001 R 0000 0010 111 R 1 Legend R Read only n value after reset Figure 5 73 JTAG ID Register Description TMS320DM642 Register Value 0x0007 902F Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 165 TMS3200DM942 33 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 89 JTAG ID Register Selection Bit Descriptions BIT NAE DESCRIPTION 31 28 VARIANT Variant 4 Bit value DM642 value 0000 27 12 PART NUMBER Part Number 16 Bit value DM642 value 0000 0000 0111 1001 11 1 MANUFACTURER Manufacturer 11 Bit value DM642 value 0000 0010 111 pn LSB LSB This bit is read as a 1 for DM642 5
183. ister 0200 0024 QSSRC QDMA psuedo source address register 0200 0028 QSCNT QDMA psuedo frame count register 0200 002C QSDST QDMA destination address register 0200 0030 QSIDX QDMA psuedo index register Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 81 TMS320DM642 da TEXAS Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 bii Table 5 6 Parameter RAM C64x 1 HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 01A0 0000 01A0 0017 Parameters for Event 0 6 words Parameters for Event 0 6 words or Reload Link Parameters for other Event 01A0 0018 01A0 002F Parameters for Event 1 6 words 01A0 0030 01A0 0047 Parameters for Event 2 6 words 01A0 0048 01A0 005F Parameters for Event 3 6 words 01A0 0060 01A0 0077 Parameters for Event 4 6 words 01A0 0078 01A0 008F Parameters for Event 5 01A0 0090 01A0 00A7 Parameters for Event 6 6 words 0180 00A8 01A0 00BF Parameters for Event 7 6 words 01A0 0000 0180 00D7 Parameters for Event 8 6 words 01A0 0008 01A0 OOEF 6 words Parameters for Event 9 6 words 0180 0060 0180 00107 Parameters for Event 10 6 words 01A0 0108 01A0 011F Parameters for Event 11 6 words 01A0 0120 01A0 0137 P
184. it RAW Video 8 10 bit capture modes and can display synchronized RAW Video data with Channel A C The same STCLK signal is used for all three video ports VP1 and VP2 Figure 2 12 Video Port 0 Peripheral Signals 26 Device Overview Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 STCLK O a VP1CLK0 gt VPICLKI 4 gt Timing and VPICTLO lt gt Control Logic VP1CTL1 lt gt VP1CTL2 lt gt VP1D 0 lt gt 4 gt VP1D 10 VP1D 1 lt gt 4 gt VP1D 11 VP1D 2 CLKX1 4 gt 4 gt VP1D 12 AXRO 0 VPID S FSX1 4 gt 4 gt VP1D 13 AXRO 1 VP1D 4 DX1 lt gt EE 4 gt VP1D 14 AXRO 2 VP1D B CLKS1 4 gt 2560 Bytes 4 gt VP1D 15 AXRO 3 VP1D 6 DR1 4 gt 4 gt VP1D 16 AXRO 4 VPID 7 FSR1 lt gt 4 gt VP1D 17 AXRO 5 VP1D 8 CLKR1 4 4 gt VP1D 18 AXRO 6 VP1D 9 lt gt 4 gt VP1D 19 AXRO 7 Channel A 4 lt lt A 4 p Channel B uses only 4 p the VP1D 19 10 2560 Bytes 4 p bidirectional pins 4 4 lt gt 4 Channel B B Video Port 1 VP1 A Channel A supports BT 656 8 10 bit Y C Video 16 20 bit RAW Video 16 20 bit display modes and BT 656 8 10 bit Y C Video 16 20 bit RAW Video 16 20
185. ital words that are long This is avoided in a Sigma Delta type D A converter by choosing a few widely spaced output levels and interpolating values between them The interpolating mechanism causes the output to oscillate rapidly between the levels in such a manner that the average output represents the value of input code In the VIC two output levels are chosen 0 and 1 and Sigma Delta interpolation scheme is implemented to interpolate between these levels with a rapidly changing signal The frequency of interpolation is dependent on the resolution needed When the video port is used in transport stream interface TSI mode the VIC port is used to control the system clock VCXO for MPEG transport stream The VIC supports the following features e Single interpolation for D A conversion e Programmable precision from 9 to 16 bits e Interface for register accesses For more detailed information on the DM642 VCXO interpolated control VIC peripheral see the TMS320C64x DSP Video Port VCXO Interpolated Control VIC Port Reference Guide literature number SPRU629 5 15 2 VIC Peripheral Register Description s 150 Table 5 68 VCXO Interpolated Control VIC Port Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C4 C000 VICCTL VIC control register 01C4 C004 VICIN VIC input register 01C4 C008 VPDIV VIC clock divider register 01C4 00 01 4 FFFF Reserved DM642 Peripheral Information and Electr
186. ization Events The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory Table 5 3 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels For the DM642 device the association of an event to a channel is fixed each of the EDMA channels has one specific event associated with it These specific events are captured in the EDMA event registers ERL ERH even if the events are disabled by the EDMA event enable registers EERL EERH The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM For more detailed information on the EDMA module and how EDMA events are enabled captured processed linked chained and cleared etc see the TMS320C6000 DSP Enhanced Direct Memory Access EDMA Controller Reference Guide literature number SPRU234 Table 5 3 TMS320DM642 EDMA Channel Synchronization Events EVENT DESCRIPTION 080 DSP INT HPI PCI to DSP interrupt 1 TINTO Timer 0 interrupt 2 TINT1 Timer 1 interrupt 3 SD INTA EMIFA SDRAM timer interrupt 4 GPINT4 EXT_INT4 GPO event 4 External interrupt pin 4 5 GPINT5 EXT_INT5 GPO event 5 External interrupt pin 5 GPINT6 EXT_INT6 GPO event 6 External interrupt pin 6 7 GPINT7 EXT_INT7 GPO event 7 External interrupt pin 7 ho Be GPINTO GPO
187. kable and fixed Interrupts 2 INT 04 through 15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields Table 5 7 shows the default interrupt sources for Interrupts INT 04 through 15 For more detailed information on interrupt sources and selection see the TMS320C6000 DSP Interrupt Selector Reference Guide literature number SPRU646 Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 83 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 7 DM642 DSP Interrupts continued CPU SELECTOR SELECIOR INTERRUPT INTERRUPT VALUE INTERRUPT SOURCE NUMBER CONTROL BINARY EVENT REGISTER 1 11100 AXINTO McASPO0 transmit interrupt 2 21 11101 ARINTO receive interrupt Jj 11110 11111 Reserved Reserved Do not use 5 5 2 Interrupts Peripheral Register Description s Table 5 8 Interrupt Selector Registers C64x HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Selects which interrupts drive CPU 019C 0000 MUXH Interrupt multiplexer high interrupts 10 15 INT10 INT15 019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4 9 INTO4 INTO9 019C 0008 EXTPOL External interrupt polarity W UM 019C 000C 0
188. l multiplexed HPI PCI pins function as PCI Also the multiplexed GPO PCI pins function as PCI pins for more details see Table 3 8 e The EN pin in combination with the PCI EN and HD5 pins controls the selection of the EMAC and MDIO peripherals for more details see Table 3 2 The PCI EN pin 1 and the PCI EEAI pin control the whether the PCI initializes its internal registers via external EEPROM PCI EEAI 1 or if the internal default values are used instead PCI EEAI 0 54 Device Configurations Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 3 2 HPI vs EMAC Peripheral Pin Selection CONFIGURATION SELECTION PERIPHERALS SELECTED GPO 0 Pin M5 HD5 Pin Y1 MAC EN Pin C5 HD50 HD 31 16 a 00 0 16 Hi Z 0 0 0 1 HPI16 used for EMAC 0 1 0 HPI32 HD 31 0 O 1 1 Hi Z used for EMAC 1 X X 1 Invalid configuration The GPO 0 pin must remain low during device reset 3 1 2 Device Configuration at Device Reset Table 3 3 describes the DM642 device configuration pins which are set up via external pullup pulldown resistors through the specified EMIFA address bus pins AEA 22 19 and the TOUT1 LENDIAN GPO S PCIEEAI and the HD5 pins all of which are latched during device reset Table 3 3 DM642 D
189. licable updates to the C64x device family specifically relating to the TMS320DM642 device have been incorporated GP7 through GPO after reset default to enabled as an input only SEE ADDS CHANGES DELETES Section 5 19 1 GPIO Device Specific Information Figure 5 71 GPIO Direction Register GPDIR Hex Address 0180 0004 Updated changed the default values for bits GP7DIR through GP3DIR and GPODIR from R W 1 to R W 0 Submit Documentation Feedback Revision History 167 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 6 Mechanical Data The following table s show the thermal resistance characteristics for the PBGA GDK GNZ ZDK and ZNZ mechanical packages 6 1 Thermal Data Table 6 1 Thermal Resistance Characteristics S PBGA Package GDK NO C W AIR FLOW m s 1 1 Junction to case 3 3 N A 2 Junction to board 7 92 N A 3 18 2 00 O 4 15 3 0 5 Junction to free air 5 13 7 1 0 6 12 2 2 00 7 0 37 O 08 Psi 0 47 0 5 si unction to package to Wee 027 0 57 1 0 10 0 7 2 00 11 11 4 00 O 12 11 0 5 Psijg Junction to board 13 10 7 1 0 14 10 2 2 00 1 m s meters per second Table 6 2 Thermal Resistance Characteristics S PBGA Package GNZ
190. ment a user interface The 2 port supports e Compatible with Philips 2 Specification Revision 2 1 January 2000 Fast Mode up to 400 Kbps no fail safe I O buffers Noise Filter to Remove Noise 50 ns or less e Seven and Ten Bit Device Addressing Modes e Master Transmit Receive and Slave Transmit Receive Functionality Events Interrupt or Polling e Slew Rate Limited Open Drain Output Buffers Figure 5 35 is a block diagram of the 2 0 module 118 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com DC Clock DC Data 12 0 Module Noise Filter Noise Filter TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Clock Prescale I2CPSCx Y Bit Clock Generator I2CCLKHx I2CCLKLx Peripheral Clock 4 Control I2COARx Addons Address Transmit I2CXSRx I2CDXRx Transmit Shift Transmit Buffer I2CMDRx Mode I2CCNTx Bata Interrupt DMA Receive I2CDRRx I2CRSRx Receive Buffer Receive Shift Interrupt Enable I2CIERx I2CSTRx interrupt I2CISRCx interrupt m Shading denotes a peripheral module not available for this configuration Figure 5 35 12 0 Module Block Diagram For more detailed information on the
191. mit frame sync 1 2 VP1D 2 CLKX1 9 AE6 V O Z IPD VP1 input output data 2 pin 1 0 2 or McBSP1 transmit clock 1 0 2 default MULTICHANNEL BUFFERED SERIAL PORT 0 McBSP0 Video Port 0 input output data 8 pin 2 or McBSPO receive clock VPOD 8 CLKRO 9 AE15 VO Z ES VO Z default VPOD 7 FSRO AB16 VO Z data 7 2 or McBSPO receive frame sync 0 2 VPOD 6 DRO 9 AC16 or PD VP0 input output data 6 pin 1 0 2 or McBSPO receive data default VPODIBJ CLKSO 9 AD16 ES ee McBSPO external clock source 1 as VPOD 4 DX0 9 AE16 O Z IPD VPO input output data 4 pin 0 2 or McBSPO transmit data 0 2 default VPOD 3 FSX09 AF16 VO Z 4 data 3 I O Z or McBSPO transmit frame sync 0 2 VPOD 2 CLKXO0 9 AF17 VO Z IPD VPO input output data 2 pin 2 or McBSPO transmit clock 0 2 default 40 Device Overview Submit Documentation Feedback 49 Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL IPD 1 NAME No TYPE IPU DESCRIPTION ETHERNET MAC EMAC Host port data 2 default or EMAC transmit receive or control pins O Z HPI pin functions are default see the Device Configurations section of this data sheet EMAC Media Independent I F
192. more details on these muxed pins see the Device Configurations section of this data sheet Figure 2 7 CPU and Peripheral Signals Submit Documentation Feedback Device Overview 21 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 22 64 AED 63 0 Device Overview 20 Memory Map Space Select Byte Enables VCXO Interpolated Control Port VIC Figure 2 8 EMIFA VIC Peripheral Signals External Memory I F Control Bus Arbitration EMIFA 64 bit da TEXAS INSTRUMENTS www ti com AECLKIN AECLKOUT1 AECLKOUT2 ASDCKE AARE ASDCAS ASADS ASRE AAOE ASDRAS ASOE AAWE ASDWE ASWE AARDY AHOLD AHOLDA ABUSREQ VDAC GPO0 8 PCI66 Submit Documentation Feedback Texas INSTRUMENTS www ti com HD 15 0 AD 15 0 HD 31 16 AD 31 16 O HCNTLO PSTOP HCNTL1 PDEVSEL HHWIL PTRDY 16 ONLY HD 15 0 AD 15 0 HD 31 16 AD 31 16 O GPO 10 PCBE3 HR W PCBE2 HDS2 PCBE1 PCBEO GPO 12 PGNT GPO 11 PREQ 32 Register Select Half Word Select 32 Command Byte Enable T un ER PCI Interface B TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Host Port Interface Serial EEPROM HAS PPAR HR W PCBE2 HCS PPERR HDS1 PSERR HDS2 PCBE1 HRDY PIRDY HINT PFRAME GPO 14 PCLK
193. motive www ti com automotive DSP dsp ti com Broadband www ti com broadband Clocks and Timers www ti com clocks Digital Control www ti com digitalcontrol Interface interface ti com Medical www ti com medical Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony and ZigBee Solutions www ti com prf Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2008 Texas Instruments Incorporated
194. n section Configurable Video Ports VP1 VP2 10 100 Ethernet MAC EMAC Management Data Input Output MDIO VCXO Interpolated Control Port VIC k lt N 32 Bit Timers internal clock source CPU 8 clock frequency 3 General Purpose Input Output Port GP0 16 Size Bytes 288K On Chip Memory Organization 16K Byte 16KB L1 Program L1P Cache 16KB L1 Data L1D Cache 256KB Unified Mapped RAM Cache L2 CPU ID CPU Rev ID Control Status Register CSR 31 16 0x0C01 JTAG BSDL_ID JTAGID register address location 0x01B3F008 0x0007902F Frequency MHz 500 600 720 2 ns DM642 500 and DM642A 500 500 MHz CPU 100 MHz EMIF 1 33 MHz PCI port Cvcle Tim 1 67 ns DM642 600 and DM642A 600 i 600 MHz CPU 133 MHz EMIF 66 MHz PCI port 1 39 ns DM642 720 720 MHz CPU 133 MHz EMIF 1 66 MHz PCI port C 1 2 V 500 Voltage Sre V 1 4 V A 500 A 600 600 720 V 3 3 V PLL Options CLKIN frequency multiplier Bypass x1 x6 x12 23 x 23 mm 548 Pin BGA GDK and ZDK BGA Package I 27 x 27 mm 548 Pin BGA GNZ and ZNZ Process Technology um 0 13 um Product Status 2 Product Preview PP Advance Information Al or Production Data PD 1 On this DM64xTM device 6 Device Overview the rated EMIF speed affects only the SDRAM interface on the EMIF For more detailed information
195. ndication Register 01C8 380C LINK MDIO PHY Link Status Register MDIO Link Status Change Interrupt Register 01C8 3810 build field is reserved and only supports writes of 0 MDIO Link Status Change Interrupt Masked Register 0128 3814 LINKINTMASKED MAC1 field is reserved and only supports writes of 0 C MDIO User Command Complete Interrupt Register 1 9 9819 USERINTRAW MAC1 field is reserved and only supports writes of 0 C8 381C MDIO User Command Complete Interrupt Masked Register 0108 381C USERINTMASKED MAC1 field is reserved and only supports writes of 0 MDIO User Command Complete Interrupt Mask Set Register 0128 3820 USERINTMASKSET MAC1 field is reserved and only supports writes of 0 C MDIO User Command Complete Interrupt Mask Clear Register 0128 3824 VSERINTMASKOLEAR MAC1 field is reserved and only supports writes of 0 01C8 3828 USERACCESSO MDIO User Access Register 0 01C8 382C USERACCESS1 Reserved Do not write 01C8 3830 USERPHYSELO MDIO User PHY Select Register 0 01C8 3834 USERPHYSEL1 Reserved Do not write 01C8 3838 01C8 3FFF Reserved 158 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback 43 Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor in SPRS200L JULY 2002 REVISED JANUARY 2007 5 17 3 Management Data Input Output MDIO Electrical Data Timing Table 5 79 Timing Requirements for MDIO Input see Figure 5 67
196. nnel A VP1D 8 2 Muxed B VP1D 9 1 0 Standalone McBSPOEN PERCFG 1 McASPOEN PERCFG 0 VPO Channel A VPO Upper Data 10 pins McASPOEN PERCFG 0 VPOD 19 12 Muxed VPOD 11 10 Standalone McASPO Control 58 Device Configurations Channel B McBSP1EN PERCFG 2 McASPOEN PERCFG 0 VP1 Channel A VP1 Upper Data 10 pins VP1D 19 12 Muxed D VP1D 11 10 Standalone McASPOEN PERCFG 0 McASPO Data VP1 Channel B Consists of VPOD BJCLKRO VPOD 7 FSRO VPOD 6J DRO VPOD B CLKSO VPOD AJDXO VPOD S FSXO VPOD 2 CLKXO Consists of VP1D 8 CLKR1 VP1D 7 FSR1 VP1D 6 DR1 VP1D BJCLKS1 VP1D 4JDX1 VP1D S FSX VP1D 2 CLKX1 Consists of VPOD 19 AHCLKXO VPOD 18 AFSX0 VPOD 17 ACLKXO VPOD 16 AMUTEO VPOD 15 AMUTEINO VPOD 14 AHCLKRO VPOD 13 AFSRO VPOD 12 ACLKRO Consists VP1D 19 12 AXRO 7 0 Figure 3 2 VP1 VPO McBSP1 5 0 and McASPO Data Control Pin Muxing Submit Documentation Feedback 4 TEXAS www ti com 3 3 Peripheral Configuration Lock TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 By default the McASPO VPO VP1 VP2 and 2 peripherals are disabled on power up In order to use these peripherals on the DM642 device the peripheral must first be enabled in the Peripheral Configuration register PERCFG Software muxed pins should not be programmed to switc
197. ns 90 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 15 Timing Requirements for CLKIN for 720 Devices 9 9 see Figure 5 11 720 PLL MODE x12 PLL MODE x6 x1 Bypass UNIT MN MAX MN MN MAX 1 tc cLkIN Cycle time CLKIN 16 6 33 3 13 3 33 3 13 3 33 3 ns 2 tw CLKINH Pulse duration CLKIN high 0 45C 0 45C 0 45C ns 3 Iw CLKINL Pulse duration CLKIN low 0 45C 0 45C 0 45C ns 4 tucuKIN Transition time CLKIN 5 5 1 ns 5 UG CLKIN Period jitter CLKIN 0 02C 0 02C 0 02C ns 1 The reference points for the rise and fall transitions are measured at Vu MAX and MIN 2 For more details on the PLL multiplier factors x6 x12 see the Clock PLL section of this data sheet 3 C CLKIN cycle time in ns For example when CLKIN frequency is 50 MHz use C 20 ns 524 o 1 kasa 2 d k 3 1 4 3 le Figure 5 11 CLKIN Timing Table 5 16 Switching Characteristics Over Recommended Operating Conditions for CLKOUTA 2 9 see Figure 5 12 500 600 PARAMETER SE UNIT CLKMODE x1 x6 x12 MN MAX MAX 1 tw CKO4H Pulse duration CLKOUT4 high 2P 0 7 2P 0 7 ns 2 tw CKO4L Pulse durat
198. nter register Contains the current value of the incrementing counter 0194 000C 0197 FFFF Reserved Table 5 82 Timer 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Determines the operating mode of the timer monitors the 91380000 EE timer status and controls the function of the TOUT pin Contains the number of timer input clock cycles to count 0138 0003 SE Timer 1 period register This number controls the TSTAT signal frequency 0198 0008 CNT1 Timer 1 counter register Contains the current value of the incrementing counter 0198 000C 019B FFFF Reserved Table 5 83 Timer 2 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Determines the operating mode of the timer monitors the 01AC 0000 CTL2 Timer 2 control register deer Statue Contains the number of timer input clock cycles to count 0182 0004 PHD2 This number controls the TSTAT signal frequency 01AC 0008 CNT2 Timer 2 counter register Contains the current value of the incrementing counter 160 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 83 Timer 2 Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 01AC 000C 01AF FFFF o Reserved 5 18 3 Timer Ele
199. ntrol 0180 0014 CECTL3 EMIFA CES space control 0180 0018 SDCTL EMIFA SDRAM control 0180 001C SDTIM EMIFA SDRAM refresh control 0180 0020 SDEXT EMIFA SDRAM extension 0180 0024 0180 003C Reserved 0180 0040 PDTCTL Peripheral device transfer PDT control 0180 0044 CE1 space secondary control 0180 0048 CESECO EMIFA CEO space secondary control 0180 004C oc Reserved 0180 0050 CESEC2 EMIFA CE2 space secondary control 0180 0054 CESEC3 EMIFA CE3 space secondary control 0180 0058 0183 FFFF Reserved 5 8 3 EMIF Electrical Data Timing 5 8 3 1 Asynchronous Memory Timing Table 5 22 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module see Figure 5 17 and Figure 5 18 500 600 720 UNIT MIN MAX 3 tsu EDV AREH Setup time AEDx valid before AARE high 6 5 ns 4 th AREH EDV Hold time AEDx valid after AARE high 1 ns 6 lsuARDY EKO1H Setup time AARDY valid before AECLKOUTx high 3 ns 7 th EKO1H ARDY Hold time AARDY valid after AECLKOUTx high 2 5 ns 1 To ensure data setup time simply program the strobe width wide enough AARDY is internally synchronized The AARDY signal is only recognized two cycles before the end of the programmed strobe time and while AARDY is low the strobe time is extended cycle by cycle When AARDY is recognized low the end of the strobe time is two cycles after AARDY is recognized high To use
200. nts TMS320C64x Technical Overview literature number SPRU395 gives an introduction to the C64x digital signal processor and discusses the application areas that are enhanced by the C64x V DSP VelociTI 2TM VLIW architecture The TMS320C64x DSP Video Port VCXO Interpolated Control VIC Port Reference Guide literature number SPRU629 describes the functionality of the Video Port and VIC Port peripherals The TMS320C6000 DSP Multichannel Audio Serial Port McASP Reference Guide literature number SPRU041 describes the functionality of the McASP peripheral TMS320C6000 DSP Inter Integrated Circuit I2C Module Reference Guide literature number SPRU175 describes the functionality of the 2 peripheral Device Overview Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 TMS320C6000 DSP Ethernet Media Access Controller EMAC Management Data Input Output MDIO Module Reference Guide literature number SPRU628 describes the functionality of the EMAC and MDIO peripherals TMS320DM642 Technical Overview literature number SPRU615 describes the TMS320DM642 architecture including details of its peripherals This document also shows several example applications such as using the DM642 device in development of IP phones video on demand set top boxes and surveillance digital video recorders The TMS320DM642
201. nue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a lic
202. o DX valid appliesonly to the first data bit of a device if and only if DXENA 1 in SPCR if DXENA 0 then D1 D2 0 if DXENA 1 then D1 4P D2 8P 8 Extra delay from FSX high to DX valid appliesonly to the first data bit of a device if and only if DXENA 1 in SPCR if DXENA 0 then D1 D2 0 if DXENA 1 then D1 4P D2 8P 136 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback d Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 CLKS 1 gt k Lu 7 CLKR rede e P T le FSR int gh ___ Ge 6 FSR ext BEE ux CHEM CENE ____________________ 10 9 4 FSX ext FSX XDATDLY 00b E 3p da k 12 13 A Parameter No 13 applies to the first data bit only when XDATDLY 0 Figure 5 51 McBSP Timing Table 5 52 Timing Requirements for FSR When GSYNC 1 see Figure 5 52 500 600 720 UNIT MN MAX 1 lsu FRH CKSH Setup time FSR high before CLKS high 4 ns 2 th CKSH FRH Hold time FSR high after CLKS high 4 ns ak XA N N N N Xy X 3 1 2 2 FSR external CLKR X no need to resync 222 N CLKR X needs resync ___ 20 No A N N Figure 5 52 FSR Timing When GSYNC 1 Submit Documentation Feedback DM642 Peri
203. o the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS Figure 5 43 HPI32 Read Timing HAS Used Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 127 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 HAS 1 2 HCNTL 1 0 J x x J e 0 3 HM HSTROBE A TK HCS S HD 31 0 gt f 4 14 EH HSTROBE refers to the following logical operation HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS Figure 5 44 HPI32 Write Timing HAS Not Used Tied High 4 gt 19 Kk 3 0 7 A 11 10 HCNTL 1 0 Le x x Wii 11 e EWL men A ME bn lt 18 HSTROBE B X HCS E HD 31 0 input 22 quss 14 HRDY A A For correct operation strobe the HAS signal only once per HSTROBE active cycle B HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS Figure 5 45 HPI32 Write Timing HAS Used 128 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002
204. ontact your sales representative Submit Documentation Feedback Device Overview 51 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 www ti com TMS 320 DM642AGDK A 5 PREFIX L DEVICE SPEED RANGE TMX S device 500 500 MHz CPU 100 MHz EMIF 33 MHz PCI TMP Prototype device 600 600 MHz CPU 133 MHz EMIF 66 MHz PCI TMS Qualified device 720 720 MHz CPU 133 MHz EMIF 66 MHz PCI SMX Experimental device MIL 5 500 2 CPU 100 MHz 33 MHz PCI SMJ MIL PRF 38535 QML 6 600 MHz CPU 133 MHz EMIF 66 MHz PCI SM High Rel 38535 7 720 MHz CPU 133 MHz EMIF 66 MHz PCI TEMPERATURE RANGE DEFAULT 02 TO 90 C A DEVICE FAMILY Blank 0 C to 90 C commercial temperature 320 TMS320 DSP family A 40 C to 105 C extended temperature PACKAGE TYPE BXC C D GDK 548 plastic BGA GNZ 548 pin plastic BGA ZDK 548 pin plastic BGA with Pb free soldered balls ZNZ 548 pin plastic BGA with Pb free soldered balls DEVICE D DM64x DSP 642 Silicon Revision 1 2 and1 1 642A Silicon Revision 2 0 The extended temperature A version devices may have different operating conditions than the commercial temperature devices For more details see the recommended operating conditions portion of this data sheet BGA Ball Grid Array The ZDK and ZNZ mechanical package designators represent th
205. operation e 143 MHz SDRAM for 100 MHz operation Other configurations may be possible but timing analysis must be done to verify all AC timings are met Verification of AC timings is mandatory when using configurations other than those specified above recommends utilizing I O buffer information specification IBIS to analyze all AC timings To properly use IBIS models to attain accurate timing analysis for a given system see the Using IBIS Models for Timing Analysis application report literature number SPRA839 To maintain signal integrity serial termination resistors should be inserted into all EMIF output signal lines see the Terminal Functions table for the EMIF output signals For more detailed information on the DM642 peripheral see the TMS320C6000 DSP External Memory Interface EMIF Reference Guide literature number SPRU266 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com 5 8 2 EMIF Peripheral Register Description s Table 5 21 EMIFA Registers TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0180 0000 GBLCTL EMIFA global control 0180 0004 CECTL1 EMIFA CE1 space control 0180 0008 CECTLO EMIFA CEO space control 0180 000C e Reserved 0180 0010 CECTL2 EMIFA CE2 space co
206. ord only 4P 8 ns 1 HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS 2 P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns 3 This parameter is used during HPID reads and writes For reads at the beginning of a word transfer 2 or the first half word transfer 16 on the falling edge of HSTROBE the HPI sends the request to the EDMA internal address generation hardware and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID For writes HRDY goes high if the internal write buffer is full 124 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 _ 12 9 2 2 TTT weg TTT eeng TTT f 3 4 3 2 HSTROBE R a cc E HCS mm NT NES CE 15 15 7 9 16 4 9 HD 15 0 output 6 ae half word d kg 2nd half word HRDY _ T TN A HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 HDS2 OR HCS Figure 5 38 16 Read Timing HAS Not Used Tied High HAS Nf A gt 19 le 1
207. ot Width 2 Bit Delay 149 15 lt Ae AXR n Data Out Transmit XGXGXC A0 Al A30 A31 BO B1 830 831 0 C1 C2 C3 C31 t For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift data out and the McASP receiver is configured for rising edge to shift data in t For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out and the McASP receiver is configured for falling edge to shift data in Figure 5 34 McASP Output Timings Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 117 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 10 Inter Integrated Circuit 12C The inter integrated circuit I2C module provides an interface between TMS320C6000 DSP and other devices compliant with Philips Semiconductors Inter IC bus bus specification version 2 1 and connected by way of an External components attached to this 2 wire serial bus can transmit receive up to 8 bit data to from the DSP through the I2C module 5 10 1 12 Device Specific Information The DC module the TMS320DM642 be used by the DSP to control local peripherals ICs DACs ADCs etc while the other may be used to communicate with other controllers in a system or to imple
208. ot covered here For information on these other bit fields in the CSR register see the TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 Figure 5 7 PWRD Field of the CSR Register A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the PD mode takes effect As best practice NOPs should be padded after the PWRD bits are set in the CSR to account for this delay If PD1 mode is terminated by a non enabled interrupt the program execution returns to the instruction where PD1 took effect If PD1 mode is terminated by an enabled interrupt the interrupt service routine will be executed first then the program execution returns to the instruction where PD1 took effect In the case with an enabled interrupt the GIE bit in the CSR and the NMIE bit in the interrupt enable register IER must also be set in order for the interrupt service routine to execute otherwise execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt PD2 and modes can only be aborted by device reset Table 5 2 summarizes all the power down modes Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 77 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 da TEXAS INSTRUMENTS www ti com Table 5 2 Characteristics of the Power Down Mode
209. peripheral while it is disabled 60 Device Configurations Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com 3 4 Device Status Register Description TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 The device status register depicts the status of the device peripheral selection For the actual register bit names and their associated bit field descriptions see Figure 3 5 and Table 3 7 31 24 Reserved R 0 23 m Reserved R 0 15 12 11 10 9 8 Reserved MAC EN WIDTH PCI EEAI PCI EN R 0 7 6 5 4 3 2 1 0 Reserved CLKMODE1 CLKMODEO LENDIAN BOOTMODE1 BOOTMODEO AECLKINSEL1 AECLKINSELO R x R x R x R x R x R x R x R x Legend Read only R W Read Write n value after reset Figure 3 5 Device Status Register DEVSTAT Description 0x01B3 F004 Submit Documentation Feedback Device Configurations 61 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor da TEXAS INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 3 7 Device Status DEVSTAT Register Selection Bit Descriptions BIT NAME DESCRIPTION 31 12 Reserved Reserved Read only writes have no effect EMAC enable bit Shows the status of whether EMAC peripheral is enabled or disabled default
210. pheral Information and Electrical Specifications 137 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 www ti com Table 5 53 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 10b CLKXP 047 see Figure 5 53 500 600 120 UNIT MASTER SLAVE MN MAX MAX MN MAX tsu DRV CKXL Setup time DR valid before CLKX low 12 2 12 ns 5 thiCKXL DRV Hold time DR valid after CLKX low 4 5 24 ons 2 P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns For all SPI Slave modes CLKG is programmed as 1 4 of the CPU clock by setting CLKSM CLKGDV 1 Table 5 54 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave CLKSTP 10b 0 see Figure 5 53 500 600 PARAMETER 720 UNIT MASTER SLAVE MIN MAX MAX MN MAX 1 th CKXL FXL Hold time FSX low after CLKX low 9 T 2 T 3 ns 2 taexL ckxH Delay time FSX low to CLKX high 9 L 25 1 3 ns 3 ta CKXH DXV Delay time CLKX high to DX valid 2 4 12P 28 20 17 ns Disable time DX high impedance following last data bit e lais ckxL DXHz from CLKX low d i Nem ERE ns Disable time DX high impedance following last data bit 7 ldis FXH DXHZ from FSX high 9 p 9 4P 3 12 17 ns 8 ta EXL DXV Del
211. programmed via the EMIF CE space control registers E AECLKOUT period in ns for EMIFA 3 Select signals for EMIFA include ACEx ABE 7 0 AEA 22 3 AAOE and for EMIFA writes include AED 63 0 Setup 2 Strobe 3 Not Ready Hold 2 AEGLKOUTE 7 7 7 ef VT X X 1 k 1 2 E ANNE 2 ma 1 le 2 ABE 7 0 m 8 X n h AEA 22 3 B Address X i i 3 kbl Ee A 4 AED 63 0 lt 1 0 AAOE ASDRAS ASOE es p 5 je 5 e AAWE ASDWE ASWE A an 72 wis A AAOE ASDRAS ASOE AARE ASDCAS ASADS ASRE and AAWE ASDWE ASWE operate as AAOE identified under select signals AARE and AAWE respectively during asynchronous memory accesses Figure 5 17 Asynchronous Memory Read Timing for EMIFA 96 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Setup 2 Strobe 3 i Not Ready Hold 2 U _f _ VZ L S _ N NS 2 82 V ee ECKE 8 i 9 4 m lH F m 8 k 9 ABE 7 0 ee a AEA 22 3 sss mr s Y
212. put O Z Boot Configuration MAC enable pin MAC EN I The PCI EN and the MAC EN pin control the selection enable disable of the TOUNO m SS HPI and GPO 15 9 or PCI peripherals The pins work in conjunction to enable disable these peripherals For more details see the Device Configurations section of this data sheet TINPO A4 Timer 0 or general purpose input Submit Documentation Feedback Device Overview 39 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL IPD TYPE 2 DESCRIPTION NAME NO IPU INTER INTEGRATED CIRCUIT 0 2060 SCLO E4 2 I2CO clock SDAO D3 2 1200 data MULTICHANNEL BUFFERED SERIAL PORT 1 McBSP1 Video Port 1 1 input output data 8 pin 2 or McBSP1 receive clock VP1D 8 CLKR1 9 AD8 2 ES VO Z default VP1D 7 FSR10 AC7 7 data 7 10 2 or McBSP1 receive frame sync 0 2 VP1D 6 DR1 9 AD7 or PPD VP1 input output data 6 pin 1 0 2 or McBSP1 receive data default VP1DIBJ CLKS1 9 AE7 BN ES 2 0 McBSP1 external clock source as VP1D 4 Dx1 AC6 0 2 IPD VP1 input output data 4 pin I O Z or McBSP1 transmit data 0 2 default VP1D 3JFSX109 AD6 VO Z EN data 3 I O Z McBSP1 trans
213. r more details on the CLKMODE pins and the PLL multiply factors see the Clock PLL section of this data sheet Device Endian mode LEND n Shows the status whether the system is operating Big Endian mode or Little Endian mode default 0 System is operating in Big Endian mode 1 System is operating in Little Endian mode default 3 BOOTMODE1 Bootmode configuration bits Shows the status of what device bootmode configuration is operational Bootmode 1 0 00 No boot default mode BOOTMODEQ 01 HPI PCI boot based on PCI_EN pin 10 Reserved 11 EMIFA boot 1 AECLKINSEL1 EMIFA input clock select Shows the status of what clock mode is enabled or disabled for the EMIF Clock mode select for EMIFA AECLKIN SEL 1 0 C 00 AECLKIN default mode CERS 01 CPU 4 Clock Rate 10 CPU 6 Clock Rate 11 Reserved 62 Device Configurations Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com 3 5 Multiplexed Pin Configurations TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed Some of these pins are configured by software and the others are configured by external pullup pulldown resistors only at reset Those muxed pins that are configured by software should not be programmed to switch functionalities during run time Those m
214. ral is enabled or disabled 5 VP1EN 0 VP1 is disabled and the module is powered down default This feature allows power savings by disabling the peripheral when not in use 1 VP1 is enabled VPO Enable bit Determines whether the VPO peripheral is enabled or disabled 4 VPOEN 0 VPO is disabled and the module is powered down default This feature allows power savings by disabling the peripheral when not in use 1 is enabled Inter integrated circuit O I2CO enable bit e GEBEN Selects whether 12 0 peripheral is enabled or disabled default 0 12 0 is disabled and the module is powered down default 1 12 0 is enabled Video Port 1 VP1 lower data pins vs McBSP1 enable bit Selects whether VP1 peripheral lower data pins or the McBSP1 peripheral is enabled 0 1 lower data pins are enabled and function if VP1EN 1 McBSP1 is disabled the remaining VP1 2 MCBSP1EN upper data pins are dependent on the MCASPOEN bit and the VP1EN bit settings 1 is enabled VP1 lower data pin functions are disabled default For a graphic logic representation of this Peripheral Configuration PERCFG Register selection bit and the signal pins controlled selected see Figure 3 2 Video Port 0 VPO lower data pins vs McBSPO enable bit Selects whether VPO peripheral lower data pins or the McBSP1 peripheral is enabled 0 VPO lower data pins are enabled and function if VPOEN 1 Mc
215. red own A Fast mode I2C bus device be used in a Standard mode I C bus system but the requirement tsu SDA SCLH 2 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line t max tsuspa scLH 1000 250 1250 ns according to the Standard mode Specification before the SCL line is released A device must internally provide a hold time of at least 300 ns for the SDA signal referred to the ViHmin of the SCL signal to bridge the undefined region of the falling edge of SCL 4 The maximum 5 504 5011 has only to be met if the device does not stretch the low period 5011 of the SCL signal 5 total capacitance of one bus line in pF If mixed with HS mode devices faster fall times are allowed Ak 11 9 3 k 1 S E us p LT X X7 le 1 8 14 11 13 le TERN gt fk sc a k SCH 12 15 des 4 2 ktol lt Stop Start Repeated Stop tart Figure 5 36 DC Receive Timings Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 121 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007
216. requency in ns For example when running parts at 720 MHz use P 1 39 ns 3 Use whichever value is greater Minimum CLKR X cycle times must be met even when CLKR X is generated by an internal clock source The minimum CLKR X cycle times are based on internal logic speed the maximum usable speed may be lower due to EDMA limitations and AC timing requirements 4 This parameter applies to the maximum McBSP frequency Operate serial clocks CLKR X in the reasonable range of 40 60 duty cycle Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 135 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 51 Switching Characteristics Over Recommended Operating Conditions for McBSP 2 see Figure 5 51 500 600 PARAMETER 720 UNIT MAX 1 Delay time CLKS high to CLKR X high for internal CLKR X 14 10 ns d CKSH CKRXH generated from CLKS input 2 Cycle time CLKR X CLKR X int 4P or 6 67 94 5 ns tw CKRX Pulse duration CLKR X high or CLKR X low CLKR X int Cc 16 1 6 ns A ta CKRH FRV Delay time CLKR high to internal FSR valid CLKR int 2 1 3 ns CLKX int 1 7 3 D la CKXH FXV Delay time CLKX high to internal FSX valid CLKX ext 17 9 ns 12 tc Disable time DX high impedance following last data CLKX in
217. rical Specifications Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 5 5 Interrupts TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 5 5 1 Interrupt Sources and Interrupt Selector The C64x DSP core supports 16 prioritized interrupts which are listed in Table 5 7 The highest priority interrupt is INT 00 dedicated to RESET while the lowest priority interrupt is INT 15 The first four interrupts INT 00 INT 03 are non maskable and fixed The remaining interrupts INT 04 15 are maskable and default to the interrupt source specified in Table 5 7 The interrupt source for interrupts 4 15 can be programmed by modifying the selector value binary value in the corresponding fields of the Interrupt Selector Control registers MUXH address 0x019C0000 and MUXL address 0x019C0004 Table 5 7 DM642 DSP Interrupts SELECTOR SELECIOR INTERRUPT MEER CONTROL BINARY EVENT INTERRUPT SOURCE REGISTER INT 000 Po RESET 010 C Po NMI INT 020 fo Reserved Reserved Do not use INT 030 NENNEN Reserved Reserved Do not use INT 040 MUXL 4 0 00100 GPINT4 EXT_INT4 GP0 interrupt 4 External interrupt pin 4 INT 0502 MUXL 9 5 00101 GPINT5 EXT_INT5 GPO interrupt 5 External interrupt pin 5 INT_06 2 MUXL 14 10 00110
218. rite latency e assertion length CEEXT For standard SBSRAM or ZBT SRAM interface goes inactive after the final command has been issued CEEXT 0 For synchronous FIFO interface with glue ACEN is active when ASOE is active CEEXT 1 e Function of ASADS ASRE RENEN For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles RENEN 0 For FIFO interface ASADS ASRE acts as ASRE with NO deselect cycles RENEN 1 e Synchronization clock SNCCLK Synchronized to AECLKOUT1 or AECLKOUT2 C AARE ASDCAS ASADS ASRE AAOE ASDRAS ASOE and AAWE ASDWE ASWE operate as ASADS ASRE ASOE and ASWE respectively during programmable synchronous interface accesses Figure 5 20 Programmable Synchronous Interface Write Timing for EMIFA With Write Latency 0 9 100 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Write Latency 1 AEcLKOUTx __ f NX f AX f _f N f J AAOE ASDRAS ASOE 0 1 12 12 AAWE ASDWE ABWE O L C A The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields respectively in the EMIFA CE Space Secondary Control register CExSEC In this figure SYNCWL 1 and C
219. roducts are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material MSL Peak Temp The Moisture Sensitivity Level rating according to the industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI
220. s PRWD Field BITS 15 10 POWER DOWN MODE WAKE UP METHOD EFFECT ON CHIP S OPERATION 000000 No power down 001001 PD1 Wake by an enabled interrupt 010001 PD1 Wake by an enabled or non enabled interrupt CPU halted except for the interrupt logic Power down mode blocks the internal clock inputs at the boundary of the CPU preventing most of the CPU s logic from switching During PD1 EDMA transactions can proceed between peripherals and internal memory 011010 PD2 Wake by a device reset Output clock from PLL is halted stopping the internal clock structure from switching and resulting in the entire chip being halted All register and internal RAM contents are preserved All functional I O freeze in the last state when the PLL clock is turned off 011100 PD3 Wake by a device reset Input clock to the PLL stops generating clocks All register and internal RAM contents are preserved All functional UO freeze in the last state when the PLL clock is turned off Following reset the PLL needs time to re lock just as it does following power up Wake up from takes longer than wake up from PD2 because the PLL needs to be re locked just as it does following power up All others Reserved 1 When entering PD2 and all functional I O remains the previous state However for peripherals which are asynchronous in nature or peripheral
221. s close as possible No less than 4 large caps per supply 8 total should be placed outside of the BGA Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 75 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 www ti com Any cap selection needs to be evaluated from a yield manufacturing point of view As with the selection of any component verification of capacitor availability over the product s production lifetime should be considered 5 3 4 Peripheral Power Down Operation The DM642 device can be powered down in three ways e Power down due to pin configuration e Power down due to software configuration relates to the default state of the peripheral configuration bits in the PERCFG register e Power down during run time via software configuration On the DM642 device the HPI PCI and EMAC and MDIO peripherals are controlled selected at the pin level during chip reset e g PCI EN HD5 and MAC EN pins The 5 0 McBSPO McBSP1 VPO VP1 VP2 and 2 0 peripheral functions are selected via the peripheral configuration PERCFG register bits For more detailed information on the peripheral configuration pins and the PERCFG register bits see the Device Configurations section of this document 5 3 5 Power Down Modes Logic 76 Figure 5 6 shows the power down mode logic on the DM642 CLKOUT
222. s data sheet DESCRIPTION N13 N15 N20 P7 P12 14 20 R13 R15 T7 T20 U7 U20 Wan Y6 Y7 Y8 Y10 Y11 Y13 Y14 Submit Documentation Feedback Device Overview 45 TMS320DM642 49 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU DESCRIPTION CVpp Y16 Y17 Y19 Y20 Y21 6 20 21 1 2 V supply voltage 500 device 1 4 V supply voltage A 500 A 600 600 720 devices see the Power Supply Decoupling section of this data sheet GROUND PINS A1 A6 A8 A12 A14 A19 A22 A26 B3 B6 B7 B13 B19 C2 C4 C13 C18 C23 D1 D2 D5 D13 D18 D22 D24 E3 E6 E9 E16 E18 E21 E23 E26 F5 GND Ground pins 46 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions
223. s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by to Customer on an annual basis Addendum Page 2 GDK S PBGA N548 23 10 22 90 99 21 10 20 90 1 SCH O 0 50 NOM 2 80 MAX gt 2 xc MECHANICAL DATA MPBG301 JULY 2002 PLASTIC BALL GRID ARRAY 20 00 TYP 0 80 Bid 0 40 0000000_ OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO 0 80 1 3 5 7 9 2 4 6 8 I OOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO
224. s with an external clock source output signals may transition in response to stimulus on the inputs Under these conditions peripherals will not operate according to specifications 5 3 7 C64x Power Down Mode with an Emulator If user power down modes are programmed and an emulator is attached the modes will be masked to allow the emulator access to the system This condition prevails until the emulator is reset or the cable is removed from the header If power measurements are to be performed when in a power down mode the emulator cable should be removed When the DSP is in power down mode PD2 or PD3 emulation logic will force any emulation execution command such as Step or Run to spin in IDLE For this reason PC writes such as loading code will fail A DSP reset will be required to get the DSP out of PD2 PD3 78 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 4 Enhanced Direct Memory Access EDMA Controller The EDMA controller handles all data transfers between the level two L2 cache memory controller and the device peripherals on the DM642 DSP These data transfers include cache servicing non cacheable memory accesses user programmed data transfers and host accesses 5 4 1 EDMA Device Specific Information 5 4 1 1 Channel Synchron
225. sistor 4 PCI input leakage currents include Hi Z output leakage for all bidirectional buffers with 3 state outputs 5 Measured with average activity 50 high 50 low power at 25 case temperature and 133 MHz for 600 and 720 speeds 100 MHz EMIF for 500 speed This model represents a device performing high DSP activity operations 50 of the time and the remainder performing low DSP activity operations The high low DSP activity models are defined as follows e High DSP Activity Model 8 instructions cycle with 2 LDDW instructions L1 Data Memory 128 bits cycle via LDDW instructions L1 Program Memory 256 bits cycle L2 EMIF EDMA 50 writes 50 reads to from SDRAM 50 bit switching McBSP 2 channels at E1 rate Timers 2 timers at maximum rate Low DSP Activity Model 2 instructions cycle with 1 LDH instruction L1 Data Memory 16 bits cycle L1 Program Memory 256 bits per 4 cycles L2 EMIF EDMA None McBSP 2 channels at E1 rate Timers 2 timers at maximum rate The actual current draw is highly application dependent For more details on core and I O activity refer to the TMS320DMx Power Consumption Summary application report literature number SPRA962 Submit Documentation Feedback Device Operating Conditions 71 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007
226. sor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 4 Terminal Functions continued SIGNAL NAME NO eg D AD18 AE3 AE8 AE10 AE12 AE14 AE19 24 Vss AF1 GND Ground pins AF7 AF9 AF11 AF13 AF15 AF19 AF22 AF26 DESCRIPTION Submit Documentation Feedback Device Overview 49 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 www ti com 2 6 Development 2 6 1 Development Support 50 TI offers an extensive line of development tools for the TMS320C6000 DSP platform including tools to evaluate the performance of the processors generate code develop algorithm implementations and fully integrate and debug software and hardware modules The following products support development of 60007 DSP based applications Software Development Tools Code Composer Studio M Integrated Development Environment IDE including Editor C C Assembly Code Generation and Debug plus additional development tools Scalable Real Time Foundation Software DSP BIOS which provides the basic run time target software needed to support any DSP application Hardware Development Tools Extended Development System XDS Emulator supports C6000 DSP multiprocessor system debug EVM Evaluation Module For a complete listing of development support tools for the TMS320C600
227. t 3 9 a dis CKXH DXHZ bit from CLKX high CLKX ext 24 9 OR CLKX int 3 9 D1 7 4 D20 la CKXH DXV elay time igh to vali CLKX ext 2 1 DI 9 D20 ns Delay time FSX high to DX valid FSX int 2 3 D1 8 5 6 028 14 iq FxH DxV ONLY applies when in data ns 8 8 delay 0 XDATDLY 00b mode FSX ext E I Da 1 CLKRP CLKXP FSRP FSXP 0 If polarity of any of the signals is inverted then the timing references of that signal are also inverted Minimum delay times also represent minimum output hold times 3 Minimum CLKR X cycle times must be met even when CLKR X is generated by an internal clock source Minimum CLKR X cycle times are based on internal logic speed the maximum usable speed may be lower due to EDMA limitations and AC timing requirements P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns 5 Use whichever value is greater C HorL S sample rate generator input clock 4P if CLKSM 1 P 1 CPU clock frequency S sample rate generator input clock clks if CLKSM 0 clks period CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit see 4 above 7 Extra delay from CLKX high t
228. t Display VPXCLKINx Timing 5 14 3 4 Video Control Input Output and Video Display Data Output Timing With Respect to VPXCLKINx and VPxCLKOUTXx Video Display Mode Table 5 65 Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to VPxCLKINx and VPxCLKOUTx see Figure 5 60 500 600 720 UNIT MIN MAX 13 lsu VCTLV VKIH Setup time VPxCTLx valid before VPxCLKINx high 2 9 ns 14 th vCTLV VKIH Hold time VPxCTLx valid after VPXCLKINx high 0 5 ns 15 tsu VCTLV VKOH Setup time VPxCTLx valid before VPxCLKOUTx high 7 4 ns 16 th VCTLV VKOH Hold time VPxCTLx valid after VPxCLKOUTx high 9 ns 1 Assuming non inverted VPxCLKOUTx signal Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 147 TMS320DM642 43 Texas Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 66 Switching Characteristics Over Recommended Operating Conditions in Video Display Mode for Video Data and Control Output Shown With Respect to VPXCLKINx and VPxCLKOUTx 2 see Figure 5 60 500 600 720 UNIT MIN MAX 1 1 Cycle time VPXCLKOUTx 0 7 V 0 7 ns 2 twvKOH Pulse duration VPxCLKOUTx high VH 0 7 VH 0 7 ns 3 Pulse duration VPXCLKOUTx low VL 0 7 VL 0 7 ns 4
229. ternal Device 11 34 Data Signals B Input to DSP gt Control signals include data for Writes B Data signals are generated during Reads from an external device Figure 5 4 Board Level Input Output Timings DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 5 2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between Vu and Vu or between Vu and in a monotonic manner 5 3 Power Supplies For more information regarding Tl s power management products and suggested devices to power DSPs visit www ti com dsppower 5 3 1 Power Supply Sequencing TI DSPs not require specific power sequencing between the core supply and the I O supply However Systems should be designed to ensure that neither supply is powered up for extended periods of time 1 second if the other supply is below the proper operating voltage 5 3 2 Power Supply Design Considerations A dual power supply with simultaneous sequencing can be used to eliminate the delay between core and power up A Schottky diode can also be used to tie the core rail to the I O rail see Figure 5 5 UO Supply Schottky Diode Core Supply A z D Figure 5
230. th extensions e Quad 8 bit and dual 16 bit extensions with data flow enhancements e Additional functional unit hardware e Increased orthogonality of the instruction set e Additional instructions that reduce code size and increase register flexibility The CPU features two sets of functional units Each set contains four units and a register file One set contains functional units L1 S1 M1 and D1 the other set contains units D2 M2 S2 and L2 The two register files each contain 32 32 bit registers for a total of 64 general purpose registers In addition to supporting the packed 16 bit and 32 40 bit fixed point data types found in the C62x VelociTI VLIW architecture the C64x register files also support packed 8 bit data and 64 bit fixed point data types The two sets of functional units along with two register files compose sides A and B of the CPU see the functional block and CPU DSP core diagram and Figure 2 1 The four functional units on each side of the CPU can freely share the 32 registers belonging to that side Additionally each side features a data cross path a single data bus connected to all the registers on the other side by which the two sets of functional units can access data from the register files on the opposite side The C64x CPU pipelines data cross path accesses over multiple clock cycles This allows the same register to be used as a data cross path operand by multiple functional units in the same
231. tions as a general purpose audio serial port optimized for the needs of multichannel audio applications The McASP is useful for time division multiplexed TDM stream Inter Integrated Sound I2S protocols and intercomponent digital audio interface transmission DIT McASP0 Device Specific Information The TMS320DM642 device includes one multichannel audio serial port McASP interface peripheral McASPO The McASP is a serial port optimized for the needs of multichannel audio applications The McASP consists of a transmit and receive section These sections can operate completely independently with different data formats separate master clocks bit clocks and frame syncs or alternatively the transmit and receive sections may be synchronized The McASP module also includes a pool of 16 shift registers that may be configured to operate as either transmit data receive data or general purpose I O GPIO The transmit section of the McASP can transmit data in either time division multiplexed TDM synchronous serial format or in a digital audio interface DIT format where the bit stream is encoded for S PDIF AES 3 IEC 60958 CP 430 transmission The receive section of the McASP supports the TDM synchronous serial format The McASP can support one transmit data format either a TDM format or DIT format and one receive format at a time All transmit shift registers use the same format and all receive shift registers use the same format Ho
232. trols EMIFA range 8800 0000 BAFF FFFF 0184 82 MAR187 Controls EMIFA range 8800 0000 BBFF FFFF 0184 82F0 MAR188 Controls EMIFA CE3 range 8000 0000 BCFF FFFF 0184 82F4 MAR189 Controls EMIFA range BD00 0000 BDFF FFFF 0184 82F8 MAR190 Controls EMIFA range 00 0000 BEFF FFFF 0184 82FC MAR191 Controls EMIFA range BF00 0000 BFFF FFFF Submit Documentation Feedback Device Overview 11 TMS320DM642 da TEXAS Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 ili Table 2 2 L2 Cache Registers C64x continued HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 01848300 018483FC MAE Reserved 01848400 0187FFFF Reserved 12 Device Overview Submit Documentation Feedback d TEXAS INSTRUMENTS www ti com 2 3 Memory Map Summary TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 2 3 shows the memory map address ranges of the DM642 device Internal memory is always located at address 0 and can be used as both program and data memory The external memory address ranges in the DM642 device begin at the hex address location 0x8000 0000 for EMIFA Table 2 3 TMS320DM642 Memory Map Summary MEMO
233. truments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been characterized fully and the quality and reliability of the device have been demonstrated fully Tl s standard warranty applies Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate still is undefined Only qualified production devices are to be used TI device nomenclature also includes a suffix with the device family name This suffix indicates the package type for example GDK the temperature range for example A is the extended temperature range and the device speed range in megahertz for example 5 is 500 MHz Figure 2 16 provides a legend for reading the complete device name for any TMS320C6000 DSP platform member The ZDK package like the GDK package is a 548 ball plastic BGA only with Pb free balls The ZNZ is the Pb free package version of the GNZ package For device part numbers and further ordering information for TMS320DM642 in the GDK GNZ ZDK and ZNZ package types see the TI website http www ti com or c
234. ts of two channels A and B with a 5120 byte capture display buffer that is splittable between the two channels For more details on the Video Port peripherals see the TMS320C64x DSP Video Port VCXO Interpolated Control VIC Port Reference Guide literature number SPRUG29 The McASPO port supports one transmit and one receive clock zone with eight serial data pins which can be individually allocated to any of the two zones The serial port supports time division multiplexing on each pin from 2 to 32 time slots The DM642 has sufficient bandwidth to support all 8 serial data pins transmitting a 192 kHz stereo signal Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter IC Sound 25 format In addition the McASPO transmitter may be programmed to output multiple S PDIF IEC60958 AES 3 CP 430 encoded data channels simultaneously with a single RAM containing the full implementation of user data and channel status fields also provides extensive error checking and recovery features such as the bad clock detection circuit for each high frequency master clock which verifies that the master clock is within a programmed frequency range 2 53200 642 Video Imaging Fixed Point Digital Signal Processor Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor
235. tsuvpaTv vkin Setup time VPxDx valid before VPXCLKINx high 2 9 ns 2 tnvDATV VKIH Hold time VPxDx valid after VPXCLKINx high 0 5 ns 3 Setup time VPxCTLx valid before VPXCLKINx high 2 9 ns 4 tn VCTLV VKIH Hold time VPxCTLx valid after VPXCLKINx high 0 5 ns 146 VPxCLKINx Nf O Z 1 NW X X Y X X XX XX X X X X Y X x V Y V M YY Y EE b Y PE x k YYYY YY WM WM WM NA NN NA NA NA Y X X X X X X X X X I CTLx PRK MO Figure 5 58 Video Port Capture Data and Control Input Timing DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 5 14 3 3 VCLKIN Timing Video Display Mode Table 5 64 Timing Requirements for Video Display Mode for VPXxCLKINx see Figure 5 59 500 600 720 UNIT MAX MAX 1 Cycle time VPXCLKINx 9 ns 2 twvkiH Pulse duration VPXCLKINx high 4 1 ns 3 twvkiL Pulse duration VPXCLKINx low 4 1 ns 4 ven Transition time VPxCLKINx 3 ns 1 The reference points for the rise and fall transitions are measured at Vu MAX and MIN Re 1 4 K MEME NN Z Aw LK ON VPXCLKINx N Figure 5 59 Video Por
236. tus Unmasked Register 01C8 01A4 MACINTSTATMASKED MAC Interrupt Status Masked Register 01C8 01A8 MACINTMASKSET MAC Interrupt Mask Set Register 01C8 01AC MACINTMASKCLEAR MAC Interrupt Mask Clear Register 01C8 01BO MACADDRLO MAC Address Channel 0 Lower Byte Register 01C8 01B4 MACADDRL1 01C8 01B8 MACADDRL2 01C8 01BC MACADDRL3 01C8 01CO MACADDRL4 Reserved Do not write 01C8 0104 MACADDRL5 01C8 0108 MACADDRL6 01C8 01CC MACADDRL7 01C8 01D0 MACADDRM MAC Address Middle Byte Register 01C8 01D4 MACADDRH MAC Address High Bytes Register 01C8 01D8 MACHASH1 MAC Address Hash 1 Register 01C8 01DC MACHASH2 MAC Address Hash 2 Register Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 153 TMS320DM642 Video Imaging Fixed Point Digital Signal Processor SPRS200L JULY 2002 REVISED JANUARY 2007 Table 5 70 Ethernet MAC EMAC Control Registers continued da TEXAS INSTRUMENTS www ti com HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 0160 BOFFTEST Backoff Test Register 01C8 01 4 TPACETEST Transmit Pacing Test Register 0108 01 8 RXPAUSE Receive Pause Timer Register 01C8 01EC TXPAUSE Transmit Pause Timer Register 01C8 01F0 0108 O1FF r om Reserved 01C8 0200 01C8 05FF see Table 5 71 EMAC Statistics Registers 01C8 0600 TXOHDP Transmit Channel 0 DMA Head D
237. ut voltage ranges PCI Vip 0 5 V to DVpp 0 5 V except PCI Vo 0 3 V to 4 V Output voltage ranges PCI Vop 0 5 V to DVpp 0 5 V default 0 C to 90 A version A 500 A 600 Storage temperature range 65 to 150 Package Temperature Cycling Temperature Range 40 C to 125 C Number of Cycles 500 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 All voltage values are with respect to Vss 4 2 Recommended Operating Conditions MIN NOM UNIT Supply voltage Core 500 device 1 1 14 1 2 1 26 V Supply voltage Core A 500 A 600 600 720 devices 1 1 36 14 1 44 V DVpp Supply voltage UO 3 14 3 3 3 46 V Vss Supply ground 0 0 0 V Vin High level input voltage except PCI 2 V Vu Low level input voltage except PCI 0 8 V Vip Input voltage PCI 0 5 DVpp 0 5 V ViHP High level input voltage PCI 0 5DVpp DVpp 0 5 V Vu p Low level input voltage PCI 0 5 0 3DVpp V Vos Maximum voltage during overshoot undershoot 1 0 2 4 300 V Default 0 90 C Tc
238. uxed pins that are configured by external pullup pulldown resistors are mutually exclusive only one peripheral has primary control of the function of these pins after reset Table 3 8 identifies the multiplexed pins on the DM642 device shows the default primary function and the default settings after reset and describes the pins registers etc necessary to configure specific multiplexed functions Table 3 8 DM642 Device Multiplexed Pin Configurations MULTIPLEXED PINS DEFAULT DEFAULT NAME No FUNCTION SETTING DESCRIPTION CLKOUTA GPO 1 D6 CLKOUT4 GP1EN 0 disabled These pins are software configurable To use these pins as GPIO pins the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured CLKOUT6 GPO 2 C6 CLKOUT6 GP2EN 0 disabled GPxEN 1 GPx pin enabled GPxDIR 0 GPx pin is an input GPxDIR 1 GPx pin is an output The VDAC output pin function is default To use GPO 8 as a GPIO pin the PCI needs to be disabled PCI EN 0 the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured C G C GP8EN 0 disabled VDAC GPO 8 AD1 VDA C EN 0 disabled GP8EN 1 GP8 pin enabled GP8DIR 0 8 pin is an input GP8DIR 1 GP8 pin is an output Note If the PCI peripheral is disabled PCI EN pin 0 this pin must not
239. ved Submit Documentation Feedback DM642 Peripheral Information and Electrical Specifications 155 TMS320DM642 da TEXAS Video Imaging Fixed Point Digital Signal Processor INSTRUMENTS SPRS200L JULY 2002 REVISED JANUARY 2007 i Table 5 73 EWRAP Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 3000 EWTRCTRL TR control 01C8 3004 EWCTL Interrupt control register 01C8 3008 EWINTTCNT Interrupt timer count 0108 300C 0108 37FF Reserved 5 16 3 EMAC Electrical Data Timing Table 5 74 Timing Requirements for MRCLK see Figure 5 63 500 600 720 UNIT MIN MAX c MRCLK Cycle time MRCLK 40 ns 2 w MRCLKH Pulse duration MRCLK high 14 ns tw MRCLKL Pulse duration MRCLK low 14 ns 1 1 2 3 A Z Z MRCLK N NL N Z N Figure 5 63 MRCLK Timing EMAC Receive Table 5 75 Timing Requirements for MTCLK see Figure 5 63 500 600 720 UNIT MN MAX MAX to MTCLK Cycle time MTCLK 40 ns tw MTCLKH Pulse duration MTCLK high 14 ns tw MTCLKL Pulse duration MTCLK low 14 ns 2 9M 3 X MTCLK N NL N Z N Figure 5 64 MTCLK Timing EMAC Transmit 156 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS
240. ved 01A0 FF9C EPRH Event polarity high register 01A0 4 CIPRH Channel interrupt pending high register 01A0 FFA8 CIERH Channel interrupt enable high register 01A0 FFAC CCERH Channel chain enable high register 01A0 FFBO ERH Event high register 01A0 4 EERH Event enable high register 01A0 FFB8 ECRH Event clear high register 01A0 FFBC ESRH Event set high register 01A0 FFCO PQARO Priority queue allocation register 0 01A0 FFC4 PQAR1 Priority queue allocation register 1 01A0 FFC8 PQAR2 Priority queue allocation register 2 01A0 FFCC Priority queue allocation register 3 01A0 FFDC EPRL Event polarity low register 01A0 FFEO PQSR Priority queue status register 01A0 4 CIPRL Channel interrupt pending low register 01A0 FFE8 CIERL Channel interrupt enable low register 01A0 FFEC CCERL Channel chain enable low register 01A0 FFFO ERL Event low register 01A0 FFF4 EERL Event enable low register 01A0 FFF8 ECRL Event clear low register 01A0 FFFC ESRL Event set low register 01A1 0000 0183 FFFF NENNEN Reserved Table 5 5 Quick DMA QDMA and Pseudo Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0200 0000 QOPT QDMA options parameter register 0200 0004 QSRC QDMA source address register 0200 0008 QCNT QDMA frame count register 0200 000C QDST QDMA destination address register 0200 0010 QIDX QDMA index register 0200 0014 0200 001C Reserved 0200 0020 QSOPT QDMA pseudo options reg
241. w group invalid O ns 13 lamsTH LOWV Delay time RESET high to low group valid 11 ns 14 twrastL zHz Delay time RESET low to Z group high impedance 01 ns 15 twastH zv Delay time RESET high to Z group valid 2P 8P ns 86 P 1 CPU clock frequency in ns For example when running parts at 720 MHz use P 1 39 ns the EMIF input clock AECLKIN CPU 4 clock or T period in ns for EMIFA a KONERT EMIF Z group consists of AEA 22 3 AED 63 0 ACE 3 0 ABE 7 0 AARE ASDCAS ASADS ASRE AAWE ASDWE ASWE AAOE ASDRAS ASOE 5 ASDCKE and APDT Low group consists XSP CS CLK MDCLK and DO MDIO all of which apply only when PCI EEPROM is enabled with PCI EN 1 and MCBSP2 0 Otherwise the CLK MDCLK and XSP DO MDIO pins are in the Z group For more details on the PCI configuration pins see the Device Configurations section of this data sheet Z group consists HD 31 0 AD 31 0 and the muxed EMAC output pins XSP_CLK MDCLK XSP_DO MDIO VPOD 2 CLKXO VP1D 2 CLKX1 VPOD 3 FSX0 VP1D 3 FSX1 VPOD 4 DX0 VP1D 4 DX1 VPOD 8 CLKRO VP1D 8 CLKR1 VPOD 7 FSRO 16 bit HPI mode only HRDY PIRDY HINT PFRAME VPOD 19 9 6 5 1 0 VP1D 19 9 6 5 1 0 and VP2D 19 0 DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SP
242. wever the transmit and receive formats need not be the same Both the transmit and receive sections of the McASP also support burst mode which is useful for non audio data for example passing control information between two DSPs The McASP peripheral has additional capability for flexible clock generation and error detection handling as well as error management For more detailed information on and the functionality of the McASP peripheral see the TMS320C6000 DSP Multichannel Audio Serial Port McASP Reference Guide literature number SPRU041 McASP Block Diagram Figure 5 32 illustrates the major blocks along with external signals of the TMS320DM642 McASPO peripheral and shows the 8 serial data AXR pins The McASP also includes full general purpose I O GPIO control so any pins not needed for serial transfers can be used for general purpose I O DM642 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320DM642 INSTRUMENTS Video Imaging Fixed Point Digital Signal Processor www ti com SPRS200L JULY 2002 REVISED JANUARY 2007 McASP0 Transmit Frame Sync AFSX0 Generator Transmit Clock Check AHCLKXO Hi it See Generator ACLKXO gt AMUTEO AMUTEINO See Clock Check AHCLKRO High ES Generator ACLKRO E o Transmit Receive 5 Data Frame Sync AFSRO lt i Generator D n S x S AXRO 0 AXRO 1 AXRO 2 AXR
243. y GPO 3 L5 Note This pin must remain low during device reset VCXO Interpolated Control Port VIC single bit digital to analog converter VDAC output output only default or this pin can be programmed as a GP0 8 1 2 Boot Configuration PCI frequency selection PCI66 If the PCI peripheral is enabled PCI EN pin 1 then 0 PCI operates at 66 MHz default VDAC GPO 8 PCI66 9 AD1 0 2 1 PCI operates at 33 MHz The 500 device supports PCI at 33 MHz only For proper 500 device operation when the PCI peripheral is enabled PCI EN 1 this pin must be pulled up with a 1 resistor at device reset Note If the PCI peripheral is disabled PCI EN pin 0 this pin be must not pulled up C Clock output at 1 6 of the device speed O Z default or this pin can be 3 LKOUT6 GP0 2 m E PM programmed as GPO 2 pin 0 2 Clock output at 1 4 of the device speed O Z default or this pin can be programmed as 1 pin 0 2 HOST PORT INTERFACE HPI or PERIPHERAL COMPONENT INTERCONNECT PCI or EMAC Boot Configuration PCI enable pin 1 The PCI EN pin and the MAC EN pin control the selection enable disable of PCI EN E2 D the HPI EMAC MDIO and GPO 15 8 or PCI peripherals The pins work in conjunction to enable disable these peripherals for more details see the Device Configurations section of this data sheet CLKOUTA GPO 1 9 D6 0 2 IPU

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