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ANALOG DEVICES ADuC832 Manual(1)(1)

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1. TIMER 2 OVERFLOW RX CLOCK TX CLOCK TIMER 2 INTERRUPT Figure 53 Timer 2 UART Baud Rates 58 0 ADuC832 Timer 3 Generated Baud Rates The high integer dividers in a UART block mean that high speed baud rates are not always possible using some particular crystals For example using a 12 MHz crystal a baud rate of 115200 is not possible To address this problem the ADuC832 has added a dedicated baud rate timer Timer 3 specifically for generating highly accurate baud rates Timer 3 can be used instead of Timer 1 or Timer 2 for generating very accurate high speed UART baud rates including 115200 and 230400 Timer 3 also allows a much wider range of baud rates to be obtained In fact every desired bit rate from 12 bit s to 393216 bit s can be generated to within an error of 0 8 Timer 3 also frees up the other three timers allowing them to be used for different applications A block diagram of Timer 3 is shown in Figure 54 TIMER 1 TIMER 2 TX CLOCK FIG 53 TIMER 1 TIMER 2 RX CLOCK FIG 53 FRACTIONAL DIVIDER RX CLOCK CORE CLK IS DEFINED BY THE CD BITS IN PLLCON Figure 54 Timer 3 UART Baud Rates Two SFRs T3CON and T3FD are used to control Timer 3 T3CON is the baud rate control SFR allowing Timer 3 to be used to set up the UART baud rate and setting up the binary divider DIV Table XXVII T3CON SFR Bit Designations Bit Name Description 7
2. 82 ss reg ea ck asa 2 7 E 5 g o 5 5 e a 12 BIT VOLTAGE OUTPUT DAC 12 BIT VOLTAGE OUTPUT DAC DAC CONTROL PWM CONTROL TIME INTERVAL COUNTER WAKEUP CCT SYNCHRONOUS SERIAL INTERFACE SPI OR PC SDATA MOSI Figure 1 ADuC832 Block Diagram Shaded Areas are Features Not Present on the ADuC812 REV 0 ADuC832 PIN FUNCTION DESCRIPTIONS Mnemonic Type Function DVpp P Digital Positive Supply Voltage 3 V or 5 V Nominal E Analog Positive Supply Voltage 3 V or 5 V Nominal CREF IO Decoupling Input for On Chip Reference Connect 0 1 uF between this pin and AGND VREF IO Reference Input Output This pin is connected to the internal reference through a series resistor and is the reference source for the analog to digital converter The nominal internal reference voltage is 2 5 V which appears at the pin See ADC section on how to connect an external reference AGND G Analog Ground Ground reference point for the analog circuitry 1 0 1 7 I Port 1 is an 8 bit input port only Unlike other ports Port 1 defaults to Analog Input mode To configure any of these Port Pins as a digital input write a 0 to the port bit Port 1 pins are multifunction and share the following functionality ADCO0 ADC7 I Analog Inputs Eight single ended analog inputs Channel selection is v
3. Figure 20 Flash EE Data Memory Control and Configuration Table VII ECON Flash EE Memory Commands ECON VALUE COMMAND DESCRIPTION NORMAL MODE Power On Default COMMAND DESCRIPTION ULOAD MODE 01H READ 02H WRITE 03H 04H VERIFY 05H ERASE PAGE 06H ERASE ALL 81H READBYTE 82H WRITEBYTE EXULOAD FOH ULOAD Results in four bytes in the Flash EE data memory addressed by the page address EADRHIL being read into EDATA 1 to 4 Results in four bytes in EDATA1 4 being written to the Flash EE data memory at the page address given by EADRH L 0 lt EADRH L lt 0400H Note The four bytes in the page being addressed must be pre erased Reserved Command Verifies if the data in EDATAI 4 is contained in the page address given by EADRH L A subsequent read of the ECON SFR will result in a 0 being read if the verification is valid or a nonzero value being read to indicate an invalid verification Results in the Erase of the 4 byte page of Flash EE data memory addressed by the page address EADRH L Results in the erase of entire 4 kBytes of Flash EE data memory Results in the byte in the Flash EE data memory addressed by the byte address EADRH L being read into EDATAI 0 lt EADRH L lt 0FFFH Results the byte in EDATAI being written into Flash EE data memory at the byte address EADRH L Leaves the ECON instructions to operate on the Flash EE data
4. ALE 0 TxD OUTPUT CLOCK RxD OUTPUT DATA AU Figure 73 UART Timing in Shift Register Mode RxD INPUT DATA REV 0 71 ADuC832 Parameter Min Max Unit Figure COMPATIBLE INTERFACE TIMING tL SCLOCK Low Pulsewidth 4 7 us 74 tH SCLOCK High Pulsewidth 4 0 us 74 tsuD Start Condition Hold Time 0 6 us 74 tpsu Data Setup Time 100 us 74 tDHD Data Hold Time 0 9 us 74 trsu Setup Time for Repeated Start 0 6 us 74 tpsu Stop Condition Setup Time 0 6 us 74 Bus Free Time between STOP Condition 1 3 us 74 and a START Condition tR Rise Time of Both SCLOCK and SDATA 300 ns 74 Fall Time of Both SCLOCK and SDATA 300 ns 74 Pulsewidth of Spike Suppressed 50 ns 74 Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns teur 4 2 4 zl SDATA 1 1 SCLK I Lal lp 1 1 1 1 1 1 1 ipsu gt 1 1 1 1 L PS START CONDITION CONDITION u Figure 74 12 Compatible Interface Timing 72 1 1568 REPEATED START REV 0 ADuC832 Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING CPHA 1 tsi SCLOCK Low Pulsewidth 476 ns 75 SCLOCK High Pulsewidth 416 ns 75 tpav Data Output Valid after SCLOCK Edge 50 ns 75 Data Input Set
5. MOV ADCCON2 00H MOV ADCCON3 25H select external AGND select offset calibration 31 averages per bit 26 To calibrate system gain Connect system Vggg to an ADC channel input 1 MOV ADCCON2 01H MOV 27H select external select offset calibration 31 averages per bit offset calibration The calibration cycle time is calculated by the following equation 14x ADCCLK x NUMAV x 16 Taco For an ADCCLK F cope divide ratio of 16 a 4 ADCCLK NUMAV 15 the calibration cycle time is Toa 14 x 1 1048576 15 x 16 4 4 2 ms In a calibration cycle the ADC busy flag Bit 7 instead of framing an individual ADC conversion as in normal mode will go high at the start of calibration and only return to zero at the end of the calibration cycle It can therefore be monitored in code to indicate when the calibration cycle is completed The following code can be used to monitor the BUSY signal during a calibration cycle WAIT MOV A ADCCON3 JB ACC 7 WAIT move ADCCON3 to A If Bit 7 is set jump to WAIT else continue REV 0 ADuC832 NONVOLATILE FLASH EE MEMORY Flash EE Memory Overview The ADuC832 incorporates Flash EE memory technology on chip to provide the user with nonvolatile in circuit repro grammable code and data memory space Flash EE memory is a relatively recent type of nonvolatile memory technology and is base
6. digitization process the more levels the smaller the quantization noise The theoretical signal to noise distortion ratio for an ideal N bit converter with a sine wave input is given by Signal to Noise Distortion 6 02 1 76 dB Thus for a 12 bit converter this is 74 dB Total Harmonic Distortion Total Harmonic Distortion is the ratio of the rms sum of the harmonics to the fundamental DAC SPECIFICATIONS Relative Accuracy Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function It is measured after adjusting for zero error and full scale error Voltage Output Settling Time This is the amount of time it takes for the output to settle to a specified level for a full scale input change Digital to Analog Glitch Impulse This is the amount of charge injected into the analog output when the inputs change state It is specified as the area of the glitch in nV sec REV 0 Typical Performance Characteristics ADuC832 The typical performance plots presented in this section illustrate typical performance of the ADuC832 under various operating conditions TPC 1 and TPC 2 show typical ADC Integral Nonlinearity INL errors from ADC code 0 to code 4095 at 5 V and 3 V supplies respectively The ADC is using its internal reference 2 5 V and operating at a sampling rate of 152 kHz and the typically worst case errors in b
7. 1 or Disable 0 Power Supply Monitor Interrupt 0 ESI Written by User to Enable 1 or Disable 0 SPI or Serial Port Interrupt 60 0 ADuC832 Interrupt Priority The Interrupt Enable registers are written by the user to enable individual interrupt sources while the Interrupt Priority registers allow the user to select one of two priority levels for each interrupt An interrupt of a high priority may interrupt the service routine of a low priority interrupt and if two interrupts of different priority occur at the same time the higher level interrupt will be serviced first An interrupt cannot be interrupted by another interrupt of the same priority level If two interrupts of the same priority level occur simultaneously a polling sequence is observed as shown in Table XXXII Table XXXII Priority within an Interrupt Level Source Priority Description PSMI 1 Highest Power Supply Monitor Interrupt WDS 2 Watchdog Timer Interrupt IEO 2 External Interrupt 0 ADCI 3 ADC Interrupt TFO 4 Timer Counter 0 Interrupt 5 External Interrupt 1 6 Timer Counter 1 Interrupt ISPI I2CI 7 SPI Interrupt I C Interrupt RI TI 8 Serial Interrupt TF2 EXF2 9 Lowest Timer Counter 2 Interrupt TII 11 Lowest Time Interval Counter Interrupt Interrupt Vectors When an interrupt occurs the program counter is pushed onto the stack and the corresponding interrupt vector addre
8. The complete parallel programming specification is available on the MicroConverter home page at www analog com microconverter 3 User Download Mode ULOAD In Figure 19 we can see that it was possible to use the 62 kBytes of Flash EE program memory available to the user as one single block of memory In this mode all of the Flash EE memory is read only to user code However the Flash EE program memory can also be written to during runtime simply by entering ULOAD mode In ULOAD mode the lower 56 kBytes of program memory can be erased and reprogrammed by user software as shown in Figure 19 ULOAD mode can be used to upgrade your code in the field via any user defined download protocol Configuring the SPI port on the ADuC832 as a slave it is possible to completely reprogram the 56 kBytes of Flash EE program memory in only 5 seconds see uC007 Alternatively ULOAD mode can be used to save data to the 56 kBytes of Flash EE memory This can be extremely useful in data logging applications where the ADuC832 can provide up to 60 kBytes of NV data memory on chip 4 kBytes of dedicated Flash EE data memory also exist The upper 6 kBytes of the 62 kBytes of Flash EE program memory is only programmable via serial download or parallel programming This means that this space appears as read only to user code Therefore it cannot be accidently erased or repro grammed by erroneous code execution This makes it very suitable to use the 6 kByt
9. 0 DVpp ALTERNATE READ OUTPUT INTERNAL LATCH FUNCTION PULL UP INTERNAL BUS WRITE TO LATCH READ n SEE FIGURE 39 FOR DETAILS OF FUNCTION INTERNAL PULL UP Figure 40 Port 3 Bit Latch and I O Buffer Additional Digital I O In addition to the port pins the dedicated pins SCLOCK and SDATA MOST also feature both input and output functions Their equivalent I O architectures are illustrated in Figure 41 and Figure 43 respectively for SPI operation and in Figure 42 and Figure 44 for operation Notice that in mode SPE 0 the strong pull up FET Q1 is disabled leaving only a weak pull up Q2 present By contrast in SPI mode SPE 1 the strong pull up FET Q1 is controlled directly by SPI hardware giving the pin push pull capability In PC mode SPE 0 two pull down FETs Q3 and Q4 operate in parallel in order to provide an extra 60 or 70 of current sinking capability In SPI mode however SPE 1 only one of the pull down FETs Q3 operates on each pin resulting in sink capabilities identical to that of Port 0 and Port 2 pins On the input path of SCLOCK notice that a Schmitt trigger conditions the signal going to the SPI hardware to prevent false triggers double triggers on slow incoming edges For incoming signals from the SCLOCK and SDATA pins going to PC hard ware a filter conditions the signals in order to reject glitches of up to 50 ns in duration Notice also that
10. 40 ns 70 TAVLL Address Valid to ALE Low 19 40 ns 70 LLAX Address Hold after ALE Low 29 30 ns 70 rv ALE Low to Valid Instruction In 138 4tck 100 ns 70 ALE Low to PSEN Low 29 tcx 30 ns 70 PSEN Pulsewidth 133 45 ns 70 PSEN Low to Valid Instruction In 73 3tcx 105 ns 70 tpxix Input Instruction Hold after PSEN 0 0 ns 70 tPXIZ Input Instruction Float after PSEN 34 tck 25 ns 70 tAVIV Address to Valid Instruction In 193 5tck 105 ns 70 7 PSEN Low to Address Float 25 25 ns 70 Address Hold after PSEN High 0 0 ns 70 ALE 0 tpi pn PSEN 0 PORT 2 0 Figure 70 External Program Memory Read Cycle 68 REV 0 ADuC832 16 78 MHz Core CIk Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth 257 100 ns 71 tavLL Address Valid after ALE Low 19 40 ns 71 Address Hold after ALE Low 24 tcx 35 ns 71 RD Low to Valid Data __ 133 165 ns 71 Data and Address Hold after RD 0 0 ns 71 tRHDZ Data Float after RD 49 2tcx 70 ns 71 ALE Low to Valid Data In 326 8 150 ns 71 tavpv Address to Valid Data In 371 91 165 ns 71 LWL ALE Low to RD or WR Low 128 228 50 50 ns 11 taywL Address Valid to RD or WR Low 108 130 ns 71 tRIAZ RD Low to Address Float 0 0 ns 71 twHLH RD or WR Hi
11. Data High Byte gt DACIH DACI Data High Byte 00H All Four Registers No All Four Registers FBH FCH The 12 bit DAC data should be written into DACxH L right justified such that DACxL contains the lower eight bits and the lower nibble of DACxH contains the upper four bits 32 REV 0 ADuC832 Using the DAC The on chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier the functional equivalent of which is illustrated in Figure 21 Details of the actual DAC architecture can be found in U S Patent Number 5969657 www uspto gov Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity ADuC832 AVpp gt VREF OUTPUT BUFFER HIGH 2 DISABLE FROM MCU Figure 21 Resistor String DAC Functional Equivalent As illustrated in Figure 21 the reference source for each DAC is user selectable in software It can be either AVpp or In 0 to AVpp mode the DAC output transfer function spans from 0 V to the voltage at the AVpp pin In 0 to Vggg mode the DAC output transfer function spans from 0 V to the internal or if an external reference is applied the voltage at the pin The DAC output buffer amplifier features a true rail to rail output stage implementation This means that unloaded each output is capable of swinging to within less than 100 mV of both AVpp and ground Moreo
12. In Mode 5 the duty cycle of the PWM outputs and the resolution of the PWM outputs are individually programmable The maxi mum resolution of the PWM output is eight bits The output resolution is set by the PVMIL and PWM1H SFRs for the P2 6 and P2 7 outputs respectively PWMOL and PWMOH sets the duty cycles of the PWM outputs at P2 6 and P2 7 respectively Both PWMs have same clock source and clock divider 38 PWM1L PWM COUNTERS Figure 31 PWM Mode 5 MODE 6 Dual RZ 16 Bit DAC Mode 6 provides a high speed PWM output similar to that of a A DAC Mode operates very similarly to Mode 4 However the key difference is that Mode 6 provides return to zero RZ A DAC output Mode 4 provides non return to zero DAC outputs The RZ mode ensures that any difference in the rise and fall times will not effect the X A DAC INL However the RZ mode halves the dynamic range of the X A DAC outputs from 0 AVpp down to 0 AVpp 2 For best results this mode should be used with a PWM clock divider of four If PWMIH was set to 4010H slightly above one quarter of FS then typically P2 7 will be low for three full clocks 3 X 60 ns high for half a clock 30 ns and then low again for half a clock 30 ns before repeating itself Over every 65536 clocks the PWM will compensate for the fact that the output should be slightly above one quarter of full scale by leaving the output high for two half clocks in four
13. OFFAH BYTE 2 2 OFF9H BYTE 4 oFFFH BYTE 4 OFFCH BYTE 1 the interface to this memory space is via a group of registers pd Ld E mapped in the SFR space A group of four data registers Ed Fg I EDATA1 4 are used to hold the four bytes of data at each as page The page is addressed via the two registers EADRH and 5 5 03H Finally ECON is an 8 control register that may be 02H written with one of nine Flash EE memory access commands to trigger various read write erase and verify functions A block diagram of the SFR interface to the Flash EE data memory array is shown in Figure 20 g EE E u ECON Flash EE Memory Control SFR ADDRESSES NEM Programming of either the Flash EE data memory or the Flash EE AREGIVENIN E E BRACKETS lt um x program memory is done through the Flash EE memory control ug I og SFR ECON This SFR allows the user to read write erase or verify the 4 kBytes of Flash EE data memory or the 56 kBytes of Flash EE program memory BYTE 1 BYTE 2 BYTE 3 BYTE 4 0004H 0005H 0006H 0007H BYTE 1 BYTE 2 BYTE 3 BYTE 4 0008H 0009H 1 000 000BH r
14. as short as possible Connect the ground terminal of each of these capacitors directly to the underlying ground plane Finally REV 0 it should also be noted that at all times the analog and digital ground pins on the ADuC832 must be referenced to the same system ground reference point Power Consumption The currents consumed by the various sections of the ADuC832 are shown in Table XXXIV The Core values given represent the current drawn by DVpp while the rest ADC DAC voltage ref are pulled by the AVpp pin and can be disabled in software when not in use The other on chip peripherals watchdog timer power supply monitor and so on consume negligible current and are therefore lumped in with the Core operating current here Of course the user must add any currents sourced by the parallel and serial I O pins and sourced by the DAC in order to deter mine the total current needed at the ADuC832 s supply pins Also current drawn from the DVpp supply will increase by approximately 10 mA during Flash EE erase and program cycles Table XXXIV Typical Ipp of Core and Peripherals Vpp 25V Vpp 23V Core Normal Mode 1 6 nAs X 0 8 nAs X 6mA 3mA Core Idle Mode 0 75 nAs X 0 25 nAs X 5 mA 3mA ADC 1 3 mA 1 0 mA DAC Each 250 uA 200 uA Voltage Ref 200 uA 150 uA Since operating DVpp current is primarily a function of clock speed the expressions for Core supply curren
15. compatible with 12 core clock periods per machine cycle 62 kBytes of nonvolatile Flash EE program memory are provided on chip 4 kBytes of nonvolatile Flash EE data memory 256 bytes RAM and 2 kBytes of extended RAM are also integrated on chip The ADuC832 also incorporates additional analog functionality with two 12 bit DACs power supply monitor and a band gap reference On chip digital peripherals include two 16 bit X A DACs dual output 16 bit PWM watchdog timer time interval counter three timers counters Timer 3 for baud rate generation and serial I O ports SPI and UART On chip factory firmware supports in circuit serial download and debug modes via UART as well as single pin emulation mode via the EA pin The ADuC832 is supported by QuickStart and QuickStart Plus development systems featuring low cost software and hardware development tools A functional block diagram of the ADuC832 is shown above with a more detailed block diagram shown in Figure 1 The part is specified for 3 V and 5 V operation over the extended industrial temperature range and is available in a 52 lead plastic quad flatpack package and a 56 lead chip scale package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2002 All rights reserved ADuC832 TABLE OF CONTENTS FEATURES 1 Using the Flash EE Data Memory 29 E
16. the core resumes code execution at the core clock selected by the CD2 0 bits Cleared by user to disable the fast interrupt response feature 2 CD2 CPU Core Clock Divider Bits 1 CD1 This number determines the frequency at which the microcontroller core will operate 0 2 CDI Core Clock Frequency MHz 0 0 0 16 777216 0 0 1 8 388608 0 1 0 4 194304 0 1 1 2 097152 Default Core Clock Frequency 1 0 0 1 048576 1 0 1 0 524288 1 1 0 0 262144 1 1 1 0 131072 REV 0 35 ADuC832 PULSEWIDTH MODULATOR PWM The PWM on the ADuC832 is a highly flexible PWM offering programmable resolution and an input clock and can be config ured for any one of six different modes of operation Two of these modes allow the PWM to be configured as a A DAC with up to 16 bits of resolution A block diagram of the PWM is shown in Figure 26 fvco TO EXTERNAL PWM CLOCK 1 1 15 3 CLOCK PROGRAMMABLE SELECT D IVIDER 16 BIT PWM COUNTER fxraL Figure 26 PWM Block Diagram The PWM uses five SFRs the control SFR PWMCON and four data SFRs PWMOH PWMOL PWM1H and PWMIL PWMCON as described below controls the different modes of operation of the PWM as well as the PWM clock frequency PWMOH L and are the data registers that deter mine the duty cycles of the PWM outputs The output pins that the PWM uses are determined by the CFG832 register and can be either P2 6 and P2 7 or P3 4 and P3 3 In t
17. 1 16 x Timer 2 Overflow Rate Therefore when Timer 2 is used to generate baud rates the timer increments every two clock cycles and not every core machine cycle as before Thus it increments six times faster than Timer 1 and therefore baud rates six times faster are possible Because Timer 2 has 16 bit autoreload capability very low baud rates are still possible Timer 2 is selected as the baud rate generator by setting the TCLK and or RCLK in T2CON The baud rates for transmit and receive can be simultaneously different Setting RCLK and or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 53 In this case the baud rate is given by the formula Modes 1 and 3 Baud Rate 32 x 65536 RCAP2H RCAP2L Table XXVI shows some commonly used baud rates and how they might be calculated from a core clock frequency of 16 78 MHz and 2 10 MHz Table XXVI Commonly Used Baud Rates Timer 2 Core Ideal CLK RCAP2H RCAP2L Actual Baud MHz Value Value Baud Error 19200 16 78 1 FFH 27 E5H 19418 1 14 9600 16 78 1 55 C9H 9532 0 7 2400 16 78 1 FFH 218 26H 2405 0 21 1200 16 78 2 181 4BH 1199 0 02 9600 2 10 1 FFH 7 9362 24 2400 2 10 1 FFH 27 2427 1 14 1200 2 10 1 55 COH 1191 0 7 8 BITS TL2 TH2 TIMER 1 OVERFLOW
18. 60 70 FREQUENCY kHz TPC 11 Dynamic Performance at Vpp 5 V AVpp DVpp fs 149 79kHz fin 9 910kHz SNR 71 0dB THD 83 0dB ENOB 11 5 FREQUENCY kHz TPC 12 Dynamic Performance at Vpp 3 V AVpp DVpp 5V fg 152kHz SNR SNR dBs 100 0 5 1 0 1 5 2 0 2 5 5 0 EXTERNAL REFERENCE V TPC 13 Typical Dynamic Performance vs Vper 5 V REV 0 THD dBs SNR dBs ADuC832 AV pp DVpp fs 152kHz SNR THD dBs 100 0 5 1 0 1 5 2 0 2 5 3 0 EXTERNAL REFERENCE V TPC 14 Typical Dynamic Performance vs V AVpp DVpp 5V 119 05 145 83 172 62 199 41 226 19 FREQUENCY kHz SNR dBs 65 476 92 262 TPC 15 Typical Dynamic Performance vs Sampling Frequency AVpp DVpp SLOPE 2mV C VOLTAGE V 40 20 0 25 50 85 TEMPERATURE C TPC 16 Typical Temperature Sensor Output vs Temperature ADuC832 MEMORY ORGANIZATION The ADuC832 contains four different memory blocks 62 kBytes of On Chip Flash EE Program Memory 4 kBytes of On Chip Flash EE Data Memory 256 Bytes of General Purpose RAM 2 kBytes of Internal XRAM Flash EE Program Memory The ADuC832 provides 62 kBytes of Flas
19. 7 Gate Timer 1 Gating Control Set by software to enable Timer Counter 1 only while INT1 pin is high and TRI control bit is set Cleared by software to enable Timer 1 whenever TRI control bit is set 6 C T Timer 1 Timer or Counter Select Bit Set by software to select counter operation input from T1 pin Cleared by software to select timer operation input from internal system clock 5 MI Timer 1 Mode Select Bit 1 Used with MO Bit 4 Timer 1 Mode Select Bit 0 MI MO 0 0 operates as an 8 bit timer counter TL1 serves as 5 bit prescaler 0 1 16 Bit Timer Counter TH1 and TL1 are cascaded there is no prescaler 1 0 8 Bit Auto Reload Timer Counter TH1 holds a value that is to be reloaded into TL1 each time it overflows 1 1 Timer Counter 1 Stopped 3 Gate Timer 0 Gating Control Set by software to enable timer counter 0 only while INTO pin is high and TRO control bit is set Cleared by software to enable Timer 0 whenever TRO control bit is set 2 C T Timer 0 Timer or Counter Select Bit Set by software to select counter operation input from TO pin Cleared by software to select timer operation input from internal system clock 1 1 Timer 0 Mode Select 1 Timer 0 Mode Select Bit 0 MI MO 0 0 THO operates as an 8 bit timer counter TLO serves as a 5 bit prescaler 0 1 16 Bit Timer Counter THO and TLO are cascaded there is no prescaler 1 0 8 Bit Auto Reload Timer Counter THO holds a value that is to be reloaded into TL
20. ADC should be configured to use an ADCCLK of MCLK 32 and four acquisition clocks Increasing the conversion time on the temperature monitor channel improves the accuracy of the reading T o further improve the accuracy an external reference with low temperature drift should also be used ADC DMA Mode The on chip ADC has been designed to run at a maximum conversion speed of 4 us 247 kHz sampling rate When converting at this rate the ADuC832 MicroConverter has 4 us to read the ADC result and store the result in memory for fur ther postprocessing otherwise the next ADC sample could be lost In an interrupt driven routine the MicroConverter would also have to jump to the ADC Interrupt Service routine which will also increase the time required to store the ADC results In applications where the ADuC832 cannot sustain the interrupt rate an ADC DMA mode is provided To enable DMA mode Bit 6 in ADCCON2 DMA must be set This allows the ADC results to be written directly to a 16 MByte external static memory SRAM mapped into data memory space without any interaction from the ADuC832 core This mode allows the ADuC832 to capture a contiguous sample stream at full ADC update rates 247 kHz A Typical DMA Mode Configuration Example To set the ADuC832 into DMA mode a number of steps must be followed 1 The ADC must be powered down This is done by ensuring and MDO are both set to 0 in ADCCONI 2 The DMA address pointer mus
21. ADC readings averaged during a calibration cycle AVGSI AVGSO Number of Averages 0 0 15 0 1 1 1 0 31 1 1 63 ADCCON3 3 RSVD Reserved This bit should always be written as 0 ADCCON3 2 RSVD This bit should always be written as 1 by the user when performing calibration ADCCON3 1 TYPICAL Calibration Type Select Bit This bit selects between Offset zero scale and Gain full scale calibration Set to 0 for Offset Calibration Set to 1 for Gain Calibration ADCCON3 0 SCAL Start Calibration Cycle Bit When set this bit starts the selected calibration cycle It is automatically cleared when the calibration cycle is completed REV 0 21 ADuC832 Driving the A D Converter The ADC incorporates a successive approximation SAR archi tecture involving a charge sampled input stage Figure 9 shows the equivalent circuit of the analog input section Each ADC conversion is divided into two distinct phases as defined by the position of the switches in Figure 9 During the sampling phase with SW1 SW2 in the track position a charge propor tional to the voltage on the analog input is developed across the input sampling capacitor During the conversion phase with both switches in the hold position the capacitor DAC is adjusted via internal SAR logic until the voltage on node A is Zero indicating that the sampled charge on the input capacitor is balanced out by the charge being output by th
22. CiH con 10H 2XH 1 PSI PADC PT2 PS PT1 PX1 PTO PXO BITS IP ECON RESERVED RESERVED EDATA1 EDATA2 EDATA3 EDATA4 0 BEH 0 0 B9H 0 sn en BEH 00H PWMOL PWMOH PWMiL PWM1H SPH RD WR Ti TO INTO TxD RxD N NOTIUSED NOFUSED 1 BeH 1 BsH 1 1 BsH 1 1 BiH 1 1 B2H o0H B4H IE IEIP2 PWMCON CFG832 EA EADC ET2 ES EXN JETO RESERVED RESERVED RESERVED RESERVED 0 0 O ACH 0 AAH O A9H O A8H BITS P2 TIMECON HTHSEC SEC MIN HOUR INTVAL DPCON 1 1 A5H 1 A4H 1 1 A2H 1 A1H 1 AO0H 1 AiH A2H ASH 00H A7H SCON SBUF I2CDAT I2CADD T3FD T3CON smo 1 su2 REN TB8 RI BITS 0 9DH Z san oon eBH 55H hl EH 1 2 2 2 SY Pt NOT USED NOTUSED NOT USED NOT USED NOT USED NOT USED NOT USED 97H 1 96H 1 95H 1 o4H 1 osH 1 s2H 1 9 1 1 TF1 TR1 TFO TRO IE1 IT IEO ITO BITS TCON TMOD TLO TL1 THO RESE
23. Input Output Synchronous of Serial UART Port TxD O Transmitter Data Output Asynchronous or Clock Output Synchronous of Serial UART Port INTO I Interrupt 0 programmable edge or level triggered Interrupt input can be programmed to one of two priority levels This pin can also be used as a gate control input to Timer 0 INTI I Interrupt 1 programmable edge or level triggered Interrupt input can be programmed to one of two priority levels This pin can also be used as a gate control input to Timer 1 TO I Timer Counter 0 Input 1 1 Timer Counter 1 Input CONVST I Active Low Convert Start Logic Input for the ADC Block when the External Convert Start Function is enabled A low to high transition on this input puts the track and hold into its hold mode and starts conversion EXTCLK I Input for External Clock Signal has to be enabled via CFG832 Register WR Write Control Signal Logic Output Latches the data byte from Port 0 into the external data memory RD Read Control Signal Logic Output Enables the external data memory to Port 0 XTAL2 Output of the Inverting Oscillator Amplifier XTALI I Input to the Inverting Oscillator Amplifier DGND G Digital Ground Ground reference point for the digital circuitry P2 0 P2 7 IO Port 2 is a bidirectional port with internal pull up resistors Port 2 pins that have 1s written to them are A8 A15 pulled high by the internal pull up resistors and in that state can be used as inputs As i
24. P1 3 ADC3 4 P1 4 ADCA 11 P1 5 ADC5 SS 12 P1 6 ADC6 13 nf PIN CONFIGURATION hows lt lt lt lt lt 52 51 49 fas 45 44 43 39 P2 7 PWM1 A15 A23 38 P2 6 PWM0 A14 A22 P2 5 A13 A21 36 P2 4 A12 A20 35 DGND 34 DVpp 33 XTAL2 32 XTAL1 31 P2 3 A11 A19 30 P2 2 A10 A18 29 P2 1 A9 A17 28 P2 0 A8 A16 SDATA MOSI PIN 1 IDENTIFIER ADuC832 52 LEAD PQFP TOP VIEW Not to Scale NE lo a SERRESSESGERS OYVGCEESAZOOSSRO fuser SFOREZSRY RE GG SS PO lt Sead Wijoa gq e SEED g 5 c E 58 5 e Bo e P1 1 ADC1 T2EX P1 2 ADC2 P1 3 ADC3 AVpp AVpp AGND AGND AGND CREF VREF DACO DAC1 P1 4 ADC4 P1 5 ADC5 SS ADuC832 ADC CONTROL AND CALIBRATION 62 KBYTES PROGRAM FLASH EE INCLUDING USER DOWNLOAD MODE 2 x DATA POINTERS 11 BIT STACK POINTER DOWNLOADER DEBUGGER ASYNCHRONOUS SERIAL PORT RESET N E e o a 5 P0 3 AD3 NN P2 7 PWM1 A15 A23 P2 6 PWMO0 A14 A22 2 5 13 21 P2 4 A12 A20 PIN 1 IDENTIFIER ADuC832 56 LEAD CSP TOP VIEW Not to Scale P2 3 A11 A19 P2 2 A10 A18 2 1 9 17 2 0 8 16 ed DJ SDATA MOSI N QW a sm LL on lt
25. The write to SBUF signal also loads a 1 stop bit into the ninth bit position of the transmit shift register The data is output bit by bit until the stop bit appears on TxD and the transmit interrupt flag TT is automatically set as shown in Figure 52 START STOP BIT X os SCON 1 h SET INTERRUPT I E READY FOR MORE DATA Figure 52 UART Serial Port Transmission Mode 0 Reception is initiated when a 1 to 0 transition is detected on RxD Assuming a valid start bit was detected character reception continues The start bit is skipped and the eight data bits are clocked into the serial port shift register When all eight bits have been clocked in the following events occur The eight bits in the receive shift register are latched into SBUF The ninth bit Stop bit is clocked into RB8 in SCON The Receiver Interrupt flag RI is set This will be the case if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or SM2 1 and the received stop bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set REV 0 Mode 2 9 Bit UART with Fixed Baud Rate Mode 2 is selected by setting SMO and clearing SM1 In this mode the UART operates in 9 bit mode with a fixed baud rate The baud rate is fixed at Core_Clk 64 by default although by setting the SMO
26. This external buffer should be located as near as physically possible to the DAC output pin on the PCB Note that the unbuffered mode only works in the 0 to range 34 drive significant loads with the DAC outputs external buff ering may be required even with the internal buffer enabled as illustrated in Figure 25 A list of recommended op amps is in Table VI ADuC832 Figure 25 Buffering the DAC Outputs The DAC output buffer also features a high impedance disable function In the chip s default power on state both DACs are disabled and their outputs are in a high impedance state or three state where they remain inactive until enabled in software This means that if a zero output is desired during power up or power down transient conditions then a pull down resistor must be added to each DAC output Assuming this resistor is in place the DAC outputs will remain at ground potential whenever the DAC is disabled REV 0 ADuC832 ON CHIP PLL The ADuC832 is intended for use with a 32 768 kHz watch crystal A PLL locks onto a multiple 512 of this to provide a stable 16 78 MHz clock for the system The core can operate at this frequency or at binary submultiples of it to allow power saving in cases where maximum core performance is not required The default core clock is the PLL clock divided by 8 or 2 097152 MHz The ADC clocks are also derived from the PLL clock with the modulator rate being the
27. Time 10 25 ns 78 tposs Data Output Valid after SS Edge 20 ns 78 tsrs SS High after SCLOCK Edge ns 78 tss tsrs lt SCLOCK CPOL 0 te tsr tsp CPOL 1 MISO MOSI ipsu Figure 78 SPI Slave Mode Timing CPHA 0 76 REV 0 REV 0 SEATING PLANE INDICATOR OUTLINE DIMENSIONS 52 Lead Plastic Quad Flatpack MQFP S 52 Dimensions shown in millimeters 14 15 13 90 SQ MA 13 65 39 27 40 26 4 10 20 7 80 TOP VIEW EUM REF PINS DOWN 10 00 SQ 9 80 PIN 1 52109 14 13 0 65 lt 0 38 22 210 2 AERA 2 00 o 1 95 0 10 MIN VIEW A COPLANARITY ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MO 112 AC 1 56 Lead Frame Chip Scale Package LFCSP 8 X 8 mm Body CP 56 Dimensions shown in millimeters PIN 1 INDICATOR 7 75 BSC SQ gt 050 BS SEATING PLANE 0 70 MAX 0 65 NOM COPLANARITY 0 08 COMPLIANT TO JEDEC STANDARDS MO 220 VLLD 2 27 7 ADuC832 78 79 0 Z0 L 1L 0 86202 WS N NI GALNIYd 80
28. Typically this will be set to 255 FFH to give an 8 bit PWM although it is pos sible to reduce this as necessary A value of 100 could be loaded here to give a percentage PWM the PWM is accurate to 1 The outputs of the PWM at P2 6 and P2 7 are shown in Figure 28 As can be seen the output of PWMO P2 6 goes low when the PWM counter equals PWMOL The output of PWM1 P2 7 goes high when the PWM counter equals PVMIH and goes low again when the PWM counter equals PWMOH Setting PWM1H to 0 ensures that both PWM outputs start simultaneously REV 0 PWMiL PWM COUNTER Figure 28 PWM Mode 2 MODE 3 Twin 16 Bit PWM In Mode 3 the PWM counter is fixed to count from 0 to 65536 giving a fixed 16 bit PWM Operating from the 16 777 MHz core clock results in a PWM output rate of 256 Hz The duty cycle of the PWM outputs at P2 6 and P2 7 is independently programmable As shown in Figure 29 while the PWM counter is less than PWMOHIL the output of PWMO P2 6 is high Once the PWM counter equals PWMOH L P2 6 goes low and remains low until the PWM counter rolls over Similarly while the PWM counter is less than PVMIH L the output of PWM1 P2 7 is high Once the PWM counter equals PWMIH L PWMI P2 7 goes low and remains low until the PWM counter rolls over In this mode both PWM outputs are synchronized i e once the PWM counter rolls over to 0 both PWMO P2 6 and PWMI P2 7 will
29. User to Enable 1 or Disable 0 Timer 0 Interrupt 0 Written by User to Enable 1 or Disable 0 External Interrupt 0 IP Interrupt Priority Register SFR Address B8H Power On Default Value 00H Bit Addressable Yes Table XXX IP SFR Bit Designations Bit Name Description 7 Reserved Future Use 6 PADC Written by User to Select ADC Interrupt Priority 1 High 0 Low 5 PT2 Written by User to Select Timer 2 Interrupt Priority 1 High 0 Low 4 PS Written by User to Select UART Serial Port Interrupt Priority 1 High 0 Low 3 PTI Written by User to Select Timer Interrupt Priority 1 High 0 Low 2 PXI Written by User to Select External Interrupt 1 Priority 1 High 0 Low 1 PTO Written by User to Select Timer 0 Interrupt Priority 1 High 0 Low 0 Written by User to Select External Interrupt 0 Priority 1 High 0 Low IEIP2 Secondary Interrupt Enable Register SFR Address A9H Power On Default Value Addressable Table XXXI IEIP2 SFR Designations Bit Name Description 7 Reserved for Future Use 6 PTI Priority for Time Interval Interrupt 5 PPSM Priority for Power Supply Monitor Interrupt 4 PSI Priority for SPI I C Interrupt This Bit Must Contain Zero 2 ETI Written by User to Enable 1 or Disable 0 Time Interval Counter Interrupt 1 EPSMI Written by User to Enable
30. direct access to the SCLOCK and SDATA MOSI pins is afforded through the SFR interface in PC master mode Therefore if you are not using the SPI or functions you can use these two pins to give additional high current digital outputs DVpp SPE 1 SPI ENABLE HARDWARE SPI MASTER SLAVE Figure 41 SCLOCK Pin I O Functional Equivalent in SPI Mode SCLOCK PIN SCHMITT TRIGGER 49 ADuC832 SPE 0 12 ENABLE HARDWARE 2C SLAVE ONLY 50ns GLITCH REJECTION FILTER DVpp Figure 42 SCLOCK Pin I O Functional Equivalent Mode DVpp SPE 1 SPI ENABLE HARDWARE SPI MASTER SLAVE Figure 43 SDATA MOSI Pin I O Functional Equivalent in SPI Mode DVpp SPE 0 12 ENABLE 50ns GLITCH REJECTION FILTER Figure 44 SDATA MOSI Pin I O Functional Equivalent Mode MISO is shared with P3 3 and as such has the same configuration as that shown in Figure 40 These instructions read the port byte all 8 bits modify the addressed bit and then write the new byte back to the latch 50 Read Modify Write Instructions Some 8051 instructions that read a port read the latch while others read the pin The instructions that read the latch rather than the pins are the ones that read a value possibly change it and then rewrite it to the latch These are called read modify write instructions Listed below are the read modify write instruct
31. function input from on chip core clock 0 CAP2 Timer 2 Capture Reload Select Bit Set by the user to enable captures on negative transitions at 2 if EXEN2 1 Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to autoreload on Timer 2 overflow Timer Counter 2 Data Registers Timer Counter 2 also has two pairs of 8 bit data registers associated with it These are used as both timer data registers and timer capture reload registers TH2 and TL2 Timer 2 data high byte and low byte SFR Address CDH CCH respectively RCAP2H and RCAP2L Timer 2 Capture Reload byte and low byte SFR Address CBH CAH respectively 54 REV 0 ADuC832 Timer Counter Operation Modes The following paragraphs describe the operating modes for Timer Counter 2 The operating modes are selected by bits in the T2CON SFR as shown in Table XXIII Table XXIII T2CON Operating Modes RCLK or TCLK CAP2 TR2 Mode 0 0 1 16 Bit Autoreload 0 1 1 16 Bit Capture 1 X 1 Baud Rate X X 0 OFF 16 Bit Autoreload Mode In Autoreload mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2L and RCAP2H which are preset by s
32. is used to implement a master receiver interface in software Data on the SDATA pin is latched into this bit on SCLOCK if the Data Output Enable MDE bit is 0 3 I2CM Master Slave Mode Bit Set by user to enable software master mode Cleared by user to enable hardware slave mode 2 I2CRS Reset Bit Slave Mode Only Set by user to reset the interface Cleared by user code for normal operation 1 I2CTX Direction Transfer Bit Slave Mode Only Set by the MicroConverter if the interface is transmitting Cleared by the MicroConverter if the interface is receiving 0 I2CI Interrupt Bit Slave Mode Only Set by the MicroConverter after a byte has been transmitted or received Cleared automatically when user code reads the I2CDAT SFR see I2CDAT below DCADD Address Register Function Holds the peripheral address for the part It may be overwritten by user code Technical Note uC001 at www analog com microconverter describes the format of the standard 7 bit address in detail SFR Address 9BH Power On Default Value 55H Bit Addressable No DCDAT Data Register Function The I2CDAT SFR is written by the user to transmit data over the interface or read by user code to read data just received by the interface Accessing I2CDAT automatically clears any pending interrupt and the I2CI bit in the I2CCON SFR User software should only access I2CDAT onc
33. oscillator can also be enabled during power down All other on chip peripherals however are shut down Port pins retain their logic levels in this mode but the DAC output goes to a high impedance state three state During full power down mode the ADuC832 consumes a total of approximately 20 uA There are five ways of terminating power down mode Asserting the RESET pin Pin 15 Returns to normal mode All registers are set to their default state and program execution starts at the reset vector once the Reset pin is deasserted Cycling Power All registers are set to their default state and program execution starts at the reset vector approximately 128 ms later Time Interval Counter TIC Interrupt Power down mode is terminated and the CPU services the TIC interrupt The RETI at the end of the TIC ISR will return the core to the instruction after the one that enabled power down SPI Interrupt Power down mode is terminated and the CPU services the interrupt The RETI at the end of the ISR will return the core to the instruction after the one that enabled power down It should be noted that the 2 8 power down interrupt enable bit SERIPD in the PCON SFR must first be set to allow this mode of operation INTO Interrupt Power down mode is terminated and the CPU services the INTO interrupt The RETI at the end of the ISR will return the core to the instruction after the one that enabled power down
34. received a valid address hardware will hold SCLOCK low until the I2CI bit is cleared by software This allows the master to wait for the slave to be ready before transmitting the clocks for the next byte The I2CI interrupt bit will be set every time a complete data byte is received or transmitted provided it is followed by a valid ACK If the byte is followed by a NACK an interrupt is NOT generated The ADuC832 will continue to issue interrupts for each complete data byte transferred until a STOP condition is received or the interface is reset When a STOP condition is received the interface will reset to a state where it is waiting to be addressed idle Similarly if the interface receives a NACK at the end of a sequence it also returns to the default idle state The I2CRS bit can be used to reset the interface This bit can be used to force the interface back to the default idle state It should be noted that there is no way in hardware to distinguish between an interrupt generated by a received START valid address and an interrupt generated by a received data byte User software must be used to distinguish between these interrupts REV 0 ADuC832 DUAL DATA POINTER DPCON Data Pointer Control SFR The ADuC832 incorporates two data pointers The second data SFR Address pointer is a shadow data pointer and is selected via the data Power On Default Value 00H pointer control SFR DPCON DPCON also includes some Bit Ad
35. received through the MOSI and MISO data lines A single data bit is transmitted and received in each SPICON SPI Control Register SFR Address F8H Power On Default Value O4H Bit Addressable Yes SCLOCK period Therefore a byte is transmitted received after eight SCLOCK periods The SCLOCK pin is configured as an output in master mode and as an input in slave mode In master mode the bit rate polarity and phase of the clock are controlled by the CPOL SPRO and SPRI bits in the SPICON SFR see Table XII In slave mode the SPICON register will have to be configured with the phase and polarity CPHA and CPOL of the expected input clock In both master and slave modes the data is transmitted on one edge of the SCLOCK signal and sampled on the other It is important therefore that the CPHA and CPOL are configured the same for the master and slave devices SS Slave Select Input Pin The Slave Select SS input pin is shared with the ADC5 input In order to configure this pin as a digital input the bit must be cleared e g CLR P1 5 This line is active low Data is only received or transmitted in slave mode when the SS pin is low allowing the ADuC832 to be used in single master multislave SPI configurations If CPHA 1 then the SS input may be permanently pulled low With CPHA 0 the SS input must be driven low before the first bit in a byte wide transmission or reception and return high again after the last bit in that byt
36. set by hardware The peripheral will only generate a core interrupt if the user has preconfigured the interrupt enable bit in the IEIP2 SFR as well as the global interrupt bit EA in the IE SFR Enabling I2C Interrupts for the ADuC832 MOV IEIP2 01H enable I2C interrupt SETB EA On the ADuC832 an autoclear of the I2CI bit is implemented so this bit is cleared automatically on a read or write access to the IZCDAT SFR MOV I2CDAT A I2CI autocleared MOV A I2CDAT 2 autocleared If for any reason the user tries to clear the interrupt more than once i e access the data SFR more than once per interrupt then the PC controller will halt The interface will then have to be reset using the I2CRS bit The user can choose to poll the I2CI bit or enable the interrupt In the case of the interrupt the PC counter will vector to 003BH at the end of each complete byte For the first byte when the user gets to the I2CI ISR the 7 bit address and the R W bit will appear in the I2CDAT SFR The I2CTX bit contains the R W bit sent from the master If I2CTX is set then the master would like to receive a byte Thus the slave will transmit data by writing to the I2CDAT register If I2CTX is cleared the master would like to transmit a byte Therefore the slave will receive a serial byte Software can interrogate the state of 2 to determine whether it should write to or read from I2CDAT Once the ADuC832 has
37. the device will come up in normal mode and run the program whenever power is cycled or RESET is toggled Note that PSEN is normally an output as described in the External Memory Interface section and is sampled as an input only on the falling edge of RESET 1 at power up or upon external manual reset Note also that if any external circuitry unintentionally pulls PSEN low during power up or reset events it could cause the chip to enter download mode and therefore fail to begin user code execution as it should To prevent this ensure that no external signals are capable of pulling the PSEN pin low except for the external PSEN jumper itself 65 ADuC832 Embedded Serial Port Debugger From a hardware perspective entry into serial port debug mode is identical to the serial download entry sequence described above In fact both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two different ways Note that the serial port debugger is fully contained on the ADuC832 device unlike ROM monitor type debuggers and therefore no external memory is needed to enable in system debug sessions Single Pin Emulation Mode Also built into the ADuC832 is a dedicated controller for single pin in circuit emulation ICE using standard production ADuC832 devices In this mode emulation access is gained by connection to a single pin the EA pin Normally this pin is hardwired
38. to increment the MIN time register A3H 00H No 0 to 59 decimal Minutes Time Register This register is incremented in 1 minute intervals once TCEN in TIMECON is active The MIN counts from 0 to 59 before rolling over to increment the HOUR time register A4H 00H No 0 to 59 decimal Hours Time Register This register is incremented in 1 hour intervals once TCEN in TIMECON is active The HOUR SER counts from 0 to 23 before rolling over to 0 A5H 00H No 0 to 23 decimal 47 ADuC832 8052 COMPATIBLE ON CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on chip These remaining functions are mostly 8052 compatible with a few additional features and are controlled via standard 8052 SFR bit definitions Parallel I O The ADuC832 uses four input output ports to exchange data with external devices In addition to performing general purpose 10 some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device In general when a peripheral is enabled that pin may not be used as a general purpose I O pin Port 0 Port 0 is an 8 bit open drain bidirectional I O port that is directly controlled via the Port 0 SFR Port 0 is also the multi plexed low order address and data bus during accesses to external program or data memory Figure 36 shows a typical bit lat
39. typ DVpp Current 35 20 max Osc Off 25 12 typ Typical Additional Power Supply Currents AVpp DVpp 5 PSM Peripheral 50 typ ADC 1 5 mA DAC 150 typ NOTES Range 40 C to 125 C ADC linearity is guaranteed during normal MicroConverter core operation LSB Size Vggp 2 i e for Internal 2 5 1 LSB 610 uV and for External 1 V 1 LSB 244 yV These numbers are not production tested but are guaranteed by design and or characterization data on production release Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration 5Based on external ADC system components the user may need to execute a system calibration to remove additional external channel errors and achieve these specifications SNR calculation includes distortion and noise components 5Channel to channel crosstalk is measured on adjacent channels The Temperature Monitor will give a measure of the die temperature directly air temperature can be inferred from this result ODAC linearity is calculated using Reduced code range of 100 to 4095 0 to range Reduced code range of 100 to 3945 0 to Vpp range DAC Output Load 10 kQ and 100 pF differential nonlinearity specified on 0 to and 0 to Vpp ranges DAC specification for output impedance in the unbuffered case depends on DAC code BDAC specifications for I
40. 1 1 LSB typ ADC Input is a DC Voltage CALIBRATED ENDPOINT ERRORS 6 Offset Error LSB max Offset Error Match 1 1 LSB typ Gain Error LSB max Gain Error Match 85 85 dB typ DYNAMIC PERFORMANCE 10 kHz Sine Wave SAMPLE 147 kHz Signal to Noise Ratio SNR 71 71 dB typ Total Harmonic Distortion THD 85 85 dB typ Peak Harmonic or Spurious Noise 85 85 dB typ Channel to Channel Crosstalk 80 80 dB typ ANALOG INPUT Input Voltage Ranges 0 Leakage Current 1 1 max Input Capacitance 32 32 pF typ TEMPERATURE SENSOR Voltage Output at 25 C 650 650 mV typ Voltage TC 2 0 2 0 mV C typ Accuracy 3 Internal 2 5 V 1 5 t1 5 C typ External 2 5 V DAC CHANNEL SPECIFICATIONS DAC Load to AGND Internal Buffer Enabled 10 100 pF DC ACCURACY Resolution 12 12 Bits Relative Accuracy 3 3 LSB typ Differential Nonlinearity 1 1 LSB max Guaranteed 12 Bit Monotonic 1 2 1 2 LSB typ Offset Error 50 50 mV max Vrrr Range Gain Error t 1 max AVpp Range 1 1 typ Range Gain Error Mismatch 0 5 0 5 typ of Full Scale on DACI ANALOG OUTPUTS Voltage Range 0 VREF VREF V typ DAC 2 5 V Voltage Range 1 0 to Vpp 0 to Vpp V typ DAC Vpp Output Impedance 0 5 0 5 Q typ DAC AC CHARACTERISTICS Voltage Output Settling Time 15 15 us typ Full Scale Settling Time to within 1 2 LSB of Final Value Digital to Anal
41. 1011 and gain calibration uses internal selected by 53 50 1100 Offset calibration should be executed first followed by gain calibration System calibration can be initiated to compensate for both inter nal and external system errors To perform system calibration using an external reference tie system ground and reference to any two of the six selectable inputs Enable external reference mode ADCCONI 6 Select the channel connected to AGND via 53 50 and perform system offset calibration Select the channel connected CS3 CSO and perform system gain calibration The ADC should be configured to use settings for an ADCCLK of divide by 16 and 4 acquisition clocks 25 ADuC832 INITIATING CALIBRATION IN CODE When calibrating the ADC using ADCCONI the ADC should be set up into the configuration in which it will be used The ADCCONG register can then be used to set up the device up and calibrate the ADC offset and gain MOV ADCCON1 0ACH ADC on ADCCLK set to divide by 16 4 acquisition clock To calibrate device offset MOV ADCCON2 0BH MOV ADCCON3 25H select internal AGND select offset calibration 31 averages per bit offset calibration To calibrate device gain MOV ADCCON2 0CH MOV ADCCON3 27H select internal select offset calibration 31 averages per bit offset calibration To calibrate system offset Connect system AGND to an ADC channel input 0
42. 15200 2 0 80H 09H 0 25 57600 0 3 83H 09H 0 25 57600 1 2 82H 09H 0 25 57600 2 1 81H 09H 0 25 57600 3 0 80H 09H 0 25 38400 0 3 83H 2DH 0 2 38400 1 2 82H 2DH 0 2 38400 2 1 81H 2DH 0 2 38400 3 0 80H 2DH 0 2 19200 0 4 84H 2DH 0 2 19200 1 3 83H 2DH 0 2 19200 2 2 82H 2DH 0 2 19200 3 1 81H 2DH 0 2 19200 4 0 80H 2DH 0 2 9600 0 5 85H 2DH 0 2 9600 1 4 84H 2DH 0 2 9600 2 3 83H 2DH 0 2 9600 3 2 82H 2DH 0 2 9600 4 1 81H 2DH 0 2 9600 5 0 80H 2DH 0 2 59 ADuC832 INTERRUPT SYSTEM The ADuC832 provides a total of nine interrupt sources with two priority levels The control and configuration of the interrupt system is carried out through three interrupt related SFRs IE Interrupt Enable Register IP Interrupt Priority Register IEIP2 Secondary Interrupt Enable Register IE Interrupt Enable Register SFR Address ASH Power On Default Value 00H Bit Addressable Yes Table XXIX IE SFR Bit Designations Bit Name Description 7 EA Written by User to Enable 1 or Disable 0 All Interrupt Sources 6 EADC Written by User to Enable 1 or Disable 0 ADC Interrupt 5 ET2 Written by User to Enable 1 or Disable 0 Timer 2 Interrupt 4 ES Written by User to Enable 1 or Disable 0 UART Serial Port Interrupt 3 ETI Written by User to Enable 1 or Disable 0 Timer 1 Interrupt 2 EXI Written by User to Enable 1 or Disable 0 External Interrupt 1 1 ETO Written by
43. 2 0 7 0 7 AV pp DVpp 5V AV pp DVpp fs 152kHz fg 152kHz s WCP DNL 0 3 0 3 1 04 4 E 2 z d 0 1 011 o WCN DNL 0 3 0 3 0 5 0 5 0 7 0 7 0 511 1023 1535 2047 2559 3071 3583 4095 0 5 1 0 1 5 2 0 2 5 3 0 ADC CODES EXTERNAL REFERENCE V TPC 5 Typical DNL Error Vpp 5 V TPC 8 Typical Worst Case DNL Error vs V 10000 AV pp DVpp fg 152kHz 8000 6000 t tr 5 4000 2000 0 0 511 1023 1535 2047 2559 3071 3583 4095 817 818 819 820 821 ADC CODES CODE TPC 6 Typical DNL Error Vpp 3 V TPC 9 Code Histogram Plot Vpp 5 V 0 6 10000 AVpp DVpp 5V fs 152kHz 9000 0 4 8000 8 02 g 000 7 7 6000 1 iu 2 5000 T 2 3 8 4000 z 0 2 o 3000 0 4 2000 1000 0 6 0 5 1 0 1 5 2 0 2 5 5 0 rm aia E FE EXTERNAL REFERENCE V CODE TPC 7 Typical Worst Case DNL Error vs Vper 5 V TPC 10 Code Histogram Plot Vpp 3 V 42 REV 0 20 AVpp DVpp 5V 0 fs 152kHz fin 9 910kHz 20 SNR 71 3dB THD 88 0dB NT ENOB 11 6 60 m 80 100 120 140 160 0 10 20 30 40 50
44. 2BCP 52 C W Lead Temperature Soldering Vapor Phase 60 sec 215 C Infrared 15 SEC bea wean we dude ad 220 C Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ORDERING GUIDE Temperature Package Package Model Range Description Option ADuC832BS 40 to 125 C 52 Lead Plastic Quad Flatpack 52 ADuC832BCP 40 to 85 C 56 Lead Chip Scale Package CP 56 EVAL ADuC832QS QuickStart Development System EVAL ADuC832QSP QuickStart Plus Development System CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the WARN N G ADuC832 features proprietary ESD protection circuitry permanent damage may occur on devices Sept subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE REV 0 7 ADuC832 P1 0 ADCO T2 P1 1 ADC1 T2EX 2 P1 2 ADC2
45. 3 RES RAAN ARAM BAERS MicroConverter 12 Bit ADCs and DACs with Embedded 62 kBytes Flash MCU ANALOG DEVICES ADuC832 FEATURES ANALOG 1 0 8 Channel 247 kSPS 12 Bit ADC DC Performance 1 LSB INL AC Performance 71 dB SNR DMA Controller for High Speed ADC to RAM Capture 2 12 Bit Monotonic Voltage Output DACs Dual Output PWM X A DACs On Chip Temperature Sensor Function 3 C On Chip Voltage Reference Memory 62 kBytes On Chip Flash EE Program Memory 4 kBytes On Chip Flash EE Data Memory Flash EE 100 Yr Retention 100 kCycles Endurance 2304 Bytes On Chip Data RAM 8051 Based Core 8051 Compatible Instruction Set 16 MHz Max 32 kHz Ext Crystal On Chip Programmable PLL 12 Interrupt Sources 2 Priority Levels Dual Data Pointer Extended 11 Bit Stack Pointer On Chip Peripherals Time Interval Counter TIC UART 12 and SPI Serial 1 0 Watchdog Timer WDT Power Supply Monitor PSM Power Specified for 3 V and 5 V Operation Normal Idle and Power Down Modes Power Down 25 pA 3 V with Wake Up cct Running APPLICATIONS Optical Networking Laser Power Control Base Station Systems Precision Instrumentation Smart Sensors Transient Capture Systems DAS and Communications Systems Upgrade to ADuC812 Systems Runs from 32 kHz External Crystal with On Chip PLL Also Available ADuC831 Pin Compatible Upgrade to Existing ADuC812 Systems that Require Additional Code or Data Memory Run
46. 72 cycles depending on how it is implemented z Swap Shadow DPTR Code MOV A DPL JNZ MOVELOOP REV 0 43 ADuC832 POWER SUPPLY MONITOR As its name suggests the Power Supply Monitor once enabled monitors the DVpp supply on the ADuC832 It will indicate when any of the supply pins drop below one of four user selectable voltage trip points from 2 63 V to 4 37 V For correct operation of the Power Supply Monitor function AVpp must be equal to or greater than 2 7 V Monitor function is controlled via the PSMCON SFR If enabled via the IEIP2 SFR the monitor will interrupt the core using the PSMI bit in the PSMCON SFR This bit will not be cleared until the failing power supply has returned above the trip point for at least 250 ms This monitor function allows the user to save working registers to avoid pos sible data loss due to the low supply condition and also ensures that normal code execution will not resume until a safe supply level has been well established The supply monitor is also pro tected against spurious glitches triggering the interrupt circuit PSMCON Power Supply Monitor Control Register SFR Address DFH Power On Default Value DEH Bit Addressable No Table XV PSMCON SFR Bit Designations Bit Name Description 7 6 CMPD DVpp Comparator Bit This is a read only bit and directly reflects the state of the DVpp comparator Read 1 indicates the DVpp supply is above its selected trip p
47. ARDWARE CONSIDERATIONS 65 ADC Offset and Gain Calibration Coefficients 25 In Circuit Serial Download Access 65 Calibrating the ADC 25 Embedded Serial Port Debugger 66 NONVOLATILE FLASH MEMORY 27 Single Pin Emulation Mode 66 Flash Memory Overview 27 Typical System Configuration 66 Flash EE Memory and the ADuC832 27 DEVELOPMENT TOOLS 66 ADuC832 Flash EE Memory Reliability 27 Using the Flash EE Program Memory 28 TIMING SPECIFICATIONS 67 MW LOAD Mode enne REG Rx 28 OUTLINE DIMENSIONS 77 Flash EE Program Memory Security 28 REV 0 ADuC832 SPECIFICATIONS Parameter Vpp75V Vpp Unit Test Conditions Comments ADC CHANNEL SPECIFICATIONS DC ACCURACY fsamptz 147 kHz see Page 11 for Typical Performance at other fsAMPLE Resolution 12 12 Bits Integral Nonlinearity 1 X LSB max 2 5 V Internal Reference 0 3 0 3 LSB typ Differential Nonlinearity 0 9 0 9 LSB max 2 5 V Internal Reference 20 25 20 25 LSB typ Integral Nonlinearity 1 5 ELS LSB max 1 V External Reference Differential Nonlinearity 1 5 0 9 1 5 0 9 LSB max 1 V External Reference Code Distribution
48. Bit Timer Counter with Autoreload Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in Figure 47 Overflow from TLO not only sets but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged INTERRUPT TFO CORE CLK IS DEFINED BY THE CD BITS IN PLLCON Figure 47 Timer Counter 0 Mode 2 Mode 3 Two 8 Bit Timer Counters Mode 3 has different effects on Timer 0 and Timer 1 Timer 1 in Mode 3 simply holds its count The effect is the same as setting TRI 0 Timer 0 in Mode 3 establishes TLO and THO as two separate counters This configuration is shown in Figure 48 TLO uses the Timer 0 control bits C T Gate TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it out of and into its own Mode 3 or can still be used by the serial interface as a baud rate generator In fact it can be used in any application not requiring an interrupt from Timer 1 itself un INTERRUPT 8 BITS TFO THO 8 BITS CORE CLK IS DEFINED BY THE CD BITS IN PLLCON INTERRUPT TF1 Figure 48 Timer Counter 0 Mode 3 53 ADuC832 T2CON Timer Counter 2 Control Reg
49. CON Flash EE Memory Control SFR 29 GENERAL DESCRIPTION Flash EE Memory Timing 30 SPECIFICATIONS 69 tn ohh ese ne 3 ADuC832 CONFIGURATION REGISTER 832 31 ABSOLUTE MAXIMUM RATINGS 7 USER INTERFACE TO OTHER ON CHIP ORDERING GUIDE ADuC832 PERIPHERALS 32 Using the RE T E took ewe ens 33 PIN CONFIGURATION 8 OR Op PL RTT 35 PIN FUNCTION DESCRIPTIONS 9 Pulsewidth Modulator PWM 36 Serial Peripheral Interface 39 TERMINOLOGY 10 Compatible Interface 41 TYPICAL PERFORMANCE CHARACTERISTICS 11 Dual Data Pointer 6 43 Power Supply Monitor 44 MEMORY ORGANIZATION 14 Watchdog Timer 45 OVERVIEW OF MCU RELATED SFRS 15 Timer Interval Counter 46 Accumiulator SFR a a rr er ors 15 8052 COMPATIBLE ON CHIP PERIPHERALS 48 2 023230 fast caw USE IN HUE OU dide 15 Parallel I O Ports 0 3 48 Stack Pointer SFR SP AND SPH 15 Timers Counters 51 Data Pointer DPTR sss epee 16 UART Serial Interface y 56 Pro
50. D bit in PCON the frequency can be doubled to Core_Clk 32 Eleven bits are transmitted or received a start bit 0 eight data bits a programmable ninth bit and a stop bit 1 The ninth bit is most often used as a parity bit although it can be used for anything including a ninth data bit if required To transmit the eight data bits must be written into SBUF The ninth bit must be written to TB8 in SCON When transmission is initiated the eight data bits from SBUF are loaded onto the transmit shift register LSB first The contents of TB8 are loaded into the ninth bit position of the transmit shift register The transmission will start at the next valid baud rate clock The TI flag is set as soon as the stop bit appears on TxD Reception for Mode 2 is similar to that of Mode 1 The eight data bytes are input at RxD LSB first and loaded onto the receive shift register When all eight bits have been clocked in the following events occur The eight bits in the receive shift register are latched into SBUF The ninth data bit is latched into RB8 in SCON The Receiver Interrupt flag RI is set This will be the case if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or SM2 1 and the received stop bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set Mode 3 9 Bit UART with Variable Baud Rate Mo
51. DuC832 allows addressing up to 16 MBytes of external RAM simply by adding an additional latch as illustrated in Figure 59 ADuC832 Figure 59 External Data Memory Interface 16 MBytes Adaress Space In either implementation Port 0 PO serves as a multiplexed address data bus It emits the low byte of the data pointer DPL as an address which is latched by a pulse of ALE prior to data being placed on the bus by the ADuC832 write operation or the SRAM read operation Port 2 P2 provides the data pointer page byte DPD to be latched by ALE followed by the data pointer high byte DPH If no latch is connected to P2 DPP is ignored by the SRAM and the 8051 standard of 64 kBytes external data memory access is maintained Power Supplies The ADuC832 s operational power supply voltage range is 2 7 V to 5 25 V Although the guaranteed data sheet specifications are given only for power supplies within 2 7 V to 3 6 V or 10 of the nominal 5 V level the chip will function equally well at any power supply level between 2 7 V and 5 5 V Note that Figures 60 and 61 refer to the PQFP package for the CSP package connect the extra DVpp DGND AVpp and AGND in the same manner REV 0 ADuC832 Separate analog and digital power supply pins AVpp and DVpp respectively allow AVpp to be kept relatively free of noisy digital signals often present on the system DVpp line However though you can power AVpp and DVpp from two separat
52. EE Note also that the timebase SFRs can be written initially with the current time the TIC can then be controlled and accessed by user software In effect this facilitates the implementation of a real time clock A block diagram of the TIC is shown in Figure 35 Figure 35 TIC Simplified Block Diagram TIMECON TIC Control Register SFR Address AIH Power On Default Value 00H Bit Addressable No Table XVII TIMECON SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 TFH Twenty Four Hour Select Bit Set by the user to enable the Hour counter to count from 0 to 23 Cleared by the user to enable the Hour counter to count from 0 to 255 5 ITS1 Interval Timebase Selection Bits 4 ITSO Written by user to determine the interval counter update rate ITS1 ITSO Interval Timebase 0 0 1 128 Second 0 1 Seconds 1 0 Minutes 1 1 Hours 3 STI Single Time Interval Bit Set by the user to generate a single interval timeout If set a timeout will clear the TIEN bit Cleared by the user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout 2 TII TIC Interrupt Bit Set when the 8 bit Interval Counter matches the value in the INTVAL SFR Cleared by user software 1 TIEN Time Interval Enable Bit Set by the user to enable the 8 bit time interval counter Cleared by the user to disable the interval counter 0 TCEN Time Clock Enable Bit Set by the user to ena
53. Figure 38 Port 2 Bit Latch and I O Buffer DVpp DVpp DVpp Figure 39 Internal Pull Up Configuration Port 3 Port 3 is a bidirectional port with internal pull ups directly controlled via the P3 SFR Port 3 pins that have 1s written to them are pulled high by the internal pull ups and in that state can be used as inputs As inputs Port 3 pins being pulled exter nally low will source current because of the internal pull ups Port 3 pins with 0s written to them will drive a logic low output voltage Voz and will be capable of sinking 4 mA Port 3 pins also have various secondary functions described in Table XIX The alternate functions of Port 3 pins can only be activated if the corresponding bit latch in the P3 SFR contains a 1 Otherwise the port pin is stuck at 0 Table XIX Port 3 Alternate Pin Functions Pin Alternate Function P3 0 RxD UART Input Pin or Serial Data I O in Mode 0 P3 1 TxD UART Output Pin or Serial Clock Output in Mode 0 P3 2 INTO External Interrupt 0 P3 3 INT1 External Interrupt 1 PWM 1 MISO P3 4 TO Timer Counter 0 External Input PWM External Clock PWM 0 P3 5 T1 Timer Counter 1 External Input P3 6 WR External Data Memory Write Strobe P3 7 RD External Data Memory Read Strobe P3 3 and P3 4 can also be used as PWM outputs In the case that they are selected as the PWM outputs via the CFG832 SFR the PWM outputs will overwrite anything written to P3 4 or P3 3 REV
54. H L with the page address 2 writing the data to be programmed to the 1 4 3 writing the ECON SFR with the appropriate command Step 1 Set Up the Page Address The two address registers EADRH and EADRL hold the high byte address and the low byte address of the page to be addressed The assembly language to set up the address may appear as MOV EADRH 0 Set Page Address Pointer MOV EADRL 03H Step 2 Set Up the EDATA Registers We must now write the four values to be written into the page into the four SFRs EDATAI 4 Unfortunately we do not know three of them Thus we must read the current page and over write the second byte MOV ECON 1 Read Page into EDATA1 4 MOV EDATA2 0F3H Overwrite byte 2 Step 3 Program Page A byte in the Flash EE array can only be programmed if it has previously been erased To be more specific a byte can only be programmed if it already holds the value FFH Because of the Flash EE architecture this erase must happen at a page level therefore a minimum of four bytes one page will be erased when an erase command is initiated Once the page is erased we can program the four bytes in page and then perform a verification of the data MOV ECON 5 ERASE Page MOV ECON 2 WRITE Page MOV ECON 4 VERIFY Page MOV A ECON Check if ECON 0 OK JNZ ERROR Although the 4 kBytes of Flash EE data memory are shipped from the factory pre erased i e byte lo
55. ITS RESERVED F7H O F6H O FSH OJ FSH 2 OjFOH 0 F2H 20H F3H 00H F5H F7H 00H 1 ADCCON1 MDO MDE MCO MDI 12CM I2CRS 12 12 1 BITS IZCCON RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0 0 0 0 EAH o E9H O E8H Y i est 000 BITS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED E7H O E6H 0 0 0 0 0 o EOH Higa 2 ADCDATAH PSMCON ADCI DMA CCONV SCONV cs3 cs2 cs1 cso BITS RESERVED RESERVED RESERVED RESERVED DFH 0 DEH 0 O DsH Vane oot DART 00H IDEH 1 PLLCON cy AC Fo RSI RSO ov BITS ML PSW REsenvep PMAL DMAH DMAP RESERVED RESERVED o 1 TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 uis T2CON envep RCAP2L RCAP2H TL2 TH2 RESERVED O CAH O C9H GDHI 1 PRE3 PRE2 PRE1 PREO WDS WDE WDWR Bits WDCON Reserven CHIPID RESERVED RESERVED EDARL EDARH O C5H 1 CsH O
56. N Core Executing internal software loop Reset 0 4 V Digital I O pins open circuit Core Clk changed via CD bits in PLLCON PCON 0 1 Core Execution suspended in Reset 0 4 V All Port 0 pins 0 4 V All other digital I O and Port 1 pins are open circuit Core Clk changed via CD bits in PLLCON PCON 0 1 Core Execution suspended in power down mode OSC turned ON or OFF via PD bit PLLCON 7 in PLLCON SFR 20 power supply current will increase typically by 3 mA 3 V operation and 10 mA 5 V operation during Flash EE memory program or erase cycle Specifications subject to change without notice REV 0 ADuC832 ABSOLUTE MAXIMUM RATINGS T4 25 C unless otherwise noted AVpptoDVpp 0 3 V to 0 3 V to DGND 0 3 V to 0 3 V DVpp to DGND AVpp to AGND 0 3 V to 7 V Digital Input Voltage to DGND 0 3 V to DVpp 0 3 V Digital Output Voltage to DGND 0 3 V to DVpp 0 3 V Vrer to AGND 0 3 V to AVpp 0 3 V Analog Inputs to AGND 0 3 V to AVpp 0 3 V Operating Temperature Range Industrial ADuCS832BS 40 to 125 C Operating Temperature Range Industrial ADuC832BQP x e s 40 to 85 C Storage Temperature Range 65 C to 150 C Junction Temperature ovv RR Res 150 C Thermal Impedance ADuC832BS 90 C W Thermal Impedance ADuC83
57. NVOLATILE FLASH EE PROGRAM MEMORY 128 BYTE 8051 SPECIAL COMPATIBLE FUNCTION CORE REGISTER AREA OTHER ON CHIP PERIPHERALS TEMPERATURE SENSOR 2 12 BIT DACs 2304 BYTES SERIAL I O RAM WDT PSM TIC PWM Figure 5 Programming Model Accumulator SFR ACC ACC is the Accumulator register and is used for math operations including addition subtraction integer multiplication and division and Boolean bit manipulations The mnemonics for accumulator specific instructions refer to the Accumulator as A B SFR B The B register is used with the ACC for multiplication and divi sion operations For other instructions it can be treated as a general purpose scratch pad register Stack Pointer SP and SPH The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the top of the stack The SP register is incremented before data is stored during PUSH and CALL execu tions While the stack may reside anywhere in on chip RAM the SP register is initialized to 07H after a reset This causes the stack to begin at location 08H As mentioned earlier the ADuC832 offers an extended 11 bit stack pointer The three extra bits to make up the 11 bit stack pointer are the 3 LSBs of the SPH byte located at B7H 15 ADuC832 Data Pointer DPTR The Data Pointer is made up of three 8 bit registers named DPP page byte DPH high byte and DPL low byte These are used to provide me
58. O each time it overflows 1 1 TLO is an 8 bit timer counter controlled by the standard timer 0 control bits THO is an 8 bit timer only controlled by Timer 1 control bits REV 0 51 ADuC832 TCON SFR Address Power On Default Value Bit Addressable Timer Counter 0 and 1 Control Register 88H 00H Yes Table XXI TCON SFR Bit Designations Bit Name Description 7 TF1 6 TRI 5 TFO 4 TRO 3 IE1 2 IT1 1 IEO 0 ITO Timer 1 Overflow Flag Set by hardware on a Timer Counter 1 overflow Cleared by hardware when the Program Counter PC vectors to the interrupt service routine Timer 1 Run Control Bit Set by the user to turn on Timer Counter 1 Cleared by the user to turn off Timer Counter 1 Timer 0 Overflow Flag Set by hardware on a Timer Counter 0 overflow Cleared by hardware when the PC vectors to the interrupt service routine Timer 0 Run Control Bit Set by the user to turn on Timer Counter 0 Cleared by the user to turn off Timer Counter 0 External Interrupt 1 INT1 Flag Set by hardware by a falling edge or zero level being applied to external interrupt Pin INT1 depending on bit IT1 state Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition activated If level activated the external requesting source controls the request flag rather than the on chip hardware External Interrupt 1 IE1 Trigger Type Set by softwar
59. PHA bits should both contain the same values for master and slave devices REV 0 39 ADuC832 The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to SPIDAT SPI Data Register Function read data just received by the SPI interface SFR Address F7H Power On Default Value 00H Bit Addressable No Using the SPI Interface Depending on the configuration of the bits in the SPICON SFR shown in Table XIII the ADuC832 SPI interface will transmit or receive data in a number of possible modes Figure 33 shows all possible ADuC832 SPI configurations and the timing rela tionships and synchronization between the signals involved Also shown in this figure is the SPI interrupt bit ISPI and how it is triggered at the end of each byte wide communication SCLOCK e SCLOCK CPOL 0 SAMPLE INPUT DATA OUTPUT BIT 6 5 4 BIT 3 BIT 2 BIT 1 LSB CPHA 1 ISPI FLAG SAMPLE INPUT Y ISPI FLAG NENNEN d Figure 33 SPI Timing All Modes DATA OUTPUT CPHA 0 40 SPI Interface Master Mode In master mode the SCLOCK pin is always an output and gener ates a burst of eight clocks whenever user code writes to the SPIDAT register The SCLOCK bit rate is determined by SPRO and SPRI in SPICON It should also be noted that the SS pin is not used in master mode If the ADuC832 needs to assert the SS pin on an external sl
60. RVED RESERVED 8FH 0 8CH 0 89H 0 M Pot SP DPL DPH DPP PCON BITS RESERVED RESERVED 87H 1 86H 1 85H 1 84H 1 82 1 80H 1 80H 82H 83H 87H 00H SFR MAP KEY THESE BITS ARE CONTAINED IN THIS BYTE MNEMONIC t rio MNEMONIC SFR ADDRESS J 89H 4 DEFAULT VALUE DEFAULT VALUE p ecc SFR ADDRESS NOTES 1SFRs WHOSE ADDRESS ENDS IN OH OR 8H ARE BIT ADDRESSABLE THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT THEREFORE TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE PORT PINS WRITE A 0 TO THE CORRESPONDING PORT 1 SFR BIT 3CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER UP TO FACTORY CALIBRATED VALUES Figure 6 Special Function Register Locations and Reset Values REV 0 17 ADuC832 ADC CIRCUIT INFORMATION General Overview The ADC conversion block incorporates a fast 8 channel 12 bit single supply ADC This block provides the user with multichannel mux track hold on chip reference calibration features and ADC All components in this block are easily configured via a 3 register SFR interface The ADC converter consists of a conventional successive approximation converter based around a capacitor DAC The converter accepts an analog inpu
61. SBs FS 3 2 LSBs The output coding is straight binary with 1 LSB FS 4096 or 2 5 V 4096 0 61 mV when 2 5 V The ideal input output transfer characteristic for the 0 to range is shown in Figure 7 OUTPUT CODE 111 111 111 110 111 101 111 100 9 4096 000 011 000 010 000 001 l 000 000 ie ov 1LSB VOLTAGE INPUT Figure 7 ADC Transfer Function Typical Operation Once configured via the ADCCON 1 3 SFRs the ADC will con vert the analog input and provide an ADC 12 bit result word in the ADCDATAH L SFRs The top four bits of the ADCDATAH SFR will be written with the channel selection bits so as to identify the channel result The format of the ADC 12 bit result word is shown in Figure 8 ADCDATAH SFR CH ID HIGH 4 BITS OF TOP 4 BITS ADC RESULT WORD ADCDATAL SFR LOW 8 BITS OF THE ADC RESULT WORD Figure 8 ADC Result Format 18 REV 0 ADuC832 ADC Control SFR 1 The ADCCONI register controls conversion and acquisition times hardware conversion modes and power down modes as detailed below SFR Address EFH SFR Power On Default Value 00H Bit Addressable NO Table III ADCCONI SFR Bit Designations Bit Name Description ADCCONI 7 MDI The Mode bit selects the active operating mode of the ADC Set by the user to power up the ADC Cleared by the user to power down the ADC ADCCONI 6 EXT REF Set by t
62. SCLOCK SDATA 0 4 0 4 V max 8 mA Enabled Floating State Leakage Current t10 t10 max 1 1 typ Floating State Output Capacitance 10 10 pF typ START UP TIME At any Core CLK At Power On 500 500 ms typ From Idle Mode 100 100 us typ From Power Down Mode Wakeup with INTO Interrupt 150 400 us typ Wakeup with SPI C Interrupt 150 400 us typ Wakeup with External RESET 150 400 us typ After External RESET in Normal Mode 30 30 ms typ After WDT Reset in Normal Mode 3 3 ms typ Controlled via WDCON SFR REV 0 ADuC832 SPECIFICATIONS continued Parameter Vpp7 5 Vpp73V Unit Test Conditions Comments POWER REQUIREMENTS 7 Power Supply Voltages AVpp DVpp AGND 2 7 V min AVpp DVpp 3 V nom 3 3 4 5 V min AVpp DVpp 5 5 5 V max Power Supply Currents Normal Mode DVpp Current 6 3 mA max Core CLK 2 097 MHz AVpp Current 1 7 157 mA max Core CLK 2 097 MHz DVpp Current 23 12 mA max Core CLK 16 78 MHz 20 10 mA typ Core CLK 16 78 MHz AVpp Current 1 7 1 7 mA max Core CLK 16 78 MHz Power Supply Currents Idle Mode DVpp Current 4 2 mA typ Core CLK 2 097 MHz AVpp Current 0 14 0 14 mA typ Core CLK 2 097 MHz DVpp Current 10 5 mA max Core CLK 16 78 MHz 9 4 mA typ Core CLK 16 78 MHz AVpp Current 0 14 0 14 mA typ Core CLK 16 78 MHz Power Supply Currents Power Down Mode Core CLK 2 097 MHz or 16 78 MHz DVpp Current 80 25 max Osc On 38 14 typ AVpp Current 2 1
63. Serial Port Programming Cable Hardware Software ASPIRE Integrated Development Environment Incorporates 8051 assembler and serial port debugger Serial Download Software CD ROM Documentation and Prototype Device Miscellaneous Windows is a registered trademark of Microsoft Corporation 66 Figure 65 shows the typical components of QuickStart Develop ment System A brief description of some of the software tools components in the QuickStart Development System follows ickStant E Development pum _ lo Bs Day Sys top Figure 65 Components of the QuickStart Development System Figure 66 Typical Debug Session Download In Circuit Serial Downloader The Serial Downloader is a Windows application that allows the user to serially download an assembled program Intel Hex format file to the on chip program FLASH memory via the serial COM I port on a standard PC An Application Note uC004 detailing this serial download protocol is available from www analog com microconverter ASPIRE IDE The ASPIRE Integrated Development Environment is a Windows application that allows the user to compile edit and debug code in the same environment The ASPIRE software allows users to debug code execution on silicon using the MicroConverter UART serial port The debugger provides access to all on chip peripherals during a typical debug session as well as single step animate and brea
64. T plots for the ADuC832 These plots were generated using an external clock input The ADC is using its internal reference 2 5 V sampling a full scale 10 kHz sine wave test tone input at a sampling rate of 149 79 kHz The resultant FFTs shown at 5 V and 3 V supplies illustrate an excellent 100 dB noise floor 71 dB Signal to Noise Ratio SNR and THD greater than 80 dB TPC 13 and TPC 14 show typical dynamic performance versus external reference voltages Again excellent ac performance can be observed in both plots with some roll off being observed as Veer falls below 1 V TPC 15 shows typical dynamic performance versus sampling frequency SNR levels of 71 dBs are obtained across the sampling range of the ADuC832 TPC 16 shows the voltage output of the on chip temperature sensor versus temperature Although the initial voltage output at 25 C can vary from part to part the resulting slope of 2 mV C is constant across all parts AVpp DVpp 5V fs 152kHz WCP INL WCP INL LSBs WCN INL LSBs 0 5 1 0 1 5 2 0 2 5 5 0 EXTERNAL REFERENCE V TPC 3 Typical Worst Case INL Error vs Vper 5 V 0 8 AVpp DVpp fg 152kHz 06 WCP INL 0 4 n Lj m 0 2 m 8 1 5 5 0 2 WCN INL 0 4 0 5 1 0 1 5 2 0 2 5 3 0 EXTERNAL REFERENCE V TPC 4 Typical Worst Case INL Error vs Veer V 11 ADuC83
65. T3BAUDEN T3UARTBAUD Enable Set to enable Timer 3 to generate the baud rate When set PCON 7 T2CON 4 and T2CON 5 are ignored Cleared to let the baud rate be generated as per a standard 8052 6 E 5 4 3 2 DIV2 Binary Divider Factor 1 DIVI DIV2 DIVI DIVO Bin Divider 0 DIVO 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 REV 0 The appropriate value to write to the DIV2 1 0 bits can be calculated using the following formula where defined in PLLCON SFR Note The DIV value must be rounded down 1 Score 08l ao no Daa 32 x Baud Rate DIV log 2 T3FD is the fractional divider ratio required to achieve the required baud rate We can calculate the appropriate value for T3FD using the following formula Note T3FD should be rounded to the nearest integer 2X T3FD 7 x Baud Rate Once the values for DIV and T3FD are calculated the actual baud rate can be calculated using the following formula 2 X Actual Baud Rate 2P x T3FD 64 For example to get a baud rate of 115200 while operating at 16 7 MHz DIV LOG 11059200 32x115200 LOG2 1 58 21 T3FD 2x11059200 2 x115200 64 32 20H therefore the actual baud rate is 114912 bit s Table XXVIII Commonly Used Baud Rates Using Timer 3 Ideal Baud CD DIV T3CON T3FD Error 230400 0 1 81H 09H 0 25 115200 0 2 82H 09H 0 25 115200 11 1 81H 09H 0 25 1
66. The INTO pin must not be driven low during or within 2 machine cycles of the instruction that initiates power down mode It should be noted that the INTO power down interrupt enable bit INTOPD in the PCON SFR must first be set to allow this mode of operation Power On Reset An internal POR Power On Reset is implemented on the ADuC832 For DVpp below 2 45 V the internal POR will hold the ADuC832 in reset As DVpp rises above 2 45 V an internal timer will timeout for 128 ms approximately before the part is released from reset The user must ensure that the power supply has reached a stable 2 7 V minimum level by this time Likewise on power down the internal POR will hold the ADuC832 in reset until the power supply has dropped below 1 V Figure 62 illustrates the operation of the internal POR in detail 2 45V TYP 128ms TYP INTERNAL CORE RESET Figure 62 Internal POR Operation 1 0V TYP 1 0V TYP Grounding and Board Layout Recommendations As with all high resolution data converters special attention must be paid to grounding and PC board layout of ADuC832 based designs in order to achieve optimum performance from the ADC and DACs 64 Although the ADuC832 has separate pins for analog and digital ground AGND and DGND the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the ADuC832 as illustrated in the simpli fied example of Figure 63
67. a In systems where digital and analog ground planes are connected together somewhere else at the system s power supply for example they cannot be connected again near the ADuC832 since a ground loop would result In these cases tie the ADuC832 s AGND and DGND pins all to the analog ground plane as illustrated in Figure 63b In systems with only one ground plane ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa The ADuC832 can then be placed between the digital and analog sections as illustrated in Figure 63c In all of these scenarios and in more complicated real life appli cations keep in mind the flow of current from the supplies and back to ground Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their desti nations For example do not power components on the analog side of Figure 63b with DVpp since that would force return currents from DVpp to flow through AGND Also try to avoid digital currents flowing under analog circuitry which could happen if the user placed a noisy digital chip on the left half of the board in Figure 63c Whenever possible avoid large discontinuities in the ground plane s such as are formed by a long trace on the same layer since they force return signals to travel a longer path And of course make all conn
68. able YES Table IV ADCCON2 SFR Bit Designations Bit Name Description ADCCON2 7 ADCI ADCCON2 6 DMA ADCCON2 5 CCONV ADCCON2 4 SCONV ADCCON2 3 CS3 ADCCON2 2 CS2 ADCCON2 1 CS1 ADCCON2 0 CSO The ADC interrupt bit ADCT is set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion ADCI is cleared by hardware when the PC vectors to the ADC Interrupt Service Routine Otherwise the ADCI bit should be cleared by user code The DMA mode enable bit DMA is set by the user to enable a preconfigured ADC DMA mode opera tion A more detailed description of this mode is given in the ADC DMA Mode section The DMA bit is automatically set to 0 at the end of a DMA cycle Setting this bit causes the ALE output to cease it will start again when is started and will operate correctly after DMA is complete The continuous conversion bit CCONV is set by the user to initiate the ADC into a continuous mode of conversion In this mode the ADC starts converting based on the timing and channel configuration already set up in the ADCCON SFRs the ADC automatically starts another conversion once a previ ous conversion has completed The single conversion bit SCONV is set to initiate a single conversion cycle The SCONV bit is automatically reset to 0 on completion of the single conversion cycle The channel selection bits CS3 0 allow the user to program the ADC channel s
69. ain Bidirectional I O Port Port 0 pins that have 1s written to them float and in A0 A7 that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application it uses strong internal pull ups when emitting 1s TERMINOLOGY ratio is dependent upon the number of quantization levels in the ADC SPECIFICATIONS Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function The endpoints of the transfer function are zero scale a point 1 2 LSB below the first code transition and full scale a point 1 2 LSB above the last code transition Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC Offset Error This is the deviation of the first code transition 0000 000 to 0000 001 from the ideal i e 1 2 LSB Gain Error This is the deviation of the last code transition from the ideal AIN voltage Full Scale 1 5 LSB after the offset error has been adjusted out Signal to Noise Distortion Ratio This is the measured ratio of signal to noise distortion at the output of the ADC The signal is the rms amplitude of the fundamental Noise is the rms sum of all nonfundamental sig nals up to half the sampling frequency 2 excluding dc The 10
70. ault Value 04H Bit Addressable No Table IX DACCON SFR Bit Designations Bit Name Description 7 MODE Set to 0 12 Bit Mode DACI Range Select Bit Set to 1 DACI Range 0 Set 0 DACI Range 0 Vggr DACO Range Select Bit Set to 1 Range 0 Set 0 Range 0 6 RNGI 5 RNGO The DAC MODE bit sets the overriding operating mode for both DACs Set to 1 8 Bit Mode Write 8 Bits to DACxL SFR 4 CLRI 3 CLRO 0 PDO DACI Clear Bit Set to 0 DACI Output Forced to 0 V Set to 1 DACI Output Normal DACO Clear Bit Set to 0 DACI Output Forced to 0 V Set to 1 DACI Output Normal DACO0 1 Update Synchronization Bit When set to 1 the DAC outputs update as soon as DACxL SFRs are written The user can simultaneously update both DACs by first updating the DACxL H SFRs while SYNC is 0 Both DACs will then update simultaneously when the SYNC bit is set to 1 DACI Power Down Bit Set to 1 Power On DACI Set to 0 Power Off DACI DACO Power Down Bit Set to 1 Power On DACO Set to 0 Power Off DACxH L Function SFR Address Power On Default Value Bit Addressable DAC Data Registers DAC Data Registers written by user to update the DAC output DACOL Data Low Byte F9H DACI Data Low Byte DACOH
71. ave device a port digital output pin should be used In master mode a byte transmission or reception is initiated by a write to SPIDAT Eight clock periods are generated via the SCLOCK pin and the SPIDAT byte being transmitted via MOSI With each SCLOCK period a data bit is also sampled via MISO After eight clocks the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register The ISPI flag will be set automatically and an interrupt will occur if enabled The value in the shift register will be latched into SPIDAT SPI Interface Slave Mode E In slave mode the SCLOCK is an input The SS pin must also be driven low externally during the byte communication Transmission is also initiated by a write to SPIDAT In slave mode a data bit is transmitted via MISO and a data bit is received via MOSI through each input SCLOCK period After eight clocks the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register The ISPI flag will be set automatically and an interrupt will occur if enabled The value in the shift register will be latched into SPIDAT only when the transmission reception of a byte has been completed The end of transmission occurs after the eighth clock has been received if CPHA 1 or when SS returns high if CPHA 0 REV 0 ADuC832 COMPATIBLE INTERFACE pins of the on chip SPI interface Therefore
72. bit rate selection bits SPR1 and SPRO bits in SPICON SFR set to 0 and 0 respectively SCLOCK CPOL 0 SCLOCK CPOL 1 MOSI MISO ipsu Figure 76 SPI Master Mode Timing CPHA 0 2742 REV 0 ADuC832 Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING CPHA 1 tss SS to SCLOCK Edge 0 ns 77 lt SCLOCK Low Pulsewidth 330 ns 77 tsH SCLOCK High Pulsewidth 330 ns 77 tpav Data Output Valid after SCLOCK Edge 50 ns 77 Data Input Setup Time before SCLOCK Edge 100 ns 77 tpHD Data Input Hold Time after SCLOCK Edge 100 ns 77 Data Output Fall Time 10 25 ns 77 Data Output Rise Time 10 25 ns 77 tsp SCLOCK Rise Time 10 25 ns 77 tsp SCLOCK Fall Time 10 25 ns 11 tsps SS High after SCLOCK Edge 0 ns TI SCLOCK CPOL 0 SCLOCK N CPOL 1 NA MISO MOSI ipsu Figure 77 SPI Slave Mode Timing CPHA 1 REV 0 75 ADuC832 Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING CPHA 0 tss SS to SCLOCK Edge 0 ns 78 tsL SCLOCK Low Pulsewidth 330 ns 78 tsH SCLOCK High Pulsewidth 330 ns 78 Data Output Valid after SCLOCK Edge 50 ns 78 tpsu Data Input Setup Time before SCLOCK Edge 100 ns 78 tpHD Data Input Hold Time after SCLOCK Edge 100 ns 78 Data Output Fall Time 10 25 ns 78 Data Output Rise Time 10 25 ns 78 tsp SCLOCK Rise Time 10 25 ns 78 ts SCLOCK Fall
73. ble the time clock to the time interval counters Cleared by the user to disable the clock to the time interval counters and reset the time interval SFRs to the last value written to them by the user The time registers HTHSEC SEC MIN and HOUR can be written while TCEN is low 46 REV 0 ADuC832 INTVAL Function SFR Address Power On Default Value Bit Addressable Valid Value HTHSEC Function SFR Address Power On Default Value Bit Addressable Valid Value SEC Function SFR Address Power On Default Value Bit Addressable Valid Value MIN Function SFR Address Power On Default Value Bit Addressable Valid Value HOUR Function SFR Address Power On Default Value Bit Addressable Valid Value REV 0 User Time Interval Select Register User code writes the required time interval to this register When the 8 bit interval counter is equal to the time interval value loaded in the INTVAL SFR the TII bit TIMECON 2 is set and generates an interrupt if enabled A6H 00H No 0 to 255 decimal Hundredths Seconds Time Register This register is incremented in 1 128 second intervals once TCEN in TIMECON is active The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register A2H 00H No 0 to 127 decimal Seconds Time Register This register is incremented in 1 second intervals once TCEN in TIMECON is active The SEC SFR counts from 0 to 59 before rolling over
74. by the CLR EA instruction and it is also a fixed high priority interrupt If the watchdog is not being used to monitor the system it can alternatively be used as a timer The prescaler is used to set the timeout period in which an interrupt will be generated Watchdog Status Bit Set by the Watchdog Controller to indicate that a watchdog timeout has occurred Cleared by writing a 0 or by an external hardware reset It is not cleared by a watchdog reset Watchdog Enable Bit Set by user to enable the watchdog and clear its counters If this bit is not set by the user within the watchdog timeout period the watchdog will generate a reset or interrupt depending WDIR Cleared under the following conditions User writes 0 Watchdog Reset WDIR 707 Hardware Reset PSM Interrupt Watchdog Write Enable Bit To write data into the WDCON SFR involves a double instruction sequence The WDWR bit must be set and the very next instruction must be a write instruction to the WDCON SFR For example CLR EA disable interrupts while writing to WDT SETB WDWR allow write to WDCON WDCON 72H enable WDT for 2 0s timeout SETB EA enable interrupts again if rqd _ Ss O REV 0 45 ADuC832 TIME INTERVAL COUNTER TIC 32 768 2 EXTERNAL CRYSTAL A time interval counter is provided on chip for counting longer inte
75. cations set to FFH it is nonetheless good programming practice to include an erase all routine as part of any configuration setup code running on the ADuC832 An ERASE ALL command consists of writing 06H to the ECON SFR which initiates an erase of the 4 kByte Flash EE array This command coded in 8051 assembly would appear as MOV ECON 06H Erase all Command 2ms Duration 30 Flash EE Memory Timing Typical program and erase times for the ADuC832 are as follows NORMAL MODE operating on Flash EE data memory READPAGE 4 bytes 5 machine cycles WRITEPAGE 4 bytes 380 us VERIFYPAGE 4 bytes 5 machine cycles ERASEPAGE 4 bytes 2 ms ERASEALL 4 kBytes 2 ms READBYTE 1 byte 3 machine cycle WRITEBYTE 1 byte 200 us ULOAD MODE operating on Flash EE program memory WRITEPAGE 256 bytes 15 ms ERASEPAGE 64 bytes 2 ms ERASEALL 56 kBytes 2ms WRITEBYTE 1 byte 200 us It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR The core microcontroller operation on the ADuC832 is idled until the requested Program Read or Erase mode is completed In practice this means that even though the Flash EE memory mode of operation is typically initiated with a two machine cycle instruction to write to the ECON SFR the next instruc tion will not be executed until the Flash EE operation is complete This m
76. ch and I O buffer for a Port 0 port pin The bit latch one bit in the port s SFR is represented as a Type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read a port activate the read latch signal and others activate the read pin signal See the following Read Modify Write Instructions section for more details ADDR DATA DVpp CONTROL READ LATCH INTERNAL BUS WRITE TO LATCH READ PIN Figure 36 Port 0 Bit Latch and I O Buffer As shown in Figure 36 the output drivers of Port 0 pins are switchable to an internal ADDR and ADDR DATA bus by an internal CONTROL signal for use in external memory accesses During external memory accesses the PO SFR gets 1s written to it all of its bit latches become 1 When accessing external memory the CONTROL signal in Figure 36 goes high enabling push pull operation of the output pin from the internal address or data bus ADDR DATA line Therefore no external pull ups are required on Port 0 in order for it to access external memory 48 In general purpose I O port mode Port 0 pins that have 1s written to them via the Port 0 SFR will be con
77. controls the SCLOCK pin and is always configured as an output in master mode In master mode the SCLOCK pin will be pulled high or low depending on the whether MCO is set or cleared To receive data MDE must be cleared to disable the output driver on SDATA Software must provide the clocks by toggling the MCO bit and read SDATA pin via the MDI bit If MDE is cleared MDI can be used to read the SDATA pin The value of the SDATA pin is latched into MDI on a rising edge of SCLOCK is set if the SDATA pin was high on the last rising edge of SCLOCK MDI is cleared if the SDATA pin was low on the last rising edge of SCLOCK Software must control MDO MCO and MDE appropriately to generate the START condition slave address acknowledge bits data bytes and STOP conditions appropriately These functions are provided in technical note uC001 Hardware Slave Mode After reset the ADuC832 defaults to hardware slave mode The interface is enabled by clearing the SPE bit in SPICON Slave mode is enabled by clearing the I2CM bit in I2CCON The ADuC832 has a full hardware slave In slave mode the address is stored in the I2CADD register Data received or to be transmitted is stored in the I2CDAT register 42 Once enabled in slave mode the slave controller waits for a START condition If the ADuC832 detects a valid start condi tion followed by a valid address followed by the R W bit the I2CI interrupt bit will automatically be
78. cted Clock 4 1 0 PWM Counter Selected Clock 16 1 1 PWM Counter Selected Clock 64 1 CSELI PWM Clock Divider CSELO Select the clock source for the PWM as shown below CSEL1 CSELO Description 0 0 PWM Clock 15 0 1 PWM Clock 1 0 PWM Clock External input at P3 4 TO 1 1 PWM Clock fyco 16 777216 MHz 36 0 ADuC832 PWM MODES OF OPERATION MODE 0 PWM Disabled The PWM is disabled allowing P2 6 and P2 7 to be used as normal MODE 1 Single Variable Resolution PWM In Mode 1 both the pulse length and the cycle time period are programmable in user code allowing the resolution of the PWM to be variable PWMLH L sets the period of the output waveform Reducing PWMLIH L reduces the resolution of the PWM output but increases the maximum output rate of the PWM e g setting to 65536 gives a 16 bit PWM with a maximum output rate of 266 Hz 16 777 MHz 65536 Setting PUMIH L to 4096 gives a 12 bit PWM with a maximum output rate of 4096 Hz 16 777MHz 4096 PWMOHIL sets the duty cycle of the PWM output waveform as shown in Figure 27 PWM1H L PWM COUNTER PWMOH L 0 P2 7 Figure 27 ADuC832 PWM in Mode 1 MODE 2 Twin 8 Bit PWM In Mode 2 the duty cycle of the PWM outputs and the resolution of the PWM outputs are both programmable The maximum resolution of the PWM output is eight bits PWMLL sets the period for both PWM outputs
79. d on a single transistor cell architecture This technology is basically an outgrowth of EPROM technology and was developed through the late 1980s Flash EE memory takes the flexible in circuit reprogrammable features of EEPROM and combines them with the space efficient density features of EPROM see Figure 17 Because Flash EE technology is based on a single transistor cell architecture a Flash memory array like EPROM can be imple mented to achieve the space efficiencies or memory densities required by a given design Like EEPROM Flash memory can be programmed in system at a byte level although it must first be erased the erase being performed in page blocks Thus Flash memory is often and more correctly referred to as Flash EE memory EPROM TECHNOLOGY EEPROM TECHNOLOGY IN CIRCUIT REPROGRAMMABLE SPACE EFFICIENT DENSITY FLASH EE MEMORY TECHNOLOGY Figure 17 Flash EE Memory Development Overall Flash EE memory represents a step closer to the ideal memory device that includes nonvolatility in circuit programma bility high density and low cost Incorporated in the ADuC832 Flash EE memory technology allows the user to update program code space in circuit without the need to replace one time programmable OTP devices at remote operating nodes Flash EE Memory and the ADuC832 The ADuC832 provides two arrays of Flash EE memory for user applications 62 kBytes of Flash EE program space are provided
80. de is selected by setting both SMO and 5 In this mode the 8051 UART serial port operates in 9 bit mode with a variable baud rate determined by either Timer 1 or Timer 2 The opera tion of the 9 bit UART is the same as for Mode 2 but the baud rate can be varied as for Mode 1 In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 UART Serial Port Baud Rate Generation Mode 0 Baud Rate Generation The baud rate in Mode 0 is fixed Mode 0 Baud Rate Core Clock Frequency 12 Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the SMOD bit in the PCON SFR If SMOD 0 the baud rate is 1 64 of the core clock If SMOD 1 the baud rate is 1 32 of the core clock Mode 2 Baud Rate 2 9P 64 x Core Clock Frequency Modes 1 and 3 Baud Rate Generation The baud rates in Modes 1 and 3 are determined by the overflow rate in Timer 1 or Timer 2 or both one for transmit and the other for receive 57 ADuC832 Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows Modes 1 and 3 Baud Rate 25M P 32 x Timer 1 Overflow Rate The Timer 1 interrupt should be disabl
81. dressable No nice features such as automatic hardware post increment and post decrement as well as automatic data pointer toggle DPCON is described in Table XIV Table XIV DPCON SFR Bit Designations Bit Name Description 7 Reserved for Future Use 6 DPT Data Pointer Automatic Toggle Enable Cleared by user to disable auto swapping of the DPTR Set in user software to enable automatic toggling of the DPTR after each each MOVX or MOVC instruction 5 DP1ml Shadow Data Pointer Mode 4 DP1m0 These two bits enable extra modes of the shadow data pointer operation allowing for more compact and more efficient code size and execution ml m0 Behavior of the Shadow Data Pointer 0 0 8052 Behavior 0 1 DPTR is post incremented after a MOVX or a MOVC instruction 1 0 DPTR is post decremented after a MOVX or MOVC instruction 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction This instruction can be useful for moving 8 bit blocks to from 16 bit devices 3 DP0m1 Main Data Pointer Mode 2 DP0mO0 These two bits enable extra modes of the main data pointer operation allowing for more compact and more efficient code size and execution ml m0 Behavior of the Main Data Pointer 0 0 8052 Behavior 0 1 DPTR is post incremented after a MOVX or a MOVC instruction 1 0 DPTR is post decremented after a MOVX or MOVC instruction 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction This instruction can be useful for moving 8 bit blocks t
82. e interrupt cycle SFR Address 9AH Power On Default Value 00H Bit Addressable No Purchase of licensed IC components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I C Patent Rights to use the ADuC832 in an system provided that the system conforms to the I C Standard Specification as defined by Philips REV 0 41 ADuC832 The main features of the MicroConverter interface are Only two bus lines are required a serial data line SDATA and a serial clock line SCLOCK An master can communicate with multiple slave devices Because each slave device has a unique 7 bit address single master slave relationships can exist at all times even in a multislave environment Figure 34 On chip filtering rejects 50 ns spikes on the SDATA and the SCLOCK lines to preserve data integrity DVpp 2 MASTER Figure 34 Typical FC System Software Master Mode The ADuC832 can be used as an master device by config uring the peripheral in master mode and writing software to output the data bit by bit This is referred to as a software master Master mode is enabled by setting the I2CM bit in the I2CCON register To transmit data on the SDATA line MDE must be set to enable the output driver on the SDATA pin If MDE is set then the SDATA pin will be pulled high or low depending on whether the MDO bit is set or cleared MCO
83. e capacitor DAC The digital value finally contained in the SAR is then latched out as the result of the ADC conversion Control of the SAR and timing of acquisition and sampling modes is handled automatically by built in ADC control logic Acquisition and conversion times are also fully configurable under user control ADuC832 VREF AGND DAC1 DACO TEMPERATURE MONITOR eg a AIN7 O o e o e o o e o e AGND Figure 9 Internal ADC Structure Note that whenever a new input channel is selected a residual charge from the 32 pF sampling capacitor places a transient on the newly selected input The signal source must be capable of recovering from this transient before the sampling switches click into hold mode Delays can be inserted in software between channel selection and conversion request to account for input stage settling but a hardware solution will alleviate this burden from the software design task and will ultimately result in a cleaner system implementation One hardware solution would be to choose a very fast settling op amp to drive each analog input Such an op amp would need to fully settle from a small signal transient in less than 300 ns in order to guarantee adequate settling under all software configurations A better solution recom mended for use with any amplifier is shown in Figure 10 Though at first glance the circuit in Figure 10 may look like a si
84. e configured to operate either as timers or event counters In Timer function the TI x register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 12 core clock periods the maximum count rate is 1 12 the core clock frequency In Counter function the TLx register is incremented by a 1 to 0 transition at its corresponding external input pin or T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes two machine cycles 24 core clock periods to recognize a 1 to 0 transition the maximum count rate is 1 24 the core clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held for a minimum of one full machine cycle User configuration and control of all Timer operating modes is achieved via three SFRs TMOD TCON Control and configuration for Timers 0 and 1 T2CON Control and configuration for Timer 2 TMOD Timer Counter 0 and 1 Mode Register SFR Address 89H Power On Default Value 00H Bit Addressable No Table XX TMOD SFR Bit Designations Bit Name Description
85. e supplies if desired you must ensure that they remain within 0 3 V of one another at all times in order to avoid damaging the chip as per the Absolute Maximum Ratings section Therefore it is recom mended that unless AVpp and DVpp are connected directly together you connect back to back Schottky diodes between them as shown in Figure 60 Figure 60 External Dual Supply Connections As an alternative to providing two separate power supplies the user can help keep AVpp quiet by placing a small series resistor and or ferrite bead between it and DVpp and then decoupling AVpp separately to ground An example of this configuration is shown in Figure 61 With this configuration other analog circuitry such as op amps voltage reference and so on can be powered from the AVpp supply line as well The user will still want to include back to back Schottky diodes between AVpp and DVpp in order to protect from power up and power down transient condi tions that could separate the two supply voltages momentarily Figure 61 External Single Supply Connections Notice that in both Figure 60 and Figure 61 a large value 10 uF reservoir capacitor sits on DVpp and a separate 10 uF capacitor sits on AVpp Also local small value 0 1 capacitors are located at each Vpp pin of the chip As per standard design prac tice be sure to include all of these capacitors and ensure the smaller capacitors are close to each AVpp pin with trace lengths
86. e the internal reference The external reference will then overdrive this ADuC832 2 5V BAND GAP REFERENCE EXTERNAL VOLTAGE REFERENCE BUFFER Figure 13 Using an External Voltage Reference 223 ADuC832 Configuring the ADC The ADuC832 s successive approximation ADC is driven by a divided down version of the master clock To ensure adequate ADC operation this ADC clock must be between 400 kHz and 6 MHz and optimum performance is obtained with ADC clock between 400 kHz and 4 5 MHz Frequencies within this range can easily be achieved with master clock frequencies from 400 kHz to well above 16 MHz with the four ADC clock divide ratios to choose from For example set the ADC clock divide ratio to 4 1 ADCCLK 16 777216 MHZ 8 2 MHz by setting the appropriate bits in ADCCONI ADCCONI 5 0 ADCCON1 4 0 The total ADC conversion time is 15 ADC clocks plus 1 ADC clock for synchronization plus the selected acquisition time 1 2 3 or 4 ADC clocks For the example above with a 3 clock acquisition time total conversion time is 19 ADC clocks or 9 05 us for a 2 MHz ADC clock In continuous conversion mode a new conversion begins each time the previous one finishes The sample rate is then simply the inverse of the total conversion time described above In the example above the continuous conversion mode sample rate would be 110 3 kHz If using the temperature sensor as the ADC input the
87. e to specify edge sensitive detection 1 1 to 0 transition Cleared by software to specify level sensitive detection i e zero level External Interrupt 0 INTO Flag Set by hardware by a falling edge or zero level being applied to external interrupt Pin INTO depending on bit ITO state Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition activated If level activated the external requesting source controls the request flag rather than the on chip hardware External Interrupt 0 1 0 Trigger Type Set by software to specify edge sensitive detection 1 1 to 0 transition Cleared by software to specify level sensitive detection i e zero level These bits are not used in the control of timer counter 0 and 1 but are used instead in the control and monitoring of the external INTO and INTI interrupt pins Timer Counter 0 and 1 Data Registers Each timer consists of two 8 bit registers These can be used as independent registers or combined to be a single 16 bit register depending on the timer mode configuration THO and TLO Timer 0 high byte and low byte SFR Address 8CH 8AH respectively and TL1 Timer 1 high byte and low byte SFR Address 8DH 8BH respectively _52 REV 0 ADuC832 TIMER COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for Timer Counters 0 and 1 Unless otherwise noted it
88. e wide transmission or reception In SPI slave mode the logic level on the external SS pin can be read via the SPRO bit in the SPICON SFR The following SFR registers are used to control the SPI interface Table XII SPICON SFR Bit Designations Bit Name Description 7 ISPI SPI Interrupt Bit 6 WCOL Write Collision Error Bit Cleared by user code 5 SPE SPI Interface Enable Bit 4 SPIM 3 CPOL Clock Polarity Select Bit 2 CPHA Clock Phase Select Bit 1 SPRI SPI Bit Rate Select Bits SPRO SPRI SPRO 0 0 0 1 1 0 1 1 Set by MicroConverter at the end of each SPI transfer Cleared directly by user code or indirectly by reading the SPIDAT SFR Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress Set by user to enable the SPI interface Cleared by user to enable the pins SPI Master Slave Mode Select Bit Set by user to enable Master Mode operation SCLOCK is an output Cleared by user to enable Slave Mode operation SCLOCK is an input Set by user if SCLOCK idles high Cleared by user if SCLOCK idles low Set by user if leading SCLOCK edge is to transmit data Cleared by user if trailing SCLOCK edge is to transmit data These bits select the SCLOCK rate bitrate in master mode as follows Selected Bit Rate fosc 2 fosc 4 fosc 8 fosc 16 In SPI Slave Mode i e SPIM 0 the logic level on the external SS pin can be read via the SPRO bit The CPOL and C
89. eans that the core will not respond to interrupt requests until the Flash EE operation is complete although the core peripheral functions like counter timers will continue to count and time as configured throughout this period REV 0 ADuC832 ADuC832 Configuration SFR CFG832 The CFG832 SFR contains the necessary bits to configure the internal XRAM External Clock select PWM output selection DAC buffer and the extended SP By default it configures the user into 8051 mode i e extended SP is disabled internal XRAM is disabled 832 ADuC832 Config SFR SFR Address AFH Power On Default Value 00H Bit Addressable No Table VIII CFG832 SFR Bit Designations Bit Name Description 7 EXSP Extended SP Enable When set to 1 by the user the stack will roll over from SPH SP 00FFH to 0100H When set to 0 by the user the stack will roll over from SP FFH to SP 00H 6 PWPO PWM pin out selection Set to 1 by the user PWM output pins selected as P3 4 and P3 3 Set to 0 by the user PWM output pins selected as P2 6 and P2 7 5 DBUF DAC Output Buffer Set to 1 by the user DAC Output Buffer Bypassed Set to 0 by the user DAC Output Buffer Enabled 4 EXTCLK Set by the user to 1 to select an external clock input on P3 4 Set by the user to 0 to use the internal PLL clock 3 RSVD Reserved This bit should always contain 0 2 RSVD Reserved This bit should alwa
90. ect dc accuracy Source Error from 1 uA Error from 10 Impedance Leakage Current Leakage Current 610 61 0 1 LSB 610 uV 1 LSB 6100 610 uV 1 LSB 6 1 mV 10 LSB Although Figure 10 shows the op amp operating at a gain of 1 you can of course configure it for any gain needed Also you can just as easily use an instrumentation amplifier in its place to condition differential signals Use any modern amplifier that is capable of delivering the signal 0 to Vggg with minimal satura tion Some single supply rail to rail op amps that are useful for this purpose include but are certainly not limited to the ones given in Table VI Check Analog Devices literature CD ROM data book and so on for details on these and other op amps and instrumentation amps Table VI Some Single Supply Op Amps Op Amp Model Characteristics OP281 OP481 Micropower OP191 OP291 OP491 I O Good up to Vpp Low Cost OP196 OP296 OP496 I O to Vpp Micropower Low Cost OP183 OP283 High Gain Bandwidth Product OP162 OP262 OP462 High GBP Micro Package AD820 AD822 AD824 FET Input Low Cost AD823 FET Input High GBP Keep in mind that the ADC s transfer function is 0 to and any signal range lost to amplifier saturation near ground will impact dynamic range Though the op amps in Table VI are capable of delivering output signals very closely approaching REV 0 ADuC832 ground no amplifier can deliver signals all the way to ground
91. ections to the ground plane directly with little or no trace separating the pin from its via to ground If the user plans to connect fast logic signals rise fall time lt 5 ns to any of the ADuC832 s digital inputs add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADuC832 input pins A value of 100 Q or 200 Q is usually sufficient to prevent high speed signals from coupling capacitively into the ADuC832 and affecting the accuracy of ADC conversions PLACE ANALOG PLACE DIGITAL a COMPONENTS AGND DGND b PLACE ANALOG PLACE DIGITAL COMPONENTS i COMPONENTS AGND i DGND PLACE ANALOG PLACE DIGITAL COMPONENTS COMPONENTS HERE mum HERE Figure 63 System Grounding Schemes ADuC832 DOWNLOAD DEBUG ENABLE JUMPER NORMALLY OPEN DVpp 1 DVpp V V 1 2 HEADER FOR EMULATION ACCESS Cm 52613609 01010101010 NORMALLY OPEN ANALOG INPUT E 1 ADCO 39 v 9 ve AVop 4 G6 DVpp OUTPUT ADuC832 lt lt G2 9 paco 19 pact Go DAC OUTPUT 5 T W 98883 415197 8 1S 0091 62 93 64 65H06 V X NOT CONNECTED IN THIS EXAMPLE DVpp V 9 PIN D SUB FEMALE 1 a 3 4 6 7 8 Figure 64 Example ADuC832 Sy
92. ed in this application The timer itself can be configured for either timer or counter operation and in any of its three running modes In the most typical application it is configured for timer operation in the Autoreload mode high nibble of TMOD 0010 binary In that case the baud rate is given by the formula Modes I and 3 Baud Rate 25 32 x Core Clock 12 x 256 TH1 Table XXV shows some commonly used baud rates and how they might be calculated from a core clock frequency of 16 78 MHz and 2 0971 MHz Generally speaking a 5 error is tolerable using asynchronous start stop communications Table XXV Commonly Used Baud Rates Timer 1 Core Ideal CLK SMOD TH1 Reload Actual Baud MHz Value Value Baud Error 9600 16 78 1 9 9 9709 1 14 2400 16 78 1 36 DCH 2427 1 14 1200 16 78 1 73 B7H 1197 0 25 1200 2 10 0 9 1213 1 14 Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2 Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted received Because Timer 2 has a 16 bit OSC FREQ IS DIVIDED BY 2 NOT 12 CONTROL NOTE AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT CONTROL TRANSITION DETECTOR EXEN2 CORE CLK IS DEFINED BY THE CD BITS IN PLLCON Autoreload mode a wider range of baud rates is possible using Timer 2 Modes 1 and Baud Rate
93. either high or low to select execution from internal or external program memory space as described earlier To enable single pin emulation mode however users will need to pull the EA pin high through a 1 resistor as shown in Figure 64 The emulator will then connect to the 2 pin header also shown in Figure 64 To be compatible with the standard connector that comes with the single pin emulator available from Accutron Limited www accutron com use a 2 pin 0 1 inch pitch Friction Lock header from Molex www molex com such as their part number 22 27 2021 Be sure to observe the polarity of this header As represented in Figure 64 when the Friction Lock tab is at the right the ground pin should be the lower of the two pins when viewed from the top Typical System Configuration A typical ADuC832 configuration is shown in Figure 64 It summarizes some of the hardware considerations discussed in the previous paragraphs DEVELOPMENT TOOLS There are two models of development tools available for the ADuC832 namely QuickStart Entry level development system QuickStart Plus Comprehensive development system These systems are described briefly below QuickStart Development System The QuickStart Development System is an entry level low cost development tool suite supporting the ADuC832 The system consists of the following PC based Windows compatible hardware and software development tools ADuC832 Evaluation Board and
94. electable in this Range FLASH EE MEMORY RELIABILITY CHARACTERISTICS Endurance 100 000 100 000 Cycles min Data Retention 100 100 Years min DIGITAL INPUTS Input High Voltage Vig 2 4 2 V min Input Low Voltage Via 0 8 0 4 V max Input Leakage Current Port 0 EA t10 t10 max Vin 0 V or Vpp d E typ Vin 0 V or Vpp Logic 1 Input Current All Digital Inputs 10 10 uA max Vin Vpp uA typ Vin Vpp Logic 0 Input Current Port 1 2 3 15 25 max 40 15 typ 450 mV Logic 1 0 Transition Current Port 2 3 660 250 max 2 400 140 typ 2 REV 0 ADuC832 Parameter Vpp 5V Vpp 3 Unit Test Conditions Comments SCLOCK and RESET Only Schmitt Triggered Inputs V 1 3 0 95 V min 3 0 2 5 V max Vr 0 8 0 4 V min 1 4 1 1 V max Vr 0 3 0 3 V min 0 85 0 85 V max CRYSTAL OSCILLATOR Logic Inputs XTAL1 Only Vwi Input Low Voltage 0 8 0 4 V typ Vine Input High Voltage 3 5 2 5 V typ XTALI Input Capacitance 18 18 pF typ XTAL2 Output Capacitance 18 18 pF typ MCU CLOCK RATE 16 78 16 78 MHz max Programmable via PLLCON DIGITAL OUTPUTS Output High Voltage Voy 2 4 V min Vpp 4 5 V to 5 5 V 4 0 V typ Isouncs 80 2 4 V min Vpp 2 7 V to 3 3 V 2 6 V typ Isource 20 HA Output Low Voltage Voi ALE Ports 0 and 2 0 4 0 4 V max 1 6 mA 0 2 0 2 V typ 1 6 mA Port 3 0 4 0 4 V max 4 mA
95. election under software control When a conversion is initiated the channel converted will be that pointed to by these channel selection bits In DMA mode the channel selection is derived from the channel ID written to the external memory CS3 CS2 CS1 CS0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 Temp Monitor Requires minimum of 1 to acquire 1 0 0 1 DACO Only use with Internal DAC o p buffer on 1 0 1 0 DACI Only use with Internal DAC o p buffer on 1 0 1 1 AGND 1 1 0 0 VREF 1 1 1 1 DMA STOP Place in XRAM location to finish DMA sequence see the section ADC DMA Mode All other combinations reserved 20 REV 0 ADuC832 ADCCONSG ADC Control SFR 3 The ADCCONG register controls the operation of various calibra tion modes as well as giving an indication of ADC busy status SFR Address F5H SFR Power On Default Value 00H Bit Addressable NO Table V ADCCON3 SFR Bit Designations Bit Name Description ADCCON3 7 BUSY The ADC Busy Status Bit BUSY is a read only status bit that is set during a valid ADC conversion or calibration cycle Busy is automatically cleared by the core at the end of conversion or calibration ADCCON3 6 GNCLD Gain Calibration Disable Bit Set to 0 to Enable Gain Calibration Set to 1 to Disable Gain Calibration ADCCON3 5 AVGS1 Number of Averages Selection Bits ADCCON3 4 AVGSO This bit selects the number of
96. er function down Decreasing the offset coefficient compensates for negative offset and effectively pushes the ADC transfer function up The maximum offset that can be compensated is typically 5 of Vggg which equates to typically 125 mV with a 2 5 V reference Similarly the gain calibration coefficient compensates for dc gain errors in both the ADC and the input signal Increasing the gain coefficient compensates for a smaller analog input signal range and scales the ADC transfer function up effectively increasing the slope of the transfer function Decreasing the gain coefficient compensates for a larger analog input signal range and scales the ADC transfer function down effectively decreasing the slope of the transfer function The maximum analog input signal range for which the gain coefficient can compensate is 1 025 X Vggg and the minimum input range is 0 975 X VREF which equates to typically 2 5 of the reference voltage CALIBRATING THE ADC There are two hardware calibration modes provided that can be easily initiated by user software The ADCCON SFR is used to calibrate the ADC Bit 1 TYPICAL and the CS3 to CSO ADCCONJ2 set up the calibration modes Device calibration can be initiated to compensate for significant changes in operating conditions frequency analog input range reference voltage and supply voltages In this calibration mode offset calibration uses internal AGND selected via ADCCON2 register bits CS3 CSO
97. es as a bootloader A Bootload Enable option exists in the serial downloader to Always RUN from E000H 28 after Reset If using a bootloader this option is recommended to ensure that the bootloader always executes correct code after reset Programming the Flash EE program memory via ULOAD mode is described in more detail in the description of ECON and also in technical note uC007 EMBEDDED DOWNLOAD DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 62 kBYTES OF ON CHIP PROGRAM MEMORY THE KERNEL PROGRAM APPEARS AS NOP INSTRUCTIONS TO USER CODE A USER BOOTLOADER SPACE THE USER BOOTLOADER SPACE CAN BE PROGRAMMED IN DOWNLOAD DEBUG MODE VIA THE KERNEL BUT IS READ ONLY WHEN EXECUTING USER CODE 62 kBYTES 1 1 1 1 OFUSER CODE MEMORY USER DOWNLOAD SPACE EITHER THE DOWNLOAD DEBUG KERNEL OR USER CODE IN SOKBXTE ULOAD MODE CAN PROGRAM THIS SPACE 1 1 0000H Figure 19 Flash EE Program Memory Map in ULOAD Mode Flash EE Program Memory Security The ADuC832 facilitates three modes of Flash EE program memory security These modes can be independently activated restricting access to the internal code space These security modes can be enabled as part of serial download protocol as described in technical note uC004 or via parallel programming The security modes available on the ADuC832 are described as follows Lock Mode This mode locks the c
98. every so often PWMOH L C000H 1 1 120 Hp 1 PWMHH L 4000H Figure 32 PWM Mode 6 REV 0 ADuC832 SERIAL PERIPHERAL INTERFACE The ADuC832 integrates a complete hardware Serial Peripheral Interface SPI on chip SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously i e full duplex It should be noted that the SPI pins are shared with the pins Therefore the user can only enable one or the other interface at any given time see SPE in Table XII The SPI port can be configured for Master or Slave operation and typically consists of four pins namely MISO Master In Slave Out Data I O Pin The MISO master in slave out pin is configured as an input line in master mode and an output line in slave mode The MISO line on the master data in should be connected to the MISO line in the slave device data out The data is transferred as byte wide 8 bit serial data MSB first MOSI Master Out Slave In Pin The MOSI master out slave in pin is configured as an output line in master mode and an input line in slave mode The MOSI line on the master data out should be connected to the MOSI line in the slave device data in The data is transferred as byte wide 8 bit serial data MSB first SCLOCK Serial Clock I O Pin The master serial clock SCLOCK is used to synchronize the data being transmitted and
99. fication pages of this data sheet the ADuC832 Flash EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of 40 C to 25 C and 85 C to 125 C The results allow the specification of a minimum endurance figure over supply and temperature of 100 000 cycles with an endurance figure of 700 000 cycles being typical of operation at 25 C Retention quantifies the ability of the Flash EE memory to retain its programmed data over time Again the ADuC832 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification A117 at a specific junction temperature T 55 C As part of this qualification procedure the Flash EE memory is cycled to its specified endurance limit described above before data retention is characterized This means that the Flash EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash EE memory is reprogrammed It should also be noted that retention lifetime based on an activation energy of 0 6 eV will derate with as shown in Figure 18 300 250 5 200 2 ADI SPECIFICATION 100 YEARS MIN z BRO 150 AT Tj 55 C E z lu 100 50 0 40 50 60 70 80 90 100 110 T JUNCTION TEMPERATURE C Figure 18 Flash EE Memory Data Retention 27 ADuC832 Using the Flash EE Program Mem
100. figured as open drain and will therefore float In this state Port 0 pins can be used as high impedance inputs This is represented in Figure 36 by the NAND gate whose output remains high as long as the CONTROL signal is low thereby disabling the top FET External pull up resistors are therefore required when Port 0 pins are used as general purpose outputs Port 0 pins with 0 written to them will drive a logic low output voltage Vor and will be capable of sinking 1 6 mA Port 1 Port 1 is also an 8 bit port directly controlled via the P1 SFR Port 1 digital output capability is not supported on this device Port 1 pins can be configured as digital inputs or analog inputs By power on default these pins are configured as analog inputs i e 1 written in the corresponding Port 1 register bit con figure any of these pins as digital inputs the user should write a 0 to these port bits to configure the corresponding pin as a high impedance digital input These pins also have various secondary functions described in Table XVIII Table XVIII Port 1 Alternate Pin Functions Pin Alternate Function P1 0 T2 Timer Counter 2 External Input 1 1 T2EX Timer Counter 2 Capture Reload Trigger P1 5 SS Slave Select for the SPI Interface READ LATCH INTERNAL BUS WRITE TO LATCH 1 o PIN TO ADC Figure 37 Port 1 Bit Latch and I O Buffer Port 2 Port 2 is a bidirectional
101. ft Register fixed baud rate Core CIk 2 0 1 Mode 1 8 bit UART variable baud rate 1 0 Mode 2 9 bit UART fixed baud rate 64 or Core_Clk 32 1 1 Mode 3 9 bit UART variable baud rate 5 SM2 Multiprocessor Communication Enable Bit Enables multiprocessor communication in Modes 2 and 3 In Mode 0 SM2 should be cleared In Mode 1 if SM2 is set RI will not be activated if a valid stop bit was not received If SM2 is cleared RI will be set as soon as the byte of data has been received In Modes 2 or 3 if SM2 is set RI will not be activated if the received ninth data bit in RB8 is 0 If SM2 is cleared RI will be set as soon as the byte of data has been received 4 REN Serial Port Receive Enable Bit Set by user software to enable serial port reception Cleared by user software to disable serial port reception 3 TB8 Serial Port Transmit Bit 9 The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3 2 RB8 Serial Port Receiver Bit 9 The ninth data bit received in Modes 2 and 3 is latched into RB8 For Mode 1 the stop bit is latched into RB8 1 TI Serial Port Transmit Interrupt Flag Set by hardware at the end of the eighth bit in Mode 0 or at the beginning of the stop bit in Modes 1 2 and 3 TI must be cleared by user software 0 RI Serial Port Receive Interrupt Flag Set by hardware at the end of the eighth bit in Mode 0 or halfway through the stop bit in Modes 1 2 and 3 RI must be c
102. gh to ALE High 19 257 tck 40 6tck 100 ns 71 ALE 0 two PSEN 0 t N LLDV gt RLRH 4 RD 0 N tavwL gt PORT 0 2 0 Figure 71 External Data Memory Read Cycle REV 0 69 ADuC832 16 78 MHz Core CIk Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY WRITE CYCLE WR Pulsewidth 257 100 ns 72 tAVLL Address Valid after ALE Low 19 tcx 40 ns 72 LLAX Address Hold after ALE Low 24 tcx 35 ns 72 ALE Low to RD or WR Low 128 228 50 50 ns 72 Address Valid to RD or WR Low 108 4tck 130 ns 72 tovwx Data Valid to WR Transition 9 50 ns 72 tovwH Data Setup before WR EN 267 150 ns 72 twHox Data and Address Hold after WR 9 tcx 50 ns 72 RD or WR High to ALE High 19 257 tcx 40 100 ns 72 ALE 0 PORT 2 0 lt P Figure 72 External Data Memory Write Cycle 70 0 ADuC832 16 78 MHz Core CIk Variable Clock Parameter Min Typ Max Min Typ Max Unit Figure UART TIMING Shift Register Mode Serial Port Clock Cycle Time 715 121 us T3 tovxH Output Data Setup to Clock 463 lOtck 133 ns 73 tpvxH Input Data Setup to Clock 252 21 133 ns 73 Input Data Hold after Clock 0 0 ns 73 txHox Output Data Hold after Clock 22 21 117 ns 73
103. gn voltage output settling time and digital to analog glitch energy depend on external buffer implementation in unbuffered mode DAC in unbuffered mode tested with OP270 external buffer which has a low input leakage current Measured with Vgge and pins decoupled with 0 1 capacitors to ground Power up time for the internal reference will be determined by the value of the decoupling capacitor chosen for both the Vpgp and Cpgp pins When using an external reference device the internal band gap reference input can be bypassed by setting the ADCCONI 6 bit In this mode the V ger and Crer pins need to be shorted together for correct operation Flash EE Memory reliability characteristics apply to both the Flash EE program memory and the Flash EE data memory Endurance is qualified to 100 000 cycles as per Std 22 method A117 and measured at 40 25 C and 125 C Typical endurance at 25 C is 700 000 cycles Retention lifetime equivalent at junction temperature Tj 55 C as per JEDEC Std 22 method A117 Retention lifetime based on an activation energy of 0 6 eV will derate with junction temperature as shown in Figure 18 in the Flash EE Memory description section PPower supply current consumption is measured in Normal Idle and Power Down Modes under the following conditions Normal Mode Idle Mode idle mode Power Down Mode Reset 0 4 V Digital I O pins open circuit Core Clk changed via CD bits in PLLCO
104. go high 65536 PWM COUNTER PWM1H L PWMOH L Figure 29 PWM Mode 3 zog ADuC832 MODE 4 Dual NRZ 16 Bit X A DAC Mode 4 provides a high speed PWM output similar to that of a A DAC Typically this mode will be used with the PWM clock equal to 16 777216 MHz In this mode P2 6 and P2 7 are updated every PWM clock 60 ns in the case of 16 MHz Over any 65536 cycles 16 bit PWM PWMO P2 6 is high for PWMOH L cycles and low for 65536 PWMOHIL cycles Similarly PWMI P2 7 is high for PWMIHIL cycles and low for 65536 PWMIH L cycles For example if PWM1H was set to 4010H slightly above one quarter of FS then typically P2 7 will be low for three clocks and high for one clock each clock is approximately 60 ns Over every 65536 clocks the PWM will compensate for the fact that the output should be slightly above one quarter of full scale by having a high cycle followed by only two low cycles PWMOH L CARRYOUTATP10 ei EE een 16 777MHz PWM1H L 4000H Figure 30 PWM Mode 4 For faster DAC outputs at lower resolution write 0s to the LSBs that are not required If for example only 12 bit perfor mance is required then write 0s to the four LSBs This means that a 12 bit accurate S D DAC output can occur at 4 096 kHz Similarly writing 0s to the eight LSBs gives an 8 bit accurate S D DAC output at 65 kHz MODE 5 Dual 8 Bit PWM
105. gram Status Word SFR PSW 16 UART Serial Port Control Register 56 Power Control SFR PCON 16 UART Operating Modes 57 UART Serial Port Baud Rate Generation 541 SPECIAL FUNCTION REGISTERS 17 Timer 1 Generated Baud Rates 58 Timer 2 Generated Baud Rates 58 ADC CIRCUIT INFORMATION 18 Timer Generated Baud Rates 59 General OVerview bind 18 Intertupt System Er REN PS 60 ADC Transfer Function 18 Typical Operation em ce a es 18 ADuC832 HARDWARE DESIGN CONSIDERATIONS 61 ADCCONI ADC Control SER 1 19 Glock Oscillator 42 52 A bees 61 ADCCON2 ADC Control SFR 2 20 External Memory Interface eder P e as 62 ADCCON3 ADC Control SER 3 21 Power Supplies B LM ILC 62 Driving the A D 22 Power Consumption C E LM EU 65 Voltage Reference Connections 23 Power Saving Modes 03 Configuring the ADC 24 Power On x ear e are see 64 ADC DMA Mode 24 Grounding and Board Layout Recommendations 64 Micro Operation during ADC DMA Mode 25 OTHER H
106. h EE program memory to run user code The user can choose to run code from this internal memory or from an external program memory If the user applies power or resets the device while the EA pin is pulled low the part will execute code from the external program space otherwise the part defaults to code execution from its internal 62 kBytes of Flash EE program memory Unlike the ADuC812 where code execution can overflow from the internal code space to external code space once the PC becomes greater than the ADuC832 does not support the rollover from F7FFH in internal code space to F800H in external code space Instead the 2048 bytes between F800H and FFFFH will appear as NOP instructions to user code This internal code space can be downloaded via the UART serial port while the device is in circuit 56 kBytes of the program memory can be reprogrammed during runtime thus the code space can be upgraded in the field using a user defined protocol or it can be used as a data memory This will be discussed in more detail in the Flash EE Memory section Flash EE Data Memory 4 kBytes of Flash EE data memory are available to the user and can be accessed indirectly via a group of control registers mapped into the Special Function Register SFR area Access to the Flash EE data memory is discussed in detail later as part of the Flash EE Memory section General Purpose RAM The general purpose RAM is divided into two separate memories
107. he user to select an external reference Cleared by the user to use the internal reference ADCCONI 5 The ADC clock divide bits select the divide ratio for the PLL master clock used to generate the ADCCONI 4 CKO ADC clock To ensure correct ADC operation the divider ratio must be chosen to reduce the ADC clock to 4 5 MHz and below A typical ADC conversion will require 17 ADC clocks The divider ratio is selected as follows CK1 MCLK Divider 0 0 8 0 1 4 1 0 16 1 1 32 ADCCONI 3 The ADC acquisition select bits AQ1 0 select the time provided for the input track and hold amplifier ADCCONI 2 AQO to acquire the input signal An acquisition of three or more ADC clocks is recommended clocks are selected as follows AQ1 0 ADC Clks 0 0 1 0 1 2 1 0 3 1 1 4 ADCCONI 1 T2C The Timer 2 conversion bit T2C is set by the user to enable the Timer 2 overflow bit be used as the ADC convert start trigger input ADCCONI 0 EXC The external trigger enable bit EXC is set by the user to allow the external Pin P3 5 CONVST to be used as the active low convert start input This input should be an active low pulse minimum pulsewidth 7100 ns at the required sample rate REV 0 19 ADuC832 ADCCON2 ADC Control SFR 2 The ADCCON2 register controls ADC channel selection and conversion modes as detailed below SFR Address D8H SFR Power On Default Value 00H Bit Address
108. his section of the data sheet it is assumed that P2 6 and P2 7 are selected as the PWM outputs To use the PWM user software first write to PWMCON to select the PWM mode of operation and the PWM input clock Writing to PWMCON also resets the PWM counter In any of the 16 bit modes of operation modes 1 3 4 6 user software should write to the PWMOL or PWMIL SFRs first This value is written to a hidden SFR Writing to the PWMOH or PWM1H SFRs updates both the PWMxH and the PWMxL SFRs but does not change the outputs until the end of the PWM cycle in progress The values written to these 16 bit registers are then used in the next PWM cycle PWMCON PWM Control SFR SFR Address AEH Power On Default Value 00H Bit Addressable No Table XI PWMCON SFR Bit Designations Bit Name Description 7 SNGL Turns off PWM Output at P2 6 or P3 4 Leaving Port Pin Free for Digital I O 6 MD2 PWM Mode Bits 5 MD1 The MD2 1 0 bits choose the PWM mode as follows 4 MD2 Mode 0 0 0 Mode 0 PWM Disabled 0 0 1 Mode 1 Single variable resolution PWM on P2 7 or P3 3 0 1 0 Mode 2 Twin 8 bit PWM 0 1 1 Mode 3 Twin 16 bit PWM 1 0 0 Mode 4 Dual NRZ 16 bit X A DAC 1 0 1 Mode 5 Dual 8 bit PWM 1 1 0 Mode 6 Dual RZ 16 bit DAC 1 1 1 Reserved for future use 3 CDIVI PWM Clock Divider 2 CDIVO Scale the clock source for the PWM counter as shown below CDIV1 CDIVO Description 0 0 PWM Counter Selected Clock 1 0 1 PWM Counter Sele
109. ia ADCCON2 SFR T2 I Timer 2 Digital Input Input to Timer Counter 2 When enabled Counter 2 is incremented in response to a 1 to 0 transition of the T2 input T2EX I Digital Input Capture Reload trigger for Counter 2 also functions as an Up Down control input for Counter 2 SS I Slave Select Input for the SPI Interface SDATA IO User Selectable PC Compatible or SPI Data Input Output Pin SCLOCK VO Serial Clock Pin for PC Compatible or SPI Serial Interface Clock MOSI IO SPI Master Output Slave Input Data I O Pin for SPI Interface MISO IO SPI Master Input Slave Output Data I O Pin for SPI Serial Interface DACO Voltage Output from DACO DACI Voltage Output from DACI RESET I Digital Input A high level on this pin for 24 master clock cycles while the oscillator is running resets the device P3 0 P3 7 IO Port 3 is a bidirectional port with internal pull up resistors Port 3 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs Port 3 pins being pulled externally low will source current because of the internal pull up resistors Port 3 pins also contain various secondary functions that are described below PWMC I PWM Clock Input PWMO Voltage Output PWM outputs be configured to uses ports 2 6 and 2 7 or 3 4 and 3 3 PWMI PWMI Voltage Output See CFG832 Register for further information RxD IO Receiver Data Input Asynchronous or Data
110. ignificantly limit output voltage swing Figures 23 and 24 illustrate this behavior It should be noted that the upper trace in each of these figures is only valid for an output range selection of 0 to AVpp In 0 to Vggg mode DAC loading will not cause highside voltage drops as long as the reference voltage remains below the upper trace in the corresponding figure For example if AVpp V and 2 5 V the high side voltage will not be affected by loads less than 5 mA But somewhere around 7 mA the upper curve in Figure 24 drops below 2 5 Vggp indicating that at these higher currents the output will not be capable of reaching 5 DAC LOADED WITH OFFFH OUTPUT VOLTAGE V DAC LOADED WITH 0000H 0 5 10 15 SOURCE SINK CURRENT mA Figure 23 Source and Sink Current Capability with Vrer 5 V 33 ADuC832 DAC LOADED WITH OFFFH OUTPUT VOLTAGE V DAC LOADED WITH 0000H 0 5 10 15 SOURCE SINK CURRENT mA Figure 24 Source and Sink Current Capability with VREF Vpp 3V To reduce the effects of the saturation of the output amplifier at values close to ground and to give reduced offset and gain errors the internal buffer can be bypassed This is done by setting the DBUF bit in the CFG832 register This allows a full rail to rail output from the DAC which should then be buffered externally using a dual supply op amp in order to get a rail to rail output
111. ions When the destination operand is a port or a port bit these instructions read the latch rather than the pin ANL Logical AND e g ANL P1 A ORL Logical OR e g ORL P2 A XRL Logical EX OR e g XRL P3 A JBC Jump if bit 1 and clear bit e g JBC P1 1 LABEL CPL Complement bit e g CPL P3 0 INC increment e g INC P2 DEC Decrement e g DEC P2 DJNZ Decrement and jump if not zero e g DINZ P3 LABEL MOV PX Y C Move carry to Bit Y of Port X CLR PX Y Clear Bit Y of Port X SETB PX Y Set Bit Y of Port X The reason that read modify write instructions are directed to the latch rather than the pin is to avoid a possible misinterpreta tion of the voltage level of a pin For example a port pin might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transistor and interpret it as a logic 0 Reading the latch rather than the pin will return the correct value of 1 REV 0 ADuC832 Timers Counters The ADuC832 has three 16 bit Timer Counters Timer 0 Timer 1 and Timer 2 The Timer Counter hardware has been included on chip to relieve the processor core of the overhead inherent in implementing Timer Counter functionality in soft ware Each Timer Counter consists of two 8 bit registers THx and TLx x 0 1 and 2 All three can b
112. ister SFR Address C8H Power On Default Value 00H Bit Addressable Yes Table XXII T2CON SFR Bit Designations Bit Name Description 7 TF2 Timer 2 Overflow Flag Set by hardware on a Timer 2 overflow TF2 will not be set when either RCLK 1 or TCLK 1 Cleared by user software 6 EXF2 Timer 2 External Flag Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 Cleared by user software 5 RCLK Receive Clock Enable Bit Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3 Cleared by the user to enable Timer 1 overflow to be used for the receive clock 4 TCLK Transmit Clock Enable Bit Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3 Cleared by the user to enable Timer 1 overflow to be used for the transmit clock 3 EXEN2 Timer 2 External Enable Flag Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port Cleared by the user for Timer 2 to ignore events at T2EX 2 TR2 Timer 2 Start Stop Control Bit Set by the user to start Timer 2 Cleared by the user to stop Timer 2 1 CNT2 Timer 2 Timer or Counter Function Select Bit Set by the user to select counter function input from external T2 pin Cleared by the user to select timer
113. k point code execution control Note the ASPIRE IDE is also included as part of the QuickStart Plus System As part of the QuickStart Plus System the ASPIRE IDE also supports mixed level and C source debug This is not available in the QuickStart System but there is an example project that demonstrates this capability REV 0 ADuC832 QuickStart Plus Development System The QuickStart Plus Development system offers users enhanced nonintrusive debug and emulation tools The System consists of the following PC based Windows compatible hardware and software development tools Hardware ADuC832 Prototype Board Accutron Nonintrusive Single Pin Emulator Software ASPIRE Integrated Development Environment Features full C and assembly emulation using the Accutron single pin emulator Miscellaneous CD ROM Documentation Figure 67 Accutron Single Pin Emulator 2 7 V to 3 6 V or 4 75 V to 5 25 V DVpp 2 7 V to 3 6 or 4 75 V to 5 25 V TIMING SPECIFICATIONS 2 3 all specifications to unless otherwise noted 32 768 kHz External Crystal Parameter Min Typ Max Unit Figure CLOCK INPUT External Clock Driven XTAL1 XTALI Period 30 52 us 68 Width Low 15 16 us 68 tckH Width High 15 16 us 68 tcKR XTALI Rise Time 20 ns 68 tckE XTALI Fall Time 20 ns 68 1 tcorE ADuC832 Core Clock Frequency 0 131 16 78 MHz tcoRE ADuC832 Core Clock Period 0 476 u
114. leared by software _56 REV 0 ADuC832 Mode 0 8 Bit Shift Register Mode Mode 0 is selected by clearing both the SMO and SM1 bits in the SFR SCON Serial data enters and exits through RxD TxD outputs the shift clock Eight data bits are transmitted or received Transmission is initiated by any instruction that writes to SBUF The data is shifted out of the RxD line The eight bits are transmitted with the least significant bit LSB first as shown in Figure 51 MACHINE MACHINE CYCLE 1 Pit 2 32 5 34 55 se 51 sa sa sa watts ce e tem 34 se 51 32 sa s ss se CORE Ju CLK ALE gt RxD DATA OUT DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7 TxD SHIFTCLock L p Figure 51 UART Serial Port Transmission Mode 0 Reception is initiated when the receive enable bit REN is 1 and the receive interrupt bit RI is 0 When RI is cleared the data is clocked into the RxD line and the clock pulses are output from the TxD line Mode 1 8 Bit UART Variable Baud Rate Mode 1 is selected by clearing SMO and setting SM1 Each data byte LSB first is preceded by a start bit 0 and followed by a stop bit 1 Therefore 10 bits are transmitted on TxD or received on RxD The baud rate is set by the Timer 1 or Timer 2 overflow rate or a combination of the two one for transmission and the other for reception Transmission is initiated by writing to SBUF
115. ltage reference in the on state This is available at the pin but as noted before there will be a gain error between this and that of the ADC The Crer output becomes available when the ADC is powered up If an external voltage reference is preferred it should be connected to and pins as shown in Figure 12 Bit 6 of the ADCCONI SFR must be set to 1 to switch in the external reference voltage REV 0 To ensure accurate ADC operation the voltage applied to must be between 1 V and AVpp In situations where analog input signals are proportional to the power supply such as some strain gage applications it may be desirable to connect the and pins directly to AVpp Operation of the ADC or DACs with a reference voltage below 1 V however may incur loss of accuracy eventually resulting in missing codes or non monotonicity For that reason do not use a reference voltage less than 1 V ADuC832 EXTERNAL 25V VOLTAGE BAND GAP REFERENCE REFERENCE BUFFER Figure 12 Using an External Voltage Reference To maintain compatibility with the ADuC812 the external refer ence may also be connected to the Vggg pin as shown in Figure 13 to overdrive the internal reference Note this introduces a gain error for the ADC that has to be calibrated out thus the previous method is the recommended one for most users For this method to work ADCCONI 6 should be configured to us
116. memory Enters ULOAD mode directing subsequent ECON instructions to operate on the Flash EE program memory Not Implemented Use the MOVC instruction Results in bytes 0 255 of internal XRAM being written to the 256 bytes of Flash EE program memory at the page address given by EADRH 0 EADRH E0H Note The 256 bytes in the page being addressed must be pre erased Reserved Command Not Implemented Use the MOVC and MOVX Instructions to verify the WRITE in software Results in the 64 byte page of Flash EE program memory addressed by the byte address EADRH L being erased EADRL can equal any of 64 locations within the page A new page starts whenever EADRL is equal to 00H 40H 80H or COH Results in the Erase of the entire 56 kBytes of ULOAD Flash EE program memory Not Implemented Use the MOVC command Results in the byte in EDATAI being written into Flash EE program memory at the byte address EADRH L 0 lt EADRH L lt DFFFH Enters NORMAL mode directing subsequent ECON instructions to operate on the Flash EE data memory Leaves the ECON instructions to operate on the Flash EE program memory REV 0 29 ADuC832 Example Programming the Flash EE Data Memory A user wishes to program F3H into the second byte on Page 03H of the Flash EE data memory space while preserving the other three bytes already in this page A typical program of the Flash EE Data array will involve 1 setting EADR
117. mory addresses for internal and external code access and external data access It may be manipulated as a 16 bit register DPTR DPH DPL although INC DPTR instructions will automatically carry over to DPP or as three independent 8 bit registers DPP DPH DPL The ADuC832 supports dual data pointers Refer to the Dual Data Pointer section Program Status Word PSW The PSW SFR contains several bits reflecting the current status of the CPU as detailed in Table I SFR Address DOH Power On Default Value 00H Bit Addressable Yes Table I PSW SFR Bit Designations Bit Name Description 7 CY Carry Flag 6 AC Auxiliary Carry Flag 5 FO General Purpose Flag 4 RS1 Register Bank Select Bits 3 RSO RS1 RSO Selected Bank 0 0 0 0 1 1 1 0 2 1 1 3 2 OV Overflow Flag 1 Fl General Purpose Flag 0 P Parity Bit Power Control SFR PCON The PCON SFR contains bits for power saving options and general purpose status flags as shown in Table II SFR Address 87H Power On Default Value 00H Bit Addressable No Table II PCON SFR Bit Designations Bit Name Description 7 SMOD Double UART Baud Rate 6 SERIPD PC SPI Power Down Interrupt Enable 5 INTOPD INTO Power Down Interrupt Enable 4 ALEOFF Disable ALE Output 3 General Purpose Flag Bit 2 General Purpose Flag Bit 1 PD Power Down Mode Enable 0 IDL Idle Mode Enable 16 REV 0 SPECIAL FUNCTION REGISTERS All registers except the program counte
118. mple antialiasing filter it actually serves no such purpose since its corner frequency is well above the Nyquist frequency even at a 200 kHz sample rate Though the R C does help to reject some incoming high frequency noise its primary function is to ensure that the transient demands of the ADC input stage are met 22 ADuC832 Figure 10 Buffering Analog Inputs It does so by providing a capacitive bank from which the 32 pF sampling capacitor can draw its charge Its voltage will not change by more than one count 1 4096 of the 12 bit transfer function when the 32 pF charge from a previous channel is dumped onto it A larger capacitor can be used if desired but not a larger resistor for reasons described below The Schottky diodes in Figure 10 may be necessary to limit the voltage applied to the analog input pin as per the data sheet absolute maximum ratings They are not necessary if the op amp is powered from the same supply as the ADuC832 since in that case the op amp is unable to generate voltages above Vpp or below ground An op amp of some kind is necessary unless the signal source is very low impedance to begin with DC leakage currents at the ADuC832 s analog inputs can cause measurable dc errors with external source impedances as little as 100 Q or so To ensure accurate ADC operation keep the total source impedance at each analog input less than 610 The table below illustrates examples of how source impedance can aff
119. n at these external Ports as a result Note that during DMA to the internally contained XRAM Ports 0 and 2 are available for use The only case in which the MCU will be able to access XRAM during DMA is when the internal XRAM is enabled and the section of RAM to which the DMA ADC results are being written to lies in an external XRAM Then the MCU will be able to access the internal XRAM only This is also the case for use of the extended stack pointer The MicroConverter core can be configured with an interrupt to be triggered by the DMA controller when it has finished filling the requested block of RAM with ADC results allowing the service routine for this interrupt to postprocess data without any real time timing constraints REV 0 ADC Offset and Gain Calibration Coefficients The ADuC832 has two ADC calibration coefficients one for offset calibration and one for gain calibration Both the offset and gain calibration coefficients are 14 bit words and are each stored in two registers located in the Special Function Register SFR area The offset calibration coefficient is divided into ADCOFSH six bits and ADCOFSL eight bits and the gain calibration coefficient is divided into ADCGAINH six bits and ADCGAINL eight bits The offset calibration coefficient compensates for dc offset errors in both the ADC and the input signal Increasing the offset coefficient compensates for positive offset and effectively pushes the ADC transf
120. namely the upper and the lower 128 bytes of RAM The lower 128 bytes of RAM can be accessed through direct or indirect addressing The upper 128 bytes of RAM can only be accessed through indirect addressing as it shares the same address space as the SFR space which can only be accessed through direct addressing The lower 128 bytes of internal data memory are mapped as shown in Figure 2 The lowest 32 bytes are grouped into four banks of eight registers addressed as RO through R7 The next 16 bytes 128 bits locations 20H through 2FH above the register banks form a block of directly addressable bit locations at bit addresses 00H through 7FH The stack can be located anywhere in the internal memory address space and the stack depth can be expanded up to 2048 bytes Reset initializes the stack pointer to location 07H and increments it once before loading the stack to start from locations 08H which is also the first register RO of register bank 1 Thus if one is going to use more than one register bank the stack pointer should be initialized to an area of RAM not used for data storage 14 GENERAL PURPOSE AREA BANKS SELECTED BIT ADDRESSABLE BIT ADDRESSES VIA BITS IN PSW FOUR BANKS OF EIGHT REGISTERS RO R7 4 RESET VALUE OF STACK POINTER 4 4 Figure 2 Lower 128 Bytes of Internal Data Memory The ADuC832 contains 2048 bytes of internal XRAM 1792 bytes of which can be configured to be used as an e
121. nputs Port 2 16 23 pins being pulled externally low will source current because of the internal pull up resistors Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the external 24 bit external data memory space REV 0 9 ADuC832 PIN FUNCTION DESCRIPTIONS continued Mnemonic Type Function PSEN 0 7 0 0 T O Program Store Enable Logic Output This output is a control signal that enables the external program memory to the bus during external fetch operations It is active every six oscillator periods except during external data memory accesses This pin remains high during internal program execution PSEN can also be used to enable serial download mode when pulled low through a resistor on power up or RESET Address Latch Enable Logic Output This output is used to latch the low byte and page byte for 24 bit address space accesses of the address into external memory during normal operation It is activated every six oscillator periods except during an external data memory access External Access Enable Logic Input When held high this input enables the device to fetch code from internal program memory locations 0000H to 1FFFH When held low this input enables the device to fetch all instructions from external program memory This pin should not be left floating Port 0 is an 8 Bit Open Dr
122. ns starting Timer 2 running for Timer 2 conversions or receiving an external trigger When the DMA conversions are completed the ADC interrupt bit ADCI is set by hardware and the external SRAM contains the new ADC conversion results as shown below It should be noted that no result is written to the last two memory locations When the DMA mode logic is active it takes the responsibility of storing the ADC results away from both the user and ADuC832 core logic As it writes the results of the ADC conversions to exter nal memory it takes over the external memory interface from the core Thus any core instructions that access the external memory while DMA mode is enabled will not get access to it The core will execute the instructions and they will take the same time to execute but they will not gain access to the external memory 00000AH 1 1 1 1 44 STOP COMMAND NO CONVERSION RESULT WRITTEN HERE CONVERSION RESULT FOR ADC CH 3 CONVERSION RESULT 1 0 0 0 gt FOR TEMP SENSOR CONVERSION RESULT 44 FOR ADC CH 5 CONVERSION RESULT 000000H o 1 44 FOR ADC CHi 2 Figure 15 Typical External Memory Configuration Post ADC DMA Operation REV 0 ADuC832 The DMA logic operates from the ADC clock and uses pipelining to perform the ADC conversions and access the external memory at the
123. o from 16 bit devices 1 This bit is not implemented to allow the INC DPCON instruction toggle the data pointer without incrementing the rest of the SFR 0 DPSEL Data Pointer Select Cleared by user to select the main data pointer This means that the contents of this 24 bit register are placed into the three SFRs DPL DPH and DPP Set by the user to select the shadow data pointer This means that the contents of a separate 24 bit register appears in the three SFRs DPL DPH and DPP Note 1 This is the only place where the main and shadow data MOV DPTR 0 Main DPTR 0 pointers are distinguished Everywhere else in this data sheet MOV DPCON 55H Select shadow DPTR wherever the DPTR is mentioned operation on the active DPTR 1 increment mode is implied DPTRO increment mode Note 2 Only MOVC MOVX DPTR instructions are relevant BEER auto toggling above MOVC MOVX PC Ri instructions will not cause the MOV DPTR to automatically post increment decrement and so on illustrate the operation of DPCON the following code will MOVC Get data copy 256 bytes of code memory at address DOOOH into XRAM Post Inc DPTR starting from address 0000H Swap to Main DPTR Data The following code uses 16 bytes and 2054 cycles To perform MOVX DPTR A Put ACC in ARON this on a standard 8051 requires approximately 33 bytes and marn DEIR 71
124. ode memory disabling parallel program ming of the program memory However reading the memory in parallel mode and reading the memory via a MOVC command from external memory is still allowed This mode is deactivated by initiating a code erase command in serial download or parallel programming modes Secure Mode This mode locks code in memory disabling parallel programming program and verify read commands as well as disabling the execution of a MOVC instruction from external memory which is attempting to read the op codes from internal memory Read Write of internal data Flash EE from external memory is also disabled This mode is deactivated by initiating a code erase command in serial download or parallel programming modes Serial Safe Mode This mode disables serial download capability on the device If Serial Safe mode is activated and an attempt is made to reset the part into serial download mode 1 e RESET asserted and de asserted with PSEN low the part will interpret the serial download reset as a normal reset only It will therefore not enter serial download mode but only execute a normal reset sequence Serial Safe mode can only be disabled by initiating a code erase command in parallel programming mode REV 0 ADuC832 USING THE FLASH EE DATA MEMORY The 4 kBytes of Flash EE data memory is configured as 1024 pages each of four bytes As with the other ADuC832 peripherals BYTE 3 OFFEH BYTE 3
125. oftware If EXEN2 1 then Timer 2 still performs the above but with the added feature that a 1 to 0 transition at external input T2EX will also trigger the 16 bit reload and set EXF2 The Autoreload mode is illus trated in Figure 49 TR2 TRANSITION DETECTOR CONTROL EXEN2 CORE CLK IS DEFINED BY THE CD BITS IN PLLCON TL2 TH2 16 Bit Capture Mode In the Capture mode there are again two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then Timer 2 is a 16 bit timer or counter that upon overflowing sets bit TF2 the Timer 2 overflow bit which can be used to generate an interrupt If EXEN2 1 then Timer 2 still performs the above but a 1 10 0 transition on external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt The Capture mode 1s illustrated in Figure 50 The baud rate generator mode is selected by RCLK 1 and or TCLK 1 In either case if Timer 2 is being used to generate the baud rate the TF2 interrupt flag will not occur Therefore Timer 2 interrupts will not occur so they do not have to be disabled In this mode the EXF2 flag however can still cause interrupts and this can be used as a third external interrupt Baud rate generation will be described as part of the UART serial por
126. og Glitch Energy 10 10 nV sec typ 1 LSB Change at Major Carry REV 0 ADuC832 SPECIFICATIONS continued Parameter Vpp 5 Vpp Unit Test Conditions Comments DAC CHANNEL SPECIFICATIONS 13 Internal Buffer Disabled DC ACCURACY Resolution 12 12 Bits Relative Accuracy 13 3 LSB typ Differential Nonlinearity 1 1 LSB max Guaranteed 12 Bit Monotonic 1 2 1 2 LSB typ Offset Error 5 mV max Vrer Range Gain Error 0 3 0 3 Vrer Range Gain Error Mismatch 0 5 0 5 max of Full Scale on DACI ANALOG OUTPUTS Voltage Range 0 0 VREF VREF DAC Vggp 2 5 V REFERENCE INPUT OUTPUT REFERENCE OUTPUT Output Voltage 2 5 2 5 t2 5 2 5 Of Measured at the Pin Power Supply Rejection 47 57 dB typ Reference Temperature Coefficient 100 100 ppm C typ Internal Power On Time 80 80 ms typ EXTERNAL REFERENCE INPUT Vrer and Pins Shorted Voltage Range Vggg 0 1 0 1 V min Vpp V max Input Impedance 20 20 kQ typ Input Leakage 1 1 max Internal Band Gap Deselected via ADCCONI 6 POWER SUPPLY MONITOR PSM DVpp Trip Point Selection Range 2 63 V min Four Trip Points Selectable in 4 37 V max This Range Programmed via TPD1 0 in PPMCON DVpp Power Supply Trip Point Accuracy 3 5 max WATCHDOG TIMER WDT Timeout Period 0 0 ms min Nine Timeout Periods 2000 2000 ms max S
127. oint Read 0 indicates the DVpp supply is below its selected trip point 5 PSMI Power Supply Monitor Interrupt Bit This bit will be set high by the MicroConverter if either CMPA or CMPD is low indicating low analog or digital supply The PSMI bit can be used to interrupt the processor Once CMPD and or CMPA return and remain high a 250 ms counter is started When this counter times out the PSMI interrupt is cleared PSMI can also be written by the user However if either comparator output is low it is not possible for the user to clear PSMI 4 TPD1 DVpp Trip Point Selection Bits 3 TPDO These bits select the DVpp trip point voltage as follows TPDI TPDO Selected DVpp Trip Point V 0 0 4 37 0 1 3 08 1 0 2 93 1 1 2 63 2 Reserved 1 Reserved 0 PSMEN Power Supply Monitor Enable Bit Set to 1 by the user to enable the Power Supply Monitor Circuit Cleared to 0 by the user to disable the Power Supply Monitor Circuit 44 0 ADuC832 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC832 enters an erroneous state possibly due to a programming error or electrical noise The watchdog function can be disabled by clearing the WDE Watchdog Enable bit in the Watchdog Control WDCON SFR When enabled the watchdog circuit will gener ate a system reset or interrupt WDS if the user program fails to set the wa
128. on chip to facilitate code execution without any external discrete ROM device requirements The program memory can be pro grammed in circuit using the serial download mode provided using conventional third party memory programmers or via a user defined protocol that can configure it as data if required A 4 kByte Flash EE data memory space is also provided on chip This may be used as a general purpose nonvolatile scratchpad area User access to this area is via a group of six SFRs This space can be programmed at a byte level although it must first be erased in 4 byte pages ADuC832 Flash EE Memory Reliability The Flash EE program and data memory arrays on the ADuC832 are fully qualified for two key Flash EE memory characteristics namely Flash EE Memory Cycling Endurance and Flash EE Memory Data Retention REV 0 Endurance quantifies the ability of the Flash EE memory to be cycled through many program read and erase cycles In real terms a single endurance cycle is composed of four independent sequential events These events are defined as a Initial page erase sequence b Read verify sequence c Byte program sequence d Second read verify sequence A single Flash EE Memory Endurance Cycle In reliability qualification every byte in both the program and data Flash EE memory is cycled from 00H to FFH until a first fail is recorded signifying the endurance limit of the on chip Flash EE memory As indicated in the speci
129. onsiderations section Internal XRAM 2 kBytes of on chip data memory exist on the ADuC832 This memory although on chip is also accessed via the MOVX instruction The 2 kBytes of internal XRAM are mapped into the bottom 2 kBytes of the external address space if the CFG832 bit is set Otherwise access to the external data memory will occur just like a standard 8051 When using the internal XRAM Ports 0 and 2 are free to be used as general purpose I O FFFFFFH FFFFFFH EXTERNAL EXTERNAL DATA DATA MEMORY MEMORY SPACE SPACE 24 BIT 24 BIT ADDRESS ADDRESS SPACE SPACE 000800H 0007FFH 2 kBYTES ON CHIP XRAM 000000H 000000H CFG832 0 0 CFG832 0 1 Figure 4 Internal and External XRAM SPECIAL FUNCTION REGISTERS SFRs The SFR space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only It provides an interface between the CPU and all on chip periph erals A block diagram showing the programming model of the ADuC832 via the SFR area is shown in Figure 5 All registers except the Program Counter PC and the four general purpose register banks reside in the SFR area The SFR registers include control configuration and data registers that provide an interface between the CPU and all on chip peripherals REV 0 4 kBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH EE DATA MEMORY 8 CHANNEL 12 BIT ADC 62 kBYTE ELECTRICALLY REPROGRAMMABLE NO
130. ory The 62 kByte Flash EE program memory array is mapped into the lower 62 kBytes of the 64 kBytes program space addressable by the ADuC832 and is used to hold user code in typical applications The program memory Flash EE memory arrays can be programmed in three ways 1 Serial Downloading In Circuit Programming The ADuC832 facilitates code download via the standard UART serial port The ADuC832 will enter serial download mode after a reset or power cycle if the PSEN pin is pulled low through an external 1 kQ resistor Once in serial download mode the user can download code to the full 62 kBytes of Flash EE program memory while the device is in circuit in its target appli cation hardware A PC serial download executable is provided as part of the ADuC832 QuickStart development system The Serial Download protocol is detailed in a MicroConverter Application Note uC004 2 Parallel Programming The parallel programming mode is fully compatible with con ventional third party Flash or EEPROM device programmers In this mode Ports and P2 operate as the external data and address bus interface ALE operates as the Write Enable strobe and Port P3 is used as a general configuration port that configures the device for various program and erase operations during parallel programming The high voltage 12 V supply required for Flash programming is generated using on chip charge pumps to supply the high voltage program lines
131. oth plots are just less than 0 3 LSBs TPC 3 and TPC 4 show the variation in worst case positive WCP INL and worst case negative WCN INL versus external reference input voltage TPC 5 and TPC 6 show typical ADC differential nonlinearity DNL errors from ADC code 0 to code 4095 at 5 V and 3 V supplies respectively The ADC is using its internal reference 2 5 V and operating at a sampling rate of 152 kHz and the typically worst case errors in both plots is just less than 0 2 LSBs TPC 7 and TPC 8 show the variation in worst case positive WCP DNL and worst case negative WCN DNL versus external reference input voltage TPC 9 shows a histogram plot of 10 000 ADC conversion results on a dc input with 5 V The plot illustrates an excellent code distribution pointing to the low noise performance of the on chip precision ADC AVpp DVpp 5V fs 152kHz LSBs 0 511 1023 1535 2047 2559 3071 3583 4095 ADC CODES TPC 1 Typical INL Error 5 V AVpp DVpp fg 152kHz LSBs 0 511 1023 1535 2047 2559 3071 3583 4095 ADC CODES TPC 2 Typical INL Error Vpp V REV 0 TPC 10 shows a histogram plot of 10 000 ADC conversion results on a dc input for Vpp 3 V The plot again illustrates a very tight code distribution of 1 LSB with the majority of codes appearing in one output pin TPC 11 and TPC 12 show typical FF
132. port with internal pull up resistors directly controlled via the P2 SFR Port 2 also emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24 bit external data memory space As shown in Figure 38 the output drivers of Ports 2 are switchable to an internal ADDR and ADDR DATA bus by an internal CONTROL signal for use in external memory accesses as for Port 0 In external memory addressing mode CONTROL 1 the port pins feature push pull operation controlled by the internal address bus ADDR line However unlike the PO SFR during external memory accesses the P2 SFR remains unchanged REV 0 ADuC832 In general purpose I O port mode Port 2 pins that have 1s written to them are pulled high by the internal pull ups Figure 39 and in that state can be used as inputs As inputs Port 2 pins being pulled externally low will source current because of the internal pull up resistors Port 2 pins with Os written to them will drive a logic low output voltage Vor and will be capable of sinking 1 6 mA P2 6 and P2 7 can also be used as PWM outputs In the case that they are selected as the PWM outputs via the CFG832 SFR the PWM outputs will overwrite anything written to P2 6 or P2 7 ADDR READ DVpp DV LATCH CONTROL DD DD INTERNAL PULL UP INTERNAL BUS WRITE TO LATCH READ SEE FIGURE 39 FOR PIN DETAILS OF INTERNAL PULL UP
133. r and the four general purpose register banks reside in the special function register SFR area The SFR registers include control configuration and data registers that provide an interface between the CPU and other on chip peripherals ADuC832 the figure below NOT USED Unoccupied locations in the SFR address space are not implemented i e no register exists at this location If an unoccupied location is read an unspecified value is returned SFR locations reserved for on chip testing are shown lighter shaded below RESERVED and should not be accessed by user software Sixteen of the SFR locations are also Figure 6 shows a full SFR memory map and SFR contents on Reset Unoccupied SFR locations are shown dark shaded in bit addressable and denoted by 1 in the figure below i e the bit addressable SFRs are those whose address ends in 0H or 8H SPICON ISPI WCOL SPE SPIM CPOL SPR1 SPRO pits gt DACOL DACOH DACiL DAC1H DACCON EESERUEDIIRESERUED O OJFBH OjFeH 0 04H F9H 00H FAH FDH M ADCOFSL ADCGAINL ADCGAINH ADCCON3 SPIDAT B
134. rvals than the standard 8051 compatible timers are capable of The TIC is capable of timeout intervals ranging from 1 128 second to 255 hours Furthermore this counter is clocked by the external 32 768 kHz crystal rather than the core clock and has the ability to remain active in power down mode and time long power down intervals This has obvious applications for remote battery powered sensors where regular widely spaced readings are required Note Instructions to the TIC SFRs are also clocked at 32 768 kHz sufficient time must be allowed for in user code for these instructions to execute Six SFRs are associated with the time interval counter TIMECON being its control register Depending on the configuration of the ITO and IT1 bits in TIMECON the selected time counter register overflow will clock the interval counter When this counter is equal to the time interval value loaded in the INTVAL SFR the TII bit TIMECON 2 is set and generates an interrupt if enabled If the ADuC832 is in power down mode again with TIC interrupt ITSO 1 8 BIT PRESCALER HUNDREDTHS COUNTER HTHSEC INTERVAL TIMEBASE TIEN SECOND COUNTER SELECTION SEC MUX MINUTE COUNTER MIN HOUR COUNTER HOUR 8 BIT INTERVAL COUNTER enabled the TII bit will wake up the device and resume code TIME INTERVAL COUNTER INTERRUPT execution by vectoring directly to the TIC interrupt service vector address at 0053H The TIC related SFRs are described below M
135. s ADuC832 Machine Cycle Time 0 72 5 7 91 55 us NOTES AC inputs during testing are driven at DVpp 0 5 for a Logic 1 and 0 45 for a Logic 0 Timing measurements are made at min for a Logic 1 and Vy max for a Logic 0 as shown in Figure 69 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs A port pin begins to float when a 100 mV change from the loaded level occurs as shown in Figure 69 5C for all outputs 80 pF unless otherwise noted ADuC822 internal PLL locks onto a multiple 512 times the external crystal frequency of 32 768 kHz to provide a Stable 16 78 MHz internal clock for the system The core can operate at this frequency or at a binary submultiple called Core Clk selected via the PLLCON SFR gt This number is measured at the default Core operating frequency of 2 09 MHz 5ADuC832 Machine Cycle Time is nominally defined as 12 Figure 68 XTAL1 Input DVpp 0 5V d 0 2DVpp 0 9V 0 1V TIMING Vioap 0 1V TEST POINTS VLoap REFERENCE 0 20 POINTS DD Vi oap 0 1V Vioap Figure 69 Timing Waveform Characteristics REV 0 67 ADuC832 16 78 MHz Core CIk Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL PROGRAM MEMORY READ CYCLE TLHLL ALE Pulsewidth 79
136. s from 1 MHz 16 MHz External Crystal MicroConverter is a registered trademark and QuickStart is a trademark of Analog Devices Inc SPI is a registered trademark of Motorola Inc I C is a registered trademark of Philips Corporation REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies FUNCTIONAL BLOCK DIAGRAM ADuC832 8051 BASED MCU WITH ADDITIONAL PERIPHERALS 62 kBYTES FLASH EE PROGRAM MEMORY 4 FLASH EE DATA MEMORY 2304 BYTES USER RAM INTERNAL BAND GAP VREF UART AND SPI VREF XTALI XTAL2 GENERAL DESCRIPTION The ADuC832 is a complete smart transducer front end integrat ing a high performance self calibrating multichannel 12 bit ADC dual 12 bit DACs and programmable 8 bit MCU on a single chip The device operates from a 32 kHz crystal with an on chip PLL generating a high frequency clock of 16 77 MHz This clock is in turn routed through a programmable clock divider from which the MCU core clock operating frequency is generated The micro controller core is an 8052 and therefore 8051 instruction set
137. s specified operational clock speed range is 400 kHz to 16 777216 MHz The core itself is static and will function all the way down to dc But at clock speeds slower that 400 kHz the ADC will no longer function correctly Therefore to ensure specified operation use a clock frequency of at least 400 kHz and no more than 16 777216 MHz 61 ADuC832 External Memory Interface In addition to its internal program and data memories the ADuC832 can access up to 64 kBytes of external program memory ROM PROM and so on and up to 16 MBytes of external data memory SRAM To select from which code space internal or external program memory to begin executing instructions tie the EA external access pin high or low respectively When EA is high pulled up to Vpp user program execution will start at address 0 of the internal 62 kBytes Flash EE code space When EA is low tied to ground user program execution will start at address 0 of the external code space A second very important function of the EA pin is described in the Single Pin Emulation Mode section External program memory if used must be connected to the ADuC832 as illustrated in Figure 57 Note that 16 I O lines Ports 0 and 2 are dedicated to bus functions during external program memory fetches Port 0 PO serves as a multiplexed address data bus It emits the low byte of the program counter PCL as an address and then goes into a float state awaiting the arrival of
138. same as the crys tal oscillator frequency The above choice of frequencies ensures that the modulators and the core will be synchronous regardless of the core clock rate The PLL control register is PLLCON PLLCON PLL Control Register SFR Address D7H Power On Default Value 53H Bit Addressable No Table X PLLCON SFR Bit Designations Bit Name Description 7 OSC_PD Oscillator Power Down Bit Set by user to halt the 32 kHz oscillator in power down mode Cleared by user to enable the 32 kHz oscillator in power down mode This feature allows the TIC to continue counting even in power down mode 6 LOCK PLL Lock Bit This is a read only bit Set automatically at power on to indicate the PLL loop is correctly tracking the crystal clock If the external crystal becomes subsequently disconnected the PLL will rail and the core will halt Cleared automatically at power on to indicate the PLL is not correctly tracking the crystal clock This may be due to the absence of a crystal clock or an external crystal at power on In this mode the PLL output can be 16 78 MHz 20 5 Reserved for future use should be written with 0 4 Reserved for future use should be written with 0 3 FINT Fast Interrupt Response Bit Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency regardless of the configuration of the CD2 0 bits see below Once user code has returned from an interrupt
139. same time The time it takes to perform one ADC conver sion is called a DMA cycle The actions performed by the logic during a typical DMA cycle are shown in the following diagram CONVERT CHANNEL READ DURING PREVIOUS DMA CYCLE WRITE ADC RESULT CONVERTED DURING PREVIOUS DMA CYCLE READ CHANNEL ID TO BE CONVERTED DURING NEXT DMA CYCLE DMA CYCLE Figure 16 DMA Cycle From the previous diagram it can be seen that during one DMA cycle the following actions are performed by the DMA logic 1 An ADC conversion is performed on the channel whose ID was read during the previous cycle bo The 12 bit result and the channel ID of the conversion per formed in the previous cycle is written to the external memory o The ID of the next channel to be converted is read from external memory For the previous example the complete flow of events is shown in Figure 16 Because the DMA logic uses pipelining it takes three cycles before the first correct result is written out Micro Operation during ADC DMA Mode During ADC DMA mode the MicroConverter core is free to continue code execution including general housekeeping and communication tasks However note that MCU core accesses to Ports 0 and 2 which of course are being used by the DMA con troller are gated OFF during ADC DMA mode of operation This means that even though the instruction that accesses the external ports 0 or 2 will appear to execute no data will be see
140. should be assumed that these modes of operation are the same for Timer 0 as for Timer 1 Mode 0 13 Bit Timer Counter Mode 0 configures an 8 bit timer counter with a divide by 32 prescaler Figure 45 shows Mode 0 operation CORE CLK C T 0 TLO THO O T 1 5 BITS 8 BITS C T 1 P3 4 TO CONTROL INTERRUPT TFO TRO CORE CLK IS DEFINED BY THE CD BITS IN PLLCON Figure 45 Timer Counter 0 Mode 0 In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the timer overflow flag The overflow flag can then be used to request an interrupt The counted input is enabled to the timer when TRO 1 and either Gate 0 or INTO 1 Setting Gate 1 allows the timer to be controlled by external input INTO to facili tate pulsewidth measurements TRO is a control bit in the special function register TCON Gate is in TMOD The 13 bit register consists of all eight bits of THO and the lower five bits of TLO The upper three bits of TLO are indeterminate and should be ignored Setting the run flag TRO does not clear the registers Mode 1 16 Bit Timer Counter Mode 1 is the same as Mode 0 except that the timer register is running with all 16 bits Mode 1 is shown in Figure 46 INTERRUPT TFO TLO THO 8 BITS 8 BITS CONTROL CORE CLK IS DEFINED BY THE CD BITS IN PLLCON Figure 46 Timer Counter 0 Mode 1 REV 0 Mode 2 8
141. ss is loaded into the program counter The Interrupt Vector Addresses are shown in Table XXXIII Table XXXIII Interrupt Vector Addresses Source Vector Address IEO 0003H TFO 000BH IEI 0013H TFI 001BH RI TI 0023H 2 EXF2 002BH ADCI 0033H 2 003BH PSMI 0043H TI 0053H WDS 005BH REV 0 ADuC832 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design consider ations that must be addressed when integrating the ADuC832 into any hardware system Clock Oscillator The clock source for the ADuC832 can be generated by the internal PLL or by an external clock input To use the internal PLL connect a 32 768 kHz parallel resonant crystal between XTALI and XTAL2 and connect a capacitor from each pin to ground as shown below This crystal allows the PLL to lock cor rectly to give a fyco of 16 777216 MHz If no crystal is present the PLL will free run giving a fyco of 16 7 MHz 20 This is useful if an external clock input is required The part will power up and the PLL will free run the user then in software writes to the CFG832 SFR to enable the external clock input on P3 4 ADuC832 TO INTERNAL TIMING CIRCUITS Figure 55 External Parallel Resonant Crystal Connections ADuC832 EXTERNAL CLOCK SOURCE TO INTERNAL TIMING CIRCUITS Figure 56 Connecting an External Clock Source Whether using the internal PLL or an external clock source the ADuC832
142. stem POFP Package OTHER HARDWARE CONSIDERATIONS To facilitate in circuit programming plus in circuit debug and emulation options users will want to implement some simple connection points in their hardware that will allow easy access to download debug and emulation modes In Circuit Serial Download Access Nearly all ADuC832 designs will want to take advantage of the in circuit reprogrammability of the chip This is accomplished by a connection to the ADuC832 s UART which requires an external RS 232 chip for level translation if downloading code from a PC Basic configuration of an RS 232 connection is illustrated in Figure 64 with a simple ADM202 based circuit If users would rather not design an RS 232 chip onto a board refer to the application note uC006 A 4 Wire UART to PC Interface for a simple and zero cost per board method of gaining in circuit serial download access to the ADuC832 Application Note uC006 is available at www analog com microconverter REV 0 In addition to the basic UART connections users will also need a way to trigger the chip into download mode This is accomplished via a 1 pull down resistor that can be jumpered onto the PSEN pin as shown in Figure 64 To get the ADuC832 into download mode simply connect this jumper and power cycle the device or manually reset the device if a manual reset button is available and it will be ready to receive a new program serially With the jumper removed
143. t be set to the start address of where the ADC results are to be written This is done by writing to the DMA mode address pointers DMAL DMAH and DMAP DMAL must be written to first followed by DMAH and then by DMAP 24 3 The external memory must be preconfigured This consists of writing the required ADC channel IDs into the top four bits of every second memory location in the external SRAM starting at the first address specified by the DMA address pointer As the ADC DMA mode operates independent from the ADuC832 core it is necessary to provide it with a stop command This is done by duplicating the last channel ID to be converted followed by 1111 into the next channel selection field A typical preconfiguration of external memory is as follows 00000AH 1 1 1 1 STOP COMMAND REPEAT LAST CHANNEL FOR A VALID STOP CONDITION CONVERT ADC CH 3 CONVERT TEMP SENSOR CONVERT ADC CH 5 000000H CONVERT ADC CH 2 Figure 14 Typical DMA External Memory Preconfiguration 4 The DMA is initiated by writing to the ADC SFRs in the following sequence a ADCCON2 is written to enable the DMA mode i e MOV ADCCON2 40H DMA mode enabled b ADCCONI is written to configure the conversion time and power up of the ADC It can also enable Timer 2 driven conversions or external triggered conversions if required c ADC conversions are initiated This is done by starting single conversio
144. t in Table XXXIV are given as functions of Mc x the core clock frequency Plug in a value for in hertz to determine the current consumed by the core at that oscillator frequency Since the ADC and DACs can be enabled or disabled in software add only the currents from the peripherals you expect to use And again do not forget to include current sourced by I O pins serial port pins DAC outputs and so forth plus the additional current drawn during Flash EE erase and program cycles A software switch allows the chip to be switched from normal mode into idle mode and also into full power down mode Below are brief descriptions of power down and idle modes Power Saving Modes In idle mode the oscillator continues to run but the core clock generated from the PLL is halted The on chip peripherals continue to receive the clock and remain functional The CPU status is preserved with the stack pointer and program counter and all other internal registers maintain their data during idle mode Port pins and DAC output pins retain their states in this mode The chip will recover from idle mode upon receiving any enabled interrupt or upon receiving a hardware reset In full power down mode both the PLL and the clock to the core are stopped The on chip oscillator can be halted or can continue to oscillate depending on the state of the oscillator power down bit in the PLLCON SFR The TIC being driven directly from 63 ADuC832 the
145. t operation in the following pages TIMER INTERRUPT Figure 49 Timer Counter 2 16 Bit Autoreload Mode TR2 TRANSITION DETECTOR CONTROL EXEN2 CORE CLK IS DEFINED BY THE CD BITS IN PLLCON Ti TH2 wee L2 TIMER INTERRUPT Figure 50 Timer Counter 2 16 Bit Capture Mode REV 0 55 ADuC832 UART SERIAL INTERFACE The serial port is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can com mence reception of a second byte before a previously received byte has been read from the receive register However if the first byte still has not been read by the time reception of the second byte is complete the first byte will be lost The physical interface to the serial data network is via pins RXD P3 0 and TXD P3 1 while the SFR interface to the UART is comprised of SBUF and SCON as described below SBUF The serial port receive and transmit registers are both accessed through the SBUF SFR SFR address 99H Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register SCON UART Serial Port Control Register SFR Address 98H Power On Default Value 00H Bit Addressable Yes Table XXIV SCON SFR Bit Designations Bit Name Description 7 SMO UART Serial Mode Select Bits 6 SMI These bits select the Serial Port operating mode as follows SMO SMI Selected Operating Mode 0 0 Mode 0 Shi
146. t range of 0 to A high precision low drift and factory calibrated 2 5 V reference is provided on chip An external reference can be connected as described later This external reference can be in the range 1 V to AVpp Single step or continuous conversion modes can be initiated in software or alternatively by applying a convert signal to an external pin Timer 2 can also be configured to generate a repeti tive trigger for ADC conversions The ADC may be configured to operate in a DMA mode whereby the ADC block continu ously converts and captures samples to an external RAM space without any interaction from the MCU core This automatic capture facility can extend through a 16 MByte external data memory space The ADuC832 is shipped with factory programmed calibration coefficients that are automatically downloaded to the ADC on power up ensuring optimum ADC performance The ADC core contains internal offset and gain calibration registers that can be hardware calibrated to minimize system errors A voltage output from an on chip band gap reference propor tional to absolute temperature can also be routed through the front end ADC multiplexer effectively a ninth ADC channel input facilitating a temperature sensor implementation ADC Transfer Function The analog input range for the ADC is 0 V to Vag For this range the designed code transitions occur midway between successive integer LSB values i e 1 2 LSB 3 2 LSBs 5 2 L
147. tchdog WDE bit within a predetermined amount of time see PRE3 0 bits in WDCON The watchdog timer itself is a 16 bit counter that is clocked directly from the 32 768 kHz external crystal The watchdog time out interval can be adjusted via the PRE3 0 bits in WDCON Full control and status of the watchdog timer function can be controlled via the watchdog timer control SFR WDCON The WDCON SFR can only be written by user software if the double write sequence described in WDWR below is initiated on every write access to the WDCON SFR WDCON SFR Address Power On Default Value Bit Addressable Watchdog Timer Control Register COH 10H Yes Table XVI WDCON SFR Bit Designations Bit Name Description PRE2 PREI PREO LUD 3 WDIR 2 WDS 1 WDE 0 WDWR Watchdog Timer Prescale Bits The Watchdog timeout period is given by the equation typ 2 x 2 fxrar PRE3 PRE2 PREO Timeout Period ms Action 0 0 0 15 6 Reset or Interrupt 31 2 Reset or Interrupt 62 5 Reset or Interrupt 125 Reset or Interrupt 250 Reset or Interrupt 500 Reset or Interrupt 1000 Reset or Interrupt 2000 Reset or Interrupt 1 0 0 0 0 Immediate Reset PRE3 0 gt 1000 Reserved Watchdog Interrupt Response Enable Bit If this bit is set by the user the watchdog will generate an interrupt response instead of a system reset when the watchdog timeout period has expired This interrupt is not disabled
148. the code byte from the program memory During the time that the low byte of the program counter is valid on the signal ALE Address Latch Enable clocks this byte into an address latch Meanwhile Port 2 P2 emits the high byte of the program counter PCH then PSEN strobes the EPROM and the code byte is read into the ADuC832 ADuC832 EPROM 00 07 INSTRUCTION 0 7 Figure 57 External Program Memory Interface Note that program memory addresses are always 16 bits wide even in cases where the actual amount of program memory used is less than 64 kBytes External program execution sacrifices two of the 8 bit ports PO and P2 to the function of addressing the pro gram memory While executing from external program memory Ports 0 and 2 can be used simultaneously for read write access to external data memory but not for general purpose I O Though both external program memory and external data memory are accessed by some of the same pins the two are completely independent of each other from a software point of view For example the chip can read write external data memory while executing from external program memory Figure 58 shows a hardware configuration for accessing up to 64 kBytes of external RAM This interface is standard to any 8051 compatible MCU 62 ADuC832 Figure 58 External Data Memory Interface 64 K Address Space If access to more than 64 kBytes of RAM is desired a feature unique to the A
149. the user can only The ADuC832 supports a fully licensed serial interface The enable one or the other interface at any given time see SPE in interface is implemented as a full hardware slave and software SPICON previously Application Note uC001 describes the master SDATA is the data I O pin and SCLOCK is the serial operation of this interface as implemented is available from the clock These two pins are shared with the MOSI and SCLOCK MicroConverter website at www analog com microconverter Three SFRs are used to control the interface These are described below I2CCON Control Register SFR Address ESH Power On Default Value 00H Bit Addressable Yes Table I2CCON SFR Bit Designations Bit Name Description 7 MDO Software Master Data Output Bit Master Mode Only This data bit is used to implement a master PC transmitter interface in software Data written to this bit will be output on the SDATA pin if the data output enable MDE bit is set 6 MDE Software Master Data Output Enable Bit Master Mode Only Set by user to enable the SDATA pin as an output Tx Cleared by the user to enable SDATA pin as an input Rx 5 MCO Software Master Clock Output Bit Master Mode Only This data bit is used to implement a master transmitter interface in software Data written to this bit will be output on the SCLOCK pin 4 MDI Software Master Data Input Bit Master Mode Only This data bit
150. up Time before SCLOCK Edge 100 ns 175 tpHD Data Input Hold Time after SCLOCK Edge 100 ns 75 Data Output Fall Time 10 25 ns 75 tpg Data Output Rise Time 10 25 ns 75 tsp SCLOCK Rise Time 10 25 ns 75 tsp SCLOCK Fall Time 10 25 ns 75 Characterized under the following conditions a Core clock divider bits CD2 CDI and CDO bits in PLLCON SFR set to 0 1 and 1 respectively i e core clock frequency 2 09 MHz and b SPI bit rate selection bits SPR1 and SPRO bits in SPICON SFR set to 0 and 0 respectively SCLOCK CPOL 0 4 toy ts tsr SCLOCK CPOL 1 gt MOSI dk zii tosu Figure 75 SPI Master Mode Timing 1 REV 0 73 ADuC832 Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING CPHA 0 ts SCLOCK Low Pulsewidth 476 ns 76 SCLOCK High Pulsewidth 416 ns 76 tpAV Data Output Valid after SCLOCK Edge 50 ns 76 tposu Data Output Setup before SCLOCK Edge 150 ns 76 tpsu Data Input Setup Time before SCLOCK Edge 100 ns 76 tpHD Data Input Hold Time after SCLOCK Edge 100 ns 76 Data Output Fall Time 10 25 ns 76 tpg Data Output Rise Time 10 25 ns 76 tsp SCLOCK Rise Time 10 25 ns 76 tsp SCLOCK Fall Time 10 25 ns 76 Characterized under the following conditions a Core clock divider bits CD2 CDI and bits in PLLCON SFR set to 0 1 and 1 respectively i e core clock frequency 2 09 MHz and b SPI
151. ver the DAC s linearity specification when driving a 10 kQ resistive load to ground is guaranteed through the full transfer function except codes 0 to 100 and in 0 to AVpp mode only codes 3995 to 4095 Linearity degradation near ground and Vpp is caused by saturation of the output amplifier and a general representation of its effects neglecting offset and gain error is illustrated in Figure 22 The dotted line in Figure 22 indicates the ideal transfer function and the solid line represents what the transfer function might look like with endpoint nonlinear ities due to saturation of the output amplifier Note that Figure 22 represents a transfer function in 0 to Vpp mode only In 0 to Veer mode with the lower nonlinearity would be similar but the upper portion of the transfer function would follow the ideal line right to the end in this case not Vpp showing no signs of endpoint linearity errors REV 0 Vpp Vpp 50mV Vpp 100mV 7 000H FFFH Figure 22 Endpoint Nonlinearities Due to Amplifier Saturation The endpoint nonlinearities conceptually illustrated in Figure 22 get worse as a function of output loading Most of the ADuC832 s specifications assume a 10 kQ resistive load to ground at the DAC output As the output is forced to source or sink more current the nonlinear regions at the top or bottom respectively of Figure 22 become larger With larger current demands this can s
152. when powered by a single supply Therefore if a negative supply is available you might consider using it to power the front end amplifiers If you do however be sure to include the Schottky diodes shown in Figure 10 or at least the lower of the two diodes to protect the analog input from undervoltage conditions To summarize this section use the circuit of Figure 10 to drive the analog input pins of the ADuC832 Voltage Reference Connections The on chip 2 5 V band gap voltage reference can be used as the reference source for the ADC and DACs To ensure the accuracy of the voltage reference you must decouple the pin to ground with a 0 1 uF capacitor and the pin to ground with a 0 1 capacitor as shown in Figure 11 ADuC832 2 5V BAND GAP REFERENCE BUFFER BUFFER d Figure 11 Decoupling Vgge and If the internal voltage reference is to be used as a reference for external circuitry the output should be used However buffer must be used in this case to ensure that no current is drawn from the pin itself The voltage on the Crer pin is that of an internal node within the buffer block and its voltage is critical to ADC and DAC accuracy On the ADuC812 was the recommended output for the external reference this can be used but it should be noted that there will be a gain error between this reference and that of the ADC The ADuC832 powers up with its internal vo
153. xtended 11 bit stack pointer By default the stack will operate exactly like an 8052 in that it will roll over from FFH to 00H in the general purpose RAM On the ADuC832 however it is possible by setting CFG832 7 to enable the 11 bit extended stack pointer In this case the stack will roll over from FFH in RAM to 0100H in XRAM The 11 bit stack pointer is visible in the SP and SPH SFRs The SP SFR is located at 81H as with a standard 8052 The SPH SFR is located at B7H The 3 LSBs of this SFR contain the three extra bits necessary to extend the 8 bit stack pointer into an 11 bit stack pointer 07 UPPER 1792 BYTES OF ON CHIP XRAM DATA STACK FOR EXSP 1 DATA ONLY FOR EXSP 0 CFG832 7 0 CFG832 7 1 FFH 256 BYTES OF LOWER 256 BYTES OF ON CHIP DATA RAM ON CHIP XRAM DATA EARS DATA ONLY 00H Figure 3 Extended Stack Pointer Operation REV 0 ADuC832 External Data Memory External XRAM Just like a standard 8051 compatible core the ADuC832 can access external data memory using a MOVX instruction The instruction automatically outputs the various control strobes required to access the data memory The ADuC832 however can access up to 16 MBytes of external data memory This is an enhancement of the 64 kBytes external data memory space available on a standard 8051 compatible core The external data memory is discussed in more detail in the ADuC832 Hardware Design C
154. ys contain 0 1 RSVD Reserved This bit should always contain 0 0 XRAMEN XRAM Enable Bit When set to 1 by the user the internal XRAM will be mapped into the lower 2 kBytes of the external address space When set to 0 by the user the internal XRAM will not be accessible and the external data memory will be mapped into the lower 2 kBytes of external data memory REV 0 31 ADuC832 USER INTERFACE TO OTHER ON CHIP ADuC832 PERIPHERALS The following section gives a brief overview of the various peripherals also available on chip A summary of the SFRs used to control and configure these peripherals is also given DAC The ADuC832 incorporates two 12 bit voltage output DACs on chip Each has a rail to rail voltage output buffer capable of driving 10 100 pF Each has two selectable ranges 0 V to Veer the internal band gap 2 5 V reference and 0 V to AVpp Each can operate in 12 bit or 8 bit mode Both DACs share a control register DACCON and four data registers DACIH L DACOHIL It should be noted that in 12 bit asynchronous mode the DAC voltage output will be updated as soon as the DACL data SFR has been written therefore the DAC data registers should be updated as DACH first followed by DACL Note for correct DAC operation on the 0 to range the ADC must be switched on This results in the DAC using the correct reference value DACCON DAC Control Register SFR Address FDH Power On Def

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