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ANALOG DEVICES AD824 Manual

1. 0 1 q e 0 010 I E s Z i z E E o E E 0 001 D rs mL o E 2 a zZ 0 0001 20 1k 10k 20k FREQUENCY Hz 60 40 20 0 20 40 60 80 100 120 140 TEMPERATURE C TPC 11 Total Harmonic Distortion TPC 14 Input Offset Current vs Temperature 280 100k 240 i k o 200 E I 5 E 2 160 a o f 4 oi 3 W420 2 2 2 am 80 E 2 a z 40 0 0 5 0 4 0 3 0 2 0 1 0 01 02 03 04 05 20 40 60 80 100 120 140 OFFSET VOLTAGE mV TEMPERATURE C TPC 12 Input Offset Distribution Vs 5 0 TPC 15 Input Bias Current vs Temperature 8 REV C 120 o o o o o D o COMMON MODE REJECTION dB N o 0 10 100 1k 10k 100k 1M 10M FREQUENCY Hz TPC 16 Common Mode Rejection vs Frequency 40 60 80 THD dB 100 120 100 1k 10k 100k FREQUENCY Hz TPC 17 THD vs Frequency 3 V rms o o 2B o OPEN LOOP GAIN dB N PHASE MARGIN Degrees 10 100 1k 10k 100k 1M 10M FREQUENCY Hz TPC 18 Open Loop Gain and Phase vs Frequency REV C AD824 1k 100 10 INPUT VOLTAGE NOISE nV VHz 10 100 ik 10k 100k FREQUENCY Hz TPC 19 Input Voltage Noise Spectral Density vs
2. R23 18 98 1E6 C15 18 98 15 9E 15 REV C 15 AD824 OUTLINE DIMENSIONS 14 Lead Standard Small Outline Package SOIC Narrow Body R 14 Dimensions shown in millimeters and inches 8 75 0 3445 a 8 55 03386 4 00 0 1575 81 6 20 0 2441 3 80 0 1496 71 7 5 80 0 2283 gt e 1 27 0 0500 1 75 0 0689 0 50 0 0197 A 0 25 0 0098 BSC 1 35 0 0531 gt 0 25 0 0098 5 0 10 0 0039 mamma PE 4 ole Pte ae COPLANARITY SS SEATING 0 25 0 0098 0 1 27 0 0500 0 10 33 0 0130 0 19 0 0075 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 012AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History 16 Lead Standard Small Outline Package SOIC Wide Body R 16 Dimensions shown in millimeters and inches 7 60 0 2992 7 40 0 2913 10 65 0 4193 10 00 0 3937 0 75 0 0295 27 0 2 65 0 1043 BSC 2 65 0 1043 0 75 0 0295 0 25 0 0098 9 2 35 0 0925 0 30 0 0118 4 elle 0 51 0 0201 SEATING 0 33 0 0130 PLANE 8 0 32 0 0126 0 23 0 0091 COMPLIANT TO JEDEC STANDARDS MS 013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALE
3. Frequency o o o POWER SUPPLY REJECTION dB gt o N o 10 100 1k 10k 100k 1M 10M FREQUENCY Hz TPC 20 Power Supply Rejection vs Frequency 30 25 20 OUTPUT VOLTAGE Volts 1k 3k 10k 30k 100k 300k 1M INPUT FREQUENCY Hz TPC 21 Large Signal Frequency Response SAY CROSSTALK dB L 3 10 100 1k 10k 100k FREQUENCY Hz TPC 22 Crosstalk vs Frequency 100 OUTPUT IMPEDANCE 3 10 100 1k 10k 100k 1M 10M FREQUENCY Hz TPC 23 Output Impedance vs Frequency Gain 1 da LIED fme Ep EL ERI EM DCN PEAS oun RR RS AAA e e e TPC 24 Small Signal Response Unity Gain Follower 10k 100 pF Load 10 TPC 25 Large Signal Response SUPPLY CURRENT yA 60 40 20 0 20 40 60 80 100 120 140 TEMPERATURE C TPC 26 Supply Current vs Temperature vs 15V gt PYs 30 1 w E 100 5 o gt E VoL Vs 4 e Pp 10 Vs Von 4 D E 5 a E 3 o 0 0 01 0 10 1 0 10 0 LOAD CURRENT mA TPC 27 Output Saturation Voltage REV C AD824 APPLICATION NOTES INPUT CHARACTERISTICS In the AD824 n channel JFETs are used to provide a low offset low noise high impedance input stage Minimum input common mode voltage extends from 0 2 V below Vs to 1 V less
4. than Vs Driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth The AD824 does not exhibit phase reversal for input voltages up to and including Vs Figure 2a shows the response of an AD824 voltage follower to a 0 V to 5 V Vs square wave input The input and output are superimposed The output tracks the input up to Vg without phase reversal The reduced bandwidth above a 4 V input causes the rounding of the output wave form For input voltages greater than Vs a resistor in series with the AD824 s noninverting input will prevent phase reversal at the expense of greater input voltage noise This is illustrated in Figure 2b Figure 2 a Response with Rp 0 Vy from 0 to Vs b Vy 2 0 to Vs 200m V Vour Oto Vs Rp 49 9 KQ Since the input stage uses n channel JFETs input current during normal operation is positive the current flows out from the input terminals If the input voltage is driven more positive than Vs 0 4 V the input current will reverse direction as internal device junctions become forward biased This is illustrated in TPC 8 REV C A current limiting resistor should be used in series with the input of the AD824 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mV or if an input voltage will be applied to the AD824 when V 0 The amplifier will be damaged if left in that condition for more than 10 seconds A
5. 1M 10M MER v ARRE EES Ta eel alae a T 2a eee TTE ee TARRE Na a Aa TPC 2 Open Loop Gain Phase and Small Signal TPC 4 Open Loop Gain Phase and Small Signal Response Vs 15 V C 100 pF Response Vs 5 V C 220 pF 6 REV C 60 Vs 23V NO LOAD 40 z 45 9 Uv g 420 90 3 3 135 7 0 180 a 20 1k 10k 100k 1M 10M TERES ETE NR ES MEL Ap eee a a ama SI Ole Seri TPC 5 Open Loop Gain Phase and Small Signal TPC 7 Slew Rate R 10k Response Vs 3 V No Load 60 Vs 3V_ A a EET C 220pF ANE TEATA AOS wg mE SN m P AA DH z on AI EIA T L d Xen ede exin rw 20 1k 10k 100k 1M 10M g El a AE E mE E m g A Es ed PA 2 RIE Aba 3 Ee E samy ET fs ie 5p 10p 50p 100p 500p 1m 5m 10m LOAD CURRENT A TPC 6 Open Loop Gain Phase and Small Signal TPC 9 Output Voltage to Supply Rail vs Sink and Source Response Vs 3 V C 220 pF Load Currents REV C 7 AD824 NOISE DENSITY nV VAz_ NUMBER OF UNITS 5 10 15 20 FREQUENCY kHz 0 2 5 2 0 1 5 1 0 05 0 05 10 15 20 25 OFFSET VOLTAGE DRIFT TPC 10 Voltage Noise Density TPC 13 TC Vos Distribution 55 C to 125 C Vs 5 0
6. Supply Rejection Ratio PSRR Vs 2 7Vto 15V 70 80 dB Tmn to Tmax 68 dB Supply Current Amplifier Isy Vo 0V 560 625 uA Tmn to Tmax 675 uA DYNAMIC PERFORMANCE Slew Rate SR R 10 kQ Ay 1 2 V us Full Power Bandwidth BWp 1 Distortion Vo 20 V p p 33 kHz Settling Time ts Vour 0 V to 10 V to 0 01 6 us Gain Bandwidth Product GBP 2 MHz Phase Margin Qo 50 Degrees Channel Separation CS f 1 kHz Ry 2 kQ 123 dB NOISE PERFORMANCE Voltage Noise n P P 0 1 Hz to 10 Hz uV p p Voltage Noise Density en f 1kHz 16 nV VHz Current Noise Density ln f 1 kHz 1 1 fAN Hz Total Harmonic Distortion THD f 10 kHz Vo 3 V rms Ry 10 kQ 0 005 REV C AD824 SPECIFICATIONS ELECTRICAL SPECIFICATIONS O Vs 3 0 V Ven 0 V Vgy 0 2 V T 25 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage AD824A 3 V Vos 0 2 1 0 mV Tyan to Tmax 1 5 mV Input Bias Current Ip 2 12 pA Tmn to Tmax 250 4000 pA Input Offset Current Ios 2 10 pA Tyan to Tax 250 pA Input Voltage Range 0 1 V Common Mode Rejection Ratio CMRR Vem 0V tol V 58 74 dB Twn to Tmax 56 dB Input Impedance 103 3 QlpF Large Signal Voltage Gain Avo Vo 0 2 V to 2 0 V Ry 2 kQ 10 20 V mV Ry 10 kQ 30 65 V mV R 100 kQ 180 500 V mV Twn to Tmax R 100 kQ 90 250 V mV Offset Voltage Drift AVos AT 2 uv C OUTPUT CHARACTERISTICS Output Voltage High Von Isource 20 uA 2 075 2 988 V Tmn to Tmax 2 97 2 985 V I
7. TO A D CONVERTER REFERENCE INPUT Figure 7 Low Dropout Bipolar Bridge Driver REV C of 4 5 V can be used to drive an A D converter front end The other half of the AD824 is configured as a unity gain inverter and generates the other bridge input of 4 5 V Resistors R1 and R2 provide a constant current for bridge excitation The AD620 low power instrumentation amplifier is used to condition the differential output voltage of the bridge The gain of the AD620 is programmed using an external resistor Rg and determined by 49 4 kQ LIU Re G 1 A 3 3 V 5 V Precision Sample and Hold Amplifier In battery powered applications low supply voltage operational amplifiers are required for low power consumption Also low supply voltage applications limit the signal range in precision analog circuitry Circuits like the sample and hold circuit shown in Figure 8 illustrate techniques for designing precision analog circuitry in low supply voltage applications To maintain high signal to noise ratios SNRs in a low supply voltage application requires the use of rail to rail input output operational amplifi ers This design highlights the ability of the AD824 to operate rail to rail from a single 3 V 5 V supply with the advantages of high input impedance The AD824 a quad JFET input op amp is well suited to S H circuits due to its low input bias currents 3 pA typical and high input impedances 3 x 10 Q typical The AD824 also exhibits ve
8. 1 kQ resistor allows the amplifier to withstand up to 10 V of continuous overvoltage and increases the input volt age noise by a negligible amount Input voltages less than Vs are a completely different story The amplifier can safely withstand input voltages 20 V below the minus supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 V In addition the input stage typically maintains picoamp level input currents across that input voltage range OUTPUT CHARACTERISTICS The AD824 s unique bipolar rail to rail output stage swings within 15 mV of the positive and negative supply voltages The AD824 s approximate output saturation resistance is 100 Q for both sourcing and sinking This can be used to estimate output saturation voltage when driving heavier current loads For instance the saturation voltage will be 0 5 V from either supply with a 5 mA current load For load resistances over 20 kO the AD824 s input error voltage is virtually unchanged until the output voltage is driven to 180 mV of either supply If the AD824 s output is overdriven so as to saturate either of the output devices the amplifier will recover within 2 us of its input returning to the amplifier s linear operating region Direct capacitive loads will interact with the amplifier s effective output impedance to form an additional pole in the amplifier s feedback loop which can cause excessive peaking on the pu
9. 3 R4 OHMTEK PART 1043 Figure 5b A Single Supply Programmable Instrumentation Amplifier REV C AD824 3 Volt Single Supply Stereo Headphone Driver The AD824 exhibits good current drive and THD N perfor mance even at 3 V single supplies At 1 kHz total harmonic distortion plus noise THD N equals 62 dB 0 079 for a 300 mV p p output signal This is comparable to other single supply op amps that consume more power and cannot run on 3 V power supplies In Figure 6 each channels input signal is coupled via a 1 uF Mylar capacitor Resistor dividers set the dc voltage at the noninverting inputs so that the output voltage is midway between the power supplies 1 5 V The gain is 1 5 Each half of the AD824 can then be used to drive a headphone channel A 5 Hz high pass filter is realized by the 500 uF capacitors and the headphones which can be modeled as 32 ohm load resistors to ground This ensures that all signals in the audio frequency range 20 Hz 20 kHz are delivered to the headphones 1pF CHANNEL 1 0 MYLAR 95 3kQ HEADPHONES 320 IMPEDANCE 1pF CHANNEL 2 0 MYLAR Figure 6 3 Volt Single Supply Stereo Headphone Driver Low Dropout Bipolar Bridge Driver The AD824 can be used for driving a 350 ohm Wheatstone bridge Figure 7 shows one half of the AD824 being used to buffer the AD589 a 1 235 V low power reference The output Vs 49 9k0 1 235V__ gt 2 Apsso
10. DABS BRAGA Mes MA AURA ANALO DEVICES Single Supply Rail to Rail Low Power FET Input Op Amp AD824 FEATURES Single Supply Operation 3 V to 30 V Very Low Input Bias Current 2 pA Wide Input Voltage Range Rail to Rail Output Swing Low Supply Current 500 pA Amp Wide Bandwidth 2 MHz Slew Rate 2 V ps No Phase Reversal APPLICATIONS Photo Diode Preamplifier Battery Powered Instrumentation Power Supply Control and Protection Medical Instrumentation Remote Sensors Low Voltage Strain Gage Amplifiers DAC Output Amplifier GENERAL DESCRIPTION The AD824 is a quad FET input single supply amplifier fea turing rail to rail outputs The combination of FET inputs and rail to rail outputs makes the AD824 useful in a wide variety of low voltage applications where low input current is a primary consideration The AD824 is guaranteed to operate from a 3 V single supply up to 15 V dual supplies AD824AR 3V Parametric Perfor mance at 3 V is fully guaranteed Fabricated on ADI s complementary bipolar process the AD824 has a unique input stage that allows the input voltage to safely extend beyond the negative supply and to the positive supply without any phase inversion or latchup The output voltage swings to within 15 mV of the supplies Capacitive loads to 350 pF can be handled without oscillation REV C Information furnished by Analog Devices is believed to be accurate and re
11. NTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN gt le 1 27 0 0500 COPLANARITY LA hee 0 10 0 40 0 0157 Location Page 2 03 Data Sheet changed from REV B to REV C Deleted N Paekage 1t eb dte dete Pr ER ITO AC goes deci de IR reg wg eee Ye uenis Universal Edits to GENERA DESCRIPTION ire tte mese deve do Ret eee er Heer PW veente e ee e vuota 1 Edits to ABSOLUTE MAXIMUM RATINGS veraa ia a a a a a a a A a S O a a a a EE 5 Edits to ORDERING GUIDE aki A A nt e EE i Re cete oh ee Oe TERR 5 Edits to Eigured s ot O EN EAEE ea E N RE RO 12 Editsito Eigure 8 i4 e as a thee eb re ev ds IA iretur dis Pee AEE 13 Updated OUTLINE DIMENSIONS sodi cimet Re ee REA pex EVA Re FIRE NDS HA de Roh gos 16 1 02 Data Sheet changed from REV A to REV B Edits to ELECTRICAL SPECIFICATIONS eee hh hah 2 3 Edits to ABSOLUTE MAXIMUM RATINGS eeee eee ehh hr hr ras 5 Edits to ORDERING GUIDE d p RR UE Are UR COR S COUR Soa Ais Reals Re ee CAUCA REOR AURORA EUR EUR 5 Deleted DIGE CHARACTERISTICS 12 2 5t ori tm RUE EOS Re Re Pm SH GAS e sies decken dob ae 5 16 REV C C00875 0 2 03 C PRINTED IN U S A
12. andwidth Product GBP 2 MHz Phase Margin oo No Load 50 Degrees Channel Separation CS f 1 kHz R 2 kQ 123 dB NOISE PERFORMANCE Voltage Noise n P P 0 1 Hz to 10 Hz 2 uV p p Voltage Noise Density n f 1 kHz 16 nV VHz Current Noise Density 15 f 1 kHz 0 8 fA VHz Total Harmonic Distortion THD f 10 kHz R 0 Ay 1 0 005 REV C ELECTRICAL SPECIFICATIONS O Vs 15 0 V Voy 0 V T 25 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage AD824A Vos 0 5 2 5 mV Tm to Tmax 0 6 4 0 mV Input Bias Current Ig Vem 0V 4 35 pA Tmn to Tmax 500 4000 pA Ig Vem 10V 25 pA Input Offset Current los 3 20 pA Twn to Tmax 500 pA Input Voltage Range 15 13 V Common Mode Rejection Ratio CMRR Vom 7 15 V to 13 V 70 80 dB Turn to Tmax 66 dB Input Impedance 103 3 O pF Large Signal Voltage Gain Avo Vo 10 V to 10 V R 2kQ 12 50 V mV Ry 10 kQ 50 200 V mV R 100 kQ 300 2000 V mV Tyan to Tmax RL 100 kQ 200 1000 V mV Offset Voltage Drift AVos AT 2 uv C OUTPUT CHARACTERISTICS Output Voltage High Von Isource 20 uA 14 975 14 988 V Tsource 2 5 mA 14 80 14 85 V Tmn to Tmax 14 75 14 82 V Output Voltage Low Vor Isinx 20 pA 14 985 14 975 V Tmn to Tmax 14 98 14 97 V Isinx 2 5 mA 14 88 14 85 V TMN to Tmax 14 86 14 8 V Short Circuit Limit Isc Sink Source Tm to Tmax 8 20 mA Open Loop Impedance Zout f 1 MHz Ay 1 100 Q POWER SUPPLY Power
13. c All rights reserved AD824 SPECIFICATIONS ELECTRICAL SPECIFICATIONS o v sov v 0 v Voyr 0 2 V T 25 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage AD824A Vos 0 1 1 0 mV Tmn to Tmax 1 5 mV Input Bias Current Ip 2 12 pA TMN to Tmax 300 4000 pA Input Offset Current Ios 2 10 pA TMN to Tmax 300 pA Input Voltage Range 0 2 3 0 V Common Mode Rejection Ratio CMRR Vem 0V to2V 66 80 dB Vem 0V to3V 60 74 dB Twn to Tax 60 dB Input Impedance 103 3 O pF Large Signal Voltage Gain Avo Vo 0 2 V to 4 0 V Ry 2 kQ 20 40 V mV Ry 10 kQ 50 100 V mV Ry 100 kQ 250 1000 V mV Twn to Tmax Ry 100 kQ 180 400 V mV Offset Voltage Drift AVos AT 2 uv C OUTPUT CHARACTERISTICS Output Voltage High Vou Isource 20 HA 4 975 4 988 V Tmn to Tmax 4 97 4 985 V Isouncg 2 5 mA 4 80 4 85 V Tmn to Tmax 4 75 4 82 V Output Voltage Low VoL Isinx 20 pA 15 25 mV Tmn to Tmax 20 30 mV Igmwk 2 5 mA 120 150 mV Tmn to Tmax 140 200 mV Short Circuit Limit Isc Sink Source 12 mA Twn to Tax 10 mA Open Loop Impedance ZouT f 1 MHz Ay 1 100 Q POWER SUPPLY Power Supply Rejection Ratio PSRR Vs 2 7 V to 12 V 70 80 dB TMN to Tmax 66 dB Supply Current Amplifier Isy Tmn to Tmax 500 600 uA DYNAMIC PERFORMANCE Slew Rate SR Ry 10 kQ Ay 1 2 V us Full Power Bandwidth BWp 1 Distortion Vo 4 V p p 150 kHz Settling Time ts Vout 0 2 V to 4 5 V to 0 01 2 5 us Gain B
14. cts into the inverting input of A3 This creates a common mode voltage across the inputs of A3 and is then rejected by the CMR of A3 otherwise the charge injection from SW1 would create a differential voltage step error that would appear at Voyr The pedestal error for this circuit is 14 less than 2 mV over the entire 0 V to 3 3 V 5 V signal range Another method of reducing pedestal error is to reduce the pulse amplitude applied to the control pins In order to control the ADG513 only 2 4 V are required for the ON state and 0 8 V for the OFF state If possible use an input control signal whose amplitude ranges from 0 8 V to 2 4 V instead of a full range 0 V to 3 3 V 5 V for minimum pedestal error Other circuit features include an acquisition time of less than 3 us to 1 reducing Cy and C2 will speed up the acquisition time further but an increased pedestal error will result Settling time is less than 300 ns to 1 and the sample mode signal BW is 80 kHz The ADG513 was chosen for its ability to work with 3 V 5 V supplies and for having normallyopen and normallyclosed preci sion CMOS switches on a dielectrically isolated process SW2 is not required in this circuit however it was used in parallel with SW3 to provide a lower Ron analog switch REV C AD824 AD824 SPICE Macro model 9 94 Rev A G15 98 18 9 98 1E 6 ARG ADI OUTPUT STAGE Copyright 1994 by Analog Devices Inc ii ES 26 98 Re
15. fer to README DOC file for License Statement 18 98 1 Use of this model indicates your acceptance with RS 26 22 the terms and provisions in the License Statement 500 Node assignments IBI 98 21 noninverting input 2 404E 3 inverting input IB2 23 98 positive supply 2 404E 3 negative supply D10 21 98 e output DY E aed Te D11 98 23 SUBCKT AD824 DY 1 2 995025 C16 20 25 K 2E 12 INPUT STAGE amp POLE AT 3 1 MHz C17 24 25 2E 12 R3 5 99 DQ197 20 1 193E3 DQ R4 6 99 Q2 20 21 1 193E3 22 NPN CIN 1 2 Q3 24 23 4E 12 22 PNP C2 5 6 DQ224 51 19 229E 12 DQ I14 50 108E 6 Q5 25 20 IOS 1 2 97 PNP 20 1E 12 Q6 25 24 EOS 7 1 51 NPN 20 POLY 1 12 98 100E 6 1 VP 96 97 ji4 2 5 0 JX VN 51 52 J24 7 6 0 JX EP 96 0 99 0 1 GAIN STAGE amp DOMINANT POLE EN 52 0 50 0 1 EREF 98 R25 30 99 0 30 0 1 5E6 R5 9 98 R26 30 50 2 205E6 5E6 C3 9 25 FSYI 99 54E 12 0 VP 1 Gl 98 9 FSY2 0 6 5 0 838E 3 50VN 1 V1 8 98 DC1 25 99 1 DX V2 98 10 DC250 25 1 DX D1 9 10 DX MODELS USED D2 8 9 DX MODEL JX NJF BETA 3 2526E 3 VTO 2 000 IS 2E 12 MODEL i NPN NPN BF 120 VAF 150 VAR 15 RB 2E3 COMMON MODE GAIN NETWORK WITH ZERO AT 1 kHz RE 4 RC 550 IS 1E 16 R21 11 12 MODEL PNP PNP BF 120 VAF 150 VAR 15 RB 2E3 RE 4 1E6 RC 750 IS 1E 16 R22 12 98 MODEL DX D IS 1E 15 100 MODEL DY D0 C14 11 12 MODEL DQ D IS 1E 16 159E 12 ENDS AD824 E13 11 98 POLY 2 2 98 1 98 0 0 5 0 5 POLE AT 10 MHz
16. ge Description Option AD824AR 14 40 C to 85 C 14 Pin SOIC R 14 AD824AR 14 3V 40 C to 85 C 14 Pin SOIC R 14 AD824AR 16 40 C to 85 C 16 Pin SOIC R 16 CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD824 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality aT Aa Tt SENSITIVE DEVICE REV C AD824 Typical Performance Characteristics eo N LOAD E N LOAD 60 60 gt 2 40 40 E 45 9 E 45 9 20 so P 20 90 P 135 1964 0 180 z 0 180 n 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M TPC 1 Open Loop Gain Phase and Small Signal TPC 3 Open Loop Gain Phase and Small Signal Response V 15 V No Load Response Vs 5 V No Load 25 Vg 15V C 100pF 60 z z 45 g 20 90 F 135 o 0 180 n 100 1k 10k 100k
17. liable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies PIN CONFIGURATIONS 14 Lead Epoxy SOIC 16 Lead Epoxy SOIC R Suffix R Suffix OUT A STR E IND IN D HMM AD824 e v o i Not le Scala NC i NC ANB OUTC OUTB NC NC NO CONNECT The FET input combined with laser trimming provides an input that has extremely low bias currents with guaranteed offsets below 1 mV This enables high accuracy designs even with high source impedances Precision is combined with low noise making the AD824 ideal for use in battery powered medical equipment Applications for the AD824 include portable medical equipment photo diode preamplifiers and high impedance transducer amplifiers The ability of the output to swing rail to rail enables designers to build multistage filters in single supply systems and maintain high signal to noise ratios The AD824 is specified over the extended industrial 40 C to 85 C temperature range and is available in narrow 14 lead and 16 lead SOIC packages One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 O 2003 Analog Devices In
18. lse response or loss of stability Worst case is when the amplifier is used as a unity gain follower TPC 4 and 6 show the AD824 s pulse response as a unity gain follower driving 220 pF Configu rations with less loop gain and as a result less loop bandwidth will be much less sensitive to capacitance load effects Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use Figure 3 shows a method for extending capacitance load drive capability for a unity gain follower With these component val ues the circuit will drive 5 000 pF with a 10 overshoot Ss 0 015F 20k0 Figure 3 Extending Unity Gain Follower Capacitive Load Capability Beyond 350 pF 11 AD824 APPLICATIONS Single Supply Voltage to Frequency Converter The circuit shown in Figure 4 uses the AD824 to drive a low power timer which produces a stable pulse of width t The positive going output pulse is integrated by R1 C1 and used as one input to the AD824 which is connected as a differential integrator The other input nonloading is the unknown voltage Vin The AD824 output drives the timer trigger input closing the overall feedback loop 10V O R2 499kQ 1 499kQ 1 OVTO 2 5V FULLSCALE 6 0 01p F 2 four V VREF x t t 1 1 x R3 x C6 25kHz fg AS SHOWN 1 METAL FILM lt 50ppm C TC 10 20T FILM lt 100ppm C TC t 33us FOR foyr 20kHz O V yy 2 0V Figure 4 Si
19. ngle Supply Voltage to Frequency Converter Typical AD824 bias currents of 2 pA allow megaohm range source impedances with negligible dc errors Linearity errors on the order of 0 01 full scale can be achieved with this circuit This performance is obtained with a 5 V single supply which delivers less than 3 mA to the entire circuit Single Supply Programmable Gain Instrumentation Amplifier The AD824 can be configured as a single supply instrumenta tion amplifier that is able to operate from single supplies down to 5 V or dual supplies up to 15 V AD824 FET inputs 2 pA bias currents minimize offset errors caused by high unbalanced source impedances An array of precision thin film resistors sets the in amp gain to be either 10 or 100 These resistors are laser trimmed to ratio match to 0 01 and have a maximum differential TC of 5 ppm C 2 Table I AD824 In Amp Performance Parameters Vs 3V 0V Vs 5V CMRR 74 dB 80 dB Common Mode Voltage Range 0 2 V to 2 V 5 2 V to 4 V 3dB BW G 10 180 kHz 180 kHz G 100 18 kHz 18 kHz tsETTLING 2 V Step Vs 0 V 3 V 2 us 5 V Vs 5 V 5 ys Noise f 1 kHz G 10 270nVWHz 270 nV VHz G 100 2 2 uVAHz 2 2 UV Hz Figure 5a Pulse Response of In Amp to a 500 mV p p Input Signal Vs 5 V 0 V Gain 10 1kQ R6 G 10 V our Ving V N2 1 OUT IN1 IN2 R4 R5 R5 R6 G 100 V our Vins Vina 177 FOR R1 R6 R2 R5 AND R
20. ry low supply currents so the total supply current in this circuit is less than 2 5 mA 3 3 5V 3 3 5V O AD824B 7 AD824D V 02 5 35 FG r d ad 14 SAMPLE 13 FG Figure 8 3 3 V 5 5 V Precision Sample and Hold In many single supply applications the use of a false ground generator is required In this circuit R1 and R2 divide the supply voltage symmetrically creating the false ground voltage at one half the supply Amplifier A1 then buffers this voltage creating a low impedance output drive The S H circuit is con figured in an inverting topology centered around this false ground level 13 AD824 A design consideration in sample and hold circuits is voltage droop at the output caused by op amp bias and switch leakage currents By choosing a JFET op amp and a low leakage CMOS switch this design minimizes droop rate error to better than 0 1 uV us in this circuit Higher values of Cy will yield a lower droop rate For best performance Cy and C2 should be poly styrene polypropylene or Teflon capacitors These types of capacitors exhibit low leakage and low dielectric absorption Addi tionally 1 metal film resistors were used throughout the design In the sample mode SW1 and SW4 are closed and the output is Vour Viy The purpose of SW4 which operates in parallel with SW1 is to reduce the pedestal or hold step error by injecting the same amount of charge into the noninverting input of A3 that SW1 inje
21. souRCE 2 5 mA 2 8 2 85 V Twn to Tax 2 75 2 82 V Output Voltage Low VoL Isivx 20 yA 15 25 mV Tmn to Tmax 20 30 mV Ismk 2 5 mA 120 150 mV Tmn to Tmax 140 200 mV Short Circuit Limit Isc Sink Source 8 mA Isc Sink Source Tmn to Tmax mA Open Loop Impedance Zour f 1 MHz Ay 1 100 Q POWER SUPPLY Power Supply Rejection Ratio PSRR Vs 2 7 V to 12 V 70 dB Twn to Tax 66 dB Supply Current Amplifier Isy Vo 0 2 V Tun to Tmax 500 600 uA DYNAMIC PERFORMANCE Slew Rate SR Ri 10 kQ Ay 1 2 V us Full Power Bandwidth BW 1 Distortion Vo 2 V p p 300 kHz Settling Time ts Vour 0 2 V to 2 5 V to 0 01 2 us Gain Bandwidth Product GBP 2 MHz Phase Margin oo 50 Degrees Channel Separation CS f 1 kHz Ry 2 KQ 123 dB NOISE PERFORMANCE Voltage Noise n P P 0 1 Hz to 10 Hz 2 uV p p Voltage Noise Density en f 1kHz 16 nV VHz Current Noise Density La 0 8 fANHz Total Harmonic Distortion THD f 10kHz R 0 Ay l1 0 01 REV C AD824 WAFER TEST LIMITS e v 5 0 v Vey 0 V T 25 C unless otherwise noted Parameter Symbol Conditions Limit Unit Offset Voltage Vos 1 0 mV max Input Bias Current Ip 12 pA max Input Offset Current los 20 pA Input Voltage Range Vem 0 2 to 3 0 V min Common Mode Rejection Ratio CMRR Vom 0Vto2V 66 dB min Power Supply Rejection Ratio PSRR V 2 7 V to 12 V 70 uV V Large Signal Voltage Gain Ayo R 2kQ 15 V mV min Output Voltage High Vou Isource 20 uA 4 975 V min Output Voltage Low VoL Ign
22. x 20 yA 25 mV max Supply Current Amplifier Isy Vo 0V RL 600 uA max NOTE Electrical tests and wafer probe to the limits shown Due to variations in assembly methods and normal yield loss yield after packaging is not guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing ABSOLUTE MAXIMUM RATINGS Storage Temperature Range R 14 R 16 Packages V Supply Voltag iier Rr xe hb TR Roe de s 18 V Input Voltage 2 4 tena danos Vs 0 2 V to Vs 16 Differential Input Voltage oooo oooomomoo o 30 V R1 T Output Short Circuit Duration to GND Indefinite Q21 1 Operating Temperature Range AD824A Junction Temperature Range E J1 IN L gt R13 IN a R 14 R 16 Packages o ooooo 65 C to 150 C Lead Temperature Range Soldering 60 sec 300 C pau Lo Package Type Oya Oc Unit cs 14 Lead SOIC R 120 36 C W 16 Lead SOIC R 92 27 C W Sto NOTES E Q28 e a26 Absolute maximum ratings apply to packaged parts unless otherwise noted Qu Da 2 Oja is specified for the worst case conditions i e Oj is specified for device in socket for P DIP packages Oya is specified for device soldered in circuit board for SOIC package m ORDERING GUIDE Figure 1 Simplified Schematic of 1 4 AD824 Temperature Package Package Model Ran

ANALOG DEVICES AD824 Manual

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