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ANALOG DEVICES AD7674 handbook(1)

1. 2 0 2 0 1 5 1 5 e 210 a 1 0 PITT m Mili ao 2 m 0 5 m 05 m a 3 E E 0 z o 0 5 0 5 1 0 1 5 1 0 0 65536 131072 196608 262144 CODE 03083 0 005 Figure 5 Integral Nonlinearity vs Code 70000 60000 50000 40000 z 2 30000 20000 10000 0 2004C 2004D 2004E 2004F 20050 20051 20052 20053 20054 20055 CODE IN HEX 03083 0 006 Figure 6 Histogram of 131 072 Conversions of a DC Input at the Code Transition 120 100 90 100 7 70 2 80 2 Z Z 60 I Lu o O 50 Q 60 a 2 40 P 2 40 Z 30 20 20 10 0 0 0 0 5 1 0 1 5 2 0 2 5 POSITIVE INL LSB 03083 0 007 Figure 7 Typical Positive INL Distribution 424 Units Rev 0 Page 12 of 28 65536 131072 CODE 196608 262144 03083 0 008 Figure 8 Differential Nonlinearity vs Code 0 2004D 2004E 2004F 20050 20051 20052 20053 20054 20055 CODE IN HEX 03083 0 009 Figure 9 Histogram of 131 072 Conversions of a DC Input at the Code Center 2 0 1 5 1 0 NEGATIVE INL LSB 0 5 0 03083 0 010 Figure 10 Typical Negative INL Distribution 424 Units 120 100 NUMBER OF UNITS POSITIVE DNL LSB 1 5 2 0 03083 0 011 Figure 11 Typical Positive DNL Distribution 424 Units AMPLITUDE dB of Full Scale AMPLITUDE dB of Full Scale fs 800kSPS fin 10kHz Vrer 4 096V SNR 98 4dB THD 119 1dB
2. 100 THD HARMONICS dB I N 1 iJ eo Sd 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C 03083 0 019 Figure 19 THD and Harmonics vs Temperature Rev 0 Page 14 of 28 OPERATING CURRENTS uA POWER DOWN OPERATING CURRENTS nA ZERO ERROR POSITIVE AND NEGATIVE FULL SCALE LSB o 100000 AVDD WARP NORMAL 10000 DVDD WARP NORMAL 1000 100 AVDD IMPULSE 10 DVDD IMPULSE PDBUF HIGH OVDD ALL MODES 10 100 1k 10k 100k 1M SAMPLING RATE SPS 03083 0 020 Figure 20 Operating Current vs Sampling Rate 800 700 600 H 25 45 55 35 15 5 400 TEMPERATURE C 03083 0 021 Figure 21 Power Down Operating Currents vs Temperature 25 NEGATIVE FULL SCALE ZERO ERROR 10 POSITIVE FULL SCALE 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C 03083 0 022 Figure 22 Zero Error Positive and Negative Full Scale vs Temperature 30 N o POSITIVE FULL SCALE o ZERO ERROR o ZERO ERROR POSITIVE AND NEGATIVE FULL SCALE LSB e N o 4 50 4 75 5 00 5 25 5 50 AVDD V 03083 0 023 Figure 23 Zero Error Positive and Negative Ful
3. 5 V OVDD 2 7 V to 5 25 V unless otherwise noted AD7674 Parameter Conditions Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range Vine Vin VREF Vrer V Operating Input Voltage Vins Vin to AGND 0 1 AVDD V Analog Input CMRR fin 100 kHz 65 dB Input Current 800 kSPS Throughput 100 uA Input Impedance THROUGHPUT SPEED Complete Cycle In Warp Mode 1 25 us Throughput Rate In Warp Mode 1 800 kSPS Time between Conversions In Warp Mode 1 ms Complete Cycle In Normal Mode 1 5 us Throughput Rate In Normal Mode 0 666 kSPS Complete Cycle In Impulse Mode 1 75 us Throughput Rate In Impulse Mode 0 570 kSPS DC ACCURACY Integral Linearity Error 2 5 2 5 LSB Differential Linearity Error 1 1 75 LSB No Missing Codes 18 Bits Transition Noise Vre 5 V 0 7 LSB Zero Error Tmn to Tmax In Warp Mode 25 25 LSB Zero Error Temperature Drift All Modes 0 5 ppm C Gain Error Tmn to Tmax In Warp Mode 0 034 0 034 of FSR Gain Error Temperature Drift All Modes 1 6 ppm C Zero Error Tmn to Tmax Normal or Impulse Mode 85 See Note3 85 LSB Gain Error Tmn to Tmax Normal or Impulse Mode 0 048 See Note3 40 048 96 of FSR Power Supply Sensitivity AVDD 5 V 5 4 LSB AC ACCURACY Signal to Noise fin 2 kHz Vreer 5 V 101 dB Vner 4 096 V 97 5 99 dB fin 10 kHz Veer 4 096 V 98 dB fin 100 kHz Veer 4 096 V 97 dB Dynamic Range Vins Vn Vger 2 2 5 V 103 dB Spurious Free Dynamic Range fin
4. 2 kHz 120 dB fin 10 kHz 118 dB fin 100 kHz 105 dB Total Harmonic Distortion fin 2 kHz 115 dB fin 10 kHz 113 dB fin 100 kHz 98 dB Signal to Noise Distortion fin 2 kHz Veer 4 096 V 98 dB fin 2 kHz 60 dB Input 40 dB 3 dB Input Bandwidth 26 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full Scale Step 250 ns Overvoltage Recovery 250 ns Rev 0 Page 3 of 28 AD7674 Parameter Conditions Min Typ Max Unit REFERENCE External Reference Voltage Range REF 3 4 096 AVDD 0 1 V REF Voltage with Reference Buffer REFBUFIN 2 5 V 4 05 4 096 4 15 V Reference Buffer Input Voltage Range REFBUFIN 1 8 2 5 2 6 V REFBUFIN Input Current 1 1 uA REF Current Drain 800 kSPS Throughput 330 uA DIGITAL INPUTS Logic Levels Vit 0 3 0 8 V Vin 2 0 DVDD 0 3 V li 1 1 yA lin 1 1 yA DIGITAL OUTPUTS Data Format Pipeline Delay VoL Isink 1 6 mA 0 4 V Vou Isource 500 uA OVDD 0 6 V POWER SUPPLIES Specified Performance AVDD 4 75 5 5 25 V DVDD 4 75 5 5 25 V OVDD 2 7 DVDD 0 3 V Operating Current 800 kSPS Throughput AVDD 16 mA DVDD 6 5 mA OVDD 50 uA POWER DISSIPATION PDBUF High 500 kSPS 78 90 mW PDBUF High 1 kSPS 160 uW PDBUF High 800 kSPS 114 126 mW PDBUF Low 800 kSPS 126 138 mW TEMPERATURE RANGE Specified Performance Tmn to Tmax 40 85 C 1 See Analog Inputs section LSB means Least Signi
5. Crossover of digital and analog signals should be avoided Traces on different but close layers of the board should run at right angles to each other This will reduce the effect of feedthrough through the board The power supply lines to the AD7674 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines Good decoupling is also important to lower the supply s impedance presented to the AD7674 and to reduce the magnitude of the supply spikes Decoupling ceramic capacitors typically 100 nF should be placed close to and ideally right up against each power supply pin AVDD DVDD and OVDD and their corresponding ground pins Additionally low ESR 10 pF capacitors should be located near the ADC to further reduce low frequency ripple The DVDD supply of the AD7674 can be a separate supply or can come from the analog supply AVDD or the digital interface supply OVDD When the system digital supply is noisy or when fast switching digital signals are present and if no separate supply is available the user should connect the DVDD digital supply to the analog supply AVDD through an RC filter see Figure 27 and connect the system supply to the interface digital supply OVDD and the remaining digital circuitry When DVDD is powered from the system supply it is useful to insert a bead to further reduce high frequency spikes The AD7674 has four different ground pins REF
6. 3 V to REFGND to AGND AVDD 0 3 V TO output c 14V Ground Voltage Differences 6opF T AGND DGND OGND 0 3 V E Supply Voltages 5004A 5j lon AVDD DVDD OVDD 0 3 V to 7 V SIN SERIAL INTERFACE MODES THE SYNC SCLK AND AVDD to DVDD AVDDtoOVDD 7V A E bere DVDD to OVDD 0 3 V to 7 V 03083 0 002 Digital Inputs 0 3 V to DVDD 0 3 V MN a Figure 2 Load Circuit for Digital Interface Timing SDOUT SYNC SCLK Internal Power Dissipation 700 mW Outputs C 10 pF Internal Power Dissipation 2 5 W Junction Temperature 150 C Storage Temperature Range 65 C to 150 C Lead Temperature Range Soldering 10 sec 300 C 03083 0 003 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability See Analog Input section Specification is for device in free air 48 Lead LQFP Os 91 C W Osc 30 C W Specification is for device in free air 48 Lead LFCSP Oja 26 C W Figure 3 Voltage Reference Levels for Timing Rev 0 Page 7 of 28 AD7674 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS we 5 a a a 48 5 REFBUFI PIN 1 AvDD 2 IDENTIFIER WARP 6 AD7674 T
7. Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective companies www analo g com 37 Lal DEVICES Rev 0 Page 28 of 28
8. completing this process the control logic generates the ADC output code and brings the BUSY output low Modes of Operation The AD7674 features three modes of operation Warp Normal and Impulse Each mode is more suited for specific applications Warp mode allows conversion rates up to 800 kSPS However in this mode and this mode only the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms If the time between two consecutive conversions is longer than 1 ms e g after power up the first conversion result should be ignored This mode makes the AD7674 ideal for applications where a fast sample rate is required Normal mode is the fastest mode 666 kSPS without any limitation on the time between conversions This mode makes the AD7674 ideal for asynchronous applications such as data acquisition systems where both high accuracy and fast sample rate are required Impulse mode the lowest power dissipation mode allows power saving between conversions The maximum throughput in this mode is 570 kSPS When operating at 1 kSPS for example it typically consumes only 136 uW This feature makes the AD7674 ideal for battery powered applications Rev 0 Page 16 of 28 Transfer Functions Except in 18 bit interface mode the AD7674 offers straight Table 8 Output Codes and Ideal Input Voltages AD7674 binary and twos complement output coding when using
9. digital core DVDD can be supplied through a simple RC filter from the analog supply as shown in Figure 27 The AD7674 is independent of power supply sequencing once OVDD does not exceed DVDD by more than 0 3 V and is therefore free from supply voltage induced latch up Additionally it is very insensitive to power supply variations over a wide frequency range as shown in Figure 32 70 65 o e PSRR dB a a a e 45 40 1 10 100 1000 10000 FREQUECY kHz 03083 0 032 Figure 32 PSRR vs Frequency POWER DISSIPATION VERSUS THROUGHPUT In Impulse mode the AD7674 automatically reduces its power consumption at the end of each conversion phase During the acquisition phase the operating currents are very low which allows for a significant power savings when the conversion rate is reduced as shown in Figure 33 This feature makes the AD7674 ideal for very low power battery applications It should be noted that the digital interface remains active even during the acquisition phase To reduce the operating digital supply currents even further the digital inputs need to be driven close to the power rails DVDD and DGND and OVDD should not exceed DVDD by more than 0 3 V 1000000 400000 WARP NORMAL Z 10000 z Q FE 1000 n lt o Q 100 a x ui IMPULSE 8 1
10. or 48 lead LFCSP packages with operation specified from 40 C to 85 C Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies FUNCTIONAL BLOCK DIAGRAM ipud REF REFGND DVDD DGND O O SiS CAP DAC PARALLEL INTERFACE CONTROL LOGIC AND CALIBRATION CIRCUITRY WARP IMPULSE CNVST 03083 0 001 Figure 1 Functional Block Diagram Table 1 PulSAR Selection 800 Type kSPS 100 250 500 570 1000 Pseudo AD7651 AD7650 AD7652 AD7653 Differential AD7660 AD7661 AD7664 AD7666 AD7667 True Bipolar AD7663 AD7665 AD7671 True AD7675 AD7676 AD7677 Differential 18 Bit AD7678 AD7679 AD7674 Multichannel AD7654 Simultaneous AD7655 PRODUCT HIGHLIGHTS 1 High Resolution Fast Throughput The AD7674 is an 800 kSPS charge redistribution 18 bit SAR ADC no latency 2 Excellent Accuracy The AD7674 has a maximum integral nonlinearity of 2 5 LSB with no missing 18 bit codes 3 Serialor Parallel Interface Versatile parallel 18 16 or 8 bit bus or 3 wire ser
11. scale The point used as negative full scale occurs LSB before the first code transition Positive full scale is defined as a level 1 LSB beyond the last code transition The deviation is measured from the middle of each code to the true straight line Differential Nonlinearity Error DNL In an ideal ADC code transitions are 1 LSB apart Differential nonlinearity is the maximum deviation from this ideal value It is often specified in terms of resolution for which no missing codes are guaranteed Gain Error The first transition from 000 00 to 000 01 should occur for an analog voltage LSB above the nominal negative full scale 74 095991 V for the 4 096 V range The last transition from 111 10 to 111 11 should occur for an analog voltage 1 LSB below the nominal full scale 4 095977 V for the 4 096 V range The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels Zero Error The zero error is the difference between the ideal midscale input voltage 0 V from the actual voltage producing the midscale output code Spurious Free Dynamic Range SFDR SFDR is the difference in decibels dB between the rms amplitude of the input signal and the peak spurious signal Effective Number of Bits ENOB ENOB is a measurement of the resolution with a sine wave input and is expressed in bit
12. signals the AD7674 behaves like a 1 pole RC filter consisting of the equivalent resistance R R and Cs The resistors R and R are typically 102 Q and are lumped components made up of a serial resistor and the on resistance of the switches Cs is typically 60 pF and mainly consists of the ADC sampling capacitor This 1 pole filter with a 3 dB cutoff frequency of 26 MHz typ reduces any undesirable aliasing effect and limits the noise coming from the inputs Because the input impedance of the AD7674 is very high the part can be driven directly by a low impedance source without gain error This allows the user to put an external 1 pole RC filter between the amplifier output and the ADC analog inputs as shown in Figure 27 to improve the noise filtering done by the AD7674 analog input circuit However the source impedance has to be kept low because it affects the ac performance especially the total harmonic distortion THD The maximum source impedance depends on the amount of THD that can be tolerated The THD degrades as a function of source impedance and the maximum input frequency as shown in Figure 30 95 100 D 105 T 2 a I 110 115 120 15 45 75 105 INPUT RESISTANCE Q PPM Figure 30 THD vs Analog Input Frequency and Source Resistance Driver Amplifier Choice Although the AD7674 is easy to drive the driver amplifier needs to meet the following requirements e The driver amplifier and t
13. used as a serial data clock input or output dependent upon the logic state of the EXT INT pin The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin 23 D12 or DO In all modes except MODE 3 this output is used as Bit 12 of the parallel port data output bus SYNC When MODE 3 serial mode this output part of the serial port is used as a digital output frame synchronization for use with the internal data clock EXT INT Logic LOW When a read sequence is initiated and INVSYNC is LOW SYNC is driven HIGH and remains HIGH while the SDOUT output is valid When a read sequence is initiated and INVSYNC is HIGH SYNC is driven LOW and remains LOW while SDOUT output is valid 24 D13 or DO In all modes except MODE 3 this output is used as Bit 13 of the parallel port data output bus RDERROR In MODE 3 serial mode and when EXT INT is HIGH this output part of the serial port is used as an incomplete read error flag In slave mode when a data read is started and not complete when the following conversion is complete the current data is lost and RDERROR is pulsed high 25 28 D 14 17 DO Bit 14 to Bit 17 of the Parallel Port Data Output Bus These pins are always outputs regardless of the interface mode 29 BUSY DO Busy Output Transitions HIGH when a conversion is started Remains HIGH until the conversion is complete and the data is latched into the on chip shift register The falling edge of BUSY coul
14. 0 PDBUF HIGH n 1 0 1 1 10 100 1k 10k 100k 1M SAMPLING RATE SPS Perera Figure 33 Power Dissipation vs Sample Rate CONVERSION CONTROL Figure 34 shows the detailed timing diagrams of the conversion process The AD7674 is controlled by the CNVST signal which initiates conversion Once initiated it cannot be restarted or aborted even by PD until the conversion is complete The CNVST signal operates independently of CS and RD signals t2 me t CNVST BUSY MODE ACQUIRE CONVERT 03083 0 034 Figure 34 Basic Conversion Timing Although CNVST is a digital signal it should be designed with special care with fast clean edges and levels with minimum overshoot and undershoot or ringing For applications where SNR is critical the CNVST signal should have very low jitter This may be achieved by using a dedicated oscillator for CNVST generation or to clock it with a high frequency low jitter clock as shown in Figure 27 In Impulse mode conversions can be initiated automatically If CNVST is held low when BUSY goes low the AD7674 controls the acquisition phase and automatically initiates a new conversion By keeping CNVST low the AD7674 keeps the conversion process running by itself Note that the analog input has to be settled when BUSY goes low Also at power up CNVST should be brought low once to initiate the conversion process In this mode the AD7674 could sometimes run slightly faster than the g
15. 1 1 us When a higher sampling rate is desired use of one of the parallel interface modes is recommended DVDD AD7674 ADSP 219x SER PAR ADDITIONAL PINS OMITTED FOR CLARITY z 03083 0 045 Figure 45 Interfacing the AD7674 to an SPI Interface Rev 0 Page 25 of 28 AD7674 APPLICATION HINTS LAYOUT The AD7674 has very good immunity to noise on the power supplies However care should still be taken with regard to grounding layout The printed circuit board that houses the AD7674 should be designed so that the analog and digital sections are separated and confined to certain areas of the board This calls for the use of ground planes which can be easily separated Digital and analog ground planes should be joined in only one place preferably underneath the AD7674 or at least as close to the AD7674 as possible If the AD7674 is in a system where multiple devices require analog to digital ground connections the connection should still be made at one point only a star ground point that should be established as close to the AD7674 as possible The user should avoid running digital lines under the device as these will couple noise onto the die The analog ground plane should be allowed to run under the AD7674 to avoid noise coupling Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and should never run near analog signal paths
16. 8021 meets these requirements and is usually appropriate for almost all applications The AD8021 needs a 10 pF external compensation capacitor which should have good linearity as an NPO ceramic or mica type The AD8022 could be used if a dual version is needed and gain of 1 is present The AD829 is an alternative in applications where high frequency above 100 kHz performance is not required In gain of 1 applications it requires an 82 pF compensation capacitor The AD8610 is another option when low bias current is needed in low frequency applications Single to Differential Driver For applications using unipolar analog signals a single ended to differential driver will allow for a differential input into the part The schematic is shown in Figure 31 When provided an input signal of 0 to Vrer this configuration will produce a differential Vrer with midscale at Vrer 2 If the application can tolerate more noise the AD8138 differential driver can be used AD7674 ANALOG INPUT UNIPOLAR OV TO 4 096V AD7674 IN REF REFBUFIN 2 5V 03083 0 031 Figure 31 Single Ended to Differential Driver Circuit Internal Reference Buffer Used Voltage Reference The AD7674 allows the use of an external voltage reference either with or without the internal reference buffer Using the internal reference buffer is recommended when sharing a common reference voltage between multiple ADCs is desired However the advanta
17. CONNECTED TO AGND E rbgemacenem ERE KESEN Toner 0 02 NOM ELECTRICAL PERFORMANCE EE SANES COPLANARITY REF SEATING 0 08 PLANE COMPLIANT TO JEDEC STANDARDS MO 220 VKKD 2 Figure 47 48 Lead Frame Chip Scale Package LFCSP CP 48 ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the WARNING human body and test equipment and can discharge without detection Although the AD7674 features proprietary y ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Sept Ate Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE ORDERING GUIDE Model Temperature Range Package Description Package Option AD7674AST 40 C to 85 C Quad Flatpack LOFP ST 48 AD7674ASTRL 40 C to 85 C Quad Flatpack LOFP ST 48 AD7674ACP 40 C to 85 C Lead Frame Chip Scale LFCSP CP 48 AD7674ACPRL 40 C to 85 C Lead Frame Chip Scale LFCSP CP 48 EVAL AD7674CB Evaluation Board EVAL CONTROL BRD2 Controller Board This board can be used as a standalone evaluation board or in conjunction with the EVAL CONTROL BRD2 for evaluation demonstration purposes This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators Rev 0 Page 27 of 28 AD7674 NOTES 2003 Analog Devices
18. GND AGND DGND and OGND REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents AGND is the ground to which most internal ADC analog signals are referenced This ground must be connected with the least resistance to the analog ground plane DGND must be tied to the analog or digital ground plane depending on the configuration OGND is connected to the digital system ground The layout of the decoupling of the reference voltage is important The decoupling capacitor should be close to the ADC and should be connected with short and large traces to minimize parasitic inductances EVALUATING THE AD7674 S PERFORMANCE A recommended layout for the AD7674 is outlined in the documentation of the EVAL AD7674CB evaluation board for the AD7674 The evaluation board package includes a fully assembled and tested evaluation board documentation and software for controlling the board from a PC via the EVAL CONTROL BRD2 Rev 0 Page 26 of 28 AD7674 OUTLINE DIMENSIONS amp lals ac Id gu EB SEATING 10 PLANE 1 45 6 TOP VIEW 1 40 2 0 20 PINS DOWN T 0 09 1 35 Ss VIEW A A 3 5 Ey ew 0 15 0 0 05 SEATING 0 40 MAX PLAI COPLANARITY VIEWA ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS 026BBC Figure 46 48 Lead Quad Flatpack LOFP ST 48 0 50 0 40 030 4 1 00 030 yc NESNOM PADDLE
19. LSE DI Conversion Mode Selection When this input is HIGH and the WARP pin is LOW IMPULSE selects a reduced power mode In this mode the power dissipation is approximately proportional to the sampling rate When WARP and IMPULSE pins are LOW the NORMAL mode is selected 8 D1 A0 DI O When MODE 0 18 bit interface mode this pin is Bit 1 of the parallel port data output bus In all other modes this input pin controls the form in which data is output as shown in Table 7 9 D2 A1 DI O When MODE 0 or 1 18 bit or 16 bit interface mode this pin is Bit 2 of the parallel port data output bus In all other modes this input pin controls the form in which data is output as shown in Table 7 10 D3 DO In all modes except MODE 3 this output is used as Bit 3 of the parallel port data output bus This pin is always an output regardless of the interface mode 11 12 D 4 5 or DI O In all modes except MODE 3 these pins are Bit 4 and Bit 5 of the parallel port data output bus DIVSCLK O When MODE 3 serial mode when EXT INT is LOW and RDC SDIN is LOW serial master read after 1 convert these inputs part of the serial port are used to slow down if desired the internal serial clock that clocks the data output In other serial modes these pins are not used Rev 0 Page 8 of 28 AD7674 Pin No Mnemonic Type Description 13 D6 or DI O In all modes except MODE 3 this output is used as Bit 6 of the parallel port
20. NAL LOW JITTER CNVST SEE CONVERSION CONTROL SECTION 03083 0 027 Figure 27 Typical Connection Diagram Internal Reference Buffer Serial Interface Rev 0 Page 17 of 28 AD7674 TYPICAL CONNECTION DIAGRAM Figure 27 shows a typical connection diagram for the AD7674 Different circuitry shown on this diagram is optional and is discussed later in this data sheet Analog Inputs Figure 28 shows a simplified analog input section of the AD7674 The diodes shown in Figure 28 provide ESD protection for the inputs Care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs This will cause these diodes to become forward biased and start conducting current These diodes can handle a forward biased current of 120 mA max This condition could eventually occur when the input buffers U1 or U2 supplies are different from AVDD In such a case an input buffer with a short circuit current limitation can be used to protect the part AVDD R 1020 AGND 03083 0 028 Figure 28 Simplified Analog Input This analog input structure is a true differential structure By using these differential inputs signals common to both inputs are rejected as shown in Figure 29 which represents typical CMRR over frequency CMRR dB a eo 1 10 100 1000 10000 FREQUECY kHz 03083 0 029 Figure 29 Analog Input CMRR vs Frequency During the acquisition phase for ac
21. OB 2C et Straight ics f e nalog Input i See Figure 26 and Table 8 for the ideal transfer characteristic Description Veer i eeu repel ides pment FSR 1 LSB 4 095962 V 3FFFF 1FFFF XY FSR 2LSB 4 095924 V 3FFFE 1FFFE dias Mo Midscale 1 LSB 31 25 uV 20001 00001 E 111 101 i Midscale OV 20000 00000 Midscale 1LSB 31 25 uV 1FFFF 3FFFF g i FSR 1 LSB 4 095962 V 00001 20001 o ur FSR 4 096 V 00000 20000 o 2 l o Q 000 010 0000 This is also the code for overrange analog input V Vin 000 000 l above Vrer Vreranp sl l Fs 1LsB USES CA USB This is also the code for underrange analog input Vw Vin l below Vner Vreranp FS 0 5 LSB tes 4 5 8B ANALOG INPUT 03083 0 026 Figure 26 ADC Ideal Transfer Function doped DVDD ANALOG ne o DISTAL supe tl4our 100nF 400nF TLF V ADR421 DGND DVDD OVDD 2 5V REF REFBUFIN scLk SERIAL PORT SDOUT Q X ves Se gt Creer icd EE Crer _ Busy po CT NOTE 1 O REFGND D uC uP DSP AD7674 Ra ERE eR E ed 1 NOTE 3 5 150 OIN ANALOG INPUT O AD8021 500 r 1 E 1150 NOTE 3 O I ANALOG INPUT O Co 27nF AD8021 1___ NOTE 4j NOTES 1 SEE VOLTAGE REFERENCE INPUT SECTION 2 OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION 3 THE AD8021 IS RECOMMENDED SEE DRIVER AMPLIFIER CHOICE SECTION 4 SEE ANALOG INPUTS SECTION 5 OPTION SEE POWER SUPPLY SECTION 6 OPTIO
22. OP VIEW Not to Scale p4ipiVscLK o 11 D5 DIVSCLK 1 12 Nc NocoNwecr dade Hel iz ire rol oo 21 22 23 faa E2 228825228 on ZETLEREEREERHT zz22g Oo M o t z eo Brak Saig DAS a 5 2 amp 03083 0 004 Figure 4 48 Lead LQFP and 48 Lead LFCSP ST 48 and CP 48 Table 6 Pin Function Descriptions Pin No Mnemonic Type Description 1 44 AGND P Analog Power Ground Pin 2 47 AVDD P Input Analog Power Pins Nominally 5 V 3 MODEO DI Data Output Interface Mode Selection 4 MODE1 DI Data Output Interface Mode Selection Interface MODE MODE1 MODEO Description 0 0 0 18 Bit Interface 1 0 1 16 Bit Interface 2 1 0 Byte Interface 3 1 1 Serial Interface 5 D0 OB 2C DI O When MODE 0 18 bit interface mode this pin is Bit O of the parallel port data output bus and the data coding is straight binary In all other modes this pin allows choice of straight binary binary twos complement When OB 2C is HIGH the digital output is straight binary when LOW the MSB is inverted resulting in a twos complement output from its internal shift register 6 WARP DI Conversion Mode Selection When this input is HIGH and the IMPULSE pin is LOW WARP selects the fastest mode the maximum throughput is achievable and a minimum conversion rate must be applied in order to guarantee full specified accuracy When LOW full accuracy is maintained independent of the minimum conversion rate 7 IMPU
23. SFDR 120 4dB SINAD 98 4dB FREQUENCY kHz Figure 12 FFT 10 kHz Tone 300 350 400 03083 0 012 fs 800kSPS fin 100kHz Ver 4 096V SNR 98 8dB THD 104 3dB SFDR 104 9dB SINAD 97 8dB FREQUENCY kHz Figure 13 FFT 100 kHz Tone 300 350 400 03083 0 013 250 200 AD7674 a eo EN o o NUMBER OF UNITS 0 2 0 1 5 1 0 NEGATIVE DNL LSB 5 0 03083 0 014 Figure 14 TypicalNegative DNL Distribution 424 Units 16 5 16 0 15 5 15 0 ENOB Bits 14 5 SNR AND S N D dB FREQUENCY kHz 14 0 03083 0 015 Figure 15 SNR S N D and ENOB vs Frequency 60 140 120 70 80 90 100 80 100 THD HARMONICS dB 110 THIRD HARMONIC 60 SFDR dB 40 120 SECOND HARMONIC 20 100 FREQUENCY kHz 0 1000 03083 0 016 Figure 16 THD SFDR and Harmonics vs Frequency Rev 0 Page 13 of 28 AD7674 104 Vref 4 096V e ce e 98 SNR REFERRED TO FULL SCALE dB gt e INPUT LEVEL dB 03083 0 017 Figure 17 SNR and S N D vs Input Level 100 16 5 Vner 4 096V 99 16 0 a EJ Zz 98 15 5 D 4 z o 97 15 0 96 14 5 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C 03083 0 018 Figure 18 SNR S N D and ENOB vs Temperature
24. SR EB RAR S TM CUu Aman 15 KASETE ANALOG DEVICES 18 Bit 2 5 LSB INL 800 kSPS SAR ADC AD7674 FEATURES 18 bit resolution with no missing codes No pipeline delay SAR architecture Differential input range Vrer Vrer up to 5 V Throughput 800 kSPS Warp mode 666 kSPS Normal mode 570 kSPS Impulse mode INL 2 5 LSB max 9 5 ppm of full scale Dynamic range 103 dB typ Vrer 5 V S N D 100 dB typ 2 kHz Vrer 5 V Parallel 18 16 or 8 bit bus and serial 5 V 3 V interface SPI QSPI MICROWIRE DSP compatible On board reference buffer Single 5 V supply operation Power dissipation 98 mW typ 800 kSPS 78 mW type 500 kSPS Impulse mode 160 pW 1 kSPS Impulse mode 48 lead LQFP or 48 lead LFCSP package Pin to pin compatible upgrade of AD7676 AD7678 AD7679 APPLICATIONS CT scanners High dynamic data acquisition Geophone and hydrophone sensors Z A replacement low power multichannel Instrumentation Spectrum analysis Medical instruments GENERAL DESCRIPTION The AD7674 is an 18 bit 800 kSPS charge redistribution SAR fully differential analog to digital converter that operates on a single 5 V power supply The part contains a high speed 18 bit sampling ADC an internal conversion clock an internal reference buffer error correction circuits and both serial and parallel system interface ports The part is available in 48 lead LQFP
25. d be used as a data ready clock signal 30 DGND P Must Be Tied to Digital Ground 31 RD DI Read Data When CS and RD are both LOW the interface parallel or serial output bus is enabled 32 CS DI Chip Select When CS and RD are both LOW the interface parallel or serial output bus is enabled CS is also used to gate the external clock 33 RESET DI Reset Input When set to a logic HIGH reset the AD7674 Current conversion if any is aborted If not used this pin could be tied to DGND Rev 0 Page 9 of 28 AD7674 Pin No Mnemonic Type Description 34 PD DI Power Down Input When set to a logic HIGH power consumption is reduced and conversions are inhibited after the current one is completed 35 CNVST DI Start Conversion A falling edge on CNVST puts the internal sample hold into the hold state and initiates a conversion In Impulse mode IMPULSE HIGH WARP LOW if CNVST is held LOW when the acquisition phase ts is complete the internal sample hold is put into hold and a conversion is immediately started 36 AGND P Must Be Tied to Analog Ground 37 REF Al Reference Input Voltage and Internal Reference Buffer Output Apply an external reference on REF if the internal reference buffer is not used Should be decoupled effectively with or without the internal buffer 38 REFGND Al Reference Input Analog Ground 39 IN Al Differential Negative Analog Input 40 42 NC No Connect 45 43 IN Al Differential P
26. data output bus EXT INT When MODE 3 serial mode this input part of the serial port is used as a digital select input for choosing the internal data clock or an external data clock With EXT INT tied LOW the internal clock is selected on the SCLK output With EXT INT set to a logic HIGH output data is synchronized to an external clock signal connected to the SCLK input 14 D7 or DI O In all modes except MODE 3 this output is used as Bit 7 of the parallel port data output bus INVSYNC When MODE 3 serial mode this input part of the serial port is used to select the active state of the SYNC signal When LOW SYNC is active HIGH When HIGH SYNC is active LOW 15 D8 or DI O In all modes except MODE 3 this output is used as Bit 8 of the parallel port data output bus INVSCLK When MODE 3 serial mode this input part of the serial port is used to invert the SCLK signal It is active in both master and slave mode 16 D9 or DI O In all modes except MODE 3 this output is used as Bit 9 of the parallel port data output bus RDC SDIN When MODE 3 serial mode this input part of the serial port is used as either an external data input or a read mode selection input depending on the state of EXT INT When EXT INT is HIGH RDC SDIN could be used as a data input to daisy chain the conversion results from two or more ADCs onto a single SDOUT line The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after t
27. e Serial Data Timing for Reading Read after Convert EXT INT 1 INVSCLK 0 RD 0 CNVST BUSY SCLK SDOUT 03083 0 043 Figure 43 Slave Serial Data Timing for Reading Read Previous Conversion during Convert Rev 0 Page 24 of 28 BUSY BUSY AD7674 AD7674 2 UPSTREAM 1 DOWNSTREAM RDC SDIN RDC SDIN OUT CNVST INO 03083 0 044 Figure 44 Two AD7674s in a Daisy Chain Configuration External Clock Data Read during Conversion Figure 43 shows the detailed timing diagrams of this method During a conversion while both CS and RD are low the result of the previous conversion can be read The data is shifted out MSB first with 18 clock pulses and is valid on both the rising and falling edge of the clock The 18 bits have to be read before the current conversion is complete If that is not done RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading There is no daisy chain feature in this mode and the RDC SDIN input should always be tied either high or low To reduce performance degradation due to digital activity a fast discontinuous clock is recommended to ensure that all bits are read during the first half of the conversion phase It is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated AD7674 MICROPROCESSOR INTERFACING The AD7674 is ideally sui
28. e modes Figure 42 shows the detailed timing diagrams of this method After a conversion is complete indicated by BUSY returning low the result of this conversion can be read while both CS and RD are low Data is shifted out MSB first with 18 clock pulses and is valid on the rising and falling edge of the clock Among the advantages of this method the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process Also data can be read at speeds up to 40 MHz accommodating both slow digital host interface and the fastest serial reading Finally in this mode only the AD7674 provides a daisy chain feature using the RDC SDIN input pin to cascade multiple converters together This feature is useful for reducing component count and wiring connections when desired for instance in isolated multiconverter applications An example of the concatenation of two devices is shown in Figure 44 Simultaneous sampling is possible by using a common CNVST signal It should be noted that the RDC SDIN input is latched on the edge of SCLK opposite the one used to shift out data on SDOUT Thus the MSB of the upstream converter follows the LSB of the downstream converter on the next SCLK cycle Rev 0 Page 23 of 28 AD7674 EXT INT 1 INVSCLK 0 RD 0 cs eooo yoo SCLK SDOUT X16 03083 0 042 tis 16 t34 lt lt SDIN t33 Figure 42 Slav
29. ead after Convert Warp Mode Normal Mode Impulse Mode ta 1 1 25 1 5 us Aperture Delay ts 2 ns End of Conversion to BUSY LOW Delay te 10 ns Conversion Time Warp Mode Normal Mode Impulse Mode t 1 1 25 1 5 us Acquisition Time ts 250 ns RESET Pulsewidth to 10 ns Refer to Figure 36 Figure 37 and Figure 38 Parallel Interface Modes CNVST LOW to Data Valid Delay Warp Mode Normal Mode Impulse Mode to 1 1 25 1 5 us Data Valid to BUSY LOW Delay th 20 ns Bus Access Request to Data Valid ta 45 ns Bus Relinquish Time tis 5 15 ns Refer to Figure 40 and Figure 41 Master Serial Interface Modes CS LOW to SYNC Valid Delay tra 10 ns CS LOW to Internal SCLK Valid Delay tis 10 ns CS LOW to SDOUT Delay tie 10 ns CNVST LOW to SYNC Delay Warp Mode Normal Mode Impulse Mode t 25 275 525 ns SYNC Asserted to SCLK First Edge Delay tis 3 ns Internal SCLK Period tio 25 40 ns Internal SCLK HIGH t20 12 ns Internal SCLK LOW tai 7 ns SDOUT Valid Setup Time t22 4 ns SDOUT Valid Hold Time tas 2 ns SCLK Last Edge to SYNC Delay toa 3 CS HIGH to SYNC HI Z tos 10 ns CS HIGH to Internal SCLK HI Z tos 10 ns CS HIGH to SDOUT HI Z ty 10 ns BUSY HIGH in Master Serial Read after Convert tos Table 4 CNVST LOW to SYNC Asserted Delay Warp Mode Normal Mode Impulse Mode t29 1 1 25 1 5 us SYNC Deasserted to BUSY LOW Delay t30 25 ns Refer to Figure 42 and Figure 43 Slave Serial Interface Modes External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT De
30. en the serial data is valid The serial clock SCLK and the SYNC signal can be inverted if desired Depending on the RDC SDIN input the data can be read after each conversion or during the following conversion Figure 40 and Figure 41 show the detailed timing diagrams of these two modes Usually because the AD7674 is used with a fast throughput the Master Read during Conversion mode is the most recommended serial mode e RDC SDIN 0 INVSCLK INVSYNC 0 CS RD EXT INT 2 0 x A N wq_2q _ qe _ _ _ _ 3 Y gt Y gt WwN gt V amp eR wq gt ts CNVST In Read during Conversion mode the serial clock and data toggle at appropriate instants minimizing potential feedthrough between digital activity and critical conversion decisions In Read after Conversion mode it should be noted that unlike in other modes the BUSY signal returns low after the 18 data bits are pulsed out and not at the end of the conversion phase which results in a longer BUSY width To accommodate slow digital hosts the serial clock can be slowed down by using DIVSCLK 03083 0 040 Figure 40 Master Serial Data Timing for Reading Read after Convert Rev 0 Page 22 of 28 l e zl o CNVST BUSY SYNC SCLK EXT INT 2 0 RDC SDIN 1 AD7674 INVSCLK INVSYNC 0 SDOUT t tig gt t22 lt 03083 0 046 Figure 41 Master Serial Data Timing
31. ficant Bit With the 4 096 V input range 1 LSB is 31 25 uV See Definitions of Specifications section These parameters are centered on nominal values which depend on the mode In Warp mode nominal zero error and nominal gain error are centered around 0 LSB In Normal and Impulse modes nominal zero error is 375 LSB and nominal gain error is 0 273 of FSR These specifications are the deviation from these nominal values These specifications do not include the error contribution from the external reference but do include the error contribution from the reference buffer if used All specifications in dB are referred to a full scale input FS Tested with an input signal at 0 5 dB below full scale unless otherwise specified gt Data Format Parallel or Serial 18 Bit Conversion results are available immediately after completed conversion 7 The max should be the minimum of 5 25 V and DVDD 0 3 V 8 In Warp mode Tested in Parallel Reading mode 10 In Impulse mode Contact factory for extended temperature range Rev 0 Page 4 of 28 AD7674 TIMING SPECIFICATIONS Table 3 40 C to 85 C AVDD DVDD 5 V OVDD 2 7 V to 5 25 V unless otherwise noted Parameter Symbol Min Typ Max Unit Refer to Figure 34 and Figure 35 Convert Pulsewidth t 10 ns Time between Conversions Warp Mode Normal Mode Impulse Mode t 1 25 1 5 1 75 us CNVST LOW to BUSY HIGH Delay t 35 ns BUSY HIGH AII Modes Except Master Serial R
32. for Reading Read Previous Conversion during Convert SLAVE SERIAL INTERFACE External Clock The AD7674 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT INT pin is held high In this mode several methods can be used to read the data The external serial clock is gated by CS When CS and RD are both low the data can be read after each conversion or during the following conversion The external clock can be either a continuous or a discontinuous clock A discontinuous clock can be either normally high or normally low when inactive Figure 42 and Figure 43 show the detailed timing diagrams of these methods While the AD7674 is performing a bit decision it is important that voltage transients not occur on digital input output pins or degradation of the conversion result could occur This is particularly important during the second half of the conversion phase because the AD7674 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase For this reason it is recommended that when an external clock is being provided it is a discontinuous clock that only toggles when BUSY is low or more importantly that it does not transition during the latter half of BUSY high External Discontinuous Clock Data Read after Conversion Though maximum throughput cannot be achieved using this mode it is the most recommended of the serial slav
33. ges of using the external reference voltage directly are e The SNR and dynamic range improvement about 1 7 dB resulting from the use of a reference voltage very close to the supply 5 V instead of a typical 4 096 V reference when the internal buffer is used e The power saving when the internal reference buffer is powered down PDBUF High To use the internal reference buffer PDBUF should be LOW A 2 5 V reference voltage applied on the REFBUFIN input will result in a 4 096 V reference on the REF pin In both cases the voltage reference input REF has a dynamic input impedance and therefore requires an efficient decoupling between REF and REFGND inputs The decoupling consists of a low ESR 47 uF tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance Care should also be taken with the reference temperature coefficient of the voltage reference which directly affects the full scale accuracy if this parameter matters For instance a 4 ppm C temperature coefficient of the reference changes the full scale by 1 LSB C Rev 0 Page 19 of 28 AD7674 Power Supply The AD7674 uses three sets of power supply pins an analog 5 V supply AVDD a digital 5 V core supply DVDD and a digital output interface supply OVDD The OVDD supply defines the output logic level and allows direct interface with any logic working between 2 7 V and DVDD 0 3 V To reduce the number of supplies needed the
34. he initiation of the read sequence When EXT INT is LOW RDC SDIN is used to select the read mode When RDC SDIN is HIGH the data is output on SDOUT during conversion When RDC SDIN is LOW the data can be output on SDOUT only when the conversion is complete 17 OGND P Input Output Interface Digital Power Ground 18 OVDD P Output Interface Digital Power Nominally at the same supply as the host interface 5 V or 3 V Should not exceed DVDD by more than 0 3 V 19 DVDD P Digital Power Nominally at 5 V 20 DGND P Digital Power Ground 21 D10 or DO In all modes except MODE 3 this output is used as Bit 10 of the parallel port data output bus SDOUT When MODE 3 serial mode this output part of the serial port is used as a serial data output synchronized to SCLK Conversion results are stored in an on chip register The AD7674 provides the conversion result MSB first from its internal shift register The data format is determined by the logic level of OB 2C In serial mode when EXT INT is LOW SDOUT is valid on both edges of SCLK In serial mode when EXT INT is HIGH and INVSCLK is LOW SDOUT is updated on the SCLK rising edge and is valid on the next falling edge if INVSCLK is HIGH SDOUT is updated on the SCLK falling edge and is valid on the next rising edge 22 D11 or DI O In all modes except MODE 3 this output is used as Bit 11 of the parallel port data output bus SCLK When MODE 3 serial mode this pin part of the serial port is
35. he AD7674 analog input circuit have to be able to settle for a full scale step of the capacitor array at an 18 bit level 0 000496 In the amplifier s data sheet settling at 0 196 or 0 0196 is more commonly specified This could differ significantly from the settling time at an 18 bit level and therefore should be verified prior to driver selection The tiny op amp AD8021 which combines ultralow noise and high gain bandwidth meets this settling time requirement e The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7674 The noise coming from the driver is filtered by the AD7674 analog input circuit 1 pole low pass filter made by R R and Cs Rev 0 Page 18 of 28 The SNR degradation due to the amplifier is 25 625 7 f up Ne y SNRLoss 20 log where f sapis the 3 dB input bandwidth in MHz of the AD7674 26 MHz or the cutoff frequency of the input filter if used Nis the noise factor of the amplifiers 1 if in buffer configuration en is the equivalent input noise voltage of each op amp in nV VHz For instance for a driver with an equivalent input noise of 2nV VHz e g AD8021 configured as a buffer thus with a noise gain of 1 the SNR degrades by only 0 34 dB with the filter in Figure 27 and by 1 8 dB without it e The driver needs to have a THD performance suitable to that of the AD7674 The AD
36. ial interface arrangement compatible with both 3 V and 5 V logic One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD7674 TABLE OF CONTENTS SPec ONS e ss etc hate La to aet E S 3 Timing Specifications sse 5 Absolute Maximum Ratings eeeeeeeeeeetntetentnnn 7 Pin Configuration and Function Descriptions s 8 Definitions of Specifications 11 Typical Performance Characteristics ses 12 Circuit InformatlOIz 2 eet e E RS 16 Converter Operation cccccccsesseseesesseseseeneseeeseeneseesseeneseeneseens 16 Typical Connection Diagram esee 18 Power Dissipation versus Throughput sss 20 Conversion Control eet iet tette tet er 20 REVISION HISTORY Revision 0 Initial Version DigitalIntetfacez o eto RN e ate 21 Parallel Intetface eet RSS 21 Serial Interface esee te ee etos 21 Master Serial Interface 22 Slave Serial Interface nian eat ea e Re totes 23 Microprocessor Interfacing seen 25 Application FANS eee eR iet M IR eue 26 Layout ieueeeie tes nien ene e OH Iis 26 Evaluating the AD7674 s Performance sse 26 Outline Dimensions eet eee eee ends 27 Ordering Guide eme ien tetto 27 Rev 0 Page 2 of 28 SPECIFICATIONS Table 2 40 C to 85 C Vre 4 096 V AVDD DVDD
37. l Scale vs Supply Rev 0 Page 15 of 28 t42 DELAY ns OVDD 2 7V 85 C AD7674 OVDD 5V OVDD 5V 25 C OVDD 2 7V 25 C 85 C 50 100 pF 150 200 03083 0 024 Figure 24 Typical Delay vs Load Capacitance C AD7674 CIRCUIT INFORMATION IN REF REFGND SWITCHES CONTROL CONTROL LOGIC CNVST 03083 0 025 Figure 25 ADC Simplified Schematic The AD7674 is a very fast low power single supply precise 18 bit analog to digital converter ADC using successive approximation architecture The AD76745 linearity and dynamic range are similar to or better than many X A ADCs With the advantages of its successive architecture which ease multiplexing and reduce power with throughput it can be advantageous in applications that normally use Z A ADCs The AD7674 features different modes to optimize performance according to the applications In Warp mode the AD7674 is capable of converting 800 000 samples per second 800 kSPS The AD7674 provides the user with an on chip track hold successive approximation ADC that does not exhibit any pipeline or latency making it ideal for multiple multiplexed channel applications The AD7674 can be operated from a single 5 V supply and can be interfaced to either 5 V or 3 V digital logic It is housed in a 48 lead LQFP or a tiny 48 lead LFCSP package that offers space savings and allows for flexible configurations as ei
38. lay t32 3 18 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period tss 25 ns External SCLK HIGH tse 10 ns External SCLK LOW t37 10 ns In Warp mode only the maximum time between conversions is 1 ms otherwise there is no required maximum time In serial interface modes the SYNC SCLK and SDOUT timings are defined with a maximum load C of 10 pF otherwise the load is 60 pF maximum 3In Serial Master Read during Convert mode See Table 4 for Serial Master Read after Convert mode Rev 0 Page 5 of 28 AD7674 Table 4 Serial Clock Timings in Master Read after Convert DIVSCLK 1 0 0 1 1 DIVSCLK O Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum tis 3 17 17 17 ns Internal SCLK Period Minimum to 25 60 120 240 ns Internal SCLK Period Maximum to 40 80 160 320 ns Internal SCLK HIGH Minimum too 12 22 50 100 ns Internal SCLK LOW Minimum ta 7 21 49 99 ns SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns SDOUT Valid Hold Time Minimum t23 2 4 30 89 ns SCLK Last Edge to SYNC Delay Minimum t24 3 60 140 300 ns Busy High Width Maximum Warp tos 1 75 2 5 4 7 us Busy High Width Maximum Normal tos 2 2 75 4 25 7 25 us Busy High Width Maximum Impulse tos 2 25 3 4 5 7 5 us Rev 0 Page 6 of 28 AD7674 ABSOLUTE MAXIMUM RATINGS Table 5 AD7674 Absolute Maximum Ratings Parameter Rating Analog Inputs IN IN REF REFBUFIN AGND 0
39. ositive Analog Input 46 REFBUFIN Al Reference Buffer Input Voltage The internal reference buffer has a fixed gain It outputs 4 096 V typically when 2 5 V is applied on this pin 48 PDBUF DI Allows Choice of Buffering Reference When LOW buffer is selected When HIGH buffer is switched off TAI Analog Input DI Digital Input DI O Bidirectional Digital DO Digital Output P Power g g g Table 7 Data Bus Interface Definitions MODE MODE1 MODEO DO OB 2C D1 A0 D2 A1 D 3 D 4 9 D 10 11 D 12 15 D 16 17 Description 0 0 0 R O R 1 R 2 R 3 R 4 9 R 10 11 R 12 15 R 16 17 18 Bit Parallel 1 0 1 OB 2C A0 0 R 2 R 3 R 4 9 R 10 11 R 12 15 R 16 17 16 Bit High Word 1 0 1 OB 2C A0 1 R O R 1 All Zeros 16 Bit Low Word 2 1 0 OB 2C A0 0 A1 0 All Hi Z R 10 11 R 12 15 R 16 17 8 Bit HIGH Byte 2 1 0 OB 2C A0 0 A1 1 All Hi Z R 2 3 R 4 7 R 8 9 8 Bit MID Byte 2 1 0 OB 2C A0 1 A1 0 All Hi Z R 0 1 All Zeros 8 Bit LOW Byte 2 1 0 OB 2C A0 1 A1 1 All Hi Z All Zeros R 0 1 8 Bit LOW Byte 3 1 1 OB 2C All Hi Z Serial Interface Serial Interface R 0 17 is the 18 bit ADC value stored in its output register Rev 0 Page 10 of 28 AD7674 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity Error INL Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full
40. s It is related to S N D by the following formula ENOB S N D dB 1 76 6 02 Total Harmonic Distortion THD THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full scale input signal and is expressed in decibels Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together The value for dynamic range is expressed in decibels Signal to Noise Ratio SNR SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency excluding harmonics and dc The value for SNR is expressed in decibels Signal to Noise Distortion Ratio S N D S N D is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for S N D is expressed in decibels Aperture Delay Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion Transient Response Transient response is the time required for the AD7674 to achieve its rated accuracy after a full scale step function is applied to its input Rev 0 Page 11 of 28 AD7674 TYPICAL PERFORMANCE CHARACTERISTICS
41. s shown in Figure 37 and Figure 38 respectively When the data is read during the conversion however it is recommended AD7674 that it is read only during the first half of the conversion phase This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry Refer to Table 7 for a detailed description of the different options available DATA CURRENT BUS CONVERSION ty gt ts 03083 0 037 Figure 37 Slave Parallel Data Timing for Reading Read after Convert 20 r t gt CNVST RD BUSY ty t3 gt DATA PREVIOUS BUS CONVERSION ti2 03083 0 038 Figure 38 Slave Parallel Data Timing for Reading Read during Convert eee PINS D 7 0 LOW BYTE PINS D 15 8 03083 0 039 Figure 39 8 Bit and 16 Bit Parallel Interface SERIAL INTERFACE The AD7674 is configured to use the serial interface when MODEO and MODE are held high The AD7674 outputs 18 bits of data MSB first on the SDOUT pin This data is synchronized with the 18 clock pulses provided on the SCLK pin The output data is valid on both the rising and falling edge of the data clock Rev 0 Page 21 of 28 AD7674 MASTER SERIAL INTERFACE Internal Clock The AD7674 is configured to generate and provide the serial data clock SCLK when the EXT INT pin is held low The AD7674 also generates a SYNC signal to indicate to the host wh
42. ted for traditional dc measurement applications supporting a microprocessor and for ac signal processing applications interfacing to a digital signal processor The AD7674 is designed to interface either with a parallel 8 bit or 16 bit wide interface or with a general purpose serial port or I O ports on a microcontroller A variety of external buffers can be used with the AD7674 to prevent digital noise from coupling into the ADC The following section illustrates the use of the AD7674 with an SPI equipped DSB the ADSP 219x SPI Interface ADSP 219x Figure 45 shows an interface diagram between the AD7674 and the SPI equipped ADSP 219x To accommodate the slower speed of the DSP the AD7674 acts as a slave device and data must be read after conversion This mode also allows the daisy chain feature The convert command could be initiated in response to an internal timer interrupt The 18 bit output data are read with 3 byte SPI access The reading process could be initiated in response to the end of conversion signal BUSY going low using an interrupt line of the DSP The serial interface SPI on the ADSP 219x is configured for master mode MSTR 1 Clock Polarity Bit CPOL 0 Clock Phase Bit CPHA 1 and SPI interrupt enable TIMOD 00 by writing to the SPI Control register SPICLTx It should be noted that to meet all timing requirements the SPI clock should be limited to 17 Mbps which allows it to read an ADC result in about
43. ther a serial or parallel interface The AD7674 is a pin to pin compatible upgrade of the AD7676 AD7678 and AD7679 CONVERTER OPERATION The AD7674 is a successive approximation ADC based on a charge redistribution DAC Figure 25 shows the simplified schematic of the ADC The capacitive DAC consists of two identical arrays of 18 binary weighted capacitors that are connected to the two comparator inputs During the acquisition phase terminals of the array tied to the comparator s input are connected to AGND via SW and SW All independent switches are connected to the analog inputs Thus the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN and IN inputs When the acquisition phase is complete and the CNVST input goes low a conversion phase is initiated When the conversion phase begins SW and SW are opened first The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input Therefore the differential voltage between the IN and IN inputs captured at the end of the acquisition phase is applied to the comparator inputs causing the comparator to become unbalanced By switching each element of the capacitor array between REFGND and REE the comparator input varies by binary weighted voltage steps Vxzx 2 Vrer 4 Vrer 262144 The control logic toggles these switches starting with the MSB first to bring the comparator back into a balanced condition After
44. uaranteed limits of 570 kSPS in Impulse mode This feature does not exist in Warp or Normal modes Rev 0 Page 20 of 28 DIGITAL INTERFACE The AD7674 has a versatile digital interface it can be interfaced with the host system by using either a serial or parallel interface The serial interface is multiplexed on the parallel data bus The AD7674 digital interface also accommodates both 3 V and 5 V logic by simply connecting the AD7674 s OVDD supply pin to the host system interface digital supply Finally by using the OB 2C input pin in any mode but 18 bit interface mode both twos complement and straight binary coding can be used The two signals CS and RD control the interface When at least one of these signals is high the interface outputs are in high impedance Usually CS allows the selection of each AD7674 in multicircuit applications and is held low in a single AD7674 design RD is generally used to enable the conversion result on the data bus RESET CNVST 03083 0 035 Figure 35 RESET Timing CS RD 0 t CNVST tio BUSY A PREVIOUS CONVERSION DATA 03083 0 036 Figure 36 Master Parallel Data Timing for Reading Continuous Read PARALLEL INTERFACE The AD7674 is configured to use the parallel interface with an 18 bit a 16 bit or an 8 bit bus width according to Table 7 The data can be read either after each conversion which is during the next acquisition phase or during the following conversion a

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