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ANALOG DEVICES ADV7129 handbook

1. WARS RAAN ERU WENN ANALOG DEVICES 915 CU 192 Bit 360 MHz True Color Video DAC with Onboard PLL ADV7129 FEATURES 192 Bit Pixel Port Allows 2048 x 2048 x 24 Screen Resolution 360 MHz 24 Bit True Color Operation Triple 8 Bit D A Converters 8 1 Multiplexing Onboard PLL RS 343A RS 170 Compatible Analog Outputs TTL Compatible Digital Inputs Internal Voltage Reference Standard 8 Bit MPU I O Interface DAC DAC Matching Typ 2 Adjustable to 0 02 5 V CMOS Monolithic Construction 304 Pin POFP Package APPLICATIONS Ultrahigh Resolution Color Graphics Image Processing Drives 24 Bit Color 2K x 2K Monitors GENERAL DESCRIPTION The ADV7129 is a complete analog output video DAC on a single CMOS ADV monolithic chip The part is specifically designed for use in the highest resolution graphics and imaging systems The ultimate level of integration comprised of 360 MHz triple 8 bit DACs a programmable pixel port an internal voltage refer ence and an onboard PLL makes the ADV7129 the only choice for the very highest level of performance and functionality The device consists of three high speed 8 bit video D A con verters RGB An onboard phase locked loop clock generator is provided to provide high speed operation without requiring high speed external crystal or clock circuitry The part is fully controlled through the MPU port by the on board command regi
2. Table II Video Output Truth Table Rser 560 Ri 25 OIP with Sync with Sync DAC Description Enabled mA Disabled mA SYNC BLANK Input Data WHITE LEVEL 40 28 57 1 1 VIDEO Video 13 6 Video 2 14 1 1 Data VIDEO to BLANK Video 2 16 Video 2 14 0 1 Data BLACK LEVEL 13 6 2 14 1 1 00H BLACK to BLANK 2 14 2 14 0 1 00H BLANK LEVEL 11 44 0 1 0 SYNC LEVEL 0 0 0 0 xxH Table III Video Output Truth Table 280 oap 25 OIP with Sync DAC Description Disabled mA SYNC BLANK Input Data WHITE LEVEL 52 8 0 0 FFH VIDEO Video 0 0 0 Data VIDEO to BLACK Video 0 0 0 Data BLACK LEVEL 0 0 0 xxH 14 REV 0 ADV7129 APPENDIX I BOARD DESIGN AND LAYOUT CONSIDERATIONS ADV7129 is a highly integrated circuit containing both precision analog and high speed digital circuitry It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry It is impera tive that these same design and layout techniques be applied to the system level design such that high speed accurate perfor mance is achieved The Recommended Analog Circuit Layout see Figure 12 shows the analog interface between the device and monitor The layout should be optimized for lowest noise on the ADV7129 power and ground lines by shielding the digital inputs and pro viding good decoupling T
3. R1 166100 GROO RO 270370 Figure 9 Gain Error Register 12 REV 0 ADV7129 DIGITAL TO ANALOG CONVERTERS DACS AND VIDEO OUTPUTS ADV7129 contains three high speed video DACs The DAC outputs are represented as the three primary analog color signals IOR red video IOG green video and IOB blue video DACs and Analog Outputs The part contains three matched 8 bit digital to analog converters The DACs are designed using an advanced high speed seg mented architecture The bit currents corresponding to each digital input are routed to either bit 717 or IOR bit 0 Normally IOR amp IOB are connected to GND IOR IOG IOB 20 500 CABLE 2 500 25 500 MONITOR SOURCE TERMINATION Figure 10 DAC Output Termination Doubly Terminated 500 Load analog video outputs are high impedance current sources Each of the these three RGB current outputs are specified to di rectly drive a 25 Q load doubly terminated 50 Q Reference Input and An external 1 235 V voltage reference is preferred to set up the analog outputs the ADV7129 The reference voltage is con nected to the Vggg input In the absence of an external refer ence the on chip voltage reference is internally connected to the pin The internal reference will set up the DAC cur rents although with slightly less accuracy REV
4. 0197 0 50 M NOM 4 PIN 1 IDENTIFIER 0 150 3 80 NOM 1 571 39 90 228 LUUD DUUM DAE TOP VIEW PINS DOWN 18 T ass 1 579 40 10 1 571 39 90 REV 0 19 96 01 9 41222 5 NI 20
5. Temperature Range Package Option Ambient Operating Temperature 0 to 70 o o Storage Temperature 65 C to 150 SOUS mes E04 Junction Temperature 150 Due to the specialized nature and application of this part it is not automati Lead Temperature Soldering 10 260 cally available to order Please contact your local sales office for details Vapor Phase Soldering 1 minute 220 Analog Outputs to GND GND 0 5 V to Vaa Current on Any DAC Output 60 mA NOTES lStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Analog Output Short Circuit to any Power Supply Common can be of an indefinite duration 304 LEAD PQFP PIN CONFIGURATION 22e a ADV7129 PQFP TOP VIEW Not to Scale PIN NO 1 IDENTIFIER QUAL LULA Ri gE CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment an
6. Vertical Sync Input TTL Compatible Input This control signal is latched on the rising edge of LOADIN CSYNC Composite Sync Input TTL Compatible Input This video control signal drives the analog outputs to the SYNC level It is only asserted during the blanking period and does not override any other control or data in put CR14 CR13 or CR12 of Command Register 1 must be set together with CR11 or Command Register 1 to decode SYNC onto the IOR IOR IOG IOG or IOB IOB analog outputs otherwise the SYNC input is ignored CE Chip Enable Input TTL Compatible Input This input must be set to logic 0 when writing or reading over the data bus 07 00 Internally data is latched on the rising edge of CE RW Read Write pin TTL Compatible Input This signal is latched on the falling edge of CE A high level indi cates a read operation and a low level indicates a write operation Register select pins TTL Compatible Inputs These inputs select which MPU port register is selected for writing or reading Data is latched on the falling edge of CE D7 D0 Data Bus TTL Compatible Input Output Bus Data including color palette values and device control infor mation is written to and read from the device over this 8 bit bidirectional databus Any unused bits of the data bus should be terminated through a resistor to either the digital power plane or GND LOADIN Pixel Data Load Input TTL Compatible Input This input latches the mu
7. compatible with RS 343A and RS 170 video stan dards without requiring external buffering An internal voltage reference is also provided to simplify system design The ADV7129 is fabricated in 5 V CMOS process ADV7129 is packaged in 304 pin PQFP package CIRCUIT DETAILS AND OPERATION Digital video or pixel data is latched into the ADV7129 over the pixel port The data is multiplexed and latched into the three 8 bit digital to analog converters DACs and output as an RGB video signal The ADV7129 can be broken into three sections for purposes of clarity of explanation 1 Pixel port and clock control circuit 2 port registers and cursor 3 Digital to analog converters and video outputs Pixel Port and Clock Circuits The pixel port of the ADV7129 is directly interfaced to the video graphics pipeline of a computer graphics subsystem It is connected directly through a gate array to the video RAM of the system s frame buffer The pixel port of the ADV7129 consists of Color Data RED GREEN BLUE Pixel Controls HSYNC VSYNC CSYNC BLANK associated clocking signals for the pixel port include LOADIN Clock Output LOADOUT Pixel Port Color Data ADV7129 has 192 color data inputs This supports 24 bit true color with 8 1 multiplexing Clock Input Color data is always latched on the rising edge of LOADIN LOADOUT is generated internally by the ADV7129 fre quency of LOADO
8. 0 A resistor is connected between the Reser Resets Reser input of the part and ground An value of 280 Q corresponds to the generation of two times RS 343A video lev els into a doubly terminated 50 load Figure 11 illustrates the resulting video waveform and the Video Output Truth Table il lustrates the corresponding control input stimuli On the ADV7129 SYNC can be encoded on any of the analog signals however in practice SYNC is generally encoded on either the IOG output or on all of the video outputs Any combination of DAC termination resistors and programming of SYNC and pedestal are possible provided that the maximum DAC current of 60 mA and the DAC output compliance specifications are adhered to The following tables show the current levels for different values of resistors and termination WHITE LEVEL 92 5 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL Figure 11 Composite Video Waveform SYNC Decoded Pedestal 7 5 IRE 13 ADV7129 Table I Video Output Truth Table 398 Ri 37 5 OIP with Sync with Sync DAC Description Enabled mA Disabled mA SYNC BLANK Input Data WHITE LEVEL 26 67 19 05 1 1 VIDEO Video 9 05 Video 1 44 1 1 Data VIDEO to BLANK Video 1 44 Video 1 44 0 1 Data BLACK LEVEL 9 05 1 44 1 1 00H BLACK to BLANK 1 44 1 44 0 1 00H BLANK LEVEL 1 62 0 1 0 xxH SYNC LEVEL 0 0 0 0 xxH
9. 150 GND 31 G5g 71 GND 111 B5g 151 GND 32 G5p 72 GND 112 B5p 152 GND 33 G5c 73 GND 113 B5c 153 GND 34 5 74 GND 114 B5g 154 GND 35 G54 75 GND 115 B54 155 GND 36 G4y 76 GND 116 VAA 156 GND 37 77 GND 117 GND 157 GND 38 78 GND 118 4 158 GND 39 G4g 79 GND 119 B4gG 159 Blc 40 G4p 80 GND 120 B4g 160 Blg No Connect 6 REV 0 ADV7129 Pin No Mnemonic Pin No Mnemonic Pin No Mnemonic Pin No Mnemonic 161 Bla 197 Raias 233 GND 269 LOADOUT 162 198 SENSE SYNCOUT 234 GND 270 163 199 VREF 235 271 164 200 GND 236 R g 272 R34 165 Bog 201 DO 237 273 R36 166 B0p 202 D1 238 R g 274 R3g 167 203 2 239 R6p 275 R35 168 204 240 R6c 276 R3p 169 205 GND 241 R6g 277 R3c 170 BLANK 206 Vaa 242 R64 278 R35 171 HSYNC 207 D4 243 5 279 R34 172 VSYNC 208 D5 244 5 280 R24 173 ODD EVEN 209 D6 245 R5g 281 R26 174 NC 210 D7 246 VAA 282 R2g 175 GND 211 CE 247 GND 283 R2g 176 GND 212 RW 248 Vaa 284 R2p 177 IOB 213 CO 249 GND 285 R2c 178 IOB 214 250 R5g 286 2 179 Rgser 215 R74 251 R5p 287 R24 180 Bcomp 216 7 252 R5c 288 181 VAA 217 R7g 253 R5g 289 182 Vaa 218 R7g 254 R54 290 183 219 R7p 255 4 291 184 220 7 256 4 292 185 IOG 221 7 257 R45 293 Ric 186 Reser 222 R74 258 R4g 294 187 Gcomp 223 GND 259 R4p 295 Rl 188 VAA 224 GND 260 R4c 296 189 VAA 225 GND 261 GND 297
10. Outputs CR11 This bit specifies whether the video SYNC is to be decoded onto the inverted analog outputs or ignored SYNC Recognition on Blue CR12 This bit specifies whether the video SYNC input is to be de coded onto the IOB analog output or ignored SYNC Recognition on Green CR13 This bit specifies whether the video SYNC input is to be de coded onto the IOG analog output or ignored SYNC Recognition on Red CR14 This bit specifies whether the video SYNC input is to be de coded onto the IOR analog output or ignored Pedestal Enable Control CR15 This bit specifies whether a 0 IRE or a 7 5 IRE blanking pedes tal is to be generated on the video outputs Display Mode Control CR17 This bit controls whether the display is interlaced or noninterlaced PEDESTAL CONTROL IOR IOG SYNC RECOGNITION CONTROL IOB IGNORE DECODE DISABLE BLANK ON INVERTED OUTPUTS DECODE BLANK ON INVERTED OUTPUTS SYNC CONTROL IOR IOG IOB DISABLE SYNC ON INVERTED OUTPUTS DECODE SYNC ON INVERTED OUTPUTS Figure 7 Command Register 1 REV 0 11 ADV7129 COMMAND REGISTER 2 CR2 Address Register A10 A0 411H This register contains a number of control bits as shown in the diagram CR2 is an 8 bit wide register CR27 CR24 CR22 and CR21 are reserved and should be set to logic 0 Figure 8 shows the various operations under the control of CR2 This register can b
11. ROG 190 Ggias 226 GND 262 GND 298 191 227 GND 263 VAA 299 GND 192 IOR 228 GND 264 LPF 300 GND 193 Reser 229 GND 265 GND 301 GND 194 230 GND 266 LOADIN 302 GND 195 Vaa 231 GND 267 GND 303 GND 196 Vaa 232 GND 268 CSYNC 304 GND No Connect REV 0 ADV7129 PIN DESCRIPTION Mnemonic Function R7 RO A H Red Pixel Port Inputs TTL Compatible Inputs Eight sets of eight bits latched on the rising edge of LOADIN G7 GO A H Green Pixel Port Inputs TTL Compatible Inputs Eight sets of eight bits latched on the rising edge of LOADIN B7 BO A H Blue Pixel Port Inputs TTL Compatible Inputs Eight sets of eight bits latched on the rising edge of LOADIN BLANK Composite Blank TTL Compatible Input This video control signal drives the analog outputs to the blanking level When BLANK is at logic 0 the pixel inputs are ignored Pedestal selection is controlled by Bit CR15 of Command Register 1 BLANK is latched on the rising edge of LOADIN ODD EVEN Odd Even Field Input TTL Compatible Input This input indicates which field of the frame is being dis played An even field is selected by setting ODD EVEN to logical 0 An odd field is selected by setting ODD EVEN to logical 1 ODD EVEN should be changed only during vertical blank HSYNC Horizontal Sync Input TTL Compatible Input This control signal is latched on the rising edge of LOADIN VSYNC
12. Reset Raser Reser DAC Output Full Scale Adjust Control Analog Input A resistor from this pin to ground sets the current in the DACs The current in the DACs is set according to the equations Tour 12 950 x Rggr SYNC not encoded on the DAC Output Tour 18 137 x Vgrer Rser SYNC encoded on the DAC Output To generate RS 343 A video levels on the DAC outputs a resistor value of 280 Q is recommended for doubly terminated 50 Q lines Any combination of value DAC termination resistor and programming of SYNC and pedestal are possible provided that the maximum DAC current and the DAC output compli ance specifications are adhered to For example in a doubly terminated 50 Q system with no SYNC or pedestal encoded on the DAC outputs value of 280 gives a DAC full scale output of 52 8 mA i e white to black value of 1 4 V This example would give a 6 dB reduction in noise and feedthrough on the DAC outputs compared to a 0 7 V full scale value but may require a 0 5X splitter at the monitor Rpras Red Bias node This node should be decoupled to Vaa with 0 01 uF capacitor Gpias Green Bias node This node should be decoupled to Va with a 0 01 capacitor Baias Blue Bias node This node should be decoupled to Vaa with 0 01 capacitor SENSE SYNCOUT Comparator Sense Output TTL Compatible Output This output will be logic 1 if one or more of the analog outputs exceeds the internal volta
13. UT is the internal clock frequency PCLK divided by 8 Other pixel data signals latched into the part by LOADIN in clude HSYNC BLANK VSYNC and CSYNC HSYNC VSYNC CSYNC BLANK The BLANK and SYNC video control signals drive the analog outputs to the blanking and sync levels respectively These are latched on the rising edge of LOADIN The SYNC information can be encoded onto any of the IOG IOR or IOB analog out puts by setting Bits CR12 CR13 or CR14 of Command Regis ter 1 to logic 1 The SYNC information is ignored if Bits CR12 CR13 and 14 of Command Register 1 are set to logic 0 The SYNC and BLANK information can be decoded onto the inverted outputs by setting CR10 and 11 of Command Register 1 to logic level 1 10 SENSE If any one or more of the analog outputs IOG IOR and IOB exceed the internal voltage reference level due to absence of CRT SENSE is set to logic 1 SENSE output can drive one CMOS load and can be used to determine the absence of a CRT monitor CLOCK CONTROL CIRCUIT The ADV7129 has an integrated clock control circuit This cir cuit is capable of generating the internal clocking signals lower frequency external clock generator is used by enabling the onboard PLL This fixed multiple PLL is used to speed up LOADIN by a factor of 8 This onboard 8 x clock multiplier is activated by setting Bit CR20 of Command Register 2 from logic 0 to logi
14. UTSFOR HSYNC 6 IMPROVED PERFORMANCE SYNC QRSET 0 OQ Grset 2800 ODD EVEN gt 0 CLOCK LOADIN 45MHz LOADOUT GND 7 500 Q SENSE SYNCOUT FERRITE BEAD BOARD GROUND ANALOG GROUND PLANE DIGITAL GROUND 1 PLANE DOESN T SHOW MPU PORT FOR CLARITY Figure 12 Typical Connection Diagram 16 REV 0 ADV7129 APPENDIX II THERMAL AND ENVIRONMENTAL CONSIDERATIONS The ADV7129 is a very highly integrated monolithic silicon device This high level of integration inevitably leads to consid eration of thermal and environmental conditions which the ADV7129 must operate in Reliability of the device is enhanced by keeping it as cool as possible In order to avoid destructive damage to the device the absolute maximum junction tempera ture must never be exceeded Certain applications depending on ambient temperature and pixel data rates may require forced air cooling or external heatsinks The following data is intended as a guide in evaluating the operating conditions of a particular appli cation so that optimum device and system performance is achieved It should be noted that information on package characteristics published herein may not be the most up to date at the time of reading this Advances in package compounds and manufacture will inevitably lead to improvements in the thermal data Please contact your local sales office for the most up
15. WRITE TO ADDRESS REGISTER UPPER BYTE WRITE TO REGISTERS READ FROM ADDRESS REGISTER LOWER BYTE READ FROM ADDRESS REGISTER UPPER BYTE READ FROM REGISTERS RESERVED REGISTER ACCESS 4FF 412 RESERVED 411 COMMAND REGISTER 2 410 RESERVED 40F RESERVED 40E RESERVED 40D RESERVED 40C RESERVED 40B RESERVED 40A RESERVED 409 RESERVED 408 RESERVED 407 BLUE DAC GAIN ERROR REGISTER 406 GREEN DAC GAIN ERROR REGISTER 405 RED DAC GAIN ERROR REGISTER 004 RESERVED 403 RESERVED 402 RESERVED 401 RESERVED COMMAND REGISTER 1 RESERVED A10 A0 400 000 3FF Figure 6 Control Registers INTERLACE ENABLE cuz DISABLE ENABLE PEDES TAL ENABLE ONTROL cris RESERVED ZERO MUST BE WRITTEN TO THIS BIT IGNORE DECODE SYNC RECOGNITION CONTROL IGNORE DECODE SYNC CON RECOGNITION TROL COMMAND REGISTER 1 Address Register 10 0 400 This register contains a number of control bits as shown in the diagram CRI is an 8 bit wide register Figure 7 shows the various operations under the control of CRI This register can be read from as well as written to Bit CR16 is reserved and should be set to logic 1 COMMAND REGISTER 1 BIT DESCRIPTION BLANK Control on Inverted Outputs CR10 This bit specifies whether the video BLANK is to be decoded onto the inverted analog outputs or ignored SYNC Control on Inverted
16. a pins the ADV7129 must have at least one 0 1 decoupling capacitor to GND These capacitors should be placed as close as possible to the device It is important to note that while the ADV7129 contains cir cuitry to reject power supply noise this rejection decreases with frequency Ifa high frequency switching power supply is used REV 0 the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane Digital Signal Interconnect The digital inputs to the ADV7129 should be isolated as much as possible from the analog outputs and other analog circuitry Also these input signals should not overlay the analog power plane Due to the high clock rates involved long clock lines to the ADV7129 should be avoided to reduce noise pickup Any active termination resistors for the digital inputs should be connected to the regular PCB power plane Vcc and not the analog power plane Analog Signal Interconnect The ADV7129 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch The video output signals should overlay the ground plane and not the analog power plane to maximize the high fre quency power supply rejection Digital Inputs especially Pixel Data Inputs and clocking signals LOADOUT LOADIN etc should never overlay any of the analog
17. c 1 It must be set up after power up MICROPROCESSOR MPU PORT ADV7129 supports a standard interface All the functions of the part are controlled via this MPU port Direct access is gained to the address register and all the control regis ters as well as the cursor palette The following sections de scribe the setup for reading and writing to all of the devices registers MPU Interface The MPU interface consists of a bidirectional 8 bit wide data bus and interface control signals RAW CE C1 CO Two write operations are required to set up the lower 8 bits and higher 2 bits of the Address Register Register Mapping The ADV7129 contains a number of onboard registers includ ing the Address Register Command Registers and Gain Error Registers Control Lines C1 C0 determine whether the Address Register is being pointed to upper or lower bytes or whether the other registers are being accessed The R W and CE control inputs allow read and write access registers can to read and written to Power On Reset After power up the ADV7129 must be set to perform a reset operation This is achieved by resetting the PLL a low to high transition on Bit CR20 of Command Register 2 This initial izes the pixel port such that the pixel sequence ABCDEFGH starts at This reset can be performed as the registers are be ing initialized The Command Registers power up in an indeter minate state and must be set up
18. d can discharge without detection WARNING lt Although ADV7129 features proprietary ESD protection circuitry permanent damage may At occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE REV 0 5 ADV7129 PIN ASSIGNMENTS Pin No Mnemonic Pin No Mnemonic Pin No Mnemonic Pin No Mnemonic 1 GND 41 4 81 GND 121 B4g 2 GND 42 4 82 GND 122 B4p 3 GND 43 G44 83 Gla 123 4 4 GND 44 VAA 84 124 4 5 GND 45 GND 85 0 125 B44 6 GND 46 VAA 86 126 7 47 GND 87 GOg 127 8 48 G3y 88 G0p 128 B3g 9 0 49 G3gG 89 G0c 129 B3g 10 R0g 50 G3 90 130 B3p 11 R04 51 G3g 91 131 B3c 12 G7y 52 G3p 92 7 132 13 53 G3c 93 B7g 133 B34 14 Gg 54 94 B7g 134 2 15 55 G3a 95 B7g 135 2 16 G7p 56 2 96 136 2 17 7 57 2 97 7 137 B2g 18 Gg 58 98 7 138 B2p 19 G7 59 G2g 99 B74 139 2 20 60 G2p 100 Boy 140 2 21 G g 61 G2c 101 141 2 22 62 2 102 142 1 23 G g 63 G2 103 B g 143 Blg 24 64 Gly 104 Bop 144 Blg 25 G c 65 105 B6c 145 Blg 26 66 106 B6g 146 Blp 27 G64 67 Glg 107 Boa 147 GND 28 G5g 68 Glp 108 5 148 GND 29 5 69 Glc 109 B5g 149 GND 30 G5g 70 110 B5g
19. de bit is released GAIN ERROR REGISTERS Address Register A10 A0 405H 407H The Red Green and Blue Gain Error Registers allow the user to compensate for any channel to channel variations in the video output system They control internal resistors from each of the three DAC outputs to GND i e they appear in parallel with the external termination resistor across the DAC outputs This allows the RGB output voltages to be adjusted as the value of is varied A logic 1 on any of the control bits GR06 to GR00 switches the appropriate resistor A logic 0 disables or open circuits the resistor Bit GRO7 of the Gain Error Register enables or disables the Gain Error Adjust Figure 9 shows the typical resistor values for these internal resistances versus PLL RESET O MONITOR PRESENT MONITOR NOT PRESENT THIS BIT SHOULD BE SET TO LOGIC 0 VCO OVERRIDE VCO OVERRIDE NORMAL PLL OPERATION CR23 0 IGNORE 1 DECODE RESERVED CR24 THIS BIT SHOULD BE SET TO LOGIC 0 RESET PLL RELEASE PLL RESERVED CR22 CR21 THESE BITS SHOULD BE SET TO LOGIC 0 Figure 8 Command Register 2 INTERNAL RESISTORS Rg Rs Ry R Ro GAIN ERROR CONTROL GRO07 0 DISABLE GAIN ERROR ADJ 1 ENABLE GAIN ERROR ADJ Ry Ro MONITOR REGISTER RESET 2800 GRO6 R6 470 GRO05 R5 9230 GRO04 R4 19260 GRO03 R3 34760 GRO02 R2 69790
20. e period from the trigger edge to the next edge of the output clock after the delay This measurement is repeated multiple times and the rms value is determined Specifications subject to change without notice TO OUTPUT PIN 211 IsouRcE Figure 1 LOADIN vs Pixel Input Data REV 0 3 ADV7129 LOADOUT LOADIN Diary Our INPy UT Pipe TO ay LINE ALO ANALOG X Y Y X X X Y V X X Y Y Y X X X XXXYXXXXYXYXXYYYyr DATA An Anat 2 Hy42 t tpp gt Figure 2 LOADIN vs Pixel Input Data tg t 4 a VALID 07 00 READ MODE 07 00 4 fr WRITE MODE 222 A 0 be Figure 3 Microprocessor Port MPU Interface Timing PCLK u lt tig zc WHITE LEVEL IOR TUM ANALOG IOG OUTPUTS FULL SCALE SYNCOUT 50 TRANSITION 10 4 gt m BLACK LEVEL NOTE THIS DIAGRAM IS NOT TO SCALE FOR THE PURPOSES OF CLARITY THE ANALOG OUTPUT WAVEFORM IS MAGNIFIED IN TIME AND AMPLITUDE W R T THE CLOCK WAVEFORM SYNCOUT IS A DIGITAL VIDEO OUTPUT SIGNAL 1 7 IS THE ONLY RELEVENT TIMING SPECIFICATION FOR SYNCOUT Figure 4 Analog Output Response vs LOADIN 4 REV ADV7129 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Vato GND iorri eedem eese e Wa ad eos Voltage on Any Digital Pin GND 0 5 to 0 5 Model
21. e read from as well as written to COMMAND REGISTER 2 BIT DESCRIPTION PLL Control CR20 This bit resets the PLL divider when set to logic 0 and re leases it when set to logic 1 SYNCOUT Control CR23 This bit is an enable for SYNCOUT If this bit is set to logic 1 the SENSE output becomes a pipelined version of CSYNC Otherwise the SENSE output remains unaffected SENSE Bit CR25 This output bit is used to determine the absence of a CRT monitor When 25 is set to logic 1 7 a CRT is not present With some diagnostic code the presence of loading on the indi vidual RGB lines can be determined The reference is generated by a voltage divider from the external voltage reference on the Vngr pin For the proper operation the following levels should be applied to the comparator by the IOR IOG and IOB outputs DAC Low Voltage lt 250 mV DAC High Voltage gt 450 mV SENSE OUTPUT RESERVED CR27 VCO Override Bit CR26 This bit is used to override the VCO and set the PLL to the lowest frequency possible If the external LOADIN source takes some time before it reaches its required frequency the internal PLL can become unstable as it tries to track to a varying LOADIN signal The VCO override bit can be set to logic level 0 and then released set to logic level 1 to allow the to track to the input after it has stabilized It is required to allow 200 us before the VCO overri
22. eed Monotonic 1 LSB Gray Scale Error 5 Gray Scale Binary Coding DIGITAL INPUTS Input High Voltage 2 0 Vaa 0 5 Input Low Voltage GND 0 5 0 8 V Input Current Ip Vin 0 4 or 2 4 10 Input Capacitance 10 pF DIGITAL OUTPUTS Output High Voltage Voy 400 pA 2 4 Output Low Voltage VoL lor 3 2 mA 0 4 V Floating State Leakage Current t10 Floating State Output Capacitance 10 pF ANALOG OUTPUTS Gray Scale Current Range 10 60 mA Output Current White Level Relative to Black 50 16 52 80 55 44 mA Black Level Relative to Blank 4 1 4 32 4 54 mA Blank Level Sync Disabled 0 5 50 LSB Size 223 DAC to DAC Matching 2 5 Output Compliance Voc 0 1 4 V Output Impedance 10 kQ Output Capacitance Cour 20 pF VOLTAGE REFERENCE Voltage Reference Range Vggr Vrer 1 234 for Specified 1 14 1 235 1 30 V Input Current Iyggr Performance 5 POWER REQUIREMENTS VAA 5 V Iaat Analog Current 160 200 mA Digital Current 360 MHz 360 400 mA Power Supply Rejection Ratio 0 12 DYNAMIC PERFORMANCE Clock and Data Feedthrough 30 Glitch Impulse 50 pV secs DAC to DAC Crosstalk 23 5 145 for all versions Temperature range Tm to 0 C 70 TJ Silicon Junction Temperature lt 100 3Static performance is measured with the Gain Error Registers set to 00H disabled 11 is measured with a typical dynamic
23. for the required operation The power on is activated when Va goes from 0 V to 5 V This is active for 1 us The ADV7129 should not be accessed during this period Register Accesses The MPU can write to or read from all of the ADV7129s regis ters Figure 6 shows the Control Registers and C1 C0 Control Input Truth Table The read write timing is controlled by the CE and R W inputs The Address Register determines which Control Register 15 being accessed The registers can be addressed directly by two write cycles to set up the high and low bytes of Address Register and then by a read or write cycle of the MPU REV 0 ADV7129 REGISTER PROGRAMMING The following section describes each register including Address Register and each of the Control Registers in terms of its configuration Address Register 10 0 As illustrated previously the C1 CO inputs in conjunction with the Address Register specify which control register or palette RAM location is accessed by the MPU port The Address Reg ister is 16 bits wide and can be read from as well as written to CONTROL REGISTERS A large bank of registers can be accessed using the Address reg ister and 1 0 Access is made first by writing the Address Register with the appropriate address to point to the particular Control Register and then performing an access to the Control Register ADDRESS REGISTER A10 A0 WRITE TO ADDRESS REGISTER LOWER BYTE
24. ge of the SENSE comparator circuit It can be used to determine the absence of a CRT monitor The value of the SENSE Output corresponds to the current pixel at the out puts The output can drive one CMOS load This pin can alternately be programmed to be a TTL sync output which is a delayed version of CSYNC VREF Voltage Reference Analog Input Output This should always have 0 1 UF decoupling capacitor attached between and Vaa If nothing else is connected then the DACs are driven by the internal voltage refer ence If it is required to use a more accurate reference then this pin acts as an overdrive input external 1 235 V voltage reference such as the AD1580 or equivalent is recommended to drive this input Note It is not recommended to use a resistor network to generate the voltage reference VAA Power Supply 5 5 The part contains multiple power supply pins all should be connected together to one common 5 V filtered analog power supply GND Analog Ground The part contains multiple ground pins all should be connected together to the system s ground plane REV 0 9 ADV7129 continued from page 1 The ADV7129 supports 24 bit true color formats where screen resolution is the primary design goal The individual Red Green and Blue pixel input ports allow true color image rendi tion at resolutions of 2048 x 2048 x 24 bit The ADV7129 is capable of generating RGB video output sig nals that are
25. he lead length between groups of Vaa and GND pins should by minimized so as to minimize inductive ringing Ground Planes The ground plane should encompass all ADV7129 ground pins voltage reference circuitry power supply bypass circuitry for the ADV7129 the analog output traces and all the digital signal traces leading up to the ADV7129 The analog ground plane should be separated from the system ground plane by a ferrite bead Power Planes The ADV7129 and any associated analog circuitry should have its own power plane referred to as the analog power plane This power plane should be connected to the regular PCB power plane Vcc at a single point through a ferrite bead This bead should be located within three inches of the ADV7129 The PCB power plane should provide power to all digital logic on the PC board and the analog power plane should provide power to all ADV7129 power pins and voltage reference circuitry Plane to plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane unless they can be arranged such that the plane to plane noise is common mode Supply Decoupling For optimum performance bypass capacitors should be installed using the shortest leads possible consistent with reliable opera tion to reduce the lead inductance Best performance is obtained with 0 1 uF ceramic capacitor decoupling Each group of Va
26. ltiplexed pixel data including BLANK HSYNC VSYNC CSYNC and ODD EVEN into the device This rising edge of this signal is used to latch in the video signal inputs It is also used a reference frequency to generate an 8 x multiple pixel clock using the fixed reference onboard PLL LOADOUT Pixel Data Load Output TTL Compatible Output This digital output is PCLK 8 If the onboard phase lock loop is used it has the same phase as LOADIN LPF Low Pass Filter Pin This pin stabilizes the internal PLL The following network is recommended VAA 0 1pF i 0 001 1000 Figure 5 REV 0 ADV7129 Mnemonic Function IOR IOG IOB Red Green amp Blue Current Outputs High Impedance Current Sources These RGB video outputs are specified to directly drive RS 343A and RS 170 video levels into doubly terminated 50 Q or 75 Q loads IOR IOG IOB Differential Red Green amp Blue Current Outputs High Impedance Current Sources These RGB video outputs are specified to directly drive RS 343A and RS 170 video levels into doubly terminated 50 Q or 75 Q loads If the complementary outputs are not required then these outputs should be tied to GND Red Compensation pin This pin should be bypassed to Vaa with 0 01 uF capacitor Green Compensation pin This pin should be bypassed to Vaa with 0 01 capacitor Bcomp Blue Compensation pin This pin should be bypassed to with 0 01 capacitor
27. pattern satisfying the absolute maximum current spec for the DACs 5Clock and Data Feedthrough is a function of the amount of overshoot and undershoot on the digital inputs Glitch impulse includes clock and data feedthrough TTL input values 0 V to 3 V with input rise fall times 23 ns measured at the 10 and 90 points Timing reference points are at 50 for inputs and outputs to DAC crosstalk is measured by holding one DAC high while the other two DACs are making low to high and high to low transitions Specifications subject to change without notice REV 0 ADV7129 Vl 25V Vnrr 41 235 V Reser Reser Reset 2800 25 for 106 10 pF TIM SPEC IFICATIONS All specifications to Ty unless otherwise noted Parameter Conditions Min Typ Max Units CLOCK CONTROL amp PIXEL PORT LOADIN Clocking Rate cr 10 45 MHz LOADIN Cycle Time t 16 67 ns LOADIN Low Time 1 6 67 ns LOADIN High Time t 6 67 ns LOADIN to LOADOUT Delay ty 5 ns Pixel Setup Time t 1 0 ns Pixel Hold Time tg 4 2 ns MPU PORT R W Co Setup Time t 10 2 5 ns C1 Hold Time 10 0 5 ns CE Low Time to 25 ns CE High Time tio 25 ns CE Asserted to Data Bus Driven 11 2 5 ns CE Asserted to Data Bus Valid tj 20 ns CE Negated to Data Bus Invalid 113 1 ns CE Negated to Data Bus Three Stated 114 15 ns Write Data 27 00 Setup Time 115 10 ns W
28. rite Data D7 D0 Hold Time 116 10 ns ANALOG OUTPUTS Analog Output Delay 1 360 MHz 5 ns Analog Output Rise Fall Time tj 0 8 ns Analog Output Transition Time 119 25 ns RGB Analog Output Skew tsk 1 5 ns Pipeline Delay tpp 19 PCLKs PLL PERFORMANCE Jitter 10 LOADIN 45 55 ps rms NOTES inputs values are 0 V to 3 V with input rise fall times 23 ns measured between the 10 and 90 points Timing reference points at 50 for inputs and out puts Analog output load lt 10 pF Databus D7 D0 loaded as shown in Figure 1 Digital output load for SENSE x30 pF 2 5 for all versions Temperature range Tmn to Tmax 0 C to 70 Pixel Port consists of the following inputs Pixel Inputs RED A H BLUE A H GREEN A H gt Output Delay is measured from the 50 rising edge of LOADIN to the 50 point of full scale transition on the A pixel t includes the analog delay due to DACs and internal gate transitions plus the pipeline stages delay The output delay for pixels B H will be the output delay to the A pixel 117 plus the appropriate number of clock cycles Output rise fall time is measured between the 10 and 90 points of full scale transition Settling time is measured from the 50 point of full scale transition to the output remaining within 1 Settling Time does not include clock and data feedthrough STitter is measured by triggering on the output clock delayed by 15 us and then measuring the tim
29. signal circuitry and should be kept as far away as possible For best performance the analog outputs should each have a 50 Q load resistor connected to GND These resistors should be placed as close as possible to the ADV7129 so as to minimize reflections There are a number of precautions that the user can take to minimize the effects of data feedthrough a Apply external filtering to the DAC outputs b Reduce input voltage risetime From experiments it has been seen that a reduction from 2 ns to 4 ns gives signifi cant improvement c Reduce input voltage swing A reduction from 5 V to 3 V gives significant improvement d Use series resistors on the pixel inputs e g 100 Q e The part can be run at 2x DAC current levels as shown in the DAC output The differential outputs can then be connected through a differential to single balun trans former to eliminate common mode noise A phase split ter should be used to reduce the 2x levels to 1x at the monitor end 15 ADV7129 REPEATED FOR EACH GROUP OF Va PINS 0 1pF 0 01pF v Vv FERRITE BEAD SH 45V VAA BOARD SUPPLY 0 ANALOG POWER PLANE 33uF VAA v 10 VREF 132 50 Reias EACH PIXEL Gaias 0 01pF DATA Bgias 7 VAA ADV7129 BLANK gid EACH 22 2 VSYNC 0 01pF AN OPTIONAL BALUN TRANSFORMER IU UC CAN BE USED ON VIDEO AND VAA COMPLEMENTARY OUTP
30. sters This MPU port may be updated at any time without causing sparkle effects on the screen ADV is a registered trademark of Analog Devices Inc continued on page 10 FUNCTIONAL BLOCK DIAGRAM VAA VSYNC HSYNC CSYNC BLANK ODD EVEN PIXEL A E DATA D COZ RED GREEN E BLUE INT PIXEL CLOCK CONTROL REGISTERS MPU PORT LOADOUT CE R W ADV is a registered trademark of Analog Devices Inc REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices BLANK AND SYNC SENSE SYNCOUT VOLTAGE REFERENCE 07 00 One Technology Way 9106 Norwood 02062 9106 U S A Tel 617 329 4700 World Wide Web Site http www analog com Fax 617 326 8703 Analog Devices Inc 1996 ADV7129 SPECIFICATION Vag 5 Varr 41 235 V Reset Reset 280 Ri 25 10 pF All specifications to unless otherwise noted Versions Conditions Min Typ Max Units STATIC PERFORMANCE Resolution Each DAC 8 Bits Accuracy Each DAC Integral Nonlinearity 1 LSB Differential Nonlinearity Guarant
31. to date information Package Characteristics Junction to Case Thermal Resistance for this particular part is 8 9 C W Note is independent of airflow maximum silicon junction temperature should be limited to 100 Temperatures greater than this will reduce long term device reliability To ensure that the silicon junction tempera Vaa 5 ture stays within prescribed limits the addition of an external heatsink can be used if the junction temperature is brought be yond the maximum limit Junction to Ambient 054 Thermal Resistance for this particu lar part is 25 9 C W Still Air Oja will significantly decrease in air flow Thermal Model The junction temperature of the device in a specific application 15 given by T4 Pp Oca 1 where Junction Temperature of Silicon T4 Ambient Temperature Pp Power Dissipation W Junction to Case Thermal Resistance C W Case to Ambient Thermal Resistance C W Junction to Ambient Thermal Resistance C W CURRENT mA 2 a eo 425 160 200 280 320 360 SPEED MHz Figure 13 Supply Current vs Frequency REV 0 17 ADV7129 OUTLINE DIMENSIONS Dimensions shown in inches and mm 304 Lead Plastic Quad Flatpack 1 677 42 60 NOM 0 167 4 23 NOM S 304 1 579 40 10 SEATING PLANE 0

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