ANALOG DEVICES ADV7195 handbook(1)(1)
Contents
1. naan messes Multiformat Progressive Scan HDTV ANALOG DEVICES Encoder with Three 11 Bit DACs and 10 Bit Data Input ADV7195 FEATURES INPUT FORMATS YCrCb in 2 x 10 Bit 4 2 2 or 3 x 10 Bit 4 4 4 Format Compliant to SMPTE 293M 525p ITU R BT1358 625p SMPTE274M 1080i SMPTE296M 720p and Any Other High Definition Standard Using Async Timing Mode RGB in 3 x 10 Bit 4 4 4 Format OUTPUT FORMATS YPrPb Progressive Scan EIA 770 1 EIA 770 2 YPrPb HDTV EIA 770 3 RGB Levels Compliant to RS 170 and RS 343A 11 Bit Sync DAC A 11 Bit DACs DAC B DAC C PROGRAMMABLE FEATURES Internal Test Pattern Generator with Color Control Y C Delay x Gamma Correction Individual DAC On Off Control 54 MHz Output 2x Oversampling Sharpness Filter with Programmable Gain Attenuation Programmable Adaptive Filter Control Undershoot Limiter Open Control 1209 Filter CGMS A 525p 2 Wire Serial MPU Interface Single Supply 3 3 V Operation 52 MOFP Package APPLICATIONS Progressive Scan HDTV Display Devices MPEG at 81 MHz Progressive Scan HDTV Projection Systems Digital Video Systems High Resolution Color Graphics Image Processing Instrumentation Digital Radio Modulation Video Signal Reconstruction GENERAL DESCRIPTION ADV7195 is a triple high speed digital to analog encoder on a single monolithic chip It consists of three high speed video D A converters with T2. 5 5 5 5 54 4 4 4 5 __587 ZERO SHOULD BE WRITTEN HERE ADV7195 SUBADDRESS REGISTER ADDRESS SR6 585 584 583 582 581 580 ADV7195 Subaddress Register SR7 SR0 Communications Register is 8 bit write only register After the part has been accessed over the bus and a read write operation is selected the subaddress is set up The Sub address Register determines to from which register the operation takes place Figure 14 shows the various operations under the control of the Subaddress Register 0 should always be written to SR7 Register Select SR6 SRO0 These bits are set up to point to the required starting address ADV7195 SUBADDRESS REGISTER ADOREGG SHi SPA SAS Hi MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 MODE REGISTER 5 COLOR Y COLOR CR COLOR CB MODE REGISTER 6 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED FILTER GAIN CGMS DATA REGISTER 0 CGMS DATA REGISTER 1 CGMS DATA REGISTER 2 GAMMA CORRECTION REGISTER 0 GAMMA CORRECTION REGISTER 1 GAMMA CORRECTION REGISTER 2 GAMMA CORRECTION REGISTER 3 GAMMA CORRECTION REGISTER 4 GAMMA CORRECTION REGISTER 5 GAMMA CORRECTION REGISTER 6 GAMMA CORRECTION REGISTER 7 GAMMA CORRECTION REGISTER 8 GAMM
3. 29 Sync PrPb MR52 29 Color Output Swap MR53 29 Reserved 54 57 29 DAC TERMINATION AND LAYOUT CONSIDERATIONS RERO 30 Voltage Reference 1 ea Rn 30 PC BOARD LAYOUT CONSIDERATIONS 30 Supply Decoupling 31 Digital Signal 31 Analog Signal Interconnect 31 Video Output Buffer and Optional Output Filter 31 OUTLINE DIMENSIONS 36 ADV7195 SPECIFICATIONS Vaa 3 1 5 10 3 45 VREF 1 235 V 2410 Rioap 300 All specifications Twin to Tmax 0 C 3 3 V SPEC IFICATIONS to 70 C unless otherwise noted 110 C Parameter Min Typ Max Unit Test Conditions STATIC PERFORMANCE Resolution Each DAC 11 Integral Nonlinearity 1 5 LSB Differential Nonlinearity 0 9 2 0 LSB DIGITAL OUTPUTS Output Low Voltage VoL 0 4 V Ismx 3 2 mA Output High Voltage 2 4 V Isource 400 Three State Leakage Current 10 uA Vin 0 4 V Three State Output Capacitance 4 pF DIGITAL AND CONTROL INPUTS Input High Voltage 2 V Input Low Voltage 0 8 0 65 V Input Current 0 uA Vin 0 0 V Input Capacitance 4 pF ANALOG OUTPUTS Full Scale Output Current 3 92 4 25 4 56 mA DAC
4. 750 1 2 5 7 25 27 74 Figure 69 SMPTE296M 720p DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL E aa 1125 2 560 DISPLAY FIELD 2 4 VERTICAL BLANKING INTERVAL 561 562 563 564 565 566 567 568 569 570 583 584 585 70 SMPT274M REV 35 ADV7195 OUTLINE DIMENSIONS Dimensions shown in inches and mm 52 Lead Plastic Quad Flatpack S 52 0 557 14 15 5094 0239 0 537 13 65 0 09 2 13 0 398 10 11 _ 0 037 0 95 s 0 390 9 91 0 026 065 1 SEATING PLANE TOP VIEW PINS DOWN 0 012 0 30 0 006 0 0 008 0 20 gt j 0 006 0 15 0 0256 0 014 0 35 0 082 2 09 0 65 0 010 0 25 0 078 1 97 BSC 36 0 398 10 11 0 390 9 91 0 557 14 15 0 537 13 65 REV C00232 0 5 02 PRINTED IN U S A
5. 360 55656565665656 gt 6 4 REV ADV7195 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Input Output Function 1 12 Vpp P Digital Power Supply 2 11 0 9 10 Bit Progressive Scan HDTV Input Port for Y Data Input for G data when RGB data is input 13 52 GND G Digital Ground 14 23 Cr0 Cr9 I 10 Bit Progressive Scan HDTV Input Port for Color Data in 4 4 4 Input Mode In 4 2 2 mode this input port is not used Input port for R data when RGB data is input 24 35 VAA P Analog Power Supply 25 CLKIN I Pixel Clock Input Requires a 27 MHz reference clock for standard operation in Progressive Scan Mode or a 74 25 MHz 74 1758 MHZ reference clock in HDTV mode 26 33 AGND G Analog Ground 27 DV I Video Blanking Control Signal Input 28 VSYNC I VSYNG Vertical Sync Control Signal Input or TSYNC Input Control Signal in TSYNC Async Timing Mode 29 HSYNC I HSYNC Horizontal Sync Control Signal Input or SYNC Input Control Signal in SYNC Async Timing Mode 30 SCL I MPU Port Serial Interface Clock Input 31 SDA IO MPU Port Serial Data Input Output 32 DACC Color Component Analog Output of Input Data on Cb Cr9 0 Input Pins 34 DACA Y Analog Output 36 DACB Color Component Analog Output of Input Data on Cr9 Cr0 Input Pins 37 Compensation Pin for DACs Connect 0 1 Capacitor from COMP pin to Vaa 38 A 2470 Q resistor for input ranges 64 940 and 64 960 output standards EIA 1
6. 27 Test Pattern Enable MR12 27 Test Pattern Hatch Frame MR13 27 VBI Open 14 225525 4 6 ERAS 27 Reserved 15 17 27 MODE 2 22 5 2 52 28 MRI MR27 MR20 bu oed ce whe RE ean 28 2 BIT DESCRIPTION 28 Y Delay MR20 MR22 28 ADV7195 Color Delay MR23 MR25 28 Reserved 26 27 28 REGISTER 3 epo Inoue ah T RR ees 28 MR37 MR30 28 BIT DESCRIPTION 28 HDTV Enable MR30 28 Reserved MR31 MR32 28 DAC A Control MR33 28 DAC B Control MR34 28 DAC Control MR35 28 Reserved 36 37 28 MODE REGISTER 4 29 MR47 MR40 29 BIT DESCRIPTION 29 Timing Reset MR40 29 Reserved MRA41 MR47 29 MODE REGISTER 5 scree ces eee ee eva ews 29 MR5 MR57 MR50 29 MR5 DESCRIPTION 29 Reserved MR50 ii eee nii oed 29 RGB 51
7. Address SR4 SR0 03H Figure 54 shows the various operations under the control of Mode Register 2 MR3 BIT DESCRIPTION HDTV Enable MR30 When this bit is set to 1 the ADV7195 reverts to HDTV mode When set to 0 the ADV7195 reverts to Progressive Scan Mode PS mode Reserved MR31 MR32 0 must be written to these bits DAC A Control MR33 Setting this bit to 1 enables DAC A otherwise this DAC is powered down DAC B Control MR34 Setting this bit to 1 enables DAC B otherwise this DAC is powered down DAC C Control MR35 Setting this bit to 1 enables DAC C otherwise this DAC is powered down Reserved MR36 MR37 A 0 must be written to these bits Y DELAY MR22 MR21 MR20 0 ZERO MUST BE WRITTEN TO THESE BITS Figure 54 Mode Register 3 28 REV ADV7195 MODE REGISTER 4 MR4 MR47 MR40 Address SR4 SR0 04H Figure 55 shows the various operations under the control of Mode Register 4 MR4 BIT DESCRIPTION Timing Reset MR40 Toggling MR40 from low to high and low again resets the inter nal horizontal and vertical timing counters Reserved MR41 MR47 0 must be written to these bits MODE REGISTER 5 MRS MR57 MR50 Address SRA SR0 05H Figure 56 shows the various operations under the control of Mode Register 5 MRS BIT DESCRIPTION Reserved 50 This bit is reserved for the revision code
8. RGB Mode MR51 When RGB mode is enabled MR51 1 the ADV7195 accepts unsigned binary RGB data at its input port This control is also available in Async Timing Mode Sync on PrPb 52 By default the color component output signals Pr Pb do not con tain any horizontal sync pulses If required they can be inserted when MR52 1 This control is not available in RGB Mode Color Output Swap 53 By default DAC B is configured as the Pr output and DAC C as the Pb output In setting this bit to 1 the DAC outputs can be swapped around so that DAC B outputs Pb and DAC C out puts Pr Table X demonstrates this in more detail Reserved MR54 MR57 A 0 must be written to these bits Table X Relationship Between Input Pixel Port MR53 and DAC B DAC C Outputs In 4 4 4 Input Mode Color Data Analog Output Input on Pins MR53 Signal Cr9 0 0 DAC B Cb Cr9 0 0 DACC Cr9 0 1 DAC Cb Cr9 0 1 DACB In 4 2 2 Input Mode Color Data Analog Output Input on Pins MRS53 Signal Cr9 0 Oorl Not Operational Cb Cr9 0 0 DAC C Pb Cb Cr9 0 1 DAC C Pr MR47 MR41 ZERO MUST BE WRITTEN TO THESE BITS MR57 MR54 DAC B PR 0 DISABLE RESERVED FOR TO THESE BITS DACC R 1 ENABLE REVISION CODE SYNC ON PrPb RGB MODE 0 DISABLE 1 ENABLE Figure 56 Mode Register 5 REV A 29 ADV7195 DAC TERMINATION AND LAYOUT C
9. Undershoot Limiter A limiter can be applied to the Y data before it is applied to the DACs Available limit values are 1 5 IRE 6 IRE 11 IRE below blanking This functionality is available in Progressive Scan Mode only Filter A selectable internal filter allows significant noise reductions on the I C interface In setting ALSB high the input bandwidth on the lines is reduced and pulses of less than 50 ns are not passed to the PC controller Setting ALSB low allows greater input bandwidth on the lines Internal Test Pattern Generator The ADV7195 can generate a crosshatch pattern white lines against a black background Additionally the ADV7195 can output a uniform color pattern The color of the lines or uni form field frame can be programmed by the user Y CrCb Delay The Y output and the color component outputs can be delayed wrt the falling edge of the horizontal sync signal by up to four clock cycles Gamma Correction Gamma correction may be performed on the luma data The user has the choice to use either of two different gamma curves or B At any one time one of these curves is operational if gamma correction is enabled Gamma correction allows the mapping of the luma data to a user defined function 54 MHz Operation In Progressive Scan mode it is possible to operate the three output DACs at 54 MHz or 27 MHz The ADV7195 is sup plied with a 27 MHz clock synced with the incoming data I
10. 1006 l FIELDS li v 12 8222ms Figure 47 Output Signal from Adaptive Filter Control REV A 25 ADV7195 HDTV MODE MODE REGISTER 0 MR07 MR00 Address SR4 SR0 00H Figure 50 shows the various operations under the control of Mode Register 0 MRO DESCRIPTION Output Standard Selection MR00 MR01 These bits are used to select the output levels from the ADV7195 If EIA 770 3 MR01 00 00 is selected the output levels will be 0 mV for blanking level 700 mV for peak white Y channel 350 mV for Pr Pb outputs and 300 mV for tri level sync If Full Input Range MR01 00 10 is selected the output levels will be 700 mV for peak white for the Y channel 350 mV for Pr Pb outputs and 300 mV for Sync This mode is used for RS 170 RS 343A standard output compatibility Sync insertion on the Pr Pb channels is optional For output levels refer to the Appendix Input Control Signals MR02 MR03 These control bits are used to select whether data is input with external horizontal vertical and blanking sync signals or if the data is input with embedded EAV SAV codes An Asynchro nous timing mode is also available using TSYNC SYNC and DV as input control signals These timing control signals have to be programmed by the user TSYNC 5 fF SET 06 1 Figure 49 shows an example of how to program the ADV7195 to accept a different high definition stan
11. power and ground lines This can be achieved by shielding the digital inputs and providing good decoupling The lead length between groups of Vaa and AGND and Vpp and DGND pins should be kept as short as possible to minimize inductive ringing It is recommended that a four layer printed circuit board be used With power and ground planes separating the layer of the signal carrying traces of the components and solder side layer Placement of components should be considered to separate noisy circuits such as crystal clocks high speed logic circuitry and analog circuitry should be a separate analog ground plane AGND and a separate digital ground plane GND Power planes should encompass a digital power plane and an analog power plane The analog power plane should contain the DACs and all associated circuitry and the Veer circuitry digital power plane should contain all logic circuitry The analog and digital power planes should be individually con nected to the common power plane at one single point through a suitable filtering device such as a ferrite bead POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP COMP Cb Cr0 Cb Cr9 Cr0 Cr9 0 9 UNUSED ADV7195 INPUTS SHOULD BE GROUNDED VAA 4 7 2 6 3V 27MHz 74 25MHz OR 74 1758MHz CLOCK v OUTPUT Pr V OUTPUT U OUTPUT MPU BUS 2 82 0 Figure 57 Circuit Layout 3
12. 0 iita cree t PEG aa rh 23 CGMS CRC MR2T 4 esed ade Ra ee ees 17 ADAPTIVE FILTER GAIN3 23 APGSCABOSIT U pes pco quis EXP 23 2 REV A ADAPTIVE FILTER THRESHOLD A 23 AFTA 7 0 4 Par n 23 ADAPTIVE FILTER THRESHOLDB 23 0 5 2222 9 49 kx inai 23 ADAPTIVE FILTER THRESHOLD C 23 0 59 23 SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATIONS EXAMPLES 24 Sharpness Filter Application 24 Adaptive Filter Control Application 25 HDTV MODE ue De bee IAE a RES 26 MODE REGISTER 0 26 MRO 07 26 MRO DESCRIPTION 26 Output Standard Selection MR00 MR01 26 Input Control Signals 2 26 Reserved MRO04 re e X gs 26 Input Standard MR05 26 DV Polarity isse ure e eoe os 26 Reserved eo ed 26 MODE REGISTER 1 6 consi nr 27 MRI 17 10 27 BIT DESCRIPTION 255525 565 RR woss 27 Pixel Data Enable 1 27 Input Format
13. 0 1 DAC Cb Cr9 0 1 DACB In 4 2 2 Input Mode Color Data Analog Output Input on Pins MR53 Signal Cr9 0 Oorl Not Operational Cb Cr9 0 0 DAC C Pb Cb Cr9 0 1 DAC C Pr Gamma Curve MR54 This bit selects which of the two programmable gamma curves 18 to be used When setting MR54 to 0 the gamma correction curve selected is Curve A Otherwise Curve B is selected Each curve will have to be programmed by the user as explained in the Gamma Correction Registers section Gamma Correction MR55 enable Gamma Correction and therefore activate the gamma curve programmed by the user this bit must be set to 1 Other wise the programmable Gamma Correction facility is bypassed Programming of the gamma correction curves is explained in the Gamma Correction Registers section Adaptive Mode Control 56 For this control to be effective Adaptive Filter Control must be enabled MR57 1 as well as the Sharpness Filter 17 41 For filter plots refer to Sharpness Filter Control and Adaptive Filter Control section REV A Adaptive Filter Control MR57 This bit enables the Adaptive Filter Control when set to 1 Sharpness Filter must be enabled as well MR17 1 The Adaptive Filter Controls is explained in more detail under Sharpness Filter Control and Adaptive Filter Control section COLOR CY CY7 CY0 Address SR4 SR0 06H CY7 CYO COLOR Y VALUE Figure 26 Colo
14. O0hex Mode Register 0 O0hex Olhex Mode Register 1 85hex 02 Mode Register 2 O0hex Mode Register 3 38hex O4hex Mode Register 4 O0hex 05 Mode Register 5 O0hex 09hex Mode Register 6 3Ehex 500 4 005 yw CH1 ALL FIELDS REF2 500mV 4 0045 9 99976ms b Figure 44 Sharpness Filter Control with Different Gain Settings for Filter Gain 24 REV ADV7195 In toggling MR17 Sharpness Filter Enable Disable and setting the Filter Gain register value to 99hex it can be seen that the line contours of the crosshatch pattern change their sharpness Adaptive Filter Control Application Figure 45 shows a typical signal to be processed by the Adaptive Filter Control block M 100ns 100mV wis ALL FIELDS li v 12 8222ms Figure 45 Input Signal to Adaptive Filter Control The following register settings were used to obtain the results Figure 46 shows the output signal when changing the Adaptive Filter Mode to Mode B MR56 1 100 5 w FIELDS li v 12 8222ms Figure 46 Output Signal from Adaptive Filter Control The Adaptive Filter Control can also be demonstrated using the internally generated crosshatch test pattern and toggling the Adaptive Filter Control Bit MR57 using the following register
15. enabled MR2 BIT DESCRIPTION Y Delay MR20 MR22 This control bit delays the Y signal with respect to the falling edge of the horizontal sync signal by up to four pixel clock Y DELAY cycles Figure 21 demonstrates this facility Color Delay MR23 MR25 This control allows delay of the color signals with respect to the NO DELAY falling edge of the horizontal sync signal by up to four pixel clock cycles Figure 21 demonstrates this facility CGMS Enable MR26 OUTPUT When this bit is set to 1 CGMS data is inserted on Line RS 41 in 525p mode The CGMS conforms to CGMS A EIA J CPR1204 1 Transfer Method of Video ID information using vertical blanking interval 525p System March 1998 and 2 DELAY L IEC61880 1998 video systems 525 60 video and accompanied data using the vertical blanking interval analog interface NO DELAY MAX DELAY Y DELAY MR22 MR21 MR20 CGMS ENABLE DISABLE ENABLE CGMS CRC wn2z7z DISABLE ENABLE COLOR DELAY MR25 MR24 MR23 Figure 22 Mode Register 2 REV A 17 ADV7195 MODE REGISTER 3 MR3 MR37 MR30 Address SR4 SR0 03H Figure 23 shows the various operations under the control of Mode Register 3 BIT DESCRIPTION HDTV Enable MR30 When this bit is set to 1 the ADV7195 reverts to HDTV mode refer to HDTV mode section When set to 0 the ADV7195 18 set up in Prog
16. protocol must be followed First the master initiates a data transfer by establishing a Start condition defined by a high to low transi tion on SDA while SCL remains high This indicates that an address data stream will follow All peripherals respond to the Start condition and shift the next eight bits 7 bit address RAW bit The bits are transferred from MSB down to LSB The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse This is known as an acknowledge bit other devices withdraw from the bus at this point and maintain an idle condition The idle condition is where the device monitors the SDA and SCL lines waiting for the Start condition and the correct transmitted address The R W bit determines the direction of the data 11 ADV7195 A Logic 0 on the LSB of the first byte means that the master will write information to the peripheral Logic 1 on the LSB of the first byte means that the master will read information from the peripheral ADV7195 acts as a standard slave device on the bus The data on the SDA pin is 8 bits long supporting the 7 bit addresses plus the R W bit It interprets the first byte as the device address and the second byte as the starting subaddress The subaddresses autoincrement allowing data to be written to or read from the starting subaddress A data transfer is always terminated by a Stop condition The user can a
17. result in a gamma curve shown on the next page assuming a ramp signal as an input 300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT 250 d SIGNAL OUTPUT 200 a 0 5 O 150 o 9 100 z SIGNAL INPUT 50 0 0 50 100 150 200 250 LOCATION Figure 35 Signal Input Ramp and Signal Output for Gamma 0 5 2 1 ADV7195 300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES e SIGNAL OUTPUTS 200 GAMMA CORRECTED AMPLITUDE a e 0 50 100 150 200 250 LOCATION Figure 36 Signal Input Ramp and Selectable Gamma Output Curves gamma curves shown in Figure 36 are examples only any user defined curve is acceptable in the range of 16 240 SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL Three Filter modes are available on the ADV7195 one Sharpness Filter mode and two Adaptive Filter modes SHARPNESS FILTER MODE enhance or attenuate the Y signal in the frequency ranges shown in Figure 37 the following register settings must be used Sharpness Filter must be enabled 17 1 and Adaptive Filter Control must be disabled MR57 0 To select one of the 256 individual responses the according gain values for each filter which range from 8 to 7 must be programmed into the Filter Gain register ADAPTIVE FILTER MODE Adaptive Filter Threshold A B C
18. settings shown in Figure 47 i e to remove the ringing on the Y signal Table VIII Input data was generated by an external signal source Address Register Setting A00hex Mode Register 0 40hex Table VII aab Olhex Mode Register 1 85hex Address Register Setting 02hex Mode Register 2 O0hex Mode Register 3 78hex 00 Register 0 40hex 4 Mode Register 4 O0hex Olhex Mode Register 8lhex 5 Mode Register 5 80hex 02hex Mode Register 2 O0hex Color Y 6Chex 03hex Mode Register 3 78hex O7hex Color Cr 52hex O04hex Mode Register 4 O0hex O8hex Color Cb 52hex 5 Mode Register 5 80hex h Mode Resi Eh 9 Mode Register 6 3Ehex 09 is egister 6 10hex Filter Gain O0hex 10 Filter Gain O0hex 22hex Adaptive Filter Gain 1 AChex 22hex Adaptive Filter Gain 1 AChex 23hex Adaptive Filter Gain 2 9Ahex 23hex Adaptive Filter Gain 2 9Ahex 24hex Adaptive Filter Gain 3 88hex 24hex Adaptive Filter Gain 3 88hex 25hex Adaptive Filter Threshold A 28hex 25hex Adaptive Filter Threshold A 28hex h Adaptive Filter Threshold Fh 26hex Adaptive Filter Threshold B 3Fhex 26 3Fhex 27 Adaptive Filter Threshold 64hex 27hex Adaptive Filter Threshold 64hex TEK RUN me TRIG D 1 1
19. 0 REV ADV7195 DAC output traces on a PCB should be treated as transmission lines It is recommended that the DACs be placed as close as possible to the output connector with the analog output traces being as short as possible less than 3 inches The DAC termi nation resistors should be placed as close as possible to the DAC outputs and should overlay the PCB s ground plane As well as minimizing reflections short analog output traces will reduce noise pickup due to neighboring digital circuitry Supply Decoupling Noise on the analog power plane can be further reduced by the use of decoupling capacitors Optimum performance is achieved by the use of 0 1 ceramic capacitors Each of group of V44 or Vpp pins should be indi vidually decoupled to ground This should be done by placing the capacitors as close as possible to the device with the capaci tor leads as short as possible thus minimizing lead inductance Digital Signal Interconnect digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry Digital signal lines should not overlay the analog power plane ADV7195 7 45V Y AD8057 t 1 45V O 08057 Due to the high clock rates used long clock lines to the ADV7195 should be avoided to minimize noise pickup Any active pull up termination resistors for the digital inputs should be connected to the digital power plane and not th
20. 0 C unless otherwise noted 3 3 V TIMING SPECIFICATIONS Parameter Min Typ Max Unit Conditions MPU PORT SCLOCK Frequency 0 400 kHz SCLOCK High Pulsewidth t 0 6 us SCLOCK Low Pulsewidth 5 1 3 us Hold Time Start Condition 13 0 6 us After this Period the 1st Clock Is Generated Setup Time Start Condition t4 0 6 us Relevant for Repeated Start Condition Data Setup Time 15 100 ns SDATA SCLOCK Rise Time 16 300 ns SDATA SCLOCK Fall Time t 300 ns Setup Time Stop Condition tg 0 6 us RESET Low Time 100 ns ANALOG OUTPUTS Analog Output Delay 1 2 10 ns Analog Output Skew 0 5 ns CLOCK CONTROL AND PIXEL PORT 27 Progressive Scan Mode 74 25 HDTV Mode 81 MHz ASYNC Timing Mode and 1x Interpolation Clock High Time 19 5 0 21 5 ns Clock Low Time tio 5 0 22 0 ns Data Setup Time 111 2 0 3 4 ns Data Hold Time 1 4 5 3 2 ns Control Setup Time 111 7 0 3 4 ns Control Hold Time 5 4 0 3 2 ns Pipeline Delay 16 Clock Cycles For 4 4 4 Pixel Input Format at 1x Oversampling Pipeline Delay 29 Clock Cycles For 4 4 4 or 4 2 2 Pixel Input Format at 2x Oversampling NOTES Guaranteed by characterization Output delay measured from 50 point of rising edge of CLOCK to the 5096 point of DAC output full scale transition Data Cb Cr 9 0 Cr 9 0 9 0 Control HSYNC SYNC VSYNC TSYNC DV Specifications subject to change without notice REV A ADV7195 CLOCK ty tio PIXEL I
21. 10 1 EIA 770 3 must be connected from this pin to ground and is used to control the amplitudes of the DAC outputs For input ranges 0 1023 output standards RS 170 RS 343A the Rsgr value must be 2820 39 VREF IO Optional External Voltage Reference Input for DACs or Voltage Reference Out put 1 235 V 40 RESET I This input resets the on chip timing generator and sets the ADV7195 into Default Register setting Reset is an active low signal 41 ALSB I Address Input This signal sets up the LSB of the MPU address When this pin is tied high the filter is activated which reduces noise on the 2 Interface When this pin is tied low the input bandwidth on the interface is increased 42 51 Cb Cr9 0 I 10 Bit Progressive scan HDTV input port for color data In 4 2 2 mode the multiplexed CrCb data must be input on these pins Input port for B data when RGB is input REV 9 ADV7195 FUNCTIONAL DESCRIPTION Digital Inputs digital inputs of the ADV7195 are TTL compatible 30 bit YCrCb or RGB pixel data in 4 4 4 format or 20 bit YCrCb pixel data in 4 2 2 format is latched into the device on the rising edge of each clock cycle at 27 MHz in Progressive Scan Mode or 74 25 MHz or 74 1785 MHz in HDTV mode It is also possible to input 3 x bit RGB data 4 4 4 format to the ADV7195 It is recommended to input data in 4 2 2 mode to make use of the chroma SSAFs on the ADV7195 As can be seen in Figures 6 and 7 t
22. 5 1 15 20 25 30 Figure 9 Interpolation Filter CrCb Channels Cr 4 2 2 Input Data REV A 0 5 10 15 20 25 30 Figure 10 Interpolation Filter CrCb Channels Cr 4 4 4 Input Data MPU PORT DESCRIPTION The ADV7195 support a 2 wire serial PC compatible micro processor bus driving multiple peripherals Two inputs Serial Data SDA and Serial Clock SCL carry information between any device connected to the bus Each slave device is recognized by a unique address The ADV7195 has four possible slave addresses for both read and write operations These are unique addresses for each device and are illustrated in Figure 11 The LSB sets either a read or write operation Logic Level 1 corre sponds to a read operation while Logic Level 0 corresponds to a write operation 1 is set by setting the ALSB pin of the ADV7195 to Logic Level 0 or Logic Level 1 When ALSB is set to 0 there is greater input bandwidth on the lines which allows high speed data transfers on this bus When ALSB is set to 1 there is reduced input bandwidth on the lines which means that pulses of less than 50 ns will not pass into the internal controller This mode is recommended for noisy systems en as 36x 0C ADDRESS CONTROL SETUP BY ALSB READ WRITE CONTROL 0 WRITE 1 READ Figure 11 Slave Address control the various devices on the bus the following
23. A 2 54 2 83 3 11 mA DAC B DAC C Output Current Range 3 92 4 25 4 56 mA DACA 2 39 2 66 2 93 mA DAC B DAC C DAC to DAC Matching 1 4 Output Compliance Range Voc 0 1 4 V Output Impedance 100 Output Capacitance Cour 7 pF VOLTAGE REFERENCE External Reference Range VREF 1 112 1 235 1 359 V POWER REQUIREMENTS Ipp 25 35 mA 1x Interpolation 51 60 mA 2x Interpolation 40 mA HDTV Mode With 7425 MHz Da 11 15 mA 1x Interpolation 2x Interpolation and HDTV Mode Iprr 6 0 12 mA 1x Interpolation 2x Interpolation and HDTV Mode Power Supply Rejection Ratio 0 01 NOTES Guaranteed by characterization Ipp or the circuit current is the continuous current required to drive the digital core without I pry is the total current required to supply all DACs including the ggr circuitry DACs On Specifications subject to change without notice 3 15 V to 3 45 V Veer 1 235 V Rser 2470 0 Rioap 300 All specifications Tmn to Tmax 0 C to 70 C unless otherwise noted 3 V DYNAMIC SPECIFICATIONS Parameter Min Typ Max Unit Luma Bandwidth 13 5 MHz Chroma Bandwidth 6 75 MHz Signal to Noise Ratio 64 dB Luma Ramp Unweighted Chroma Luma Delay Inequality 0 ns Specifications subject to change without notice 4 REV ADV7195 Via 3 15 V to 3 45 V Veer 1 235 V 2410 Rioap 300 All specifications to Tmax 096 to 7
24. A CORRECTION REGISTER 9 GAMMA CORRECTION REGISTER 10 GAMMA CORRECTION REGISTER 11 GAMMA CORRECTION REGISTER 12 GAMMA CORRECTION REGISTER 13 ADAPTIVE FILTER GAIN 1 ADAPTIVE FILTER GAIN 2 ADAPTIVE FILTER GAIN 3 ADAPTIVE FILTER THRESHOLD A ADAPTIVE FILTER THRESHOLD B ADAPTIVE FILTER THRESHOLD C aaocoaaocoaaocoaaocoaaocoaaocoaaocoaaocooaacoaaoo 2o2o2o2o02o02o02020202020202020202020202020 MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 MODE REGISTER 5 COLOR Y COLOR CR COLOR CB ota OOOO Figure 15 Subaddress Registers in HDTV Mode REV A 13 ADV7195 PROGRESSIVE SCAN MODE MODE REGISTER 0 MRO MR07 MR00 Address SR4 SR0 00H Figure 16 shows the various operations under the control of Mode Register 0 MRO DESCRIPTION Output Standard Selection MR00 MR01 These bits are used to select the output levels for the ADV7195 If EIA 770 2 MR01 00 00 is selected the output levels will be 0 mV for blanking level 700 mV for peak white for the Y channel 350 mV for Pr Pb outputs and 300 mV for Sync Sync insertion on the Pr Pb channels is optional If EIA 770 1 MR01 00 017 is selected the output levels will be 0 mV for blanking level 714 mV for peak white for the Y channel 350 mV for Pr Pb outputs and 286 mV for Sync Optional sync insertion on the Pr Pb channels is not possible If Full I P Rang
25. AC Control MR35 18 PIN CONFIGURATION js beer 8 Interpolation MR36 18 PIN FUNCTION DESCRIPTIONS 9 Reserved MR37 os e ERA EVER 18 FUNCTIONAL DESCRIPTION 10 MODE REGISTER 4 RR RR and 18 Digital Inputs 224555060 yx ARE ER S eR 10 MR47 MR40 18 Control Signals 10 BIT DESCRIPTION 18 Analog Outputs 222222224 Rr CP CES 10 Timing Reset MR40 18 Undershoot Limiter 10 MODE REGISTER 5 54 peres rege en 18 PCIE Cos endete 10 MR5 MR57 MR50 3 664 660 ee 18 Internal Test Pattern Generator 10 MR5 DESCRIPTION 18 Y GECD Delay e x er oes 10 Reserved 18 Gamma Correction 10 RGB Mode MR51 18 54 MHz Operation 2 ed 10 Sync on PrPb MR52 18 PROGRAMMABLE SHARPNESS FILTER 10 Color Output Swap MR53 19 PROGRAMMABLE ADAPTIVE FILTER CONTROL 11 Gamma Curve MR54 19 INPUT OUTPUT CONFIGURATION 11 Gamma Correction MR55 19 MPU PORT DESCRIPTION cues
26. BADDRESS DATA ACK STOP Figure 12 Bus Data Transfer Figure 12 illustrates an example of data transfer for a read sequence and the Start and Stop conditions Figure 13 shows bus write and read sequences s rol A M P A S z NO ACKNOWLEDGE BY SLAVE A M NO ACKNOWLEDGE BY MASTER Figure 13 Write and Read Sequence 2 REV REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7195 except the Subaddress Registers which are write only registers The Subaddress Register determines which register the next read or write operation accesses All communications with the part through the bus begin with an access to the Subaddress Register read write operation is performed from to the target address which then increments to the next address until a Stop command on the bus is performed REGISTER PROGRAMMING The following section describes the functionality of each regis ter All registers can be read from as well as written to unless otherwise stated ZERO SHOULD BE WRITTEN HERE coOcoOcoOcoOoocoocoooooooooooooooooooooooooooooooo Q a a gt mae OOOOH 5 5 5 4 5 5 5 5
27. NCY RESPONSE IN SHARPNESS FILTER MODE WITH Kg 7 Figure 37 Frequency Response in Sharpness Filter Mode REV A ADV7195 ADAPTIVE FILTER GAIN 1 AFG1 AFG1 7 0 Address SR5 SRO0 22H This 8 bit wide register is used to program the gain applied to signals that lie above Adaptive Filter Threshold A but are smaller than Adaptive Filter Threshold B Gain and Gain B values vary from 8 to 7 Settings for AFG1 3 0 have no effect unless Adaptive Mode Control is set to Mode B MR56 1 Caras aran arai AFG17 AFG14 AFG13 AFG10 Figure 38 Adaptive Filter Gain 1 Register ADAPTIVE FILTER GAIN 2 AFG2 AFG2 7 0 Address SRS SR0 23H This 8 bit wide register is used to program the gain applied to signals that lie above Adaptive Filter Threshold B but are smaller than Adaptive Filter Threshold C Gain and Gain B values vary from 8 to 7 Settings for AFG2 3 0 have no effect unless Adaptive Mode Control is set to Mode B MR56 1 AFG27 AFG24 Figure 39 Adaptive Filter Gain 2 Register ADAPTIVE FILTER GAIN 3 AFG3 AFG3 7 0 Address SR5 SR0 24H This 8 bit wide register is used to program the gain applied to signals that lie above Adaptive Filter Threshold C Gain and Gain B values vary from 8 to 7 Settings for AFG3 3 0 have no effect unless Adaptive Mode Control is set to Mode B MR56 1 gain applied t
28. NPUT DATA gt tie CLOCK HIGH TIME pe tio CLOCK LOW TIME t41 DATA SETUP TIME 112 DATA HOLD TIME E 11 Figure 1 4 4 4 RGB Input Data Format Timing Diagram CLOCK PIXEL INPUT DATA tie tg CLOCK HIGH TIME tu CLOCK LOW TIME t41 DATA SETUP TIME t42 DATA HOLD TIME Figure 2 4 2 2 Input Data Format Timing Diagram CLOCK PIXEL INPUT DATA tie ty CLOCK HIGH TIME tio CLOCK LOW TIME t41 DATA SETUP TIME ty2 DATA HOLD TIME ty Figure 3 4 4 4 YCrCb Input Data Format Timing Diagram 6 REV A ADV7195 HSYNC VSYNC A PIXEL Y DATA 2 4544 Pe 2 a B gt Apn 16 CLK CYCLES 525P Byjy 122 CLK CYCLES 525P Apn 12 CLK CYCLES 625P 132 CLK CYCLES 625P Amin 44 CLK CYCLES 10801 Byin 236 CLK CYCLES 10801 Ay n 70 CLK CYCLES 720P Byjy 300 CLK CYCLES 720P Figure 4 Input Timing Diagram SDA SCL t ty ts Figure 5 MPU Port Timing Diagram REV A 7 ADV7195 ABSOLUTE MAXIMUM RATINGS Vaa to GND Voltage on Any Digital Pin Ambient Operating Temperature Storage Temperature Ts rrt 7V GND 0 5 V to Va 0 5 V 402 to 85 C NOTES IStresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the ope
29. ONSIDERATIONS Voltage Reference The ADV7195 contains an onboard voltage reference The pin is normally terminated to V44 through a 0 1 uF capacitor when the internal is used Alternatively the ADV7195 can be used with an external Vggg AD589 Resistor is connected between the pin and AGND and is used to control the full scale output current and there fore the DAC voltage output levels For full scale output Rsgr must have a value of 2470 Ri oap has a value of 300 Q When an input range of 0 1023 is selected the value of Rgpr must be 2820 Q The ADV7195 has three analog outputs corresponding to Y Pr Pb video signals The DACs must be used with external buffer circuits in order to provide sufficient current to drive an output device Suitable op amps are the AD8009 AD8002 AD8001 or AD8057 To calculate the output full scale current and voltage the following equations should be used Vour IourX Rroap Tour X k Rser k 5 66 for Ranges 64 940 64 960 O P Standards 14 770 1 3 k 6 46 Input Ranges 0 1023 Output Standard RS 170 343A PC BOARD LAYOUT CONSIDERATIONS ADV7195 is optimally designed for lowest noise perfor mance both radiated and conducted noise To complement the excellent noise performance of the ADV7195 it is imperative that great care be given to the PC board layout layout should be optimized for lowest noise on the ADV7195
30. R x4 adeo ibe tease eh eek 16 CGMS0 507 500 20 MRI 17 10 16 FILTER GAIN he bade 21 MRI BIT DESCRIPTION 16 RA we E 21 Pixel Data Enable 10 16 FG BIT DESCRIPTION 5 21 Input Format MR11 16 Filter Gain FG3 FG0 21 Test Pattern Enable MR12 16 Filter Gain B FG4 FG7 21 Test Pattern Hatch Frame MR13 16 GAMMA CORRECTION REGISTERS 0 13 VBI Open sess RW versare 16 GAMMA CORRECTION 0 13 21 Undershoot Limiter MRI5 MRI6 16 SHARPNESS FILTER CONTROL AND Sharpness Filter MR17 16 ADAPTIVE FILTER CONTROL 22 MODE REGISTER 2 354 e 17 SHARPNESS FILTER MODE 22 MR27 MR20 17 ADAPTIVE FILTER MODE 22 MR2 BIT DESCRIPTION 17 ADAPTIVE FILTER 1 23 Y Delay MR20 MR22 17 I 0 4 Peptide 23 Color Delay MR23 MR25 17 ADAPTIVE FILTER GAIN2 23 CGMS Enable MR26 17 APBG2 AFG2 7
31. R15 ZERO MUST BE WRITTEN TO THIS BIT VBI OPEN DCN iis DISABLE 1 ENABLE TEST PATTERN HATCH FRAME PIXEL DATA ENABLE mrio _____ 0 DISABLE 1 ENABLE INPUT FORMAT ENABLE Y CRCB FIELD FRAME Y CRCB Figure 51 Mode Register 1 REV A 27 ADV7195 MODE REGISTER 2 MR27 MR20 Address SRA SR0 02H Figure 53 shows the various operations under the control of Mode Register 2 MR2 BIT DESCRIPTION Y Delay MR20 MR22 With these bits it is possible to delay the Y signal with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles Figure 52 demonstrates this facility Color Delay MR23 MR25 With these bits it is possible to delay the color signals with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles Figure 52 demonstrates this facility Reserved MR26 MR27 0 must be written to these bits NO DELAY 1 Y DELAY a gt Y OUTPUT gt MAX DELAY NO DELAY PrPb OUTPUT PrPb DELAY MR27 MR26 A ZERO MUST BE WRITTEN TO THESE BITS 0 0 0 0 1 MR37 MR36 ZERO MUST BE WRITTEN TO THESE BITS DAC C CONTROL POWER DOWN NORMAL COLOR DELAY MR25 MR24 MR23 ____ DAC B CONTROL POWER DOWN NORMAL DAC A CONTROL POWER DOWN NORMAL MODE REGISTER 3 MR3 MR37 MR30
32. RGB complying to RS 170 RS 343A The ADV7195 requires a single 3 3 V power supply an optional external 1 235 V reference and a 27 MHz clock in Progressive Scan Mode or a 74 25 MHz or 74 1758 MHz clock in HDTV mode In Progressive Scan Mode a sharpness filter with programmable gain allows high frequency enhancement on the luminance signal Programmable Adaptive Filter Control which may be used allows removal of ringing on the incoming Y data The ADV7195 supports CGMS A data control generation The ADV7195 is packaged in a 52 lead MQFP package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2002 ADV7195 TABLE OF CONTENTS FEATURES AA Ad 1 MODE REGISTER 3 18 GENERAL DESCRIPTION 1 MR37 MR30 18 FUNCTIONAL BLOCK DIAGRAM 1 DESCRIPTION 18 3 3 V SPECIFICATIONS 4 HDTV Enable MR30 18 3 V DYNAMIC SPECIFICATIONS 4 Reserved MR31 MR32 18 3 3 V TIMING SPECIFICATIONS 5 Control MR33 acc aee e aC 18 ABSOLUTE MAXIMUM RATINGS 8 DAC B Control MR34 18 ORDERING GUIDE oa P EY aon 8 D
33. TL compatible inputs is a registered trademark of Philips Corporation REV Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL CGMS MACROVISION TEST PATTERN GENERATOR AND DELAY AND GAMMA CORRECTION CLKINO HORIZONTAL SYNC TIMING GENERATOR VERTICAL GENERATOR SYNC 9 REE BLANKING DOT RESET RESETO O comp The ADV7195 has three separate 10 bit wide input ports that accept data in 4 4 4 10 bit YCrCb or RGB or 4 2 2 10 bit YCrCb This data is accepted in progressive scan format at 27 MHz or HDTV format at 74 25 MHz or 74 1758 MHz For any other high definition standard but SMPTE293M ITU R BT 1358 SMPTE274M or SMPTE296M the Async Timing Mode can be used to input data to the ADV7195 For all standards exter nal horizontal vertical and blanking signals or EAV SAV codes control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals The ADV7195 outputs analog YPrPb progressive scan format complying to EIA 770 1 EIA 770 2 YPrPb HDTV complying to EIA 770 3
34. ables the facility of VBI data insertion during the Vertical Blanking Interval For this purpose Lines 13 to 42 of each frame can be used for VBI when SMPTE293M standard is used or Lines 6 to 43 when ITU R BT1358 standard is used Undershoot Limiter MR15 MR16 This control limits the Y signal to a programmable level in the active video region Available limit levels are 71 5 IRE 6 IRE 11 IRE Note that this facility is only available when Interpolation is enabled MR36 1 Sharpness Filter MR17 This control bit enables or disables the Sharpness Filter Mode This bit must be set to 1 for any values programmed into the Filter Gain Register to take effect It must also be set to 1 when Adaptive Filter mode is used Refer to Sharpness Filter Control and Adaptive Filter Control section 100 IRE 0 IRE 6 IRE 40 IRE Figure 19 Undershoot Limiter Programmed to 6 IRE TESTI ADE PIXEL DATA ENABLE jum _____ 0 DISABLE 1 ENABLE INPUT FORMAT Figure 20 Mode Register 1 16 REV ADV7195 MODE REGISTER 2 CGMS data bits are programmed into the CGMS Data MR1 MR27 MR20 Registers 0 2 For more information refer to CGMS Data Address SR4 SR0 02H Registers section Figure 22 shows the various operations under the control of CGMS CRC MR27 Mode Register 2 This bit enables the automatic Cyclic Redundancy Check when CGMS is
35. bs rr EP 11 Adaptive Mode Control MR56 19 REGISTER ACCESSES 13 Adaptive Filter Control MR57 19 REGISTER PROGRAMMING 13 COLOR Y dr 19 Subaddress Register SR7 SR0 13 serait enetan debes een 19 Register Select SR6 SR0 13 COLOR GR 19 PROGRESSIVE SCAN MODE 14 259 Gg es 19 MODE REGISTER 0 14 COLOR CB nexus iude nien enrages nares 19 MRO 07 00 14 CGCDB CCBZ CGBO sese x UR 19 MRO BIT DESCRIPTION 14 MODE REGISTER 6 20 Output Standard Selection MR00 MROI 14 MR6 MR67 MR60 nn 20 Input Control Signals 2 14 MR6 BIT DESCRIPTION eae eese 20 Input Standard MR04 14 67 60 52 beer e Rae es qe 20 Reserved MRO05 5 2 00 6 4 4 duos ve ERU CP RES 14 CGMS DATA REGISTERS 2 0 20 DV Polarity 205 14 CGMS2 527 520 20 Reserved EATER LES 14 CGMS1 CGMS17 CGMS10 20 MODE REGISTE
36. ch provides buffering and low pass filtering for HDTV applications O0hex Mode Register 0 00 The Eval ADV7195 ADV7196 ADV7197 EB Rev B and Rev Mode Register 1 02hex Mode Register 2 O0hex evaluation board uses the AD8057 as a buffer and a sixth order filter as a LPF 03hex Mode Register 3 38hex 4 Mode Register 4 O0hex 6 84H 10H 2 2pH 05hex Mode Register 5 00 Color Y AOhex 600R 5 6 8 22 18pF O7hex Color Cr 80hex 08 Color Cb 80hex 09 Mode Register 6 O0hex Figure 59 Example Cr Output Filter 10 Filter Gain O0hex PS Mode 2x Oversampling 22hex Adaptive Filter Gain 1 23hex Adaptive Filter Gain 2 9Ahex 24hex Adaptive Filter Gain 3 88hex 25hex Adaptive Filter Threshold A 28 hex d 498 26hex Adaptive Filter Threshold B 3Fhex pon 27 Adaptive Filter Threshold 64 hex MAGNITUDE dB 398 5 54n 298 Table XII Internal Colorbars Hatch Progressive Scan Mode 10 45n GROUP DELAY SEC n Address Register Setting 15 sen 00 Mode Register 0 00 20 97 6 Olhex Mode Register 1 05 PHASE DEG 2 02 Mode Register 2 O0hex 25 m 03hex Mode Register 3 38hex 04 Mode Register 4 O0hex 30 re 05 Mode Register 5 O0hex Color Y xxhex m 5 qf rs EU 2 3 40n O7hex Color Cr xxhex FREQUENCY MHz O8hex Color Cb xxhex 09hex Mode Register 6 3Ehex Figure 60 Frequency Response C1 Filter Circuit in above F
37. dard but SMPTE293M 5 274 SMPTE296M or ITU R BT1358 standard Reserved MR04 A 0 must be written to this bit Input Standard MR05 Select between 10801 or 720p input DV Polarity 06 This control bit allows to select the polarity of the DV input control signal to be either active high or active low Reserved MR07 0 must be written to this bit Table IX Truth Table SYNC TSYNC DV 1 20 0 Oorl 50 Point of Falling Edge of Tri Level Horizontal Sync Signal A 0 0 21 Oorl 25 Point of Rising Edge of Tri Level Horizontal Sync Signal B 0 21 0 or 1 0 50 Point of Falling Edge of Tri Level Horizontal Sync Signal C 1 Oorl 0 21 5096 Start of Active Video D 1 Oorl 1 gt 0 50 End of Active Video E PROGRAMMABLE INPUT TIMING ANALOG OUTPUT 525 12 13 42 43 Figure 49 DV Input Control Signal in Relation to Video Output Signal 26 REV A ADV7195 MODE REGISTER 1 MR17 MR10 Address SR4 SR0 01H Figure 51 shows the various operations under the control of Mode Register 1 MR1 BIT DESCRIPTION Pixel Data Enable MR10 When this bit is set to 0 the pixel data input to the ADV7195 is blanked such that a black screen is output from the DACs When this bit is set to 1 pixel data is accepted at the input pins and the ADV7195 outputs to the standard set in Output Standard Selection MR01 00 This b
38. e MR01 00 10 is selected the output levels will be 0 mV for blanking level 700 mV for peak white for the Y channel 350 mV for Pr Pb outputs and 300 mV for Sync Sync insertion on the Pr Pb channels is optional This mode is used for RS 170 RS 343A standard output compatibil ity Refer to Figures 61 to 64 for output level plots TO THIS BIT TO THIS BIT DV POLARITY ACTIVE HIGH ACTIVE LOW _______ MRO7 MROS INPUT ZERO MUST ZERO MUST STANDARD BE WRITTEN BE WRITTEN Input Control Signals MR02 MR03 These control bits are used to select whether data is input with external horizontal vertical and blanking sync signals or if the data is input with embedded EAV SAV codes An Asynchronous timing mode is also available using TSYNC SYNC and DV as input control signals These control signals have to be programmed by the user Figure 17 shows an example of how to program the ADV7195 to accept a different high definition standard but SMPTE293M 5 274 SMPTE296M or ITU R BT1358 standard Input Standard MR04 Select between 525p progressive scan input or 625p progressive scan input Reserved MR05 0 must be written to this bit DV Polarity 06 This control bit allows the user to select the polarity of the DV input control signal to be either active high or active low This is in order to facilitate interfacing from I to P Converters which use an active
39. e analog power plane Analog Signal Interconnect ADV7195 should be located as close as possible to the output connectors thus minimizing noise pickup and reflec tions due to impedance mismatch For optimum performance the analog outputs should be source and load terminated as shown in Figure 58 The termination resistors should be as close as possible to the ADV7195 to mini mize reflections Any unused inputs should be tied to ground Video Output Buffer and Optional Output Filter Output buffering is necessary in order to drive output devices such as progressive scan or HDTV monitors Analog Devices produces a range of suitable op amps for this application Suitable op amps would be the AD8009 AD8002 AD8001 or AD8057 More information on line driver buffering circuits is given in the relevant op amp data sheets 10pF 750 COAX PROGRESSIVE SCAN 10 amp F MONITOR 750 COAX al 10pF 750 COAX 5V O Y AD8057 6 Figure 58 Output Buffer and Optional Filter REV 31 ADV7195 An optional analog reconstruction LPF might be required as an REGISTER SETTINGS antialias filter if the ADV7195 is connected to a device that requires this filtering Table XI Register Settings on Power Up Eval ADV7195 ADV7196 ADV7197 EB evaluation board Address Register Setting uses the ML6426 Microlinear IC whi
40. ex must be written to this register before the PLL is reset reset MR36 to guarantee correct operation of the ADV7195 cures unes C mnes Ces ume ZERO MUST BE ONE MUST BE ONE MUST BE ZERO MUST BE WRITTEN TO WRITTEN TO WRITTEN TO WRITTEN TO THIS BIT THIS BIT THIS BIT THIS BIT ONE MUST BE WRITTEN TO THIS BIT ONE MUST BE WRITTEN TO THIS BIT ZERO MUST BE WRITTEN TO THIS BIT ZERO MUST BE WRITTEN TO THIS BIT Figure 29 Mode Register 6 700mV REF BIT1 BIT3 70 10 BIT2 4 CGMS DATA REGISTERS 2 0 CGMS2 CGMS27 CGMS20 Address SRA SR0 13H This 8 bit wide register contains the last four CGMS data bits C16 C19 of the CGMS data stream CGMS27 CGMS24 CGMS23 CGMS20 ZERO MUST BE WRITTEN TO 52 THESE BITS Figure 30 CGMS2 Data Register CGMS1 CGMS17 CGMS10 Address SR4 SR0 12H This 8 bit wide register contains C8 C15 of the CGMS data stream CGMS17 CGMS10 CGMS1 Figure 31 CGMS1 Data Register CGMS0 CGMS07 CGMS00 Address SR4 SR0 11H This 8 bit wide register contains the first eight CGMS data bits C0 C7 of the CGMS data stream CGMS07 CGMS00 CGMSO Figure 32 5 Data Register crc sEauENcE gt 5 BIT7 BIT9 BIT11 BIT13 BIT15 BIT17 BIT19 6 BIT8 BIT10 BIT12 BIT14 BIT16 BIT18 BIT20 5 8ps x0 15p
41. f required a second stage interpolation filter interpolates the data to 54 MHz before it is applied to the three output DACs The second stage interpolation filter is controlled by MR36 After applying a Reset it is recommended to toggle this bit Before toggling this bit 3Ehex must be written to Address 09hex PROGRAMMABLE SHARPNESS FILTER Sharpness Filter Mode is applicable to the Y data only in Progressive Scan Mode desired frequency response can be chosen by the user in programming the correct value via the The variation of frequency responses can be seen in the figures on the follow ing pages REV A ADV7195 PROGRAMMABLE ADAPTIVE FILTER CONTROL If the Adaptive Filter Mode is enabled Progressive Scan Mode only it is possible to compensate for large edge transitions on the incoming Y data Sensitivity and attenuation are all pro grammable over the For further information refer to Sharpness Filter Control and Adaptive Filter Control section INPUT OUTPUT CONFIGURATION Table I shows possible input output configurations when using the ADV7195 Table I Input Format Output YCrCb Progressive Scan 4 2 2 2x 4 4 4 1xor 2x YCrCb HDTV 4 2 2 1x 4 4 4 1x RGB Progressive Scan 4 4 4 2x RGB HDTV 4 4 4 1x Timing Mode All Inputs 1x 10 0 10 20 30 40 50 60 70 80 0 5 10 15 20 25 30
42. his filter has 0 dB passband response and prevents signal com ponents being loaded back into the frequency band In 4 4 4 input mode the video data is already interpolated by the external input device and the chroma SSAFs of the ADV7195 are bypassed ATTEN 10dB VAVG 1 MKR 0dB RL 10 0dBm 10dB 3 18MHz START 100kHz STOP RBW 10kHz VBW 300Hz 20 00MHz SWP 17 0SEC Figure 6 ADV7195 SSAF Response to a 2 5 MHz Chroma Sweep Using 4 2 2 Input Mode ATTEN 10dB 4 MKR RL 10 0dBm 10dB 3 12MHz JONOT 3 00dB HW START 100kHz 5 RBW 10kHz VBW 300Hz SWP 20 00MHz 17 05 Figure 7 Conventional Filter Response to a 2 5 MHz Chroma Sweep Using 4 4 4 Input Mode 10 Control Signals The ADV7195 accepts sync control signals accompanied by valid 4 2 2 or 4 4 4 data These external horizontal vertical and blanking pulses or EAV SAV codes control the insertion of appropriate sync information into the output signals Analog Outputs analog Y signal is output on the 11 bit Sync DAC A the color component analog signals on the 11 bit DAC B and DAC C conforming to EIA 770 1 or EIA 770 2 standards in PS mode or EIA 770 3 in HDTV mode has a value of 2470 Q 770 1 EIA 770 2 EIA 770 3 has a value of 300 Q For RGB outputs conforming to RS 170 RS 343A output stan dards must have a value of 2820 Q
43. i Table XIII Internal Colorbars Field HDTV Mode Address Register Setting O0hex Mode Register 0 Olhex Mode Register 1 0Dhex 02 Mode Register 2 O0hex 03hex Mode Register 3 39hex O4hex Mode Register 4 O0hex 05 Mode Register 5 O0hex Color Y xxhex O7hex Color Cr xxhex 8 Color Cb xxhex 32 REV A INPUT CODE EIA 770 2 STANDARD FOR Y 940 700mV ACTIVE VIDEO 64 300 EIA 770 2 STANDARD FOR Pr Pb OUTPUT VOLTAGE 960 350mV ACTIVE VIDEO 512 300mV 64 350mV Figure 61 EIA 770 2 Standard Output Signals 525p EIA 770 1 STANDARD FOR Y INPUT CODE OUTPUT VOLTAGE 782mvV 940 714 ACTIVE VIDEO 64 OmV 286mV EIA 770 1 STANDARD Pr Br OUTPUT VOLTAGE 960 350mV ACTIVE VIDEO 512 0 300 64 350 Figure 62 EIA 770 1 Standard Output Signals 525 REV A OUTPUT VOLTAGE ADV7195 EIA 770 3 STANDARD FOR Y INPUT CODE OUTPUT VOLTAGE 940 700mV ACTIVE VIDEO 300mV 64 0 300mV EIA 770 3 STANDARD FOR Pr Pb OUTPUT VOLTAGE 960 350mV 300mV ACTIVE VIDEO 512 300 64 350mV Figure 63 EIA 770 3 Standard Output Signals 1080i 720p Y OUTPUT LEVELS FOR FULL I P SELECTION INPUT CODE OUTPUT VOLTAGE 1023 700mV ACTIVE VIDEO 64 300 PrPb OUTPUT LEVELS FOR FULL I P SELECTION OUTPUT VOLTAGE 1023 700mV ACTIVE VIDEO 64 300 Figure 64 Outp
44. ion code RGB Mode MR51 When RGB mode is enabled MR51 1 the ADV7195 accepts unsigned binary RGB data at its input port This control is also available in Async Timing Mode Sync on PrPb 52 By default the color component output signals Pr Pb do not contain any horizontal sync pulses They can be inserted when MR52 1 This facility is only available when Output Stan dard Selection has been set to EIA 770 2 MR01 00 00 or Full Input Range MR01 00 10 This control is not available in RGB mode ZERO MUST BE WRITTEN TO THIS BIT ENABLE Lo ENABLE ZERO MUST BE WRITTEN TO THIS BIT Figure 23 Mode Register 3 MR47 MR41 ZERO MUST BE WRITTEN TO THESE BITS TIMING RESET Figure 24 Mode Register 4 18 REV ADV7195 ADAPTIVE MODE CONTROL MODE A MODE B Figure 25 Mode Register 5 Color Output Swap MR53 By default DAC B is configured as the Pr output and DAC C as the Pb output In setting this bit to 1 the DAC out puts can be swapped around so that DAC B outputs Pb and DAC C outputs Pr Table III demonstrates this in more detail This control is also available in RGB mode Table III Relationship Between Color Input Pixel Port MR53 and DAC B DAC C Outputs In 4 4 4 Input Mode Color Data Analog Output Input on Pins MR53 Signal Cr9 0 0 DACB Cb Cr9 0 0 DACC Cr9
45. is used Gamma correction uses the function Signaloyr Signal where y gamma power factor Gamma correction is performed on the luma data only The user has the choice of two different curves Curve A or Curve B At any one time only one of these curves can be used REV A The response of the curve is programmed at seven predefined locations In changing the values at these locations the gamma curve can be modified Between these points linear interpola tion is used to generate intermediate values Considering the curve to have a total length of 256 points the seven locations are at 32 64 96 128 160 192 224 Locations 0 16 240 and 255 are fixed and cannot be changed For the length of 16 to 240 the gamma correction curve has to be calculated as below y x where y gamma corrected output x linear input signal gamma power factor To program the gamma correction registers the seven values for y have to be calculated using the following formula Yn 19 240 16 240 16 16 where Value for x along x axis at points n 32 64 96 128 160 192 or 224 Yn Value for y along the y axis which has to be written into the gamma correction register Example 16 224 x 2 24 16 76 Ye 48 224 x 224 16 120 96 80 224 x 224 16 150 112 224 gt x 224 16 174 Rounded to the nearest integer The above will
46. it also must be set to 1 to enable output of the test pattern signals Input Format MR11 It is possible to input data in 4 2 2 format or in 4 4 4 HDTV format Test Pattern Enable MR12 Enables or disables the internal test pattern generator TO THIS BIT 1080 720 DV POLARITY ACTIVE HIGH ACTIVE LOW are I MRO7 INPUT ___ INPUT CONTROL SIGNALS ZERO MUST STANDARD ZERO MUST BE WRITTEN WRITTEN 02 TO THIS BIT Test Pattern Hatch Frame MR13 If this bit is set to 0 a crosshatch test pattern is output from the ADV7195 crosshatch test pattern can be used to test monitor convergence If this bit is set to 1 7 a uniform colored frame field test pattern is output from the ADV7195 color of the lines or the frame field is white by default but can be programmed to be any color using the Color Y Color Cr Color Cb registers VBI Open MR14 This bit enables or disables the facility of VBI data insertion during the Vertical Blanking Interval For this purpose Lines 7 20 in 10801 and Lines 6 25 in 720p can be used for VBI data insertion Reserved MR15 MR17 A 0 must be written to these bits 0 0 HSYNC VSYNC DV 0 1 EAV SAV 1 0 TSYNC SYNC DV 1 1 RESERVED OUTPUT STANDARD SELECTION MRO1 00 0 0 EIA770 3 0 1 RESERVED 1 0 FULL I P RANGE 1 1 RESERVED Figure 50 Mode Register 0 MR17 M
47. it wide register is used to program the threshold value for large edges and has priority over Adaptive Threshold A and B The recommended programmable threshold range is from 16 235 although any value in the range of 0 255 can be used AFTC7 AFTCO ADAPTIVE FILTER THRESHOLD C Figure 43 Adaptive Filter Threshold C 23 ADV7195 SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application sharpness filter can be used to enhance or attenuate the Y video output signal The following register settings were used to achieve the results shown in Figure 44a and Figure 44b Input data was generated by an external signal source Table V Address Register Setting O0hex Mode Register 0 40hex Olhex Mode Register 1 81hex 02hex Mode Register 2 O0hex Mode Register 3 78hex 04hex Mode Register 4 O0hex 5 Mode Register 5 O0hex 9 Mode Register 6 3Ehex 10 Filter Gain OOhex 10 Filter Gain 08 b 10 Filter Gain O4hex 10 Filter Gain 40hex d 10 Filter Gain 80hex e 10 Filter Gain 22hex f E TRIG D 500mV 4 005 4 5 CH1 ALL FIELDS REF4 500 4 00ys lj v 9 99976ms a effect of the sharpness filter can also be seen when using the internally generated crosshatch pattern Table VI Address Register Setting
48. low blanking signal output Reserved MR07 0 must be written to this bit INPUT CONTROL SIGNALS HSYNC VSYNC DV EAV SAV TSYNC SYNC DV RESERVED OUTPUT STANDARD SELECTION MRO 2 0 770 2 0 1 EIA 770 1 1 0 i FULL I P RANGE 1 RESERVED Figure 16 Mode Register 0 14 REV ADV7195 Table II must be followed when programming the control sig nals in Async Timing Mode Table II Truth Table SYNC TSYNC DV 1 20 0 Oorl 50 Point of Falling Edge of Tri Level Horizontal Sync Signal A 0 0 21 1 25 Point of Rising Edge of Tri Level Horizontal Sync Signal B 0 21 0 or 1 0 50 Point of Falling Edge of Tri Level Horizontal Sync Signal C 1 Oorl 0 gt 1 50 Start of Active Video D 1 1 1 gt 0 50 End of Active Video Nw Ww Y LAAL PROGRAMMABLE INPUT TIMING VS SY SET 06 1 ALAA HORIZONTAL SYN ACTIVE VIDE oo ANALOG OUTPUT A B D E Figure 17 Async Timing Mode Programming Input Control Signals for SMPTE295M Compatibility 525 1 12 13 42 43 VIDEO OUTPUT _______ Ww eo p Figure 18 DV Input Control Signal in Relation to Video Output Signal REV A 15 ADV7195 MODE REGISTER 1 MR1 MR17 MR10 Address 5 4 5 0 01H Figure 20 shows the variou
49. lso access any unique subaddress register on a one by one basis without having to update all the registers Stop and Start conditions can be detected at any stage during the data transfer If these conditions are asserted out of sequence with normal read and write operations they cause an immediate jump to the idle condition During a given SCL high period the user should issue only one Start condition one Stop condition or a single Stop condition followed by a single Start condition If an invalid subaddress is issued by the user the ADV7195 will not issue an acknowledge and will return to the idle condition If SEQUENCE S stavEAppR a sus a a9 SEQUENCE 5 SLAVE ADDR 5 508 ADDR 5 5 SLAVE avor 5 para S STARTBIT A S ACKNOWLEDGE SLAVE P STOPBIT ACKNOWLEDGE BY MASTER in autoincrement mode the user exceeds the highest subaddress the following action will be taken 1 In Read Mode the highest subaddress register contents will continue to be output until the master device issues a no acknowledge This indicates the end of a read A no acknowledge condition is where the SDA line is not pulled low on the ninth pulse 2 In Write Mode the data for the invalid byte will not be loaded into any subaddress register a no acknowledge will be issued by the ADV7195 and the part will return to the idle condition START ADDR R W SU
50. o signals that lie below Adaptive Threshold A is programmed in the Filter Gain register At any one time only one of the following registers is active AFGI AFG2 AFG3 The gain values can be preprogrammed and become active whenever the threshold conditions for the accord ing register are met program the Adaptive Filter Gain registers the same register settings are used as for the Filter Gain register REV A es es AFG33 AFG30 AFG37 AFG34 Figure 40 Adaptive Filter Gain 3 Register ADAPTIVE FILTER THRESHOLD A AFTA AFTA7 0 Address SR5 SR0 25H This 8 bit wide register is used to program the threshold value for small edges The recommended programmable threshold range is from 16 235 although any value in the range of 0 255 can be used AFTA7 AFTAO ADAPTIVE FILTER THRESHOLD A Figure 41 Adaptive Filter Threshold A Register ADAPTIVE FILTER THRESHOLD B AFTB AFTB7 0 Address SR5 SR0 26H This 8 bit wide register is used to program the threshold value for medium edges and has priority over Adaptive Threshold A recommended programmable threshold range is from 16 235 although any value in the range of 0 255 can be used AFTB7 AFTBO ADAPTIVE FILTER THRESHOLD B Figure 42 Adaptive Filter Threshold B Register ADAPTIVE FILTER THRESHOLD C AFTC AFTC7 0 Address SRS SR0 27H This 8 b
51. r Y Register COLOR CR CCR CCR7 CCR0 Address SR4 SR0 07H CCR7 CCRO COLOR CR VALUE Figure 27 Color Cr Register COLOR CB CCB CCB7 CCB0 Address SR4 SRO0 08H CCB7 COLOR CB VALUE Figure 28 Color Cb Register These three 8 bit wide registers are used to program the output color of the internal test pattern generator be it the lines of the crosshatch pattern or the uniform field test pattern and are available in PS mode and HDTV mode standard used for the values for Y and the color difference signals to obtain white black and the saturated primary and complementary colors conforms to the ITU R BT 601 4 standard 19 ADV7195 Table IV shows sample color values to be programmed into the color registers when Output Standard Selection 15 set to EIA 770 2 MR01 00 00 Table IV Sample Color Values for EIA 770 2 Output Standard Selection Sample Color Y Color Cr Color Cb Color Value Value Value White 235 EB 128 80 128 80 Black 16 10 128 80 128 80 Red 81 51 240 F0 90 5A Green 145 91 34 22 54 36 Blue 41 29 110 6E 240 F0 Yellow 210 D2 146 92 16 10 Cyan 170 AA 16 10 166 A6 Magenta 106 6A 222 DB 202 CA MODE REGISTER 6 MR6 MR67 MR60 ADDRESS SR4 SR0 09H Figure 29 shows the various operations under the control of Mode Register 6 MR6 BIT DESCRIPTION MR67 MR60 value 3EH
52. rational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Analog Output Short Circuit to any Power Supply Common can be of an Infrared Reflow Soldering 20 sec 225 C i Vapor Phase Soldering 1 minute 220 C lour to GND Mo scie an E dote pute VOU Eod e br dee 0 V to Vaa ORDERING GUIDE Model Temperature Range Package Description Package Option ADV7195KS 0 C to 70 C Plastic Quad Flatpack 5 52 CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the ADV7195 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Ls ESD SENSITIVE DEVICE PIN CONFIGURATION 5 5 5 2222222222270 cooooooooooddlr 52 51 50 49 48 47 46 45 44 43 42 41 40 PIN 1 VREF IDENTIFIER Rset COMP DAC B Vaa ADV7195 DAC A Y OUTPUT TOP VIEW AGND Not to Scale DACC SDA SCL HSYNC SYNC VSYNC TSYNC DV 16 17 18 19 20 21 22 23 T24 25 26
53. registers the Adaptive Filter Gain 1 2 3 registers and the Filter Gain register are used in Adaptive Filter mode To activate the Adaptive Filter control Sharpness Filter must be enabled 17 1 and Adaptive Filter Control must be enabled MR57 1 The derivative of the incoming signal is compared to the three programmable threshold values Adaptive Filter Threshold A B C edges can then be attenuated with the settings in Adaptive Filter Gain 1 2 3 registers and Filter Gain register According to the settings of the Adaptive Mode control MR56 two Adaptive Filter Modes are available 1 Mode A is used when Adaptive Filter Mode 56 is set to 0 In this case Filter B LPF will be used in the adap tive filter block Also only the programmed values for Gain B in the Filter Gain Adaptive Filter Gain 1 2 3 are applied when needed The Gain A values are fixed and can not be changed 2 Mode B is used when Adaptive Filter Mode MR56 is set to 1 7 In this mode a cascade of Filter A and Filter B is used Both settings for Gain A and Gain B in the Filter Gain Adaptive Filter Gain 1 2 3 become active when needed 22 INPUT SIGNAL STEP SHARPNESS AND ADAPTIVE FILTER CONTROL MODE M 2 E 5 lt N NS 1 UN MAGNITUDE LL ANN 6 8 FREQUENCY MHz MAGNITUDE RESPONSE Linear Scale FREQUENCY MHz FREQUE
54. ressive Scan Mode PS Mode Reserved MR31 MR32 0 must be written to these bits DAC A Control MR33 Setting this bit to 1 enables DAC A otherwise this DAC is powered down DAC B Control MR34 Setting this bit to 1 enables DAC B otherwise this DAC is powered down DAC C Control MR35 Setting this bit to 1 enables DAC C otherwise this DAC is powered down Interpolation MR36 This bit enables the second stage interpolation filters When this bit is enabled MR36 1 data is sent at 54 MHz to the DAC output stage After Reset it is recommended to toggle this bit Before toggling this bit 3Ehex must be written to address 09hex to guarantee correct operation Reserved MR37 A 0 must be written to this bit MR37 ZERO MUST BE WRITTEN TO THIS BIT INTERPOLATION CONTROL DISABLE DOWN ENABLE NORMAL NORMAL NORMAL MODE REGISTER 4 MR4 MR47 MR40 Address 584 860 04H Figure 24 shows the various operations under the control of Mode Register 4 MR4 BIT DESCRIPTION Timing Reset MR40 Toggling MR40 from low to high and low again resets the inter nal horizontal and vertical timing counters MODE REGISTER 5 MRS 57 50 Address SR4 SR0 05H Figure 25 shows the various operations under the control of Mode Register 5 MRS BIT DESCRIPTION Reserved 50 This bit is reserved for the revis
55. s eT 21 25 0 22 5 22T T 1 fH x 33 963ns fH HORIZONTAL SCAN FREQUENCY T 30 5 Figure 33 CGMS Waveform 20 REV ADV7195 FILTER GAIN FG FG7 FG0 Address SR4 SR0 10H Figure 34 shows the various operations under the control of the Filter Gain register FG7 FG4 FILTER GAIN lt 0 400 gt 010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Figure 34 Filter Gain Register FG BIT DESCRIPTION Filter Gain FG3 FG0 These bits are used to program the gain A value which varies from response 8 to response 7 and are applied to Filter A Filter Gain FG4 FG7 These bits are used to program the gain B value which varies from response 8 to response 7 and are applied to Filter B Refer to Sharpness Filter Control and Adaptive Filter Control section for more detail GAMMA CORRECTION REGISTERS 0 13 GAMMA CORRECTION 0 13 Address SR5 SR0 14 21 The Gamma Correction Registers are 14 8 bit wide registers They are used to program the gamma correction Curves and B Generally gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output as perceived on the CRT It can also be applied wherever nonlinear processing
56. s operations under the control of Mode Register 1 MR1 BIT DESCRIPTION Pixel Data Enable MR10 When this bit is set to 0 the pixel data input to the ADV7195 is blanked such that a black screen is output from the DACs When this bit is set to 1 pixel data is accepted at the input pins and the ADV7195 outputs the standard set in Output Standard Selection MR01 00 This bit also must be set to 41 to enable output of the test pattern signals Input Format MR11 It is possible to input data in 4 2 2 format or at 4 4 4 format at 27 MHz Test Pattern Enable MR12 Enables or disables the internal test pattern generator Test Pattern Hatch Frame MR13 If this bit is set to 0 a crosshatch test pattern is output from the ADV7195 for example in SMPTE293M 11 horizontal and 11 vertical white lines four pixels wide are displayed against a black background The crosshatch test pattern can be used to test monitor convergence If this bit is set to 1 a uniform colored frame field test pattern is output from the ADV7195 color of the lines or the frame field is by default white but can be programmed to be any color using the Color Y Color Cr Color Cb registers la MR17 Gece ERES VBI OPEN UNDERSHOOT LIMITER Cer Camis Cmi Cots Cum D wr DISABLE 1 ENABLE TEST PATTERN HATCH FRAME VBI Open MR14 This bit enables dis
57. ut Levels for Full I P Selection 33 ADV7195 SMPTE293M ANALOG WAVEFORM OyDATUM EAV CODE INPUT PIXELS 4 CLOCK 9 SAMPLE NUMBER 719 723 736 FVH FVH AND PARITY BITS SAV z LINE 43 525 200H SAV LINE 1 42 EAV z LINE 43 525 274H EAV z LINE 1 42 2D8 ANCILLARY DATA OPTIONAL _____ V V H H DIGITAL HORIZONTAL BLANKING DIGITAL ACTIVE LINE SAV CODE 854 Figure 65 EAV SAV Input Data Timing Diagram SMPTE293M SMPTE274M ANALOG WAVEFORM INPUT PIXELS 4 CLOCK 0 NUMBER 2112 2116 2156 2199 FVH AND PARITY BITS SAV EAV LINE 1 562 F 0 SAV EAV LINE 563 1125 F 1 SAV EAV LINE 1 20 561 583 1124 1125 V 1 LINE 21 560 584 1123 V 0 OHDATUM ANCILLARY DATA OPTIONAL OR BLANKING CODE CODE F vie ve Y H DIGITAL ACTIVE LINE SAV 44 188 192 2111 Figure 66 EAV SAV Input Data Timing Diagram SMPTE274M 34 REV A ADV7195 VERTICAL BLANK gt re 522 523 524 525 1 2 s 6 7 8 9 12 40 11 42 42 43 44 ACTIVE VIDEO ACTIVE VIDEO gt Figure 67 SMPTE293M 525p VERTICAL BLANK 10 12 13 ACTIVE VIDEO T VIDEO 622 623 625 1 44 45 Figure 68 ITU R BT1358 625p DISPLAY VERTICAL BLANKING INTERVAL 4
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ANALOG DEVICES ADV7195 handbook(1)(1)