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ANALOG DEVICES ADV7188 handbook(1)

1. User Sub Map Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0x40 Interrupt Configuration 1 INTRQ_OP_SEL 1 0 Interrupt Drive Level 0 0 Open drain Select 0 1 Drive low when active 1 0 Drive high when active 1 1 Reserved MPU_STIM_INTRQ 1 0 Manual Interrupt 0 Manual interrupt mode disabled Set Mode 1 Manual interrupt mode enabled Reserved x Not used MV_INTRQ_SEL 1 0 Macrovision 0 0 Reserved Interrupt Select ola Pseudo sync only 1 0 Color stripe only 1 1 Pseudo sync or color stripe INTRQ_DUR_SEL 1 0 Interrupt duration 0 0 3 XTAL periods Select oft 15 XTAL periods 1 0 63 XTAL periods 1 1 Active until cleared 0x42 Interrupt Status 1 SD_LOCK_Q 0 No change These bits can be cleared or Read Only 1 SD input has caused the decoder to masked in Registers 0x43 and go from an unlocked state to a 0x44 respectively locked state SD_UNLOCK_Q 0 No change 1 SD input has caused the decoder to go from a locked state to an unlocked state Reserved x Reserved x Reserved x SD FR CHNG Q 0 No Change 1 Denotes a change in the free run status MV PS CS Q 0 No Change 1 Pseudo sync color striping detected See Reg 0x40 MV INTRO SEL 1 0 for selection Reserved x 0x43 Interrupt Clear 1 SD_LOCK_CLR 0 Do not clear Write Only 1 Clears SD_LOCK_Q bit SD_UNLOCK_CLR 0 Do not clear 1 Clears SD_UNLOCK_Q b
2. Address Reset Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value Hex 0 00 Input Control RW VID_SEL 3 VID_SEL 2 VID_SEL 1 VID_SEL O INSEL 3 INSEL 2 INSEL 1 INSEL O 00000000 00 1 01 Video Selection RW ENHSPLL BETACAM ENVSPROC 11001000 C8 3 03 Output Control RW VBI EN TOD OF SEL3 OF SEL2 OF SEL 1 OF SELO SD DUP AV 00001100 0C Extended Output 4 04 Control RW BT656 4 TIM_OE BL_C_VBI EN_SFL_PIN RANGE 01xx0101 45 7 07 Autodetect Enable RW AD_SEC525_EN AD_SECAM_EN AD_N443_EN AD_P60_EN AD PALN EN AD PALM EN AD_NTSC_EN AD_PAL_EN 01111111 7F 8 08 Contrast RW CON 7 CON 6 CON 5 CON 4 CON 3 CON 2 CON 1 CON O 10000000 80 10 OA Brightness RW BRI 7 BRI 6 BRI 5 BRI 4 BRI 3 BRI 2 BRI 1 BRI O 00000000 00 11 OB Hue RW HUE 7 HUE 6 HUE 5 HUE 4 HUE 3 HUE 2 HUE 1 HUE O 00000000 00 DEF VAL AUTO 12 OC Default Value Y RW DEF Y 5 DEF Y 4 DEF Y 3 DEF Y 2 DEF Y 1 DEF Y O _EN DEF VAL EN 00110110 36 13 OD Default Value C RW DEF C7 DEF C6 DEF C 5 DEF C4 DEF C3 DEF C2 DEF C 1 DEF CO 01111100 7C 14 OE ADI Control SUB USR EN 00000000 00 15 OF Power Management RW RES PWRDN PDBP FB PWRDN 00000000 00 16 10 Status 1 R COL KILL AD RESULT 2 AD_RESULT 1 AD RESULT O FOLLOW PW FSC_LOCK LOST LOCK IN LOCK 18 12 Status2 R FSC NSTD LL NSTD MV AGC DET MV PS DET MVCS T3 MVCS DET 19 13 Status3 R PAL SW LOCK INTERLACE S
3. User Sub Map Bit Address Register Bit Description 7 6 5 4 3 2 Comments Notes 0x7D VDP_CGMS_WSS_DATA_0 CGMS_CRC 5 2 x x Decoded CRC sequence for CGMS Read Only Reserved 0 0 0 0 Ox7E VDP CGMS WSS DATA 1 CGMS WSS 13 8 x x x x Decoded CGMS WSS data Read Only CGMS_CRC 1 0 x x Decoded CRC sequence for CGMS Ox7F VDP CGMS WSS DATA 2 CGMS WSS 7 0 x X x x x Decoded CGMS WSS data Read Only 0x84 VDP GS VPS PDC UTC 0 GS VPS PDC UTC BYTE 0 7 0 XX X X x x Decoded Gemstar VPS PDC UTC Read Only data 0x85 VDP_GS_VPS_PDC_UTC_1 GS_VPS_PDC_UTC_BYTE_1 7 0 XX xX xX x x Decoded Gemstar VPS PDC UTC Read Only data 0x86 VDP_GS_VPS_PDC_UTC_2 GS_VPS_PDC_UTC_BYTE_2 7 0 X X X X X X Decoded Gemstar VPS PDC UTC Read Only data 0x87 VDP GS VPS PDC UTC 3 GS VPS PDC UTC BYTE 3 7 0 X X X X X X Decoded Gemstar VPS PDC UTC Read Only data 0x88 VDP VPS PDC UTC 4 VPS PDC UTC BYTE 4 7 0 X X X X X X Decoded VPS PDC UTC data Read Only 0x89 VDP VPS PDC UTC 5 VPS PDC UTC BYTE 5 7 0 X X X X X X Decoded VPS PDC UTC data Read Only Ox8A VDP_VPS_PDC_UTC_6 VPS_PDC_UTC_BYTE_6 7 0 X X X X X X Decoded VPS PDC UTC data Read Only Ox8B VDP VPS PDC UTC 7 VPS PDC UTC BYTE 7 7 0 X X X X X X Decoded VPS PDC UTC data Read Only 0x8C VDP VPS PDC UTC 8 VPS PDC UTC BYTE 8 7 0 X X X X X X Decoded VPS PDC UTC data Read Only 0x8D VDP_VPS_PDC_UTC_9 VPS_PDC_UTC_BYT
4. Byte DI9 DI8 D 7 DI6 D 5 D 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 EP EP 0 0 CCAP word1 7 4 0 0 User data words 7 EP EP 0 0 CCAP word1 3 0 0 0 User data words 8 EP EP 0 0 CCAP word2 7 4 0 0 User data words 9 EP EP 0 0 CCAP word2 3 0 0 0 User data words 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 89 PAL CCAP Data Full Byte Mode Byte DI9 DI8 D 7 DI6 D 5 D 4 DI3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data Count 6 CCAP word1 7 0 0 0 User data words 7 CCAP word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 200h 9 1 0 0 0 0 0 0 0 0 0 UDW padding 200h 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum NTSC CCAP Data Only closed caption data can be embedded in the output data Half byte output mode is selected by setting CDECAD 0 the full byte mode is enabled by CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address Ox4C 0 section The data packet formats are shown in Table 86 and Table 87
5. Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes NVBIELCM 1 0 NTSC VBI everlffield line 0 0 VBI ends 1 line earlier line 282 Controls position of first active comb control 011 ITU R BT 470 compliant Line 283 filtered line after VBI on even field in NTSC 110 VBI ends 1 line later line 284 1 1 VBI ends 2 lines later line 285 PVBIOLCM 1 0 NTSC VBI odd field line 0 0 VBI ends 1 line earlier line 20 Controls position of first active comb control 011 ITU R BT 470 compliant Line 21 filtered line after VBI on odd field in NTSC 110 VBI ends 1 line later line 22 1 1 VBI ends 2 lines later line 23 OxEC V Blank Control 2 PVBIECCM 1 0 PAL VBI even field color 0 0 Color output beginning line 335 Controls the position of first line that control 0 1 ITU R BT 470 compliant color outputs color after VBI on even field in output beginning Line 336 PAL 1 0 Color output beginning line 337 1 1 Color output beginning line 338 PVBIOCCM 1 0 PAL VBI odd field color ojo Color output beginning line 22 Controls the position of first line that control ol1 ITU R BT 470 compliant color outputs color after VBI on odd field in output beginning Line 23 PAL 1 0 Color output beginning line 24 1 1 Color output beginning line 25 NVBIECCM 1 0 NTSC VBI even field color ojo Color output beginning line 282 Controls the position of first line that control 1 IT
6. RGB IP SEL Address 0xF1 0 For SCART input R G and B signals can be input on either AIN4 AIN5 and AIN6 or on AIN7 AIN8 and AIN9 0 default B is input on AIN4 R is input on AIN 5 and G is input on AIN6 1 B is input on AIN7 R is input on AIN 8 and G is input on AINS MANUAL INPUT MUXING By accessing a set of manual override muxing registers the analog input muxes of the ADV7188 can be controlled directly This is referred to as manual input muxing Manual input muxing overrides other input muxing control bits for example INSEL and SDM_SEL means if the settings of INSEL and the manual input muxing registers ADC0 ADC1 ADC2 ADC3_SW contradict each other the ADC0 ADC1 ADC2 ADC3_SW settings apply and INSEL SDM_SEL is ignored Manual input muxing controls only the analog input muxes INSEL 3 0 still has to be set so the follow on blocks process the video data in the correct format This means INSEL must still be used to tell the ADV7188 whether the input signal is of component YC or CVBS format Restrictions in the channel routing are imposed by the analog signal routing inside the IC every input pin cannot be routed to each ADC Refer to Figure 6 for an overview on the routing capabilities inside the chip The four mux sections can be controlled by the reserved control signal buses ADCO_SW 3 0 ADCI SW 3 0 ADC2_SW 3 0 and ADC3 SW 3 0 Table 11 explains the control words us
7. Bit Address Register Bit Description 7 6 5 4 3 2 1 Comments Notes 0x80 204mV 0x0B Hue Register HUE 7 0 This register contains the value for 0 0 0 0 0 0 0 Hue range 90 to 90 the color hue adjustment 0x0C Default Value Y DEF_VAL_EN Default value enable Free run mode dependent on DEF_VAL_AUTO_EN Force free run mode on and output blue screen DEF_VAL_AUTO_EN Default value 0 Disable free run mode When lock is lost free run mode can 1 Enable automatic free run mode be enabled to output stable timing blue screen clock and a set color DEF Y 5 0 Default value Y This register 0 0 1 1 0 1 Y 7 0 DEF Y 5 0 0 0 Default Y value output in free run holds the Y default value mode 0x0D Default Value C DEF_C 7 0 Default value C The Cr and Cb OEE P TEE TEE JE Cr 7 0 DEF_C 7 4 0 0 0 0 Default Cb Cr value output in free run default values are defined in this register Cb 7 0 DEF_C 3 0 0 0 0 0 mode Default values give blue screen output OxOE ADI Control Reserved 0 0 00 Set as default SUB USR EN Enables the user to access the 0 Access User Map See Figure 46 User Sub Map 1 Access User Sub Map Reserved 0 0 Set as default OxOF Power Management Reserved Set to default FB PWRDN 0 FB input operational 1 FB input in power save mode PDBP Power down bit priority selects 0 Chip power down controlled by between PWRDN bit or pin pin 1 Bit has priority pin disregarded Reserved 0 0 Set to default
8. DR STR C 1 0 Description 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x Enable Subcarrier Frequency Lock Pin EN SFL PIN Address 0x04 1 The EN SFL PIN bit enables the output of subcarrier lock information also known as GenLock from the ADV7188 core to an encoder in a decoder encoder back to back arrangement 0 default The subcarrier frequency lock output is disabled 1 The subcarrier frequency lock information is presented on the SFL pin Polarity LLC Pin PCLK Address 0x37 0 The polarity of the clock that leaves the ADV7188 via the LLC1 and LLC2 pins can be inverted using the PCLK bit Changing the polarity of the LLC clock output may be necessary to meet the setup and hold time expectations of follow on chips This bit also inverts the polarity of the LLC2 clock 0 The LLC output polarity is inverted 1 default The LLC output polarity is normal as per the timing diagrams Rev 0 Page 20 of 112 GLOBAL STATUS REGISTERS Three registers provide summary information about the video decoder The STATUS_1 STATUS_2 and STATUS_3 registers contain status bits that report operational information to the user STATUS_1 7 0 Address 0x10 7 0 This read only register provides information about the internal status of the ADV7188 See CIL 2 0 Count Into Lock Address 0x51 2 0 and COL 2 0 Count Out of Lock Address 0x51
9. 100 CVBS SOURCE 50 CONTRAST SANDCASTLE CVBS SOURCE 05478 010 100 Figure 10 Fast Blank Signal Representation with Contrast Reduction Enabled Contrast Reduction Enable CNTR ENABLE Address OxEF 3 This register enables the contrast reduction feature and changes the meaning of the signal applied to the FB pin 0 default The contrast reduction feature is disabled and the fast blank signal is interpreted as a bi level signal 1 The contrast reduction feature is enabled and the fast blank signal is interpreted as a tri level signal Fast Blank and Contrast Reduction Programmable Thresholds FB LEVEL 1 0 Address OxF1 5 4 Controls the reference level for the fast blank comparator CNTR LEVEL 1 0 Address OxF1 7 6 Controls the reference level for the contrast reduction comparator The internal fast blank and contrast reduction signals are resolved from the tri level FB signal using two comparators as shown in Figure 11 To facilitate compliance with different input level standards the reference level to these comparators is programmable under the control of FB LEVEL 1 0 and CNTR LEVEL 1 0 The resulting thresholds are given in Table 15 FB PIN FAST BLANK FAST BLANK COMPARATOR PROGRAMMABLE THRESHOLDS CONTRAST REDUCTION COMPARATOR 0 1713 31 84 0 17 13A31 H1NO 318VN3 HLIND 05478 011 Figure 11 Fast Blank and Contrast Reducti
10. DNR is based on the assumption that high frequency signals with low amplitude are probably noise and therefore that their removal improves picture quality There are two DNR blocks in the ADV7188 the DNRI block before the luma peaking filter and the DNR2 block after the luma peaking filter as shown in Figure 23 LUMA LUMA PEAKING LUMA SIGNAL FILTER OUTPUT 05478 023 Figure 23 DNR and Peaking Block Diagram DNR EN Digital Noise Reduction Enable Address Ox4D 5 0 Bypasses DNR disables it 1 default Enables DNR on the luma data DNR TH 7 0 DNR Noise Threshold Address 0x50 7 0 The DNRI block is positioned before the luma peaking block The DNR TH 7 0 value is an unsigned 8 bit number that determines the maximum edge that is still interpreted as noise and therefore blanked from the luma data Programming a large value into DNR_TH 7 0 causes the DNR block to interpret even large transients as noise and removes them As a result the effect on the video data is more visible Programming a small value causes only small transients to be seen as noise and to be removed The recommended DNR TH 7 0 setting for A V inputs is 0x04 and the recommended DNR TH 7 0 setting for tuner inputs is Ox0A The default value for DNR_TH 7 0 is 0x08 indicating the threshold for maximum luma edges to be interpreted as noise PEAKING GAIN 7 0 Luma Peaking Gain Address OxFB 7 0 This filter can be manually enabled The us
11. Ox9C Letterbox 2 Read Only LB LCM 7 0 Letterbox data register Reports the number of black lines detected in the bottom half of active video if subtitles are detected Ox9D Letterbox 3 Read Only LB LCB 7 0 Letterbox data register Reports the number of black lines detected at the bottom of active video This feature examines the active video atthe start and at the end of each field It enables format detection even if the video is not accompanied by a CGMS or WSS sequence OxC3 ADC SWITCH 1 ADCO SW 3 0 Manual muxing control for ADCO No connection AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 No connection No connection AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 2 2 2 212 2 2 S o ololololo oio 2 2 l2 2lolololo 5 2 2 liolo oio 2 2l lolol2 olo 25 olioli 3 2 olo EAE EXE dE AL HE de aM ES Bc e No connection SETADC SW MAN EN 1 OxC3 ADC SWITCH 1 ADC1 SW 3 0 Manual muxing control for No connection SETADC SW MAN EN 1 Rev 0 Page 85 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes cont ADC1 0 0 0 1 No connection 0 0 1
12. 1 Forces a colored screen output determined by user programmable Y Cr and Cb values This overrides picture data even if the decoder is locked DEF VAL AUTO EN Default Value Automatic Enable Address 0x0C 1 This bit enables the automatic use of the default values for Y Cr and Cb when the ADV7188 cannot lock to the video signal 0 Disables free run mode If the decoder is unlocked it outputs noise 1 default Enables free run mode A colored screen set by the user programmable Y Cr and Cb values is displayed when the decoder loses lock CLAMP OPERATION The input video is ac coupled into the ADV7188 through a 0 1 uF capacitor It is recommended that the range of the input video signal is 0 5 V to 1 6 V typically 1 V p p If the signal exceeds this range it cannot be processed correctly in the decoder Since the input signal is ac coupled into the decoder its dc value needs to be restored This process is referred to as clamping the video This section explains the general process of clamping on the ADV7188 and shows the different ways in which a user can configure its behavior The ADV7188 uses a combination of current sources and a digital processing block for clamping as shown in Figure 14 The analog processing channel shown is replicated three times inside the IC While only one single channel and only one ADC is needed for a CVBS signal two independent channels are needed for YC S VHS type signals an
13. No connection No connection No connection 2 2 2 2 2 2 2 2 o 2 o o u 2 o 25 o No connection OxF4 Drive Strength DR STR S 1 0 Selects the drive strength for the sync output signals Reserved Medium low drive strength 2x Medium high drive strength 3x lolo o E o High drive strength 4x DR_STR_C 1 0 Selects the drive strength for the clock output signal Reserved Medium low drive strength 2x Medium high drive strength 3x lolo 2 oi o High drive strength 4x DR STR 1 0 Selects the drive strength for the data output signals Can be increased or decreased for EMC or crosstalk reasons Reserved Medium low drive strength 2x Medium high drive strength 3x slolo o 2 o High drive strength 4x Reserved No delay OxF8 IF Comp Control IFFILTSEL 2 0 IF filter selection for PAL and NTSC Bypass mode OdB 2MHz 5MHz 3 dB 2 dB 6 dB 3 5 dB 10 dB 5 dB NTSC Filters ojojo oO 2 2 o oS m a Reserved 3 MHz 6 MHz 2 dB 2 dB 5 dB 3 dB 7 dB 5 dB PAL Filters Reserved OxF9 VS Mode Control EXTEND_VS_MAX_FREQ Limit maximum VSYNC frequency to 66 25 Hz 475 lines frame Limit maximum VSYNC frequency to 70 09 Hz 449 lines frame EXTEND_VS_MIN_FREQ Limit minimum VSYN
14. VITC DATA 3 3 VITC DATA 3 2 VITC DATA 3 1 VITC DATA 3 0 VDP VITC 149 95 DATA 3 R VITC DATA 47 VITC DATA 4 6 VITC DATA 45 VITC DATA 44 VITC DATA 4 3 VITC DATA 4 2 VITC DATA 4 1 VITC DATA 4 0 VDP VITC 150 96 DATA 4 R VITC DATA 57 VITC DATA 5 6 VITC DATA 5 5 VITC DATA 54 VITC DATA 5 3 VITC DATA 5 2 VITC DATA 5 1 VITC DATA 5 0 a VDP VITC 151 97 DATA 5 R VITC DATA 67 VITC DATA 6 6 VITC DATA 6 5 VITC DATA 64 VITC DATA 63 VITC DATA 6 2 VITC DATA 6 1 VITC DATA 6 0 VDP VITC 152 98 DATA 6 R VITC DATA 77 VITC DATA 7 6 VITC DATA 7 5 VITC DATA 74 VITC DATA 7 3 VITC DATA 7 2 VITC DATA 7 1 VITC DATA 7 0 VDP VITC 153 99 DATA 7 R VITC DATA 87 VITC DATA 8 amp 6 VITC DATA 85 VITC DATA 84 VITC DATA 83 VITC DATA 82 VITC DATA 8 1 VITC DATA 8 0 VDP VITC 154 9A DATA 8 R VITC DATA 97 VITC DATA 9 6 VITC DATA 9 5 VITC DATA 94 VITC DATA 93 VITC DATA 9 2 VITC DATA 9 1 VITC DATA 9 0 VDP VITC 155 9B CALC CRC R VITC CRC7 VITC_CRC 6 VITC_CRC 5 VITC_CRC 4 VITC_CRC 3 VITC_CRC 2 VITC_CRC 1 VITC_CRC O x GS VPS PDC VDP_ I2C_GS_VPS_ I2C GS VPS UTC CB WSS CGMS 156 9C OUTPUT SEL RW PDC UTC 1 PDC UTCO CHANGE CB CHANGE 00110000 30 Rev 0 Page 92 of 112 ADV7188 Table 103 provides a detailed description of the registers located in the User Sub Map Table 103 User Sub Map Detailed Description
15. VITC has a sync sequence of 10 in between each data byte The VDP strips these syncs from the data stream to give out only the data bytes The VITC results are available in VDP VITC DATA 0 to VDP VITC DATA 8 registers Register 0x92 to Register Ox9A User Sub Map The VITC has a CRC byte at the end the in between syncs are also used in this CRC calculation Since the in between syncs are not given out the CRC is also calculated internally The calculated CRC is also available for the user in VITC CALC CRC register Resister 0x9B User Sub Map Once the VDP completes decoding the VITC line the VITC DATA and VITC CALC CRC registers are updated and VITC_AVL bit is set VITC CLEAR VITC Clear Address 0x78 6 User Sub Map Write Only Self Clearing 1 Re initializes the VITC readback registers VITC_AVL VITC Available Address 0x78 6 User Sub Map 0 VITC data was not detected 1 VITC data was detected VITC Readback Registers See Figure 40 for the C to VITC bit mapping Rev 0 Page 60 of 112 ADV7188 Table 77 VITC Readback Registers Signal Name Register Location Address User Sub Map VITC DATA 0 7 0 VDP VITC DATA 0 7 0 VITC bits 9 2 146 0x92 VITC DATA 1 7 0 VDP VITC DATA 1 7 0 VITC bits 19 12 147 0x93 VITC DATA 2 7 0 VDP VITC DATA 2 7 0 VITC bits 29 22 148 0x94 VITC DATA 3 7 0 VDP VITC DATA 3 7 0 VITC bits 39 32 149 0x95 VITC DATA 4 7 0 VDP VITC DATA 4 7 0 VITC bits 49 42 150
16. Disables the CTI alpha blender 1 default Enables the CTI alpha blender CTI AB 1 0 Chroma Transient Improvement Alpha Blend Address 0x4D 3 2 This controls the behavior of alpha blend circuitry that mixes the sharpened chroma signal with the original one It thereby controls the visual impact of CTI on the output data For CTI AB 1 0 to become active the CTI block must be enabled via the CTI EN bit and the alpha blender must be switched on via CTI AB EN Rev 0 Page 35 of 112 ADV7188 Sharp blending maximizes the effect of CTI on the picture but may also increase the visual impact of small amplitude high frequency chroma noise Table 49 CTI_AB Function CTI_AB 1 0 Description 00 Sharpest mixing between sharpened and original chroma signal 01 Sharp mixing 10 Smooth mixing 11 default Smoothest alpha blend function CTI C TH 7 0 CTI Chroma Threshold Address 0x4E 7 0 The CTI C TH 7 0 value is an unsigned 8 bit number speci fying how big the amplitude step in a chroma transition has to be in order to be steepened by the CTI block Programming a small value into this register causes even smaller edges to be steepened by the CTI block Making CTI C TH 7 0 a large value causes the block to improve large transitions only The default value for CTI C TH 7 0 is 0x08 indicating the threshold for the chroma edges prior to CTI DIGITAL NOISE REDUCTION DNR AND LUMA PEAKING FILTER
17. PWRDN Power down places the decoder in a 0 System functional full power down mode 1 Powered down See PDBP OxOF Bit 2 Reserved 0 Set to default RES Chip Reset loads all C bits with default 0 Normal operation values 1 Start reset sequence Executing reset takes approx 2 ms Self clearing 0x10 Status Register 1 IN_LOCK n lock right now 1 Provides information about the Read Only LOST_LOCK Lost lock since last read 1 internal status of the decoder FSC_LOCK x Fsc lock right now 1 FOLLOW_PW x Peak white AGC mode active 1 AD_RESULT 2 0 Autodetection result 0 0 0 NTSM MJ Detected standard reports the standard of the Input video 0lol1 NTSC 443 0 1 0 PAL M 01 1 PAL 60 1 0 0 PAL BGHID 1 0 1 SECAM 1 1 0 PAL combination N TREPI SECAM 525 COL_KILL x Color kill is active 1 Color kill 0x11 IDENT Read Only IDENT 7 0 Provides identification on the X X X X X X X revision of the part 0x12 Status Register 2 MVCS DET MV color striping detected 1 Detected Read Only MVCS T3 x MV color striping type 0 Type 2 1 Type 3 MV_PS DET x MV pseudo Sync detected 1 Detected MV_AGC DET x MV AGC pulses detected 1 Detected LL_NSTD x Nonstandard line length 1 Detected FSC_NSTD x Fsc frequency nonstandard 1 Detected Reserved x x 0x13 Status Register 3 INST_HLOCK 1 horizontal lock achieved Unfiltered Read only GEMD x 1 Gemstar data detected When GEMD bit goes HIGH it will remain HIGH until end of active video lines in that fiel
18. SVHS 13 0 1 1 1 1 SVHS 14 1 0 0 0 0 SVHS 15 1 0 0 0 1 SVHS 16 1 0 0 1 O SVHS 17 1 0 01 1 SVHS 18 CCIR601 1 0 1 0 0 Reserved Do not use Reserved Do not use 1 1 1 1 11 Reserved Do not use Reserved 0 0 Set to default WYSFMOVR Enables the use of automatic 0 Auto selection of best filter WYSEN filter 1 Manual select filter using WYSFM A 0 0x19 Comb Filter Control PSFSEL 1 0 Controls the signal bandwidth 0 O Narrow that is fed to the comb filters PAL 0111 Medium 1 0 Wide 1 1 Widest NSFSEL 1 0 Controls the signal bandwidth ojo Narrow that is fed to the comb filters NTSC 0 1 Medium 1 0 Medium 1 1 Wide Reserved FU ayaa Set as default 0x1D ADI Control 2 Reserved 0 0 0 x x x Set to default EN28XTAL 0 Use 27 MHz crystal 1 Use 28 63636 MHz crystal TRI LLC 0 LLC pin active 1 LLC pin three stated 0x27 Pixel Delay Control LTA 1 0 Luma timing adjust allows the user 0 0 No Delay CVBS mode LTA 1 0 00b to specify a timing difference between 1 0 Luma 1 clk 37 nS delayed S Video mode LTA 1 0 01b chroma and luma samples YPrPb mode LTA 1 0 2 O1b 1 0 Luma 2 clk 74 nS early 1 1 Luma 1 clk 37 nS early Reserved 0 Set to Zero CTA 2 0 Chroma timing adjust allows a ojojo Not valid setting CVBS mode CTA 2 0 011b specified timing difference between the 0lol1 Chroma 4 2 pixels early S Video mode CTA 2 0 101b luma and chroma samples YPrPb mode CTA 2 0 110b 0 1
19. Set SDM SEL to 03 for YC CVBS auto AIN11 AIN12 Enable anti alias filter on ADCO and ADC1 Set maximum v lock range Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Rev 0 Page 103 of 112 ADV7188 MODE 5 SCART FAST BLANK CVBS amp RGB CVBS input on AIN11 B INPUT on AIN7 R INPUT on AIN8 and G INPUT on AINO 10 bit ITU R BT 656 output on P19 P10 Table 108 Mode 5 SCART CVBS S Video Autodetect on AIN 11 AIN12 Register Address Register Value Notes 0x00 OxOF CVBS on AIN11 0x03 0x00 10 bit mode 0x17 0x41 Set CSFM to SH1 0x19 OxFA Split filter control 0x1D 0x47 Enable 28 63636 MHz crystal mode 0x3A 0x10 Power up all four ADCs Ox3B 0x71 Recommended setting Ox3D OxA2 MWE enable manual window color kill threshold to 2 Ox3E Ox6A BLM optimization Ox3F OxAO BGB optimization Ox4D OxEE Disable CTI 0x67 0x01 Format 422 0x73 OxDO Manual gain channels A B C 0x74 0x04 Manual gain channels A B C 0x75 0x01 Manual gain channels A B C 0x76 0x00 Manual gain channels A B C 0x77 0x04 Manual offsets A to 64d B and C to 5
20. The clamp timing register determines the time constant of the digital fine clamp circuitry It is important to realize that the digital fine clamp reacts very quickly since it is supposed to immediately correct any residual dc level error for the active line The time constant of the digital fine clamp must be much quicker than the one from the analog blocks By default the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal Table 35 DCT Function DCT 1 0 Description 00 Slow TC 1 sec 01 Medium TC 0 5 sec 10 default Fast TC 0 1 sec 11 Determined by the ADV7188 depending on the I P video parameters DCFE Digital Clamp Freeze Enable Address 0x15 4 This register bit allows the user to freeze the digital clamp loop at any time It is intended for users who would like to do their own clamping Users should disable the current sources for analog clamping via the appropriate register bits wait until the digital clamp loop settles and then freeze it via the DCFE bit 0 default The digital clamp is operational 1 The digital clamp loop is frozen LUMA FILTER Data from the digital fine clamp block is processed by three sets of filters The data format at this point is CVBS for CVBS input or luma only for Y C and YPrPb input formats e Luma antialias filter YAA The ADV7188 receives video at a rate of 27 MHz For 4x oversampled vide
21. The user can adjust the saturation of the picture Table 30 SD_SAT_Cr Function Table 34 HUE Function SD SAT Cr 7 0 Description HUE 7 0 Description 0x00 default Phase of the chroma signal 0 Ox7F Phase of the chroma signal 90 0x80 Phase of the chroma signal 90 0x80 default 0x00 OxFF Gain on Cr channel 1 Gain on Cr channel 0 Gain on Cr channel 2 SD OFF Cb 7 0 SD Offset Cb Channel Address 0xE1 7 0 This register allows the user to select an offset for data on the Cb channel only and adjust the hue of the picture There is a functional overlap with the HUE 7 0 register Table 31 SD OFF Cb Function SD OFF Cb 7 0 Description 0x80 default 0x00 OxFF 0 offset applied to the Cb channel 568 mV offset applied to the Cb channel 568 mV offset applied to the Cb channel SD OFF Cr 7 0 SD Offset Cr Channel Address OxE2 7 0 This register allows the user to select an offset for data on the Cr channel only and adjust the hue of the picture There is a func tional overlap with the HUE 7 0 register Table 32 SD OFF Cr Function SD OFF Cr 7 0 Description 0x80 default 0x00 OxFF 0 offset applied to the Cr channel 568 mV offset applied to the Cr channel 568 mV offset applied to the Cr channel BRI 7 0 Brightness Adjust Address 0x0A 7 0 This register controls the brightness of the video signal It all
22. User Sub Map Read Only 0 CGMS WSS was not detected 1 CGMS WSS was detected CGMS WSS DATA 0 3 0 Address 0x7D 3 0 CGMS WSS DATA 1 7 0 Address Ox7E 7 0 CGMS WSS DATA 2 7 0 Address Ox7F 7 0 User Sub Map read only These bits hold the decoded CGMS or WSS data Refer to Figure 37 and Figure 38 for the C to WSS and CGMS bit mapping CCAP Two bytes of decoded closed caption data are available in the FC registers The field information of the decoded CCAP data can be obtained from the CC EVEN FIELD bit register 0x78 CC CLEAR Closed Caption Clear Address 0x78 0 User Sub Map Write Only Self Clearing 1 Re initializes the CCAP readback registers CC AVI Closed Caption Available Address 0x78 0 User Sub Map Read Only 0 Closed captioning was not detected 1 Closed captioning was detected CC EVEN FIELD Address 0x78 1 User Sub Map Read Only Identifies the field from which the CCAP data was decoded 0 Closed captioning detected on an ODD field 1 Closed captioning was detected on an EVEN field VDP CCAP DATA 0 Address 0x79 7 0 User Sub Map Read Only Decoded Byte 1 of CCAP data VDP CCAP DATA 1 Address 0x7A 7 0 User Sub Map Read Only Decoded Byte 2 of CCAP data VDP CGMS WSS VDP CGMS WSS DATA 2 DATA 1 5 0 1 7 RUN IN START ACTIVE SEQUENCE CODE VIDEO 38 4us 42 5us 05478 037 Figure 37 WSS Waveform 100 IRE REF VDP CGMS WSS DATA 2 70 IR
23. VDP LINE 020 RW P23 N21 3 N21 2 N21 1 N21 0 N284 3 N284 2 N284 1 P336 N284 0 00000000 00 VBI DATA VBI DATA P24 VBI DATA P24 VBI DATA P24 VBI DATA P337 VBI DATA P337 VBI DATA P337 VBl DATA 119 77 VDP LINE 021 RW P24 N223 N22 2 N22 1 N22 0 N285 3 N285 2 N285 1 P337 N285 0 00000000 00 VDP STATUS GS PDC VPS CGMS WSS 120 78 CLEAR w VITC_CLEAR UTC_CLEAR CLEAR CC_CLEAR 00000000 00 GS_PDC_VPS_ 120 78 VDP STATUS R TTXT_AVL VITC_AVL GS DATA TYPE UTC_AVL CGMS WSS AVL CC EVEN FIELD CC AVL VDP CCAP CCAP_ 121 79 DATA 0 R CCAP BYTE 17 CCAP BYTE 1 6 CCAP BYTE 1 5 CCAP BYTE 1 4 CCAP BYTE 1 3 CCAP BYTE 1 2 CCAP BYTE 1 1 BYTE 1 0 E VDP CCAP CCAP_ 122 7A DATA 1 R CCAP BYTE 27 CCAP BYTE 26 CCAP BYTE 2 5 CCAP BYTE 24 CCAP BYTE 23 CCAP BYTE 2 2 CCAP BYTE 2 1 BYTE 2 0 CGMS WSS CGMS_ 125 7D DATA_O R zero zero zero zero CGMS CRC 5 CGMS CRCA CGMS CRC 3 CRC2 CGMS WSS CGMS_ 126 7E DATA 1 R CGMS CRC 1 CGMS CRCO CGMS WSS 13 CGMS WSS 12 CGMS WSS 11 CGMS WSS 10 CGMS WSS 9 WSS 8 CGMS WSS CGMS 127 7F DATA 2 R CGMS WSS 7 CGMS WSS 6 CGMS WSS 5 CGMS_WSS 4 CGMS WSS 3 CGMS WSS 2 CGMS WSS 1 WSS 0 VDP GS VPS GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC 132 84 PDC UTC O R UTC BYTE 0 7 UTC BYTE 0 6 UTC BYTE 0 5 UTC BYTE 0 4 UTC BYTE 0 3 UTC BYTE 0 2 UTC BYTE 0 1 UTC BYTE 0 0 VDP GS VPS GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS
24. components wisely because the current loops are much longer current takes the path of least resistance An example of a current loop power plane to ADV7188 to digital output trace to digital data receiver to digital ground plane to analog ground plane PLL Place the PLL loop filter components as close as possible to the ELPF pin Do not place any digital or other high frequency traces near these components Use the values suggested in Figure 50with tolerances of 1096 or less DIGITAL OUTPUTS BOTH DATA AND CLOCKS Try to minimize the trace length that the digital outputs have to drive Longer traces have higher capacitance which requires more current which causes more internal digital noise Shorter traces reduce the possibility of reflections Adding a 30 Q to 50 Q series resistor can suppress reflections reduce EMI and reduce the current spikes inside the ADV7188 If series resistors are used place them as close as possible to the ADV7188 pins However try not to add vias or extra length to the output trace to make the resistors closer If possible limit the capacitance that each of the digital outputs drives to less than 15 pF This can easily be accomplished by keeping traces short and by connecting the outputs to only one device Loading the outputs with excessive capacitance increases the current transients inside the ADV7188 creating more digital noise on its power supplies Rev 0 Page 106 of 112 ADV7188 DIGI
25. the aspect ratio of the video can be derived from the digitally decoded bits WSS contains In the absence of a WSS sequence letterbox detection may be used to find wide screen signals The detection algorithm examines the active video content of lines at the start and end of a field If black lines are detected this may indicate that the currently shown picture is in wide screen format ADV7188 The active video content luminance magnitude over a line of video is summed together At the end of a line this accumulated value is compared with a threshold and a decision is made as to whether or not a particular line is black The threshold value needed may depend on the type of input signal some control is provided via LB_TH 4 0 Detection at the Start of a Field The ADV7188 expects a section of at least six consecutive black lines of video at the top of a field Once those lines are detected register LB LCT 7 0 reports back the number of black lines that were actually found By default the ADV7188 starts looking for those black lines in sync with the beginning of active video for example straight after the last VBI video line LB SL 3 0 allows the user to set the start of letterbox detection from the beginning of a frame on a line by line basis The detection window closes in the middle of the field Detection at the End of a Field The ADV7188 expects at least six continuous lines of black video at the bottom of a field be
26. 0 gt VDP VPS PDC VPS PDC UTC VPS PDC UTC VPS PDC UIC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC 140 8C UTC 8 R BYTE 87 BYTE 8 6 BYTE 8 5 BYTE 84 BYTE 8 3 BYTE 82 BYTE 8 1 UTC BYTE 8 0 VDP VPS PDC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC 141 8D UTC 9 R BYTE 97 BYTE 9 6 BYTE 9 5 BYTE 94 BYTE 9 3 BYTE 92 BYTE 9 1 UTC BYTE 9 0 VDP VPS PDC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC 142 8E UTC 10 R BYTE 107 BYTE 10 6 BYTE 10 5 BYTE 10 4 BYTE 10 3 BYTE 10 2 BYTE 10 1 UTC BYTE 10 0 VDP VPS PDC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC 143 BF UTC_11 R BYTE 117 BYTE 11 6 BYTE 11 5 BYTE 11 4 BYTE 11 3 BYTE 11 2 BYTE 11 1 UTC BYTE 11 0 VDP VPS PDC VPS PDC UTC VPS PDC UTC VPS PDC UIC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC 144 90 UTC_12 R BYTE 127 BYTE 12 6 BYTE 12 5 BYTE 124 BYTE 12 3 BYTE 12 2 BYTE 12 1 UTC BYTE 120 VDP VITC 146 92 DATA 0 R VITC DATA 1 7 VITC DATA 1 6 VITC DATA 1 5 VITC DATA 14 VITC DATA 1 3 VITC DATA 1 2 VITC DATA 1 1 VITC DATA 1 0 VDP VITC 147 93 DATA 1 R VITC DATA 27 VITC DATA 2 6 VITC DATA 2 5 VITC DATA 24 VITC DATA 2 3 VITC DATA 22 VITC DATA 2 1 VITC DATA 2 0 PES VDP VITC 148 94 DATA 2 R VITC DATA 37 VITC DATA 3 6 VITC DATA 3 5 VITC DATA 34
27. 0x4 320 321 3220e0e0 335 336 337 318 319 PVEND 4 0 0x4 Figure 32 PAL Default BT 656 The Polarity of H V and F is Embedded in the Data Rev 0 Page 46 of 112 05478 032 FIELD 1 1622 i 1623 624 625 ADV7188 l 6 7 8 9 10 110080 st a mua dune mE L output 7i f 2 VIDEO Li n sata ae 3E me et pa ae SUE ale ME 8 UE OI 2 HS OUTPUT vs amp d OUTPUT FIELD PVBEG 4 0 0x1 PVEND 4 0 0x4 OUTPUT amp FIELD 2 HS OUTPUT 1310 311 312 313 314 315 316 318 319 320 321 322 323 eee 337 Liz bets ig i l OUTPUT ve ri VIDEO it d PFTOG 4 0 0x6 uF MEME M NO OUTPUT PVBEG 4 0 0x1 FIELD OUTPUT PVEND 4 0 0x4 05478 033 PFTOG 4 0 0x6 Figure 33 PAL Typical VSYNC Field Positions Using Register Writes in Table 63 NOT VALID FOR USER PROGRAMMING NO PVBEGDELO PVBEGDELE 1 0 0 1 ADDITIONAL ADDITIONAL DELAY BY DELAY BY 1 LINE 1 LINE ADVANCE BY 0 5 LINE ADVANCE BY 0 5 LINE Figure 34 PAL VSYNC Begin 05478 034 PVENDDELO PAL VSYNC End Delay on Odd Field Address 0xE9 7 0 default No delay 1 Delays VSYNC going low on an odd field by a line relative to PVEND PVENDDELE PAL VSYNC End Delay on Even Field Address OxE9 6 0 default No delay 1 Delays VSYNC going low on an even field by a line relative to PVEND PVENDSIGN PAL VS
28. 0x96 VITC DATA 5 7 0 VDP VITC DATA 5 7 0 VITC bits 59 52 151 0x97 VITC DATA 6 7 0 VDP VITC DATA 6 7 0 VITC bits 69 62 152 0x98 VITC DATA 7 7 0 VDP VITC DATA 7 7 0 VITC bits 79 72 153 0x99 VITC DATA 8 7 0 VDP VITC DATA 8 7 0 VITC bits 89 82 154 Ox9A VITC_CALC_CRC 7 0 VDP_VITC_CALC_CRC 7 0 155 Ox9B The register is a readback register default value does not apply VPS PDC UTC GEMSTAR The readback registers for VPS PDC and UTC have been shared Gemstar is a high data rate standard and so is available only through the ancillary stream however for evaluation purposes any one line of Gemstar is available through C registers sharing the same register space as PDC UTC and VPS Thus only one standard out of VPS PDC UTC and Gemstar can be read through the I C at a time To identify the data that should be made available in the IC registers the user has to program I2C GS VPS PDC UTCT 1 0 register address 0x9C User Sub Map I2C GS VPS PDC UTC VDP 1 0 Address 0x9C 6 5 User Sub Map Specifies which standard result to be available for PC readback Table 78 I2C GS VPS PDC UTCT 1 0 Function I2C GS VPS PDC UTC Description 1 0 00 default Gemstar 1x 2x 01 VPS 10 PDC 11 UTC GS PDC VPS UTC CLEAR GS PDC VPS UTC Clear Address 0x78 4 User Sub Map Write Only Self Clearing 1 Re initializes the GS PDC VPS UTC data readback registers GS PDC VPS UTC AVL
29. 1 0 0 Kill at 8 5 TEA Kill at 16 1 1 0 Kill at 3296 1 1 1 Reserved Reserved 0 Set to default 0x41 Resample Control Reserved 0 0 0 0 0 1 Set to default SFL_INV Controls the behavior of the PAL 0 SFL compatible with switch bit ADV7190 ADV7191 ADV7194 encoders 1 SFL compatible with ADV717x ADV7173x encoders Reserved 0 Set to default 0x48 Gemstar Control 1 GDECEL 15 8 See the Comments column 0 0 0 0 0 0 0 0 GDECEL 15 0 16 individual LSB Line 10 MSB Line 25 0x49 Gemstar Control2 GDECEL 7 0 See above o o o o o o o o enable bits that select the linesof Default Do not check for Gemstar video even field Lines 10 25 that compatible data on any lines 10 25 the decoder checks for Gemstar in even fields compatible data Ox4A Gemstar Control 3 GDECOL 15 8 See the Comments column 0 0 0 0 0 0 0 0 GDECOL 15 0 16 individual LSB Line 10 MSB Line 25 enable bits that select the lines of Default Do not check for Gemstar video odd field Lines 10 25 that compatible data on any lines 10 25 Ox4B Gemstar Control 4 GDECOL 7 0 See above 0 0 0 0 0 0 0 0 ue decoder checks for Gemstar Sd Skis y compatible data Ox4C Gemstar Control 5 GDECAD Controls the manner in which 0 Split data into half byte To avoid 00 FF code decoded Gemstar data is inserted into the 1 Output in straight 8 bit format horizontal blanking period Reserved Xx x x x 0 0 0 Undefined Ox4D CTI DNR Control 1 CTI EN C
30. 1 RW DNR EN CTI AB 1 CTI AB O CTI AB EN CTI EN 11101111 EF 78 4E CTIDNR Ctrl 2 RW CTI C TH 7 CTI C TH 6 CIC TH5 CTI C THA CTI C TH3 CTI_C_TH 2 CTI C TH 1 CI C THO 00001000 08 80 50 CTIDNR Ctrl 4 RW DNR TH 7 DNR TH 6 DNR TH 5 DNR_TH 4 DNR_TH 3 DNR_TH 2 DNR_TH 1 DNR_TH O 00001000 08 81 51 Lock Count RW FSCLE SRLS COL2 COL 1 COLO CIL 2 CIL 1 CIL O 00100100 24 Free Run Line LLC PAD X LLC PAD LLC PAD 143 8F Length 1 Ww SEL MAN SEL 1 SEL O 00000000 00 153 99 CCAP 1 R CCAP1 7 CCAP1 6 CCAP1 5 CCAP1 4 CCAP1 3 CCAP1 2 CCAP1 1 CCAP1 0 154 9A CCAP2 R CCAP27 CCAP2 6 CCAP2 5 CCAP2 4 CCAP2 3 CCAP2 2 CCAP2 1 CCAP2 0 155 9B Letterbox 1 R LB LCT 7 LB LCT 6 LB LCT 5 LB LCTA LB LCT 3 LB LCT2 LB LCT 1 LB LCT O 156 9C Letterbox 2 R LB LCM 7 LB LCM 6 LB LCM 5 LB_LCM4 LB LCM 3 LB LCM 2 LB LCM 1 LB LCM O 157 9D Letterbox 3 R LB LCB7 LB LCB 6 LB LCB 5 LB LCB 4 LB LCB 3 LB LCB 2 LB LCB 1 LB LCB O 195 C3 ADC Switch 1 RW ADC1 SW 3 ADC1_SW 2 ADCI1 SW 1 ADC1_SW 0 ADCO SW 3 ADCO SW 2 ADCO SW 1 ADCO SW 0 ooooxxx 00 196 C4 ADC Switch 2 RW ADC SW MAN ADC2 SW 33 ADC2_SW 2 ADC2 SW 1 ADC2 SW 0 Oxoooxx 00 220 DC Letterbox Control 1 RW LB TH 4 LB TH 3 LB TH 2 LB TH 1 LB TH O 10101100 AC 221 DD Letterbox Control 2 RW LB SL 3 LB SL 2 LB SL 1 LB SLO LB EL 3 LB EL2 LB EL 1 LB ELO 01001100 4C 222 DE ST Noise Readback 1 R ST NOISE VLD ST NOISE 10 ST NOISE 9 ST NOISE8 223 DF STNoise Readback2 R ST
31. 10 0 The number applied offsets the edge 101 Chroma 2 chroma pixel late with respect to an internal counter that is reset to 0 immediately 110 Chroma 3 chroma pixel late after EAV code FE 00 00 XY see Figure 26 HSB 10 0 is set 111 Not used to 00000000010 which is 2 LLC1 clock cycles from count 0 The default value of HSB 10 0 is 0x002 indicating that the HS pulse starts two pixels after the falling edge of HS Table 61 HS Timing Parameters see Figure 26 Characteristic HS to Active Video Active Video Total LLC1 HS Begin Adjust HS End Adjust LLC1 Clock Cycles Samples Line Clock Cycles Standard HSB 10 0 default HSE 10 0 default Cin Figure 26 default Din E in NTSC 00000000010 00000000000 272 720Y 720C 1440 1716 NTSC Square 00000000010 00000000000 276 640Y 640C 1280 1560 Pixel PAL 00000000010 00000000000 284 720Y 720C 1440 1728 2 eae FS EAV gt H BLANK gt a SAV gt a ACTIVE VIDEO PA HS j HSE 10 0 HSB 10 0 4 LLC1 a c a D t S Figure 26 HS Timing HSE 10 0 HS End Address 0x34 2 0 Address 0x36 7 0 after EAV code FF 00 00 XY see Figure 26 HSE is set to 00000000000 which is 0 LLC1 clock cycles f t 0 The position of this edge is controlled by placing a binary APIS elocec yas Eon COURHUN number into HSE 10 0 The number applied offsets the edge The default value of HSE 10 0 is 000 indicating that t
32. 100 10001 SVHS 16 E 10010 SVHS 17 cio a CHEEEC OEC EC NEED 10011 default SVHS 18 CCIR 601 FREQUENCY MHz 10100 11111 Do not use Figure 17 Y S VHS 18 Extra Wideband Filter CCIR 601 Compliant The filter plots in Figure 16 show the S VHS 1 narrowest to S VHS 18 widest shaping filter settings Figure 18 shows the PAL notch filter responses The NTSC compatible notches are shown in Figure 19 Rev 0 Page 30 of 112 ADV7188 COMBINED Y ANTIALIAS PAL NOTCH FILTERS Y RESAMPLE CHROMA FILTER N Data from the digital fine clamp block is processed by three sets Y A dk of filters The data format at this point is CVBS for CVBS 10 We VAP d op inputs chroma only for Y C or Cr Cb interleaved for YPrPb 20 il T a input formats B S e Chroma Antialias Filter CAA The ADV7188 over a _40 samples the CVBS by a factor of 2 and the Chroma CrCb 2 by a factor of 4 A decimating filter CAA is used to preserve the active video band and to remove any out of band components The CAA filter has a fixed response 05478 018 e Chroma Shaping Filters CSH The shaping filter block CSH can be programmed to perform a variety of low pass responses It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression lil TII 8 10 12 FREQUENCY MHz Figure 18 Y PAL Notch Filter Responses COMBINED Y ANTIALIAS NTSC NOTGH FILTERS e Digi
33. 102 Mode 4 SCART S Video or CVBS autodetect 103 Mode 5 SCART Fast Blank CVBS amp RGB 104 Mode 6 SCART RGB Input Static Fast Blank CV BS and RG Baa r E E r Sizes assess vecadersp saute 105 PCB Layout Recommendations eee 106 Rev 0 Page 2 of 112 ADV7188 Analog Interface Inputs sseeeeeeeeteeenen 106 XTAL And Load Capacitor Values Selection 107 Power Supply Decoupling seen 106 Typical Circuit Connection essere 108 IN 106 Outline Dimensions eeeeeeeneerteenntetentnttetenntnnns 109 Digital Outputs Both Data and Clocks 106 Ordering Guide Ede ERE ebrei tete nete 109 Digital Inputs enint pie ie Rep exert 107 REVISION HISTORY 7 05 Revision 0 Initial Version Rev 0 Page3 of 112 ADV7188 INTRODUCTION The ADV7188 is a high quality single chip multiformat video decoder that automatically detects and converts PAL NTSC and SECAM standards in the form of composite S Video and component video into a digital ITU R BT 656 format The advanced and highly flexible digital output interface enables performance video decoding and conversion in line locked clock based systems This makes the device ideally suited for a broad range of applications with diverse analog video characteristics including tape based sources broadcast sou
34. 3 0 Analog Input Pins Video Format INSEL 3 0 Analog Input Pins Video Format 0000 default CVBS1 AIN1 SCART CVBS and R G B 1000 Y3 AIN3 YC B AIN4 or AIN7 C3 AIN6 R AIN5 or AIN8 1001 Y1 AIN1 YPrPb G AIN6 or AIN9 PB1 AINA 0001 CVBS2 AIN2 SCART CVBS and R G B PR1 AIN5 B AIN4 or AIN7 1010 Y2 AIN2 YPrPb R AIN5 or AIN8 PB2 AIN3 G AIN6 or AIN9 PR2 AIN6 0010 CVBS3 AIN3 SCART CVBS and R G B 1011 CVBS7 AIN7 SCART CVBS and R G B B AIN4 or AIN7 B AIN7 R AIN5 or AIN8 R AIN8 G AIN6 or AIN9 G AIN9 0011 CVBS4 AIN4 SCART CVBS and R G B 1100 CVBS8 AIN8 SCART CVBS and R G B B AIN7 B AIN7 R AIN8 R AIN8 G AIN9 G Ain9 0100 CVBS1 AIN1 SCART CVBS and R G B 1101 CVBS9 AIN9 SCART CVBS and R G B B AIN4 B AIN7 R AIN5 R AIN8 G AIN6 G Ain9 0101 CVBS1 AIN1 SCART CVBS and R G B 1110 CVBS10 AIN10 SCART CVBS and R G B B AIN4 B AIN4 or AIN7 R AIN5 R Ain5 or Ain8 G AIN6 G Ain6 or Ain9 0110 Y1 AIN1 YC 1111 CVBS11 AIN11 SCART CVBS and R G B C1 AIN4 B AIN4 or AIN7 0111 Y2 AIN2 YC R AIN5 or AIN8 C2 AIN5 G AIN6 or AIN9 1 Selectable via RGB IP SEL Rev 0 Page 13 of 112 ADV7188 Table 10 Input Channel Assignments Input Channel Pin ADI Recommended Input Muxing Control INSEL 3 0 AIN7 41 CVBS7 SCART1 B AIN1 42 CVBS1 YC1 Y YPrPb1 Y SCART2 CVBS AIN8 43 CVBS8 SCART1 R AIN2 44 CVBS2 YC
35. 3 line 3 tap luma Use low pass notch Fixed luma comb 2 line Top lines of memory Fixed luma comb 3 Line All lines of memory 2 2 2 2l o 2 o oNES o 2Jjope Fixed luma comb 2 line Bottom lines of memory CCMN 2 0 Chroma Comb Mode NTSC 3 line adaptive for CTAPSN 01 4 line adaptive for CTAPSN 10 5 line adaptive for CTAPSN 11 Disable chroma comb Fixed 2 line for CTAPSN 01 Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 Top lines of memory Fixed 3 line for CTAPSN 01 Fixed 4 line for CTAPSN 10 Fixed 5 line for CTAPSN 11 All lines of memory Fixed 2 line for CTAPSN 01 Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 Bottom lines of memory CTAPSN 1 0 Chroma Comb Taps NTSC Not used Adapts 3 lines 2 lines Adapts 5 lines 3 lines m olo oj o Adapts 5 lines 4 lines 0x39 PAL Comb Control YCMP 2 0 Luma Comb mode PAL Adaptive 5 line 3 tap luma comb Use low pass notch Fixed luma comb Top lines of memory Fixed luma comb 5 line All lines of memory 2 2 2 2lo o B ojoj oj o Fixed luma comb 3 line Bottom lines of memory CCMP 2 0 Chroma Comb mode PAL 3 line adaptive for CTAPSP 01 4 line adaptive for CTAPSP 10 5 line adaptive for CTAPSP 11 Disable chroma comb Fixed 2 line for CTAPSP 01 Fixed 3
36. Address 0x4C 0 section Rev 0 Page 64 of 112 ADV7188 Table 82 Gemstar 2x Data Half Byte Mode Byte DI9 DI8 D 7 DI6 D 5 D 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 1 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 1 0 0 0 Data count 6 EP EP 0 0 Gemstar word1 7 4 0 0 User data words 7 EP EP 0 0 Gemstar word1 3 0 0 0 User data words 8 EP EP 0 0 Gemstar word2 7 4 0 0 User data words 9 EP EP 0 0 Gemstar word2 3 0 0 0 User data words 10 EP EP 0 0 Gemstar word3 7 4 0 0 User data words 11 EP EP 0 0 Gemstar word3 3 0 0 0 User data words 12 EP EP 0 0 Gemstar word4 7 4 0 0 User data words 13 EP EP 0 0 Gemstar word4 3 0 0 0 User data words 14 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 83 Gemstar 2x Data Full Byte Mode Byte DI9 DI8 DI7 DI6 D 5 D 4 D 3 D 2 D 1 D o Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 1 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 Gemstar word1 7 0 0 0 User data words 7 Gems
37. BIT INTERFACE omms D m X Jo C semen D Y Y ED ED ee ee AV CODE SECTION 16 20 BIT INTERFACE a7 Ee 2s aa e362 AV CODE SECTION This is done so any data that may arrive during VBI is not decoded as color and output through Cr and Cb As a result it is possible to send VBI lines into the decoder then output them through an encoder again undistorted Without this blanking any wrongly decoded color is encoded by the video encoder therefore the VBI lines are distorted 0 Decodes and outputs color during VBI 1 default Blanks Cr and Cb values during VBI SD_DUP_AV 0 8 10 BIT INTERFACE dom RE AV CODE SECTION 05478 025 Figure 25 AV Code Duplication Control RANGE Range Selection Address 0x04 0 AV codes as per ITU R BT 656 formerly known as CCIR 656 consist of a fixed header made up of OxFF and 0x00 values These two values are reserved and therefore not to be used for active video Additionally the ITU specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and 16 to 240 for chroma The RANGE bit allows the user to limit the range of values output by the ADV7188 to the recommended value range In any case it ensures that the reserved values of 255d OxFF and 00d 0x00 are not presented on the output pins unless they are part of an AV code header Table 58 RANGE Function LTA 1 0 Luma Timing Adjust Address 0x27 1 0 This r
38. C shaping filter mode allows the selection 0 0 1 Auto selection 2 17 MHz on video standard and quality from a range of low pass chrominance filters o 1 g SH1 Selects a C filter for all video standards If either auto mode is selected the decoder olil1 SH2 and for good and bad video selects the optimum C filter depending on the CVBS video source quality good vs bad 1 00 SH3 Non auto settings force a C filter for all 1 0 1 SH4 standards and quality of CVBS video 1l1lo SH5 1 141 Wideband mode 0x18 Shaping Filter WYSFMIA 0 Wideband Y shaping filter 010 0 0 0 Reserved Do not use Control 2 mode allows the user to select which Y olololo l1 Reserved Do not use shaping filter is used for the Y component of Y C YPbPr B W input signals it is also used 0 0 0 11 0 SVHS1 when a good quality input CVBS signal is 0 0 0 11 1 SVHS2 detected For all other inputs the Y shaping olol1lololsvHs3 Rev 0 Page 80 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes filter chosen is controlled by YSFM 4 0 0 0 1 0 1 SVHS4 0 0 1 1 0 SVHS5 0 0 1 1 1 SVHS6 0 1 0 0 0 SVHS7 0 1 0 0 1 SVHS8 0 1 0 1 0 SVHS9 0 1 0 1 1 SVHS 10 0 1 1 0 0 SVHS 11 0 1 1 0 1 SVHS 12 0 1 1 1 0
39. CS CIR CHNG CLR SD UNLOCK CLR SD LOCK CLR x0000000 00 SD FR CHNG SD UNLOCK 68 44 InterruptMask1 RW MV PS CS MSKB MSKB MSKB SD LOCK MSKB x0000000 00 MPU STIM I 69 45 Raw Status 2 R NTRO EVEN FIELD CCAPD ee MPU STIM I SD FIELD 70 46 InterruptStatus2 R NTRO O CHNGD Q GEMD Q CCAPD Q MPU_STIM_ SD_FIELD_ 71 47 interrupt Clear2 fW INTRO CLR CHNGD CLR GEMD CLR CCAPD CLR 0xx00000 00 MPU STIM SD FIELD 72 48 ntemuptMask2 RW INTRO MSKB CHNGD MSKB GEMD MSKB CCAPD MSKB 0xx00000 00 73 49 RawStatus3 R SCM LOCK SD H LOCK SD V LOCK SD OP 50Hz x m PAL_SW_LK_ SCM_LOCK_ SD_H_LOCK_ SD_V_LOCK_ 74 4A nteruptStatus3 R CHNG Q CHNG Q SD_AD_CHNG_Q CHNG Q CHNG Q SD OP CHNG Q PAL SW LK SCM_LOCK C sp AD cHNG SD H LOCK SD V LOCK SD OP 75 4B interruptClear3 w CHNG CLR HNG CLR CLR CHNG CLR CHNG CLR CHNG CLR xx000000 00 PAL SW LK SCM_LOCK_ SD_AD_CHNG SD_H_LOCK_ SD_V_LOCK_ SD_OP_ 76 4C interrupt Mask3 RW CHNG_MSKB CHNG_MSKB MSKB CHNG_MSKB CHNG_MSKB CHNG_MSKB xx000000 00 VDP_GS_VPS__ VDP_ PDC UTC CGMS WSS 78 4E nteruptStatus4 R VDP VITC Q CHNG Q CHNGD Q VDP CCAPDQ VDP_GS_VPS_ PDC_UTC_ VDP_CGMS_WSS_ 79 4F interruptClear4 W VDP_VITC_CLR CHNG_CLR CHNGD_CLR VDP_CCAPD_CLR 00xOxOxO 00 VDP_GS_VPS__ PDC_UTC_ VDP_CGMS_WSS_ VDP_CCAPD_ 80 50 InterruptMask4 RW VDP_VITC_MSKB CHNG_MSKB CHNGD_MSKB MSKB 00x0x0x0 00 WST_PKT_ DECOD_ VDP_TTXT_TYPE_ VDP_TTXT_TYPE_ VDP_TTXT_ 96 60 VDP Configi RW DISA
40. DE pin are modified PVBEGDELO PAL VSYNC Begin Delay on Odd Field Address OxES 7 0 default No delay 1 Delays VSYNC going high on an odd field by a line relative to PVBEG Rev 0 Page 45 of 112 ADV7188 PVBEGDELE PAL VSYNC Begin Delay on Even Field Address OxES 6 0 default No delay 1 default Delays VSYNC going high on an even field by a line relative to PVBEG PVBEGSIGN PAL VSYNC Begin Sign Address 0xE8 5 0 Delays the beginning of VSYNC Set for user manual programming 1 default Advances the beginning of VSYNC Not recommended for user programming Table 63 Recommended User Settings for PAL see Figure 33 PVBEG 4 0 PAL VSYNC Begin Address 0xE8 4 0 The default value of PVBEG is 00101 indicating the PAL VSYNC begin position For all NTSC PAL VSYNC timing controls both the V bit in the AV code and the VSYNC on the VS pin are modified Register Register Name Write 0x31 VSYNC Field Control 1 Ox1A 0x32 VSYNC Field Control 2 0x81 0x33 VSYNC Field Control 3 0x84 0x34 HSYNC Position 1 0x00 0x35 HSYNC Position 2 0x00 0x36 HSYNC Position 3 Ox7D 0x37 Polarity OxA1 OxE8 PAL V Bit Beg 0x41 OxE9 PAL_V_Bit_End 0x84 OxEA PAL_F_Bit_Tog 0x06 FIELD 1 624 65 1 2 3 4 5 6 7 8 l 19 lel 22 EPI is iiuna RES PFTOG 4 0 0x3 nae FIELD 2 is 1 st 312 313 314 315 316 317 OUTPUT i VIDEO H v PFTOG 4 0 0x3 PVEND 4 0
41. EP EP 0 0 word4 3 0 0 0 User data words 14 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 0 0 Checksum Rev 0 Page 63 of 112 ADV7188 Table 81 Data Byte Allocation Raw Information Bytes User Data Words 2x Retrieved from the Video Line GDECAD Including Padding Padding Bytes DC 1 0 1 4 0 8 0 10 1 4 1 4 0 01 0 2 0 4 0 01 0 2 1 4 2 01 Gemstar Bit Names e CS 8 2 The checksum is provided to determine the e DID The data identification value is 0x140 10 bit value Care has been taken that in 8 bit systems the two LSBs do not carry vital information EP and EP The EP bit is set to ensure even parity on the data word D 8 0 Even parity means there is always an even number of 1s within the D 8 0 bit arrangement This includes the EP bit EP describes the logic inverse of EP and is output on D 9 The EP is output to ensure that the reserved codes of 00 and FF cannot happen e EF Even field identifier EF 1 indicates that the data was recovered from a video line on an even field e 2x This bit indicates whether the data sliced was in Gemstar 1x or 2x format A high indicates 2x format e line 3 0 This entry provides a code that is unique for each of the possible 16 source lines of video from which Gemstar data may have been retrieved Refer to Table 90 and Table 91 e DC I 0 Data count value The number of UDWs in the packet divided by 4 The number of
42. Enables autodetection GS_DATA_TYPE Address 0x78 5 User Sub Map Read Only Identifies the decoded Gemstar data type 0 Gemstar 1x mode is detected Read 2 data bytes from 0x84 1 Gemstar 2x mode is detected Read 4 data bytes from 0x84 The Gemstar data that is available in the I C register could be from any line of the input video on which Gemstar was decoded To read the Gemstar data on a particular video line the user should use the Manual Configuration as described in Table 65 and Table 66 and enable Gemstar decoding on the required line only Rev 0 Page 61 of 112 ADV7188 Table 79 GS VPS PDC UTC Readback Registers Signal Name Register Location GS_VPS_PDC_UTC_BYTE_0 7 0 GS VPS PDC UTC BYTE 1 7 0 GS VPS PDC UTC BYTE 2 7 0 GS VPS PDC UTC BYTE 3 7 0 VPS PDC UTC BYTE 4 7 0 VPS PDC UTC BYTE 5 7 0 VPS PDC UTC BYTE 6 7 0 VPS PDC UTC BYTE 7 7 0 VPS PDC UTC BYTE 8 7 0 VPS PDC UTC BYTE 9 7 0 VPS PDC UTC BYTE 10 7 0 VPS PDC UTC BYTE 11 7 0 VPS PDC UTC BYTE 12 7 0 VDP GS VPS PDC UTC O 7 VDP GS VPS PDC UTC 1 7 VDP GS VPS PDC UTC 2I 7 VDP GS VPS PDC UTC 3 7 VDP VPS PDC UTC 4 7 0 VDP VPS PDC UTC 5 7 0 VDP VPS PDC UTC 96 7 0 VDP VPS PDC UTC 7 7 0 VDP VPS PDC UTC 8 7 0 VDP VPS PDC UTC 9 7 0 VDP VPS PDC UTC 10 7 0 VDP VPS PDC UTC 11 7 0 VDP VPS PDC UTC 12 7 0 Address User Sub Map Dec Hex 0 132d 0x84 0 133d 0x85 0 134d 0x86
43. FORMATTER RGB gt YPrPb CONVERSION 05478 009 Figure 9 Fast Blank Block Diagram Rev 0 Page 16 of 112 Fast Blank Edge Shaping FB_EDGE_SHAPE 2 0 Address OxEF 2 0 To improve the picture transition for high speed fast blank switching an edge shape mode is available on the ADV7188 Depending on the format of the RGB inputs it may be advantageous to apply this scheme to different degrees The levels are selected via the FB EDGE SHAPE 2 0 bits Users are advised to try each of the settings and select the setting that is most visually pleasing in their system Table 13 FB EDGE SHAPE 2 0 Function ADV7188 Contrast Mode CNTR MODE 1 0 Address OxF1 3 2 The contrast level in the selected contrast reduction box is selected using the CNTR_MODE 1 0 bits Table 14 CNTR MODE 1 0 Function CNTR MODE 1 0 Description 00 default 2596 01 50 10 75 11 100 FB EDGE SHAPE 2 0 Description 000 No Edge Shaping 001 Level 1 Edge Shaping 010 default Level 2 Edge Shaping 011 Level 3 Edge Shaping 100 Level 4 Edge Shaping 101 to 111 Not Valid Contrast Reduction For overlay applications text can be more readable if the contrast of the video directly behind the text is reduced To enable the definition of a window of reduced contrast behind inserted text the signal applied to the FB pin can be interpreted as a tri level signal as shown in Figure 10 RGB SOURCE
44. GEMD_Q Gemstar data not detected in the Note that interrupt in register input video signal 0x46 for the CCAP Gemstar Gemstar data detected in the input CGMS and WSS data I using the Mode 1 data slicer video signal Reserved x SD FIELD CHNGD OQ 0 SD signal has not changed Field from ODD to Even or vice versa 1 SD signal has changed Field from ODD to Even or vice versa Reserved x Not used Reserved Not used MPU STIM INTRO Q Manual interrupt not Set Manual interrupt Set 0x47 Interrupt Clear 2 CCAPD_CLR Do not clear Note that interrupt in register Write Only Clears CCAPD_Q bit 0x46 for the CCAP Gemstar CGMS and WSS data is using GEMD_CLR Do not clear the Mode 1 data slicer Clears GEMD_Q bit Reserved 0 SD FIELD CHNGD CLR 0 Do not Clear 1 Clears SD FIELD CHNGD Q bit Reserved x Not used Reserved Not used MPU STIM INTRO CLR Do not clear Clears MPU_STIM_INTRQ_Q bit 0x48 Interrupt Mask 2 CCAPD_MSKB Masks CCAPD_Q bit Note that interrupt in register Read Write Unmasks CCAPD_Q bit 0x46 for the CCAP Gemstar T CGMS and WSS data is using GEMD MSKB Masks GEMD Q bit the Mode 1 data slicer Unmasks GEMD Q bit Reserved 0 Masks CGMS_CHNGD_Q bit SD_FIELD_CHNGD_MSKB 0 Masks SD_FIELD_CHNGD_Q bit 1 Unmasks SD FIELD CHNGD Q bit Reserved 0 Not used Reserved Not used MPU STIM INTRO MSKB Masks MPU_STIM_INTRQ_Q bit Unmasks MPU_STIM_INTRQ_Q bit 0x49 Raw Status 3 SD OP 50Hz SD 60 50Hz frame rate at SD 60 Hz signal output These bits are status bits on
45. GS PDC VPS UTC Available Address 0x78 4 User Sub Map Read Only 0 One of GS PDC VPS or UTC data was not detected 1 One of GS PDC VPS or UTC data was detected VDP GS VPS PDC UTC Readback Registers See Table 79 VPS The VPS data bits are bi phase decoded by the VDP The decoded data is available in both the ancillary stream and in the PC readback registers VPS decoded data is available in the VDP GS VPS PDC UTC 0to VDP VPS PDC UTC 12 registers addresses 0x84 0x90 User Sub Map The GS VPS PDC UTC AVI bit is set if the user had programmed I2C GS VPS PDC UTC to 01 as explained in Table 78 GEMSTAR The Gemstar decoded data is made available in the ancillary stream and any one line of Gemstar is also available in PC registers for evaluation purposes To obtain Gemstar results in PC registers the user has to program I2C GS VPS PDC UTC to 00 as explained in Table 78 VDP supports auto detection of Gemstar standard between Gemstar 1x or Gemstar 2x and decodes accordingly For this auto detection mode to work the user has to set AUTO DETECT GS TYPETPC bit register 0x61 User Sub Map and program the decoder to decode Gemstar 2x on the required lines through line programming The type of Gemstar decoded can be determined by observing the bit GS DATA TYPE bit Register 0x78 User Sub Map AUTO DETECT GS TYPE Address 0x61 4 User Sub Map 0 default Disables autodetection of Gemstar type 1
46. NOISE7 ST NOISE 6 ST NOISE5 ST NOISEA ST NOISE 3 ST NOISE2 ST NOISE 1 ST NOISEO 225 E1 SD Offset Cb RW SD OFF CB7 SD OFF CB6 SD OFF CB 5 SD OFF CB4 SD OFF CB3 SD OFF CB2 SD OFF CB 1 SD OFF CB 10000000 80 226 E2 SD Offset Cr RW SD OFF CR7 SD OFF CR6 SD OFF CR 5 SD OFF CR4 SD OFF CR3 SD OFF CR2 SD OFF CR1 SD_OFF_CR O 10000000 80 227 E3 SD Saturation CB RW SD SAT CB7 SD SAT CB6 SD SAT CB 5 SD SAT CB4 SD SAT CB 3 SD SAT CB2 SD SAT CB 1 SD SAT CB O 10000000 80 228 E4 SD Saturation Cr RW SD SAT CR7 SD SAT CR6 SD SAT CR 5 SD_SAT_CR 4 SD SAT CR3 SD SAT CR2 SD SAT CR1 SD_SAT_CR O 10000000 80 229 E5 NTSCV bit begin RW NVBEGDELO NVBEGDELE NVBEGSIGN NVBEG A NVBEG 3 NVBEG 2 NVBEG 1 NVBEG O 00100101 25 230 E6 NTSCV bit end RW NVENDDELO NVENDDELE NVENDSIGN NVEND 4 NVEND 3 NVEND 2 NVEND 1 NVEND O 00000100 04 231 E7 NTSCF bit toggle RW NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG 4 NFTOG 3 NFTOG 2 NFTOG 1 NFTOG O 01100011 63 232 E8 PALV bit begin RW PVBEGDELO PVBEGDELE PVBEGSIGN PVBEG 4 PVBEG 3 PVBEG 2 PVBEG 1 PVBEG O 01100101 65 233 E9 PALV bit end RW PVENDDELO PVENDDELE PVENDSIGN PVEND 4 PVEND 3 PVEND 2 PVEND 1 PVEND O 0001010014 234 EA PALF bit toggle RW PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG4 PFTOG 3 PFTOG 2 PFTOG 1 PFTOG O 01100011 63 235 EB Vblank Control 1 RW NVBIOLCM 1 NVBIOLCM O NVBIELCM 1 NVBIELCM O PVBIOLCM 1 PVBIOLCM O PVBIELCM 1 PVBIELCM O 01010101 55 236 EC Vblank Co
47. Only closed caption data can be embedded in the output data stream NTSC closed caption data is sliced on Line 21d on even and odd fields The corresponding enable bit has to be set high See the GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 and the GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address Ox4B 7 0 sections PAL CCAP Data Half byte output mode is selected by setting CDECAD 0 full byte output mode is selected by setting CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Table 88 and Table 89 list the bytes of the data packet PAL closed caption data is sliced from Line 22 and Line 335 The corresponding enable bits have to be set stream See the GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 and the GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address Ox4B 7 0 sections GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 The 16 bits of the GDECEL 15 0 are interpreted as a collection of 16 individual line decode enable signals Each bit refers to a line of video in an even field Setting the bit enables the decoder block trying to find Gemstar or closed caption compatible data on that particular line Setting the bit to 0 prevents the decoder from trying to retrieve data See Table 90 and Table 91 To retrieve closed caption data services on NTS
48. Pins listed in Note 6 50 50 yA All other pins 10 10 pA Input Capacitance Civ 10 pF DIGITAL OUTPUTS Output High Voltage Vou Isource 0 4 MA 24 V Output Low Voltage VoL Isink 3 2 MA 0 4 V High Impedance Leakage Current Leak 10 yA Output Capacitance Cour 20 pF POWER REQUIREMENTS Digital Core Power Supply Dvoo 1 65 1 8 2 0 V Digital I O Power Supply Dvopio 3 0 3 3 3 6 V PLL Power Supply Pvop 1 71 1 8 1 89 V Analog Power Supply Avbp 3 15 3 3 3 45 V Digital Core Supply Current Ipvop 105 mA Digital I O Supply Current Ipvbbio 4 mA PLL Supply Current lpvop 11 mA Analog Supply Current lavop CVBS input 99 mA SCART RGB FB input 269 mA Power Down Current lpwroN 0 65 mA Power Up Time tewrup 20 ms 1 All ADC linearity tests performed at input range of full scale 12 5 and at zero scale 12 5 Max INL and DNL specificationss obtained with part configured for component video input 3 Temperature range Tmn to Tmax 40 C to 85 C The min max specifications are guaranteed over this range To obtain specified Vi level on Pin 29 register 0x13 write only must be programmed with value 0x04 If Register 0x13 is programmed with value 0x00 then Viuon Pin 29 1 2 V 5 To obtain specified Vi level on Pin 29 register 0x13 write only must be programmed with value 0x04 If Register 0x13 is programmed with value 0x00 then Vion Pin 29 0 4 V 5 Pins 36 64 79 7 Excluding all TEST pins TESTO to TEST8 8 Von and
49. Vo levels obtained using default drive strength value 0xD5 in register subaddress OxF4 Guaranteed by characterization 1 ADCO powered on only All four ADCs powered on Rev 0 Page 5 of 112 ADV7188 VIDEO SPECIFICATIONS At Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvpnio 3 0 V to 3 6 V Pvpp 1 71 V to 1 89 V operating temperature range unless otherwise noted Table 2 Parameter Symbol Test Conditions Min Typ Max Unit NONLINEAR SPECIFICATIONS Differential Phase DP CVBS I P modulate 5 step 0 4 0 6 degree Differential Gain DG CVBS I P modulate 5 step 0 4 0 6 96 Luma Nonlinearity LNL CVBS I P 5 step 0 4 0 7 NOISE SPECIFICATIONS SNR Unweighted Luma ramp 61 63 dB Luma flat field 63 65 dB Analog Front End Crosstalk 60 dB LOCK TIME SPECIFICATIONS Horizontal Lock Range 5 5 Vertical Lock Range 40 70 Hz Fsc Subcarrier Lock Range 1 3 Hz Color Lock In Time 60 Lines Sync Depth Range 20 200 Color Burst Range 5 200 Vertical Lock Time 2 Fields Autodetection Switch Speed 100 Lines CHROMA SPECIFICATIONS Hue Accuracy HUE 1 degree Color Saturation Accuracy CL_AC 1 Color AGC Range 5 400 Chroma Amplitude Error 0 4 Chroma Phase Error 0 3 degree Chroma Luma Intermodulation 0 1 LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy CVBS 1 V I P CVBS 1 V I P 1 Temperature range Tmn to Tmax 40 C to 85 C The min max specifications
50. a high data rate standard data extraction is supported only through the ancillary data packet The details of these registers and their access procedure are described below User Interface for I C Readback Registers The VDP decodes all enabled VBI data standards in real time Since the C access speed is much lower than the decoded rate when the registers are being accessed they may be updated with data from the next line In order to avoid this VDP has a self clearing CLEAR bit and an AVAILABLE status bit accompanying all the C readback registers The user has to clear the I C readback register by writing a high to the CLEAR bit This resets the state of the AVAILABLE bit to low and indicates that the data in the associated readback registers is not valid After the VDP decodes the next line of the corresponding VBI data the decoded data is placed in the C readback register and the AVAILABLE bit is set to HIGH to indicate that valid data is now available Though the VDP decodes this VBI data in subsequent lines if present the decoded data is not updated to the readback registers until the CLEAR bit is set high again However this data is available through the 656 ancillary data packets The CLEAR and AVAILABLE bits are in the VDP CLEAR 0x78 User Sub Map write only and VDP STATUS 0x78 User Sub Map read only registers Example PC Readback Procedure The following tasks have to be performed to read one packet line of
51. equivalent to controlling the RESET pin on the ADV7188 issues a full chip reset All C registers are reset to their default values making these bits self clearing Some register bits do not have a reset value specified They keep their last written value Those bits are marked as having a reset value ofx in the register tables After the reset sequence the part immediately starts to acquire the incoming video signal Executing a software reset takes approximately 2 ms However it is recommended to wait 5 ms before performing any more C writes The C master controller receives a no acknowledge condition on the ninth clock cycle when chip reset is implemented See the MPU Port Description section for a full description 0 default Operation is normal 1 The reset sequence starts GLOBAL PIN CONTROL Three State Output Drivers TOD Address 0x03 6 This bit allows the user to three state the output drivers ofthe ADV7188 Upon setting the TOD bit the P19 to P0 HS VS FIELD and SFL pins are three stated The ADV7188 also supports three stating via a dedicated pin OE The output drivers are three stated if the TOD bit or the OE pin is set high The timing pins HS VS FIELD can be forced active via the TIM_OE bit For more information on three state control refer to the Three State LLC Drivers and the Timing Signals Output Enable sections Individual drive strength controls are provided by the DR_STR_XX bits 0 default
52. in full The luma shaping filter has three control registers e YSFM 4 0 allows the user to manually select a shaping filter mode applied to all video signals or to enable an automatic selection dependent on video quality and video standard e WYSFMOVR allows the user to manually override the WYSFM decision e WYSFM 4 0 allows the user to select a different shaping filter mode for good quality CVBS component YPrPb and S VHS YC input signals In automatic mode the system preserves the maximum possible bandwidth for good CVBS sources since they can successfully be combed and for luma components of YPrPb and YC sources since they need not be combed For poor quality signals the system selects from a set of proprietary shaping filter responses that complements comb filter operation in order to reduce visual artifacts The decisions of the control logic are shown in Figure 15 YSFM 4 0 Y Shaping Filter Mode Address 0x17 4 0 The Y shaping filter mode bits allow the user to select from a wide range of low pass and notch filters When switched in automatic mode the filter is selected based on other register selections such as detected video standard and properties extracted from the incoming video itself such as quality and time base stability The automatic selection always picks the widest possible bandwidth for the video input encountered e If the YSFM settings specify a filter that is YSFM is set to values ot
53. line for CTAPSP 10 Fixed 4 line for CTAPSP 11 Top lines of memory Fixed 3 line for CTAPSP 01 Fixed 4 line for CTAPSP 10 Fixed 5 line for CTAPSP 11 All lines of memory Fixed 2 line for CTAPSP 01 Fixed 3 line for CTAPSP 10 Fixed 4 line for CTAPSP 11 Bottom lines of memory CTAPSP 1 0 Chroma comb taps PAL Not used Adapts 5 lines 2 lines 2 taps Rev 0 Page 83 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 110 Adapts 5 lines 3 lines 3 taps My Li Adapts 5 lines 4 lines 4 taps Ox3A ADC Control PWRDN ADC 3 Enables power down of 0 ADC3 normal operation ADC3 1 Power down ADC3 PWRDN_ADC_2 Enables power down of 0 ADC2 normal operation ADC2 1 Power down ADC2 PWRDN_ADC_1 Enables power down of 0 ADC1 normal operation ADC 1 Power down ADC1 PWRDN_ADC_0 Enables power down of 0 ADCO normal operation ADCO 1 Power down ADCO Reserved 0 0 0 1 Set as defaul Ox3D Manual Window Reserved 0 0 1 1 Set to defaul Control CKILLTHR 2 0 o olo Kill at 0 5 CKE 1 enables the color kill function olol1 Kill at 1 596 and must be enabled for CKILLTHR 2 0 to take effect 01 0 Kill at 2 596 01 1 Kill at 496
54. not sharp but blurred in the worst case over several pixels LUMA SIGNAL WITH A TRANSITION ACCOMPANIED LUMA BY A CHROMA TRANSITION SIGNAL a Z fo ORIGINAL SLOW CHROMA DEMODULATED 7 CHROMA oo TRANSITION PRIOR TO CTI SIGNAL SHARPENED CHROMA amp TRANSITION AT THE OUTPUT OF CTI i Figure 22 CTI Luma Chroma Transition The CTI block examines the input video data It detects transitions of chroma and can be programmed to steepen the chroma edges in an attempt to artificially restore lost color bandwidth However it operates only on edges above a certain threshold to ensure that noise is not emphasized Care has also been taken to avoid edge ringing and undesirable saturation and hue distortion Chroma transient improvements are needed primarily for signals that experienced severe chroma bandwidth limitations For those types of signals it is strongly recommended to enable the CTI block via CTI EN CTI EN Chroma Transient Improvement Enable Address 0x4D 0 0 Disables the CTI block 1 default Enables the CTI block CTI AB EN Chroma Transient Improvement Alpha Blend Enable Address 0x4D 1 This bit enables an alpha blend function which mixes the transient improved chroma with the original signal The sharpness of the alpha blending can be configured via the CTI AB I1 0 bits For the alpha blender to be active the CTI block must be enabled via the CTI EN bit 0
55. o CAPY2 0 1uF oEQ OUTPUT ENABLE I P AGND CAPCI 10uF 0 1uF 1nF AGND CAPC2 ci NTO INTERRUPT O P L T SFLO SFL O P 104F 0 1uF Q REFOUT HSQ HS O P Y Y 10uF 0 14F vsQ VS O P TE FIELD FIELD O P 28 6363MHz AGND i O i DVDDIO T 47pF 1MQ t Xo O XTALI ELPFQ SELECT PC A7pF 10nF ADDRESS g P ITKO i DGND 82nF DVSS ALSB DVDDIO DVDDIO SVDD Q OQ 2ko 2kO 4000 oz MPU INTERFACE S TEST7 CONTROL LINES 1009 db V DVDDIO AGND 4 7kQ TEST8Q O RESET RESET DVDDIO 100nF AGND DGND i O O DGND 1LOAD CAP VALUES g V V ARE DEPENDENT ON 2 AGND DGND CRYSTAL ATTRIBUTES Figure 50 Typical Connection Diagram Rev 0 Page 108 of 112 ADV7188 OUTLINE DIMENSIONS TOP VIEW PINS DOWN 10 MAX COPLANARITY BSC VIEW A LEADPITCH ROTATED 90 CCW 0 22 COMPLIANT TO JEDEC STANDARDS MS 026 BEC Figure 51 80 Lead Low Profile Quad Flat Package LOFP ST 80 2 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADV7188BSTZ 40 C to 85 C 80 Lead Low Profile Quad Flat Package LOFP ST 80 2 EVAL ADV7188EB Evaluation Board The ADV7188 is a Pb free environmentally friendly product It is manufactured using the most up to date materials and processes The coating on the leads of each device is 10096 pure Sn electroplate The device is suitable for Pb free applications and is able to withsta
56. old ancillary data formatter to be backward compatible with the ADV7189B set GDE SEL OLD ADF 1 The ancillary data format in this section refers to the ADV7189B compatible ancillary data formatter 0 default Enables new ancillary data system for use with VDP and VBI System 2 1 Enables old ancillary data system for use with VBI System 2 only ADV7189B compatible Rev 0 Page 62 of 112 The format of the data packet depends on the following criteria e Transmission is 1x or 2x e Data is output in 8 bit or 4 bit format see the description of the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 bit e Data is closed caption CCAP or Gemstar compatible Data packets are output if the corresponding enable bit is set see the GDECEL 15 0 and GDECOL 15 0 descriptions and if the decoder detects the presence of data This means that for video lines where no data has been decoded no data packet is output even if the corresponding line enable bit is set Each data packet starts immediately after the EAV code of the preceding line Figure 41 and Table 80 show the overall structure of the data packet Entries within the packet are as follows e Fixed preamble sequence of 0x00 OxFF OxFF DATA IDENTIFICATION aT DATA OPTIONAL PADDING CHECK CL PREAMBLE FOR ANCILLARY DATA ADV7188 e Data identification word DID The value for the DID marking a Gemstar or CCAP data pa
57. over the commonly used PGA programmable gain amplifier before the ADCs include that the gain is now completely independent of supply temperature and process variations As shown in Figure 21 the ADV7188 can decode a video signal as long as it fits into the ADC window The two components to this are the amplitude of the input signal and the dc level on which it resides The dc level is set by the clamping circuitry see the Clamp Operation section If the amplitude of the analog video signal is too high clipping may occur resulting in visual artifacts The analog input range of the ADC together with the clamp level determines the maximum supported amplitude of the video signal The minimum supported amplitude of the input video is determined by the ADV71885 ability to retrieve horizontal and vertical timing and to lock to the color burst if present There are separate gain control units for luma and chroma data Both can operate independently of each other The chroma unit however can also take its gain value from the luma path The possible AGC modes are summarized in Table 39 It is possible to freeze the automatic gain control loops This causes the loops to stop updating and the AGC determined gain at the time of the freeze to stay active until the loop is either unfrozen or the gain mode of operation is changed The currently active gain from any of the modes can be read back Refer to the description of the dual funct
58. point and maintain an idle condition The idle condition is where the device monitors the SDA and SCLK lines waiting for the start condition and the correct transmitted address Hl US ER IDE SONS ED NT COND a SCLOCK 4 7 8 9 START ADDR R W ACK SUBADDRESS ACK DATA ACK STOP ADV7188 The R W bit determines the direction of the data Logic 0 on the LSB of the first byte means the master writes information to the peripheral Logic 1 on the LSB of the first byte means the master reads information from the peripheral The ADV7188 acts as a standard slave device on the bus The data on the SDA pin is eight bits long supporting the 7 bit addresses plus the R W bit The ADV7188 has 249 subaddresses to enable access to the internal registers It therefore interprets the first byte as the device address and the second byte as the starting subaddress The subaddresses auto increment allowing data to be written to or read from the starting subaddress A data transfer is always terminated by a stop condition The user can also access any unique subaddress register on a one by one basis without updating all the registers Stop and start conditions can be detected at any stage during the data transfer If these conditions are asserted out of sequence with normal read and write operations they cause an immediate jump to the idle condition During a given SCLK high period the user should issue only one start condition one stop condition or a sing
59. set 0 Decode and output color During VBI enables data in the VBI region to be passed 1 Blank Cr and Cb through the decoder undistorted TIM OE Timing signals output enable 0 HS VS F three stated Controlled by TOD 1 HS VS F forced active Reserved x x Reserved 1 BT656 4 Allows the user to select 0 BT656 3 complatible an output mode compatible with 1 BT656 4 compatible ITU R BT656 3 4 0x07 AutodetectEnable AD PAL EN PAL B G I H autodetect enable 0 Disable 1 Enable AD_NTSC_EN NTSC autodetect enable Disable Enable AD_PALM_EN PAL M autodetect enable 0 Disable 1 Enable AD PALN EN PAL N autodetect enable 0 Disable 1 Enable AD P60 EN PAL 60 autodetect enable 0 Disable 1 Enable AD N443 EN NTSC443 autodetect enable 0 Disable 1 Enable AD SECAM EN SECAM autodetect enable 0 Disable 1 Enable AD SEC525 EN SECAM 525 autodetect 0 Disable enable 1 Enable 0x08 Contrast Register CON 7 0 Contrast adjust This is the user 1 0 0 0 0 0 0 Luma gain 1 0x00 Gain 0 control for contrast adjustment 0x80 Gain 1 OxFF Gain 2 0x09 Reserved Reserved 1 0 0 0 0 0 0 Ox0A Brightness Register BRI 7 0 This register controls the brightness 0 0 0 0 0 0 0 0x00 OmV of the video signal Ox7F 204mV Rev 0 Page 78 of 112 ADV7188
60. setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Rev 0 Page 101 of 112 ADV7188 MODE 3 5251 6251 YPRPB INPUT Y on AIN6 Pr on AIN4 and Pb on AIN5 All standards are supported through autodetect 10 bit ITU R BT 656 output on P19 P10 Table 106 Mode 3 YPrPb Input 525i 625i Register Address Register Value Notes 0x8D 0x83 Recommended setting 0x00 0x09 Set YPrPb mode Note Writes below to registers OxC3 and OxC4 overrides INSEL YPrPb setting 0x03 0x00 10 bit mode 0x1D 0x47 Enable 28 63636 MHz crystal mode 0x27 0x98 Swap Cr and Cb Y C delay correction 0x3A 0x11 Power down ADC3 0x3B 0x71 Recommended setting Ox3D OxA2 MWE enable manual window color kill threshold to 2 Ox3E Ox6A BLM optimization Ox3F OxAO BGB optimization 0xB4 OxF9 Recommended setting OxB5 0x00 Recommended setting 0xC3 0x46 Manually mux Y signal on AIN6 to ADCO Pr signal on AIN4 to ADC1 OxC4 OxB5 Manual mux enable Pb signal on AIN5 to ADC2 OxF3 0x07 Enable anti alias filter on ADCO ADC1 and ADC2 OxF9 0x03 Set maximum v lock range OxOE 0x80 Recommended setting 0x5
61. the ADV7188 evaluation note which can be obtained from a local ADI representative FERRITE BEAD DVDDOG f yea p 77777777773 o g 3 3V 33uF 10uF 0 1uF 0 01uF POWER SUPPLY f DECOUPLING FOR Poeno Poeno Voen Ven EACH POWER FIM i PUUD FERRITE BEAD lcm rcc D E VIAE o Q i 1 8V 33uF 10uF 0 1uF 0 01uF POWER SUPPLY DECOUPLING FOR AGND DGND Vacnp Vann i Vaend VrAGND EACH POWER PIN i ee FERRITE BEAD 3 3V 33uF 10uF i OiuF 0 01uF POWER SUPPLY i DECOUPLING FOR Tacno Tacno i v AGND v AGNpD EACH POWER PIN FERRITE BEAD DVDD 1 1 1 8V 33uF 104F Tour oo wr PowERsuPPLY i DECOUPLING FOR i I i 1 Voenp Gono Joann Ypanp EACH POWER PIN CVBS1 Q m e EL coe OOOO S VIDEO OFB oaao PO rio Sam 268 PQ V gt P2O a n n AIN7 P3 P4 o 2 BLUE OAIN2 m O p RED C of 4QAIN8 P6 MULTIFORMAT PIXEL PORT O pj GREEN DAN ADV7188 P7Q EE i o P19 P10 10 BIT 1 g B evesv 0 P8 ITU R BT 656 PIXEL DATA 27MHz gH D AIN9 PIO 1 P9 PO Cb AND Cr 20 BIT gH P100 1 ITU R BT 656 PIXEL DATA 13 5MHz B AIN4 PHQ P19 P10 Y 20 BIT ITU R BT 656 PIXEL DATA 13 5MHz 1 OQ AIN10 Pi20 0 9 iRmesneseenencnHteee eB E P13O s QOAIN5 P140 AIN11 P15 P160 CVBSO Q AING P170 OAIN12 P18 P190 J CAPY1 LLC1Q 27MHz OUTPUT CLOCK 0 iuF 10uF 0 1uF 1nF LLC2Q 13 5MHz OUTPUT CLOCK
62. the mode of operation for the gain ojola AGC Peak white algorithm off Blank level to sync tip control in the luma path 0 1 0 AGC Peak white algorithm on Blank level to sync tip 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 141 Freeze gain Reserved 1 Set to 1 0x2D Chroma Gain CMG 1 1 8 Chroma manual gain can be used 0 1 0 0 CAGC 1 0 settings decide in which Control 1 to program a desired manual chroma gain mode CMG 1 1 0 operates Reading back from this register in AGC mode gives the current gain Reserved EM Setto 1 CAGT 1 0 Chroma automatic gain timing Slow TC 2 2 s Has an effect only if CAGC 1 0 is set to allows adjustment of the chroma AGC tracking speed Medium TC 1 s Fast TC 2 0 2 s Adaptive auto gain 10 eo 2 oj o eo 25 o j o Ox2E Chroma Gain CMGI7 0 Chroma manual gain lower 8 bits 0 0 0 0 0 0 CMG 11 0 750d gain is 1 in Min value is Od G 60 dB Control 2 See CMG 11 8 for description NTSC Max value is 3750 G 5 CMGI 11 0 741d gain is 1 in PAL Ox2F Luma Gain Control 1 LMG 11 8 Luma manual gain can be used to X x x x LAGC 1 0 settings decide in which program a desired manual chroma gain or to mode LMG 11 0 operates read back the actual gain value used Reserved 1 1 Set to 1 LAGT 1 0 Luma automatic gain timing 010 Slo
63. using the VBI System 2 data slicer see the ADI applications note on ADV7188 VBI processing Gemstar Data Recovery The Gemstar compatible data recovery block GSCD supports 1x and 2x data transmissions In addition it can serve as a closed caption decoder Gemstar compatible data transmissions can occur only in NTSC Closed caption data can be decoded in both PAL and NTSC The block is configured via I C in the following ways e GDECEL 15 0 allows data recovery on selected video lines on even fields to be enabled and disabled e GDECOL I15 0 enables the data recovery on selected lines for odd fields e GDECAD configures the way in which data is embedded in the video data stream The recovered data is not available through T C but is inserted into the horizontal blanking period of an ITU R BT656 compatible data stream The data format is intended to comply with the recommendation by the International Telecommunications Union ITU R BT 1364 For more information see the ITU website at www itu ch See Figure 41 GDE SEL OLD ADR Address 0x4C 3 User Map The ADV7188 has a new ancillary data output block that can be used by the VDP data slicer and the VBI System 2 data slicer The new ancillary data formatter is used by setting GDE SEL OLD ADF 0 this is the default setting If this bit is set low refer to Table 68 and Table 69 for information about how the data is packaged in the ancillary data stream To use the
64. 0 135d 0x87 136d 0x88 137d 0x89 138d Ox8A 139d Ox8B 140d 0x8C 141d Ox8D 142d Ox8E 143d Ox8F 144d 0x90 The register is a readback register default value does not apply PDC UTC PDC and UTC are data transmitted through teletext packet 8 30 format 2 magazine 8 row 30 design code 2 or 3 and packet 8 30 format 1 magazine 8 row 30 design code 0 or 1 Hence if PDC or UTC data is to be read through I C the corresponding teletext standard WST or PAL System B should be decoded by VDP The whole teletext decoded packet is output on the ancillary data stream The user can look for the magazine number row number and design code and qualify the data as PDC UTC or none of these If PDC UTC packets have been identified Byte 0 to Byte 12 are updated to the GS VPS PDC UTC 0 to VPS PDC UTC 12 registers and the GS VPS PDC UTC AVI bit set The full packet data is also available in the ancillary data format Note that the data available in the C register depends on the status ofthe WST PKT DECODE DISABLE bit Bit 3 subaddress 0x60 User Sub Map VBI SYSTEM 2 The user has an option of using a different VBI data slicer called VBI System 2 This data slicer is used to decode Gemstar and Closed Caption VBI signals only Using this system the Gemstar data is only available in the ancillary data stream A special mode enables one line of data to be read back via I C For details on how to get C readback when
65. 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 86 NTSC CCAP Data Half Byte Mode Byte DI9 DI8 DI7 DI6 D 5 D 4 DI3 D 2 D 1 D O Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 1 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 EP EP 0 0 CCAP word1 7 4 0 0 User data words 7 EP EP 0 0 CCAP word1 3 0 0 0 User data words 8 EP EP 0 0 CCAP word2 7 4 0 0 User data words 9 EP EP 0 0 CCAP word2 3 0 0 0 User data words 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 87 NTSC CCAP Data Full Byte Mode Byte DI9 DI8 D 7 DI6 D 5 D 4 D 3 D 2 D 1 DI 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 1 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 CCAP word1 7 0 0 0 User data words 7 CCAP word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Rev 0 Page 66 of 112 Table 88 PAL CCAP Data Half Byte Mode ADV7188
66. 0 Chroma 1 pixel early 0 1 1 No delay 1 0 0 Chroma 1 pixel late 1 0 1 Chroma 2 pixels late 1 1 0 Chroma 3 pixels late 1 1 1 Not valid setting AUTO_PDC_EN Automatically programs the 0 Use values in LTA 1 0 and LTA CTA values to align luma and chroma at CTA 2 0 for delaying the output for all modes of operation luma chroma 1 LTA and CTA values determined automatically SWPC Allows the Cr and Cb samples to be 0 No Swapping swapped 1 Swap the Cr and Cb O P samples Ox2B Misc Gain Control PW UPD Peak white update determines the 0 Update once per video line Peak white must be enabled See rate of gain 1 Update once per field LAGC 2 0 Reserved 1 0 0 0 0 Set to default CKE Color kill enable allows the color kill 0 Color kill disabled For SECAM color kill threshold is set at function to be switched on and off 1 Color kill enabled 8 See CKILLTHR 2 0 Reserved 1 Set to default Rev 0 Page 81 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes Ox2C AGC Mode Control CAGC 1 0 Chroma automatic gain control 0 O Manual fixed gain Use CMG 1 1 0 selects the basic mode of operation for the 0 1 Use luma gain for chroma AGC in the chroma path 1 0 Automatic gain Based on color burst 1 1 Freeze chroma gain Reserved TER Setto 1 LAGC 2 0 Luma automatic gain control 0 0 0 Manual fixed gain Use LMG 11 0 selects
67. 0 No connection 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 No connection 1 0 0 0 No connection 110 041 No connection 1 0 1 0 No connection 1 0 1 1 AIN9 1 1 0 0 AIN10 1 1 0 1 AIN11 1 1 1 0 AIN12 111 1411 No connection OxC4 ADC SWITCH 2 ADC2 SW 3 0 Manual muxing control for 0 010 0 Noconnection SETADC_SW_MAN_EN 1 ADC2 0 010 J1 No connection 0 0 1 0 AIN2 0 0 1 1 Noconnection 0 110 J0 Noconnection 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 Noconnection 1 0 0 0 Noconnection 1 0 0 1 Noconnection 1 0 1 0 AIN8 1 0 1 1 Noconnection 1 1 0 0 Noconnection 1 1 0 1 AINT11 1 1 1 0 AIN12 1 1 1 1 Noconnection Reserved x x x ADC SW MAN EN Enables manual setting 0 Disable of the input signal muxing 1 Enable OxDC Letterbox Control 1 LB TH 4 0 Sets the threshold value that 0 1 1100 Default threshold for the determines if a line is black detection of black lines Reserved 1 0 1 Set as default OxDD Letterbox Control 2 LB EL 3 0 Programs the end line of the 11110 0 LB detection ends with the last activity window for LB detection end of line of active video on a field field 1100b 262 525 LB_SL 3 0 Programs the start line of the 0 1 0 0 Letterbox detection aligned with activity window for LB detection start of the start of active video field 0100b 23 286 NTSC OxDE ST Noise Readback 1 ST NOISE 10 0 Sync Tip noise Measurement Read Only ST NOISE 10 8 x Ix x
68. 1 Recommended setting Ox3D OxA2 MWE enable manual window color kill threshold to 2 Ox3E Ox6A BLM optimization Ox3F OxAO BGB optimization Ox4D OxEE Disable CTI 0x67 0x01 Format 422 0x73 OxDO Manual gain channels A B C 0x74 0x04 Manual gain channels A B C 0x75 0x01 Manual gain channels A B C 0x76 0x00 Manual gain channels A B C 0x77 0x04 Manual offsets A to 64d B and C to 512d 0x78 0x08 Manual offsets A to 64d B and C to 512d 0x79 0x02 Manual offsets A to 64d B and C to 512d Ox7A 0x00 Manual offsets A to 64d B and C to 512d 0x93 0x78 Clamp optimization 0x94 0x23 Clamp optimization 0x95 0x11 Clamp optimization 0x96 OxCO Clamp optimization 0xC5 0x00 Recommended write OxED OxCA Enable static switching mode and select RGB input OxF3 OxOF Enable anti alias filter on all ADCs OxF9 0x03 Set maximum v lock range OxOE 0x80 Recommended setting 0x52 0x46 Recommended setting 0x54 0x00 Recommended setting Ox7F OxFF Recommended setting 0x81 0x30 Recommended setting 0x90 0xC9 Recommended setting 0x91 0x40 Recommended setting 0x92 0x3C Recommended setting 0x93 OxCA Recommended setting 0x94 OxD5 Recommended setting OxB1 OxFF Recommended setting OxB6 0x08 Recommended setting 0xCO Ox9A Recommended setting OxCF 0x50 Recommended setting OxDO Ox4E Recommended setting OxD1 OxB9 Recommended setting OxD6 OxDD Recommended setting OxD7 OxE2 Recommended setting OxE5 0x51 Recommended s
69. 1110001111000 GEMSTAR_1X NTSC 3 001 100 GEMSTAR 2X NTSC 11 1001 1011 101 101 1101 1001 CCAP NTSC and PAL 3 001 100 CGMS NTSC 1 0 0 Table 72 Total User Data Words for Different VBI Standards Framing code VBIData Number of VBI Standard ADF Mode UDWs Words Padding Words Total UDWs TIXT SYSTEM A PAL 00 Nibble Mode 6 74 0 84 01 10 Byte Mode 3 37 0 44 00 Nibble Mode 6 84 2 96 TIXT SYSTEM B PAL T GB PAL 01 10 Byte Mode 3 42 3 52 00 Nibble Mod 6 68 2 80 TTXT SYSTEM B NTSC EHE 01 10 Byte Mode 3 34 3 44 00 Nibble Mode 6 66 0 76 TTXT SYSTEM C PAL and NTSC SC End 01 10 Byte Mode 3 33 2 42 00 Nibble Mod 6 68 2 80 TTXT SYSTEM D PAL and NTSC DC 01 10 Byte Mode 3 34 3 44 00 Nibble Mode 6 26 0 36 VPS PAL FAL 01 10 Byte Mode 3 13 0 20 00 Nibble Mod 6 18 0 28 VITC NTSC and PAL iM E 01 10 Byte Mode 3 9 0 16 00 Nibble Mode 6 4 2 16 WSS PAL PAL 01 10 Byte Mode 3 2 3 12 00 Nibble Mod 6 4 2 16 GEMSTAR_1X NTSC AE R 01 10 Byte Mode 3 2 3 12 00 Nibble Mode 6 8 2 20 GEMSTAR_2X NTSC 2X 01 10 Byte Mode 3 4 1 12 00 Nibble Mod 6 4 2 16 CCAP NTSC and PAL D dd 01 10 Byte Mode 3 2 3 12 00 Nibble Mode 6 6 0 16 CGMS NTSC 01 10 Byte Mode 3 343 2 12 The first four UDWs are always the ID Rev 0 Page 55 of 112 ADV7188 PC Interface Dedicated I C readback registers are available for CCAP CGMS WSS Gemstar VPS PDC UTC and VITC Since Teletext is
70. 12d 0x78 0x08 Manual offsets A to 64d B and C to 512d 0x79 0x02 Manual offsets A to 64d B and C to 512d Ox7A 0x00 Manual offsets A to 64d B and C to 512d OxC5 0x00 Recommended write OxED 0x12 Enable dynamic fast blank mode OxF3 OxOF Enable anti alias filter on all ADCs OxF9 0x03 Set maximum v lock range OxOE 0x80 Recommended setting 0x49 0x01 Recommended setting 0x52 0x46 Recommended setting 0x54 0x00 Recommended setting Ox7F OxFF Recommended setting 0x81 0x30 Recommended setting 0x90 0xC9 Recommended setting 0x91 0x40 Recommended setting 0x92 0x3C Recommended setting 0x93 OxCA Recommended setting 0x94 OxD5 Recommended setting OxB1 OxFF Recommended setting OxB6 0x08 Recommended setting 0xCO Ox9A Recommended setting OxCF 0x50 Recommended setting OxDO Ox4E Recommended setting OxD1 OxB9 Recommended setting OxD6 OxDD Recommended setting 0xD7 OxE2 Recommended setting OxE5 0x51 Recommended setting OxOE 0x00 Recommended setting Rev 0 Page 104 of 112 MODE 6 SCART RGB INPUT STATIC FAST BLANK CVBS AND RGB CVBS Input on AIN11 B INPUT on AIN7 R INPUT on AINS G INPUT on AINO 10 bit ITU R BT 656 output on P19 P8 Table 109 Mode 6 SCART CVBS S Video Autodetect on AIN 11 AIN12 ADV7188 Register Address Register Value Notes 0x00 OxOF CVBS on AIN11 0x03 0x00 10 bit mode 0x1D 0x47 Enable 28 63636 MHz crystal mode 0x3A 0x10 Power up all four ADCs Ox3B 0x7
71. 2 0x46 Recommended setting 0x54 0x00 Recommended setting Ox7F OxFF Recommended setting 0x81 0x30 Recommended setting 0x90 0xC9 Recommended setting 0x91 0x40 Recommended setting 0x92 0x3C Recommended setting 0x93 OxCA Recommended setting 0x94 OxD5 Recommended setting Ox7E 0x73 Recommended setting OxB1 OxFF Recommended setting OxB6 0x08 Recommended setting 0xCO Ox9A Recommended setting OxCF 0x50 Recommended setting OxDO Ox4E Recommended setting OxD1 OxB9 Recommended setting OxD6 OxDD Recommended setting OxE5 0x51 Recommended setting OxOE 0x00 Recommended setting Rev 0 Page 102 of 112 MODE 4 SCART S VIDEO OR CVBS AUTODETECT Y CVBS Input on AIN11 C INPUT on AIN12 10 bit ITU R BT 656 output on P19 to P10 Table 107 Mode 4 SCART CVBS S Video Autodetect on AIN 11 AIN12 ADV7188 Register Address Register Value Notes 0x03 0x1D Ox3A Ox3B Ox3D Ox3E Ox3F 0x69 OxF3 OxF9 OxOE 0x52 0x54 Ox7F 0x81 0x90 0x91 0x92 0x93 0x94 OxB1 OxB6 0xCO OxCF OxDO OxD1 OxD6 OxD7 OxE5 OxOE 0x00 0x47 0x13 0x71 OxA2 Ox6A OxAO 0x03 0x03 0x03 0x80 0x46 0x00 OxFF 0x30 0xC9 0x40 0x3C OxCA OxD5 OxFF 0x08 Ox9A 0x50 Ox4E OxB9 OxDD OxE2 0x51 0x00 10 bit mode Enable 28 63636 MHz crystal mode Power down ADC2 and ADC3 Recommended Setting MWE enable manual window color kill threshold to 2 BLM optimization BGB optimization
72. 2 Y YPrPb2 Y AIN9 45 CVBS9 SCART1 G AIN3 46 CVBS3 YC3 Y YPrPb2 Pb AIN10 57 CVBS10 AINA 58 CVBS4 YC1 C YPrPb1 Pb SCART2 B AIN11 59 CVBS11 SCART1 CVBS AIN5 60 CVBS5 YC2 C YPrPb1 Pr SCART2 R AIN12 61 Not Available AING 62 CVBS6 YC3 C YPrPb2 Pr SCART2 G Table 11 Manual Mux Settings for All ADCs SETADC SW MAN EN 1 ADCO ADC1 ADC2 ADC3 ADCO sw 3 0 Connected To ADC1 sw 3 0 Connected To ADC2 sw 3 0 Connected To ADC3 sw 3 0 Connected To 0000 No Connection 0000 No Connection 0000 No Connection 0000 No Connection 0001 AIN1 0001 No Connection 0001 No Connection 0001 No Connection 0010 AIN2 0010 No Connection 0010 AIN2 0010 No Connection 0011 AIN3 0011 AIN3 0011 No Connection 0011 No Connection 0100 AIN4 0100 AIN4 0100 No Connection 0100 AIN4 0101 AIN5 0101 AIN5 0101 AIN5 0101 No Connection 0110 AIN6 0110 AING 0110 AIN6 0110 No Connection 0111 No Connection 0111 No Connection 0111 No Connection 0111 No Connection 1000 No Connection 1000 No Connection 1000 No Connection 1000 No Connection 1001 AIN7 1001 No Connection 1001 No Connection 1001 AIN7 1010 AIN8 1010 No Connection 1010 AIN8 1010 No Connection 1011 AIN9 1011 AIN9 1011 No Connection 1011 No Connection 1100 AIN10 1100 AIN10 1100 No Connection 1100 No Connection 1101 AIN11 1101 AIN11 1101 AIN11 1101 No Connection 1110 AIN12 1110 AIN12 1110 AIN12 1110 No Connection 1111 No Connection 1111 No Connection 1111 No Connection 1111 No Connection
73. 24 DNR TH 23 DNR TH 22 DNR TH 2 1 DNR TH 2 0 00000100 04 Rev 0 Page 76 of 112 Table 101 provides a detailed description of the registers located in the User Map Table 101 User Map Detailed Description ADV7188 Address Register Bit Description Bit Comments Notes 0x00 Input Control INSEL 3 0 The INSEL bits allow the user to select an input channel and the input format CVBS in on AIN1 SCART G on AIN6 AIN9 B on AIN4 AIN7 R on AIN5 AIN8 CVBS in on AIN2 SCART G on AIN6 AIN9 B on AIN4 AIN7 R on AIN5 AIN8 CVBS in on AIN3 SCART G on AIN6 AIN9 B on AIN4 AIN7 R on AIN5 AIN8 CVBS in on AIN4 SCART G on AINO9 B on AIN7 R on AIN8 CVBS in on AIN5 SCART G on AINO9 B on AIN7 R on AIN8 CVBS in on AIN6 SCART G on AINO9 B on AIN7 R on AIN8 Composite and SCART RGB RGB analog input options selectable via RGB IP SEL Y on AIN1 C on AIN4 Y on AIN2 C on AIN5 Y on AIN3 C on AIN6 S Video Y on AINT Pb on AIN4 Pr on AINS Y on AIN2 Pb on AIN3 Pr on AIN6 YpbPr 2 2 2 2lol o eo ojojo 2 2 2 olo 2 2 RA X ck RS ee CVBS in on AIN7 SCART G on AIN6 B on AIN4 Ron AIN5 CVBS in on AIN8 SCART G on AIN6 B on AIN4 Ron AIN5 CVBS in on AIN9 SCART G on AIN6 B on AIN4 Ron AIN5 CVBS in on AIN10 SCART G on AIN6 AIN9 B on AIN4 AIN7 Ron AIN5 AIN8 CVBS in on AIN11 SCART G on AI
74. 286 Gemstar 1x 8 WST 320 WST 25 Gemstar 1x 287 Gemstar 1x 9 WST 321 WST 288 Gemstar 1x 10 WST 322 WST 11 WST 323 WST 12 WST 324 WST 10 NABTS 272 NABTS 13 WST 325 WST 11 NABTS 273 NABTS 14 WST 326 WST 12 NABTS 274 NABTS 15 WST 327 WST 13 NABTS 275 NABTS 16 VPS 328 WST 14 VITC 276 NABTS 17 329 VPS 15 NABTS 277 VITC 18 330 16 VITC 278 NABTS 19 VITC 331 17 NABTS 279 VITC 20 WST 332 VITC 18 NABTS 280 NABTS 21 WST 333 WST 19 NABTS 281 NABTS 22 CCAP 334 WST 20 CGMS 282 NABTS 23 WSS 335 CCAP 21 CCAP 283 CGMS 24 4 Full WST 336 WST 22 4 Full NABTS 284 CCAP ODD Field ODD Field 337 Full WST 285 Full NABTS EVEN Field EVEN Field Table 65 VBI Data Standards Manual Configuration VBI DATA Px Ny 625 50 PAL 525 60 NTSC 0000 Disable VDP Disable VDP 0001 Teletext system identified by VDP TTXT TYPE Teletext system identified by VDP TTXT TYPE 0010 VPS ETSI EN 300 231 V 1 3 1 Reserved 0011 VITC VITC 0100 WSS BT 1119 1 ETSI EN 300294 CGMS EIA J CPR 1204 IEC 61880 0101 Reserved Gemstar_1X 0110 Reserved Gemstar_2X 0111 CCAP CCAP EIA 608 1000 1111 Reserved Reserved Table 66 VBI Data Standards to be Decoded on Line Px PAL or Line Ny NTSC Address Signal Name Register Location Dec Hex VBI_DATA_P6_N23 VDP_LINE_OOF 7 4 101 0x65 VBI_DATA_P7_N24 VDP_LINE_010 7 4 102 0x66 VBI_DATA_P8_N25 VDP_LINE_011 7 4 103 0x67 VBI_DATA_P9 VDP_LINE_012 7 4 104 0x68 VBI_DATA_P10 VDP LIN
75. 3 VBI DATA P334 N282 VDP LINE O1E 3 0 116 0x74 VBI DATA P335 N283 VDP LINE O1F 3 0 117 0x75 VBI DATA P336 N284 VDP LINE 020 3 0 118 0x76 VBI DATA P337 N285 VDP LINE 021 3 0 119 0x77 Note Full field detection lines other than VBI lines of any standard can also be enabled by writing into registers VBI DATA P24 N22 3 0 and VBI DATA P337 N285 3 0 So if VBI DATA P24 N22 3 0 is programmed with any Teletext standard then teletext is decoded off the whole of the ODD field The corresponding register for the EVEN field is VBI DATA P337 N285 3 0 Teletext System Identification VDP assumes that if teletext is present in a video channel all the teletext lines complies with a single standard system Thus the line programming using VBI DATA Px Ny registers identifies whether the data in line is teletext the actual standard is identified by the VDP TTXT TYPE MAN bit To program the VDP TTXT TYPE MAN bit the VDP TTXT TYPE MAN ENABLE bit must be set to 1 VDP TTXT TYPE MAN ENABLE Enable Manual Selection of Teletext Type Address 0x60 2 User Sub Map 0 default Manual programming of the teletext type is disabled 1 Manual programming of the teletext type is enabled VDP TTXT TYPE MAN 1 0 Specify the Teletext Type Address 0x60 1 0 User Sub Map These bits specify the teletext type to be decoded These bits are functional only if VDP TTXT TYPE MAN ENABLE is set to 1 Table 67 VDP TTXT TYPE MAN Fun
76. 36 37 38 39 40 uadapoOo201aB8B22gsgsis artac2e g Hadek 8 3 go s Figure 5 80 Lead LQFP Pin Configuration Table 7 Pin Function Descriptions Pin No Mnemonic Type Function 3 9 14 31 71 DGND G Digital Ground 39 47 53 56 AGND G Analog Ground 4 15 DVDDIO P Digital I O Supply Voltage 3 3 V 10 30 72 DVDD P Digital Core Supply Voltage 1 8 V 50 AVDD P Analog Supply Voltage 3 3 V 38 PVDD P PLL Supply Voltage 1 8 V 42 44 46 58 60 62 AIN1 to AIN12 l Analog Video Input Channels 41 43 45 57 59 61 11 INT O Interrupt Request Output Interrupt occurs when certain signals are detected on the input video See the User Sub Map register details in Table 103 40 FB Fast Blank FB is a fast switch overlay input that switches between CVBS and RGB analog signals 70 78 13 25 69 63 TESTO to TEST5 Leave these pins unconnected 77 65 TEST6 to TEST7 Tie to AGND 16 TEST8 Tie to DVDDIO 35 34 33 32 24 23 PO to P19 O Video Pixel Output Port 22 21 20 19 18 17 8 7 6 5 76 75 74 73 2 HS O Horizontal Synchronization Output Signal 1 VS O Vertical Synchronization Output Signal 80 FIELD O Field Synchronization Output Signal 67 SDA 1 0 I C Port Serial Data Input Output Pin 68 SCLK lC Port Serial Clock Input Max Clock Rate of 400 kHz Rev 0 Page 10 of 112 ADV7188 Pin No Mnemonic Type Function 66 ALSB l This pin selects the I C address for the ADV7188 ALSB set to Logic 0 sets
77. 5 3 ADV7188 STATUS_3 7 0 Address 0x13 7 0 See Table 23 AD_RESULT 2 0 Autodetection Result Address 0x10 6 4 These bits report back on the findings from the autodetection block For more information on enabling the autodetection block see the General Setup section For information on configuring it see the Autodetection of SD Modes section for information on the timing Table 20 AD_RESULT Function Depending on the setting of the FSCLE bit the STATUS_1 0 AD_RESULT 2 0 Description and STATUS_1 1 bits are based solely on horizontal timing 000 NTSM MJ information or on the horizontal timing and lock status of the 001 NTSC 443 color subcarrier See the FSCLE Fsc Lock Enable Address 0x51 010 PAL M 7 section 011 PAL 60 100 PAL BGHID STATUS 2 7 0 Address 0x12 7 0 101 SECAM See Table 22 110 PAL Combination N 111 SECAM 525 Table 21 STATUS 1 Function STATUS 1 7 0 Bit Name Description 0 IN LOCK In lock right now 1 LOST LOCK Lost lock since last read of this register 2 FSC LOCK Fsc locked right now 3 FOLLOW PW AGC follows peak white algorithm 4 AD RESULT O Result of autodetection 5 AD RESULT 1 Result of autodetection 6 AD RESULT 2 Result of autodetection 7 COL KILL Color kill active Table 22 STATUS 2 Function STATUS 2 7 0 Bit Name Description 0 MVCS DET Detected Macrovision color striping 1 MVCS T3 Macrovision color striping protection
78. A P324 VBI DATA P324 106 6A VDP LINE 014 RW P113 VBL DATA P112 VBI DATA P11 1 VBI DATA P110 N2723 N2722 N272 1 N272 0 00000000 00 VBI DATA VBLDATA P12 VBLDATA P12 VBI DATA P12 VBL DATA P325 VBI DATA P325 VBL DATA P325 VBI DATA P325 107 6B VDP LINE 015 RW P12 N103 N102 N10 1 N10 0 N2733 N2732 N273 1 N273 0 00000000 00 VBI DATA VBLDATA P13 VBI DATA P13 VBLDATA P13 VBL DATA P326 VBI DATA P326 VBL DATA P326 VBI DATA P326 108 6C VDPLINE O16 RW P13_N11 3 N11 2 N11 1 N11 0 N2743 N2742 N274 1 N274 0 00000000 00 VBI DATA VBLDATA Pl4 VBI DATA P14 VBI DATA P14 VBL DATA P327 VBI DATA P327 VBI DATA P327 VBI DATA P327 109 6D VDP LINE 017 RW P14 N123 N122 N12 1 N12 0 N2753 N275 2 N275 1 N275 0 00000000 00 VBI DATA VBLDATA P15 VBI DATA P15 VBI DATA P15 VBL DATA P328 VBI DATA P328 VBL DATA P328 VBI DATA P328 110 6E VDP LINE 018 RW P15 N133 N132 N13 1 N13 0 N276 3 N276 2 N276 1 N276 0 00000000 00 VBI DATA VBLDATA P 6 VBI DATA P16 VBI DATA P16 VBL DATA P329 VBI DATA P329 VBL DATA P329 VBI DATA P329 111 6F VDP LINE 019 RW P16 N143 N142 N14 1 N14 0 N2773 N2772 N277 1 N277 0 00000000 00 VBI DATA VBI DATA P17 VBL DATA P17 VBLDATA P17 VBI DATA P330 VBI DATA P330 VBI DATA P330 VBLDATA P330 112 70 VDP LINE 01A RW P17 N153 N152 N15 1 N15 0 N2783 N2782 N278 1 N278 0 00000000 00 VBI DATA VBLDATA P18 VBI DATA P18 VBI DATA P18 VBL DATA P331 VBI DATA P331 VBL
79. ABLE bit Bit 3 register 0x60 User Sub Map The feature is valid for WST only Table 74 WST Packet Description WST PKT DECOD DISABLE Disable Hamming Decoding of Bytes in WST Address 0x60 3 User Sub Map 0 Enables hamming decoding of WST packets 1 default Disables hamming decoding of WST packets For hamming coded bytes the dehammed nibbles are output along with some error information from the hamming decoder as follows e Input Hamming Coded byte D3 P3 D2 P2 D1 P1 DO PO bits in decoded order e Output Dehammed byte EL E0 0 0 D3 D2 DI D0 Di corrected bits Ei error info Table 73 Explanation of Error Bits in the Dehammed Output Byte Output Data Bits E 1 0 Error Information in Nibble 00 No errors detected OK 01 Error in P4 OK 10 Double error BAD 11 Single error found and corrected OK The different WST packets that are decoded are described in Table 74 Packet Byte Description Header Packet 1P Byte Mag No Dehammed Byte 4 X 00 2P Byte Row No Dehammed Byte 5 3 Byte Page No Dehammed Byte 6 4 Byte Page No Dehammed Byte 7 5th to 10 Byte Control Bytes Dehammed Byte 8 to Byte 13 11 to 42 4 Byte Raw data bytes Text Packets 1 Byte Mag No Dehammed Byte 4 X 01 to X 25 2 4 Byte Row No Dehammed Byte 5 3 to 42 Byte Raw data bytes 8 30 Format 1 packet 1 Byte Mag No Dehammed Byte 4 Desig Code 0000 o
80. BLE MAN_ENABLE MAN 1 TYPE_MAN O 10001000 88 AUTO_DETECT_ 97 61 VDP Config 2 RW GS TYPE 0001xx00 10 VDP ADF 98 62 Config 1 RW ADF ENABLE ADF MODE ADF MODEO ADF DID4 ADF DID 3 ADF DID2 ADF DID 1 ADF DID O 00010101 15 VDP ADF 99 63 Config 2 RW DUPLICATE ADF ADF_SDID 5 ADF SDIDA ADF SDID 3 ADF SDID 2 ADF SDID 1 ADF SDID O 0x101010 2A VBI DATA VBI DATA VBI DATA VBI DATA 100 64 VDP_LINE_OOE RW MAN LINE PGM P3183 P3182 P318 1 P318 0 Oxxx0000 00 VBI_DATA_ VBI DATA P6 VBLDATA P6 VBL DATA P6 VBLDATA P319 VBL DATA P319 VBL DATA P319 VBI DATA P319 101 65 VDP LINE OOF RW P6 N233 N232 N23 1 N23 0 N286 3 N286 2 N286 1 N286 0 00000000 00 VBI DATA VBLDATA P7 VBLDATA P7 VBLDATA P7 VBLDATA P320 VBI DATA P320 VBLDATA P320 VBI DATA P320 102 66 VDP LINE O10 RW P7 N243 N242 N24 1 N24 0 N287 3 N287 2 N287 1 N287 0 00000000 00 VBI DATA VBI DATA P8 VBLDATA P8 VBL DATA P8 VBLDATA P321 VBL DATA P321 VBL DATA P321 VBI DATA P321 103 67 VDP LINE O11 RW P8 N253 N25 2 N25 1 N25 0 N288 3 N288 2 N288 1 N288 0 00000000 00 VBI DATA VBI DATA VBI DATA 104 68 VDP LINE 012 RW P93 VBL DATA P92 VBLDATA P9 1 VBLDATA P90 P3223 VBL DATA P3222 P322 1 VBI DATA P3220 00000000 00 VBI DATA VBI DATA 105 69 VDP LINE 013 RW P103 VBL DATA P102 VBI_DATA_P10 1 VBI DATA P10 0 VBI DATA P3233 VBI DATA P3232 P323 1 VBI DATA P323 0 00000000 00 VBI DATA VB DATA P324 VBI DATA P324 VBL DAT
81. C Line 284 GDECEL 11 must be set To retrieve closed caption data services on PAL Line 335 GDECEL 14 must be set The default value of GDECEL 15 0 is 0x0000 This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the even field The User should only enable Gemstar slicing on lines where VBI data is expected Rev 0 Page 67 of 112 ADV7188 Table 90 NTSC Line Enable Bits and Corresponding Line Numbering Line Number Line 3 0 ITU R BT 470 Enable Bit Comment 0 10 GDECOL 0 Gemstar 1 11 GDECOL 1 Gemstar 2 12 GDECOL 2 Gemstar 3 13 GDECOL 3 Gemstar 4 14 GDECOL 4 Gemstar 5 15 GDECOLL 5 Gemstar 6 16 GDECOL 6 Gemstar 7 17 GDECOL 7 Gemstar 8 18 GDECOL 8 Gemstar 9 19 GDECOL 9 Gemstar 10 20 GDECOL 10 Gemstar 11 21 GDECOL 11 Gemstar or closed caption 12 22 GDECOL 12 Gemstar 13 23 GDECOL 13 Gemstar 14 24 GDECOL 14 Gemstar 15 25 GDECOL 15 Gemstar 0 273 10 GDECEL 0 Gemstar 1 274 11 GDECEL 1 Gemstar 2 275 12 GDECEL 2 Gemstar 3 276 13 GDECEL 3 Gemstar 4 277 14 GDECEL 4 Gemstar 5 278 15 GDECEL 5 Gemstar 6 279 16 GDECEL 6 Gemstar 7 280 17 GDECEL 7 Gemstar 8 281 18 GDECEL 8 Gemstar 9 282 19 GDECEL 9 Gemstar 10 283 20 GDECEL 10 Gemstar 11 284 21 GDECEL 11 Gemstar or closed caption 12 285 22 GDECEL 12 Gemstar 13 286 23 GDECEL 13 Gemstar 14 287 24 GDECEL 14 Gemstar 15 288 25 GDECE
82. C frequency to 42 75 Hz 731 lines frame Limit minimum VSYNC frequency to 39 51 Hz 791 lines frame VS_COAST_MODE 1 0 Auto coast mode 50 Hz coast mode 60 Hz coast mode a lolo 0 i Reserved This value sets up the output coast frequency Reserved OxFB Peaking Control PEAKING GAIN 7 0 Increases decreases the gain for high frequency portions of the video signal OxFC Coring Threshold 2 DNR_TH2 7 0 Specifies the max edge that is interpreted as noise and therefore blanked Rev 0 Page 90 of 112 USER SUB MAP ADV7188 The collective name for the subaddress registers in Table 102 is User Sub Map To access the User Sub Map SUB_USR_EN in Register Address 0x0E User Map must be programmed to 1 Table 102 User Sub Map Register Details Address Reset Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value Hex nterrupt INTRO DUR INTRO DUR MV INTRQ MV INTRO MPU STIM 64 40 ConfigurationO RW SEL 1 SELO SEL1 SELO NTRQ INTRQ OP SEL1 INTRO OP SELO 0001x000 10 SD FR 66 42 InterruptStatus1 R MV PS C Q HNG Q SD UNLOCK Q SD LOCK Q SD_FR_ 67 43 interruptClear1 W MV PS
83. Conforms to Type 3 if high and to Type 2 if low 2 MV PS DET Detected Macrovision pseudo Sync pulses 3 MV AGC DET Detected Macrovision AGC pulses 4 LL NSTD Line length is nonstandard 5 FSC NSTD Fsc frequency is nonstandard 6 Reserved 7 Reserved Table 23 STATUS 3 Function STATUS 3 7 0 Bit Name Description 0 INST HLOCK Horizontal lock indicator instantaneous 1 GEMD Gemstar detect 2 SD OP 50HZ Flags whether 50 Hz or 60 Hz is present at output 3 CVBS Indicates if a CVBS signal is detected in YC CVBS autodetection configuration 4 FREE RUN ACT Indicates if the ADV7188 is in free run mode Outputs a blue screen by default See the DEF VAL AUTO EN Default Value Automatic Enable Address OxOC 1 bit for details about disabling this function 5 STD FLD LEN Field length is correct for currently selected video standard 6 INTERLACED Interlaced video detected field sequence found 7 PAL SW LOCK Reliable sequence of swinging bursts detected Rev 0 Page 21 of 112 ADV7188 STANDARD DEFINITION PROCESSOR SDP STANDARD DEFINITION PROCESSOR EJ AENEA DATA EM EJ AENEA EM SLLC CONTROL LUMA DIGITIZED CVBS LUMA NU DIGITIZED Y YC FILTER 1 CONTROL I 1 1 SYNC RESAMPLE CODE VIDEO DATA EXTRACT ppepictor CONTROL 1 OUTPUT 1 I CHROMA DIGITIZED CVBS DIGITAL CHROMA CHROMA CHROMA _ CHROMA MEASUREMENT DIGITIZED C YC FINE i DEMOD g FILTER Le cdita LU 2D C
84. D M N PAL combination N NTSC M NTSC J SECAM 50 Hz 60 Hz NTSC 4 43 and PAL 60 ADV7188 GENERAL SETUP Video Standard Selection The VID SEL 3 0 register allows the user to force the digital core into a specific video standard Under normal circumstances this should not be necessary The VID_SEL 3 0 bits default to an autodetection mode that supports PAL NTSC SECAM and variants thereof The following section describes the autodetec tion system Autodetection of SD Modes In order to guide the autodetect system individual enable bits are provided for each of the supported video standards Setting the relevant bit to 0 inhibits the standard from being automatically detected Instead the system picks the closest of the remaining enabled standards The results of the autodetection can be read back via the status registers See the Global Status Registers section for more information VID SEL 3 0 Address 0x00 7 4 Table 24 VID SEL Function VID SEL 3 0 Description 0000 default Autodetect PAL BGHID lt gt NTSC J without pedestal SECAM 0001 Autodetect PAL BGHID NTSC M with pedestal SECAM 0010 Autodetect PAL N pedestal NTSC J no pedestal SECAM 0011 Autodetect PAL N with pedestal lt gt NTSC M with pedestal SECAM 0100 NTSC J 1 0101 NTSC M 1 0110 PAL 60 0111 NTSC 4 43 1 1000 PAL BGHID 1001 PAL N PAL BGHID with pedestal 1010 PAL M without pe
85. DATA P331 VBL DATA P331 113 71 VDP LINE 01B RW P18_N16 3 N162 N16 1 N16 0 N2793 N2792 N279 1 N279 0 00000000 00 VBI DATA VBLDATA P19 VBI DATA P19 VBI DATA P19 VBL DATA P332 VBI DATA P332 VBL DATA P332 VBI DATA 114 72 VDP LINE OC RW P19 N173 N172 N17 1 N17 0 N280 3 N280 2 N280 1 P332_N280 0 00000000 00 Rev 0 Page 91 of 112 ADV7188 Address Reset Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value Hex VBI DATA VBI DATA P20 VBI DATA P20 VBI DATA P20 VBI DATA P333 VBI DATA P333 VBI DATA P333 VBI DATA 115 73 VDP LINE 01D RW P20 N18 3 N18 2 N18 1 N18 0 N281 3 N281 2 N281 1 P333 N281 0 00000000 00 VBI DATA VBI DATA P21 VBI DATA P21 VBI DATA P21 VBI DATA P334 VBI DATA P334 VBI DATA P334 VBl DATA 116 74 VDP LINE O1E RW P21 N19 3 N19 2 N19 1 N19 0 N282 3 N282 2 N282 1 P334 N282 0 00000000 00 VBI DATA VBI DATA P22 VBI DATA P22 VBI DATA P22 VBI DATA P335 VBI DATA P335 VBI DATA P335 VBl DATA 117 75 VDP LINE O1F RW P22 N20 3 N20 2 N20 1 N20 0 N283 3 N283 2 N283 1 P335 N283 0 00000000 00 VBI DATA VBI DATA P23 VBI DATA P23 VBI DATA P23 VBI DATA P336 VBI DATA P336 VBI DATA P336 VBl DATA 118 76
86. DV717x encoders Lock Related Controls Lock information is presented to the user through Bits 1 0 of the Status 1 register See the STATUS 1 7 0 Address 0x10 7 0 section Figure 13 outlines the signal flow and the controls available to influence the way the lock status information is generated SRLS Select Raw Lock Signal Address 0x51 6 Using the SRLS bit the user can choose between two sources for determining the lock status per Bits 1 0 in the Status 1 register The time win signal is based on a line to line evaluation of the horizontal synchronization pulse of the incoming video It reacts quite quickly The free run signal evaluates the properties of the incoming video over several fields and takes vertical synchronization information into account 0 default Selects the free run signal 1 Selects the time win signal FILTER THE RAW LOCK SIGNAL CIL 2 0 COL 2 0 STATUS 1 0 STATUS 1 1 MEMORY 05478 013 Figure 13 Lock Related Signal Path Rev 0 Page 24 of 112 FSCLE Fsc Lock Enable Address 0x51 7 The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits 1 0 in STATUS_1 This bit must be set to 0 when operating in YPrPb component mode to generate a reliable HLOCK status bit 0 default Makes the overall lock status dependent on the horizontal syn
87. E MOIRE SERIE 112us 49 1us 0 5us CRC SEQUENCE i 2 235us 20ns VDP_CGMS_WSS_ VDP_CGMS_WSS_DATA_1 DATA_0 3 0 05478 038 Figure 38 CGMS Waveform Rev 0 Page 59 of 112 ADV7188 Table 75 CGMS Readback Registers Signal Name Register Location Address User Sub Map CGMS_WSS_DATA_0 3 0 VDP_CGMS_WSS_DATA_0 3 0 125d 0x7D CGMS WSS DATA 1 7 0 VDP CGMS WSS DATA 1 7 0 126d Ox7E CGMS WSS DATA 2 7 0 VDP CGMS WSS DATA 2 7 0 127d Ox7F The register is a readback register default value does not apply 10 5 0 25us 12 91us 7 CYCLES OF 0 5035MHz CLOCK RUN IN 50 IRE 40 IRE REFERENCE COLOR BURST 9 CYCLES FREQUENCY Fgc 3 579545MHz AMPLITUDE 40 IRE 10 003us 27 382us is MM M We 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 P PEET 4 2 XA4 m u7 VDP CCAP DATA 0 VDP CCAP DATA 1 33 764us 05478 039 Figure 39 CCAP Waveform and Decoded Data Correlation Table 76 CCAP Readback Registers Signal Name Register Location Address User Sub Map CCAP BYTE 1 7 0 VDP CCAP DATA 0 7 0 121d 0x79 CCAP BYTE 2 7 0 VDP CCAP DATA 1 7 0 122d Ox7A The register is a readback register default value does not apply BITO BIT1 wee lew Sims rs ees rim riim p BIT88 BIT89 VITC WAVEFORM 05478 040 Figure 40 VITC Waveform and Decoded Data Correlation VITC
88. E 0 FB threshold 2V CNTR ENABLE 1 FB threshold Not Used B olo ojij jo CNTR LEVEL 1 0 Controls reference level for 0 4 V contrast reduction threshold CNTR ENABLE 1 0 6 V contrast reduction threshold 0 8 V contrast reduction threshold 0 contrast reduction comparator 0 1 1 2 oil 2 o Not used OxF3 AFE CONTROL 1 AA FILT EN O 0 Disables the internal anti aliasing filter on Channel 0 1 Enables the internal anti aliasing filter on Channel 0 o AA FILT EN Disables the internal anti aliasing filter on Channel 1 1 Enables the internal anti aliasing filter on Channel 1 AA FILT EN 2 0 Disables the internal anti aliasing filter on Channel 2 1 Enables the internal anti aliasing filter on Channel 2 AA FILT EN 3 0 Disables the internal anti aliasing filter on Channel 3 1 Enables the internal anti aliasing filter on Channel 3 ADC3 SW 3 0 No connection No connection No connection No connection AIN4 No connection No connection No connection No connection AIN7 No connection 2 o o oj o o o j o o eo ojo jo 25 25 25 25 o o o p m 2 o o 2 2 o o 2 ogpm o 2 oj j 2 o 2 o 2 o pe No connection Rev 0 Page 89 of 112 ADV7188 Address Register Bit Description Comments Notes
89. E 013 7 4 105 0x69 VBI DATA P11 VDP LINE 014 7 4 106 Ox6A VBI DATA P12 N10 VDP LINE 015 7 4 107 Ox6B VBI DATA P13 N11 VDP LINE 016 7 4 108 Ox6C VBI DATA P14 N12 VDP LINE 017 7 4 109 0x6D VBI_DATA_P15_N13 VDP_LINE_018 7 4 110 Ox6E VBI_DATA_P16_N14 VDP_LINE_019 7 4 111 Ox6F VBI DATA P17 N15 VDP LINE 01A 7 4 112 0x70 Rev 0 Page 50 of 112 ADV7188 Address Signal Name Register Location Dec Hex VBI_DATA_P18_N16 VDP_LINE_01B 7 4 113 0x71 VBI DATA P19 N17 VDP LINE 01C 7 4 114 0x72 VBI DATA P20 N18 VDP LINE 01D 7 4 115 0x73 VBI DATA P21 N19 VDP LINE O1E 7 4 116 0x74 VBI DATA P22 N20 VDP LINE O1F 7 4 117 0x75 VBI DATA P23 N21 VDP LINE 020 7 4 118 0x76 VBI DATA P24 N22 VDP LINE 021 7 4 119 0x77 VBI DATA P318 VDP LINE OOE 3 0 100 0x64 VBI DATA P319 N286 VDP LINE OOF 3 0 101 0x65 VBI DATA P320 N287 VDP LINE 010 3 0 102 0x66 VBI DATA P321 N288 VDP LINE 011 3 0 103 0x67 VBI DATA P322 VDP LINE 012 3 0 104 0x68 VBI DATA P323 VDP LINE 013 3 0 105 0x69 VBI DATA P324 N272 VDP LINE 014 3 0 106 Ox6A VBI DATA P325 N273 VDP LINE 015 3 0 107 Ox6B VBI DATA P326 N274 VDP LINE 016 3 0 108 Ox6C VBI DATA P327 N275 VDP LINE 017 3 0 109 0x6D VBI_DATA_P328_N276 VDP LINE 018 3 0 110 Ox6E VBI DATA P329 N277 VDP LINE 019 3 0 111 Ox6F VBI DATA P330 N278 VDP LINE 01A 3 0 112 0x70 VBI DATA P331 N279 VDP LINE 01B 3 0 113 0x71 VBI_DATA_P332_N280 VDP_LINE_01C 3 0 114 0x72 VBI_DATA_P333_N281 VDP LINE 01D 3 0 115 0x7
90. E_9 7 0 X X X X X X Decoded VPS PDC UTC data Read Only Ox8E VDP VPS PDC UTC 10 VPS PDC UTC BYTE 10 7 0 X X X X X X Decoded VPS PDC UTC data Read Only Ox8F VDP VPS PDC UTC 11 VPS PDC UTC BYTE 11 7 0 X X X X X X Decoded VPS PDC UTC data Read Only 0x90 VDP VPS PDC UTC 12 VPS PDC UTC BYTE 12 7 0 X X X X X X Decoded VPS PDC UTC data Read Only 0x92 VDP VITC DATA O0 VITC DATA O 7 0 X X xX X X X Decoded VITC data Read Only 0x93 VDP VITC DATA 1 VITC DATA 1 7 0 X X x X X X Decoded VITC data Read Only 0x94 VDP VITC DATA 2 VITC DATA 2 7 0 X X X X X X Decoded VITC data Read Only 0x95 VDP VITC DATA 3 VITC DATA 3 7 0 X X IX X X X Decoded VITC data Read Only 0x96 VDP VITC DATA 4 VITC DATA 4 7 0 X X xX X X X Decoded VITC data Read Only 0x97 VDP VITC DATA 5 VITC DATA 5 7 0 X X X X X X Decoded VITC data Read Only 0x98 VDP VITC DATA 6 VITC DATA 6 7 0 X X X X X X Decoded VITC data Read Only 0x99 VDP VITC DATA 7 VITC DATA 7 7 0 X X X X X X Decoded VITC data Read Only Ox9A VDP VITC DATA 8 VITC DATA 8 7 0 X X xX X X X Decoded VITC data Read Only Ox9B VDP VITC CALC CRC VITC_CRC 7 0 X X X X X X Decoded VITC CRC data Read Only Ox9C VDP OUTPUT SEL Reserved 0 0 WSS_CGMS_CB_CHANGE 0 Disable content based updating of The AVAILABLE bit shows the CGMS and WSS data availability of data only when 1 Enable content based updating of its content changes CGMS and WSS data GS
91. ILLTHR 2 0 bits allow the user to select a threshold for the color kill function The threshold applies only to QAM based NTSC and PAL or FM modulated SECAM video standards To enable the color kill function the CKE bit must be set For settings 000 001 010 and 011 chroma demodulation inside the ADV7188 may not work satisfactorily for poor input video signals Table 48 CKILLTHR Function Description CKILLTHR 2 0 SECAM NTSC PAL 000 No color kill Kill at lt 0 5 001 Kill at lt 5 Kill at lt 1 5 010 Kill at lt 7 Kill at lt 2 5 011 Kill at lt 8 Kill at lt 4 0 100 default Kill at lt 9 5 Kill at lt 8 5 101 Kill at lt 15 Kill at lt 16 0 110 Kill at lt 32 Kill at lt 32 0 111 Reserved for ADI internal use only do not select CHROMA TRANSIENT IMPROVEMENT CTI The signal bandwidth allocated for chroma is typically much smaller than that of luminance In the past this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance The uneven bandwidth however may lead to visual artifacts in sharp color transitions At the border of two bars of color both components luma and chroma change at the same time see Figure 22 ADV7188 Due to the higher bandwidth the signal transition of the luma component is usually much sharper than that of the chroma component The color edge is
92. IXEL DATA 12 12 CVBS Y LUMA LUMA on na LY P19 P10 DECIMATION AND FILTER RESAMPLE 5 MAX P9 PO DOWNSAMPLING FILTERS 20 12 SYNC RESAMPLE RECOVERS EXTRACT CONTROL HS 12 cr _ FAST BLANK m CHROMA OVERLAY u vs EH CHROMA CHROMA E DEMOD err ners FILTER RESAMPLE 2o AX eae CONTROL lt i z FIELD l tt 1 o i uL n soece 2 E COLORSPACE Cr 5 SYNCAND LK CONTROL CONVERSION Cb E 2 LLC1 FB i ADV7188 LLC2 1 E aea eu E LE A v E E ae EEE E Ai AA E AE NE NL LETE S PAEA DI LUI pu a 1 i i I I gt VBI DATA RECOVERY GLOBAL CONTROL Add SFL SCLK i i SDA SERIAL INTERFACE 4 gt MACROVISION STANDARD FREE RUN gt CONTROL AND VBI DATA 1 DETECTION AUTODETECTION OUTPUT CONTROL 7 EE a ALSB gt CONTROL i int OS AND DATA Suede ee lowe eae oe dcome ee cuncta ues cae E E Figure 1 Rev 0 Page4 of 112 ADV7188 ELECTRICAL CHARACTERISTICS At Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvppio 3 0 V to 3 6 V Pvpp 1 71 V to 1 89 V nominal input range 1 6 V Operating temperature range unless otherwise noted Table 1 Parameter Symbol Test Conditions Min Typ Max Unit STATIC PERFORMANCE 2 3 Resolution Each ADC N 12 Bits Integral Nonlinearity INL BSL at 54 MHz 1 5 42 5 8 LSB Differential Nonlinearity DNL BSL at 54 MHz 0 7 0 7 0 99 4 2 5 LSB DIGITAL INPUTS Input High Voltage Vin 2 V Input Low Voltage Vit 0 8 V Input Current lin
93. I_DATA_P333_N281 3 0 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set from line 333 PAL 281 NTSC to 1 for these bits to be VBL DATA P20 N18 3 0 ofololo Sets VBI standard to be decoded effective from line 20 PAL 18 NTSC 0x74 VDP_LINE_O1E VBI_DATA_P334_N282 3 0 0 0 010 Sets VBI standard to be decoded MAN_LINE_PGM must be set from line 334 PAL 282 NTSC to 1 for these bits to be VBI_DATA_P21_N19 3 0 0 o o o Sets VBI standard tobe decoded effective from line 21 PAL 19 NTSC 0x75 VDP LINE 01F VBI DATA P335 N283 3 0 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set from line 335 PAL 283 NTSC to 1 for these bits to be VBI_DATA_P22_N20 3 0 ofolofo Sets VBI standard tobe decoded ffective from line 22 PAL 20 NTSC 0x76 VDP_LINE_020 VBI_DATA_P336_N284 3 0 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be set from line 336 PAL 284 NTSC to 1 for these bits to be VBI_DATA_P23_N21 3 0 ofolofo Sets VBI standard tobe decoded amp ffective from line 23 PAL 21 NTSC 0x77 VDP LINE 021 VBI DATA P337 N285 3 0 0 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set from line 337 PAL 285 NTSC to 1 for these bits to be VBI_DATA_P24_N22 3 0 ofololo Sets VBI standard tobe decoded effective from line 24 PAL 22 NTSC 0x78 VDP_STATUS Read Only CC_AVL 0 Closed captioning not detected CC_CLEAR resets the CC_AVL 1 Closed captioning detected bit CC_E
94. L ZA IFA 3 0 3 5 4 0 4 5 5 0 5 5 6 FREQUENCY MHz AMPLITUDE dB 05478 047 eo Figure 43 PAL IF Compensation Filter Responses See Table 101 for programming details PC Interrupt System The ADV7188 has a comprehensive interrupt register set This map is located in the User Sub Map See Table 103 for details of the interrupt register map Figure 46 describes how to access this map Interrupt Request Output Operation When an interrupt event occurs the interrupt pin INTRQ goes low with a programmable duration given by INTRQ DUR SEL 1 0 INTRQ DURSEL 1 0 Interrupt Duration Select Address 0x40 7 6 User Sub Map Table 94 INTRQ DUR SEL INTRQ DURSEL 1 0 Description 00 default 3 XTAL periods 01 15 XTAL periods 10 63 XTAL periods 11 Active until cleared When the active until cleared interrupt duration is selected and the event that caused the interrupt is no longer in force the interrupt persists until it is masked or cleared For example if the ADV7188 loses lock an interrupt is generated and the INTRQ pin goes low If the ADV7188 returns to the locked state INTRQ continues to drive low until the SD LOCK bit is either masked or cleared Interrupt Drive Level The ADV7188 resets with open drain enabled and all interrupts masked off Therefore INTRQ is in a high impedance state after reset 01 or 10 has to be written to INTRQ OP SEL 1 0 fora logic le
95. L 15 Gemstar GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 The 16 bits of the GDECOL 15 0 form a collection of 16 individual line decode enable signals See Table 90 and Table 91 To retrieve closed caption data services on NTSC Line 21 GDECOL 11 must be set To retrieve closed caption data services on PAL Line 22 GDECOL 14 must be set The default value of GDECOL 15 0 is 0x0000 This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the odd field The user should only enable Gemstar slicing on lines where VBI data is expected GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 The decoded data from Gemstar compatible transmissions or closed caption transmission is inserted into the horizontal blanking period of the respective line of video A potential problem can arise if the retrieved data bytes have the value 0x00 or OxFF In an ITU R BT 656 compatible data stream those values are reserved and used only to form a fixed preamble The GDECAD bit allows the data to be inserted into the horizontal blanking period in two ways e Insert all data straight into the data stream even the reserved values of 0x00 and OxFF if they occur This may violate the output data format specification ITU R BT 1364 e Split all data into nibbles and insert the half bytes over double the number of cycles in a 4 bit format 0 default The d
96. L swinging burst lock status PAL swinging burst lock status has changed Reserved Not used Reserved Not used Ox4B Interrupt Clear 3 SD OP CHNG CLR 0 Do not clear Write Only 1 Clears SD OP CHNG Q bit SD V LOCK CHNG CLR Do not clear Clears SD_V_LOCK_CHNG_Q bit SD_H_LOCK_CHNG_CLR Do not clear Clears SD_H_LOCK_CHNG_Q bit SD_AD_CHNG_CLR 0 Do not clear 1 Clears SD_AD_CHNG_Q bit SCM_LOCK_CHNG_CLR 0 Do not clear Clears SCM_LOCK_CHNG_Q bit PAL_SW_LK_CHNG_CLR Do not clear Clears PAL_SW_LK_CHNG_Q bit Reserved Not used Reserved Not used Ox4C Interrupt Mask 2 SD OP CHNG MSKB 0 Masks SD_OP_CHNG_Q bit Read Write 1 Unmasks SD_OP_CHNG_Q bit SD_V_LOCK_CHNG_ MSKB Masks SD_V_LOCK_CHNG_Q bit Unmasks SD_V_LOCK_CHNG_Q bit SD_H_LOCK_CHNG_ MSKB Masks SD_H_LOCK_CHNG_Q bit Unmasks SD_H_LOCK_CHNG_Q bit SD AD CHNG MSKB 0 Masks SD AD CHNG Qbit 1 Unmasks SD AD CHNG Qbit SCM LOCK CHNG MSKB 0 Masks SCM_LOCK_CHNG_Q bit Unmasks SCM_LOCK_CHNG_Q bit PAL SW LK CHNG MSKB Masks PAL SW LK CHNG OQ bit Unmasks PAL SW LK CHNG QO bit Reserved Not used Reserved Not used Ox4E Interrupt Status 4 VDP CCAPD Q 0 Closed captioning not detected These bits can be cleared and Read Only 1 Closed captioning detected masked by Registers Ox4F and 0x50 respectively Reserved VDP_CGMS_WSS_CHNGD_Q See 0x9C Bit 4of User Sub Map to determine whether interrupt is issued for a change in detected data or for when data is detected regardless of content CGMS WSS d
97. LSBs are padded with 0s For example in 10 bit mode the output is Y 9 0 DEF Y 5 0 0 0 0 0 The value for Y is set by the DEF Y 5 0 bits A value of Ox0D produces a blue color in conjunction with the DEF C 7 0 default setting Register 0x0C has a default value of 0x36 DEF C 7 0 Default Value C Address 0x0D 7 0 The DEF C 7 0 register complements the DEF Y 5 0 value It defines the 4 MSBs of Cr and Cb values to be output if e TheDEF VAL AUTO EN bit is set to high and the ADV7188 cant lock to the input video automatic mode e DEF VAL EN bit is set to high forced output The data that is finally output from the ADV7188 for the chroma side is Cr 7 0 DEF C 7 4 0 0 0 0 Cb 7 0 DEF_C 3 0 0 0 0 0 In full 10 bit output mode two extra LSBs of value 00 are appended The values for Cr and Cb are set by the DEF_C 7 0 bits A value of 0x7C produces a blue color in conjunction with the DEF_Y 5 0 default setting Rev 0 Page 26 of 112 ADV7188 DEF_VAL_EN Default Value Enable Address 0x0C 0 This bit forces the use of the default values for Y Cr and Cb Refer to the descriptions for DEF_Y and DEF_C for additional information In this mode the decoder also outputs a stable 27 MHz clock HS and VS 0 default Outputs a colored screen determined by user programmable Y Cr and Cb values when the decoder free runs Free run mode is turned on and off by the DEF_VAL_AUTO_EN bit
98. N AND CONTROLS This section describes the IC based controls that affect e Insertion of AV codes into the data stream e Data blanking during the vertical blank interval VBI e The range of data values permitted in the output data stream e The relative delay of luma vs chroma signals Note that some of the decoded VBI data is being inserted during the horizontal blanking interval See the Gemstar Data Recovery section for more information BT656 4 ITU Standard BT R 656 4 Enable Address 0x04 7 The ITU has changed the position for toggling the V bit within the SAV EAV codes for NTSC between revisions 3 and 4 The BT656 4 standard bit allows the user to select an output mode that is compliant with either the previous or the new standard For more information review the standard at http www itu int Note that the standard change affects NTSC only and has no bearing on PAL 0 default The BT656 3 specification is used The V bit goes low at EAV of Lines 10 and 273 1 The BT656 4 specification is used The V bit goes low at EAV of Lines 20 and 283 SD_DUP_AV Duplicate AV Codes Address 0x03 0 Depending on the output interface width it may be necessary to duplicate the AV codes from the luma path into the chroma path In an 8 10 bit wide output interface Cb Y Cr Y interleaved data the AV codes are defined as FF 00 00 AV with AV being the transmitted word that contains information about H V F In this outpu
99. N6 AIN9 B on AIN4 AIN7 R on AINS AIN8 Composite amp SCART RGB RGB analog input options selectable via RGB IP SEL VID SEL 3 0 The VID SEL bits allow the user to select the input video standard Auto detect PAL BGHID NTSC without pedestal SECAM Auto detect PAL BGHID NTSC M with pedestal SECAM Auto detect PAL N NTSC M without pedestal SECAM Auto detect PAL N NTSC M with pedestal SECAM NTSCQ NTSC M PAL 60 NTSC 4 43 PAL BGHID PAL N BGHID without pedestal PAL M without pedestal PALM PAL combination N PAL combination N SECAM with pedestal 2 2 2 21 2 2 23 2 olololo 2 2 2 2lolololo 2 23 2 2 2 2 olol2 olo 2 liolo o 25 o 2 o 5 o 2 o o SECAM with pedestal 0x01 Video Selection Reserved Set to default ENVSPROC Disable VSYNC processor Enable VSYNC processor Reserved Set to default BETACAM Standard video input Betacam input enable ENHSPLL Disable HSYNC processor Enable HSYNC processor Reserved Set to default Rev 0 Page 77 of 112 ADV7188 Bit Address Re
100. OMB 3 BLOCK gt 12c 1 SEM d VIDEO DATA i 3 PROCESSING BLOCK Fsc RECOVERY 05478 012 Figure 12 Block Diagram of the Standard Definition Processor A block diagram of the ADV7188 s standard definition processor SDP is shown in Figure 12 The SDP block can handle standard definition video in CVBS YC and YPrPb formats It can be divided into a luminance and a chrominance path If the input video is of a composite type CVBS both processing paths are fed with the CVBS input SD LUMA PATH The input signal is processed by the following blocks Digital Fine Clamp This block uses a high precision algorithm to clamp the video signal Luma Filter Block This block contains a luma decimation filter YAA with a fixed response and some shaping filters YSH that have selectable responses Luma Gain Control The automatic gain control AGC can operate on a variety of different modes including gain based on the depth of the horizontal sync pulse peak white mode and fixed manual gain Luma Resample To correct for line length errors and dynamic line length changes the data is digitally resampled Luma 2D Comb The two dimensional comb filter provides YC separation AV Code Insertion At this point the decoded luma Y signal is merged with the retrieved chroma values AV codes as per ITU R BT 656 can be inserted SD CHROMA PATH The input signal is processed by the following blocks Digital Fine Clamp T
101. PAL configuration registers allow the user to customize comb filter operation depending on which video standard is detected by autodetection or selected by manual programming In addition to the bits listed in this section there are some other ADI internal controls contact ADI for more information NTSC Comb Filter Settings Used for NTSC M J CVBS inputs NSFSEL 1 0 Split Filter Selection NTSC Address 0x19 3 2 NSFSEL 1 0 selects how much of the overall signal bandwidth is fed to the combs A narrow bandwidth split filter gives better performance on diagonal lines but leaves more dot crawl in the final output image The opposite is true for a wide bandwidth split filter Table 50 NSFSEL Function ADV7188 CTAPSN 1 0 Chroma Comb Taps NTSC Address 0x38 7 6 Table 51 CTAPSN Function CTAPSN 1 0 Description 00 Do not use 01 NTSC chroma comb adapts 3 lines 3 taps to 2 lines 2 taps 10 default NTSC chroma comb adapts 5 lines 5 taps to 3 lines 3 taps 11 NTSC chroma comb adapts 5 lines 5 taps to 4 lines 4 taps NSFSEL 1 0 Description 00 default Narrow 01 Medium 10 Medium 11 Wide Table 52 CCMN Function CCMN 2 0 Chroma Comb Mode NTSC Address 0x38 5 3 See Table 52 YCMN 2 0 Luma Comb Mode NTSC Address 0x38 2 0 See Table 53 CCMN 2 0 Description Configuration 000 default Adaptive comb mode Adaptive 3 line chroma comb for CTAPSN 01 Adaptive 4 li
102. PDC GS VPS PDC GS VPS PDC GS VPS PDC 133 85 PDC UTC 1 R UTC BYTE 1 7 UTC BYTE 1 6 UTC BYTE 1 5 UTC BYTE 1 4 UTC BYTE 1 3 UTC BYTE 1 2 UTC BYTE 1 1 UTC BYTE 1 0 VDP GS VPS GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC 134 86 PDC UTC 2 R UTC BYTE 27 UTC BYTE 2 6 UTC BYTE 2 5 UTC BYTE 24 UTC BYTE 23 UTC BYTE 22 UTC BYTE 2 1 UTC BYTE 2 0 VDP GS VPS GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC GS VPS PDC 135 87 PDC UTC 3 R UTC BYTE 3 7 UTC BYTE 3 6 UTC BYTE 3 5 UTC BYTE 3 4 UTC BYTE 3 3 UTC BYTE 3 2 UTC BYTE 3 1 UTC BYTE 3 0 VDP VPS PDC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC 136 88 UTC 4 R BYTE 47 BYTE 4 6 BYTE 4 5 BYTE 44 BYTE 4 33 BYTE 42 BYTE 4 1 UTC BYTE 40 VDP VPS PDC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC 137 89 UTC 5 R BYTE 57 BYTE 5 6 BYTE 5 5 BYTE 5 4 BYTE 5 3 BYTE 5 2 BYTE 5 1 UTC BYTE 5 0 VDP VPS PDC VPS PDC UTC VPS PDC UTC VPS PDC UIC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC 138 8A UTC 6 R BYTE 67 BYTE 6 6 BYTE 6 5 BYTE 64 BYTE 6 3 BYTE 62 BYTE 6 1 UTC BYTE 6 0 Pes VDP VPS PDC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC UTC VPS PDC 139 8B UTC 7 R BYTE 77 BYTE 7 6 BYTE 7 5 BYTE 7 4 BYTE 7 3 BYTE 7 2 BYTE 7 1 UTC BYTE 7
103. PDC data from the decoder e Write 10 to I2C GS VPS PDC UTCT 1 0 0x9C User Sub Map to specify that PDC data has to be updated to I2C registers e Write high to the GS PDC VPS UTC CLEAR bit 0x78 User Sub Map to enable I C register updating e PolltheGS PDC VPS UTC AVL bit 0x78 User Sub Map going high to check the availability of the PDC packets e Read the data bytes from the PDC I C registers To read another line or packet of data the above steps have to be repeated To read a packet of CC CGMS or WSS data steps 1 through 3 only are required since they have dedicated registers VDP Content Based Data Update For certain standards like WSS CGMS Gemstar PDC UTC and VPS the information content in the signal transmitted remains the same over numerous lines and the user may want to be notified only when there is a change in the information content or loss of the information content The user needs to enable content based updating for the required standard through the GS VPS PDC UTC CB CHANGE and WSS CGMS CB CHANGE bits Thus the AVAILABLE bit shows the availability of that standard only when its content has changed Content based updating also applies to loss of data at the lines where some data was present before Thus for standards like VPS Gemstar CGMS and WSS if no data arrives in the next four lines programmed then the corresponding AVAILABLE bit in the VDP STATUS register is set high and t
104. ST NOISE VLD x 1 ST_NOISE 10 0 measurement is valid 0 ST_NOISE 10 0 measurement is invalid Reserved x x x x OxDF ST Noise Readback 2 ST NOISE 7 0 See ST NOISE 10 0 above X X X X X X X X Read Only OxE1 SD Offset Cb SD OFF CB 7 0 Adjusts the hue by 1 0 0 0 0 0 0 0 selecting the offset for the Cb channel OxE2 SD Offset Cr SD OFF CR 7 0 Adjusts the hue by 1 0 0 0 0 0 0 0 selecting the offset for the Cr channel OxE3 SD Saturation Cb SD SAT CB 7 0 Adjusts the saturation of 1 0 0 0 0 0 0 0 Chroma gain 0 dB the picture by affecting gain on the Cb channel 0xE4 SD Saturation Cr SD_SAT_CR 7 0 Adjusts the saturation of 1 0 0 0 0 0 0 0 Chroma gain 0 dB the picture by affecting gain on the Cr channel 0xE5 NTSC V Bit Begin NVBEGI4 0 How many lines after Icount 0 0 1 0 1 NTSC default BT 656 rollover to set V high NVBEGSIGN 0 Set to low when manual Rev 0 Page 86 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes programming 1 Not suitable for user programming NVBEGDELE Delay V bit going high by one 0 No delay line relative to NVBEG even field 1 Additional delay by 1 line NVBEGDELO Delay V bit going high byone 0 No delay line relative to NVBEG odd field 1 Addi
105. SYNC End Sign Address 0xE6 5 0 default Delays the end of VSYNC Set for user manual programming 1 Advances the end of VSYNC Not recommended for user programming NVEND 4 0 NTSC VSYNC End Address OxE6 4 0 The default value of NVEND is 00100 indicating the NTSC VSYNC end position For all NTSC PAL VSYNC timing controls both the V bit in the AV code and the VSYNC on the VS pin are modified NFTOGDELO NTSC Field Toggle Delay on Odd Field Address OxE7 7 0 default No delay 1 Delays the field toggle transition on an odd field by a line relative to NFTOG NFTOGDELE NTSC Field Toggle Delay on Even Field Address OxE7 6 0 No delay 1 default Delays the field toggle transition on an even field by a line relative to NFTOG ADVANCE TOGGLE OF FIELD BY NFTOG 4 0 NOT VALID FOR USER PROGRAMMING DELAY TOGGLE OF FIELD BY NFTOG 4 0 ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE 05478 031 TOGGLE Figure 31 NTSC FIELD Toggle NFTOGSIGN NTSC Field Toggle Sign Address OxE7 5 0 Delays the field transition Set for user manual programming 1 default Advances the field transition Not recommended for user programming NFTOG 4 0 NTSC Field Toggle Address OxE7 4 0 The default value of NFTOG is 00011 indicating the NTSC Field toggle position For all NTSC PAL field timing controls both the F bit in the AV code and the field signal on the FIELD
106. T MUXING SEE TABLES 8 AND 9 e By functional registers INSEL Using INSEL 3 0 ae nu SET INSEL 3 0 AND SET INSEL 3 0 TO simplifies the setup of the muxes and minimizes crosstalk SDM SEL 1 0 CONFIGURE ADV7188 bet h ish a ere ls Thi FOR REQUIRED MUXING TO DECODE VIDEO FORMAT etween channels by pre assigning the input channels This CONFIGURATION CVBS 0000 YC 0110 is referred to as ADI recommended input muxing VIDE 1001 SCART CVBS RGB 1111 e ByanI C manual override ADC SW MAN EN SET SDM_SEL 1 0 FOR S VIDEO CVBS AUTODETECT ADCO SW ADC1_SW ADC2_SW and ADC3 SW This is provided for applications with special requirements such ERE USE MANUAL INPUT MUXING as number combinations of signals which would not be ADC SW MAN EN ADCO SW served by the pre assigned input connections This is aaa ee ae referred to as manual input muxing Figure 7 Input Muxing Overview Refer to Figure 7 for an overview of the two methods of controlling input muxing Rev 0 Page 12 of 112 05478 007 ADI Recommended Input Muxing A maximum of 12 CVBS inputs can be connected and decoded by the ADV7188 As seen in Figure 5 this means the sources must be connected to adjacent pins on the IC This calls for a careful design of the PCB layout for example ground shielding between all signals routed through tracks that are physically close together SDM_SEL 1 0 S Video and CVBS Autodetect Mode Select Address 0x69 1 0
107. TAL INPUTS The digital inputs on the ADV7188 are designed to work with 3 3 V signals and are not tolerant of 5 V signals Extra compo nents are needed if 5 V logic signals are required to be applied to the decoder XTAL AND LOAD CAPACITOR VALUES SELECTION Figure 49 shows an example reference clock circuit for the ADV7188 Special care must be taken when using a crystal circuit to generate the reference clock for the ADV7188 Small variations in reference clock frequency may cause autodetection issues and impair the ADV7188 performance XTAL i 28 63636MHz Rado T Figure 49 Crystal Circuit C1 47pF 05478 Use the following guidelines to ensure correct operation e Usethe correct 28 63636 MHz frequency crystal Tolerance should be 50 ppm or better e User a parallel resonant crystal e Know the Cra for the crystal part selected The values of the C1 and C2 capacitors must be calculated using this Ci value To find C1 and C2 use the following formula C 2 Croad Cstray Cpg where C is usually 2 pF to 3 pF depending on board traces and Cj pin to ground capacitance is 4 pF for the ADV7188 Example Cia 30 pF C1 50 pF C2 50 pF in this case 47 pF is the nearest real life cap value to 50 pF Rev 0 Page 107 of 112 ADV7188 TYPICAL CIRCUIT CONNECTION An example of how to connect the ADV7188 video decoder is shown in Figure 50 For a detailed schematic diagram for the ADV7188 refer to
108. TC or VPS data has been detected VDP VITC Q Address Ox4E 6 User Sub Map read only 0 default VITC data has not been detected 1 VITC data has been detected Interrupt Status Clear Register Details It is not necessary to write 0 to these write only bits as they automatically reset when they are set self clearing VDP CCAPD CLR Address Ox4F 0 User Sub Map 1 Clears VDP CCAP Q bit VDP CGMS WSS CHNGD CLR Address 0x4F 2 User Sub Map 1 Clears VDP CGMS WSS CHNGD OQ bit VDP GS VPS PDC UTC CHNG CIR Address 0x4F 4 User Sub Map 1 Clears VDP GS VPS PDC UTC CHNG Q bit VDP VITC CLR Address Ox4F 6 User Sub Map 1 Clears VDP VITC Q bit Rev 0 Page 57 of 112 ADV7188 lC READBACK REGISTERS TELETEXT Because teletext is a high data rate standard the decoded bytes are available only as ancillary data However a TTX_AVL bit has been provided in I C so that the user can check whether the VDP has detected teletext Note that the TTXT_AVL bit is a plain status bit and does not use the protocol identified in the TPC Interface section TTXT AVI Teletext Detected Status bit Address 0x78 7 User Sub Map Read Only 0 Teletext was not detected 1 Teletext was detected WST Packet Decoding For WST ONLY the VDP decodes the Magazine and Row address of WST teletext packets and further decodes the packet s 8x4 hamming coded words This feature can be disabled using WST PKT DECOD DIS
109. TDFLD LEN FREE RUN ACT CVBS SD OP 50Hz GEMD INST HLOCK Analogue Control 19 13 Internal Ww XTAL TTL SEL 00000000 00 Analogue Clamp 20 14 Control RW CCLEN 00010010 12 Digital Clamp 21 15 Control 1 RW DCT 1 DCT O 0000xxxx 00 Shaping Filter 23 17 Control RW CSFM 2 CSFM 1 CSFM O YSFM 4 YSFM 3 YSFM 2 YSFM 1 YSFM O 00000001 01 Shaping Filter 24 18 Control 2 RW WYSFMOVR WYSFM 4 WYSFM 3 WYSFM 2 WYSFM 1 WYSFM O 10010011 93 25 19 Comb Filter Control RW NSFSEL 1 NSFSEL O PSFSEL 1 PSFSEL O 11110001 F1 29 1D ADI Control 2 RW TRI LLC EN28XTAL 00000xxx 00 39 27 Pixel Delay Control RW SWPC AUTO PDC EN CTA 2 CTA 1 CTA O LTA 1 LTA O 01011000 58 43 2B MiscGain Control RW CKE PW UPD 11100001 E1 44 2C AGC Mode Control RW LAGC 2 LAGC 1 LAGC O CAGC 1 CAGC O 10101110 AE Chroma Gain Control 45 2D 1 W CAGT 1 CAGT O CMG 11 CMG 10 CMG 9 CMG 8 11110100 FA Chroma Gain Control 46 2E 2 W CMG7 CMG 6 CMG 5 CMG 4 CMG 3 CMG 2 CMG 1 CMG 0 00000000 00 47 2F Luma Gain Control 1 W LAGT 1 LGAT O LMG 11 LMG 10 LMG 9 LMG 8 111 box FO 48 30 LumaGain Control 2 W LMG 7 LMG 6 LMG 5 LMGA LMG 3 LMG 2 LMG 1 LMG O XXXXXXXX 00 VSYNC Field Control 49 31 1 RW NEWAVMODE HVSTIM 0001001012 VSYNC Field Control 50 32 2 RW VSBHO VSBHE 01000001 41 VSYNC Field Control 51 33 33 RW VSEHO VSEHE 1000010084 HSYNC Position 52 34 Control 1 RW HSB 10 HSB 9 HSB 8 HSE 10 HSE 9 HSE 8 00000000 00 HSYNC Position 53 35 Control 2 R
110. TI enable 0 Disable CTI 1 Enable CTI CTI AB EN Enables the mixing of the 0 Disable CTI alpha blender transient improved chroma with the original 1 Enable CTI alpha blender signal CTI AB 1 0 Controls the behavior of the ojo Sharpest mixing alpha blend circuitry 011 Sharp mixing 1 0 Smooth 1 1 Smoothest Reserved 0 Set to default DNR EN Enable or bypass the DNR block 0 Bypass the DNR block 1 Enable the DNR block Reserved 1 1 Set to default Ox4E CTI DNR Control 2 CTI CTH 7 0 Specifies how big the 0 0 0 0 1 0 0 J0 Setto 0x04 for A V input set to amplitude step must be to be steepened by Ox0A for tuner input the CTI block 0x50 CTI DNR Control 4 DNR TH 7 0 Specifies the maximum edge 0 0 0 0 1 0 0 0 that is interpreted as noise and is therefore blanked 0x51 Lock Count CIL 2 0 Count into lock determines the 0 0 0 1 line of video number of lines the system must remain in 01011 2lines of video lock before showing a locked status 0 1 0 5 lines of video O 1 1 10 lines of video Rev 0 Page 84 of 112 ADV7188 Address Register Bit Description Bit Comments Notes 100 lines of video 500 lines of video 1000 lines of video 2 2 2 2 N 2 2 olo 2 2 o 2 o o 100000 lines of video COL 2 0 Count out of lock determines the number of lines the system must remain out of lock before showing a lost locked status 1line of video 2 lines of video 5 lines o
111. TSC WN 1 11101 NTSC WN 2 11110 NTSC WN 3 11111 Reserved Rev 0 Page 29 of 112 ADV7188 SET YSFM YSFM IN AUTO MODE YES i 00000 OR 00001 VIDEO QUALITY BAD GOOD USE YSFM SELECTED i FILTER REGARDLESS FOR GOOD AND BAD VIDEO AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB 1 0 SELECT WIDEBAND MEE ESTAS WYSFM 4 0 Figure 15 YSFM and WYSFM Control Flowchart WYSFM 4 0 Wide Band Y Shaping Filter Mode COMBINED V ANTA RESAMPLE n FILTERS NO 05478 015 Address 0x18 4 0 The WYSFM 4 0 bits allow the user to manually select a shaping filter for good quality video signals for example CVBS with in stable time base luma component of YPrPb and luma 2 component of YC The WYSFM bits are only active if the WYSFMOVR bit is set to 1 See the general discussion of the 5 A shaping filter settings in the Y Shaping Filter section a m Table 37 WYSFM Function T WYSFMI4 0 Description 00000 Do not use 60 e 00001 Do not use 00010 SVHS 1 E 2 4 6 8 10 12 00011 SVHS 2 FREQUENCY MHz 00100 SVHS 3 Figure 16 Y S VHS Combined Responses 00101 SVHS 4 COMBINED Y ANTIALIAS CCIR MODE SHAPING FILTER 00110 SVHS 5 av 00111 SVHS 6 01000 SVHS 7 E 01001 SVHS 8 01010 SVHS 9 ar 01011 SVHS 10 s 01100 SVHS 11 S _60 01101 SVHS 12 amp 01110 SVHS 13 X 80 01111 SVHS 14 10000 SVHS 15
112. Table 97 and Table 98 summarize the various functions that the ADV7188 pins can have in different modes of operation The ordering of components for example Cr vs Cb CHA B C can be changed Refer to the SWPC Swap Pixel Cr Cb Address 0x27 7 section Table 97 indicates the default positions for the Cr Cb components OF SEL 3 0 Output Format Selection Address 0x03 5 2 The modes in which the ADV7188 pixel port can be configured are under the control of OF SEL 3 0 See Table 98 for details The default LLC frequency output on the LLCI pin is approxi mately 27 MHz For modes that operate with a nominal data rate of 13 5 MHz 0001 0010 the clock frequency on the LLC1 pin stays at the higher rate of 27 MHz For information on outputting the nominal 13 5 MHz clock on the LLCI pin see the LLC PAD SEL 2 0 LLC1 Output Selection Address Ox8F 6 4 section Table 97 P19 P0 Output Input Pin Mapping SWPC Swap Pixel Cr Cb Address 0x27 7 0 default No swapping is allowed 1 The Cr and Cb values can be swapped LLC PAD SEL 2 0 LLC1 Output Selection Address Ox8F 6 4 The following I C write allows the user to select between LLC1 nominally at 27 MHz and LLC2 nominally at 13 5 MHz The LLC2 signal is useful for LLC2 compatible wide bus 16 20 bit output modes See the OF SEL 3 0 Output Format Selection Address 0x03 5 2 section for additional information The LLC2 signal and data on the data bus are sync
113. The SDM SEL bits decide on input routing and whether INSEL 3 0 is used to govern I P routing decisions The CVBS YC autodetection feature is enabled using SDM SEL 11 Table 8 SDM_SEL 1 0 SDM SEL 1 0 Mode Analogue Video Inputs 00 As per INSEL 3 0 As per INSEL 3 0 01 CVBS AIN11 10 YC Y AIN10 C AIN12 11 YC CVBS auto CVBS AIN11 Y AIN11 C AIN12 Table 9 Input Channel Switching Using INSEL 3 0 ADV7188 INSEL 3 0 Input Selection Address 0x00 3 0 The INSEL bits allow the user to select an input channel and the input format Depending on the PCB connections only a subset of the INSEL modes are valid The INSEL 3 0 not only switches the analog input muxing it also configures ADV7188 to process CVBS Comp S Video Y C or component YPbPr format ADI recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity Table 10 summarizes how the PCB layout should connect analog video signals to the ADV7188 It is strongly recommended to connect any unused analog input pins to AGND to act as a shield Connect inputs AIN7 to AIN11 to AGND when only six input channels are used This improves the quality of the sampling due to better isolation between the channels AIN12 is not under the control of INSEL 3 0 It can be routed to ADCO ADCI ADC2 only by manual muxing See Table 11 for details Description Description INSEL
114. The output drivers are enabled 1 The output drivers are three stated Rev 0 Page 19 of 112 ADV7188 Three State LLC Drivers TRI_LLC Address 0x1D 7 This bit allows the output drivers for the LLC1 and LLC2 pins of the ADV7188 to be three stated For more information on three state control refer to the Three State Output Drivers and the Timing Signals Output Enable sections Individual drive strength controls are provided via the DR STR XX bits 0 default The LLC pin drivers work according to the DR STR C 1 0 setting pin enabled 1 The LLC pin drivers are three stated Timing Signals Output Enable TIM OE Address 0x04 3 The TIM OE bit should be regarded as an addition to the TOD bit Setting it high forces the output drivers for HS VS and FIELD into the active that is driving state even if the TOD bit is set If set to low the HS VS and FIELD pins are three stated dependent on the TOD bit This functionality is useful if the decoder is to be used as a timing generator only This may be the case if only the timing signals are to be extracted from an incoming signal or if the part is in free run mode where for example a separate chip can output a company logo For more information on three state control refer to the Three State Output Drivers and the Three State LLC Drivers sections Individual drive strength controls are provided via the DR STR XX bits 0 default HS VS and FIELD are three s
115. U R BT 470 compliant color outputs color after VBI on even field in output beginning Line 283 NTSC 110 VBI ends 1 line later line 284 1 1 Color output beginning line 285 NVBIOCCM 1 0 NTSC VBI odd field color 010 Color output beginning line 20 Controls the position of first line that control 0l1 ITU R BT 470 compliant color outputs color after VBI on odd field in output beginning Line 21 NTSC 1 0 Color output beginning line 22 1 1 Color output beginning line 23 OxED FB STATUS Read Reserved XIX X x Only FB STATUS 3 0 Provides information about x FB RISE 1 there has been a Self clearing bit the status of the FB pin rising edge on FB pin since last IC FB STATUS 0 read FB STATUS 1 x FB FALL 1 there has been a Self clearing bit falling edge on FB pin since last C read FB STATUS 2 x FB STAT Instantaneous value of FB signal at time of C read FB STATUS 3 x FB HIGH Indicates that the FB Self clearing bit signal has gone high since the last PC read OxED FB CONTROL 1 FB MODE 1 0 Selects FB mode 0 0 Static switch mode full RGB or Write Only full CVBS data 0 1 Fixed alpha blending See MAN ALPHA VAL 6 0 1 0 Dynamic switching fast mux 1 1 Dynamic switching with edge enhancement 0 CVBS source Selects either CVBS or RGB to be O P 1 RGB source 0 FB pin active high 1 FB pin active low 0 0 0 1 OxEE FB_CONTROL 2 MAN_ALPHA_VALJ 6 0 Determines in what 0 0 0 0 0 0 0 proportion the video from the CVBS source
116. UDWs in any packet must be an integral number of 4 Padding is required at the end if necessary as set in ITU R BT 1364 See Table 81 e The2xbit determines whether the raw information retrieved from the video line was 2 or 4 bytes The state of the GDECAD bit affects whether the bytes are transmitted straight that is two bytes transmitted as two bytes or whether they are split into nibbles that is two bytes transmitted as four half bytes Padding bytes are then added where necessary integrity of the ancillary data packet It is calculated by summing up D 8 2 of DID SDID the data count byte and all UDWs and ignoring any overflow during the summation Since all data bytes that are used to calculate the checksum have their 2 LSBs set to 0 the CS 1 0 bits are also always 0 CS 8 describes the logic inversion of CS 8 The value CS 8 is included in the checksum entry of the data packet to ensure that the reserved values of 0x00 and OxFF do not occur Table 82 to Table 87 outline the possible data packages Gemstar 2x Format Half Byte Output Mode Half byte output mode is selected by setting CDECAD 0 full byte output mode is selected by setting CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Gemstar 1x Format Half byte output mode is selected by setting CDECAD 0 full byte output mode is selected by setting CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format
117. UT LLC 2 OUTPUTS P0 P19 VS HS FIELD Figure 2 PC Timing 05478 003 Figure 3 Pixel Port and Control Output Timing PO P19 HS VS FIELD SFL 05478 004 Figure 4 OE Timing Rev 0 Page 8 of 112 ABSOLUTE MAXIMUM RATINGS Table 6 Parameter Rating Avov to AGND 4V Dvpp to DGND 2 2V Pvop to AGND 2 2V Dvopio to DGND 4V Dvopio to AVDD 0 3 V to 40 3 V Pvpp to Dvop 0 3 V to 40 3 V Dvopio to Pvop 0 3V to 42V Dvopio to Dvop 0 3V to 2 V Avop to Pypp 0 3V to 2 V Avop to Dvop 0 3V to 2 V Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Inputs to AGND Maximum Junction Temperature T max Storage Temperature Range Infrared Reflow Soldering 20 sec 0 3V to Dvonio 0 3 V 0 3V to Dvonio 0 3 V AGND 0 3 V to Avpp 0 3 V 125 C 65 C to 150 C 260 C ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ADV7188 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only f
118. V Mode Address 0x31 4 0 EAV SAV codes are generated to suit ADI encoders No adjustments are possible 1 default Enables the manual position of the VSYNC Field and AV codes using Register 0x34 to Register 0x37 and Register OxE5 to Register OxEA Default register settings are CCIR656 compliant see Figure 27 for NTSC and Figure 32 for PAL For recommended manual user settings see Table 62 and Figure 28 for NTSC see Table 63 and Figure 33 for PAL HVSTIM Horizontal VS Timing Address 0x31 3 The HVSTIM bit allows the user to select where the VS signal is being asserted within a line of video Some interface circuitry may require VS to go low while HS is low 0 default The start of the line is relative to HSE 1 The start of the line is relative to HSB VSBHO VS Begin Horizontal Position Odd Address 0x32 7 This bit selects the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low 0 default The VS pin goes high at the middle of a line of video odd field 1 The VS pin changes state at the start of a line odd field VSBHE VS Begin Horizontal Position Even Address 0x32 6 This bit selects the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low 0 The VS pin goes
119. VEN_FIELD 0 Closed captioning decoded from odd field 1 Closed captioning decoded from even field CGMS WSS AVL 0 CGMS WSS not detected CGMS WSS CLEAR resets the 1 CGMS WSS detected CGMS_WSS_AVL bit Reserved 0 GS PDC VPS UTC AVL 0 VPS not detected GS PDC VPS UTC CLEAR 1 VPS detected resets the GS PDC VPS UTC AVL bit GS DATA TYPE 0 Gemstar 1x detected 1 Gemstar 2x detected VITC_AVL 0 VITC not detected VITC CLEAR resets the 1 VITC detected VITC_AVL bit TTXT AVL 0 Teletext not detected 1 Teletext detected 0x78 VDP STATUS CLEAR CC CLEAR 0 Do not re initialize the CCAP This is a self clearing bit Write Only registers 1 Re initializes the CCAP readback registers Reserved 0 CGMS_WSS_CLEAR 0 Do not re initialize the CGMS WSS This is a self clearing bit registers 1 Re initializes the CGMS WSS readback registers Reserved 0 GS_PDC_VPS_UTC_CLEAR 0 Do not re initialize the GS PDC VPS This is a self clearing bit UTC registers 1 Refreshes the GS PDC VPS UTC readback registers Reserved 0 VITC CLEAR 0 Do not re initialize the VITC registers This is a self clearing bit 1 Re initializes the VITC readback registers Reserved 0 0x79 VDP_CCAP_DATA_0 Read CCAP_BYTE_1 7 0 x x x X X X X x Decoded Byte 1 of CCAP Only Ox7A VDP CCAP DATA 1 Read CCAP BYTE 2 7 0 x x x X X X X X Decoded Byte 2 of CCAP Only Rev 0 Page 98 of 112 ADV7188
120. W HSB 7 HSB 6 HSB 5 HSB 4 HSB 3 HSB 2 HSB 1 HSB O 00000010 02 HSYNC Position 54 36 Control3 RW HSE 7 HSE 6 HSE 5 HSE 4 HSE 3 HSE 2 HSE 1 HSE O 00000000 00 55 37 Polarity RW PHS PVS PF PCLK 00000001 01 56 38 NTSC Comb Control RW CTAPSN 1 CTAPSN O CCMN 2 CCMN 1 CCMN O YCMN 2 YCMN 1 YCMN O 10000000 80 57 39 PALComb Control RW CTAPSP 1 CTAPSP O CCMP 2 CCMP 1 CCMP 0 YCMP 2 YCMP 1 YCMP O 11000000 CO 58 3A ADC Control RW PDN ADCO PDN_ADC1 PDN_ADC2 PDN ADC3 00010001 11 Manual Window 61 3D Control RW CKILLTHR 2 CKILLTHR 1 CKILLTHR O 01000011 43 65 41 Resample Control RW SFL_INV 00000001 01 72 48 Gemstar Ctrl 1 RW GDECEL 15 GDECEL 14 GDECEL 13 GDECEL 12 GDECEL 11 GDECEL 10 GDECEL 9 GDECEL 8 00000000 00 Rev 0 Page 75 of 112 ADV7188 Address Reset Dec Hex Register Name RW 7 6 5 4 3 2 1 0 Value Hex 73 49 Gemstar Ctrl 2 RW GDECEL 7 GDECEL 6 GDECEL 5 GDECEL A GDECEL 3 GDECEL 2 GDECEL 1 GDECEL O 00000000 00 74 4A Gemstar Ctrl 3 RW GDECOL 15 GDECOL 14 GDECOL 3 GDECOL 12 GDECOL 11 GDECOL 10 GDECOL 9 GDECOL 8 00000000 00 75 4B Gemstar Ctrl 4 RW GDECOL 7 GDECOL 6 GDECOL 5 GDECOL 4 GDECOL 3 GDECOL 2 GDECOL 1 GDECOL O 00000000 00 76 4C Gemstar Ctrl 5 RW GDECAD xxxx0000 00 77 4D CTIDNR Ctrl
121. WR EB RAB TM CU A Zh 187 WR ft Ee ANALOG DEVICES FEATURES Multiformat video decoder supports NTSC J M 4 43 PAL B D G H I M N SECAM Integrates four 54 MHz Noise Shaped Video 12 bit ADCs SCART fast blank support Clocked from a single 28 63636 MHz crystal Line locked clock compatible LLC Adaptive digital line length tracking ADLLT signal processing and enhanced FIFO management give mini TBC functionality 5 line adaptive comb filters Proprietary architecture for locking to weak noisy and unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated AGC with adaptive peak white mode Macrovision copy protection detection CTI chroma transient improvement DNR digital noise reduction Multiple programmable analog input formats CVBS composite video S Video Y C YPrPb component VESA MII SMPTE and Betacam 12 analog video input channels Integrated anti aliasing filters Programmable Interrupt request output pin Automatic NTSC PAL SECAM identification GENERAL DESCRIPTION The ADV7188 integrated video decoder automatically detects and converts a standard analog baseband television signal that is compatible with worldwide standards NTSC PAL and SECAM into 4 2 2 component video data compatible with 20 16 10 and 8 bit CCIR601 CCIR656 The advanced and highly flexible digital output interface
122. YES NO NVBEGDELO 1 0 i ADDITIONAL DELAY BY 1 LINE to NVBEG NVBEGDELE NTSC VSYNC Begin Delay on Even Field Address OxE5 6 Y 0 default No delay S 1 Delays VSYNC going high on an even field by a line relative to NVBEG i NVBEGSIGN NTSC VSYNC Begin Sign Address OxE5 5 ADDITIONAL DELAY BY 1 LINE 0 Delays the start of VSYNC Set for user manual programming ADVANCE BY 0 5 LINE t 1 default Advances the start of VSYNC Not recommended for user programming NVBEG 4 0 NTSC VSYNC Begin Address OxE5 4 0 The default value of NVBEG is 00101 indicating the NTSC VSYNC begin position For all NTSC PAL VSYNC timing controls both the V bit in the AV code and the VSYNC on the ADVANCE BY 0 5 LINE a VSYNC BEGIN Figure 29 NTSC VSYNC Begin VS pin are modified 05478 029 Rev 0 Page 44 of 112 ADV7188 ADVANCE END OF DELAY END OF VSYNC VSYNC BY NVEND 4 0 BY NVEND 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO i 05478 030 VSYNC END Figure 30 NTSC VSYNC End NVENDDELO NTSC VSYNC End Delay on Odd Field Address OxE6 7 0 default No delay 1 Delays VSYNC from going low on an odd field by a line relative to NVEND NVENDDELE NTSC VSYNC End Delay on Even Field Address OxE6 6 0 default No delay 1 Delays VSYNC from going low on an even field by a line relative to NVEND NVENDSIGN NTSC V
123. YNC End Sign Address OxE9 5 0 default Delays the end of VSYNC Set for user manual programming 1 Advances the end of VSYNC Not recommended for user programming Rev 0 Page 47 of 112 ADV7188 DELAY END OF VSYNC BY PVEND 4 0 ADVANCE END OF VSYNC BY PVEND 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO 1 0 0 1 i ADDITIONAL DELAY BY 1 LINE 0 0 1 ADVANCE BY 0 5 LINE ADVANCE BY 0 5 LINE 05478 035 VSYNC END Figure 35 PAL VSYNC End PVEND 4 0 PAL VSYNC End Address OxE9 4 0 The default value of PVEND is 10100 indicating the PAL VSYNC end position For all NTSC PAL VSYNC timing controls both the V bit in the AV code and the VSYNC on the VS pin are modified PFTOGDELO PAL Field Toggle Delay on Odd Field Address OxEA 7 0 default No delay 1 Delays the F toggle transition on an odd field by a line relative to PFTOG PFTOGDELE PAL Field Toggle Delay on Even Field Address OxEA 6 0 default No delay 1 default Delays the F toggle transition on an even field by a line relative to PFTOG PFTOGSIGN PAL Field Toggle Sign Address OxEA 5 0 Delays the field transition Set for user manual programming 1 default Advances the field transition Not recommended for user programming PFTOG PAL Field Toggle Address OxEA 4 0 The default value of PFTOG is 00011 indicating the PAL field toggle position For
124. _VPS_PDC_UTC_CB_CHANGE Disable content based updating of Gemstar VPS PDC and UTC data Enable content based updating of Gemstar VPS PDC and UTC data I2C GS VPS PDC UTC 1 0 0 0 Gemstar 1x 2x 0 1 VPS 1 0 PDC 1 1 UTC Standard expected to be decoded Rev 0 Page 99 of 112 ADV7188 C PROGRAMMING EXAMPLES Note These scripts are applicable to a system with the analog inputs arranged as shown in Figure 50 The input selection registers change in accordance with how the PCB is laid out MODE 1 CVBS INPUT Composite video on AIN10 All standards are supported through autodetect 10 bit 4 2 2 ITU R BT 656 output on P19 P10 Table 104 Mode 1 CVBS Input Register Address Register Value Notes 0x00 OxOE CVBS on AIN 10 0x03 0x00 10 bit enable 0x17 0x41 Set CSFM to SH1 0x19 OxFA Split filter control 0x1D 0x47 Enable 28 63636 MHz crystal mode Ox3A 0x17 Power down ADC1 ADC2 and ADC3 0x3B 0x71 Recommended setting Ox3D OxA2 MWE enable manual window color kill threshold to 2 Ox3E Ox6A BLM optimization Ox3F OxAO BGB optimization OxF3 0x01 Enable antialias filter on ADCO OxF9 0x03 Set maximum v lock range OxOE 0x80 Recommended setting 0x52 0x46 Recommended setting 0x54 0x00 Recommended setting Ox7F OxFF Recommended setting 0x81 0x30 Recommended setting 0x90 0xC9 Recommended setting 0x91 0x40 Recommended setting 0x92 0x3C Recommended sett
125. ability of PVDD Careful attention must be paid to regulation filtering and decoupling It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups AVDD DVDD DVDDIO and PVDD Some graphic controllers use substantially different levels of power when active during active picture time and when idle during horizontal and vertical sync periods This can result in a measurable change in the voltage supplied to the analog supply regulator which can in turn produce changes in the regulated analog supply voltage This can be mitigated by regulating the analog supply or at least PVDD from a different cleaner power source for example from a 12 V supply It is also recommended to use a single ground plane for the entire board This ground plane should have a space between the analog and digital sections of the PCB see Figure 48 ADV7188 ANALOG DIGITAL SECTION SECTION 05478 052 Figure 48 PCB Ground Layout Experience has repeatedly shown that the noise performance is the same or better with a single ground plane Using multiple ground planes can be detrimental because each separate ground plane is smaller and long ground loops can result In some cases using separate ground planes is unavoidable For those cases it is recommended to place a single ground plane under the ADV7188 The location ofthe split should be under the ADV7188 For this case it is even more important to place
126. ach time sliced data is available or triggering an interrupt request only when the sliced data has changed Selection is made via the WSS_CGMS_CB_CHANGE bit Gemstar PDC VPS or UTC The user can select between triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed Selection is made via the GS_VPS_PDC_UTC CB_CHANGE bit The sequence for the interrupt based reading of the VDP C data registers is the following for the CCAP standard 1 User unmasks CCAP interrupt mask bit 0x50 Bit 0 User Sub Map 1 CCAP data occurs on the incoming video VDP slices CCAP data and places it in the VDP readback registers 2 The VDP CCAP available bit goes high and the VDP module signals to the interrupt controller to stimulate an interrupt request for CCAP in this case 3 The user reads the interrupt status bits User Sub Map and sees that new CCAP data is available 0x4E Bit 0 User Sub Map 1 4 The user writes 1 to the CCAP interrupt clear bit 0x4F Bit 0 User Sub Map 1 in the Interrupt I C space this is a self clearing bit This clears the interrupt on the INTRQ pin but does NOT have an effect in the VDP I C area The user reads the CCAP data from the VDP IC area The user writes to a bit CC CLEAR in the VDP STATUS 0 register 0x78 Bit 0 User Sub Map 1 to signify the CCAP data has been read gt the VDP CCAP can be updated at the nex
127. al programming 1 Not suitable for user programming PVENDDELE Delay V bit going low by one 0 No delay line relative to PVEND even field 1 Additional delay by 1 line PVENDDELO Delay V bit going low by one 0 No delay line relative to PVEND odd field 1 Additional delay by 1 line OxEA PALF Bit Toggle PFTOG 4 0 How many lines after count 0 0 0 1 1 PAL default BT 656 rollover to toggle F signal PFTOGSIGN 0 Set to low when manual programming 1 Not suitable for user programming PFTOGDELE Delay F transition by one line 0 No delay relative to PFTOG even field 1 Additional delay by 1 line PFTOGDELO Delay F transition by one line 0 No delay relative to PFTOG odd field 1 Additional delay by 1 line OxEB V Blank Control 1 PVBIELCM 1 0 PAL VBI even field line 0 O VBI ends 1 line earlier line 335 Controls position of first active comb control 0 1 ITU R BT 470 compliant Line 336 o line after VBI on even field in 1 0 VBI ends 1 line later line 337 1 1 VBI ends 2 lines later line 338 PVBIOLCM 1 0 PAL VBI odd field line control ojo VBI ends 1 line earlier line 22 Controls position of first active comb oli ITU R BT 470 compliant Line 23 filtered line after VBI on odd field in PAL 1 0 VBI ends 1 line later line 24 tri VBI ends 2 lines later line 25 Rev 0 Page 87 of 112 ADV7188
128. all NTSC PAL field timing controls the F bit in the AV code and the field signal on the FIELD DE pin are modified ADVANCE TOGGLE OF FIELD BY PTOG 4 0 NOT VALID FOR USER PROGRAMMING DELAY TOGGLE OF FIELD BY PFTOG 4 0 ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE 05478 036 TOGGLE Figure 36 PAL F Toggle SYNC PROCESSING The ADV7188 has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video If desired the blocks can be disabled via the following two I C bits ENHSPLL Enable HSYNC Processor Address 0x01 6 The HSYNC processor is designed to filter incoming HSYNCs that have been corrupted by noise providing improved per formance for video signals with stable time bases but poor SNR 0 Disables the HSYNC processor 1 default Enables the HSYNC processor Rev 0 Page 48 of 112 ADV7188 ENVSPROC Enable VSYNC Processor Address 0x01 3 This block provides extra filtering of the detected VSYNCs to give improved vertical lock 0 Disables the VSYNC processor 1 default Enables the VSYNC processor VBI DATA DECODE There are two VBI data slicers on the ADV7188 The first is called is called the VBI data processor VDP and the second is called VBI System 2 The VDP can slice both low bandwidth standards and high bandwidth standards such as Teletext VBI System 2 can slice low
129. am Rev 0 Page 96 of 112 ADV7188 User Sub Map Address Register Bit Description Comments Enable insertion of VBI decoded data into ancillary 656 stream 0x63 VDP_ADF_Config_2 ADF SDID 5 0 User specified SDID sent in the ancillary data stream with VDP decoded data Reserved DUPLICATE ADF Ancillary data packet is spread across the Y and C data streams Ancillary data packet is duplicated on the Y and C data streams 0x64 VDP LINE OOE VBI DATA P318 3 0 Sets VBI standard to be decoded from line 318 PAL NTSC N A Reserved MAN LINE PGM Decode default standards on the lines indicated in Table 64 Manually program the VBI standard If set to 1 all VBI DATA Px Ny to be decoded on each line See bits must set as desired Table 65 0x65 VDP_LINE_OOF VBI DATA P319 N286 Sets VBI standard to be decoded PGM must be set from line 319 PAL 286 NTSC e bits to be VBI DATA P6 N23 3 0 Sets VBI standard to be decoded from line 6 PAL 23 NTSC 0x66 VDP LINE 010 VBI DATA P320 N287 Sets VBI standard to be decoded PGM must be set from line 320 PAL 287 NTSC e bits to be VBI DATA P7 N24 3 0 Sets VBI standard to be decoded from line 7 PAL 24 NTSC 0x67 VDP LINE 011 VBI DATA P321 N288 Sets VBI standard to be decoded PGM must
130. and the RGB source are blended FB CSC MAN 0 Automatic configuration of the CSC is used to convert RGB portion of CSC for SCART support SCART signal to YCrCb 1 Enable manual programming of CSC OxEF FB CONTROL 3 FB EDGE SHAPE 2 0 0 0 0 Improves picture transition for high 0lol1 speed fast blank switching 0 1 0 0 1 1 1 0 0 CNTR ENABLE 0 Contrast reduction mode disabled Rev 0 Page 88 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes FB signal interpreted as Bi level signal 1 Contrast reduction mode enabled FB signal interpreted as Tri level signal FB SP ADJUST 0 1 0 0 Adjusts FB timing in reference to Each LSB corresponds to 1 8 of a clock the sampling clock cycle OxFO FB CONTROL 4 FB DELAY 3 0 0 1 0 0 Delay on FB signal in 28 63636 MHz clock cycles Reserved 0 1 0 0 OxF1 FB CONTROL 5 RGB IP SEL 0 SD RGB input for FB on AIN7 AIN8 and AIN9 1 SD RGB input for FB on AIN4 AINS and AING Reserved 0 Set to Zero CNTR_MODE 1 0 Allows adjustment of 25 contrast level in the contrast reduction box 50 75 100 FB_LEVEL 1 0 Controls reference level for 0 0 CNTR ENABLE 0 FB threshold fast blank comparator 14V CNTR ENABLE 1 FB threshold 1 6V 0 1 CNTR ENABLE 0 FB threshold 1 6V CNTR_ENABLE 1 FB threshold 18V 1 0 CNTR ENABLE 0 FB threshold 18V CNTR ENABLE 1 FB threshold 2V 1 1 CNTR ENABL
131. are guaranteed over this range Guaranteed by characterization 3 Nominal sync depth is 300 mV at 100 sync depth range Rev 0 Page 6 of 112 TIMING SPECIFICATIONS ADV7188 At Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvppio 3 0 V to 3 6 V Pvpp 1 71 V to 1 89 V operating temperature range unless otherwise noted Table 3 Parameter Symbol Test Conditions Min Typ Max Unit SYSTEM CLOCK AND CRYSTAL Nominal Frequency 28 63636 MHz Frequency Stability 50 ppm PC PORT SCLK Frequency 400 kHz SCLK Min Pulse Width High t 0 6 Us SCLK Min Pulse Width Low t 1 3 us Hold Time Start Condition t3 0 6 us Setup Time Start Condition t4 0 6 us SDA Setup Time ts 100 ns SCLK and SDA Rise Time te 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition ts 0 6 us RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC1 Mark Space Ratio to tio 45 55 55 45 96 Duty Cycle LLC1 Rising to LLC2 Rising i 1 ns LLC1 Rising to LLC2 Falling to 1 ns DATA AND CONTROL OUTPUTS Data Output Transitional Time tis Negative clock edge to start of valid data 3 6 ns taccess tio t13 Data Output Transitional Time ta End of valid data to negative clock edge 24 ns thoro to t14 Propagation Delay to Hi Z tis 6 ns Max Output Enable Access Time tie 7 ns Min Output Enable Access Time ti 4 ns 1 Temperature range Tmn to Tmax 40 C to 85 C The min max specifica
132. ata is not changed not available CGMS WSS data is changed available Reserved VDP GS VPS PDC UTC CHNG Q See Ox9C Bit 5of User Sub Map to determine whether interrupt is issued for a change in detected data or for when data is detected regardless of content Gemstar PDC VPS UTC data is not changed available Gemstar PDC VPS UTC data is changed available Reserved VDP VITC Q VITC data is not available in the VDP VITC data is available in the VDP Note that interrupt in register Ox4E for the CCAP Gemstar CGMS WSS VPS PDC UTC and VITC data is using the VDP data slicer Rev 0 Page 95 of 112 ADV7188 User Sub Map Bit Address Register Bit Description 7 6 5 4 3 2 Comments Notes Reserved x Ox4F Interrupt Clear 4 VDP_CCAPD_CLR Do not clear Note that interrupt in register Write Only Clears VDP_CCAPD_Q Ox4E for the CCAP Gemstar CGMS WSS VPS PDC UTC and Reserved VITC data is using the VDP data VDP_CGMS_WSS_CHNGD_CLR 0 Do not clear slicer 1 Clears VDP CGMS WSS CHNGD Q Reserved x VDP GS VPS PDC UTC 0 Do not clear CHNG CLR 1 Clears VDP GS VPS PDC UTC CHNG O Reserved x VDP VITC CLR 0 Do not clear 1 Clears VDP VITC Q Reserved x 0x50 Interrupt Mask 4 VDP CCAPD MSKB Masks VDP CCAPD Q Note that inter
133. ata is split into half bytes and inserted 1 The data is output straight in 8 bit format Rev 0 Page 68 of 112 Table 91 PAL Line Enable Bits and Corresponding Line Numbering Line Number Line 3 0 ITU R BT 470 Enable Bit Comment 12 8 GDECOLJ 0 Not valid 13 9 GDECOL 1 Not valid 14 10 GDECOL 2 Not valid 15 11 GDECOL 3 Not valid 0 12 GDECOL 4 Not valid 1 13 GDECOL 5 Not valid 2 14 GDECOL 6 Not valid 3 15 GDECOL 7 Not valid 4 16 GDECOL 8 Not valid 5 17 GDECOL 9 Not valid 6 18 GDECOL 10 Not valid 7 19 GDECOL 11 Not valid 8 20 GDECOL 12 Not valid 9 21 GDECOL 13 Not valid 10 22 GDECOL 14 Closed caption 11 23 GDECOL 15 Not valid 12 321 8 GDECEL 0 Not valid 13 322 9 GDECEL 1 Not valid 14 323 10 GDECEL 2 Not valid 15 324 11 GDECEL 3 Not valid 0 325 12 GDECEL 4 Not valid 1 326 13 GDECEL 5 Not valid 2 327 14 GDECEL 6 Not valid 3 328 15 GDECEL 7 Not valid 4 329 16 GDECEL 8 Not valid 5 330 17 GDECEL 9 Not valid 6 331 18 GDECEL 10 Not valid 7 332 19 GDECEL 11 Not valid 8 333 20 GDECEL 12 Not valid 9 334 21 GDECEL 13 Not valid 10 335 22 GDECEL 14 Closed caption 11 336 23 GDECEL 15 Not valid Letterbox Detection Incoming video signals may conform to different aspect ratios 16 9 wide screen or 4 3 standard For certain transmissions in the wide screen format a digital sequence WSS is transmitted with the video signal If a WSS sequence is provided
134. be set from line 321 PAL 288 NTSC e bits to be VBI DATA P8 N25 3 0 Sets VBI standard to be decoded from line 8 PAL 25 NTSC 0x68 VDP LINE 012 VBI DATA P322 3 0 Sets VBI standard to be decoded PGM must be set from line 322 PAL NTSC N A e bits to be VBI DATA P9 3 0 Sets VBI standard to be decoded from line 9 PAL NTSC N A 0x69 VDP LINE 013 VBI DATA P323 3 0 Sets VBI standard to be decoded PGM must be set from line 323 PAL NTSC N A e bits to be VBI DATA P10 3 0 Sets VBI standard to be decoded from line 10 PAL NTSC N A Ox6A VDP_LINE_014 VBI_DATA_P324_N272 Sets VBI standard to be decoded _PGM must be set from line 324 PAL 272 NTSC e bits to be VBI_DATA_P11 3 0 Sets VBI standard to be decoded from line 11 PAL NTSC N A Ox6B VDP LINE 015 VBI DATA P325 N273 Sets VBI standard to be decoded PGM must be set from line 325 PAL 273 NTSC e bits to be VBI DATA P12 N10 3 0 Sets VBI standard to be decoded from line 12 PAL 10 NTSC 0x6C VDP_LINE_016 VBI_DATA_P326_N274 Sets VBI standard to be decoded PGM must be set from line 326 PAL 274 NTSC e bits to be VBI DATA P13 N11 3 0 Sets VBI standard to be decoded from line 13 PAL 11 NTSC 0x6D VDP_LINE_017 VBI_DATA_P327_N275 Sets VBI standard to be decoded PGM must be set from line 327 PAL 275 NTSC e bits to be VBI DATA P14 N12 3 0 Sets VBI standard to be decoded from line 14 PAL 12 NTSC Ox6E VDP LINE 018 VBI DATA P328 N276 Sets VBI standard to be deco
135. bles autodetection Subcarrier Frequency Lock Inversion The SFL INV bit controls the behavior of the PAL switch bit in the SFL GenLock Telegram data stream It was implemented to solve some compatibility issues with video encoders It solves two problems First the PAL switch bit is only meaningful in PAL Some encoders including Analog Devices encoders also look at the state of this bit in NTSC SELECT THE RAW LOCK SIGNAL SRLS TIME_WIN FREE_RUN Fgc LOCK TAKE Fgc LOCK INTO ACCOUNT FSCLE COUNTER INTO LOCK COUNTER OUT OF LOCK Second there was a design change in Analog Devices encoders from ADV717x to ADV719x The older versions used the SFL GenLock Telegram bit directly while the later ones invert the bit prior to using it The reason for this is that the inversion compensated for the 1 line delay of an SFL GenLock Telegram transmission As a result ADV717x encoders need the PAL switch bit in the SFL GenLock Telegram to be 1 for NTSC to work Also the ADV7190 ADV7191 ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC If the state of the PAL switch bit is wrong a 180 phase shift occurs In a decoder encoder back to back system in which SFL is used this bit must be set up properly for the specific encoder used SFL INV Address 0x41 6 0 default Makes the part SFL compatible with ADV7190 ADV7191 ADV7194 and ADV73xx encoders 1 Makes the part SFL compatible with A
136. c lock 1 Makes the overall lock status dependent on the horizontal sync lock and Fsc lock VS Coast 1 0 Address 0xF9 3 2 These bits are used to set VS free run coast frequency Table 25 VS_COAST 1 0 function ADV7188 Table 27 COL Function COL 2 0 Description 000 1 001 2 010 5 011 10 100 default 100 101 500 110 1000 111 100000 VS_COAST 1 0 Description 00 default 01 10 11 Auto coast Mode follows VS frequency from last video input Forces 50 Hz coast Mode Forces 60 Hz coast Mode Reserved CIL 2 0 Count Into Lock Address 0x51 2 0 CIL 2 0 determines the number of consecutive lines for which the into lock condition must be true before the system switches into the locked state and reports this via STATUS 1 1 0 It counts the value in lines of video Table 26 CIL Function CIL 2 0 Description 000 1 001 2 010 5 011 10 100 default 100 101 500 110 1000 111 100000 ST NOISE VLD HS Tip Noise Measurement Valid Address OxDE 3 read only 0 The ST NOISE 10 0 measurement is not valid 1 default The ST NOISE 10 0 measurement is valid ST NOISE 10 0 HS Tip Noise Measurement Address 0xDE 2 0 OxDF 7 0 The ST NOISE 10 0 measures over four fields a readback value of the average of the noise in the HSYNC tip ST NOISE VLD must be 1 for this measurement to be valid 1 bit of ST NOISE 10 0 1 ADC code 1 bit o
137. cket is 0x140 10 bit value e Secondary data identification word SDID which contains information about the video line from which data was retrieved whether the Gemstar transmission was of 1x or 2x format and whether it was retrieved from an even or odd field e Data count byte giving the number of user data words that follow e User data section e Optional padding to ensure that the length of the user data word section of a packet is a multiple of four bytes requirement as set in ITU R BT 1364 e Checksum byte Table 80 lists the values within a generic data packet that is output by the ADV7188 in 10 bit format SECONDARY DATA IDENTIFICATION 05478 045 USER DATA 4 OR 8 WORDS Figure 41 Gemstar and CCAP Embedded Data Packet Generic Table 80 Generic Data Output Packet Byte DI9 DI8 DI7 DI6 D 5 D 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 2X line 3 0 0 0 SDID 5 EP EP 0 0 0 0 DC 1 DC O 0 0 Data count DC 6 EP EP 0 0 word1 7 4 0 0 User data words 7 EP EP 0 0 word1 3 0 0 0 User data words 8 EP EP 0 0 word2 7 4 0 0 User data words 9 EP EP 0 0 word2 3 0 0 0 User data words 10 EP EP 0 0 word3 7 4 0 0 User data words 11 EP EP 0 0 word3 3 0 0 0 User data words 12 EP EP 0 0 word4 7 4 0 0 User data words 13
138. ction VDP TTXT TYPE MAN 1 0 Description 625 50 PAL 525 60 NTSC 00 default Teletext ITU Reserved BT 653 625 50 A 01 Teletext ITU Teletext ITU BT 653 BT 653 625 50 B 525 60 B WST 10 Teletext ITU Teletext ITU BT 653 BT 653 625 50 C Teletext ITU BT 653 625 50 525 60 C or EIA516 NABTS Teletext ITU BT 653 525 60 D Rev 0 Page 51 of 112 ADV7188 VDP Ancillary Data Output Reading the data back via I C may not be feasible for VBI data standards with high data rates for example teletext An alternative is to place the sliced data in a packet in the line blanking of the digital output CCIR656 stream This is available for all standards sliced by the VDP module When data has been sliced on a given line the corresponding ancillary data packet is placed immediately after the next EAV code that occurs at the output that is data sliced from multiple lines are not buffered up and then emitted in a burst Note that the line number on which the packet is placed differs from the line number on which the data was sliced due to the vertical delay through the comb filters The user can enable or disable the insertion of VDP decoded results into the 656 ancillary streams by using the ADF_ENABLE bit ADF_ENABLE Enable Ancillary Data Output Through 656 Stream Address 0x62 7 User Sub Map 0 default Disables insertion of VBI decoded data into ancillary 656 stream 1 Enables i
139. d SD OP 50HZ x SD field rate detect 0 SD 60 Hz detected 1 SD 50 Hz detected CVBS x Result of CVBS YC autodetection 0 Y G 1 CVBS FREE RUN ACT x 1 Free run mode active Blue screen output STD FLD LEN x 1 Field length standard Correct field length found INTERLACED x 1 Interlaced video detected Field sequence found Rev 0 Page 79 of 112 ADV7188 Bit Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes PAL_SW_LOCK x 1 Swinging burst detected Reliable swinging burst sequence 0x13 Analogue Control Reserved 0 0 Internal Write Only XTAL_TTL_SEL 0 Crystal used to derive 28 63636 MHz clock 1 External TTL level clock supplied Reserved 0 0 0 0 0 0x14 Analog Clamp Reserved 0 0 1 0 Set to default Control CCLEN Current clamp enable allows the user 0 Current sources switched off to switch off the current sources in the 1 Current sources enabled analog front Reserved 0 0 0 Set to default 0x15 Digital Clamp Reserved O0 x x x x Set to default Control 1 DCT 1 0 Digital clamp timing determines ojo Slow TC 1 sec the time constant of the digital fine clamp 0 1 Medium TC 0 5 sec circuitry 1 0 Fast TC 0 1 sec 1 1 TC dependent on video Reserved 0 Set to default 0x17 Shapi
140. d definition signals to enable SCART compatibility and overlay functionality This function is available when INSEL 3 0 is set appropriately see Table 9 Timing extraction is always performed by the ADV7188 on the CVBS signal However a combination of the CVBS and RGB inputs can be mixed and output under control of C registers and the fast blank FB pin Four basic modes are supported Static Switch Mode The FB pin is not used The timing is extracted from the CVBS signal and either the CVBS content or RGB content can be output under the control of CVBS RGB SEL This mode allows the selection of a full screen picture from either source Overlay is not possible in static switch mode Fixed Alpha Blending The FB pin is not used The timing is extracted from the CVBS signal and an alpha blended combination of the video from the CVBS and RGB sources is output This alpha blending is applied to the full screen The alpha blend factor is selected with the IC signal MAN ALPHA 6 0 Overlay is not possible in fixed alpha blending mode Rev 0 Page 15 of 112 ADV7188 Dynamic Switching Fast Mux Source selection is under the control of the fast blank FB pin This enables dynamic multiplexing between the CVBS and RGB sources With default settings when Logic 1 is applied to the FB pin the RGB source is selected when Logic 0 is applied to the FB pin the CVBS source is selected This mode is suitable for the overlay of subtitl
141. d three independent channels are needed to allow component signals YPrPb to be processed The clamping can be divided into two sections e Clamping before the ADC analog domain current sources e Clamping after the ADC digital domain digital processing block The ADCs can digitize an input signal only if it resides within their 1 6 V input voltage range An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so that the analog to digital conversion can take place It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the ADC range After digitization the digital fine clamp block corrects for any remaining variations in dc level Since the dc level of an input video signal refers directly to the brightness of the picture transmitted it is important to perform a fine clamp with high accuracy otherwise brightness variations may occur Further more dynamic changes in the dc level almost certainly lead to visually objectionable artifacts and must therefore be prohibited The clamping scheme must be able to acquire a newly connected video signal with a completely unknown dc level and it must maintain the dc level during normal operation To quickly acquire an unknown video si
142. data rate VBI standards only The VDP is capable of slicing multiple VBI data standards on SD video It decodes the VBI data on the incoming CVBS YC or YUV data The decoded results are available as ancillary data in output 656 data stream For low data rate VBI standards like CC WSS CGMS the user can read the decoded data bytes from FC registers The VBI data standards that can be decoded by the VDP are PAL Teletext System A or Cor D Teletext System B WST VPS Video Programming System VITC Vertical Interval Time Codes WSS Wide Screen Signaling ITU BT 653 ITU BT 653 ETSI EN 300 231 V 1 3 1 BT 1119 1 ETSI EN 300294 CCAP Closed Captioning NTSC Teletext System B and D ITU BT 653 Teletext System C NABTS ITU BT 653 EIA 516 VITC Vertical Interval Time Codes CGMS Copy Generation Management EIA J CPR 1204 IEC System 61880 GEMSTAR CCAP Closed Captioning EIA 608 The VBI data standard that the VDP decodes on a particular line of incoming video has been set by default as described in Table 64 This can be overridden manually and any VBI data can be decoded on any line The details of manual program ming are described in Table 65 and Table 66 VDP Default Configuration The VDP can decode different VBI data standards on a line to line basis The various standards supported by default on different lines of VBI are explained in Table 64 VDP Manual Configuration MAN LINE PGM Enable Manual Line Program
143. data word 9 Pad 0x200 These padding words may or may not be present i depending on ancillary n 3 1 0 0 0 0 0 0 0 0 0 data type User data n 2 1 0 0 0 0 0 0 0 0 0 word XX n 1 B8 Checksum 0 0 CS checksum word Rev 0 Page 53 of 112 ADV7188 Table 69 Ancillary Data in Byte Output Format Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 BO Description 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Ancillary data preamble 2 1 1 1 1 1 1 1 1 1 1 3 EP EP 0 I2C DID6 2 4 0 0 0 DID 4 EP EP I2C SDID7 2 5 0 0 0 SDID 5 EP EP 0 DC 4 0 0 0 Data count 6 EP EP padding 1 0 VBI DATA STDI 3 0 0 0 IDO user data word 1 7 EP EP 0 Line number 9 5 0 0 ID1 user data word 2 8 EP EP Even Field Line number 4 0 0 0 ID2 user data word 3 9 EP EP 0 0 0 0 VDP_TTXT_TYPE 1 0 0 0 ID3 user data word 4 10 VBI WORD 1 7 0 0 0 User data word 5 11 VBI WORD 2 7 0 0 0 User data word 6 12 VBI WORD 3 7 0 0 0 User data word 7 13 VBI WORD 4 7 0 0 0 User data word 8 14 VBI WORD 5 7 0 0 0 User data word 9 Pad 0x200 These padding words may or may not be present i i H x depending on ancillary n 3 1 0 0 0 0 0 0 0 0 0 data type User data n 2 1 0 0 0 0 0 0 0 0 0 word XX n 1 B8 Checksum 0 0 This mode does not fully comply with ITU R BT 1364 Structure of VBI Words in Ancillary Data St
144. ded PGM must be set from line 328 PAL 276 NTSC e bits to be VBI DATA P15 N13 3 0 Sets VBI standard to be decoded from line 15 PAL 13 NTSC Ox6F VDP LINE 019 VBI DATA P329 N277 Sets VBI standard to be decoded PGM must be set from line 329 PAL 277 NTSC e bits to be VBI DATA P16 N14 3 0 Sets VBI standard to be decoded from line 16 PAL 14 NTSC 0x70 VDP LINE 01A VBI DATA P330 N278 Sets VBI standard to be decoded PGM must be set from line 330 PAL 278 NTSC e bits to be VBI DATA P17 N15 3 0 Sets VBI standard to be decoded from line 17 PAL 15 NTSC 0x71 VDP LINE 01B VBI DATA P331 N279 Sets VBI standard to be decoded PGM must be set from line 331 PAL 279 NTSC to 1 for these bits to be Rev 0 Page 97 of 112 ADV7188 User Sub Map Bit Address Register Bit Description 7 6 5 3 2 1 0 Comments Notes VBI DATA P18 N16 3 0 0 0 0 0 Sets VBI standard to be decoded effective from line 18 PAL 16 NTSC 0x72 VDP LINE 01C VBI DATA P332 N280 3 0 0 0 0 0 Sets VBI standard to be decoded MAN LINE PGM must be set from line 332 PAL 280 NTSC to 1 for these bits to be VBL DATA P19 N17 3 0 ofololo Sets VBI standard tobe decoded effective from line 19 PAL 17 NTSC 0x73 VDP_LINE_01D VB
145. deo standard and process it accordingly The ADV7188 has a 5 line superadaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality without user intervention Video user controls such as brightness contrast saturation and hue are also available within the ADV7188 The ADV7188 implements a patented adaptive digital line length tracking ADLLT algorithm to track varying video line lengths from sources such as a VCR ADLLT enables the ADV7188 to track and decode poor quality video sources such as VCRs noisy sources from tuner outputs VCD players and camcorders The ADV7188 contains a chroma transient improvement CTI processor that sharpens the edge rate of chroma transitions resulting in sharper vertical transitions The ADV7188 can process a variety of VBI data services such as closed captioning CC wide screen signaling WSS copy generation management system CGMS Gemstar 1x 2x extended data service XDS and teletext The ADV7188 is fully Macrovision certified detection circuitry enables Type I IL and III protection levels to be identified and reported to the user The decoder is also fully robust to all Macrovision signal inputs FUNCTIONAL BLOCK DIAGRAM DATA PREPROCESSOR STANDARD DEFINITION PROCESSOR P
146. deo timing generator Free run mode generates stable video output with no I P VBI decode support for close captioning including XDS WSS CGMS Gemstar 1x 2x teletext VITC VPS Power down mode 2 wire serial MPU interface IC compatible 3 3 V analog 1 8 V digital core 3 3 V IO supply Industrial temperature grade 40 C to 85 C 80 lead LQFP Pb free package APPLICATIONS High end DVD recorders Video projectors HDD based PVRs DVDRs LCD TVs Set top boxes Professional video products AVR receiver AGC and clamp restore circuitry allow an input video signal peak to peak range of 0 5 V to 1 6 V Alternatively these can be bypassed for manual settings The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise accurate sampling and digital filtering The line locked clock output allows the output data rate timing signals and output clock signals to be synchronous asynchronous or line locked even with 5 line length variation The output control signals allow glueless interface connections in almost any application The ADV7188 modes are set up over a 2 wire serial bidirectional port C compatible SCART and overlay functionality are enabled by the ADV7188 s ability to simultaneously process CVBS and standard definition RGB signals Signal mixing is controlled by the fast blank pin The ADV7188 is fabricated in a 3 3 V CMOS process Its monolithic CMOS construction ensures greater functionalit
147. destal 1011 PAL M 1100 PAL combination N 1101 PAL combination N with pedestal 1110 SECAM 1111 SECAM with pedestal AD SEC525 EN Enable Autodetection of SECAM 525 Line Video Address 0x07 7 0 default Disables the autodetection of a 525 line system with a SECAM style FM modulated color component 1 Enables autodetection AD SECAM EN Enable Autodetection of SECAM Address 0x07 6 0 Disables the autodetection of SECAM 1 default Enables autodetection Rev 0 Page 23 of 112 ADV7188 AD_N443_EN Enable Autodetection of NTSC 443 Address 0x07 5 0 Disables the autodetection of NTSC style systems with a 4 43 MHz color subcarrier 1 default Enables autodetection AD_P60_EN Enable Autodetection of PAL 60 Address 0x07 4 0 Disables the autodetection of PAL systems with a 60 Hz field rate 1 default Enables autodetection AD_PALN_EN Enable Autodetection of PAL N Address 0x07 3 0 Disables the autodetection of the PAL N standard 1 default Enables autodetection AD_PALM_EN Enable Autodetection of PAL M Address 0x07 2 0 Disables the autodetection of PAL M 1 default Enables autodetection AD_NTSC_EN Enable Autodetection of NTSC Address 0x07 1 0 Disables the autodetection of standard NTSC 1 default Enables autodetection AD PAL EN Enable Autodetection of PAL Address 0x07 0 0 Disables the autodetection of standard PAL 1 default Ena
148. e Video Standard Selection to select the various standards for example with and without pedestal The automatic gain control AGC algorithms adjust the levels based on the setting of the BETACAM bit Rev 0 Page 33 of 112 ADV7188 Table 43 BETACAM Function BETACAM Description 0 default Assuming YPrPb is selected as input format Selecting PAL with pedestal selects MII Selecting PAL without pedestal selects SMPTE Selecting NTSC with pedestal selects MII Selecting NTSC without pedestal selects SMPTE 1 Assuming YPrPb is selected as input format Selecting PAL with pedestal selects BETACAM Selecting PAL without pedestal selects BETACAM variant Selecting NTSC with pedestal selects BETACAM Selecting NTSC without pedestal selects BETACAM For more information refer to the LAGC 2 0 Luma Automatic Gain Control Address 0x2C 6 4 section 0 Updates the gain once per video line 1 default Updates the gain once per field Chroma Gain CAGC 1 0 Chroma Automatic Gain Control Address 0x2C 1 0 These two bits select the basic mode of operation for automatic gain control in the chroma path Table 44 CAGC Function variant CAGC 1 0 Description 00 Manual fixed gain use CMG 11 0 PW_UPD Peak White Update Address 0x2B 0 01 Use luma gain for chroma i 10 default Automatic gain based on color burst The peak white and average video algorithms determine the 11 Freeze chro
149. ed Manual muxing is activated by setting the ADC SW MAN EN bit It affects only the analog switches in front of the ADCs This Rev 0 Page 14 of 112 ADV7188 SETADC SW MAN EN Manual Input Muxing Enable Address C4 7 ADCO sw 3 0 ADCO Mux Configuration Address 0xC3 3 0 ADCI sw 3 0 ADC1 Mux Configuration Address 0xC3 7 4 ADC2 sw 3 0 ADC2 Mux Configuration Address 0xC4 3 0 ADC3 sw 3 0 ADC3 Mux Configuration Address 0xF3 7 4 See Table 11 XTAL CLOCK INPUT PIN FUNCTIONALITY XTAL TTL SEL Address 0x13 2 The XTAL pad is normally part of the crystal oscillator circuit powered from a 1 8 V supply For optimal clock generation the slice level of the input buffer of this circuit is at approximately half the supply voltage This makes it incompatible with TLL level signals 0 default A crystal is used to generate the ADV7188 s clock 1 An external TTL level clock is supplied A different input buffer can be selected which slices at TTL compatible levels This inhibits operation of the crystal oscillator and therefore can only be used when a clock signal is applied 28 63636 MHZ CRYSTAL OPERATION EN28XTAL Address Ox1D 6 The ADV7188 can operate on two different base crystal frequencies Selecting one over the other can be desirable in systems in which board crosstalk between different components leads to undesirable interference between video signals It is recommended by ADI to use an XTAL of
150. egister allows the user to specify a timing difference between chroma and luma samples Note that there is a certain functionality overlap with the CTA 2 0 register For manual programming use the following defaults e CVBS input LTA 1 0 00 e YC input LTA 1 0 01 e YPrPb input LTA 1 0 01 Table 59 LTA Function RANGE Description 0 16 lt Y lt 235 16 lt C lt 240 1 default 1 lt Y lt 254 1 lt C lt 254 AUTO_PDC_EN Automatic Programmed Delay Control Address 0x27 6 Enabling the AUTO_PDC_EN function activates a function within the ADV7188 that automatically programs LTA 1 0 and CTA 2 0 to have the chroma and luma data match delays for all modes of operation 0 The ADV7188 uses the LTA 1 0 and CTA 2 0 values for delaying luma and chroma samples Refer to the LTA 1 0 Luma Timing Adjust Address 0x27 1 0 and the CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 sections 1 default The ADV7188 automatically programs the LTA and CTA values to have luma and chroma aligned at the output Manual registers LTA 1 0 and CTA 2 0 are not used LTA 1 0 Description 00 default No delay 01 Luma 1 clk 37 ns delayed 10 Luma 2 clk 74 ns early 11 Luma 1 clk 37 ns early CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 This register allows the user to specify a timing difference between chroma and luma samples This may be used to compensate for external filter group d
151. elay differences in the luma vs chroma path and to allow a different number of pipeline delays while processing the video downstream Review this functionality together with the LTA 1 0 register Rev 0 Page 40 of 112 ADV7188 The chroma can be delayed advanced only in chroma pixel SYNCHRONIZATION OUTPUT SIGNALS steps One chroma pixel step is equal to two luma pixels The HS Configuration programmable delay Mos after demodulation where one can The following controls allow the user to configure the behavior no longer delay by luma pixel steps of the HS output pin only For manual programming use the following defaults e Beginning of HS signal via HSB 10 0 e CVBS input CTA 2 0 011 e EndofHS signal via HSE 10 0 e YC input CTA 2 0 101 e Polarity of HS using PHS e YPrPb input CTA 2 0 110 The HS begin and HS end registers allow the user to freely position the HS output pin within the video line The values Table 60 CTA Function in HSB 10 0 and HSE 10 0 are measured in pixel units from CTA 2 0 Description the falling edge of HS Using both values the user can program 000 Not used both the position and length of the HS output signal 001 Chroma 2 chroma pixel early 010 Chroma 1 chroma pixel early HSB 10 0 HS Begin Address 0x34 6 4 Address 0x35 7 0 011 default No delay The position of this edge is controlled by placing a binary 100 Chroma 1 chroma pixel late number into HSB
152. eld Control 2 0x81 0x33 VSYNC Field Control 3 0x84 0x34 HSYNC Position 1 0x00 0x35 HSYNC Position 2 0x00 0x36 HSYNC Position 3 0x7D 0x37 POLARITY OxA1 OxE5 NTSV_V_BIT_BEG 0x41 OxE6 NTSC_V_BIT_END 0x84 OxE7 NTSC_F_BIT_TOG 0x06 AP FIELD 1 busieacqo xu ado 4 le I7 output 0 3 p VIDEO i NFTOG 4 0 0x3 FIELD 2 P ntl 1262 i 1263 264 265 266 267 268 269 270 BT 656 4 i REG 0x04 BIT 7 2 1 271 272 273 274 275 276 ee 283 gi 205 fi NFTOG 4 0 0x3 APPLIES IF NEMAVMODE 0 MUST BE MANUALLY SHIFTED IF NEWAVMODE 1 05478 027 Figure 27 NTSC Default BT 656 The Polarity of H V and F is Embedded in the Data Rev 0 Page 43 of 112 ADV7188 wastu quurrucinnnnnmrrrrruug wu uuu VIDEO i HS K li I I Y v OUTPUT vs amp OUTPUT p FIELD NVBEG 4 0 0x0 NVEND A4 0 0x3 OUTPUT NFTOG 4 0 0x5 OUTPUT DH VIDEO E FIELD gt OUTPUT ree ADVANCE BEGIN OF VSYNC BY NVBEG 4 0 FIELD 2 OUTPUT A 1 1 NVBEG 4 0 0x0 NVEND A4 0 0x3 05478 028 NFTOG 4 0 0x5 Figure 28 NTSC Typical VSYNC Field Positions Using Register Writes in Table 62 NVBEGDELO NTSC VSYNC Begin Delay on Odd Field Address OxE5 7 0 default No delay DELAY BEGIN OF VSYNC BY NVBEG 4 0 1 Delays VSYNC going high on an odd field by a line relative NOT VALID FOR USER PROGRAMMING ODD FIELD
153. enables performance video decoding and conversion in line locked clock based systems This makes the device ideally suited for a broad range of applications with diverse analog video character istics including tape based sources broadcast sources security surveillance cameras and professional systems The 12 bit accurate ADC provides professional quality video performance and is unmatched This allows true 10 bit resolution in the 10 bit output mode The 12 analog input channels accept standard composite S Video and YPrPb video signals in an extensive number of combinations Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Multiformat SDTV Video Decoder with Fast Switch Overlay Support ADV7188 Digital output formats 8 bit 10 bit 16 bit or 20 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and FIELD 0 5 V to 1 6 V analog signal input range Differential gain 0 496 typ Differential phase 0 4 typ Programmable video controls Peak white hue brightness saturation contrast Integrated on chip vi
154. er can boost or attenuate the mid region of the Y spectrum around 3 MHz The peaking filter can visually improve the picture by showing more definition on the picture details that contain frequency components around 3 MHz The default value 0x40 in this register passes through the luma data unaltered 0 dB response A lower value attenuates the signal and a higher value amplifies it A plot of the filter responses is shown in Figure 24 PEAKING GAIN USING BP FILTER FILTER RESPONSE dB 05478 024 FREQUENCY MHz Figure 24 Peaking Filter Responses DNR TH2 7 0 DNR Noise Threshold 2 Address OxFC 7 0 The DNR2 block is positioned after the luma peaking block so it affects the amplified luma signal It operates in the same way as the DNRI block but has an independent threshold control DNR_TH2 7 0 This value is an unsigned 8 bit number that determines the maximum edge that is still interpreted as noise and therefore blanked from the luma data Programming a large value into DNR_TH2 7 0 causes the DNR block to interpret even large transients as noise and remove them As a result the effect on the video data is more visible Programming a small value causes only small transients to be seen as noise and removed Rev 0 Page 36 of 112 COMB FILTERS The comb filters of the ADV7188 have been greatly improved to automatically handle video of all types standards and levels of quality The NTSC and
155. erved 110 Reserved 111 Freeze gain ADV7188 NTSC Luma_Gain 1024 lt LMG 11 0 lt 4095 0 9078 3 63 2 1128 PAL Luma_Gain 1024 lt LMG 11 0 lt 4095 0 838 3 351 3 1222 If read back this register returns the current gain value Depending on the setting in the LAGC 2 0 bits this is one of the following values e Luma manual gain value LAGC 2 0 set to luma manual gain mode e Luma automatic gain value LAGC 2 0 set to any of the automatic modes Table 42 LG LMG Function LAGT 1 0 Luma Automatic Gain Timing Address 0x2F 7 6 The luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control Note that this register only has an effect if the LAGC 2 0 register is set to 001 010 011 or 100 automatic gain control modes If peak white AGC is enabled and active see the STATUS_1 7 0 Address 0x10 7 0 section the actual gain update speed is dictated by the peak white AGC loop and as a result the LAGT settings have no effect As soon as the part leaves peak white AGC LAGT becomes relevant again The update speed for the peak white algorithm can be customized by the use of internal parameters Contact ADI for more information Table 41 LAGT Function LG 11 0 LMG 11 0 Read Write Description LMG 11 0 X Write Manual gain for luma path LG 11 0 Read Actually used gain LAGT 1 0 Descri
156. es teletext or other material Typically the CVBS source carries the main picture and the RGB source has the overlay data Dynamic Switching with Edge Enhancement This provides the same functionality as the dynamic switching mode but with ADI proprietary edge enhancement algorithms that improve the visual appearance of transitions for signals from a wide variety of sources System Diagram A block diagram of the ADV7188 fast blanking configuration is shown in Figure 9 The CVBS signal is processed by the ADV7188 and converted to YPrPb The RGB signals are processed by a color space converter CSC and samples are converted to YPrPb Both sets of YPrPb signals are input to the sub pixel blender which can be configured to operate in any of the four modes outlined above The fast blank position resolver determines the time position of the FB to a very high accuracy lt 1 ns this position infor mation is then used by the sub pixel blender in dynamic switching modes This enables the ADV7188 to implement high performance multiplexing between the CVBS and RGB sources even when the RGB data source is completely asynchronous to the sampling crystal reference An anti aliasing filter is required on all four data channels R G B and CVBS The order of this filter is reduced as all of the The switched or blended data is output from the ADV7188 in the standard output formats see Table 98 FAST BLANK CONTROL FB_MODE 1 0 Addre
157. es 1 to 20 264 to 282 comb half lines PVBIOLCM 1 0 PAL VBI Odd Field Luma Comb Mode Address OxEB 3 2 These bits control the first combed line after VBI on PAL odd field luma comb 01 default BT470 compliant blank lines 624 to 22 311 to 335 comb half lines PVBIELCM 1 0 PAL VBI Even Field Luma Comb Mode Address OxEB 1 0 These bits control the first combed line after VBI on PAL even field luma comb 01 default BT470 compliant blank lines 624 to 22 311 to 335 comb half lines NVBIOCCM 1 0 NTSC VBI Odd Field Chroma Comb Mode Address OxEC 7 6 These bits control the first combed line after VBI on NTSC odd field chroma comb 01 default SMPTE170 compliant no color on lines 1 to 20 264 to 282 chroma present on half lines NVBIECCM 1 0 NTSC VBI Even Field Chroma Comb Mode Address OxEC 5 4 These bits control the first combed line after VBI on NTSC even field chroma comb 01 default SMPTE170 compliant no color on lines 1 to 20 264 to 282 chroma present on half lines PVBIOCCM 1 0 PAL VBI Odd Field Chroma Comb Mode Address OxEC 3 2 These bits control the first combed line after VBI on PAL odd field chroma comb 01 default BT470 compliant no color on lines 624 to 22 311 to 335 chroma present on half lines PVBIECCM 1 0 PAL VBI Even Field Chroma Comb Mode Address OxEC 1 0 These bits control the first combed line after VBI on PAL even field chroma co
158. etting OxOE 0x00 Recommended setting Rev 0 Page 105 of 112 ADV7188 PCB LAYOUT RECOMMENDATIONS The ADV7188 is a high precision high speed mixed signal device To achieve the maximum performance from the part it is important to have a well laid out PCB board The following is a guide for designing a board using the ADV7188 ANALOG INTERFACE INPUTS Care should be taken when routing the inputs on the PCB Track lengths should be kept to a minimum and 75 Q trace impedances should be used when possible Trace impedances other than 75 Q increase the chance of reflections POWER SUPPLY DECOUPLING It is recommended to decouple each power supply pin with 0 1 uF and 10 nF capacitors The fundamental idea is to have a decoupling capacitor within about 0 5 cm of each power pin Also avoid placing the capacitor on the opposite side of the PC board from the ADV7188 as doing so interposes resistive vias in the path The decoupling capacitors should be located between the power plane and the power pin Current should flow from the power plane to the capacitor to the power pin Do not make the power connection between the capacitor and the power pin Placing a via underneath the 100 nF capacitor pads down to the power plane is generally the best approach see Figure 47 VIA TO SUPPLY VIA TO GND 05478 051 Figure 47 Recommended Power Supply Decoupling It is particularly important to maintain low noise and good st
159. etween the ADV7188 and the system IC master controller Each slave device is recognized by a unique address The ADV7188 s I C port allows the user to set up and configure the decoder and to read back captured VBI data The ADV7188 has four possible slave addresses for both read and write operations depending on the logic level on the ALSB pin These four unique addresses are shown in Table 99 The ADV7188 s ALSB pin controls Bit 1 of the slave address By altering the ALSB it is possible to control two ADV7188s in an application without having a conflict with the same slave address The LSB Bit 0 sets either a read or write operation Logic 1 corresponds to a read operation Logic 0 corresponds to a write operation Table 99 IC Address ALSB R W Slave Address 0 0 0x40 0 1 0x41 1 0 0x42 1 1 0x43 To control the device on the bus a specific protocol must be followed First the master initiates a data transfer by establishing a start condition which is defined by a high to low transition on SDA while SCLK remains high This indicates that an address data stream follows All peripherals respond to the start condition and shift the next eight bits 7 bit address R W bit The bits are transferred from MSB down to LSB The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse this is known as an acknowledge bit All other devices withdraw from the bus at this
160. f ST_NOISE 10 0 1 6 V 4096 390 625 uV COLOR CONTROLS These registers allow the user to control the picture appearance including control of the active data in the event of video being lost These controls are independent of any other controls For instance brightness control is independent of picture clamping although both controls affect the signal s dc level CON 7 0 Contrast Adjust Address 0x08 7 0 This register allows the user to adjust the contrast of the picture Table 28 CON Function COL 2 0 Count Out of Lock Address 0x51 5 3 COL 2 0 determines the number of consecutive lines for which the out of lock condition must be true before the system switches into unlocked state and reports this via STATUS 0 1 0 It counts the value in lines of video CON 7 0 Description 0x80 default Gain on luma channel 1 0x00 Gain on luma channel 0 OxFF Gain on luma channel 2 SD SAT Cb 7 0 SD Saturation Cb Channel Address OxE3 7 0 This register allows the user to control the gain of the Cb channel only The user can adjust the saturation of the picture Table 29 SD SAT Cb Function SD SAT Cb 7 0 Description 0x80 default 0x00 OxFF Gain on Cb channel 1 Gain on Cb channel 0 Gain on Cb channel 2 Rev 0 Page 25 of 112 ADV7188 SD_SAT_Cr 7 0 SD Saturation Cr Channel Address OxEA 7 0 This register allows the user to control the gain of the Cr channel only
161. f the FB pins as shown in Table 16 FB Timing FB SP ADJUST 3 0 Address OxEF 7 4 The critical information extracted from the FB signal is the time at which it switches relative to the input video Due to small timing inequalities either on the IC or on the PCB it may be necessary to adjust the result by fractions of one clock cycle This is controlled by FB SP ADJUST 3 0 Each LSB of FB SP ADJUST 3 0 corresponds to 1 8 of an ADC clock cycle Increasing the value is equivalent to adding delay to the FB signal The reset value is chosen to give equalized channels when the ADV7188 internal anti aliasing filters are enabled and there is no unintentional delay on the PCB The default value of FB SP ADJUST 3 0 is 0100 Alignment of FB Signal FB DELAY 3 0 Address 0xF0 3 0 In the event of misalignment between the FB input signal and the other input signals CVBS RGB or unequalized delays in their processing it is possible to alter the delay of the FB signal in 28 63636 MHz clock cycles For a finer granularity delay of the FB signal refer to FB SP ADJUST 3 0 Address OxEF 7 4 above The default value of FB DELAY 3 0 is 0100 Color Space Converter Manual Adjust FB CSC MAN Address OxEE 7 As shown in Figure 9 the data from the CVBS source and the RGB source are both converted to YPbPr before being combined For the RGB source the color space converter CSC must be used to perform this conversion When SCART su
162. f video 10lines of video 100 lines of video 500 lines of video 1000 lines of video STolololo o o lolo lol loelslolalo 100000 lines of video SRLS Select raw lock signal Selects the determination of the lock status Over field with vertical info Line to line evaluation FSCLE Fsc lock enable Lock status set only by horizontal lock Lock status set by horizontal lock and subcarrier lock 0x69 Config 1 SDM SEL 1 0 INSEL selects Analog I P Muxing CVBS AIN11 S Video Y on AIN10 and C on AIN12 CVBS S Video autodetect CVBS on AIN11 Y on AIN11 Con AIN12 Reserved Ox8F Free Run Line Length 1 Reserved Set to default LLC_PAD_SEL 2 0 Enables manual selection of clock for LLC1 pin LLC1 nominal 27 MHz selected out on LLC1 pin LLC2 nominally 13 5 MHz selected out on LLC1 pin For 16 bit 4 2 2 out OF SEL 3 0 0010 Reserved Set to default 0x99 CCAP1 Read Only CCAP1 7 0 Closed caption data register CCAP1 7 contains parity bit for byte 0 Only for use with VBI System 2 Ox9A CCAP2 Read Only CCAP2 7 0 Closed caption data register CCAP2 7 contains parity bit for byte 0 Only for use with VBI System 2 Ox9B Letterbox 1 Read Only LB LCT 7 0 Letterbox data register Reports the number of black lines detected at the top of active video
163. fect video sources such as videocassette recorders with head switches The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm The raw sync information is sent to a line length measurement and prediction block The output of this block is then used to drive the digital resampling section to ensure that the ADV7188 outputs 720 active pixels per line The sync processing on the ADV7188 also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video e VSYNC Processor This block provides extra filtering of the detected VSYNCS to give improved vertical lock e HSYNC Processor The HSYNC processor is designed to filter incoming HSYNCS that have been corrupted by noise providing much improved performance for video signals with stable time base but poor SNR VBI DATA RECOVERY The ADV7188 can retrieve the following information from the input video e Wide screen signaling WSS e Copy generation management system CGMS e Closed caption CC e Macrovision protection presence e Gemstar compatible data slicing e Teletext The ADV7188 is also capable of automatically detecting the incoming video standard with respect to e Color subcarrier frequency e Field rate e Line rate The ADV7188 can configure itself to support PAL B G H I
164. fore reporting the number of lines actually found via the LB LCB 7 0 value The activity window for letterbox detection end of field starts in the middle of an active field Its end is programmable via LB EL 3 0 Detection at the Midrange Some transmissions of wide screen video include subtitles within the lower black box If the ADV7188 finds at least two black lines followed by some more nonblack video for example the subtitle followed by the remainder of the bottom black block it reports a midcount via LB LCM 7 0 If no subtitles are found LB LCM 7 0 reports the same number as LB LCB 7 0 There is a 2 field delay in the reporting of any line count parameters There is no letterbox detected bit Read the LB LCT 7 0 and LB LCB 7 0 register values to conclude whether or not the letterbox type video is present in software LB LCT 7 0 Letterbox Line Count Top Address 0x9B 7 0 LB LCM 7 0 Letterbox Line Count Mid Address 0x9C 7 0 LB LCB 7 0 Letterbox Line Count Bottom Address 0x9D 7 0 Table 92 LB LCx Access Information Signal Name Address LB LCT 7 0 Ox9B LB LCM 7 0 Ox9C LB_LCB 7 0 0x9D 1 This register is a readback register default value does not apply Rev 0 Page 69 of 112 ADV7188 LB TH 4 0 Letterbox Threshold Control Address 0xDC 4 0 Table 93 LB_TH Function LB TH 4 0 Description 01100 Default threshold for detection of black lines default 01101 to I
165. frequency 28 63636 MHz to clock the ADV7188 The programming examples at the end of this datasheet presume 28 63636 MHz crystal is used 0 default XTAL frequency is 27 MHz 1 XTAL frequency is 28 63636 MHz ANTIALIASING FILTERS The ADV7188 has optional antialiasing filters on each of the four input channels The filters are designed for SD video with approximately 6 MHz bandwidth A plot of the filter response is shown in Figure 8 The filters can be individually enabled via I C under the control of AA FILT EN 3 0 AA FILT EN 0 Address OxF3 0 0 default The filter on channel 0 is disabled 1 The filter on channel 0 is enabled AA FILT EN 1 Address OxF3 1 0 default The filter on channel 1 is disabled 1 The filter on channel 1 is enabled AA FILT EN 2 Address OxF3 2 0 default The filter on channel 2 is disabled 1 The filter on channel 2 is enabled AA FILT EN 3 Address OxF3 3 0 default The filter on channel 3 is disabled 1 The filter on channel 3 is enabled RESPONSE OF AA FILTER WITH CALIBRATED CAPACITORS ATTENUATION dB b o eo 05478 008 1M 10M 100M 1G FREQUENCY Hz Figure 8 Frequency Response of Internal ADV7188 Antialiasing Filters SCART AND FAST BLANKING The ADV7188 can support simultaneous processing of CVBS and RGB standar
166. gister Bit Description 7 6 5 4 3 2 0 Comments Notes 0x03 Output Control SD_DUP_AV Duplicates the AV codes from 0 AV codes to suit 8 bit interleaved the luma into the chroma path data output 1 AV codes duplicated for 16 bit interfaces Reserved Set as default OF_SEL 3 0 Allows the user to choose from 0 0 0 0 Reserved aset of output formats 0ololol1 Reserved 0 0 1 0 16 bit LLC1 4 2 2 o rom n 8 bit LLC1 4 2 2 ITU R BT 656 0 1 0 0 Not used 0 1 0 1 Not used 0 1 1 0 Not used 0 1 1 1 Not used 1 0 0 0 Not used 1 0 0 1 Not used 1 0 1 0 Not used 1 0 1 1 Not used 1 1 0 0 Not used 1 1 0 1 Not used 1 1 1 0 Not used 1 1 1 1 Not used TOD Three state output drivers This bit 0 Output pins enabled See also TIM OE and TRI LLC allows the user to three state the output 1 Drivers three stated drivers P 19 0 HS VS FIELD and SFL VBI EN Allows VBI data Lines 1 to 21 tobe 0 All lines filtered and scaled passed through with only a minimum 1 Only active video region filtered amount of filtering performed 0x04 Extended Output RANGE Allows the user to select the range of 0 16 lt Y lt 235 16 lt C lt 240 ITU R BT 656 Control output values Can be BT656 compliant or T 1 lt Y lt 254 1 lt C lt 254 Extended range can fill the whole accessible number range EN_SFL_PIN SFL output is disabled SFL output enables connecting SFL information output on the SFL encoder and decoder directly pin BL_C_VBI Blank chroma during VBI If
167. gnal the large current clamps may be activated It is assumed that the amplitude of the video signal at this point is of a nominal value Control of the coarse and fine current clamp parameters is automatically performed by the decoder Standard definition video signals may have excessive noise on them In particular CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise 2100 mV A voltage clamp would be unsuitable for this type of video signal Instead the ADV7188 uses a set of four current sources that can cause coarse 20 5 mA and fine 0 1 mA currents to flow into and away from the high impedance node that carries the video signal see Figure 14 The following sections describe the I C signals that can be used to influence the behavior of the clamping block on the ADV7188 CCLEN Current Clamp Enable Address 0x14 4 The current clamp enable bit allows the user to switch off the current sources in the analog front end altogether This may be useful if the incoming analog video signal is clamped externally 0 The current sources are switched off 1 default The current sources are enabled Rev 0 Page 27 of 112 ADV7188 FINE COARSE CURRENT CURRENT SOURCES SOURCES ANALOG VIDEO INPUT DATA PRE SDP processor j imi DIGITAL DPP 05478 014 Figure 14 Clamping Overview DCT 1 0 Digital Clamp Timing Address 0x15 6 5
168. he HS with respect to an internal counter that is reset to 0 immediately pulse ends 0 pixels after falling edge of HS Rev 0 Page 41 of 112 ADV7188 For example 1 To shift the HS toward active video by 20 LLC1s add 20 LLCIs to both HSB and HSE that is HSB 10 0 00000010110 HSE 10 0 00000010100 2 To shift the HS away from active video by 20 LLC1s add 1696 LLC1s to both HSB and HSE for NTSC that is HSB 10 0 11010100010 HSE 10 0 11010100000 1696 is derived from the NTSC total number of pixels 1716 To move 20 LLC1s away from active video is equal to subtracting 20 from 1716 and adding the result in binary to both HSB 10 0 and HSE 10 0 PHS Polarity HS Address 0x37 7 The polarity of the HS pin can be inverted using the PHS bit 0 default HS is active high 1 HS is active low VS and FIELD Configuration The following controls allow the user to configure the behavior of the VS and FIELD output pins and to generate embedded AV codes e ADV encoder compatible signals via NEWAVMODE e PVS PF e HVSTIM e VSBHO VSBHE e VSEHO VSEHE e For NTSC control o NVBEGDELO NVBEGDELE NVBEGSIGN NVBEG 4 0 o NVENDDELO NVENDDELE NVENDSIGN NVEND 4 0 o NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG 4 0 e For PAL control o PVBEGDELO PVBEGDELE PVBEGSIGN PVBEG 4 0 o PVENDDELO PVENDDELE PVENDSIGN PVEND 4 0 o PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG 4 0 NEWAVMODE New A
169. he content in the C registers for that standard is set to zero The user has to write high to the corresponding CLEAR bit so that when a valid line is decoded after some time the decoded results are available into the I C registers with the AVAILABLE status bit set high If content based updating is enabled the AVAILABLE bit is set high assuming the CLEAR bit was written in the following cases e The data contents change e Data was being decoded and four lines with no data have been detected e No data was being decoded and new data is now being decoded GS VPS PDC UTC CB CHANGE Enable Content Based Updating for Gemstar VPS PDC UTC Address 0x9C 5 User Sub Map 0 Disables content based updating 1 default Enables content based updating WSS_CGMS_CB_CHANGE Enable Content Based Updating for WSS CGMS Address 0x9C 4 User Sub Map 0 Disables content based updating 1 default Enables content based updating VDP Interrupt Based Reading of VDP PC registers Some VDP status bits are also linked to the interrupt request controller so that the user does not have to poll the AVAILABLE status bit The user can configure the video decoder to trigger an interrupt request on the INTRQ pin in response to the valid data available in I C registers This function is available for the following data types Rev 0 Page 56 of 112 ADV7188 CGMS or WSS The user can select between triggering an interrupt request e
170. her than 00000 or 00001 the chosen filter is applied to all video regardless of its quality e In automatic selection mode the notch filters are used only for bad quality video signals For all other video signals wideband filters are used see Table 36 ADV7188 WYSFMOVR Wideband Y Shaping Filter Override Address 0x18 7 Setting the WYSFMOVR bit enables the use of the WYSFM 4 0 settings for good quality video signals For more information refer to the general discussion of the luma shaping filters in the Y Shaping Filter section and the flowchart shown in Figure 15 0 The shaping filter for good quality video signals is selected automatically 1 default Enables manual override via WYSFM 4 0 Table 36 YSFM Function YSFM 4 0 Description 00000 Automatic selection including a wide notch response PAL NTSC SECAM 00001 Automatic selection including a narrow notch default response PAL NTSC SECAM 00010 SVHS 1 00011 SVHS 2 00100 SVHS 3 00101 SVHS 4 00110 SVHS 5 00111 SVHS 6 01000 SVHS 7 01001 SVHS 8 01010 SVHS 9 01011 SVHS 10 01100 SVHS 11 01101 SVHS 12 01110 SVHS 13 01111 SVHS 14 10000 SVHS 15 10001 SVHS 16 10010 SVHS 17 10011 SVHS 18 CCIR 601 10100 PAL NN 1 10101 PAL NN 2 10110 PAL NN 3 10111 PAL WN 1 11000 PAL WN 2 11001 NTSC NN 1 11010 NTSCNN 2 11011 NTSC NN 3 11100 N
171. high at the middle of a line of video even field 1 default The VS pin changes state at the start of a line even field VSEHO VS End Horizontal Position Odd Address 0x33 7 This bit selects the position within a line at which the VS pin not the bit in the AV code becomes inactive Some follow on chips require the VS pin to change state only when HS is high low 0 The VS pin goes low inactive at the middle of a line of video odd field 1 default The VS pin changes state at the start of a line odd field Rev 0 Page 42 of 112 VSEHE VS End Horizontal Position Even Address 0x33 6 This bit selects the position within a line at which the VS pin not the bit in the AV code becomes inactive Some follow on chips require the VS pin to change state only when HS is high low 0 default The VS pin goes low inactive at the middle ofa line of video even field 1 The VS pin changes state at the start of a line even field Table 62 Recommended User Settings for NTSC See Figure 28 ADV7188 PVS Polarity VS Address 0x37 5 The polarity of the VS pin can be inverted using the PVS bit 0 default VS is active high 1 VS is active low PF Polarity FIELD Address 0x37 3 The polarity of the FIELD pin can be inverted using the PF bit 0 default FIELD is active high 1 FIELD is active low Register Register Name Write 0x31 VSYNC Field Control 1 Ox1A 0x32 VSYNC Fi
172. his block uses a high precision algorithm to clamp the video signal Chroma Demodulation This block uses a color subcarrier Fsc recovery unit to regenerate the color subcarrier for any modulated chroma scheme The demodulation block then performs an AM demodulation for PAL and NTSC and an FM demodulation for SECAM Chroma Filter Block This block contains a chroma decimation filter CAA with a fixed response and some shaping filters CSH that have selectable responses Gain Control Automatic gain control AGC can operate on several different modes including gain based on the color subcarrier s amplitude gain based on the depth of the horizontal sync pulse on the luma channel or fixed manual gain Chroma Resample The chroma data is digitally resampled to keep it perfectly aligned with the luma data The resampling is done to correct for static and dynamic line length errors of the incoming video signal Chroma 2D Comb The two dimensional 5 line superadaptive comb filter provides high quality YC separation in case the input signal is CVBS AV Code Insertion At this point the demodulated chroma Cr and Cb signal is merged with the retrieved luma values AV codes as per ITU R BT 656 can be inserted Rev 0 Page 22 of 112 SYNC PROCESSING The ADV7188 extracts syncs embedded in the video data stream There is currently no support for external HS VS inputs The sync extraction has been optimized to support imper
173. hronized By default the rising edge of LLC1 LLC2 is aligned with the Y data the falling edge occurs when the data bus holds C data The polarity of the clock and therefore the Y C assignments to the clock edges can be altered by using the Polarity LLC pin 000 default The output is nominally 27 MHz LLC on the LLCI pin 101 The output is nominally 13 5 MHz LLC on the LLCI pin Data Port Pins P 19 0 Processor Format and Mode 19 18 17 16 15 14 13 12 11 110 9 8 7 6 5 4 3 2 1 0 Video Out 8 Bit 4 2 2 YCrCb 7 0 OUT Video Out 10 Bit 4 2 2 YCrCb 9 0 OUT Video Out 16 Bit 4 2 2 Y 7 0 OUT CrCb 7 0 OUT Video Out 20 Bit 4 2 2 Y 9 0 OUT CrCb 9 0 OUT Table 98 Standard Definition Pixel Port Modes Pixel Port Pins P 19 0 P 19 10 P9 9 0 OF SEL 3 0 Format P 19 12 P 11 10 P 9 2 P 1 0 0000 10 Bit at LLC1 4 2 2 YCrCb 9 2 YCrCb 1 0 Three State Three State 0001 20 Bit at LLC2 4 2 2 Y 9 2 Y 1 0 CrCb 9 2 CrCb 1 0 0010 16 Bit at LLC2 4 2 2 Y 7 0 Three State CrCb 7 0 Three State 0011 default 8 Bit at LLC1 4 2 2 YCrCb 7 0 Three State Three State Three State 0110 1111 Reserved Reserved Do not use Rev 0 Page 72 of 112 MPU PORT DESCRIPTION The ADV7188 supports a 2 wire C compatible serial inter face Two inputs serial data SDA and serial clock SCLK carry information b
174. in power down mode The ADV7188 leaves the power down state if the PWRDN bit is set to 0 via IC or if the overall part is reset using the RESET pin Note that PDBP must be set to 1 for the PWRDN bit to power down the ADV7188 0 default The chip is operational 1 The ADV7188 is in chip wide power down ADC Power Down Control The ADV7188 contains four 12 bit ADCs ADC 0 ADC 1 ADC 2 and ADC 3 If required it is possible to power down each ADC individually e In CVBS mode ADCI and ADC2 should be powered down to save on power consumption e In S Video mode ADC2 should be powered down to save on power consumption PWRDN ADC O0 Address 0x3A 3 0 default The ADC is in normal operation 1 ADCO is powered down PWRDN ADC Il Address 0x3A 2 0 default The ADC is in normal operation 1 ADCI is powered down PWRDN ADC 2 Address 0x3A 1 0 default The ADC is in normal operation 1 ADC2 is powered down PWRDN ADC 3 Address 0x3A 0 0 default The ADC is in normal operation 1 ADC3 is powered down FB PWRDN Address 0x0F 1 To achieve very low power down current it is necessary to prevent activity on toggling input pins from reaching circuitry that could consume current FB PWRDN gates signals from the FB input pin 0 default The FB input is in normal operation 1 The FB input is in power save mode RESET CONTROL RES Chip Reset Address OxOF 7 Setting this bit
175. ing 0x93 OxCA Recommended setting 0x94 OxD5 Recommended setting OxB1 OxFF Recommended setting OxB6 0x08 Recommended setting 0xCO Ox9A Recommended setting OxCF 0x50 Recommended setting OxDO Ox4E Recommended setting OxD1 OxB9 Recommended setting OxD6 OxDD Recommended setting OxD7 OxE2 Recommended setting OxE5 0x51 Recommended setting OxOE 0x00 Recommended setting Rev 0 Page 100 of 112 MODE 2 S VIDEO INPUT Y on AIN2 and C on AIN3 All standards are supported through autodetect 10 bit ITU R BT 656 output on P19 P10 Table 105 Mode 2 S Video Input ADV7188 Register Address Register Value Notes 0x03 0x1D Ox3A Ox3B Ox3D Ox3E Ox3F 0x69 OxC3 OxC4 OxF3 OxF9 OxOE 0x52 0x54 Ox7F 0x81 0x90 0x91 0x92 0x93 0x94 OxB1 OxB6 0xCO OxCF OxDO OxD1 OxD6 OxD7 OxE5 OxOE 0x00 0x47 0x13 0x71 OxA2 Ox6A OxAO 0x03 0x32 OxFF 0x03 0x03 0x80 0x46 0x00 OxFF 0x30 0xC9 0x40 Ox3C OxCA OxD5 OxFF 0x08 Ox9A 0x50 Ox4E OxB9 OxDD OxE2 0x51 0x00 10 bit mode Enable 28 63636 MHz crystal mode Power down ADC2 and ADC3 Recommended setting MWE enable manual window color kill threshold to 2 BLM optimization BGB optimization Set SDM SEL to 03 for YC CVBS auto AIN11 AIN12 Manually mux Y signal on AIN2 to ADCO and C signal on AIN3 to ADC1 Manual mux enable Enable anti alias filter on ADCO and ADC1 Set maximum v lock range Recommended
176. ion manual gain registers LG 11 0 Luma Gain and CG 11 0 Chroma Gain in the Luma Gain and the Chroma Gain sections ANALOG VOLTAGE RANGE SUPPORTED BY ADC 1 6V RANGE FOR ADV7188 MAXIMUM VOLTAGE SDP DATA GAIN SELECTION ONLY PRE 1 PROCESSOR L DPP GAIN CONTROL 5 MINIMUM CLAMP E VOLTAGE LEVEL Figure 21 Gain Control Overview Table 39 AGC Modes Input Video Type Luma Gain Chroma Gain Any Manual gain luma Manual gain chroma CVBS Dependent on horizontal sync depth Dependent on color burst amplitude Taken from luma path Peak white Dependent on color burst amplitude Taken from luma path Y C Dependent on horizontal sync depth Dependent on color burst amplitude Taken from luma path Peak white Dependent on color burst amplitude Taken from luma path YPrPb Dependent on horizontal sync depth Taken from luma path Rev 0 Page 32 of 112 Luma Gain LAGC 2 0 Luma Automatic Gain Control Address 0x2C 6 4 The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path There are ADI internal parameters to customize the peak white gain control Contact ADI for more information Table 40 LAGC Function LAGC 2 0 Description 000 Manual fixed gain use LMG 11 0 001 AGC blank level to sync tip peak white algorithm OFF 010 AGC blank level to sync tip peak white algorithm default ON 011 Reserved 100 Reserved 101 Res
177. it Reserved 0 Not used Reserved 0 Not used Reserved 0 Not used SD FR CHNG CLR 0 Do not clear 1 Clears SD FR CHNG Q bit MV PS CS CLR 0 Do not clear 1 Clears MV PS CS Obit Reserved x Not used 0x44 Interrupt Mask 1 SD_LOCK_MSKB 0 Masks SD_LOCK_Q bit Read Write 1 Unmasks SD_LOCK_Q bit SD_UNLOCK_MSKB 0 Masks SD_UNLOCK_Q bit 1 Unmasks SD_UNLOCK_Q bit Reserved 0 Not used Reserved 0 Not used Reserved 0 Not used SD FR CHNG MSKB 0 Masks SD FR CHNG QO bit 1 Unmasks SD FR CHNG Q bit MV PS CS MSKB 0 Masks MV PS CS Qbit 1 Unmasks MV PS CS Qbit Reserved x Not used 0x45 Raw Status 2 Read Only CCAPD 0 No CCAPD data detected These bits are status bits only Rev 0 Page 93 of 112 ADV7188 User Sub Map Bit Address Register Bit Description 543 Comments Notes CCAPD data detected They cannot be cleared or Reserved x masked Register 0x46 is used for this purpose EVEN FIELD 0 Current SD Field is Odd Numbered 1 Current SD Field is Even Numbered Reserved x MPU STIM INTRO MPU_STIM_INT 0 MPU_STIM_INT 1 0x46 Interrupt Status 2 CCAPD_Q Closed captioning not detected in These bits can be cleared or Read Only the input video signal masked by registers 0x47 and Closed captioning data detected in 0x48 respectively the video input signal
178. l neue e uldep uen EUIHRHISHRUERRUREREHEEN E 19 Global Pin Gonitrol rennen erret 19 Global Status Registers eerte 21 Standard Definition Processor SDP sss 22 SD Luria Path eene eo ied valide etsi eb cente ipie 22 SD Chroma Path errem epe een Parts 22 Sync Processing nri EY TREE tiM 23 VBI Data Recovery eee eh edens 23 General Set p c cciam EN EEEE 23 Color Controls iseseisana 25 Clamp per ati om ari N KEER 27 Luma Filtered ce be iei 28 Chroma Filter oeste temen A E R 31 Gaim Op ration sesia ett Ae Os 32 Chroma Transient Improvement CTI ss 35 Digital Noise Reduction DNR and Luma Peaking Filter 36 Comi Filter eps a RR 37 AV Code Insertion and Controls ses 39 Synchronization Output Signals sss 4l SyDC PrOC SSIIB oA UEFA R ee 48 VBI Data Decode teneas deuote e Pee EP 49 FC Readback Registers serere 58 Pixel Port Config rdtion eerte hires 72 MPU Port Description 73 Register ACCESSES ui eene ien ene ne etie nest deeem 74 Register Programming 74 TG Sequencetz up Eee ERU Hie 74 EG Register Maps aic iet eese ORE Ran 75 User EP 75 User Sub Map aee bio bebe te dod e orte ete ie E ipee 91 PC Programming Examples eerte 100 Mode 1 CVBS Input 100 Mode 2 S Video Tup t recte 101 Mode 3 525i 625i YPrPb Input see
179. l response is chosen by the system with no requirement for user intervention Figure 16 through Figure 19 show the overall response of all filters together Unless otherwise noted the filters are set into a typical wideband mode Y Shaping Filter For input signals in CVBS format the luma shaping filters play an essential role in removing the chroma component from a composite signal YC separation must aim for best possible crosstalk reduction while still retaining as much bandwidth especially on the luma component as possible High quality YC separation can be achieved by using the internal comb filters ofthe ADV7188 Comb filtering however relies on the frequency relationship of the luma component multiples of the video line rate and the color subcarrier Fsc For good quality CVBS signals this relationship is known the comb filter algorithms can be used to separate out luma and chroma with high accuracy Rev 0 Page 28 of 112 For nonstandard video signals the frequency relationship may be disturbed and the comb filters may not be able to remove all crosstalk artifacts in an optimum fashion without the assistance of the shaping filter block An automatic mode is provided Here the ADV7188 evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard YFSM WYSFMOVR and WYSEM allow the user to manually override the automatic decisions in part or
180. le stop condition followed by a single start condition If an invalid subaddress is issued by the user the ADV7188 does not issue an acknowledge and returns to the idle condition If in autoincrement mode the highest subaddress is exceeded the following action is taken l Inread mode the highest subaddress register contents continue to be output until the master device issues a no acknowledge This indicates the end of a read In a no acknowledge condition the SDA line is not pulled low on the ninth pulse 2 Inwrite mode the data for the invalid byte is not loaded into any subaddress register a no acknowledge is issued by the ADV7188 and the part returns to the idle condition d F 05478 049 Figure 44 Bus Data Transfer WRIT SEQUENCE e e para fawje LSB 0 LSB 1 i scout S Stave ADDR AGI sus oos ss SUAVE ADOR AS oara aww osx aon S START BIT A S ACKNOWLEDGE BY SLAVE P STOP BIT A M ACKNOWLEDGE BY MASTER A S NO ACKNOWLEDGE BY SLAVE A M NO ACKNOWLEDGE BY MASTER 05478 050 Figure 45 Read and Write Sequence Rev 0 Page 73 of 112 ADV7188 REGISTER ACCESSES The MPU can write to or read from most of the ADV7188 s registers excepting the registers that are read only or write only The subaddress register determines which register the next read or write operation accesses All communications with the part through the bus start with an access to the subaddress regi
181. ly Read Only output SD 50 Hz signal output They cannot be cleared or masked Register 0x4A is used SD V LOCK SD vertical sync lock not established for this purpose SD vertical sync lock established SD H LOCK SD horizontal sync lock not established SD horizontal sync lock established Reserved x Not used SCM LOCK 0 SECAM lock not established 1 SECAM lock established Reserved x Not used Reserved Not used Reserved Not used Ox4A Interrupt Status 3 SD OP CHNG Q SD 60 50 Hz frame rate No Change in SD signal standard These bits can be cleared and Read Only at output detected at the output masked by Registers Ox4B and A Change in SD signal standard is Ox4C respectively detected at the output Rev 0 Page 94 of 112 ADV7188 User Sub Map Bit Address Register Bit Description 43 0 Comments Notes SD V LOCK CHNG Q No change in SD vertical sync lock status SD vertical sync lock status has changed SD H LOCK CHNG Q No change in SD horizontal sync lock status SD horizontal sync lock status has changed SD AD CHNG Q SD autodetect changed x No change in AD RESULT 2 0 bits in Status Register 1 AD RESULT 2 0 bits in Status Register 1 have changed SCM LOCK CHNG Q SECAM Lock 0 No change in SECAM Lock status SECAM lock status has changed PAL SW LK CHNG Q No change in PA
182. ma gain gain based on measurements taken from the active video The PW_UPD bit determines the rate of gain change LAGC 2 0 must be set to the appropriate mode to enable the peak white or average video mode in the first place Table 45 Betacam Levels Name Betacam mV Betacam Variant mV SMPTE mV MII mV Y Range 0 to 714 incl 7 596 pedestal 0to714 0 to 700 0 to 700 incl 7 5 pedestal Prand Pb Range 467 to 467 505 to 505 350 to 350 324 to 4324 Sync Depth 286 286 300 300 CAGT 1 0 Chroma Automatic Gain Timing Address 0x2D 7 6 This register allows the user to influence the tracking speed of the chroma automatic gain control It has an effect only if the CAGC 1 0 register is set to 10 automatic gain Table 46 CAGT Function e Chroma automatic gain value CAGC 1 0 set to any of the automatic modes Table 47 CG CMG Function CAGT 1 0 Description 00 Slow TC 2 sec 01 Medium TC 1 sec 10 Fast TC 0 2 sec 11 default Adaptive CG 11 0 Chroma Gain Address 0x2D 3 0 Address 0x2E 7 0 CMG 11 0 Chroma Manual Gain Address 0x2D 3 0 Address 0x2E 7 0 CG 11 0 is a dual function register If written to a desired manual chroma gain can be programmed This gain becomes active if the CAGC 1 0 mode is switched to manual fixed gain Refer to Equation 4 for calculating a desired gain If read back the register returns the current gain val
183. mb 01 default BT470 compliant no color on lines 624 to 22 311 to 335 chroma present on half lines Rev 0 Page 38 of 112 Table 56 CCMP Function ADV7188 CCMP 2 0 Description Configuration 000 default Adaptive comb mode 100 Disable chroma comb 101 Fixed chroma comb top lines of line memory 110 Fixed chroma comb all lines of line memory 111 Fixed chroma comb bottom lines of line memory Adaptive 3 line chroma comb for CTAPSP 01 Adaptive 4 line chroma comb for CTAPSP 10 Adaptive 5 line chroma comb for CTAPSP 11 Fixed 2 line chroma comb for CTAPSP 01 Fixed 3 line chroma comb for CTAPSP 10 Fixed 4 line chroma comb for CTAPSP 11 Fixed 3 line chroma comb for CTAPSP 01 Fixed 4 line chroma comb for CTAPSP 10 Fixed 5 line chroma comb for CTAPSP 11 Fixed 2 line chroma comb for CTAPSP 01 Fixed 3 line chroma comb for CTAPSP 10 Fixed 4 line chroma comb for CTAPSP 11 Table 57 YCMP Function YCMP 2 0 Description Configuration Oxx default Adaptive comb mode Adaptive 5 lines 3 taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb top lines of line memory Fixed 3 lines 2 taps luma comb 110 Fixed luma comb all lines of line memory Fixed 5 lines 3 taps luma comb 111 Fixed luma comb bottom lines of line memory Fixed 3 lines 2 taps luma comb AV CODE INSERTIO
184. ming of VBI Standards Address 0x64 7 User Sub Map The user can configure the VDP to decode different standards on a line to line basis through manual line programming For this the user has to set the MAN LINE PGM bit The user needs to write into all the line programming registers VBI DATA Px Ny Register 0x64 to Register 0x77 User Sub Map 0 default The VDP decodes default standards on lines as shown in Table 64 1 The VBI standards to be decoded are manually programmed VBI DATA Px Ny 3 0 VBI Standard to be Decoded on Line x for PAL Line y for NTSC Address 0x64 0x77 User Sub Map These are related 4 bit clusters contained from Register 0x64 to Register 0x77 in the User Sub Map The 4 bit line programming registers named VBI DATA Px Ny identifies the VBI data standard that would be decoded on line number X in PAL or on line number Y in NTSC mode The different types of VBI standards decoded by VBI DATA Px Ny are shown in Table 65 Note that the interpretation of its value depends on whether the ADV7188 is in PAL or NTSC mode Rev 0 Page 49 of 112 ADV7188 Table 64 Default Standards on Lines for PAL and NTSC Default VBI PAL 625 50 Default VBI Default VBI NTSC 525 60 Default VBI Line No DATA Decoded Line No DATA Decoded Line No DATA Decoded Line No DATA Decoded 6 WST 318 VPS 23 Gemstar 1x 7 WST 319 WST 24 Gemstar 1x
185. n IDO UDW 1 UDWS 5 2 0000 undefined bits made zeros UDWS9 5 2 0000 undefined bits made zeros UDW10 5 2 0000 undefined bits made zeros and for the byte mode UDWS 9 2 0010 0111 UDWSo 9 2 0000 0000 undefined bits made zeros UDW7 9 2 0000 0000 undefined bits made zeros Rev 0 Page 54 of 112 ADV7188 Data Bytes VBI_WORD_4 BYTEI 7 0 VBI_WORD_5 BYTE2 7 0 The number of VBI WORDS for each VBI data standard and The VBI WORD 4 to VBI WORD N 3 contains the data words that were decoded by the VDP in the transmission order The position of bits in bytes is in the inverse transmission order the total number of UDWs in the ancillary data stream is shown For example closed caption has two user data bytes as shown in in Table 72 Table 76 The data bytes in the ancillary data stream would be as follows Table 71 Framing Code Sequence for Different VBI Standards Error Free Framing Code bits Error Free Framing Code Reported by VBI Standard Length in Bits In Order of Transmission VDP In Reverse Order of Transmission TIXT SYSTEM A PAL 8 11100111 11100111 TIXT SYSTEM B PAL 8 11100100 00100111 TTXT SYSTEM B NTSC 8 11100100 00100111 TTXT_SYSTEM_C PAL and NTSC 8 11100111 11100111 TTXT_SYSTEM_D PAL and NTSC 8 11100101 10100111 VPS PAL 16 10001010100011001 1001100101010001 VITC NTSC and PAL 1 0 0 WSS PAL 24 000111100011110000011111 11111000001
186. n a 625 line system and from 1 to 263 in a 525 line system Note the line number on which the packet is output differs from the line number on which the VBI data was sliced due to the vertical delay through the comb filters e Data Count The data count specifies the number of UDWs in the ancillary stream for the standard The total number of user data words 4 x Data Count Padding words may be introduced to make the total number of UDWSs divisible by four Rev 0 Page 52 of 112 Table 68 Ancillary Data in Nibble Output Format ADV7188 Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 BO Description 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Ancillary data preamble 2 1 1 1 1 1 1 1 1 1 1 3 EP EP 0 I2C DID6 2 4 0 0 0 DID data identification word TD j SDID secondary data 4 EP EP I2C SDID7 2 5 0 0 0 identification word 5 EP EP 0 DC 4 0 0 0 Data count 6 EP EP padding 1 0 VBI DATA STD 3 0 0 0 IDO user data word 1 7 EP EP 0 Line number 9 5 0 0 ID1 user data word 2 8 EP EP Even Field Line number 4 0 0 0 ID2 user data word 3 9 EP EP 0 0 0 0 VDP TTXT TYPE 1 0 O 0 ID3 user data word 4 10 EP EP 0 0 VBI WORD 1 7 4 0 0 User data word 5 11 EP EP 0 0 VBI WORD 1 3 0 0 0 User data word 6 12 EP EP 0 0 VBI WORD 27 4 0 0 User data word 7 13 EP EP 0 0 VBI WORD 2 3 0 0 0 User data word 8 14 EP EP 0 0 VBI WORD 3 7 4 0 0 User
187. ncrease threshold need larger active video 10000 content before identifying nonblack lines 00000 to Decrease threshold even small noise levels can 01011 cause the detection of nonblack lines LB SL 3 0 Letterbox Start Line Address OxDD 7 4 The LB SL 3 0 bits are set at 0100 by default For an NTSC signal this window is from Line 23 to Line 286 By changing the bits to 0101 the detection window starts on Line 24 and ends on Line 287 LB EL 3 0 Letterbox End Line Address 0xDD 3 0 The LB_EL 3 0 bits are set at 1101 by default This means that letterbox detection window ends with the last active video line For an NTSC signal this window is from Line 262 to Line 525 By changing the bits to 1100 the detection window starts on Line 261 and ends on Line 254 IF Compensation Filter IFFILTSEL 2 0 IF Filter Select Address OxF8 2 0 The IFFILTSEL 2 0 register allows the user to compensate for SAW filter characteristics on a composite input as would be observed on tuner outputs Figure 42 and Figure 43 show IF filter compensation for NTSC and PAL The options for this feature are as follows e Bypass mode default e NTSC consists of three filter characteristics e PAL consists of three filter characteristics 6 4 eo b AMPLITUDE dB 05478 046 2 0 2 5 3 0 3 5 4 0 4 5 5 0 FREQUENCY MHz Figure 42 NTSC IF Compensation Filter Responses
188. nd surface mount soldering at up to 255 C 5 C In addition itis backward compatible with conventional SnPb soldering processes This means that the electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220 C to 235 C 2 Z Pb free part Rev 0 Page 109 of 112 ADV7188 NOTES Rev 0 Page 110 of 112 ADV7188 NOTES Rev 0 Page 111 of 112 ADV7188 NOTES Purchase of licensed l C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips C Patent Rights to use these components in an lC system provided that the system conforms to the I C Standard Specification as defined by Philips 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D05478 0 7 05 0 DEVICES Rev 0 Page 112 of 112 www analog com
189. ne chroma comb for CTAPSN 10 Adaptive 5 line chroma comb for CTAPSN 11 100 Disable chroma comb 101 Fixed chroma comb top lines of line memory Fixed 2 line chroma comb for CTAPSN 01 Fixed 3 line chroma comb for CTAPSN 10 Fixed 4 line chroma comb for CTAPSN 11 110 Fixed chroma comb all lines of line memory Fixed 3 line chroma comb for CTAPSN 01 Fixed 4 line chroma comb for CTAPSN 10 Fixed 5 line chroma comb for CTAPSN 11 111 Fixed chroma comb bottom lines of line memory Fixed 2 line chroma comb for CTAPSN 01 Fixed 3 line chroma comb for CTAPSN 10 Fixed 4 line chroma comb for CTAPSN 11 Table 53 Y CMN Function YCMN 2 0 Description Configuration 000 default Adaptive comb mode Adaptive 3 line 3 taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb top lines of line memory Fixed 2 line 2 taps luma comb 110 Fixed luma comb all lines of line memory Fixed 3 line 3 taps luma comb 111 Fixed luma comb bottom lines of line memory Fixed 2 line 2 taps luma comb Rev 0 Page 37 of 112 ADV7188 PAL Comb Filter Settings Used for PAL B G H I D PAL M PAL Combinational N PAL 60 and NTSC 443 CVBS inputs PSFSEL 1 0 Split Filter Selection PAL Address 0x19 1 0 PFSEL 1 0 selects how much of the overall signal bandwidth is fed to the combs A wide bandwidth split filter eliminates dot crawl but shows imperfections
190. ng Filter YSFM A 0 Selects Y shaping filter mode 0 0 0 0 0 Auto wide notch for poor quality Decoder selects optimum Y shaping Control when in CVBS only mode sources or wide band filter with filter depending on CVBS quality Comb for good quality input Allows the user to select a wide range of low 0 0 0 0 1 Auto narrow notch for poor pass and notch filters quality sources or wideband filter with comb for good quality input If either auto mode is selected the decoder 0 0 0 1 0 SVHS1 If one of these modes is selected the selects the optimum Y filter depending on 010 0 1 1 SVHS2 decoder does not change filter modes the CVBS video source quality good vs bad 0 0 1 01 0 SVHS3 Depending on video quality a fixed olol lo sva filter response the one selected is used for good and bad quality video 0 0j1 1 10 SVHS5 0J0 1 1 1 SVHS6 0 1 0 0 0 SVHS7 0 1 0 0 1 SVHS8 0 1 0 1 0 SVHS9 0 1 0 1 1 SVHS 10 0 1 1 0 0 SVHS 11 0 1 1 0 1 SVHS 12 0 1 1 1 0 SVHS 13 0 1 1 1 1 SVHS 14 1 0 0 0 0 SVHS 15 1 0 0 0 1 SVHS 16 1 0 0 1 O SVHS 17 1 0 0 1 1 SVHS 18 CCIR601 1 0 1 0 O PALNN1 1 0 1 0 1 PALNN2 1 0 1 1 0O PALNN3 1 0 1 1 1 PALWN 1 1 1 0 0 0 PALWN2 1 1 0 0 1 NTSCNN1 1 1 0 1 0 NTSCNN2 1 1 0 1 1 NTSCNN3 1 1 1 0 0 NTSCWN1 1 1 1 0 1 NTSCWN2 1 1 1 1 0 NTSCWN3 1 1 11 1 1 Reserved 0x17 Shaping Filter CSFM 2 0 0 0 0 Auto selection 15 MHz Automatically selects a C filter based Control cont
191. nsertion of VBI decoded data into ancillary 656 stream The user may select the data identification word DID and the secondary data identification word SDID through programming the ADF_DID 4 0 and ADF_SDID 5 0 bits respectively as explained below ADF DID 4 0 User Specified Data ID Word in Ancillary Data Address 0x62 4 0 User Sub Map This bit selects the data ID word to be inserted in the ancillary data stream with the data decoded by the VDP The default value of ADF DID 4 0 is 10101 ADF SDID 5 0 User Specified Secondary Data ID Word in Ancillary Data Address 0x63 5 0 User Sub Map These bits select the secondary data ID word to be inserted in the ancillary data stream with the data decoded by the VDP The default value of ADF SDID 5 0 is 101010 DUPLICATE ADF Enable Duplication Spreading of Ancillary Data over Y and C Buses Address 0x 63 7 User Sub Map This bit determines whether the ancillary data is duplicated over both Y and C buses or if the data packets are spread between the two channels 0 default The ancillary data packet is spread across the Y and C data streams 1 The ancillary data packet is duplicated on the Y and C data streams ADF MODE 1 0 Determine the Ancillary Data Output Mode Address 0x62 6 5 User Sub Map These bits determine if the ancillary data output mode is in byte mode or nibble mode ADF MODE 1 0 Description 00 default Nibble mode 01 B
192. ntrol 2 RW NVBIOCCM 1 NVBIOCCM O NVBIECCM 1 NVBIECCM 0 PVBIOCCM 1 PVBIOCCM O PVBIECCM 1 PVBIECCM O 0101010155 237 ED FB STATUS R FB STATUS 3 FB STATUS FB STATUS 1 FB_STATUS O 237 ED FB_CONTROL1 Ww FB INV CVBS RGB SEL FB MODE 1 FB MODEO 00010000 10 MAN ALPHA MAN ALPHA MAN ALPHA MAN ALPHA MAN ALPHA MAN ALPHA MAN ALPHA 238 EE FB CONTROL 2 RW FB CSC MAN VAL 6 VAL VALA VAL3 VAL 2 VAL 1 VAL O 00000000 00 FB_SP_ FB_SP_ FB_SP_ FB_SP_ CNTR_ FB_EDGE_ FB_EDGE_ FB_EDGE_ 239 EF FB_CONTROL 3 RW ADJUST 3 ADJUST 2 ADJUST 1 ADJUST O ENABLE SHAPE 2 SHAPE 1 SHAPE O 01001010 4A 240 FO FB_CONTROL 4 RW FB DELAY 3 FB_DELAY 2 FB DELAY 1 FB DELAY O 01000100 44 241 F1 FB CONTROL 5 RW CNTR LEVEL 1 CNTR LEVELO FB LEVEL 1 FB LEVEL O CNTR_MODE 1 CNTR MODE O RGB IP SEL 00001100 0C 243 F3 AFE CONTROL 1 RW ADC3 SW 3 ADC3 SW 2 ADC3 SW 1 ADC3 SW AA FILT EN 3 AA FILT EN 2 AA FILT EN 1 AA FILT EN O 00000000 00 244 F4 Drive Strength RW DR STR DR STR O DR STR C DR STR CO DR STR S DR STR SO xx010101 15 248 F8 IF Comp Control RW IFFILTSEL 2 IFFILTSEL 1 IFFILTSEL O 00000000 00 VS COAST VS COAST EXTEND VS EXTEND VS 249 F9 VS Mode Control RW MODE 1 MODE O MIN FREQ MAX FREQ 00000000 00 PEAKING PEAKING PEAKING PEAKING PEAKING_ PEAKING_ PEAKING_ PEAKING_ 251 FB Peaking Control RW GAIN 7 GAIN 6 GAIN 5 GAIN 4 GAIN 3 GAIN 2 GAIN 1 GAIN O 01000000 40 252 FC Coring Threshold2 RW DNR TH 27 DNR TH 26 DNR TH 2 5 DNR TH
193. o the ADCs sample at 54 MHz and the first decimation is performed inside the DPP filters Therefore the data rate into the ADV7188 is always 27 MHz The ITU R BT 601 recommends a sampling frequency of 13 5 MHz The luma antialias filter decimates the oversampled video using a high quality linear phase low pass filter that preserves the luma signal while at the same time attenuating out of band components The luma antialias filter has a fixed response e Luma shaping filters YSH The shaping filter block is a programmable low pass filter with a wide variety of re sponses It can be used to selectively reduce the luma video signal bandwidth needed prior to scaling for example For some video sources that contain high frequency noise reducing the bandwidth of the luma signal improves visual picture quality A follow on video compression stage may work more efficiently if the video is low pass filtered The ADV7188 has two responses for the shaping filter one that is used for good quality CVBS component and S VHS type sources and a second for nonstandard CVBS signals The YSH filter responses also include a set of notches for PAL and NTSC However it is recommended to use the comb filters for YC separation e Digital resampling filter This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actua
194. on Programmable Threshold Rev 0 Page 17 of 112 ADV7188 Table 15 Fast Blank and Contrast Reduction Programmable Threshold IC Controls CNTR ENABLE FB LEVEL 1 0 CNTR LEVEL 1 0 0 00 default XX 0 01 XX 0 10 XX 0 11 XX 1 00 default 00 1 01 01 1 10 10 1 11 11 Fast Blanking Threshold Contrast Reduction Threshold 14V n a 1 6V n a 1 8V n a 2 0V n a 1 6V 0 4V 1 8V 0 6 V 2 0V 0 8 V 2 2V 2 0V Table 16 FB_STATUS Functions FB_STATUS 3 0 Bit Name Description 0 FB_STATUS O FB rise A high value indicates there has been a rising edge on FB since the last IC read Value is cleared by current I C read self clearing bit 1 FB STATUS 1 FB fall A high value indicates there has been a falling edge on FB since the last I C read Value is cleared by current C read self clearing bit 2 FB STATUS 2 FB stat Value of FB input pin at time of read 3 FB STATUS 3 FB high A high value indicates there has been a rising edge on FB since the last PC read Value is cleared by current I C read self clearing bit FB INV Address OxED 3 write only The interpretation of the polarity of the signal applied to the FB pin can be changed using FB INV 0 default The fast blank pin is active high 1 The fast blank pin is active low READBACK OF FB PIN STATUS FB STATUS 3 0 Address OxED 7 4 FB STATUS 3 0 is a readback value that provides the system information on the status o
195. on diagonal lines The opposite is true for a narrow bandwidth split filter Table 54 PSFSEL Function PSFSEL 1 0 Description 00 Narrow 01 default Medium 10 Wide 11 Widest CTAPSP 1 0 Chroma Comb Taps PAL Address 0x39 7 6 Table 55 CTAPSP Function CTAPSP 1 0 Description 00 Do not use 01 PAL chroma comb adapts 5 lines 3 taps to 3 lines 2 taps cancels cross luma only 10 PAL chroma comb adapts 5 lines 5 taps to 3 lines 3 taps cancels cross luma and hue error less well 11 default PAL chroma comb adapts 5 lines 5 taps to 4 lines 4 taps cancels cross luma and hue error well CCMP 2 0 Chroma Comb Mode PAL Address 0x39 5 3 See Table 56 YCMP 2 0 Luma Comb Mode PAL Address 0x39 2 0 See Table 57 Vertical Blank Control Each vertical blank control register has the same meaning for the following bits 00 Early by 1 line 10 Delay by 1 line 11 Delay by 2 lines 01 default is described under each register NVBIOLCM 1 0 NTSC VBI Odd Field Luma Comb Mode Address OxEB 7 6 These bits control the first combed line after VBI on NTSC odd field luma comb 01 default SMPTE170 compliant blank lines 1 to 20 264 to 282 comb half lines NVBIELCM 1 0 NTSC VBI Even Field Luma Comb Mode Address OxEB 5 4 These bits control the first combed line after VBI on NTSC even field luma comb 01 default S5MPTE170 compliant blank lin
196. ows the user to adjust the brightness of the picture Table 33 BRI Function BRI 7 0 Description 0x00 default Offset of the luma channel OmV Ox7F Offset of the luma channel 204mV 0x80 Offset of the luma channel 204mV HUE 7 0 Hue Adjust Address OxOB 7 0 This register contains the value for the color hue adjustment It allows the user to adjust the hue of the picture HUE 7 0 has a range of 90 with 0x00 equivalent to an adjustment of 0 The resolution of HUE 7 0 is 1 bit 0 7 The hue adjustment value is fed into the AM color demodulation block Therefore it only applies to video signals that contain chroma information in the form of an AM modulated carrier CVBS or Y C in PAL or NTSC It does not affect SECAM and does not work on component video inputs YPrPb DEF Y 5 0 Default Value Y Address 0x0C 7 2 If the ADV7188 loses lock on the incoming video signal or if there is no input signal the DEF Y 5 0 bits allow the user to specify a default luma value to be output The register is used under the following conditions e IfDEF VAL AUTO ENbbit is set to high and the ADV7188 loses lock to the input video signal This is the intended mode of operation automatic mode e TheDEF VAL EN bit is set regardless of the lock status of the video decoder This is a forced mode that may be useful during configuration The DEF Y 5 0 values define the 6 MSBs of the output video The remaining
197. pport is enabled the parameters for the CSC are automatically configured correctly for this operation If the user wishes to use a different conversion matrix this autoconfiguration can be disabled and the CSC can be manually programmed For details on this manual configuration please contact ADI 0 default The CSC is configured automatically for the RGB to YPrPb conversion 1 The CSC can be configured manually not recommended Rev 0 Page 18 of 112 ADV7188 GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip POWER SAVE MODES Power Down PDBP Address 0x0F 2 The digital core of the ADV7188 can be shut down by using a pin PWRDN and the PWRDN bit The PDBP register controls which of the two has the higher priority The default is to give the pin PWRDN priority This allows the user to have the ADV7188 powered down by default 0 default The digital core power is controlled by the PWRDN pin the bit is disregarded 1 The bit has priority the pin is disregarded PWRDN Address OxOF 5 Setting the PWRDN bit switches the ADV7188 into a chip wide power down mode The power down stops the clock from entering the digital section of the chip thereby freezing its operation No I C bits are lost during power down The PWRDN bit also affects the analog blocks and switches them into low current modes The IC interface itself is unaffected and remains operational
198. ption 00 Slow TC 2 sec 01 Medium TC 1 sec 10 Fast TC 0 2 sec 11 default Adaptive LG 11 0 Luma Gain Address 0x2F 3 0 Address 0x30 7 0 LMG 11 0 Luma Manual Gain Address 0x2F 3 0 Address 0x30 7 0 Luma gain 11 0 is a dual function register If written to a desired manual luma gain can be programmed This gain becomes active if the LAGC 2 0 mode is switched to manual fixed gain Equation 2 and Equation 3 show how to calculate a desired gain for NTSC and PAL standards respectively For example to program the ADV7188 into manual fixed gain mode with a desired gain of 0 89 for the NTSC standard 1 Use Equation 2 to convert the gain 0 95 x 1128 1071 6 2 Truncate to integer value 1071 6 1071 3 Convert to hexadecimal 1071d 0x42F 4 Split into two registers and program Luma Gain Control 1 3 0 0x4 Luma Gain Control 2 7 0 0x2F 5 Enable manual fixed gain mode Set LAGC 2 0 to 000 BETACAM Enable Betacam Levels Address 0x01 5 If YPrPb data is routed through the ADV7188 the automatic gain control modes can target different video input levels as outlined in Table 45 Note that the BETACAM bit is valid only if the input mode is YPrPb component The BETACAM bit sets the target value for AGC operation A review of the following sections is useful e INSEL 3 0 Input Selection Address 0x00 3 0 to find how component video YPrPb can be routed through the ADV7188
199. r 0001 2 4 Byte Row No Dehammed Byte 5 UTC 3 Byte Desig Code Dehammed Byte 6 4th Byte to 10 Byte Dehammed Initial teletext Page Byte 7 to Byte 12 11 to 23 Byte UTC bytes Dehammed Bytes 13 to Byte 25 24 to 42 Byte Raw status bytes 8 30 Format 2 packet 1 Byte Mag No Dehammed Byte 4 Desig Code 0010 or 0011 2 d Byte Row No Dehammed Byte 5 PDC 3 Byte Desig Code Dehammed Byte 6 4 Byte to 10 Byte Dehammed Initial teletext Page Byte 7 to Byte 12 11 to 23 Byte PDC bytes Dehammed Byte 13 to Byte 25 24th to 42d Byte Raw status bytes X 26 X 27 X 28 X 29 X 30 X 31 1 Byte Mag No Dehammed Byte 4 2 4 Byte Row No Dehammed Byte 5 3 Byte Desig Code Dehammed Byte 6 4 to 42 4 Byte Raw data bytes For X 26 X 28 and M 29 further decoding needs 24x18 hamming decoding Not supported at present Rev 0 Page 58 of 112 ADV7188 CGMS and WSS The CGMS and WSS data packets convey the same type of information for different video standards WSS is for PAL and CGMS is for NTSC and hence the CGMS and WSS readback registers are shared WSS is bi phase coded the VDP does a bi phase decoding to produce the 14 raw WSS bits in the CGMS WSS readback I C registers and sets the CGMS_WSS_AVL bit CGMS_WSS_CLEAR CGMS WSS Clear Address 0x78 2 User Sub Map Write Only Self Clearing 1 Re initializes the CGMS WSS readback registers CGMS WSS AVL CGMS WSS Available Bit Address 0x78 2
200. rces security and surveillance cameras and professional systems ANALOG FRONT END The ADV7188 analog front end includes four 12 bit noise shaped video ADCs that digitize the analog video signal before applying it to the standard definition processor The analog front end uses differential channels to each ADC to ensure high performance in mixed signal applications The front end also includes a 12 channel input mux that enables multiple video signals to be applied to the ADV7188 Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7188 The ADCs are configured to run in 4x oversampling mode The ADV7188 has optional anti aliasing filters on each of the four input channels The filters are designed for SD video with approximately 6 MHz bandwidth SCART and overlay functionality are enabled by the ADV7188 s ability to simultaneously process CVBS and Standard Definition RGB signals Signal mixing is controlled by the Fast Blank pin STANDARD DEFINITION PROCESSOR SDP The ADV7188 is capable of decoding a large selection of baseband video signals in composite S Video and component formats The video standards supported include PAL B D I G H PAL60 PAL M PAL N PAL Nc NTSC M J NTSC 4 43 and SECAM B D G K L The ADV7188 can automatically detect the vi
201. ream Each VBI data standard has been split into a clock run in CRI a framing code FC and a number of data bytes n The data packet in the ancillary stream includes only the FC and data bytes The VBI WORD X in the ancillary data stream has the following format Table 70 Structure of VBI Data Words in Ancillary Stream The framing code is always reported in the inverse transmission order Table 71 shows the framing code and its valid length for VBI data standards supported by VDP Example For teletext B WST the framing code byte is 11100100 OxEA bits shown in the order of transmission Thus VBI WORD 1 0x27 VBI WORD 2 0x00 and VBI WORD 3 0x00 Translating them into UDWs in the ancillary data stream for the nibble mode UDWS5 5 2 0010 UDW6 5 2 0111 UDW7 5 2 0000 undefined bits made zeros Ancillary data byte Byte number Type Byte Description VBI WORD 1 FCO Framing code 23 16 VBI WORD 2 FC1 Framing Code 15 8 VBI WORD 3 FC2 Framing Code 7 0 VBI WORD 4 DB1 1 data byte VBI WORD N43 DBn Last nth data byte VDP Framing Code The length of the actual framing code depends on the VBI data standard For uniformity the length of the framing code reported in the ancillary data stream is always 24 bits For standards with a lesser framing code length the extra LSB bits are set to 0 The valid length of the framing code can be decoded from the VBI DATA STD bit available i
202. rupt in register Unmasks VDP CCAP D Q Ox4E for the CCAP Gemstar CGMS WSS VPS PDC UTC and Reserved VITC data is using the VDP data VDP CGMS WSS CHNGD MSKB 0 Masks VDP CGMS WSS CHNGD Q slicer 1 Unmasks VDP CGMS WSS CHNGD Q Reserved x VDP GS VPS PDC UTC 0 Masks CHNG MSKB VDP GS VPS PDC UTC CHNG Q 1 Unmasks VDP GS VPS PDC UTC CHNG OQ Reserved x VDP VITC MSKB 0 Masks VDP_VITC_Q 1 Unmasks VDP VITC Q Reserved x 0x60 VDP Config 1 VDP TTXT TYPE MAN 1 0 PAL teletext ITU BT 653 625 50 A NTSC Reserved PAL teletext ITU BT 653 625 50 B WST NTSC teletext ITU BT 653 525 60 B PAL teletext ITU BT 653 625 50 C NTSC teletext ITU BT 653 525 60 C OR EIA516 NABTS PAL teletext ITU BT 653 625 50 D NTSC teletext ITU BT 653 525 60 D VDP_TTXT_TYPE_MAN_ENABLE 0 User programming of teletext type disabled 1 User programming of teletext type enabled WST_PKT_DECOD_DISABLE 0 Enable hamming decoding of WST packets 1 Disable hamming decoding of WST packets Reserved 1 0 0 0 0x61 VDP Config 2 Reserved x x AUTO_DETECT_GS_TYPE 0 Disable autodetection of Gemstar type 1 Enable autodetection of Gemstar type Reserved 0 0 0 0x62 VDP ADF Config 1 ADF DID 4 0 1 01 User specified DID sent in the ancillary data stream with VDP decoded data ADF MODE 1 0 0 0 Nibble mode 01 Byte mode no code restrictions 1 0 Byte mode with 0x00 and OxFF prevented 1 1 Reserved ADF ENABLE 0 Disable insertion of VBI decoded data into ancillary 656 stre
203. s state at the start of the line even field VSEHO 0 VS goes low in the middle of the line odd field 1 VS changes state at the start of the line odd field Rev 0 Page 82 of 112 ADV7188 Address Register Bit Description Bit Comments Notes 0x34 HS Position Control 1 HSE 10 8 HS end allows the positioning of the HS output within the video line HS output ends HSE 10 0 pixels after the falling edge of HSYNC Using HSB and HSE the user can program the position and length of the output HSYNC Reserved Set to 0 HSB 10 8 HS begin allows the positioning of the HS output within the video line HS output starts HSB 10 0 pixels after the falling edge of HSYNC Reserved Set to 0 0x35 HS Position Control 2 HSB 7 0 See above using HSB 10 0 and HSE 10 0 the user can program the position and length of HS output signal o o eo o o 0x36 HS Position Control 3 HSE 7 0 See above 0x37 Polarity PCLK Sets the polarity of LLC1 Invert polarity Normal polarity as per the timing diagrams Reserved Setto 0 PF Sets the FIELD polarity Active high Active low Reserved Setto 0 PVS Sets the VS Polarity Active high Active low Reserved Setto 0 PHS Sets HS Polarity Active high Active low 0x38 NTSC Comb Control YCMN 2 0 Luma Comb Mode NTSC Adaptive
204. ss OxED 1 0 FB_MODE controls which of the fast blank modes is selected Table 12 FB_MODE 1 0 function FB_MODE 1 0 Description 00 default Static Switch Mode 01 Fixed Alpha Blending 10 Dynamic Switching Fast Mux 11 Dynamic Switching with Edge Enhancement Static Mux Selection Control CVBS RGB SEL Address OxED 2 CVBS RGB SEL controls whether the video from the CVBS or the RGB source is selected for output from the ADV7188 0 default Data from the CVBS source is selected for output 1 Data from the RGB source is selected for output Alpha Blend Coefficient MAN ALPHA VAL 6 0 Address OxEE 6 0 When FB MODEL 1 0 01 and fixed alpha blending is selected MAN ALPHA VAL 6 0 determines the proportion in which the video from the CVBS source and the RGB source are blended Equation 1 shows how these bits affect the video output MAN ALPHA_VAL 6 Video Videocygs x 1 VALS 2 1 out 64 MAN ALPHA_VAL 6 0 64 Video pgp X The maximum valid value for MAN ALPHA VAL 6 0 is 1000000 such that the alpha blender coefficients remain between 0 and 1 The default value for MAN ALPHA VAL 6 0 is 0000000 signals are sampled at 54 MHz FAST BLANK FB PIN FAST BLANK POSITION RESOLVER SIGNAL CVBS CONDITIONING CLAMPING AND DECIMATION TIMING EXTRACTION 12C CONTROL O PROCESSING 5 OUTPUT SIGNAL CONDITIONING
205. ster A read write operation is then performed from to the target address which then increments to the next address until a stop command on the bus is performed REGISTER PROGRAMMING The I C Register Maps section describes each register in terms of its configuration After the part has been accessed over the bus and a read write operation is selected the subaddress is set up The subaddress register determines to from which register the operation takes place Table 102 and Table 103 list the various operations under the control of the subaddress register As can be seen in Figure 46 the registers in the ADV7188 are arranged into two maps the User Map enabled by default and the User Sub Map The User Sub Map has controls for the interrupt and VDP functionality on the ADV7188 and the User Map controls everything else The User Map and the User Sub Map consist of a common space from address 0x00 to Ox3F Depending on how Bit 5 in register OXOE SUB USR EN is set the register map then splits in two sections SUB USR EN Address OxOE 5 This bit splits the register map at register 0x40 0 default The register map does not split and the User Map is enabled 1 The register map splits and the User Sub Map is enabled USER MAP USER SUB MAP COMMON I C SPACE ADDRESS 0x00 gt Ox3F ADDRESS OXxOE BIT 5 0b ADDRESS 0x0E BIT 5 1b 12C SPACE ADDRESS 0x40 gt 0x9C INTERRUPT AND VDP REGISTER SPACE Figure 46 Regi
206. ster Access User Map and User Sub Map I C SEQUENCER An IC sequencer is used when a parameter exceeds eight bits and is therefore distributed over two or more I C registers for example HSB 11 0 12C SPACE ADDRESS 0x40 gt OxFF NORMAL REGISTER SPACE 05478 048 When such a parameter is changed using two or more I C write operations the parameter may hold an invalid value for the time between the first and last IC being completed In other words the top bits of the parameter may already hold the new value while the remaining bits of the parameter still hold the previous value To avoid this problem the I C sequencer holds the already updated bits of the parameter in local memory all bits of the parameter are updated together once the last register write operation has completed The correct operation of the IC sequencer relies on the following e Alll C registers for the parameter in question must be written to in order of ascending addresses For example for HSB 10 0 write to Address 0x34 first followed by 0x35 e No other I C taking place between the two or more C writes for the sequence For example for HSB 10 0 write to Address 0x34 first immediately followed by 0x35 Rev 0 Page 74 of 112 C REGISTER MAPS USER MAP The collective name for the registers in Table 100 below is the User Map Table 100 User Map Register Details ADV7188
207. t interface mode the following assignment takes place Cb FE Y 00 Cr 00 and Y AV Ina 16 20 bit output interface where Y and Cr Cb are delivered via separate data buses the AV code is over the whole 16 20 bits The SD_DUP_AV bit allows the user to replicate the AV codes on both buses so the full AV sequence can be found on the Y bus and on the Cr Cb bus See Figure 25 0 default The AV codes are in single fashion to suit 8 10 bit interleaved data output 1 The AV codes are duplicated for 16 20 bit interfaces VBI_EN Vertical Blanking Interval Data Enable Address 0x03 7 The VBI enable bit allows data such as intercast and closed caption data to be passed through the luma channel of the decoder with a minimal amount of filtering All data for Line 1 to Line 21 is passed through and available at the output port The ADV7188 does not blank the luma data and automatically switches all filters along the luma data path into their widest bandwidth For active video the filter settings for YSH and YPK are restored Rev 0 Page 39 of 112 ADV7188 Refer to the BL_C_VBI Blank Chroma during VBI Address 0x04 2 section for information on the chroma path 0 default All video lines are filtered scaled 1 Only the active video region is filtered scaled BL C VBI Blank Chroma during VBI Address 0x04 2 When BL C VBl is set high the Cr and Cb values of all VBI lines are blanked SD DUP AV 1 16 20
208. t occurrence of CCAP 7 Back to step 2 Interrupt Mask Register Details The following bits set the interrupt mask on the signal from the VDP VBI data slicer VDP_CCAPD_MSKB Address 0x50 0 User Sub Map 0 default Disables interrupt on VDP_CCAPD_Q signal 1 Enables interrupt on VDP_CCAPD_Q signal VDP_CGMS_WSS_CHNGD_MSKB Address 0x50 2 User Sub Map 0 default Disables interrupt on VDP_CGMS_WSS_CHNGD_Q signal 1 Enables interrupt on VDP_CGMS_WSS_CHNGD_Q signal VDP_GS_VPS_PDC_UTC_CHNG_MSKB Address 0x50 4 User Sub Map 0 default Disables interrupt on VDP GS VPS PDC UTC CHNG Q signal 1 Enables interrupt on VDP GS VPS PDC UTC CHNG Q signal VDP VITC MSKB Address 0x50 6 User Sub Map 0 default Disables interrupt on VDP VITC Q signal 1 Enables interrupt on VDP_VITC_Q signal Interrupt Status Register Details The following read only bits contain data detection information from the VDP module from the time the status bit has been last cleared or unmasked VDP_CCAPD_Q Address 0x4E 0 User Sub Map 0 default CAP data has not been detected 1 CCAP data has been detected VDP CGMS WSS CHNGD Q Address Ox4E 2 User Sub Map 0 default CGMS or WSS data has not been detected 1 CGM or WSS data has been detected VDP GS VPS PDC UTC CHNG Q Address 0x4E 4 User Sub Map 0 default Gemstar PDC UTC or VPS data has not been detected 1 Gemstar PDC U
209. tal Resampling Filter This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actual response is chosen by the system without user intervention ao a The plots in Figure 20 show the overall response of all filters a 1 rs 2 together from SH1 narrowest to SH5 widest in addition to z the wideband mode in red lt COMBINED C ANTIALIAS C SHAPING FILTER C RESAMPLER 0 zi FREQUENCY MHz T 20 Figure 19 Y NTSC Notch Filter Responses Z amp 30 2 z ul E 20 50 60 0 1 2 3 4 5 6 FREQUENCY MHz Figure 20 Chroma Shaping Filter Responses Rev 0 Page 31 of 112 ADV7188 CSFM 2 0 C Shaping Filter Mode Address 0x17 7 The C shaping filter mode bits allow the user to select from a range of low pass filters for the chrominance signal Table 38 CSFM Function CSFM 2 0 Description 000 default 1 5 MHz bandwidth filter 001 2 17 MHz bandwidth filter 010 SH1 011 SH2 100 SH3 101 SH4 110 SH5 111 Wideband mode GAIN OPERATION The gain control within the ADV7188 is done on a purely digital basis The input ADCs support a 12 bit range mapped into a 1 6 V analog voltage range Gain correction takes place after the digitization in the form ofa digital multiplier Advantages of this architecture
210. tar word2 7 0 0 0 User data words 8 Gemstar word3 7 0 0 0 User data words 9 Gemstar word4 7 0 0 0 User data words 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 84 Gemstar 1x Data Half Byte Mode Byte DI9 DI8 DI7 DI6 D 5 D 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 EP EP 0 0 Gemstar word1 7 4 0 0 User data words 7 EP EP 0 0 Gemstar word1 3 0 0 0 User data words 8 EP EP 0 0 Gemstar word2 7 4 0 0 User data words 9 EP EP 0 0 Gemstar word2 3 0 0 0 User data words 10 CS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Rev 0 Page 65 of 112 ADV7188 Table 85 Gemstar 1x Data Full Byte Mode Byte DI9 DI8 D 7 DI6 D 5 D 4 DI3 D 2 D 1 DI 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 Gemstar word1 7 0 0 0 User data words 7 Gemstar word2 7 0 0 0 User data words 8 1 0 0 0 0 0
211. tated according to the TOD bit 1 HS VS and FIELD are forced active all the time Drive Strength Selection Data DR STR 1 0 Address 0xF4 5 4 For EMC and crosstalk reasons it may be desirable to strengthen or weaken the drive strength of the output drivers The DR STR I1 0 bits affect the P 19 0 output drivers For more information on three state control refer to the Drive Strength Selection Clock and the Drive Strength Selection Sync sections Table 17 DR STR C Function Drive Strength Selection Clock DR STR C 1 0 Address OxFA 3 2 The DR STR C 1 0 bits can be used to select the strength of the clock signal output driver LLC pin For more information refer to the Drive Strength Selection Sync and the Drive Strength Selection Data sections Table 18 DR STR C Function DR STR C 1 0 Description 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x Drive Strength Selection Sync DR STR S 1 0 Address OxF4 1 0 The DR STR S 1 0 bits allow the user to select the strength of the synchronization signals with which HS VS and F are driven For more information refer to the Drive Strength Selection Clock and the Drive Strength Selection Data sections Table 19 DR STR S Function DR STR S 1 0 Description 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x
212. the address for a write as 0x40 set to Logic 1 sets the address to 0x42 64 RESET System Reset Input Active Low A minimum low reset pulse width of 5 ms is required to reset the ADV7188 circuitry 27 LLC1 O Line Locked Clock 1 This is a line locked output clock for the pixel data output by the ADV7188 Nominally 27 MHz but varies up or down according to video line length 26 LLC2 O Line Locked Clock 2 This is a divide by 2 version of the LLC1 output clock for the pixel data output by the ADV7188 Nominally 13 5 MHz but varies up or down according to video line length 29 XTAL l This is the input pin for the 28 63636 MHz crystal or can be overdriven by an external 3 3 V 28 63636 MHz clock oscillator source In crystal mode the crystal must be a fundamental crystal 28 XTAL1 O This pin should be connected to the 28 63636 MHz crystal or left as a no connect if an external 3 3 V 28 63636 MHz clock oscillator source is used to clock the ADV7188 In crystal mode the crystal must be a fundamental crystal 36 PWRDN l Logic 0 on this pin places the ADV7188 in a power down mode Refer to the I C Register Maps section for more options on power down modes for the ADV7188 79 OE I When set to Logic 0 OE enables the pixel output bus P19 to PO of the ADV7188 Logic 1 on the OE pin places P19 to PO HS VS and SFL SYNC_OUT into a high impedance state 37 ELPF l The recommended external loop filter must be connected to this ELPF pin as shown in Fig
213. tional delay by 1 line OxE6 NTSC V Bit End NVEND 4 0 How many lines after Icounr 0 0 1 0 0 NTSC default BT 656 rollover to set V low NVENDSIGN 0 Set to low when manual programming 1 Not suitable for user programming NVENDDELE Delay V bit going low by one 0 No delay line relative to NVEND even field 1 Additional delay by 1 line NVENDDELO Delay V bit going low by one 0 No delay line relative to NVEND odd field 1 Additional delay by 1 line OxE7 NTSCF Bit Toggle NFTOG 4 0 How many lines after lcounr 0 0 0 1 1 NTSC default rollover to toggle F signal NFTOGSIGN 0 Set to low when manual programming 1 Not suitable for user programming NFTOGDELE Delay F transition by one line 0 No delay relative to NFTOG even field 1 Additional delay by 1 line NFTOGDELO Delay F transition by one line 0 No delay relative to NFTOG odd field 1 Additional delay by 1 line OxE8 PAL V Bit Begin PVBEGI 4 0 How many lines after Icount 0 0 1 0 1 PAL default BT 656 rollover to set V high PVBEGSIGN 0 Setto low when manual programming 1 Not suitable for user programming PVBEGDELE Delay V bit going high by one 0 No delay line relative to PVBEG even field 1 Additional delay by 1 line PVBEGDELO Delay V bit going high by one 0 No delay line relative to PVBEG odd field 1 Additional delay by 1 line OxE9 PAL V Bit End PVENDI4 0 How many lines after lcount 1 0 11 0 0 PAL default BT 656 rollover to set V low PVENDSIGN 0 Set to low when manu
214. tions are guaranteed over this range Guaranteed by characterization 3 TTL input values are 0 to 3 volts with rise fall times lt 3 ns measured between the 10 and 90 points SDP timing figures obtained using default drive strength value 0xD5 in register subaddress OxF4 ANALOG SPECIFICATIONS At Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvpnio 3 0 V to 3 6 V Pvpp 1 71 V to 1 89 V operating temperature range unless otherwise noted Recommended analog input video signal range 0 5 V to 1 6 V typically 1 V p p Table 4 Parameter Symbol Test Condition Min Typ Max Unit CLAMP CIRCUITRY External Clamp Capacitor 0 1 uF Input Impedance Clamps switched off 10 MQ Input impedance of Pin 40 FB 20 kQ Large Clamp Source Current 0 75 mA Large Clamp Sink Current 0 75 mA Fine Clamp Source Current 60 uA Fine Clamp Sink Current 60 uA 1 Temperature range Tmn to Tmax 40 C to 85 C The min max specifications are guaranteed over this range 2 Guaranteed by characterization 3 Except Pin 40 FB Rev 0 Page 7 of 112 ADV7188 THERMAL SPECIFICATIONS Table 5 Parameter Symbol Test Conditions Min Typ Max Unit Junction to Case Thermal Resistance Bic 4 layer PCB with solid ground plane 7 6 C W Junction to Ambient Thermal Resistance Still Air Osa 4 layer PCB with solid ground plane 38 1 C W TIMING DIAGRAMS t SDA SCLK u t4 ts gt lt OUTPUT LLC 1 OUTP
215. ue Depending on the setting in the CAGC 1 0 bits this is either e Chroma manual gain value CAGC 1 0 set to chroma manual gain mode CG 11 0 CMG 11 0 Read Write Description CMG 11 0 Write Manual gain for chroma path CG 11 0 Read Currently active gain 0 CG lt 4095 Chroma _ Gain 0 4 4 1024 For example freezing the automatic gain loop and reading back the CG 11 0 register results in a value of 0x47A 1 Convert the readback value to decimal 0x47A 1146d 2 Apply Equation 4 to convert the readback value 1146 1024 1 12 CKE Color Kill Enable Address 0x2B 6 This bit allows the optional color kill function to be switched on or off For QAM based video standards PAL and NTSC and FM based systems SECAM the threshold for the color kill decision is selectable via the CKILLTHR 2 0 bits Rev 0 Page 34 of 112 If color kill is enabled and if the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines color processing is switched off black and white output To switch the color processing back on another 128 consecutive lines with a color burst greater than the threshold are required The color kill option works only for input signals with a modu lated chroma part For component input YPrPb there is no color kill 0 Disables color kill 1 default Enables color kill CKILLTHR 2 0 Color Kill Threshold Address 0x3D 6 4 The CK
216. unctional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability PACKAGE THERMAL PERFORMANCE To reduce power consumption the user is advised to turn off any unused ADCs when using the part The junction temperature must always stay below the maximum junction temperature T max of 125 C The following equation shows how to calculate the junction temperature Tj 2 Ta Max Oja X Wmax where Ta Max 85 C 0j 30 C W Wmas Avpp x Tavpp dE Dvbp x Ipvpp Dvppio x Ipvpp10 a a Pvpp X Ipvpp Ewa ESD SENSITIVE DEVICE Rev 0 Page 9 of 112 ADV7188 PIN CONFIGURATION AND FUNCTION DESCRIPT e z o a rg ogg ripe a dyi ereessiaggoabaz 80 79 78 77 76 75 74 731 72 71 70 69 68 67 66 651 64 63 62 61 vs 1 60 AIN5 HS 2 T 59 AIN11 DGND 3 58 AINA DVDDIO 4 57 AIN10 p15 5 56 AGND P14 6 55 CAPC2 P13 7 AVIS 54 CAPC1 P12 s TOP VIEW 53 AGND DGND 9 Not to Scale 52 CML DVDD 1o 51 REFOUT INT 14 50 AVDD SFL 12 49 CAPY2 TEST2 13 48 CAPY1 DGND 14 47 AGND DVDDIO 15 46 AIN3 TESTS 16 45 AIN9 p11 17 44 AIN2 P10 18 43 AIN8 P9 19 42 AIN1 P8 20 41 AIN7 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
217. ure 50 12 SFL O Subcarrier Frequency Lock This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices Inc digital video encoder 51 REFOUT O Internal Voltage Reference Output Refer to Figure 50 for a recommended capacitor network for this pin 52 CML O The CML pin is a common mode level for the internal ADC s Refer to Figure 50 for a recommended capacitor network for this pin 48 49 CAPY1 CAPY2 ADC s Capacitor Network Refer to Figure 50 for a recommended capacitor network for this pin 54 55 CAPC1 CAPC2 ADC s Capacitor Network Refer to Figure 50 for a recommended capacitor network for this pin Rev 0 Page 11 of 112 ADV7188 ANALOG FRONT END ANALOG INPUT MUXING RGB_IP_SEL INSEL 3 0 INTERNAL 5 MAPPING z E g 2 2 2 es E 9 E BE PAM MOREE FUNCTIONS a 4 d d l l l l d d 4 4 O O Q Q e O o o Q Q o O SDM SEL 1 0 E ADCO SW 3 0 ADC2 SW 3 0 AIN4 Figure 6 Internal Pin Connections E ADC3 SW 3 0 05478 006 The ADV7188 has an integrated analog muxing section that CONNECTING ANALOG SIGNALS allows connecting more than one source of video signal to the TO ADV7188 decoder Figure 6 outlines the overall structure of the input muxing provided in ADV7188 As can be seen in Figure 6 the analog input muxes can be controlled in two ways ADI RECOMMENDED INPU
218. vel to be driven out from the INTRQ pin Rev 0 Page 70 of 112 It is also possible to write to a register in the ADV7188 that manually asserts the INTRQ pin This bit is MPU_STIM_INTRQ INTRQ_OP_SEL 1 0 Interrupt Duration Select Address 0x40 1 0 User Sub Map Table 95 INTRQ_OP_SEL ADV7188 Macrovision Interrupt Selection Bits The user can select between pseudo sync pulse and color stripe detection as follows MV INTRQ _SEL 1 0 Macrovision Interrupt Selection Bits Address 0x40 5 4 User Sub Map Table 96 MV_INTRQ_SEL INTRQ_OP_SEL 1 0 Description 00 default Open drain 01 Drive low when active 10 Drive high when active 11 Reserved Multiple Interrupt Events If interrupt event 1 occurs and then interrupt event 2 occurs before the system controller has cleared or masked interrupt event 1 the ADV7188 does not generate a second interrupt signal The system controller should check all unmasked interrupt status bits since more than one may be active MV_INTRQ_SEL 1 0 Description 00 Reserved 01 default Pseudo sync only 10 Color stripe only 11 Either pseudo sync or color stripe Additional information relating to the interrupt system is detailed in Table 103 Rev 0 Page 71 of 112 ADV7188 PIXEL PORT CONFIGURATION The ADV7188 has a very flexible pixel port that can be config ured in a variety of formats to accommodate downstream ICs
219. w TC 2 2 s Only has an effect if LAGC 1 0 is set to allows adjustment of the luma AGC tracking ol Medium TC 1 s auto gain 001 010 011 or 100 d iiu 1 0 Fast TC 0 25 1 1 Adaptive 0x30 Luma Gain Control 2 LMG 7 0 Luma manual gain canbe usedto x x X X X X X x LMG 11 0 2 1128 dec gain is 1 in Min value NTSC 1024 G 0 90 PAL G program a desired manual chroma gain or NTSC LMG 11 0 1222d gain is 1 0 84 read back the actual used gain value in PAL Max value NTSC 4095 G 3 63 PAL 4095 G 3 35 0x31 VS and FIELD Reserved 0 1 0 Set to default Control 1 HVSTIM Selects where within a line of video 0 Start of line relative to HSE HSE HSYNC end the VS signal is asserted 1 Start of line relative to HSB HSB HSYNC begin NEWAVMODE Sets the EAV SAV mode 0 EAV SAV codes generated to suit ADI encoders 1 Manual VS Field position controlled by Registers 0x32 0x33 and OxE5 OxEA Reserved 0 0 0 Set to default 0x32 VSYNC Field Control Reserved NEWAVMODE bit must be set high 2 0 0 0010 1 Set to default VSBHE 0 VS goes high in the middle of the line even field 1 VS changes state at the start of the line even field VSBHO 0 VS goes high in the middle of the line odd field 1 VS changes state at the start of the line odd field 0x33 VSYNC Field Control Reserved 0 0 0 1 0 0 Set to default 3 VSEHE 0 VS goes low in the middle of the NEWAVMODE bit must be set high line even field 1 VS change
220. y with lower power dissipation It is packaged in a small 80 lead LQFP Pb free package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved ADV7188 TABLE OF CONTENTS Introduction cde ec irira de ees 4 Analog Front End cte tae e a 4 Standard Definition Processor SDP sss 4 Electrical Characteristics eerte 5 Video Specifications cete ere tee eR En 6 Timing Specifications sees 7 Analog Specifications seen 7 Thermal Specifications seen 8 Timing Diagrams cccseesseseseeeseeseeessessessessessessssessesesesesees 8 Absolute Maximum Ratings seen 9 Package Thermal Performance sees 9 ESD Caution E 9 Pin Configuration and Function Descriptions 10 Analog ErontiEnd eee terieta 12 Analog Input Muxing eet tette ient 12 Manual Input Muxing seeeeeeeeeeeeetenentnnnn 14 XTAL Clock Input Pin Functionality eee 15 28 63636 MHz Crystal Operation sse 15 Antialiasing Ellters i ove dstteiten ee tede 15 SCART and Fast Blanking serene 15 Fast Blank Control iet retten 16 Readback of FB Pin Status seen 18 Global Control Registers eerte 19 Power Save Modes ciere NENA 19 Reset Gontro
221. yte mode no code restrictions 10 Byte mode but 0x00 and OxFF prevented 0x00 replaced by 0x01 OxFF replaced by OxFE 11 Reserved The ancillary data packet sequence is explained in Table 68 and Table 69 The nibble output mode is the default mode of output from the ancillary stream when ancillary stream output is enabled This format is in compliance with ITU R BT 1364 Some definitions of the abbreviations used in Table 68 and Table 69 are shown below e EP Even parity for bits B8 to B2 This means that the parity bit EP is set so that an even number of 1s are in bits in B8 to B2 including the parity bit D8 e CS Checksum word The CS word is used to increase confidence of the integrity of the ancillary data packet from the DID SDID and DC through user data words UDWs It consists of 10 bits a 9 bit calculated value and B9 as the inverse of B8 The checksum value B8 to BO is equal to the 9 LSBs of the sum of the 9 LSBs of the DID SDID and DC and all UDWs in the packet Prior to the start of the checksum count cycle all checksum and carry bits are pre set to zero Any carry resulting from the checksum count cycle is ignored EP The MSB B9 is the inverse EP This ensures that restricted codes 0x00 and OxFF do not occur e Line number 9 0 The line number of the line that immediately precedes the ancillary data packet The line number is as per the numbering system in ITU R BT 470 The line number runs from 1 to 625 i

ANALOG DEVICES ADV7188 handbook(1)

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