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ANALOG DEVICES ADV7183B handbook(1)(1)

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1. Bit Subaddress Register Bit Description 61514 3 5 Notes 0 48 Interrupt CCAPD MSKB Masks CCAPD Q bit Mask 2 Unmasks CCAPD bit GEMD MSKB Masks GEMD bit Read Write Unmasks GEMD Q bit CGMS CHNGD MSKB Masks CGMS CHNGD Q bit 2 Unmasks CGMS CHNGD bit Page 2 WSS CHNGD MSKB 0 Masks WSS CHNGD bit 1 Unmasks WSS CHNGD bit Reserved 0 Not used Reserved 0 Not used Reserved 0 Not used MPU STIM INTRO MSKB Masks MPU STIM INTRQ bit Unmasks MPU STIM INTRO bit 0x49 Raw SD OP 50Hz SD 60 Hz signal output These bits Status 3 SD 60 50 2 frame rate at SD 50 Hz signal output cannot be output cleared or Read Only SD_V_LOCK SD vertical sync lock not masked Register established Ox4A SD vertical sync lock established usea this purpose Register SD H LOCK SD horizontal sync lock not Access established Page 2 SD horizontal sync lock established Reserved x Not used SCM_LOCK 0 SECAM lock not established SECAM Lock 1 SECAM lock established Reserved Not used Reserved x Not used Reserved Not used 0x4A Interrupt SD_OP_CHNG_Q No change in SD signal standard These bits Status 3 SD 60 50 Hz frame rate at detected at the input can be input A change in SD signal standardis cleared and Read Only detected at the input masked by Register SD_V_LOCK_CHNG_Q No change in SD vertical sync lock oe sta
2. CVBS on 11 Composite VID_SEL 3 0 The VID SEL bits allow the user to select the input video standard Auto detect PAL B G H 1 D NTSC without pedestal SECAM Auto detect PAL B G H 1 D NTSC M with pedestal SECAM Auto detect PAL N TSC M without pedestal SECAM Auto detect PAL N TSC M with pedestal SECAM TSC J TSC M PAL60 5 4 43 PAL B G H I D 31 PAL N B G H I D without pedestal PAL M without pedestal PAL M PAL Combination N PAL Combination N SECAM with pedestal lolo SECAM with pedestal Rev B Page 71 of 100 ADV7183B Bits Subaddress Register Bit Description 716 5 413 2 Comments Notes 0 01 Video Reserved 0 Set to default Selection ENVSPROC 0 Disable Vsync processor 1 Enable Vsync processor Reserved 0 Set to default BETACAM 0 Standard video input 1 Betacam input enable ENHSPLL 0 Disable Hsync processor 1 Enable Hsync processor Reserved 1 Set to default 0x03 Output SD_DUP_AV Duplicates the AV AV codes to suit 8 bit Control codes
3. EB TM st 15 KSET ANALOG DEVICES Multiformat SDTV Video Decoder ADV7183B FEATURES Multiformat video decoder supports NTSC J M 4 43 PAL B D G H I M N SECAM Integrates three 54 MHz 10 bit ADCs Clocked from a single 27 MHz crystal Line locked clock compatible LLC Adaptive Digital Line Length Tracking ADLLT signal processing and enhanced FIFO management give mini TBC functionality 5 line adaptive comb filters Proprietary architecture for locking to weak noisy and unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated AGC with adaptive peak white mode Macrovision copy protection detection Chroma transient improvement CTI Digital noise reduction DNR Multiple programmable analog input formats Composite video CVBS S Video Y C YPrPb component VESA SMPTE and BetaCam 12 analog video input channels Automatic NTSC PAL SECAM identification Digital output formats 8 bit or 16 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and FIELD GENERAL DESCRIPTION The ADV7183B integrated video decoder automatically detects and converts a standard analog baseband television signal compatible with worldwide standards NTSC PAL and SECAM into 4 2 2 component video data compatible with 16 8 bit CCIR601 CCIR656 The advanced and highly flexible digital output interface ena
4. No connection SETADC sw man 1 ADC1 SW 3 0 Manual muxing control for No connection No connection No connection AIN3 AIN5 AIN6 No connection No connection No connection No connection AIN9 10 11 12 5133333 lt gt 335 5 3 3 gt 3 No connection SETADC sw man 1 OxC4 ADC SWITCH 2 2 SW 3 0 Manual muxing control for ADC2 No connection No connection AIN2 No connection No connection AIN5 AIN6 No connection No connection No connection AIN8 No connection No connection 11 12 3 gt of oJ gt oOo No connection SETADC sw man en 1 Reserved ADC SW MAN EN Enable manual setting of the input signal muxing Disable Enable Rev B Page 84 of 100 ADV7183B Bits Subaddress Register Bit Description 716 1
5. registers for the target parameter must be written to in order of ascending addresses For example for HSB 10 0 write to Address 0x34 first followed by 0x35 other can take place between the two or more writes for the sequence For example for HSB 10 0 write to Address 0x34 first immediately followed by 0x35 Rev B Page 61 of 100 ADV7183B IP2PC REGISTER MAPS Table 82 Common and Normal Page 1 Register Map Details Subaddress Register Name Reset Value rw Dec Hex Input Control 0000 0000 rw 0 0 00 Video Selection 1100 1000 rw 1 0 01 Reserved 0000 0100 rw 2 0 02 Output Control 0000 1100 rw 3 0 03 Extended Output Control 01 0101 rw 4 0 04 Reserved 0000 0000 rw 5 0 05 Reserved 0000 0010 rw 6 0 06 Autodetect Enable 0111 1111 rw 7 0 07 Contrast 1000 0000 rw 8 0x08 Reserved 1000 0000 rw 9 0x09 Brightness 0000 0000 rw 10 0000 0000 rw 11 Default Value Y 0011 0110 rw 12 OxOC Default Value C 0111 1100 rw 13 ADI Control 0000 0000 rw 14 Power Management 0000 0000 rw 15 OxOF Status 1 XXXX XXXX r 16 Ox10 ldent XXXX XXXX r 17 0 11 Status 2 XXXX XXXX r 18 Ox12 Status 3 XXXX XXXX r 19 Ox13 Analog Clamp Control 0001 0010 rw 20 0 14 Digital Clamp Control 1 0100 xxxx rw 21 0 15 Reserved XXXX XXXX rw 22
6. 04997 032 Figure 32 EDTV Data Extraction Table 59 EDTV Access Information Signal Name Register Location Address Register Default Value EDTV1 7 0 EDTV 1 7 0 147d 0x93 Readback only EDTV2 7 0 EDTV 2 7 0 148d 0x94 Readback only EDTV3 7 0 EDTV 3 7 0 149d 0x95 Readback only Rev B Page 48 of 100 ADV7183B CGMS Data Registers Closed Caption Data Registers CGMS1 7 0 Address 0x96 7 0 CCAP1 7 0 Address 0x99 7 0 CGMS2 7 0 Address 0x97 7 0 CCAP2 7 0 Address 0x9A 7 0 CGMS3 7 0 Address 0x98 7 0 Figure 34 shows the bit correspondence between the analog Figure 33 shows the bit correspondence between the analog video waveform and the 2 registers video waveform and the CGMS1 CGMS2 CGMSS registers CGMS3 7 4 are undetermined and should be masked out by software CCAPI 7 contains the parity bit from the first word CCAP2 7 contains the parity bit from the second word Refer to the GDECAD Gemstar Decode Ancillary Data Format Address 0 4 0 section 100 IRE REF CGMS1 7 0 CGMS2 7 0 CGMS3 3 0 70 IRE 49 1ms 0 5us 40IRE l 11 2 ate CRC SEQUENCE 2 23515 2015 04997 033 Figure 33 CGMS Data Extraction Table 60 CGMS Access Information Signal Name Register Location Address Register Default Value CGMS1 7 0 CGMS 1 7 0 150d 0x96 Readback only CGMS2 7 0 CGMS 2 7
7. 9 Change to Figure 13 Change Formatting of Table 15 to 17 19 Change to Figure 8 isis 21 Changes to Lock Related Controls 24 Changes to T ble 34 see 32 Changes to Table Reference in Section 33 Change to PAL Comb Filter Settings 37 Change to NFTOG Section serere 44 Charnges to Table 85 eerte tene pter 68 Changes to Table 86 72 6 05 Rev 0 to Rev Changed Crystal References to 28 MHz Crystal Universal Changes to Features Section 9 04 Revision 0 Initial Version Outline Dimensions eret tette ska a 98 Ordering Guilde etre ete e ER ERE 98 Changes to Table 3 and 8 Changes to Analog Specifications Section sss 8 Changes to tannsa 11 Changes to Clamp Operation Section sss 26 Renamed Figure 14 and Figure 5 30 Changes to Table ia insi 31 Changed Register Address in Luma Gain Section 32 Changed VSBHE VS Default 41 Changes to Table 55 43 Changes to Table 56 retenta retro 45 Changed Comments for CTAPSP 1 0 in Table 85 81 Changes to Table 86 umb 89 Changes to Table 90 Changes to Table 88
8. 91 Changes to Table 89 i ire rettet edente 92 Added Examples Using 27 MHz Clock Section 93 Added XTAL Load Capacitor Value Selection Section 96 Changes to Ordering 99 Rev B Page 3 of 100 ADV7183B INTRODUCTION The ADV7183B is a high quality single chip multiformat video decoder that automatically detects and converts PAL NTSC and SECAM standards in the form of composite S Video and component video into a digital ITU R BT 656 format The advanced and highly flexible digital output interface enables performance video decoding and conversion in line locked clock based systems This makes the device ideally suited for a broad range of applications with diverse analog video charac teristics including tape based sources broadcast sources security surveillance cameras and professional systems ANALOG FRONT END The ADV7183B analog front end comprises three 10 bit ADCs that digitize the analog video signal before applying it to the standard definition processor The analog front end uses differential channels to each ADC to ensure high performance in mixed signal applications The front end also includes a 12 channel input mux that enables multiple video signals to be applied to the ADV7183B Current and voltage clamps are positioned in front of each ADC to ensure the video signal remains within the range of the converter Fine clamping of the vid
9. 283 asa aas 4 output ii LUUULULI III TI VIDEO 1 NVBEG 4 0 0 5 NVEND 4 0 0 4 1BT 656 4 0x04 BIT 7 1 d NFTOG 4 0 0x3 TAPPLIES IF NEWAVMODE 0 MUST BE MANUALLY SHIFTED IF NEWAVMODE 1 Figure 21 NTSC Default BT 656 The Polarity of H V and F is Embedded in the Data 04997 021 FIELD 1 Pec od ims 1 1 21314 15 16 17 18 91 wi 9i 3 wi gs na ae we U Uu uu i VIDEO T 1 1 1 vs 4 OUTPUT FIELD NVBEG 4 0 0x0 NVEND 4 0 0x3 OUTPUT q NFTOG 4 0 0x5 FIELD 2 12621 1263 264 2651 266 267 268 269 270 2711 2721 273 274 275 276 277 MALE 1 1 output VIDEO i OUTPUT i vs i 4 OUTPUT NVBEG 4 0 0x0 NVEND 4 0 0x3 FIELD OUTPUT d NFTOG 4 0 0x5 04997 022 Figure 22 NTSC Typical Vsync Field Positions Using Register Writes in Table 56 Rev B Page 41 of 100 ADV7183B Table 56 Recommended User Settings for NTSC See Figure 22 Register Register Name Write 0x31 Vsync Field Control 1 0 32 Vsync Field Control 2 0 81 0 33 Vsync Field Control 3 0 84 0 34 Hsync Pos Control 1 0 00 0 35 Hsync Pos Control 2 0 00 0 36 Hsync Pos Control 3 Ox7D 0 37 Polarity 5 NTSV V Beg 0 41 OxE6 NTSC V Bit End 0 84 OxE7 NTSC F Bit Tog 0 06 DELAY BEGIN OF VSYNC BY NVBEG 4 0 ADVANCE BEGIN OF
10. MHz Figure 14 PAL Notch Filter Response Rev B Page 29 of 100 ADV7183B 2 0 C Shaping Filter Mode Address 0x17 7 The C shaping filter mode bits allow the user to select from range of low pass filters SH1 to SH5 and wideband mode for the chrominance signal The autoselection options automa tically select from the filter options to give the specified response See settings 000 and 001 in Table 32 Table 32 CSFM Function CSFM 2 0 Description 000 default Autoselect 1 5 MHz bandwidth 001 Autoselect 2 17 MHz bandwidth 010 SH1 011 SH2 100 SH3 101 SH4 110 5 111 Wideband mode COMBINED C ANTIALIAS C SHAPING FILTER C RESAMPLER 0 10 8 2 30 i 50 60 Figure 16 shows responses of SHI narrowest to SH5 1 2 3 4 5 6 FREQUENCY MHz Figure 16 Chroma Shaping Filter Responses widest and the wide band mode in red MAXIMUM VOLTAGE MINIMUM VOLTAGE 04997 016 GAIN OPERATION The gain control within the ADV7183B is performed strictly on a digital basis The input ADCs support a 10 bit range mapped into a 1 6 V analog voltage range Gain correction occurs after the digitization in the form of a digital multiplier One advantage of this architecture over the commonly used programmable gain amplifier PGA before the ADCs is that the gain is now completely independent of supply temperature and process
11. 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V 3 0 to 3 6 V 1 65 V to 2 0 V operating temperature range unless otherwise specified Table 1 Parameter Symbol Test Conditions Min Typ Max Unit STATIC PERFORMANCE Resolution each ADC N 10 Bits Integral Nonlinearity INL BSL at 54 MHz 0 475 0 6 3 LSB Differential Nonlinearity DNL BSL at 54 MHz 0 25 0 5 0 7 2 LSB DIGITAL INPUTS Input High Voltage 2 V Input Low Voltage 0 8 V Input Current lin Pins listed in Note 3 50 50 HA All other pins 10 10 HA Input Capacitance 10 pF DIGITAL OUTPUTS Output High Voltage Von lsource 0 4 mA 2 4 V Output Low Voltage Vor Isink 3 2 mA 0 4 V High Impedance Leakage Current Pins listed in Note 4 50 HA All other pins 10 HA Output Capacitance Cour 20 pF POWER REQUIREMENTS Digital Core Power Supply Dvop 1 65 1 8 2 V Digital Power Supply Dvopio 3 0 33 3 6 V PLL Power Supply 1 65 1 8 2 0 V Analog Power Supply Avon 3 15 33 3 45 V Digital Core Supply Current 82 mA Digital Supply Current Iovopio 2 mA PLL Supply Current 10 5 Analog Supply Current CVBS input 85 mA YPrPb input 180 mA Power Down Current 1 5 Power Up Time tewrup 20 ms Temperature range to Tmax 40 C to 85 C 0 to 70 C for ADV7183BKSTZ The min max specifications are guaranteed over this range 3 Pins 36 and 79 4 P
12. The sync processing on the ADV7183B also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video e Processor This block provides extra filtering of the detected Vsyncs to give improved vertical lock Hsync Processor The Hsync processor is designed to filter incoming Hsyncs that are corrupted by noise providing much improved performance for video signals with stable time base but poor SNR VBI DATA RECOVERY The ADV7183B can retrieve the following information from the input video e Wide screen signaling WSS Copy generation management system CGMS Closed caption CC e Macrovision protection presence e EDTV data e Gemstar compatible data slicing The ADV7183B is also capable of automatically detecting the incoming video standard with respect to Color subcarrier frequency e Field rate Line rate The SPD can configure itself to support PAL B G H I D PAL M N PAL combination N NTSC M NTSC J SECAM 50 Hz 60 Hz NTSC4 43 and PAL60 ADV7183B GENERAL SETUP Video Standard Selection The VID SEL 3 0 bits allows the user to force the digital core into a specific video standard Under normal circumstances this should not be necessary The VID_SEL 3 0 bits default to an autodetection mode that supports PAL NTSC SECAM and variants thereof The following section describes the autodetec tion s
13. ss 33 Digital Noise Reduction DNR sss 34 Combs cte eb eee meme 35 AV Code Insertion and Controls 37 Synchronization Output Signals sss 39 edd vM 46 VBEData Decode eicere eei eterne 47 Pixel Port Configuration oie 59 MPU Port Description 60 Register 33 68 eiie eiie inet eerte 61 Register 61 Sequencer DER 61 IP2PC Register Maps recette eere tenet 62 Register 66 Programming Examples serene 88 Examples in this Section use a 28 MHz Clock 88 Examples Using 27 MHz 92 PCB Layout Recommendations see 94 Analog Interface Inputs seen 94 Power Supply Decoupling 94 PLL esie tee URRHERIHEHRHEHRHEHRHRHAHRHRTIHIE ES 94 Digital Outputs Both Data and 94 Digital 94 Antialiasing 95 2 of 100 ADV7183B Crystal Load Capacitor Value 95 Typical Circuit Connection 96 REVISION HISTORY 9 05 Rev A to Rev B Changesito Table L issi 6 Chatigesito Table 2 aceto ett 7 Changes to Table 3 and Table 4 sse 8 Changes to Table 5
14. 0111 2 2 2 AIN5 1000 AIN3 AIN6 1001 AIN1 YPrPb PB1 AIN4 YPrPb PR1 AIN5 YPrPb 1010 Y2 AIN2 YPrPb PB2 AIN3 YPrPb PR2 AIN6 YPrPb 1011 CVBS7 AIN7 Composite 1100 CVBS8 AIN8 Composite 1101 CVBS9 AIN9 Composite 1110 CVBS10 AIN10 Composite 1111 CVBS11 AIN11 Composite Input Pin ADI Recommended Input Muxing Control Channel No INSEL 3 0 AIN7 41 CVBS7 AIN1 42 CVBS1 Y C1 Y YPrPb1 Y AIN8 43 CVBS8 AIN2 44 CVBS2 Y C2 Y YPrPb2 Y AIN9 45 CVBS9 AIN3 46 CVBS3 Y C3 Y YPrPb2 Pb AIN10 57 CVBS10 AINA 58 CVBS4 1 YPrPb1 Pb 11 59 511 5 60 CVBS5 Y C2 C YPrPb1 Pr AIN12 61 Not available AIN6 62 CVBS6 Y C3 C YPrPb2 Pr ADI recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity Table 9 summarizes how the PCB layout should connect analog video signals to the ADV7183B It is strongly recommended to connect any unused analog input pins to AGND to act as a shield Inputs AIN7 to AIN11 should be connected to when only six input channels are used This improves the quality of the sampling due to better isolation between the channels AINI2 is not under the control of INSEL 3 0 It can be routed to ADCO ADCI ADC2 only by manual muxing See Table 10 for details Rev B Page 14 of 100 MANUAL INPUT MUXING By accessing a set
15. EN function activates function within the ADV7183B that automatically programs the LTA 1 0 and 2 0 to have chroma and luma data match delays for all modes of operation If set manual registers LTA 1 0 and CTA 2 0 are not used If the automatic mode is disabled via setting the AUTO_PDC_EN bit to 0 the values programmed into LTA 1 0 and CTA 2 0 registers become active When AUTO PDC EN is 0 the ADV7183 uses the LTA 1 0 and CTA 2 0 values for delaying luma and chroma samples Refer to the LTA 1 0 Luma Timing Adjust Address 0x27 1 0 and the CTA 2 0 Chroma Timing Adjust Address 0 27 5 3 sections When AUTO_PDC_EN is 1 default the ADV7183B auto matically determines the LTA and CTA values to have luma and chroma aligned at the output CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 The Chroma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples This can be used to compensate for external filter group delay differences in the luma vs chroma path and to allow a different number of pipeline delays while processing the video downstream Review this functionality together with the LTA 1 0 register The chroma can only be delayed advanced in chroma pixel steps One chroma pixel step is equal to two luma pixels The programmable delay occurs after demodulation where one can no longer delay by luma pixel steps For manual programming use the following de
16. Reserved Rev B Page 87 of 100 ADV7183B PROGRAMMING EXAMPLES EXAMPLES IN THIS SECTION USE A 28 MHz CLOCK Mode 1 CVBS Input Composite Video on AIN5 All standards are supported through autodetect 8 bit 4 2 2 ITU R BT 656 output on P15 to 8 Table 87 Mode 1 CVBS Input Register Address Register Value Notes 0x00 0x04 CVBS input on AIN5 0x15 0x00 Slow down digital clamps 0x17 0x41 Set CSFM to SH1 Ox1D 0 40 Enable 28 MHz crystal OxOF 0x40 TRAQ 0 16 Power down 1 and 2 0x3D OxC3 MWE enable manual window 4 to 36 0 50 0 04 Set DNR threshold to 4 for flat response OxOE 0 80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0 50 0 20 Recommended setting 0 52 0 18 Recommended setting 0 58 OxED Recommended setting 0 77 OxC5 Recommended setting 0 7 0 93 Recommended setting 0 70 0 00 Recommended setting 0 90 0 9 Recommended setting 0 91 0 40 Recommended setting 0 92 Ox3C Recommended setting 0 93 Recommended setting 0 94 OxdD Recommended setting OxCF 0 50 Recommended setting OxDO Ox4E Recommended setting Recommended setting OxE5 0 51 Recommended setting OxD5 Recommended setting 0 07 Recommended setting OxE4 Ox3E Recommended setting OxE9 Ox3E Recommended setting
17. Rev B Page 65 of 100 ADV7183B REGISTER MAP DETAILS The following registers are located in the Common Map and Register Access Page 2 Table 84 Interrupt Page 2 Register Map Bit Names Register Reset Subaddress Name Value rw Dec Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Interrupt 0001 rw 64 0 40 INTRQ_DUR INTRQ_DUR MV_INTRQ_ MV_INTRQ_ MPU_STIM_ INTRQ_OP_ INTRQ_OP_ Config 0 x000 _SEL 1 _SEL O SEL 1 SEL O INTRO SEL 1 SEL O Reserved 65 0 41 Interrupt r 66 0 42 MV 5 5 50 SD UNLOCK SD LOCK Status 1 Q GO Q Interrupt x000 w 67 0x43 MV_PS_CS_ SD_FR_CHN SD_UNLOCK SD_LOCK_ Clear 1 0000 CLR G_CLR _ Interrupt 000 rw 68 0 44 MV 5 5 50 SD UNLOCK SD_LOCK_ Maskb 1 0000 MSKB MSKB _MSKB MSKB Reserved 69 0x45 Interrupt 70 0 46 MPU_STIM_ WSS_ CGMS_ GEMD_Q CCAPD_Q Status 2 INTRQ_Q CHNGD_Q CHNGD_Q Interrupt Oxxx w 71 0x47 MPU_STIM_ WSS_ CGMS_CHN GEMD_CLR CCAPD_CLR Clear 2 0000 INTRQ_CLR CHNGD_CLR GD_CLR Interrupt Oxxx rw 72 0x48 MPU_STIM_ WSS CGMS GEMD CCAPD_ Maskb 2 0000 INTRQ_ CHNGD_ CHNGD_ MSKB MSKB MSKB MSKB MSKB Raw 73 0 49 SCM LOCK 50 1 SDV LOCK SD OP Status 3 50HZ Interrupt r 74 0 4 PAL SW LK SCM_LOCK_ SD AD SD 1 50 VLOCK SD Status 3 Q Q _CHNG_Q CHNG CHNG Q Inter
18. Status 1 1 SDinputhas caused the decoder These bits to go from an un locked state toa can be Read Only locked state cleared or SD UNLOCK Q 0 No change masked in Registers Register 1 SD input has caused the decoder 0x43 and Access to go from a locked state to an 0x44 Page 2 unlocked state respectively Reserved x Reserved x Reserved SD FR CHNG 0 No change 1 Denotes a change in the free run status MV PS CS 0 No change 1 Pseudo sync color striping detected See MV INTRO SEL 1 0 Macrovision Interrupt Selection Bits Address 0x40 Interrupt Space 5 4 for selection Reserved 0 43 Interrupt SD LOCK CLR 0 Donotclear Clear 1 1 Clears SD_LOCK_Q bit SD_UNLOCK_CLR 0 Do not clear Write Only 1 Clears SD UNLOCK Q bit Reserved 0 Not used Register Reserved 0 Not used Access Page 2 Reserved 0 Not used SD FR CHNG CLR 0 Do not clear 1 Clears SD FR CHNG Q bit PS CS CLR 0 Do not clear 1 Clears MV PS CS Q bit Reserved x Not used Rev B Page 67 of 100 ADV7183B Bit Subaddress Register Bit Description Comments Notes 0x44 Interrupt SD_LOCK_MSKB Masks SD_LOCK_Q bit Mask 1 Unmasks SD_LOCK_Q bit SD UNLOCK MSKB Masks SD UNLOCK Q bit Read Write Unmasks SD UNLOCK Q bit Register Reserved Not used Reserved Not used Register Access Reserved Not us
19. 07 6 Setting AD SECAM EN to 0 disables autodetection of SECAM Setting AD SECAM EN to 1 default enables detection AD NA443 EN Enable Autodetection of NTSC 443 Address 0x07 5 Setting AD N443 EN to 0 disables the autodetection of NTSC style systems with a 4 43 MHz color subcarrier Setting AD N443 EN to 1 default enables the detection AD P60 EN Enable Autodetection of PAL60 Address 0x07 4 Setting P60 EN to 0 disables autodetection of PAL systems with a 60 Hz field rate Setting P60 EN to 1 default enables the detection AD PALN EN Enable Autodetection of PAL N Address 0x07 3 Setting AD PALN EN to 0 disables the detection of the PAL standard Setting AD PALN EN to 1 default enables the detection AD PALM EN Enable Autodetection of PAL M Address 0x07 2 Setting AD PALM EN to 0 disables the autodetection of PAL M Setting AD PALM EN to 1 default enables the detection AD NTSC EN Enable Autodetection of NTSC Address 0x07 1 Setting AD NTSC EN to 0 disables the detection of standard NTSC Setting AD NTSC EN to 1 default enables the detection AD PAL EN Enable Autodetection of PAL Address 0x07 0 Setting AD PAL EN to 0 disables the detection of standard PAL Setting PAL EN to 1 default enables the detection SELECT THE RAW LOCK SIGNAL SRLS TIME WIN FREE RUN LOCK TAKE LOCK INTO ACCOUNT FSCLE COUNTER INTO LOCK COUNTER OUT OF
20. 50 OxOE 0x50 0x52 0x58 0x77 0 7 0 70 0 90 0 91 0 92 0 93 0 94 OxCF OxD6 OxE5 OxD5 OxD7 OxE4 OxE9 OxEA OxOE 0x83 0x01 0x00 0 41 0 40 0 40 OxC3 OxE4 OxFA 0x16 Ox0A 0x80 0x20 0x18 OxED OxC5 0 93 0 00 OxC9 0 40 Ox3C OxCA OxdD 0x50 Ox4E OxDD 0x51 OxAO OxEA Ox3E Ox3E OxOF 0x00 CVBS AIN4 Force PAL only mode Enable PAL autodetection only Slow down digital clamps Set CSFM to SH1 Enable 28 MHz crystal TRAQ MWE enable manual window BGB to 36 Stronger dot crawl reduction Power down ADC 1 and ADC 2 Set higher DNR threshold ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Rev B Page 91 of 100 ADV7183B EXAMPLES USING 27 MHz CLOCK Mode 1 CVBS Input Composite Video AIN5 All standards are supported through autodetect 8 bit 4 2 2 ITU R BT 656 output on P15 to 8 Table 91 Mode 1 CVBS Input Register Address Register Va
21. For all NTSC PAL Vsync timing controls both the V bit in the AV code and the Vsync on the VS pin are modified PFTOGDELO PAL Field Toggle Delay on Odd Field Address 0xEA 7 When PFTOGDELO is 0 default there is no delay Setting PFTOGDELO to 1 delays the F toggle transition on an odd field by a line relative to PFTOG PFTOGDELE PAL Field Toggle Delay on Even Field Address 0xEA 6 When PFTOGDELE is 0 there is no delay Setting PFTOGDELE to 1 default delays the F toggle transition on an even field by a line relative to PFTOG PFTOGSIGN PAL Field Toggle Sign Address 5 Setting PFTOGSIGN to 0 delays the field transition Set for user manual programming Setting PFTOGSIGN to 1 default advances the field transition Not recommended for user programming PFTOG PAL Field Toggle Address 4 0 The default value of PFTOG is 00011 indicating the PAL field toggle position For all NTSC PAL Field timing controls the bit in the AV code and the field signal on the FIELD DE pin are modified ADVANCE TOGGLE OF FIELD BY PTOG 4 0 NOT VALID FOR USER PROGRAMMING DELAY TOGGLE OF FIELD BY PFTOG 4 0 YES 1 ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE 04997 030 FIELD TOGGLE Figure 30 PAL F Toggle SYNC PROCESSING The ADV7183B has two additional sync processing blocks that postprocess the raw synchronization information extracted from the di
22. LUMA BY A CHROMA TRANSITION SIGNAL A ORIGINAL SLOW CHROMA DEMODULATED TRANSITI N PRIOR TO CTI CHROMA SIGNAL SHARPENED CHROMA TRANSITION THE 5 OUTPUT OF CTI 5 Figure 18 CTI Luma Chroma Transition Rev B Page 33 of 100 ADV7183B The chroma transient improvement block examines the input video data It detects transitions of chroma and can be programmed to steepen the chroma edges in an attempt to artificially restore lost color bandwidth The CTI block however operates only on edges above a certain threshold to ensure that noise is not emphasized Care has also been taken to ensure that edge ringing and undesirable saturation or hue distortion are avoided Chroma transient improvements are needed primarily for signals that experienced severe chroma bandwidth limitations For those types of signals it is strongly recommended to enable the CTI block CTI_EN Chroma Transient Improvement Enable Address 0 4 0 The CTI EN bit enables the CTI function If set to 0 the CTI block is inactive and the chroma transients are left untouched Setting CTI EN to 0 disables the CTI block Setting EN to 1 default enables the CTI block CTI AB EN Chroma Transient Improvement Alpha Blend Enable Address Ox4D 1 The CTI AB EN bit enables an alpha blend function within the CTI block If set to 1 the alpha blender mixes the transient improved chroma with the original signal The sharpness
23. OxEA OxOF Recommended setting OxOE 0x00 Recommended setting Rev B Page 88 of 100 Mode 2 S Video Input AIN1 4 All standards are supported through autodetect 8 bit ITU R BT 656 output on P15 to P8 Table 88 Mode 2 S Video Input ADV7183B Register Address Register Value Notes 0x00 0x15 0x3A 0x1D OxOF 0 50 OxOE 0x50 0x52 0x58 0x77 0 7 0 70 0 90 0 91 0 92 0 93 Ox 94 OxCF OxD6 OxE5 OxD5 OxD7 OxE4 OxE9 OxEA OxOE 0x06 0x00 0x12 0x40 0x40 OxC3 OxE4 0 04 0 80 0 20 0 18 OxED OxC5 0 93 0 00 OxC9 0 40 Ox3C OxCA OxdD 0x50 Ox4E OxDD 0x51 OxAO OxEA Ox3E Ox3E OxOF 0x00 Y1 Slow down digital clamps Power down ADC 2 Enable 28 MHz crystal TRAQ MWE enable manual window BGB to 36 Set DNR threshold to 4 for flat response ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended
24. TC 0 1 sec 11 Determined by the ADV7183B depending on the I P video parameters DCFE Digital Clamp Freeze Enable Address 0x15 4 This register bit allows the user to freeze the digital clamp loop at any time It is intended for users who would like to do their own clamping Users should disable the current sources for analog clamping via the appropriate register bits wait until the digital clamp loop settles and then freeze it via the DCFE bit When is 0 default the digital clamp is operational When DCFE is 1 the digital clamp loop is frozen LUMA FILTER Data from the digital fine clamp block is processed by three sets of filters The data format at this point is CVBS for CVBS input or luma only for Y C and YPrPb input formats e LumaAntialias Filter YAA The ADV7183B receives video at a rate of 27 MHz For 4x oversampled video the ADCs sample at 54 MHz and the first decimation is performed inside the DPP filters Therefore the data rate into the SDP core is always 27 MHz The ITU R BT 601 recommends a sampling frequency of 13 5 MHz The luma antialias filter decimates the oversampled video using a high quality linear phase low pass filter that preserves the luma signal while at the same time attenuating out of band components The luma antialias filter has a fixed response LumaShaping Filters YSH The shaping filter block is a programmable low pass filter with a wide variety of responses It
25. another 128 consecutive lines with a color burst greater than the threshold are required The color kill option works only for input signals with a modu lated chroma part For component input YPrPb there is color kill Setting CKE to 0 disables color kill Setting CKE to 1 default enables color kill Description CKILLTHR 2 0 SECAM NTSC PAL 000 No color kill Kill at 0 596 001 Kill at 596 Kill at 1 596 010 Kill at 796 Kill at 2 596 011 Kill at 896 Kill at 4 096 100 default Kill at 9 596 Kill at 8 596 101 Kill at 1596 Kill at 16 096 110 Kill at 3296 Kill at 32 096 111 Reserved for ADI internal use only do not select CHROMA TRANSIENT IMPROVEMENT CTI The signal bandwidth allocated for chroma is typically much smaller than that of luminance In the past this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance The uneven bandwidth however can lead to visual artifacts in sharp color transitions At the border of two bars of color both components luma and chroma change at the same time see Figure 18 Due to the higher bandwidth the signal transition of the luma component is usually much sharper than that of the chroma component The color edge is not sharp but blurred in the worst case over several pixels LUMA SIGNAL WITH TRANSITION ACCOMPANIED
26. gy ug gu wu VIDEO E 22 P OUTPUT vs 4 4 OUTPUT FIELD PVBEG 4 0 0x1 PVEND 4 0 0x4 7 OUTPUT k 4 0 0 6 FIELD 2 1310 311 312 313 314 315 316 317 318 319 320 321 322 323 336 EL ovur LLL uu u uU uU VIDEO Li OUTPUT i 4 OUTPUT gt PVBEG 4 0 0 1 PVEND 4 0 0x4 FIELD 4 OUTPUT 4 PFTOG 4 0 0 6 Figure 27 PAL Typical Vsync Field Positions Using Register Writes in Table 57 04997 027 Rev B Page 44 of 100 ADV7183B DELAY BEGIN OF VSYNC BY PVBEG 4 0 ADVANCE BEGIN OF VSYNC BY PVBEG 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO 0 0 1 1 ADDITIONAL ADDITIONAL DELAY BY DELAY BY 1 LINE 1 LINE 1 0 0 1 ADVANCE BY ADVANCE BY 0 5 LINE 0 5 LINE 04997 028 Figure 28 PAL Vsync Begin PVBEGDELO PAL Vsync Begin Delay on Odd Field Address 0 8 7 When PVBEGDELO is 0 default there is no delay Setting PVBEGDELO to 1 delays Vsync going high on an odd field by a line relative to PVBEG PVBEGDELE PAL Vsync Begin Delay on Even Field Address OxE8 6 When PVBEGDELE is 0 there is no delay Setting PVBEGDELE to 1 default delays Vsync going high on an even field by a line relative to PVBEG PVBEGSIGN PAL Vsync Begin Sign Address 0xE8 5 Setting PVBEGSIGN to 0 delays the beginning of Vsync Set for user manual pro
27. 0 The peak white and average video algorithms determine the gain based on measurements taken from the active video The PW UPD bit determines the rate of gain change The LAGC 2 0 must be set to the appropriate mode to enable the peak white or average video mode in the first place For more information refer to the LAGC 2 0 Luma Automatic Gain Control Address 0x2C 7 0 section Setting PW UPD to 0 updates the gain once per video line Setting PW UPD to 1 default updates the gain once per field Chroma Gain 0 Chroma Automatic Gain Control Address 0x2C 1 0 The two bits of the Color Automatic Gain Control mode select the basic mode of operation for automatic gain control in the chroma path Table 38 CAGC Function CAGC 1 0 Description 00 Manual fixed gain use CMG 11 0 01 Use luma gain for chroma 10 default Automatic gain based on color burst 11 Freeze chroma gain BETACAM Description 0 default Assuming YPrPb is selected as input format Selecting PAL with pedestal selects MII Selecting PAL without pedestal selects SMPTE Selecting NTSC with pedestal selects MII Selecting NTSC without pedestal selects SMPTE 1 0 Chroma Automatic Gain Timing Address 0x2D 7 6 The chroma automatic gain timing register allows the user to influence the tracking speed of the chroma automatic gain con trol This register has an effect only if the CAGC 1 0 register is set to 10 aut
28. 0 Select the drive 0 Low drive strength 1x Strength strength for the sync output 1 Medium low drive signals strength 2x 0 Medium high drive strength 3x 1 High drive strength 4x DR STR C 1 0 Select the drive 010 Low drive strength 1x strength for the clock output 1 Medium low drive signal strength 2 110 Medium high drive strength 3 111 High drive strength 4x DR STR 1 0 Select the drive 010 Low drive strength 1 strength for the data output 0 1 Medium low drive signals Can be increased or strength 2 decreased for EMC or crosstalk 110 Medium high drive reasons strength 3x 111 High drive strength 4x Reserved x x No delay OxF8 IF Comp IFFILTSEL 2 0 IF filter selection for 0 0 Bypass mode 0 dB Control PAL and NTSC 2 MHz 5MHz NTSC filters 0 1 3 dB 2 dB 0 0 6dB 3 5 dB 0 1 10 dB 5 dB 1 0 Reserved 3 MHz 6 MHz PAL filters 1 1 2dB 2 dB 1 0 5dB 3 dB 1 1 7 dB 5 dB Reserved 9 5 EXTEND VS MAX FREQ 0 Limit maximum Vsync Control frequency to 66 25 Hz 475 lines frame 1 Limit maximum Vsync frequency to 70 09 Hz 449 lines frame EXTEND VS MIN FREQ Limit minimum Vsync frequency to 42 75 Hz 731 lines frame Limit minimum Vsync frequency to 39 51 Hz 791 lines frame VS COAST 01 01 0 Auto coast mode This value sets up the 0 1 50 Hz coast mode coast 110 60 Hz coast mode Sono 111 Reserved
29. 0 151d 0x97 Readback only CGMS3 3 0 CGMS 3 3 0 152d 0x98 Readback only 10 5 0 25us 12 9118 7 CLOCK RUN IN 1 7 0 2 7 0 1 2 34 5 6 7 o 1 2 3145 6 7 50 IRE 1 R 1 BYTEO 1 AO IRE REFERENCE COLOR BURST 9 CYCLES FREQUENCY Fac 3 579545MHz AMPLITUDE lt 40 IRE 10 003us 3 27 38215 33 764us B Figure 34 Closed Caption Data Extraction Table 61 CCAP Access Information Signal Name Register Location Address Register Default Value CCAP1 7 0 CCAP1 7 0 153d 0x99 Readback only CCAP2 7 0 CCAP2 7 0 154d Readback only Rev B Page 49 of 100 ADV7183B Letterbox Detection Incoming video signals may conform to different aspect ratios 16 9 wide screen of 4 3 standard For certain transmissions in the wide screen format a digital sequence WSS is transmitted with the video signal If a WSS sequence is provided the aspect ratio of the video can be derived from the digitally decoded bits WSS contains In the absence of a WSS sequence letterbox detection may be used to find wide screen signals The detection algorithm examines the active video content of lines at the start and end of a field If black lines are detected this indicates that the picture currently displayed is in wide screen format The active video content luminance magnitude over a line of video is summed together At the end of a line
30. 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 0 1 0 1 1 0 0 500 5 0 0 0 0 0 1 0 0 Data count 6 0 0 CCAP 7 4 0 0 User data words 7 0 0 CCAP Word1 3 0 0 0 User data words 8 0 0 CCAP Word2 7 4 0 0 User data words 9 0 0 CCAP Word2 3 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 71 NTSC CCAP Data Full Byte Mode Byte DI9 0181 D 7 0161 0151 0141 0131 0121 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 0 1 0 1 1 0 0 500 5 0 0 0 0 0 1 0 0 Data count 6 CCAP Word1 7 0 0 0 User data words 7 CCAP Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0 200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0 200 10 ICS 8 CS 8 CS 7 CS 6 CS 5 5 4 CS 3 CS 2 CS 1 CS 0 Checksum Rev B Page 54 of 100 ADV7183B NTSC CCAP Data PAL CCAP Data Half byte output mode is selected by setting CDECAD 0 Half byte output mode is selected by setting CDECAD 0 the full byte mode is enabled by CDECAD 1 See the full byte output mode is selected by setting CDECAD 1 GDECAD Gemstar Decode Ancillary Data Format See the GDECAD G
31. 0x16 Shaping Filter Control 0000 0001 rw 23 0x17 Shaping Filter Control 2 1001 0011 rw 24 0 18 Comb Filter Control 1111 0001 rw 25 0 19 Reserved XXXX XXXX rw 26to 28 0x1A to Ox1C ADI Control 2 0000 Oxxx rw 29 0x1D Reserved XXXX XXXX rw 30 to 38 to 0x26 Pixel Delay Control 0101 1000 rw 39 0x27 Reserved XXXX XXXX rw 40 to 42 0x28 to 0x2A Misc Gain Control 1110 0001 rw 43 0x2B AGC Mode Control 1010 1110 rw 44 0 2 Chroma Gain Control 1 1111 0100 rw 45 Ox2D Chroma Gain Control 2 0000 0000 rw 46 0 2 Luma Gain Control 1 1111 rw 47 Ox2F Luma Gain Control 2 XXXX XXXX rw 48 0 30 Vsync Field Control 1 0001 0010 rw 49 0 31 Vsync Field Control 2 0100 0001 rw 50 0 32 Vsync Field Control 3 1000 0100 rw 51 0 33 Hsync Position Control 1 0000 0000 rw 52 0 34 Hsync Position Control 2 0000 0010 rw 53 0 35 Hsync Position Control 3 0000 0000 rw 54 0 36 Polarity 0000 0001 rw 55 0x37 NTSC Comb Control 1000 0000 rw 56 0x38 PAL Comb Control 1100 0000 rw 57 0x39 ADC Control 0001 0000 rw 58 Ox3A Reserved XXXX XXXX rw 59 to 60 Manual Window Control 0100 0011 rw 61 0x3D Rev B Page 62 of 100 ADV7183B Subaddress Register Name Reset Value rw Dec Hex Reserved XXXX XXXX rw 62 to 64 to 0x40 Resample Control 0100 0001 rw
32. 1 delays Vsync from going low on an odd field by a line relative to NVEND NVENDDELE NTSC Vsync End Delay on Even Field Address 0xE6 6 When NVENDDELE is set to 0 default there is delay Setting NVENDDELE to 1 delays Vsync from going low on an even field by a line relative to NVEND NVENDSIGN NTSC End Sign Address 0xE6 5 Setting NVENDSIGN to 0 default delays end of Vsync default Set for user manual programming Setting NVENDSIGN to 1 advances the end of Vsync Not recommended for user programming NVEND NTSC 4 0 Vsync End Address 0xE6 4 0 The default value of NVEND is 00100 indicating the NTSC Vsync end position For all NTSC PAL Vsync timing controls both the V bit in the AV code and the Vsync on the VS pin are modified NFTOGDELO NTSC Field Toggle Delay on Odd Field Address OxE7 7 When NFTOGDELO is 0 default there is no delay Setting NFTOGDELO to 1 delays the field toggle transition on an odd field by a line relative to NFTOG NFTOGDELE NTSC Field Toggle Delay on Even Field Address 0 7 6 When NFTOGDELE 0 there is no delay Setting NFTOGDELE to 1 default delays the field toggle transition on an even field by a line relative to NFTOG ADVANCE TOGGLE OF FIELD BY NFTOG 4 0 NOT VALID FOR USER PROGRAMMING DELAY TOGGLE OF FIELD BY NFTOG 4 0 ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE 04997 025 FIELD TOGGLE Figure
33. 2 is 0 default the ADC is in normal operation When PWRDN ADC 2 is 1 ADC2 is powered down RESET CONTROL Chip Reset RES Address 0x0F 7 Setting this bit equivalent to controlling the RESET pin on the ADV7183B issues a full chip reset All registers are reset to their default values Some register bits do not have a reset value specified They keep their last written value Those bits are marked as having a reset value of x in the register table After the reset sequence the part immediately starts to acquire the incoming video signal After setting the RES bit or initiating a reset via the pin the part returns to the default mode of operation with respect to its primary mode of operation PC bits are loaded with their default values making this bit self clearing Executing a software reset takes approximately 2 ms However it is recommended to wait 5 ms before any further PC writes are performed The master controller receives a no acknowledge condition on the ninth clock cycle when chip reset is implemented See the MPU Port Description section When RES is 0 default operation is normal When RES is 1 the reset sequence starts Rev B Page 16 of 100 ADV7183B GLOBAL PIN CONTROL Three State Output Drivers TOD Address 0 03 6 This bit allows the user to three state the output drivers of the ADV7183B Upon setting the TOD bit the P15 to PO HS VS FIELD and SFL pins are three s
34. 55 HS Timing Parameters see Figure 20 HSE 10 0 HS End Address 0x34 2 0 Address 0x36 7 0 The position of this edge is controlled by placing a binary number into HSE 10 0 The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FF 00 00 XY see Figure 20 HSE is set to 00000000000b which is 0 LLC1 clock cycles from Count 0 The default value of HSE 9 0 is 000 indicating that the HS pulse ends zero pixels after falling edge of HS For example 1 To shift the HS toward active video by 20 LLCIs add 20 LLCIs to both HSB and HSE that is HSB 10 0 00000010110 HSE 10 0 00000010100 2 To shift the HS away from active video by 20 11 15 add 1696 11 15 to both HSB and HSE for NTSC that is HSB 10 0 11010100010 HSE 10 0 11010100000 1696 is derived from the NTSC total number of pixels 1716 To move 20 LLC1s away from active video is equal to subtracting 20 from 1716 and adding the result in binary to both HSB 10 0 and HSE 10 0 PHS Polarity HS Address 0 37 7 The polarity of the HS pin can be inverted using the PHS bit When PHS is 0 default HS is active high When PHS is 1 HS is active low Characteristic HS Begin Adjust HS to Active Video Active Video Total LLC1 HSB 10 0 HS End Adjust LLC1 Clock Cycles Samples Line Clock Cycles Standard Default HSE 10 0 Default Cin Figure 20 Default
35. D in Figure 20 E in Figure 20 NTSC 00000000010b 00000000000b 272 720Y 720C 1440 1716 NTSC Square Pixel 00000000010b 00000000000b 276 640Y 640C 1280 1560 PAL 00000000010b 00000000000b 284 720Y 720 1440 1728 e VIDEO el wat SAV Figure 20 HS Timing Rev B Page 39 of 100 04997 020 ADV7183B VS and FIELD Configuration The following controls allow the user to configure the behavior of the VS and FIELD output pins and to generate embedded AV codes encoder compatible signals via NEWAVMODE PVS PF e HVSTIM VSBHE VSEHE NTSC control NVBEGDELO NVBEGDELE NVBEGSIGN NVBEG 4 0 NVENDDELO NVENDDELE NVENDSIGN NVEND 4 0 NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG 4 0 e For PAL control PVBEGDELE PVBEGSIGN PVBEG 4 0 PVENDDELO PVENDDELE PVENDSIGN PVEND 4 0 PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG 4 0 NEWAVMODE New Mode Address 0x31 4 When NEWAVMODE is 0 EAV SAV codes are generated to suit ADI encoders No adjustments are possible Setting NEWAVMODE to 1 default enables the manual posi tion of the Vsync Field and AV codes using Register 0x34 to Register 0x37 and Register OxE5 to Register Default register settings are CCIR656 compliant see Figure 21 for NTSC and Figure 26 for PAL For recommended man
36. Dvss 6 000 MPU INTERFACE CONTHOLLINES DVDDIO RESET 100nF DGND ADV7183B ADV7183B 1 POWER SUPPLY DECOUPLING FOR 1 1 POWER POWER SUPPLY DECOUPLING FOR 1 1 POWER POWER SUPPLY 1 DECOUPLING FOR 1 0 01uF POWER SUPPLY DECOUPLING FOR 1 Vpenp POWER MULTI FORMAT PIXEL PORT P15 P8 8 BIT ITU R 656 PIXEL DATA 27MHz 1 7 0 Cb AND Cr 16 BIT ITU R BT 656 PIXEL DATA 13 5MHz 5 16 BIT ITU R 81 656 PIXEL 13 5MHz ____ 2 27MHz OUTPUT CLOCK 13 5MHz OUTPUT CLOCK OUTPUT ENABLE INTERRUPT O P SFL O P HS O P VS O P FIELD O P 1 69kQ 10nF 82nF PVDD DGND 04997 045 Figure 46 Typical Connection Diagram Rev B Page 97 of 100 ADV7183B OUTLINE DIMENSIONS TOP VIEW PINS DOWN 0 20 0 09 7 s AN Y uu 3 0 10 COPLANARITY 5 0 2 LEADPITCH ROTATED 90 CCW 0 22 COMPLIANT TO JEDEC STANDARDS MS 026 BEC Figure 47 80 Lead Low Profile Quad Flat Package LOFP ST 80 2 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADV7183BKSTZ 0 C to 70 80 lead Low Profile Quad Flat Package LOFP ST 80 2 ADV7183B
37. Enables the use of 0 Auto selection of best automatic WYSFN filter filter 1 Manual select filter using WYSFMI4 01 0 19 Comb PSFSEL 1 0 Controls the signal 0 01 Narrow Filter bandwidth that is fed to the comb 0 1 Medium Control filters PAL 1 0 Wide 1 1 Widest NSFSEL 1 0 Controls the signal 0 69 Narrow bandwidth that is fed to the comb 11 Medium filters NTSC 1 Medium 1 1 Wide Reserved 1 1 1 1 Set as default 0x1D ADI Reserved 010 x Setas default Control2 vs COMP 0 Enabled 1 Disabled EN28XTAL 0 Use 27 MHz crystal 1 Use 28 MHz crystal TRI_LLC 0 LLC pin active 1 LLC pin three stated Rev B Page 76 of 100 ADV7183B Bits Subaddress Register Bit Description 7161543 Comments Notes 0 27 Pixel Delay LTA 1 0 timing adjust allows No delay CVBS mode Control the user to specify a timing LTA 1 0 00b difference between chroma and FRA 37 ns S Video mode luma samples LTA 1 0 01b 2 clk 74 ns early YPrPb mode LTA 1 0 01b Luma 1 clk 37 ns early Reserved Set to zero CTA 2 0 Chroma timing adjust Not valid setting CVBS mode allows a specified timing difference olol1 Chroma 2 pixels early CTA 2 0 011b between the luma and chroma 1 pixel
38. HUE 7 0 is 1 bit 0 7 The hue adjustment value is fed into the AM color demodulation block Therefore it applies only to video signals that contain chroma information in the form of an AM modulated carrier CVBS or Y C in PAL or NTSC It does not affect SECAM and does not work on component video inputs YPrPb Table 28 HUE Function functional overlap with the Hue 7 0 register Table 25 50 OFF Cb Function HUE 7 0 Description 0x00 default Phase of the chroma signal 0 Ox7F Phase of the chroma signal 90 0x80 Phase of the chroma signal 90 SD OFF Cb 7 0 Description 0x80 default 0x00 OxFF 0 offset applied to the Cb channel 312 offset applied to the Cb channel 312 mV offset applied to the Cb channel SD OFF Cr 7 0 SD Offset Cr Channel Address 0xE2 7 0 This register allows the user to select an offset for data on the Cr channel only and adjust the hue of the picture There is a func tional overlap with the Hue 7 0 register Table 26 SD OFF Cr Function SD OFF Cti 7 0 Description 0x80 default 0 offset applied to the Cr channel 0x00 312 mV offset applied to the Cr channel OxFF 312 mV offset applied to the Cr channel BRI 7 0 Brightness Adjust Address 0x0A 7 0 This register controls the brightness of the video signal It allows the user to adjust the brightness of the picture Table 27 BRI Function BRI 7 0 Descripti
39. Kill at 8 5 Kill at 16 Kill at 32 o Reserved CKE 1 enables the color kill function and must be enabled for CKILLTHR 2 0 to take effect Reserved Set to default Rev B Page 80 of 100 ADV7183B Bits Subaddress Register Bit Description 716 5 413 2 Comments Notes 0 41 Resample Reserved 0 Set to default Control SFL_INV Controls the behavior of 0 SFL compatible with the PAL switch bit ADV7190 ADV7191 ADV7194 encoders 1 SFL compatible with ADV717x ADV7173x encoders Reserved 0 Set to default 0x48 Gemstar GDECEL 15 8 See the Comments 0 GDECEL 15 0 16 LSB Line 10 Control 1 column individual enable bits that MSB Line 25 0x49 Gemstar GDECEL 7 0 See Comments select the lines of video Default Do not Control 2 column even field Lines 10 to 25 check for Gemstar that the decoder checks compatible data on for Gemstar compatible any lines 10 to 25 in data even fields Ox4A Gemstar GDECOL 15 8 See the Comments 0 GDECOL 15 0 16 LSB Line 10 Control 3 column individual enable bits that MSB Line 25 select the lines of video Default Do not 0x4B Gemstar GDECOL 7 0 See Comments 0 101 0 0 0 0 odd field lines 10 to 25 check for Gemst
40. Processor SDP sss 4 Functional Block Diagram seen 5 aE e 6 Electrical Characteristics seen 6 ote peto en 7 Timing Specifications essent 8 Analog Specifications 8 Thermal Specifications 9 Timing 9 Absolute Maximum Ratings essent 10 ESD Caton ia 10 Pin Configuration and Function 11 Analog Front End 13 Analog Input 13 Manual Input 15 Global Control Registers 16 Power Save eee hd 16 Reset Control 16 Global Pin Control tret 17 Global Status Registers aeree rper reser rae 19 Identificati n ss 19 StAtUs ER 19 Autodetection 19 SEALS 2 A 19 STATUS 19 Standard Definition Processor 0 20 SD Luria Pati 20 SD Chroma Path enr emper p eed arts 20 SYNG Processing vinci ETHER ERU REX HN 21 VBI Data Recovery eee eig 21 General cciam ENNIO Des 21 Color 23 Glamp OBperatlo fia 25 Ea FI ai 26 Chroma pute at ie rte 29 Op ration 30 Chroma Transient Improvement CTI
41. Rev 25 of 100 ADV7183B The following sections describe the I C signals that can be used to influence the behavior of the clamps on the ADV7183B Previous revisions of the ADV7183B had controls FACL FICL fast and fine clamp length to allow configuration of the length for which the coarse fast and fine current sources are switched on These controls were removed on the ADV7183B FT and replaced by an adaptive scheme CCLEN Current Clamp Enable Address 0x14 4 The current clamp enable bit allows the user to switch off the current sources in the analog front end altogether This can be useful if the incoming analog video signal is clamped externally When CCLEN is 0 the current sources are switched off When CCLEN is 1 default the current sources are enabled DCT 1 0 Digital Clamp Timing Address 0x15 6 5 The clamp timing register determines the time constant of the digital fine clamp circuitry It is important to realize that the digital fine clamp reacts very quickly because it is supposed to immediately correct any residual dc level error for the active line The time constant of the digital fine clamp must be much faster than the one from the analog blocks By default the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal Table 29 DCT Function DCT 1 0 Description 00 Slow TC 1 sec 01 Medium TC 0 5 sec 10 default Fast
42. The VBI enable bit allows data such intercast and closed caption data to be passed through the luma channel of the decoder with a minimal amount of filtering All data for Line 1 to Line 21 is passed through and available at the output port The ADV7183B does not blank the luma data and auto matically switches all filters along the luma data path into their widest bandwidth For active video the filter settings for YSH and YPK are restored Refer to the BL_C_VBI Blank Chroma During VBI Address 0x04 2 section for information on the chroma path When VBI_EN is 0 default all video lines are filtered scaled When VBI_EN is 1 only the active video region is filtered scaled SD DUP AV 0 8 BIT INTERFACE renveavep Av 04997 019 Figure 19 AV Code Duplication Control Rev B Page 37 of 100 ADV7183B BL_C_VBI Blank Chroma During VBI Address 0x04 2 Setting BL_C_VBI high the Cr and Cb values of all VBI lines are blanked This is done so any data that arrives during VBI is not decoded as color and output through Cr and Cb As a result it should be possible to send VBI lines into the decoder then output them through an encoder again undistorted Without this blanking any wrongly decoded color is encoded by the video encoder therefore the VBI lines are distorted Setting BL_C_VBI to 0 decodes and outputs color during VBI Setting BL_C_VBI to 1 default blanks Cr and Cb values during VB
43. and Chroma Gain sections ANALOG VOLTAGE RANGE SUPPORTED BY ADC 1 6V RANGE FOR ADV7189B SDP DATA GAIN SELECTION ONLY GAIN PRE PROCESSOR DPP 04983 017 Figure 17 Gain Control Overview Rev B Page 30 of 100 Table 33 Modes ADV7183B Input Video Type Luma Gain Chroma Gain Any Manual gain luma Manual gain chroma CVBS Dependent on horizontal sync depth Dependent on color burst amplitude Taken from luma path Peak white Dependent on color burst amplitude Taken from luma path Y C Dependent on horizontal sync depth Dependent on color burst amplitude Taken from luma path Peak white Dependent on color burst amplitude Taken from luma path YPrPb Dependent on horizontal sync depth Taken from luma path Luma Gain Table 35 LAGT Function LAGC 2 0 Luma Automatic Gain Control LAGT 1 0 Description Address 0x2C 7 0 00 alow TC 2 sec 01 Medium TC 1 sec The luma automatic gain control mode bits select the mode of 10 Fast TC 0 2 sec operation for the gain control in the luma path 11 default Adaptive ADI internal parameters are available to customize the peak white gain control Contact ADI sales for more information Table 34 LAGC Function LAGC 2 0 Description 000 Manual fixed gain use LMG 11 0 001 AGC blank level to sync tip peak white algorithm off 010 default AGC blank level to sync tip peak white algorithm on 011 Reserved 100 Reser
44. compatible 3 3 V analog 1 8 V digital core 3 3 V IO supply 2 temperature grades 0 C to 70 C and 40 C to 85 80 lead LQFP Pb free package APPLICATIONS DVD recorders Video projectors HDD based PVRs DVDRs LCD TVs Set top boxes Security systems Digital televisions AVR receivers combinations AGC and clamp restore circuitry allow an input video signal peak to peak range of 0 5 V up to 1 6 V Alternatively these can be bypassed for manual settings The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise accurate sampling and digital filtering The line locked clock output allows the output data rate timing signals and output clock signals to be synchronous asynchronous or line locked even with 5 line length variation The output control signals allow glueless interface connections in almost any application The ADV7183B modes are set up over a 2 wire serial bidirectional port I C compatible The ADV7183B is fabricated in a 3 3 V CMOS process Its monolithic CMOS construction ensures greater functionality with lower power dissipation The ADV7183B is packaged in a small 80 lead LOFP Pb free package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc rights reserved ADV7183B TABLE OF CONTENTS Introduction si ina 4 Analog Front End tame ei e tris 4 Standard Definition
45. digitization the digital fine clamp block corrects for any remaining variations in dc level Since the dc level of an input video signal refers directly to the brightness of the picture transmitted it is important to perform a fine clamp with high accuracy otherwise brightness variations can occur Further more dynamic changes in the dc level almost certainly lead to visually objectionable artifacts and must therefore be prohibited The clamping scheme has to be able to acquire a newly connected video signal with a completely unknown dc level and it must maintain the dc level during normal operation For quickly acquiring an unknown video signal the large cur rent clamps can be activated It is assumed that the amplitude of the video signal at this point is of a nominal value Control of the coarse and fine current clamp parameters is performed automatically by the decoder Standard definition video signals can have excessive noise on them In particular CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise gt 100 mV A voltage clamp is unsuitable for this type of video signal Instead the ADV7183B uses a set of four current sources that can cause coarse gt 0 5 mA and fine lt 0 1 mA currents to flow into and away from the high impedance node that carries the video signal see Figure 10 PRE PROCESSOR DPP 04997 010 Figure 10 Clamping Overview
46. internal digital noise Shorter traces reduce the possibility of reflections Adding a 30 to 50 Q series resistor can suppress reflections reduce EMI and reduce the current spikes inside the ADV7183B If series resistors are used place them as close as possible to the ADV7183B pins However try not to add vias or extra length to the output trace to make the resistors closer If possible limit the capacitance that each of the digital outputs drive to less than 15 pF This can easily be accomplished by keeping traces short and by connecting the outputs to only one device Loading the outputs with excessive capacitance increases the current transients inside the ADV7183B creating more digital noise on its power supplies DIGITAL INPUTS The digital inputs on the ADV7183B are designed to work with 3 3 V signals and are not tolerant of 5 V signals Extra compo nents are needed if 5 V logic signals are required to be applied to the decoder Rev B Page 94 of 100 ANTIALIASING FILTERS For inputs from some video sources that are not bandwidth limited signals outside the video band can alias back into the video band during A D conversion and appear as noise on the output video The ADV7183B oversamples the analog inputs by a factor of 4 This 54 MHz sampling frequency reduces requirement for an input filter for optimal performance it is recommended that an antialiasing filter be used The recommended low cost circuit for imp
47. no CRC check is performed The CGMSD bit goes high if the rising edge of the start bit is detected within a time window When CRC_ENABLE is 1 default CRC checksum is used to validate the CGMS sequence The CGMSD bit goes high for a valid checksum The default is ADTs recommended setting Rev B Page 47 of 100 ADV7183B Wide Screen Signaling Data EDTV Data Registers WSS1 7 0 Address 0x91 7 0 EDTV1 7 0 Address 0x93 7 0 WSS2 7 0 Address 0x92 7 0 EDTV2 7 0 Address 0x94 7 0 Figure 31 shows the bit correspondence between the analog EDTV3 7 0 Address 0x95 7 0 video waveform and the WSS1 WSS2 registers WSS2 7 6 are Figure 32 shows bit correspondence between analog undetermined and should be masked out by software video waveform and the EDTV1 EDTV2 EDTV3 registers EDT V3 7 6 are undetermined and should be masked out by software EDT V3 5 is reserved for future use and for now contains 0 The 3 LSBs of the EDTV waveform are currently not supported WSS1 7 0 55215 0 1 7 RUN IN START ACTIVE SEQUENCE CODE VIDEO 11 015 38 415 5 42 5us 5 3 Figure 31 WSS Data Extraction Table 58 WSS Access Information Signal Name Register Location Address Register Default Value WSS1 7 0 WSS 1 7 0 145d 0x91 Readback Only WSS2 5 0 WSS 2 5 0 146d 0x92 Readback Only EDTV1 7 0 EDTV2 7 0 EDTV3 5 0 NOT SUPPORTED i 1 W
48. not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low When VSEHO is 0 default the VS pin goes low inactive at the middle of a line of video odd field When is 1 the VS pin changes state at the start of a line odd field VSEHE VS End Horizontal Position Even Address 0x33 6 The VSEHO and VSEHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low When VSEHE is 0 default the VS pin goes low inactive at the middle of a line of video even field When VSEHE is 1 the VS pin changes state at the start of a line even field PVS Polarity VS Address 0x37 5 The polarity of the VS pin can be inverted using the PVS bit When PVS is 0 default VS is active high Rev B Page 40 of 100 ADV7183B When PVS is 1 VS is active low PF Polarity FIELD Address 0 37 3 The polarity of the FIELD pin can be inverted using the PF bit When PF is 0 default FIELD is active high When PF is 1 FIELD is active low FIELD 1 1 21314 15 16 17 9 91H 112 13l 19 1 2012 eo 4 ITIL VIDEO NVBEG 4 0 0 5 NVEND 4 0 0 4 1 656 4 REG 0x04 BIT 7 1 ln NFTOG 4 0 0x3 FIELD 2 2641 2651 266 267 268 269 270 2711 2721 273 274 275 1276
49. of manual override muxing registers the analog input muxes of the ADV7183B can be controlled directly This is referred to as manual input muxing Manual input muxing overrides other input muxing control bits such as INSEL The manual muxing is activated by setting the ADC SW MAN EN bit It affects only the analog switches in front of the ADCs This means if the settings of INSEL and the manual input muxing registers ADCO ADCI ADC2 sw contradict each other the ADCO ADCI ADC2 sw settings apply and INSEL is ignored Manual input muxing controls only the analog input muxes INSEL 3 0 still has to be set so the follow on blocks process video data in the correct format This means INSEL must still be used to tell the ADV7183B whether the input signal is of component Y C or CVBS format ADV7183B Restrictions in the channel routing are imposed by the analog signal routing inside the IC every input pin cannot be routed to each ADC Refer to Figure 6 for an overview on the routing capabilities inside the chip The three mux sections can be controlled by the reserved control signal buses ADC0 ADC1 ADC2_sw 3 0 Table 10 explains the control words used SETADC_sw_man_en Manual Input Muxing Enable Address 0xC4 7 ADCO sw 3 0 ADCO mux configuration Address 0xC3 3 0 ADCI sw 3 0 ADC1 mux configuration Address 0xC3 7 4 ADC2 sw 3 0 ADC2 mux configuration Address 0xC4 3 0 Table 10 Manual Mux Settings for All ADCs SET
50. of the alpha blending can be configured via the AB 1 0 bits For the alpha blender to be active the CTI block must be enabled via the CTI EN bit Setting CTI AB EN to 0 disables the CTI alpha blender Setting CTI AB EN to 1 default enables the CTI alpha blend mixing function AB 1 0 Chroma Transient Improvement Alpha Blend Address 0 4 3 2 The AB 1 0 controls the behavior of alpha blend circuitry that mixes the sharpened chroma signal with the original one It thereby controls the visual impact of CTI on the output data For CTI AB 1 0 to become active the CTI block must be enabled via the EN bit and the alpha blender must be switched on AB EN Sharp blending maximizes the effect of CTI on the picture but can also increase the visual impact of small amplitude high frequency chroma noise Table 43 CTI AB Function CTI AB 1 0 Description 00 Sharpest mixing between sharpened and original chroma signal 01 Sharp mixing 10 Smooth mixing 11 default Smoothest alpha blend function CTI C TH 7 0 CTI Chroma Threshold Address Ox4E 7 0 The C TH 7 0 value is an unsigned 8 bit number speci fying how big the amplitude step in a chroma transition must be steepened by the CTI block Programming a small value into this register causes even smaller edges to be steepened by the CTI block Making CTI C TH 7 0 a large value causes the block to improve lar
51. on Line 287 LB EL 3 0 Letterbox End Line Address 0xDD 3 0 The LB EL 3 0 bits are set at 1101b by default This means the letterbox detection window ends with the last active video line For an NTSC signal this window is from Line 262 to Line 525 Changing the bits to 1100 the detection window starts on Line 261 and ends on Line 254 Gemstar Data Recovery The Gemstar compatible data recovery block GSCD supports 1x and 2x data transmissions It can also serve as a closed caption decoder Gemstar compatible data transmissions can occur only in NTSC Closed caption data can be decoded in both PAL and NTSC The block is configured via PC in the following ways GDECEL 15 0 allow data recovery on selected video lines on even fields to be enabled and disabled GDECOL 15 0 enable the data recovery on selected lines for odd fields GDECAD configures the way in which data is embedded in the video data stream Rev B Page 50 of 100 The recovered data is not available through I C but is inserted into the horizontal blanking period of an ITU R BT656 com patible data stream The data format is intended to comply with the recommendation by the International Telecommunications Union ITU R BT 1364 For more information see the ITU website at www itu ch See Figure 35 The format of the data packet depends on the following criteria e Transmission is 1x or 2x e Data is output in 8 bit or 4 bit format see the des
52. over this range ANALOG SPECIFICATIONS Guaranteed by characterization Avpp 3 15 V to 3 45 V 1 65 V to 2 0 V 3 0 V to 3 6 V 1 65 V to 2 0 V operating temperature range unless otherwise noted Recommended analog input video signal range 0 5 V to 1 6 V typically 1 V p p Table 4 Parameter Symbol Test Conditions Min Typ Max Unit CLAMP CIRCUITRY External Clamp Capacitor 0 1 uF Input Impedance Clamps switched off 10 Large Clamp Source Current 0 75 mA Large Clamp Sink Current 0 75 Fine Source Current 60 Fine Clamp Sink Current 60 1 Temperature range to Tmax 40 C to 85 C 0 to 70 C for ADV7183BKSTZ 2 The min max specifications are guaranteed over this range Rev B Page 8 of 100 ADV7183B THERMAL SPECIFICATIONS Table 5 Parameter Symbol Test Conditions Min Typ Max Unit Junction to Case Thermal Resistance 4 layer PCB with solid ground plane 7 6 C W Junction to Ambient Thermal Resistance Still Air 4 layer PCB with solid ground plane 38 1 C W 1 Temperature range to Tmax 40 C 85 C 0 C 70 C for ADV7183BKSTZ 2 The min max specifications are guaranteed over this range TIMING DIAGRAMS SDA SCLK 04997 002 Figure 2 PC Timing tg lt gt OUTPUT LLC 1 OUTPUT LLC 2 ts OUTPUTS P0 P15 VS HS FIELD SFL 0
53. setting Recommended setting Rev B Page 89 of 100 ADV7183B Mode 3 5251 6251 YPrPb Input on AIN2 PB AIN3 and PR AIN6 All standards are supported through autodetect 8 bit ITU R BT 656 output on P15 to P8 Table 89 Mode 3 YPrPb Input 5251 6251 Register Address Register Value Notes 0x00 Ox0A Y2 AIN2 PB2 AIN3 PR2 AIN6 0x1D 0x40 Enable 28 MHz crystal 0 40 TRAQ 0x3D OxC3 MWE enable manual window Ox3F OxE4 BGB to 36 0 50 0 04 Set DNR threshold to 4 for flat response OxOE 0 80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0 52 0 18 Recommended setting 0 58 OxED Recommended setting 0 77 OxC5 Recommended setting Ox7C 0 93 Recommended setting 0 90 OxC9 Recommended setting 0 91 0 40 Recommended setting 0 92 0x3C Recommended setting 0x93 Recommended setting 0 94 OxdD Recommended setting OxCF 0 50 Recommended setting Ox4E Recommended setting OxD6 OxDD Recommended setting OxE5 0 51 Recommended setting 9 Recommended setting OxOE 0 00 Recommended setting Rev B Page 90 of 100 Mode 4 CVBS Tuner Input PAL Only on AIN4 8 ITU R BT 656 output on P15 to 8 Table 90 Mode 4 Tuner Input CVBS PAL Only ADV7183B Register Address Register Value Notes 0x00 0x07 0x15 0x17 0x1D OxOF Ox3D Ox3F 0x19 0
54. this accumulated value is compared with a threshold and a decision is made as to whether or not a particular line is black The threshold value needed depends on the type of input signal some control is provided via LB_TH 4 0 Detection at the Start of a Field The ADV7183B expects a section of at least six consecutive black lines of video at the top of a field Once those lines are detected Register LB LCT 7 0 reports back the number of black lines actually found By default the ADV7183B starts looking for those black lines in sync with the beginning of active video for example straight after the last VBI video line SL 3 0 allows the user to set the start of letterbox detection from the beginning of a frame on a line by line basis The detection window closes in the middle of the field Detection at the End of a Field The ADV7183B expects at least six continuous lines of black video at the bottom of a field before reporting back the number of lines actually found via the LB LCB 7 0 value The activity window for letterbox detection end of field starts in the middle of an active field Its end is programmable via LB EL 3 0 Detection at the Midrange Some transmissions of wide screen video include subtitles within the lower black box If the ADV7183B finds at least two black lines followed by some more nonblack video for example the subtitle and is then followed by the remainder of the bottom black block it repor
55. three stated dependent on the TOD bit This functionality is useful if the decoder is used as a timing generator only This can happen when only the timing signals are to be extracted from an incoming signal or if the part is in free run mode where a separate chip can output for an example a company logo For more information on three state control refer to the Three State Output Drivers and the Three State LLC Driver sections Individual drive strength controls are provided via the DR STR XX bits When OE is 0 default the HS VS and FIELD pins three stated according to the TOD bit When OE is 1 HS VS and FIELD are forced active all the time Drive Strength Selection Data DR STR 1 0 Address 0xF4 5 4 For EMC and crosstalk reasons it can be desirable to strengthen or weaken the drive strength of the output drivers The DR STR 1 0 bits affect the P 15 0 output drivers For more information on three state control refer to the Drive Strength Selection Clock and the Drive Strength Selection Sync sections Table 11 STR Function DR STR 1 0 Description 00 Low drive strength 1x 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x Rev B Page 17 of 100 ADV7183B Drive Strength Selection Clock DR_STR_C 1 0 Address 0xF4 3 2 The DR_STR_C 1 0 bits can be used to select the strength of the clock signal out
56. value used Reserved Setto 1 LAGT 1 0 Luma automatic 010 Slow 2 sec Has an effect only if timing allows adjustment of the ol 1 Medium TC 1 sec LAGC 1 0 is set to luma AGC tracking speed auto gain 001 010 10 Fast 0 2 sec 011 0r 100 Adaptive 0 30 Gain LMG 7 0 manual gain be LMG 11 0 1234 Min value Control 2 used to program a desired manual is 1 in NTSC NTSC 1024 G 0 85 chroma gain or read back the actual LMG 11 0 12664 gain PAL 0 81 used gain value is 1 PAL Max value NTSC 2468 2 PAL 2532 6 2 0 31 5 Reserved Set to default HVSTIM Selects where within a line 0 Start of line relative HSE HSE Hsync end ontrol 1 of video the VS signal is asserted 1 Start of line relative to HSB HSB Hsync begin NEWAVMODE Sets the EAV SAV 0 EAV SAV codes mode generated to suit ADI encoders 1 Manual VS field position controlled by Registers 0x32 0x33 and OxE5 to OxEA Reserved 10 default 0 32 Vsync Reserved NEWAVMODE bit Field ololo Set to default must be set high VSBHE 0 VS goes high in the middle of the line even field 1 VS changes state at the start of the line even field VSBHO 0 VS goes high in the middle of the line odd field 1 VS changes state at the start of the line odd field 0x33 Vsync Reserved Set to default
57. version of the LLC1 output clock for the pixel data output by the ADV7183B Nominally 13 5 MHz but varies up or down according to video line length 29 XTAL This is the input pin for 28 6363 MHz crystal or overdriven by an external 3 3 V 27 MHz clock oscillator source In crystal mode the crystal must be a fundamental crystal 28 XTAL1 This pin should be connected to 28 6363 MHz crystal or left as no connect if an external 3 3 V 27 MHz clock oscillator source is used to clock the ADV7183B In crystal mode the crystal must be a fundamental crystal 36 PWRDN logic low on this pin places the ADV7183B in power down mode Refer to the IP2PC Register Maps section for more options power down modes for the 7 1838 79 OE When set to a logic low OE enables the pixel output bus P15 to PO of the ADV7183B A logic high on the OE pin places Pins P15 to PO HS VS SFL into a high impedance state 37 ELPF The recommended external loop filter must be connected to this ELPF pin as shown in Figure 46 12 SFL Subcarrier Frequency Lock This pin contains serial output stream that be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices Inc digital video encoder 51 REFOUT Internal Voltage Reference Output Refer to 46 for a recommended network for this pin 52 CML CML pin is common mode level for the internal ADC
58. 0 7 0 section Figure 9 outlines the signal flow and the controls available to influence the way the lock status information is generated FILTER THE RAW LOCK SIGNAL CIL 2 0 COL 2 0 STATUS 1 0 STATUS 1 1 04997 009 Figure 9 Lock Related Signal Path Rev B Page 22 of 100 ADV7183B SRLS Select Raw Lock Signal Address 0 51 6 Using the SRLS bit the user can choose between two sources for determining the lock status per Bits 1 0 in the Status 1 register e The time_win signal is based on a line to line evaluation of the horizontal synchronization pulse of the incoming video It reacts quite quickly COL 2 0 Count Out of Lock Address 0 51 5 3 COL 2 0 determines the number of consecutive lines for which the out of lock condition must be true before the system switches into unlocked state and reports this via Status 0 1 0 It counts the value in lines of video Table 21 COL Function COL 2 0 Description e Thefree run signal evaluates the properties of the 000 1 incoming video over several fields and takes vertical 001 2 synchronization information into account 010 5 Setting SRLS to 0 default selects the free run signal 011 10 100 default 100 Setting SRLS to 1 selects the time win signal 101 500 FSCLE Lock Enable Address 0x51 7 110 1000 The FSCLE bit allows the user to choose whether the status of a the color subcarrier loop is taken into account when the overa
59. 00 SVHS3 01100 SVHS 11 0 0101 SVHS4 01101 SVHS 12 0 0110 SVHS 5 01110 SVHS 13 00111 SVHS 6 01111 SVHS 14 01000 SVHS 7 10000 SVHS 15 0 1001 SVHS 8 10001 SVHS 16 0 1010 SVHS 9 10010 SVHS T 01011 SVHS 10 10011 SVHS 18 CCIR 601 01100 SVHS 11 19190 01101 SVHS 12 Oro 01110 SVHS 13 1 0110 PLNS 01111 SVHS 14 10111 FR 10000 SVHS 15 11000 PAEWN 2 1 0001 SVHS 16 11001 NTSC NN 1 10010 SVHS 17 11019 10011 default SVHS 18 CCIR 601 11017 NISI 10100to 171111 Do not use 11100 NTSCWN 1 11101 NTSCWN 2 11110 NTSCWN 3 111111 Reserved Page 28 of 100 The filter in Figure 12 show S VHS 1 narrowest to ADV7183B COMBINED Y ANTIALIAS NTSC NOTCH FILTERS Y AMPLE RES S VHS 18 widest shaping filter settings Figure 14 shows the PAL notch filter responses The NTSC compatible notches are shown in Figure 15 710 Ta COMBINED ANTIALIAS S VHS LOW PASS FILTERS 20 RESAMPLE kJ 0 a 30 2 E m 10 amp 40 20 50 30 60 5 5 40 70 o 8 10 2 FREQUENCY MHz Figure 15 NTSC Notch Filter Response 60 70 CHROMA FILTER 0 2 4 6 8 10 12 2 04997 012 Data from digital fine clamp block is processed by three sets Figure 12 Y S VHS Combined Respo
60. 1 71 DGND G Digital Ground 39 40 47 53 56 AGND G Analog Ground 4 15 DVDDIO P Digital Supply Voltage 3 3 V 10 30 72 DVDD P Digital Core Supply Voltage 1 8 V 50 AVDD P Analog Supply Voltage 3 3 V 38 PVDD P PLL Supply Voltage 1 8 V 42 44 46 58 60 AIN1 to AIN12 Analog Video Input Channels 62 41 43 45 57 59 61 11 INTRO Interrupt Request Output Interrupt occurs when certain signals are detected the input video See the interrupt register map in Table 83 13 16 to 18 25 34 No Connect Pins 35 63 65 69 70 77 78 33 32 24 23 22 PO to P15 Video Pixel Output Port 21 20 19 8 7 6 5 76 75 74 73 2 HS Horizontal Synchronization Output Signal 1 vs Vertical Synchronization Output Signal 80 FIELD Field Synchronization Output Signal 67 SDA Port Serial Data Input Output Pin 68 SCLK PC Port Serial Clock Input Maximum clock rate of 400 kHz 66 ALSB This pin selects the address for the ADV7183B ALSB set to Logic 0 sets the address for a write as 0 40 for ALSB set to logic high the address selected is 0 42 64 RESET System Reset Input Active Low minimum low reset pulse width of 5 ms is required to reset the ADV7183B circuitry 27 LLC1 This is line locked output clock for the pixel output by the ADV7183B Nominally 27 MHz but varies up or down according to video line length 26 LLC2 This is a divide by 2
61. 1 and 2 Rev B Page 95 of 100 ADV7183B TYPICAL CIRCUIT CONNECTION Figure 45 and Figure 46 show examples of how to connect the ADV7183B video decoder For a detailed schematic diagram for the ADV7183B refer to the ADV7183B evaluation note AVDD_5V 04997 044 Figure 45 ADI Recommended Antialiasing Circuit for All Input Channels Rev B Page 96 of 100 FERRITE BEAD DVDDIO 83 10uF FERRITE BEAD 1 8 10uF FERRITE BEAD AVDD 0 33uF 10uF Paano FERRITE BEAD DVDD 1 8V AGND DGND J0uF S VIDEO FILTER CIRCUIT PIETER CIRCUIT 100nF ANTI ALIAS FILTER CIRCUIT ANTI ALIAS M FILTER CIRCUIT _ ANTI ALIAS rO FILTER CIRCUIT _ ANTI ALIAS FILTER CIRCUIT ANTI ALIAS FILTER CIRCUIT RECOMMENDED ANTI ALIAS FILTER 1 CIRCUIT IS SHOWN FIGURE 45 ON THE i PREVIOUS PAGE THIS CIRCUIT INCLUDES 750 TERMINATION RESISTOR INPUT AGND BUFFER AND ANTI ALIASING FILTER 1 AGND O1uF 10uF 0 1uF 11 J AGND e t t 1 t 10uF AGND CAPC2 CML REFOUT Y Y 10uF EOduF i CAPACITOR VALUES 1 AREDEPENDANTON AGND 1MO XTALATTRIBUTES 28 63636MHz CI al DGND ATpF DVDDIO 7 SELECT 9 ADDRESS i DVDDIO DVDDIO
62. 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 1 Line 3 0 0 0 SDID 5 0 0 0 0 1 0 0 0 Data count 6 0 0 Gemstar 7 4 0 0 User data words 7 0 0 Gemstar Word 1 3 0 0 0 User data words 8 0 0 Gemstar Word2 7 4 0 0 User data words 9 0 0 Gemstar Word2 3 0 0 0 User data words 10 0 0 Gemstar Word3 7 4 0 0 User data words 11 0 0 Gemstar Word3 3 0 0 0 User data words 12 0 0 Gemstar Word4 7 4 0 0 User data words 13 0 0 Gemstar Word4 3 0 0 0 User data words 14 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5 0 Checksum Table 67 Gemstar 2x Data Full Byte Mode Byte 0191 0181 07 0161 0151 0141 0121 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 1 Line 3 0 0 0 SDID 5 0 0 0 0 0 1 0 0 Data count 6 Gemstar 1 7 0 0 0 User data words 7 Gemstar Word2 7 0 0 0 User data words 8 Gemstar Word3 7 0 0 0 User data words 9 Gemstar Word4 7 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5 0 Checksum Table 68 Gemstar 1 Data Half Byte Mode Byte 0191 0181 DI7 0161 0151 0141 0121 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1
63. 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 0 Line 3 0 0 0 500 5 0 0 0 0 0 1 0 0 Data count 6 0 0 Gemstar 7 4 0 0 User data words 7 0 0 Gemstar Word 1 3 0 0 0 User data words 8 0 0 Gemstar Word2 7 4 0 0 User data words 9 0 0 Gemstar Word2 3 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5 0 Checksum Rev B Page 53 of 100 ADV7183B Table 69 Gemstar 1x Data Full Byte Mode Byte 0191 0181 07 0161 0151 0 4 0121 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 0 Line 3 0 0 0 500 5 0 0 0 0 0 1 0 0 Data count 6 Gemstar 1 7 0 0 0 User data words 7 Gemstar Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0 200 10 ICS 8 CS 8 CS 7 CS 6 CS 5 5 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 70 NTSC CCAP Data Half Byte Mode Byte DI9 DI8 DI7 0161 0151 0 4 0121 D 1 DIO Description
64. 25 NTSC FIELD Toggle NFTOGSIGN NTSC Field Toggle Sign Address 0 7 5 Setting NFTOGSIGN to 0 delays the field transition Set for user manual programming Setting NFTOGSIGN to 1 default advances the field transition Not recommended for user programming Rev B Page 43 of 100 ADV7183B NFTOG 4 0 NTSC Field Toggle Address OxE7 4 0 Table 57 Recommended User Settings for PAL see Figure 27 The default value of NFTOG is 00011 indicating the NTSC Register Register Name Write Field toggle position 0x31 Vsync Field Control 1 0 32 Vsync Field Control 2 0 81 For all NTSC PAL Field timing controls both the F bit in 0x33 Vsync Field Control 3 0x84 AV code and the Field signal on the FIELD pin are modified 0x34 Hsync Pos Control 1 0x00 0x35 Hsync Pos Control 2 0x00 0x36 Hsync Pos Control 3 0x7D 0x37 Polarity 0x29 OxE8 PAL_V_Bit_Beg 0x41 OxE9 PAL_V_Bit_End 0x84 OxEA PAL_F_Bit_Tog 0x06 FIELD 1 Pn 162211 16231 624 1 6511 12 1 4 15 6 I 7 8 19 110000 22 23 24 OUTPUT VIDEO PFTOG 4 0 0 3 FIELD 2 i310 311 312 313 314 315 316 317 318 319 320 3211322 335 397 OUTPUT 4 7 5 77 VIDEO 11 PVEND 4 0 0 4 04997 026 4 0 0 3 Figure 26 PAL Default BT 656 The Polarity of V and is Embedded in the Data FIELD 1 1 DES 8 54s 6535 6 7 8 9 10 111 EIN omer
65. 4997 003 Figure 3 Pixel Port and Control Output Timing OE tis 97 PO P15 HS Vs FIELD SFL tig Figure 4 Timing 04997 004 Rev B Page 9 of 100 ADV7183B ABSOLUTE MAXIMUM RATINGS Table 6 Parameter Rating to GND 4V Stresses above those listed under Absolute Maximum Ratings Avon to AGND 4V may cause permanent damage to the device This is a stress Dvop to 22V rating only functional operation of the device at these or any to AGND 22V other conditions above those indicated in the operational to 4V section of this specification is not implied Exposure to absolute to Avon 0 3V to 0 3 V maximum rating conditions for extended periods may affect Pvoo to Dvoo 0 3 V to 40 3 V device reliability 0 3Vto 2V 0 3Vtot2V 0 3Vto 2V 0 3Vtot2V Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Input to AGND Maximum Junction Temperature max Storage Temperature Range Infrared Reflow Soldering 20 sec 0 3 V to 0 3 V 0 3 V to 0 3 V 0 3 V to 0 3 V 150 65 C to 150 C 260 ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without de
66. 54 3 2 1 0 Comments Notes OxDC Letterbox LB THI4 01 Sets the threshold 1 1 0 0 Default threshold for Control 1 value that determines line is the detection of black black lines Reserved 1011 Set as default OxDD Letterbox LB EL 3 0 Programs the end line 1 1 0 0 LB detection ends with Control2 ofthe activity window for LB the last line of active detection end of field video on a field 1100b 262 525 LB_SL 3 0 Program the start line 01100 Letterbox detection of the activity window for LB aligned with the start of detection start of field active video 0100b 23 286 NTSC Reserved Reserved Reserved OxE1 SD Offset SD OFF 7 01 Adjusts the hue Cb by selecting the offset for the Cb channel OxE2 SD Offset SD_OFF_CRI 7 0 Adjusts the hue by selecting the offset for the Cr channel OxE3 SD Satura SD SAT CB 7 01 Adjusts the 1010100 0 00 Chroma gain 0 dB tion Cb saturation of the picture by affecting gain on the Cb channel OxE4 SD SD SAT CR 7 0 Adjusts the 1010100 0 0 0 Chroma gain 0 dB Saturation saturation of the picture by Cr affecting gain on the Cr channel OxE5 NTSCV NVBEG 4 0 Number of lines after 010111 0 1 NTSC default BT 656 Begin Icount rollover to set V high NVBEGSIGN 0 Set to low when manual programming 1 Not suitable for user programmi
67. 65 0x41 Reserved XXXX XXXX rw 66 to 71 0x42 to 0x47 Gemstar Ctrl 1 00000000 rw 72 0x48 Gemstar Ctrl 2 0000 0000 rw 73 0x49 Gemstar Ctrl 3 0000 0000 rw 74 Ox4A Gemstar Ctrl 4 0000 0000 rw 75 4 GemStar Ctrl 5 XXXX rw 76 0 4 DNR Ctrl 1 1110 1111 rw 77 Ox4D CTI DNR Ctrl 2 0000 1000 rw 78 Ox4E Reserved XXXX XXXX rw 79 Ox4F DNR Ctrl 4 0000 1000 rw 80 0 50 Lock Count 0010 0100 rw 81 0x51 Reserved XXXX XXXX rw 82 to 142 0x52 to Ox8E Free Run Line Length 1 0000 0000 w 143 Reserved 0000 0000 144 0 90 VBI Info XXXX XXXX r 144 0x90 WSS 1 XXXX XXXX r 145 0x91 WSS 2 XXXX XXXX r 146 0x92 EDTV 1 XXXX XXXX r 147 0x93 EDTV 2 XXXX XXXX r 148 0x94 EDTV 3 XXXX XXXX r 149 0x95 CGMS 1 XXXX XXXX r 150 0x96 CGMS 2 XXXX XXXX r 151 0x97 CGMS 3 XXXX XXXX r 152 0x98 CCAP1 XXXX XXXX r 153 0x99 CCAP2 XXXX XXXX r 154 Ox9A Letterbox 1 XXXX XXXX r 155 9 Letterbox 2 156 Ox9C Letterbox 3 XXXX XXXX r 157 Ox9D Reserved XXXX XXXX rw 158 to 177 Ox9E to OxB1 CRC Enable 0001 1100 w 178 0 2 Reserved XXXX XXXX rw 179 to 194 2 OxC2 Switch 1 rw 195 OxC3 ADC Switch 2 rw 196 OxC4 Reserved XXXX XXXX rw 197 to 219 OxC5 to Letterbox Control 1 1010 1100 rw 220 OxDC Letterbox Control 2 0100 1100 rw 221 OxDD Reserved 0000 0000 rw 222 Reserved 0000 0000 rw 223 Reserved 0001 0100 rw 224 SD Offset 1000 0000 rw 225 OxE1 SD Off
68. 83B s PC port allows the user to set up and configure the decoder and to read back captured VBI data The ADV7183B has two possible slave addresses for both read and write operations depending on the logic level on the ALSB pin These four unique addresses are shown in Table 81 The ADV7183B s ALSB pin controls Bit 1 of the slave address altering the ALSB it is possible to control two ADV7183Bs in an application without having a conflict with the same slave address The LSB Bit 0 sets either a read or write operation Logic 1 corresponds to a read operation Logic 0 corresponds to a write operation Table 81 C Address for the ADV7183B ALSB R W Slave Address 0 0 0x40 0 1 0 41 1 0 0 42 1 1 0 43 To control the device on bus a specific protocol must be followed First the master initiates a data transfer by establishing a start condition which is defined by a high to low transition on SDA while SCLK remains high This indicates that an address data stream will follow All peripherals respond to the start condition and shift the next eight bits 7 bit address R W bit The bits are transferred from MSB down to LSB The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse this is known as an acknowledge bit All other devices withdraw from the bus at this point and maintain an idle condition The idle condition is where the device monitors the
69. ADC sw man en 1 ADCO sw 3 0 ADCO Connected to 1 sw 3 0 ADC1 Connected to ADC2 sw 3 0 ADC2 Connected to 0000 No connection 0000 No connection 0000 No connection 0001 AIN1 0001 No connection 0001 No connection 0010 AIN2 0010 No connection 0010 AIN2 0011 AIN3 0011 AIN3 0011 No connection 0100 AIN4 0100 AIN4 0100 No connection 0101 AIN5 0101 AIN5 0101 AIN5 0110 AIN6 0110 AIN6 0110 AIN6 0111 No connection 0111 No connection 0111 No connection 1000 No connection 1000 No connection 1000 No connection 1001 AIN7 1001 No connection 1001 No connection 1010 AIN8 1010 No connection 1010 AIN8 1011 AIN9 1011 AIN9 1011 No connection 1100 AIN10 1100 AIN10 1100 No connection 1101 AIN11 1101 AIN11 1101 AIN11 1110 AIN12 1110 AIN12 1110 AIN12 1111 No connection 1111 No connection 1111 No connection Rev Page 15 of 100 ADV7183B GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip POWER SAVE MODES Power Down PDBP Address 0x0F 2 The digital core of the ADV7183B can be shut down by using the PWRDN pin and the PWRDN bit see below The PDBP controls which of the two pins has the higher priority The default is to give priority to the PWRDN pin This allows the user to have the ADV7183B powered down by default When PDBD is 0 default the digital core power is controlled by the PWRDN pin the bit is disregarded When PDBD is 1 the bit has priority the pin i
70. BSTZ 40 C to 85 80 lead Low Profile Quad Flat Package LOFP ST 80 2 EVAL ADV7183BEB Evaluation Board The ADV7183B is a Pb free environmentally friendly product It is manufactured using the most up to date materials and processes The coating on the leads of each device is 100 pure Sn electroplate The device is suitable for Pb free applications can withstand surface mount soldering at up to 255 C 5 In addition the ADV71893B is backward compatible with conventional SnPb soldering processes This means the electroplated Sn coating can be soldered with Sn Pb solder pastes at conventional reflow temperatures of 220 C to 235 C 27 Pb free part Rev B Page 98 of 100 ADV7183B NOTES Rev B Page 99 of 100 ADV7183B NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components in an system provided that the system conforms to the Standard Specification as defined by Philips 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners DEVICES Rev B Page 100 of 100 www analog com
71. C2 SW 1 ADC2 SW 0 AN Reserved Letterbox Control 1 LB 4 LB TH 3 LB TH 2 LB TH 1 LB Letterbox Control 2 LB SL 3 LB SL 2 LB SL 1 LB 51 0 LB EL 3 LB EL 2 LB EL 1 LB EL O Reserved Reserved Reserved SD Offset Cb SD OFF CB7 SD OFF CB 6 SD OFF 5 SD OFF 4 SD OFF CB 3 SD OFF CB 2 SD OFF CB 1 SD OFF 0 SD Offset Cr SD OFF 7 SD OFF CR 6 SD OFF CR 5 SD OFF CR4 SD OFF CR3 SD OFF CR2 SD OFF CR 1 SD OFF 0 SD Saturation Cb SD SAT CB7 SD SAT CB 6 SD SAT CB 5 SD SAT 4 SD SAT CB 3 SD SAT CB2 SD SAT CB 1 SD SAT CB 0 SD Saturation Cr SD SAT CR 7 SD SAT CR 6 SD SAT CR 5 SD SAT CR 4 SD SAT CR 3 SD SAT CR 2 SD SAT CR 1 SD SAT 0 NTSC V Bit Begin NVBEGDEL O NVBEGDEL E NVBEGSIGN NVBEG 4 NVBEG 3 NVBEG 2 NVBEG 1 NVBEG O NTSC V Bit End NVENDDEL O NVENDDEL NVENDSIGN NVEND 4 NVEND 3 NVEND 2 NVEND 1 NVEND O NTSC F Bit Toggle NFTOGDEL O NFTOGDEL E NFTOGSIGN NFTOG 4 NFTOG 3 NFTOG 2 1 0 PAL V Begin PVBEGDEL O PVBEGDEL E PVBEGSIGN 4 PVBEG 3 PVBEG 2 PVBEG 1 0 PAL V End PVENDDEL O PVENDDEL E PVENDSIGN PVEND 4 PVEND 3 PVEND 2 PVEND 1 PVEND O PAL F Bit Toggle PFTOGDEL O PFTOGDEL E PFTOGSIGN PFTOG 4 PFTOG 3 PFTOG 2 PFTOG 1 0 Reserved Drive Strength DR STR 1 DR STR O DR STR C 1 DR STR CO DR STR S 1 DR STR 5 0 Reserved IF Comp Control IFFILTSEL 2 IFFILTSEL 1 IFFILTSEL O VS Mode Control VS COAST VS COAST EXTEND VS EXTEND VS MODE 1 MODE O MIN_FREQ MAX_FREQ
72. Field VSEHE 0 VS goes low in the middle NEWAVMODE bit Control 3 of the line even field must be set high 1 VS changes state at the start of the line even field VSEHO 0 VS goes low in the middle of the line odd field VS changes state at the start of the line odd field Rev B Page 78 of 100 ADV7183B Bits Subaddress Register Bit Description 716 154 3 2 1 0 Comments Notes 0 34 HS Position HSE 10 8 HS end allows the 0 O O HS output ends HSE 10 0 Using HSB and HSE Control 1 positioning of the HS output within pixels after the falling the user can program the video line edge of Hsync the position and Reserved 0 Set to 0 length of the output HSB 10 8 HS begin allows the 1 HS output starts positioning of the HS output within HSB 10 0 pixels after the the video line falling edge of Hsync Reserved 0 Set to 0 0x35 HS Position HSB 7 0 Using HSB 10 0 and Control 2 HSE 10 0 the user can program the position and length of HS output signal 0x36 HS Position HSE 7 0 See above Control 3 0 37 Polarity PCLK Sets the polarity of 0 Invert polarity 1 Normal polarity as per the timing diagrams Reserved Set to 0 PF Sets the FIELD polarity 0 Active high 1 Active low Reserved 0 Se
73. HUE 7 HUE 6 HUE 5 HUE 4 HUE 3 HUE 2 HUE 1 HUE O Default Value Y DEF 5 DEF Y 4 DEF Y 3 DEF Y 2 DEF Y 1 DEF 0 DEF VAL DEF VAL EN AUTO EN Default Value C DEF C7 DEF C 6 DEF C 5 DEF C4 DEF DEF C2 DEF C 1 DEF 0 ADI Control SUB USR 0 Power Management RES PWRDN PDBP Status 1 COL KILL AD RESULT 2 AD RESULT 1 AD RESULT O FOLLOW PW FSC LOCK LOST LOCK LOCK Ident IDENT 7 IDENT 6 IDENT 5 IDENT 4 IDENT 3 IDENT 2 IDENT 1 IDENT O Status 2 FSC NSTD LL NSTD MV AGC DET MV PS DET MVCS MVCS DET Status 3 PAL SW LOCK INTERLACE STD FLD LEN FREE RUN ACT SD OP 50HZ GEMD INST HLOCK Analog Clamp Control CCLEN Digital Clamp Control 1 DCT 1 DCT 0 Reserved Shaping Filter Control CSFM 2 CSFM 1 5 0 YSFM 4 YSFM 3 YSFM 2 YSFM 1 5 0 Shaping Filter Control 2 WYSFMOVR WYSFM 4 WYSFM 3 WYSFM 2 WYSFM 1 WYSFM O Comb Filter Control NSFSEL 1 NSFSEL O PSFSEL 1 PSFSEL O Reserved ADI Control 2 TRI_LLC EN28XTAL VS_JIT_ COMP_EN Reserved Pixel Delay Control SWPC AUTO_PDC_EN CTA 2 CTA 1 CTA O LTA 1 LTA O Reserved Misc Gain Control CKE PW UPD AGC Mode Control LAGC 2 LAGC 1 LAGC O CAGC 1 0 Chroma Gain Control 1 1 0 CMG 11 CMG 10 CMG 9 CMG 8 Chroma Gain Control 2 CMG 7 CMG 6 CMG 5 CMG 4 CMG 3 CMG 2 CMG 1 CMG 0 Luma Gain Control 1 LAGT 1 0 LMG 11 LMG 10 LMG 9 LMG 8 Luma Gain Control 2 LMG 7 LMG 6 LMG 5 LMG 4 LMG 3 LMG 2 LMG 1 LMG O Vsync Field Control 1 NEWAVMODE HVSTIM Vsync Field Control 2 VSBHO VSBHE Vsync Field Control 3
74. I RANGE Range Selection Address 0 04 0 AV codes as per ITU R BT 656 formerly known as CCIR 656 consist of a fixed header made up of OxFF and 0x00 values These two values are reserved and therefore cannot be used for active video Additionally the ITU specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and 16 to 240 for chroma The RANGE bit allows the user to limit the range of values output by the ADV7183B to the recommended value range In any case it ensures that the reserved values of 255d and 00d 0x00 are not presented on the output pins unless they are part of an AV code header Table 52 RANGE Function LTA 1 0 Luma Timing Adjust Address 0x27 1 0 The Luma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples There is a certain functionality overlap with the CTA 2 0 register For manual programming use the following defaults e CVBS input LTA 1 0 00 e Y Cinput LTA 1 0 01 e YPrPb input LTA 1 0 01 Table 53 LTA Function LTA 1 0 Description 00 default No delay 01 1 37 ns delayed 10 Luma 2 clk 74 ns early 11 Luma 1 clk 37 ns early RANGE Description 0 16 lt Y lt 235 16 lt C P lt 240 1 default 1 lt lt 254 1 lt lt 254 AUTO EN Automatic Programmed Delay Control Address 0 27 6 Enabling the AUTO
75. IFICATION ae DATA OPTIONAL PADDING CHECK V V PREAMBLE FOR ANCILLARY DATA USER 4 8 WORDS 04997 035 Figure 35 Gemstar CCAP Embedded Data Packet Generic Table 64 Generic Data Output Packet Byte 0191 0181 D 7 DI6 0151 0 4 0121 D 1 0 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 2 Line 3 0 0 0 SDID 5 0 0 0 0 DC 1 DC 0 0 0 Data count DC 6 0 0 7 4 0 0 User data words 7 0 0 1 3 0 0 0 User data words 8 0 0 Word2 7 4 0 0 User data words 9 IEP EP 0 0 Word2 3 0 0 0 User data words 10 0 0 Word3 7 4 0 0 User data words 11 IEP EP 0 0 Word3 3 0 0 0 User data words 12 0 0 47 41 0 0 User data words 13 0 0 Word4 3 0 0 0 User data words 14 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 0 0 Checksum Rev B Page 51 of 100 ADV7183B Table 65 Data Byte Allocation Raw Information Bytes User Data Words 2x Retrieved from the Video Line GDECAD Including Padding Padding Bytes DC 1 0 1 4 0 8 0 10 1 4 1 4 0 01 0 2 0 4 0 01 0 2 1 4 2 01 Gemstar Bit Names DID The data identification value is 0 140 10 bit v
76. INST HLOCK Horizontal lock indicator instantaneous 1 GEMD Gemstar detect 2 SD OP 50HZ Flags whether 50 Hz or 60 Hz are present at output 3 Reserved for future use 4 FREE RUN ACT Outputs a blue screen see the DEF VAL AUTO EN Default Value Automatic Enable Address OxOC 1 section 5 STD FLD LEN Field length is correct for currently selected video standard 6 INTERLACED Interlaced video detected field sequence found 7 PAL SW LOCK Reliable sequence of swinging bursts detected Rev B Page 19 of 100 ADV7183B STANDARD DEFINITION PROCESSOR SDP STANDARD DEFINITION PROCESSOR MACROVISION VBI DATA STANDARD DETECTION RECOVERY AUTODETECTION LUMA GAIN FILTER CONTROL DIGITIZED CVBS DIGITIZED Y YC LINE SYNC LENGTH EXTRACT pREpICTOR E IN DIGITIZED CVBS DIGITIZED C YC E LUMA RESAMPLE AV RESAMPLE CODE CONTROL INSERTION CHROMA RESAMPLE SLLC CONTROL LUMA VIDEO DATA OUTPUT MEASUREMENT HROMA 2 COMB E BLock gt VIDEO DATA PROCESSING BLOCK 04997 008 Figure 8 Block Diagram of the Standard Definition Processor A block diagram of the ADV7183B s standard definition processor SDP is shown in Figure 8 The SDP block can handle standard definition video in CVBS Y C and YPrPb formats It can be divided into a luminance and a chrominance path If the input video is of a composite type CVBS both processing paths are
77. IX X X x Reports the number of This feature examines Read Only Letterbox data register black lines detected at the active video at the the top of active video start and at the end of Ox9C Letterbox2 LB 01 x x Reports the number of each field It enables Read Only Letterbox data register black lines detected in format detection even the bottom half of if the video 4 22 subtitles CGMS or WSS are detected sequence Ox9D Letterbox3 LB LCB 7 0 Reports the number of Read Only Letterbox data register black lines detected at the bottom of active video 0 2 CRC Reserved Set as default CRC ENABLE Enable CRC checksum Turn off CRC check decoded from CGMS packet to CGMSD goes high with Register validate CGMSD 2 3 valid checksum Reserved Set as default Rev B Page 83 of 100 ADV7183B Subaddress Register Bit Description Bits Comments Notes OxC3 ADC SWITCH 1 ADCO SW 3 0 Manual muxing control for ADCO No connection AINT No connection No connection AIN9 10 11 12 gt
78. LOCK SFL_INV Subcarrier Frequency Lock Inversion This bit controls the behavior of the PAL switch bit in the SFL GenLock Telegram data stream It was implemented to solve some compatibility issues with video encoders It solves two problems First the PAL switch bit is only meaningful in PAL Some encoders including ADI encoders also look at the state of this bit in NTSC Second there was a design change in ADI encoders from ADV717x to ADV719x The older versions used the SFL Genlock Telegram bit directly while the later ones invert the bit prior to using it The reason for this is that the inversion compensated for the 1 line delay of an SFL GenLock Telegram transmission As a result ADV717x encoders need the PAL switch bit in the SFL Genlock Telegram to be 1 for NTSC to work and ADV7190 ADV7191 ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC If the state of the PAL switch bit is wrong a 180 phase shift occurs In a decoder encoder back to back system in which SFL is used this bit must be set up properly for the specific encoder used SFL_INV Address 0x41 6 Setting SFL_INV to 0 makes the part SFL compatible with ADV7190 ADV7191 ADV7194 encoders Setting SFL_INV to 1 default makes the part SFL compatible with ADV717x ADV7173x encoders Lock Related Controls Lock information is presented to the user through Bits 1 0 of the Status 1 register See the STATUS_1 7 0 Address 0x1
79. LTT 2 0 bits report back on the findings from the autodetection block For more information on enabling the autodetection block see the General Setup section For information on configuring it see the Autodetection of SD Modes section Table 14 RESULT Function Table 15 STATUS 1 Function ADV7183B STATUS 1 7 0 Name Description 0 IN LOCK In lock right now 1 LOST LOCK Lost lock since last read of this register 2 FSC LOCK Fsc locked right now 3 FOLLOW PW AGC follows peak white algorithm 4 AD RESULT Result of autodetection 5 AD RESULT 1 Result of autodetection 6 AD RESULT 2 Result of autodetection 7 COL KILL Color kill active STATUS 2 STATUS 2 7 0 Address 0 12 7 0 Table 16 STATUS 2 Function STATUS 2 7 0 BitName Description 0 MVCS DET Detected Macrovision color striping 1 MVCS T3 Macrovision color striping protection Conforms to Type 3 if high and to Type 2 if low 2 MV PS DET Detected Macrovision pseudo sync pulses 3 MV Detected Macrovision AGC pulses 4 LL NSTD Line length is nonstandard 5 FSC NSTD Fsc frequency is nonstandard 6 Reserved 7 Reserved STATUS 3 STATUS 3 7 0 Address 0x13 7 0 Table 17 STATUS 3 Function AD RESULT 2 0 Description 000 NTSM MJ 001 NTSC 443 010 PAL M 011 PAL 60 100 PAL BGHID 101 SECAM 110 PAL Combination N 111 SECAM 525 STATUS 3 7 0 Name Description 0
80. OL 2 Not valid 15 11 GDECOL 3 Not valid 2 0 12 GDECOLI4 Not valid 1 13 GDECOL 5 Not valid 2 14 GDECOL 6 Not valid 3 15 GDECOL 7 Not valid 4 16 GDECOL 8 Not valid 8 5 17 GDECOLI9 Not valid FREQUENCY MHz 8 6 18 GDECOL 10 Not valid Figure 36 NTSC IF Compensation Filter Responses 7 19 GDECOL 11 Not valid 8 20 GDECOL 12 Not valid 9 21 GDECOL 13 Not valid 10 22 GDECOL 14 Closed caption 11 23 GDECOL 15 Not valid 12 321 8 Not valid ur 13 322 9 GDECEL 1 Not valid S 14 323 10 GDECEL 2 Not valid z 15 324 11 GDECEL 3 Not valid lt 0 325 12 GDECEL A Not valid 1 326 13 GDECEL 5 Not valid 2 327 14 GDECEL 6 Not valid 3 328 15 GDECEL 7 Not valid 4 329 16 GDECEL 8 Not valid FREQUENCY MHz 8 5 330 17 GDECEL 9 Not valid Figure 37 PAL IF Compensation Filter Responses E F is See Table 86 for programming details 8 333 20 GDECEL 12 Not valid PC Interrupt System 9 334 21 GDECELI13 Not valid The ADV7183B has a comprehensive interrupt register set This 10 335 22 GDECEL 14 Closed caption map is located in Register Access Page 2 See Table 84 for details H 336 23 GDECELI15 Not valid of the interrupt register map IF Compensation Filter How to access this map is described in Figure 38 FILTSEL 2 0 IF Filter Select Address OxF8 2 0 The IF FILTSEL 2 0 register allows the user to compensate for SAW filter characteristics on a composite input as obse
81. SDA and SCLK lines waiting for the start condition and the correct transmitted see EET Sy C SCLOCK 1 7 8 9 START ADDR R W SUBADDRESS DATA ACK address The R W bit determines the direction of the data Logic 0 on the LSB of the first byte means the master writes information to the peripheral Logic 1 on the LSB of the first byte means the master reads information from the peripheral The ADV7183B acts as a standard slave device on the bus The data on the SDA pin is eight bits long supporting the 7 bit addresses and the R W bit The ADV7183B has 249 subad dresses to enable access to the internal registers It therefore interprets the first byte as the device address and the second byte as the starting subaddress The subaddresses auto increment which allows data to be written to or read from the starting sub address A data transfer is always terminated by a stop condition The user can also access any unique subaddress register on a one by one basis without updating all the registers Stop and start conditions can be detected at any stage during the data transfer If these conditions are asserted out of sequence with normal read and write operations they cause an immediate jump to the idle condition During a given SCLK high period the user should only issue one start condition one stop condition or a single stop condition followed by a single start condition If an invalid subaddress is issued by the user th
82. SN 11 100 Disable chroma comb 101 Fixed chroma comb top lines of line memory Fixed 2 line chroma comb for CTAPSN 01 Fixed 3 line chroma comb for CTAPSN 10 Fixed 4 chroma comb for CTAPSN 11 110 Fixed chroma comb all lines of line memory Fixed 3 line chroma comb for CTAPSN 01 Fixed 4 line chroma comb for CTAPSN 10 Fixed 5 line chroma comb for CTAPSN 11 111 Fixed chroma comb bottom lines of line memory Fixed 2 line chroma comb for CTAPSN 01 Fixed 3 line chroma comb for CTAPSN 10 Fixed 4 chroma comb for CTAPSN 11 YCMN 2 0 Luma Comb Mode NTSC Address 0x38 2 0 Table 47 Y CMN Function YCMN 2 0 Description Oxx default Adaptive comb mode Adaptive 3 line 3 taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb top lines of line memory Fixed 2 line 2 taps luma comb 110 Fixed luma comb all lines of line memory Fixed 3 line 3 taps luma comb 111 Fixed luma comb bottom lines of line memory Fixed 2 line 2 taps luma comb Rev B Page 35 of 100 ADV7183B PAL Comb Filter Settings Table 48 PSFSEL Function Used for PAL B G H I D PAL M PAL Combination PSFSEL 1 0 Description PAL60 and NTSC443 CVBS inputs Narrow 01 default Medium PSFSEL 1 0 Split Filter Selection PAL 10 Wide Address 0x19 1 0 11 Widest The PSFSEL 1 0 control selects how much of the overall signal bandwid
83. TH2 CTI C TH 1 CTI C TH O Reserved CTI DNR Ctrl 4 DNR TH 7 DNR TH 6 DNR TH 5 DNR 4 DNR TH 3 DNR TH 2 DNR TH 1 DNR 0 Lock Count FSCLE SRLS COL 2 COL 1 COL O CIL 2 CIL 1 CIL O Reserved Free run Line Length 1 PAD SEL 2 LLC PAD SEL 1 PAD SEL O Reserved VBI Info CGMSD EDTVD CCAPD WSSD WSS 1 WSS1 7 WSS1 6 WSS1 5 WSS1 4 WSS1 3 WSS1 2 WSS1 1 WSS1 0 55 2 WSS2 7 WSS2 6 WSS2 5 WSS2 4 WSS2 3 WSS2 2 WSS2 1 WSS2 0 EDTV 1 EDTV1 7 EDTV1 6 EDTV1 5 EDTV1 4 EDTV1 3 EDTV1 2 EDTV1 1 EDTV1 0 EDTV 2 EDTV2 7 EDTV2 6 EDTV2 5 EDTV2 4 EDTV2 3 EDTV2 2 EDTV2 1 EDTV2 0 EDTV 3 EDTV3 7 EDTV3 6 EDTV3 5 EDTV3 4 EDTV3 3 EDTV3 2 EDTV3 1 EDTV3 0 CGMS 1 CGMS1 7 CGMS1 6 CGMS1 5 CGMS1 4 CGMS1 3 CGMS1 2 CGMS1 1 CGMS1 0 CGMS 2 CGMS2 7 CGMS2 6 CGMS2 5 CGMS2 4 CGMS2 3 CGMS2 2 CGMS2 1 CGMS2 0 CGMS3 CGMS3 7 CGMS3 6 CGMS3 5 CGMS3 4 CGMS3 3 CGMS3 2 CGMS3 1 CGMS3 0 CCAP1 CCAP1 7 1 6 1 5 CCAP1 4 CCAP1 3 CCAP1 2 CCAP1 1 CCAP1 0 CCAP2 CCAP2 7 CCAP2 6 CCAP2 5 CCAP2 4 CCAP2 3 CCAP2 2 CCAP2 1 CCAP2 0 Letterbox 1 LB_LCT 7 LB_LCT 6 LB_LCT 5 LB_LCT 4 LB_LCT 3 LB_LCT 2 LB_LCT 1 LB LCT O Letterbox 2 LB LCM 7 LB LCM 6 LB LCM 5 LB LCM 4 LB LCM 3 LB LCM 2 LB LCM 1 LB LCM 0 Letterbox 3 LB LCB 7 LB LCB 6 LB LCB 5 LB LCB 4 LB LCB 3 LB LCB 2 LB LCB 1 LB LCB O Reserved CRC Enable CRC ENABLE Reserved ADC Switch 1 ADC1 SW 3 ADC1 SW 2 ADC1 SW 1 1 5 0 SW 3 SW 2 ADCO SW 1 SW 0 ADC Switch 2 SW M ADC2 SW 3 ADC2 SW 2 AD
84. VSEHO VSEHE Hsync Position Control 1 HSB 10 HSB 9 HSB 8 HSE 10 HSE 9 HSE 8 Hsync Position Control 2 HSB 7 HSB 6 5 5 HSB 4 HSB 3 HSB 2 HSB 1 5 0 Hsync Position Control 3 HSE 7 HSE 6 HSE 5 HSE 4 HSE 3 HSE 2 HSE 1 5 0 Polarity PHS 5 PCLK NTSC Comb Control CTAPSN 1 CTAPSN O CCMN 2 CCMN 1 CCMN O YCMN 2 YCMN 1 YCMN O PAL Comb Control CTAPSP 1 5 0 2 CCMP 1 0 2 YCMP 1 0 Control PWRDN ADC 0 PWRDN ADC PWRDN ADC 2 1 Reserved Manual Window Control CKILLTHR 2 CKILLTHR 1 0 Rev 64 of 100 ADV7183B Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Resample Control SFL_INV Reserved Gemstar Ctrl 1 GDECEL 15 GDECEL 14 GDECEL 13 GDECEL 12 GDECEL 11 GDECEL 10 GDECEL 9 GDECEL 8 Gemstar Ctrl 2 GDECEL 7 GDECEL 6 GDECEL 5 GDECEL 4 GDECEL 3 GDECEL 2 GDECEL 1 GDECEL O Gemstar Ctrl 3 GDECOL 15 GDECOL 14 GDECOL 13 GDECOL 12 GDECOL 11 GDECOL 10 GDECOL 9 GDECOL 8 Gemstar Ctrl 4 GDECOL 7 GDECOL 6 GDECOL 5 GDECOL 4 GDECOL 3 GDECOL 2 GDECOL 1 GDECOL O Gemstar Ctrl 5 GDECAD CTI DNR Ctrl 1 DNR_EN CTI_AB 1 0 CTI DNR Ctrl 2 CTI_C_TH 7 CTI_C_TH 6 5 C 4 CTI C TH 3 CTI C
85. VSYNC BY NVBEG 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO 0 0 1 1 ADVANCE BY 0 5 LINE 1 0 0 ADVANCE BY 0 5 LINE Figure 23 NTSC Vsync Begin 04997 023 NVBEGDELO NTSC Vsync Begin Delay on Odd Field Address 0xE5 7 When NVBEGDELO is 0 default there is no delay Setting NVBEGDELO to 1 delay Vsync going high on an odd field by a line relative to NVBEG NVBEGDELE NTSC Vsync Begin Delay on Even Field Address 0xE5 6 When NVBEGDELE is 0 default there is no delay Setting NVBEGDELE to 1 delays Vsync going high on an even field by a line relative to NVBEG NVBEGSIGN NTSC Vsync Begin Sign Address OxE5 5 Setting NVBEGSIGN to 0 delays the start of Vsync Set for user manual programming Setting NVBEGSIGN to 1 default advances the start of Vsync Not recommended for user programming NVBEG 4 0 NTSC Vsync Begin Address 0xE5 4 0 The default value of NVBEG is 00101 indicating the NTSC Vsync begin position For all NTSC PAL Vsync timing controls both the V bit in the AV code and the Vsync on the VS pin are modified Rev B Page 42 of 100 ADV7183B ADVANCE END OF VSYNC BY NVEND 4 0 DELAY END OF VSYNC BY NVEND 4 0 1 0 0 1 ADVANCE BY ADVANCE BY 0 5 LINE 0 5 LINE 04997 024 VSYNC END Figure 24 NTSC Vsync End NVENDDELO NTSC Vsync End Delay on Odd Field Address 0xE6 7 When NVENDDELO is 0 default there is no delay Setting NVENDDELO to
86. alue Care has been taken that in 8 bit systems the two LSBs do not carry vital information EP and EP The EP bit is set to ensure even parity on the data word D 8 0 Even parity means there will always be an even number of 1s within the D 8 0 bit arrangement This includes the EP bit describes the logic inverse of EP and is output on D 9 The EP is output to ensure that the reserved codes of 00 and FF cannot happen EF Even field identifier EF 1 indicates that the data was recovered from a video line on an even field 2X This bit indicates whether the data sliced was in Gemstar 1x or 2x format A high indicates 2x format Line 3 0 This entry provides a code that is unique for each of the possible 16 source lines of video from which Gemstar data can be retrieved Refer to Table 74 and Table 75 DC 1 0 Data count value The number of user data words in the packet divided by 4 The number of user data words UDW in any packet must be an integral number of 4 Padding is required at the end if necessary as set in ITU R BT 1364 See Table 65 The 2X bit determines whether the raw information retrieved from the video line was 2 or 4 bytes The state of the GDECAD bit affects whether the bytes are transmitted straight that is two bytes transmitted as two bytes or whether they are split into nibbles that is two bytes transmitted as four half bytes Padding bytes are then added where necessary CS 82 The
87. and appears in the appropriate registers with the next field transition They are then static until the next field The user should start an read sequence with VS by first examining the VBI Info register Then depending on what data was detected the appropriate data registers should be read Note that the data registers are filled with decoded VBI data even if their corresponding detection bits are low it is likely that bits within the decoded data stream are wrong The closed captioning data CCAP is available in the registers and is also inserted into the output video data stream during horizontal blanking The Gemstar compatible data is not available in registers and is inserted into the data stream only during horizontal blanking WSSD Wide Screen Signaling Detected Address 0 90 0 Logic 1 for this bit indicates the data in the WSS1 and WSS2 registers is valid The WSSD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the data transmitted When WSSD is 0 no WSS is detected and confidence in the decoded data is low When WSSD is 1 WSS is detected and confidence in the decoded data is high CCAPD Closed Caption Detected Address 0x90 1 A Logic 1 for this bit indicates that the data in the CCAP1 and CCAP registers is valid The CCAPD bit goes high if the rising edge of the start bit is detected within a time
88. ar that the decoder checks compatible data Control 4 column f ibl p or Gemstar compatible any lines 10 to 25 in data odd fields 0x4C Gemstar GDECAD Controls the manner in Split data into half byte To avoid 00 FF code Control 5 which decoded Gemstar data is inserted into the horizontal blanking period Output in straight 8 bit format Reserved Undefined 0 4 DNR Disable Control 1 Enable Enables the of Disable alpha blender the transient improved chroma with Enable alpha blender the original signal AB 1 0 Controls the behavior 0 Sharpest mixing of the alpha blend circuitry 011 Sharp mixing 110 Smooth 1 1 Smoothest Reserved 0 Set to default DNR EN Enable or bypass the DNR 0 Bypass the DNR block block 1 Enable the DNR block Reserved 1 Set to default Ox4E CTI DNR CTI CTH 7 0 Specifies how big the 010101011 0 Set to 0x04 for A V input Control 2 amplitude step must be to be set to OxOA for tuner steepened by the CTI block input 0x50 CTI DNR DNR TH 7 0 Specifies the 0 0 0 1 0 Control 4 maximum edge that is interpreted as noise and is therefore blanked Rev B Page 81 of 100 ADV7183B Bits Subaddre
89. arity of the LLC clock output can be necessary to meet the setup and hold time expectations of follow on chips This bit also inverts the polarity of the LLC2 clock When PCLK is 0 the LLC output polarity is inverted When PCLK is 1 default the LLC output polarity is normal as per the timing diagrams Rev B Page 18 of 100 GLOBAL STATUS REGISTERS Four registers provide summary information about the video decoder The IDENT register allows the user to identify the revision code of the ADV7183B The three other registers contain status bits regarding IC operation IDENTIFICATION IDENT 7 0 Address 0x11 7 0 This register provides identification of the revision of the ADV7183B An identification value of 0x11 indicates the ADV7183 released silicon An identification value of 0x13 indicates the ADV7183B silicon STATUS 1 STATUS 1 7 0 Address 0x10 7 0 This read only register provides information about the internal status of the ADV7183B See VS Coast 1 0 Address 0xF9 3 2 CIL 2 0 Count Into Lock Address 0 51 2 0 and COL 2 0 Count Out of Lock Address 0 51 5 3 for information on the timing Depending on the setting of the FSCLE bit the Status 0 and Status 1 bits are based solely on horizontal timing information on the horizontal timing and lock status of the color subcarrier See the FSCLE FSC Lock Enable Address 0x51 7 section AUTODETECTION RESULT AD RESULT 2 0 Address 0x10 6 4 The AD RESU
90. atly improved ei pare Rees to automatically handle video of all types standards and levels 00 default Narrow 5 01 of quality The NTSC and PAL configuration registers allow user to customize comb filter operation depending on which 11 Wide video standard is detected by autodetection or selected by manual programming In addition to the bits listed in this section there are some other ADI internal controls contact CTAPSN 1 0 Chroma Comb Taps NTSC Address x38 7 6 ADI for more information Table 45 CTAPSN Function CTAPSN 1 0 Description NTSC Comb Filter Settings 00 Used for NTSC M J CVBS inputs 01 NTSC chroma comb adapts 3 lines 3 taps to 2 lines 2 taps NSFSEL 1 0 Split Filter Selection NTSC Address 10 default NTSC chroma comb adapts 5 lines 5 taps to 0x19 3 2 3 lines 3 taps The NSFSEL 1 0 control selects how much of the overall signal 11 NTSC chroma comb adapts 5 lines 5 taps to bandwidth is fed to the combs A narrow split filter selection 4 lines 4 taps gives better performance on diagonal lines but leaves more dot crawl in the final output image the opposite is true for selecting a wide bandwidth split filter CCMN 2 0 Chroma Comb Mode NTSC Address 0 38 5 3 Table 46 CCMN Function CCMN 2 0 Description Oxx default Adaptive comb mode Adaptive 3 line chroma comb for CTAPSN 01 Adaptive 4 line chroma comb for CTAPSN 10 Adaptive 5 line chroma comb for CTAP
91. bles performance video decoding and conversion in line locked clock based systems This makes the device ideally suited for a broad range of applications with diverse analog video characteristics including tape based sources broadcast sources security surveillance cameras and professional systems The 10 bit accurate A D conversion provides professional quality video performance and is unmatched This allows true 8 bit resolution in the 8 bit output mode The 12 analog input channels accept standard composite S Video YPrPb video signals in an extensive number of Rev B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 0 5 V to 1 6 V analog signal input range Differential gain 0 5 typ Differential phase 0 5 typ Programmable video controls Peak white hue brightness saturation contrast Integrated on chip video timing generator Free run mode generates stable video output with no decode support for close captioning WSS CGMS EDTV Gemstar 1x 2x Power down mode 2 wire serial MPU interface IC
92. can be used to selectively reduce the luma video signal bandwidth needed prior to scaling for example For some video sources that contain high frequency noise reducing the bandwidth of the luma signal improves visual picture quality A follow on video compression stage can work more efficiently if the video is low pass filtered The ADV7183B has two responses for the shaping filter one that is used for good quality CVBS component and S VHS type sources and a second for nonstandard CVBS signals The YSH filter responses also include a set of notches for PAL and NTSC However using the comb filters for Y C separation is recommended e Digital Resampling Filter This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actual response is selected by the system and user intervention is not required Figure 12 through Figure 15 show the overall response of all filters together Unless otherwise noted the filters are set into a typical wideband mode Rev B Page 26 of 100 ADV7183B Y Shaping Filter For input signals in CVBS format the luma shaping filters play an essential role in removing the chroma component from a composite signal Y C separation must aim for best possible crosstalk reduction while still retaining as much bandwidth especially on the luma component as possible High quali
93. ch the lock condition must be true before the system switches into This register allows the user to control the gain of the Cb channel only The user can adjust the saturation of the picture Table 23 SD SAT Cb Function the locked state and reports this via Status 0 1 0 It counts the SD SAT Cb 7 0 Description value in lines of video 0x80 default Gain on Cb channel 0 dB Table 20 CIL Function 0x00 channel 42 dB CIL 2 0 Description OxFF Gain on Cb channel 6 dB 000 1 001 2 010 5 011 10 100 default 100 101 500 110 1000 111 100000 Rev B Page 23 of 100 ADV7183B SD_SAT_Cr 7 0 SD Saturation Cr Channel Address OxEA 7 0 This register allows the user to control the gain of the Cr channel only The user can adjust the saturation of the picture Table 24 SD SAT Cr Function SD SAT Cr 7 0 Description 0x80 default Gain on Cr channel 0 dB 0x00 Gain Cb channel 42 dB OxFF Gain on Cb channel 6 dB SD OFF Cb 7 0 SD Offset Cb Channel Address 0 1 7 0 This register allows the user to select an offset for data on the Cb channel only and adjust the hue of the picture There is a HUE 7 0 Hue Adjust Address 0x0B 7 0 This register contains the value for the color hue adjustment It allows the user to adjust the hue of the picture HUEQ 7 0 has a range of 90 with 0x00 equivalent to an adjustment of 0 The resolution of
94. checksum is provided to determine the integrity of the ancillary data packet It is calculated by summing up D 8 2 of DID SDID the Data Count byte and all UDWs and ignoring any overflow during the summation Since all data bytes that are used to calculate the checksum have their two LSBs set to 0 the CS 1 0 bits are also always 0 1 5181 describes the logic inversion of CS 8 The value ICS 8 is included in the checksum entry of the data packet to ensure the reserved values of 0x00 and OxFF do not occur Table 66 to Table 71 outline the possible data packages Gemstar 2x Format Half Byte Output Mode Half byte output mode is selected by setting CDECAD 0 full byte output mode is selected by setting CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Gemstar 1x Format Half byte output mode is selected by setting CDECAD 0 full byte output mode is selected by setting CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Rev B Page 52 of 100 ADV7183B Table 66 Gemstar 2x Data Half Byte Mode Byte 0191 0181 DI7 DI6 0151 0141 0121 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1
95. cription of the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 bit e Data is closed caption CCAP or Gemstar compatible Data packets are output if the corresponding enable bit is set see the GDECEL and GDECOL descriptions and if the decoder detects the presence of data This means that for video lines where no data has been decoded no data packet is output even if the corresponding line enable bit is set Each data packet starts immediately after the EAV code of the preceding line See Figure 35 and Table 64 which show the overall structure of the data packet DATA IDENTIFICATION ADV7183B Entries within the packet are as follows e Fixed preamble sequence of 0x00 OxFF OxFF e Data identification word DID The value for the DID marking a Gemstar or CCAP data packet is 0x140 10 bit value e Secondary data identification word SDID contains information about the video line from which data was retrieved whether the Gemstar transmission was of 1x or 2x format and whether it was retrieved from an even or odd field Data count byte giving the number of user data words that follow User data section e Optional padding to ensure the length of the user data word section of a packet is a multiple of four bytes requirement as set in ITU R BT 1364 Checksum byte Table 64 lists the values within a generic data packet that is output by the ADV7183B in 8 bit format SECONDARY DATA IDENT
96. d from to the target address which then increments to the next address until a stop command on the bus is performed REGISTER PROGRAMMING This section describes the configuration of each register The communications register is an 8 bit write only register After the part has been accessed over the bus and a read write operation is selected the subaddress is set up The subaddress register determines to from which register the operation takes place Table 82 lists the various operations under the control of the subaddress register for the control port Register Select SR7 to SRO These bits are set up to point to the required starting address ADV7183B SEQUENCER An sequencer is used when a parameter exceeds eight bits and is therefore distributed over two or more registers such as HSB 11 0 When such a parameter is changed using two or more I C write operations the parameter can hold an invalid value for the time between the first completion and last completion This means the top bits of the parameter can already hold the new value while the remaining bits of the parameter still hold the previous value To avoid this problem the sequencer holds the already updated bits of the parameter in local memory all bits of the parameter are updated together once the last register write operation has completed The correct operation of the sequencer relies on the following
97. de bus 16 bit output modes See the OF_SEL 3 0 Output Format Selection Address 0x03 5 2 section for additional information The LLC2 signal and data on the data bus are synchronized By default the rising edge of LLCI LLC2 is aligned with the Y data the falling edge occurs when the data bus holds C data The polarity of the clock and therefore the Y C assignments to the clock edges can be altered by using the Polarity LLC pin When LLC PAD SEL 2 0 is 000 default the output is nominally 27 MHz LLC on the LLCI pin When LLC PAD SEL 2 0 is 101 the output is nominally 13 5 MHz LLC on the LLCI pin Data Port Pins P 15 0 Format and Mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Video Out 8 Bit 4 2 2 YCrCb 7 0 OUT Video Out 16 Bit 4 2 2 Y 7 0 OUT CrCb 7 0 OUT Table 80 Standard Definition Pixel Port Modes P 15 0 OF SEL 3 0 Format P 15 8 P 7 0 0010 16 bit LLC2 4 2 2 Y 7 0 CrCb 7 0 0011 default 8 bit LLC1 4 2 2 default YCrCb 7 0 default Three state 0110 1111 Reserved Reserved Do not use Rev B Page 59 of 100 ADV7183B MPU PORT DESCRIPTION The ADV7183B supports 2 wire I C compatible serial inter face Two inputs serial data SDA and serial clock SCLK carry information between the ADV7183B and the system master controller Each slave device is recognized by a unique address The ADV71
98. ded setting 0 70 0 00 Recommended setting 0 48 Recommended setting OxD5 Recommended setting OxD7 Recommended setting OxE4 Ox3E Recommended setting 9 Recommended setting Recommended setting 0 00 Recommended setting 92 of 100 Mode 3 5251 6251 YPrPb Input AIN2 PB AIN3 and PR All standards are supported through autodetect 8 bit ITU R BT 656 output on P15 to P8 Table 93 Mode 3 YPrPb Input 525i 625i ADV7183B Register Address Register Value Notes 0x00 0x50 OxOE 0x52 0x58 0x77 0 7 0 70 OxD5 OxE4 OxE9 OxOE 0 04 0 80 0 18 OxED OxC5 0 93 0 00 0 48 0 00 Y2 PB2 AIN3 PR2 AIN6 Set DNR threshold to 4 for flat response ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Mode 4 CVBS Tuner Input PAL Only on AIN4 8 bit ITU R BT 656 output on P15 to P8 Table 94 Mode 4 Tuner Input CVBS PAL Only Register Address Register Value Notes 0x00 0x07 0x15 0x17 0x19 0 50 OxOE 0
99. default value for Cr and Cb Rev B Page 24 of 100 ADV7183B DEF VAL EN Default Value Enable Address 0x0C 0 This bit forces the use of the default values for Y Cr and Cb Refer to the descriptions for DEF_Y and DEF_C for additional information In this mode the decoder also outputs a stable 27 MHz clock HS and VS Setting DEF_VAL_EN to 0 default outputs a colored screen determined by user programmable Y Cr and Cb values when the decoder free runs Free run mode is turned on and off by the DEF_VAL_AUTO_EN bit Setting DEF_VAL_EN to 1 forces a colored screen output determined by user programmable Y Cr and Cb values This overrides picture data even if the decoder is locked DEF_VAL_AUTO_EN Default Value Automatic Enable Address 0x0C 1 This bit enables the automatic usage of the default values for Y Cr and Cb when the ADV7183B cannot lock to the video signal Setting DEF_VAL_AUTO_EN to 0 disables free run mode If the decoder is unlocked it outputs noise Setting DEF_VAL_EN to 1 default enables free run mode A colored screen set by the user programmable Y Cr and Cb values is displayed when the decoder loses lock CLAMP OPERATION The input video is ac coupled into the ADV7183B through a 0 1 capacitor The recommended range of the input video signal is 0 5 V to 1 6 V typically 1 V p p If the signal exceeds this range it cannot be processed correctly in the decoder Since the input signal is ac co
100. e 36 LG LMG Function LG 11 0 LMG 11 0 Read Write Description LMG 11 0 2 X Write Manual gain for luma path LG 11 0 Read Actually used gain 0 lt 1 lt 4095 _ 0 2 1 2048 Rev 31 of 100 ADV7183B For example program the ADV7183B into manual fixed gain mode with a desired gain of 0 89 1 Use Equation 1 to convert the gain 0 89 x 2048 1822 72 2 Truncate to integer value 1822 72 1822 3 Convert to hexadecimal 18224 0x71E 4 Split into two registers and program Luma Gain Control 1 3 0 0x7 Luma Gain Control 2 7 0 Ox1E 5 Enable manual fixed gain mode Set LAGC 2 0 to 000 BETACAM Enable Betacam Levels Address 0 01 5 If YPrPb data is routed through the ADV7183B the automatic gain control modes can target different video input levels as outlined in Figure 40 The BETACAM bit is valid only if the input mode is YPrPb component The BETACAM bit sets the target value for AGC operation A review of the following sections is useful INSEL 3 0 Input Selection Address 0x00 3 0 to find how component video YPrPb can be routed through the ADV7183B e Video Standard Selection to select the various standards such as those with and without pedestal The automatic gain control AGC algorithms adjust the levels based on the setting of the BETACAM bit see Table 37 Table 37 BETACAM Function PW Peak White Update Address 0x2B
101. e ADV7183B does not issue an acknowledge and returns to the idle condition If the user exceeds the highest subaddress in auto increment mode the following occurs e Inread mode the highest subaddress register contents continue to be output until the master device issues a no acknowledge This indicates the end of a read A no acknowledge condition is where the SDA line is not pulled low on the ninth pulse In write mode the data for the invalid byte is not loaded into any subaddress register a no acknowledge is issued by the ADV7183B and the part returns to the idle condition 9 1 7 8 9 04997 039 Figure 39 Bus Data Transfer WRIT s SLAVE soon ADR AS LSB 0 e OF LSB 1 i 80 S 8 AGI sus ADDR us stve anon ae oara aww aon S START A S ACKNOWLEDGE BY SLAVE P STOP BIT A M ACKNOWLEDGE BY MASTER A S NO ACKNOWLEDGE BY SLAVE A M NO ACKNOWLEDGE BY MASTER 04997 040 Figure 40 Read and Write Sequence Rev B Page 60 of 100 REGISTER ACCESSES The MPU can write to or read from most of the ADV7183B s registers except the registers that are read only or write only The subaddress register determines which register the next read or write operation accesses All communications with the part through the bus start with an access to the subaddress register Next a read write operation is performe
102. early Y samples S Video mode Nodelay CTAI2 0 101b 1 010 Chroma 1 pixel late 11011 Chroma 2 pixels late YPrPb mode 1 1 0 Chroma 3 pixels late CTA 2 0 110b Not valid setting AUTO PDC EN Automatically 0 Use values in LTA 1 0 and programs the LTA CTA values so CTA 2 0 for delaying that luma and chroma are aligned at luma chroma the output for all modes of 1 LTA and CTA values operation determined automatically SWPC Allows the Cr and Cb samples 0 No swapping to be swapped 1 Swap the Cr and Cb O P samples Ox2B Misc Gain PW UPD Peak white update Update once per video Peak white must be Control determines the rate of gain line enabled See LAGC 2 0 Update once per field Luma Automatic Gain Control Address 0x2C 7 0 Reserved 11010 default Color kill enable allows the 0 Color kill disabled For SECAM color kill color kill function to be switched on 1 Color kill enabled threshold is set at 8 and off See CKILLTHR 2 0 Reserved 1 Set to default 0 2 Mode 1 0 automatic gain Manual fixed gain Use CMG 1 1 0 Control control selects the basic mode of Use luma gain for operation for the AGC in the chroma chroma th pa Automatic gain Based on color burst Freeze chroma gain Reserved 1 Setto 1 LAGC 2 0 Luma automatic gain o 00 Manual fixed gain Use LMG 11 0 control selects the mode of 0 0 1 Peak white Blank level to
103. ed Page 2 SD FR CHNG MSKB Masks SD FR CHNG Q bit Unmasks SD FR CHNG Q bit MV PS CS MSKB Masks MV PS CS Q bit Unmasks MV PS CS Q bit Reserved Not used 0x45 Reserved x 0x46 Interrupt CCAPD_Q Closed captioning not detectedin These bits Status 2 the input video signal can be Closed captioning data detected cleared or Read Only in the video input signal masked by Register GEMD_Q Gemstar data not detected in the input video signal 0 48 Register Gemstar data detected in the respectively Access input video signal Page 2 CGMS CHNGD Q No change detected in CGMS data in the input video signal A change is detected in the CGMS data in the input video signal WSS CHNGD Q 0 No change detected in WSS data in the input video signal A change is detected in the WSS data in the input video signal Reserved Not used Reserved Not used Reserved Not used MPU STIM INTRO Manual interrupt not set Manual interrupt set 0x47 Interrupt CCAPD_CLR Do not clear Clear 2 Clears CCAPD_Q bit GEMD_CLR Do not clear Write Only Clears bit CGMS CHNGD CLR Do not clear Register Clears CGMS_CHNGD_Q bit Access WSS CHNGD CLR 0 Do not clear age 2 Clears WSS CHNGD bit Reserved Not used Reserved Not used Reserved Not used MPU STIM INTRO CLR Do not clear Clears MPU_STIM_INTRQ_Q bit Rev B Page 68 of 100 ADV7183B
104. emstar Decode Ancillary Data Format Address 0x4C 0 section The data packet formats are Address 0x4C 0 section shown in Table 72 and Table 73 Table 72 and Table 73 list the bytes of the data packet Only closed caption data can be embedded in the output ita Only closed caption data can be embedded in the output data stream PAL closed caption data is sliced from Line 22 and NTSC closed caption data is sliced on Line 21d on even and Line 335 The corresponding enable bits have to be set odd fields The corresponding enable bit has to be set high See the and the GDECOL 15 0 Gemstar Decoding Odd Lines See the GDECAD Gemstar Decode Ancillary Data For mat Address 0x4A 7 0 Address 0x4B 7 0 sections Address 0 4 0 and GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 sections Table 72 PAL CCAP Data Half Byte Mode Byte 0191 0181 DI7 0161 0151 DI4 0121 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 IEP EP EF 0 1 0 1 0 0 0 SDID 5 0 0 0 0 0 1 0 0 Data count 6 0 0 CCAP 7 4 0 0 User data words 7 0 0 CCAP Word1 3 0 0 0 User data words 8 0 0 CCAP Word2 7 4 0 0 User data wo
105. eo signals is performed downstream by digital fine clamping within the ADV7183B The ADCs are configured to run in 4x oversampling mode STANDARD DEFINITION PROCESSOR SDP The ADV7183B is capable of decoding a large selection of baseband video signals in composite S Video and component formats The video standards supported include PAL B D I G H PAL60 PAL M PALN PAL Nc NTSC M J NTSC 4 43 and SECAM B D G K L The ADV7183B can automatically detect the video standard and process it accordingly ADV7183B has a 5 line superadaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required Video user controls such as brightness contrast saturation and hue are also available within the ADV7183B The ADV7183B implements a patented adaptive digital line length tracking ADLLT algorithm to track varying video line lengths from sources ADLLT enables the ADV7183B to track and decode poor quality video sources such as VCRs noisy sources from tuner outputs VCD players and camcorders The ADV7183B contains a chroma transient improvement processor that sharpens the edge rate of chroma transitions resulting in sharper vertical transitions The ADV7183B can process a variety of VBI data services such as closed capti
106. essfully be combed as well as for luma components of YPrPb and Y C sources since they need not be combed For poor quality signals the system selects from a set of proprietary shaping filter responses that complements comb filter operation to reduce visual artifacts The decisions of the control logic are shown in Figure 11 YSFM 4 0 Y Shaping Filter Mode Address 0x17 4 0 The Y shaping filter mode bits allow the user to select from a wide range of low pass and notch filters When switched in automatic mode the filter is selected based on other register selections for example detected video standard as well as properties extracted from the incoming video itself for example quality time base stability The automatic selection always selects the widest possible bandwidth for the video input encountered If the YSFM settings specify a filter where YSFM is set to values other than 00000 or 00001 the chosen filter is applied to all video regardless of its quality In automatic selection mode the notch filters are used only for bad quality video signals For all other video signals wideband filters are used WYSFMOVR Wideband Y Shaping Filter Override Address 0x18 7 Setting the WYSFMOVR bit enables the use of the WYSFM 4 0 settings for good quality video signals For more information refer to the general discussion of the luma shaping filters in the Y Shaping Filter section and the flowchart shown in Figure 11 W
107. faults e CVBS input CTA 2 0 011 e Y C input CTA 2 0 101 YPrPb input CTA 2 0 110 Table 54 CTA Function CTA 2 0 Description 000 Not used 001 Chroma 2 chroma pixel early 010 Chroma 1 chroma pixel early 011 default No delay 100 Chroma 1 chroma pixel late 101 Chroma 2 chroma pixel late 110 Chroma 3 chroma pixel late 111 Not used Rev B Page 38 of 100 ADV7183B SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only Beginning of HS signal via HSB 10 0 End of HS signal via HSE 10 0 e Polarity of HS using PHS The HS begin and HS end registers allow the user to freely position the HS output pin within the video line The values in HSB 10 0 and HSE 10 0 are measured in pixel units from the falling edge of HS Using both values the user can program both the position and length of the HS output signal HSB 10 0 HS Begin Address 0x34 6 4 Address 0 35 7 0 The position of this edge is controlled binary number into HSB 10 0 The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FE 00 00 XY see Figure 20 HSB is set to 00000000010b which is 2 LLC1 clock cycles from Count 0 The default value of HSB 10 0 is 0x002 indicating the HS pulse starts two pixels after the falling edge of HS Table
108. fed with the CVBS input SD LUMA PATH The input signal is processed by the following blocks e Digital Fine Clamp This block uses a high precision algorithm to clamp the video signal Luma Filter Block This block contains luma decimation filter YAA with a fixed response and some shaping filters YSH that have selectable responses e Luma Gain Control The automatic gain control AGC can operate on a variety of different modes including gain based on the depth of the horizontal sync pulse peak white mode and fixed manual gain Luma Resample To correct for line length errors as well as dynamic line length changes the data is digitally resampled e Luma2D Comb The two dimensional comb filter provides Y C separation Code Insertion At this point the decoded luma Y signal is merged with the retrieved chroma values AV codes as per ITU R BT 656 can be inserted SD CHROMA PATH The input signal is processed by the following blocks e Digital Fine Clamp This block uses a high precision algorithm to clamp the video signal e Chroma Demodulation This block uses a color subcarrier Fsc recovery unit to regenerate the color subcarrier for any modulated chroma scheme The demodulation block then performs an AM demodulation for PAL and NTSC and an FM demodulation for SECAM Chroma Filter Block This block contains a chroma decimation filter with a fixed response and some shaping filter
109. from the luma into the interleaved data output chroma path AV codes duplicated for 16 bit interfaces Reserved Set as default OF_SEL 3 0 Allows the user to 01010 10 Reserved choose from a set of output formats ololol1 Reserved 0101 0 16 bit LLC1 4 2 2 0 0 1 1 8 bit LLC1 4 2 2 ITU R BT 656 0 ot used 0 1 0 1 ot used Not used 01111 1 Not used 11010 Not used 110 011 Not used 110110 Not used 11011 1 Not used 11110 Not used 111 011 Not used 1111110 ot used 11111 1 Not used TOD Three State Output Drivers 0 Output pins enabled See TIM_OE Address This bit allows the user to three 0x04 3 and state the output drivers P 19 0 HS Introduction VS FIELD and SFL 1 Drivers three stated VBI_EN Allows VBI data Lines 1 to 0 All lines filtered 21 to be passed through with only a scaled minimum amount of filtering 1 Only active video region performed filtered 0x04 Extended RANGE Allows the user to select the 16 lt Y lt 235 ITU R BT 656 Output range of output values Can be 16 lt C lt 240 Control BT656 compliant or can fill the 1 lt lt 254 1 lt lt 254 Extended range whole accessible number range SFL PIN SFL output is disabled SFL output enables SFL information output encoder and decoder on the SFL pin to be connected directly BL C VBI Blank Chroma during VBI 0 Decode and output color During VBI If set enables data in the VBI region 1 Blank Cr a
110. ge transitions only The default value for TH 7 0 is 0x08 indicating threshold for the chroma edges prior to CTI DIGITAL NOISE REDUCTION DNR Digital noise reduction is based on the assumption that high frequency signals with low amplitude are probably noise and that their removal therefore improves picture quality DNR EN Digital Noise Reduction Enable Address Ox4D 5 The DNR EN bit enables or bypasses the DNR block Setting DNR EN to 0 bypasses DNR disables it Setting DNR EN to 1 default enables digital noise reduction on the luma data DNR TH 7 0 DNR Noise Threshold Address 0x50 7 0 The DNR TH 7 0 value is an unsigned 8 bit number used to determine the maximum edge to be interpreted as noise and therefore blanked from the luma data Programming a large value into DNR TH 7 0 causes the DNR block to interpret even large transients as noise and remove them The effect on the video data is therefore more visible Programming a small value causes only small transients to be seen as noise and to be removed The recommended DNR TH 7 0 setting for A V inputs is 0x04 and the recommended DNR TH 7 0 setting for tuner inputs is The default value for DNR TH 7 0 is 0x08 indicating the threshold for maximum luma edges to be interpreted as noise Rev B Page 34 of 100 ADV7183B COMB FILTERS Table 44 NSFSEL Function The comb filters of the ADV7183B have been gre
111. gitized input video If desired the blocks can be disabled via the following two bits ENHSPLL Enable Hsync Processor Address 0 01 6 Hsync processor is designed to filter incoming Hsyncs that have been corrupted by noise providing improved performance for video signals with stable time bases but poor SNR Setting ENHSPLL to 0 disables the Hsync processor Setting ENHSPLL to 1 default enables the Hsync processor ENVSPROC Enable Vsync Processor Address 0 01 3 This block provides extra filtering of the detected Vsyncs to give improved vertical lock Setting ENVSPROC to 0 disables the Vsync processor Setting ENVSPROC to 1 default enables the Vsync processor Page 46 of 100 ADV7183B VBI DATA DECODE The following low data rate VBI signals can be decoded by the ADV7183B e Wide screen signaling WSS generation management systems CGMS e Closed captioning CCAP EDTV Gemstar 1x and 2x compatible data recovery The presence of any of the above signals is detected and if applicable a parity check is performed The result of this testing is contained in a confidence bit in the VBI Info 7 0 register Users are encouraged to first examine the VBI Info register before reading the corresponding data registers All VBI data decode bits are read only All VBI data registers are double buffered with the field signals This means that data is extracted from the video lines
112. gramming Setting PVBEGSIGN to 1 default advances the beginning of Vsync Not recommended for user programming PVBEG 4 0 PAL Vsync Begin Address 0 8 4 0 The default value of PVBEG is 00101 indicating the PAL Vsync begin position For all NTSC PAL Vsync timing controls both the V bit in the AV code and the Vsync on the VS pin are modified DELAY END OF VSYNC BY PVEND 4 0 ADVANCE END OF VSYNC BY PVEND 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO 0 0 1 ADDITIONAL DELAY BY 1 0 0 1 ADVANCE BY ADVANCE BY 0 5 LINE 0 5 LINE 04997 029 VSYNC END Figure 29 PAL Vsync End PVENDDELO PAL Vsync End Delay on Odd Field Address OxE9 7 When PVENDDELO is 0 default there is no delay Setting PVENDDELO to 1 delays Vsync going low on an odd field by a line relative to PVEND PVENDDELE PAL Vsync End Delay on Even Field Address OxE9 6 When PVENDDELE is 0 default there is no delay Setting PVENDDELE to 1 delays Vsync going low on an even field by a line relative to PVEND Rev B Page 45 of 100 ADV7183B PVENDSIGN PAL Vsync End Sign Address 0xE9 5 Setting PVENDSIGN to 0 default delays the end of Vsync Set for user manual programming Setting PVENDSIGN to 1 advances the end of Vsync Not recommended for user programming 4 0 PAL Vsync End Address 0xE9 4 0 The default value of PVEND is 10100 indicating the PAL end position
113. he Register value for the color hue adjustment 90 to 90 OxOC Default DEF VAL EN Default value enable Free run mode Value Y dependent on DEF VAL AUTO EN Force free run mode on and output blue screen DEF VAL AUTO EN Default value Disable free run mode When lock is lost free Enable automatic free run mode can be run mode blue screen enabled to output stable timing clock and a set color DEF YI5 01 Default value Y This Ba Y 7 0 DEF Y 5 0 0 0 Default Y value output register holds the Y default value in free run mode Default DEF C 7 0 Default value C The Cr 0 1 Cr 7 0 DEF_C 7 4 0 0 Default Cb Cr value Value C and Cb default values are defined in 0 0 output in free run this register Cb 7 0 DEF_C 3 0 0 0 mode Default values 0 0 give blue screen output ADI Reserved 0 0 Set as default Control SUB_USR_EN Enables the user to access the interrupt map Access user reg map Access interrupt reg map See Figure 38 Reserved Set as default Rev B Page 73 of 100 ADV7183B Bits Subaddress Register Bit Description 7161543 Comments Notes Reserved Set to default Management PDBP Power down bit priority Chip power down selec
114. hen WYSFMOVR is 0 the shaping filter for good quality video signals is selected automatically Setting WYSFMOVR to 1 enables manual override via WYSFM 4 0 default Rev B Page 27 of 100 ADV7183B SET YSFM YSFM IN AUTO MODE 00000 OR 00001 NO QUALITY BAD GOOD USE YSFM SELECTED FILTER REGARDLESS FOR GOOD AND BAD VIDEO AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB SELECT WIDEBAND FILTER AS PER SELECT AUTOMATIC WIDEBAND FILTER 04997 011 WYSFM 4 0 Figure 11 YSFM and WYSFM Control Flowchart Table 30 YSFM Function WYSFM 4 0 Wideband Y Shaping Filter Mode 5 4 01 Description Address 0 1814 0 0 0000 Automatic selection including a wide notch response PAL NTSC SECAM The WYSFM 4 0 bits allow the user to manually select a shaping 0 0001 default Automatic selection including a narrow notch filter for good quality video signals for example CVBS with response PAL NTSC SECAM time base stability luma component of YPrPb and luma 0 0010 SVHS 1 component of Y C The WYSFM bits are active only if the 0 0011 SVHS 2 WYSFMOVR bit is set to 1 See the general discussion of the 0 0100 SVHS 3 shaping filter settings in the Y Shaping Filter section 00101 SVHS 4 Table 31 WYSFM Function 0010 SVHS 5 WYSFM A 0 Description 90111 AMRS 0 0000 Do not use 0 1000 SVHS 7 0 0001 Do not use 0 1001 SVHS 8 0 0010 SVHS 1 0100 00011 SVHS 2 01011 SVHS 10 0 01
115. iled in Table 84 Rev B Page 58 of 100 ADV7183B PIXEL PORT CONFIGURATION The ADV7183B has a very flexible pixel port that can be confi gured in a variety of formats to accommodate downstream ICs Table 79 and Table 80 summarize the various functions that the ADV7183B s pins can have in different modes of operation The ordering of components for example Cr versus Cb CHA B C can be changed Refer to the section Table 79 indicates the default positions for the Cr Cb components OF_SEL 3 0 Output Format Selection Address 0 03 5 2 The modes in which the ADV7183B pixel port can be onfigured are under the control of OF_SEL 3 0 See Table 80 for details The default LLC frequency output on the LLCI pin is approximately 27 MHz For modes that operate with a nominal data rate of 13 5 MHz 0001 0010 the clock frequency on the LLCI pin stays at the higher rate of 27 MHz For information on outputting the nominal 13 5 MHz clock on the LLCI pin see the PAD_SEL 2 0 Address 0x8F 6 4 section Table 79 P15 to PO Output Input Pin Mapping SWPC Swap Pixel Cr Cb Address 0x27 7 This bit allows Cr and Cb samples to be swapped When SWPC is 0 default no swapping is allowed When SWPC is 1 the Cr and Cb values can be swapped PAD_SEL 2 0 Address 0x8F 6 4 This write allows the user to select between the LLC1 nominally at 27 MHz and LLC2 nominally at 13 5 MHz The LLC2 signal is useful for LLC2 compatible wi
116. ins 1 2 5 6 8 12 17 18 to 24 32 to 35 74 to 76 80 5 Guaranteed by characterization 5 ADC1 powered on 7 All three ADCs powered on Rev B Page 6 of 100 ADV7183B VIDEO SPECIFICATIONS At 3 15 V to 3 45 V 1 65 V to 2 0 V 3 0 V to 3 6 V 1 65 V to 2 0 V operating temperature range unless otherwise specified Table 2 Parameter Symbol Test Conditions Min Typ Max Unit NONLINEAR SPECIFICATIONS Differential Phase DP CVBS modulate 5 step 0 5 0 7 Degrees Differential Gain DG CVBS modulate 5 step 0 5 0 7 96 Luma Nonlinearity LNL CVBS 5 step 0 5 0 7 96 NOISE SPECIFICATIONS SNR Unweighted Luma ramp 54 56 dB Luma flat field 58 60 dB Analog Front End Crosstalk 60 dB LOCK TIME SPECIFICATIONS Horizontal Lock Range 5 5 Vertical Lock Range 40 70 Hz Fsc Subcarrier Lock Range 1 3 2 Color Lock In Time 60 Lines Sync Depth Range 20 200 Color Burst Range 5 200 Vertical Lock Time 2 Fields Autodetection Switch Speed 100 Lines CHROMA SPECIFICATIONS Hue Accuracy HUE 1 Degrees Color Saturation Accuracy CL 1 Color AGC Range 5 400 90 Chroma Amplitude Error 0 5 Chroma Phase Error 0 4 Degrees Chroma Luma Intermodulation 0 2 LUMA SPECIFICATIONS Luma Brightness Accuracy CVBS 1 V 1 96 Luma Contrast Accuracy CVBS 1 V 1 96 1 Temperature range Tmn to Tmax 40 C to 85 C 0 C to 70 C for ADV7183BKSTZ 2 The
117. lementing this buffer and filter circuit for all analog input signals is shown in Figure 45 The buffer is a simple emitter follower using a single npn transistor The antialiasing filter is implemented using passive components The passive filter is a third order Butterworth filter with a 3 dB point of 9 MHz The frequency response of the passive filter is shown in Figure 43 The flat pass band up to 6 MHz is essential The attenuation of the signal at the output of the filter due to the voltage divider of R24 and R63 is compensated for in the ADV7183B part by using the automatic gain control The ac coupling capacitor at the input to the buffer creates a high pass filter with the biasing resistors for the transistor This filter has a cutoff of 2 x n x R39 R89 x C93 0 62 Hz It is essential that the cutoff of this filter be less than 1 Hz to ensure correct operation of the internal clamps within the part These clamps ensure the video stays within the 5 V range of the op amp used 0 20 40 80 100 120 100k 300k 1M 3M 10M 30M 100M 300M 1G FREQUENCY Hz Figure 43 Third Order Butterworth Filter Response 04997 043 ADV7183B CRYSTAL LOAD CAPACITOR VALUE SELECTION Figure 44 shows an example of a reference clock circuit for the ADV7183B Special care must be taken when using a crystal circuit to generate the reference clock for the ADV7183B Small variations in
118. ll lock status is determined and presented via Bits 1 0 in Status COLOR CONTROLS Register 1 This bit must be set to 0 when operating in YPrPb component mode to generate a reliable HLOCK status bit Setting FSCLE to 0 default makes the overall lock status dependent on only horizontal sync lock Setting FSCLE to 1 makes the overall lock status dependent on horizontal sync lock and Fsc lock VS_Coast 1 0 Address 0xF9 3 2 These bits are used to set VS free run coast frequency These registers allow the user to control the picture appearance including control of the active data in the event of video being lost These controls are independent of any other controls For instance brightness control is independent from picture clamp ing although both controls affect the signal s dc level CON 7 0 Contrast Adjust Address 0 08 7 0 This allows the user to adjust the contrast of the picture Table 22 CON Function CON 7 0 Description Table 19 VS COASTT 1 0 Function 0x80 default Gain on luma channel 1 VS COAST 1 0 Description 0x00 Gain on luma channel 0 00 default Auto coast mode follows VS Gain luma channel 2 frequency from last video input 01 Forces 50 Hz coast mode 10 Forces 60 Hz coast mode SD SAT Cb 7 0 SD Saturation Cb Channel 11 Reserved Address 0 7 0 CIL 2 0 Count Into Lock Address 0x51 2 0 CIL 2 0 determines the number of consecutive lines for whi
119. lue Notes 0x00 0x04 CVBS input on AIN5 0x15 0x00 Slow down digital clamps 0x17 0x41 Set CSFM to SH1 0 16 Power down 1 2 0 50 0 04 Set DNR threshold to 4 for flat response 0 80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0 50 0 20 Recommended setting 0 52 0 18 Recommended setting 0 58 OxED Recommended setting 0 77 OxC5 Recommended setting Ox7C 0 93 Recommended setting 0 70 0 00 Recommended setting 0 48 Recommended setting OxD5 Recommended setting OxD7 Recommended setting OxE4 Ox3E Recommended setting 9 Recommended setting Recommended setting OxOE 0 00 Recommended setting Mode 2 S Video Input AIN1 AIN4 All standards are supported through autodetect 8 bit ITU R BT 656 output on P15 to P8 Table 92 Mode 2 S Video Input Register Address Register Value Notes 0 00 0 06 Y1 0 15 0 00 Slow down digital clamps 0 12 Power down ADC 2 0 50 0 04 Set DNR threshold to 4 for flat response OxOE 0 80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0 50 0 20 Recommended setting 0 52 0 18 Recommended setting 0 58 OxED Recommended setting 0 77 OxC5 Recommended setting Ox7C 0 93 Recommen
120. min max specifications are guaranteed over this range Rev B Page 7 of 100 ADV7183B TIMING SPECIFICATIONS Guaranteed by characterization At Avpp 3 15 V to 3 45 V 1 65 V to 2 0 V Dvppio 3 0 V to 3 6 V 1 65 V to 2 0 V operating temperature range unless otherwise specified Table 3 Parameter Symbol Test Conditions Min Typ Max Unit SYSTEM CLOCK AND CRYSTAL Nominal Frequency 28 6363 MHz Frequency Stability 50 lC PORT SCLK Frequency 400 kHz SCLK Min Pulse Width High ti 0 6 us SCLK Min Pulse Width Low t2 1 3 us Hold Time Start Condition 0 6 us Setup Time Start Condition ta 0 6 us SDA Setup Time 5 100 ns SCLK and SDA Rise Time 16 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition ts 0 6 us RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC1 Mark Space Ratio to t10 45 55 55 45 duty cycle LLC1 Rising to LLC2 Rising th 0 5 ns LLC1 Rising to LLC2 Falling 12 0 5 ns DATA AND CONTROL OUTPUTS Data Output Transitional Time tis Negative clock edge to start of 3 4 ns valid data taccess tio 113 Data Output Transitional Time ta End of valid data to negative clock 2 4 ns edge to t14 Propagation Delay to Hi Z tis 6 ns Max Output Enable Access Time te 7 ns Min Output Enable Access Time t 4 ns 1 Temperature range Tmn to Tmax 40 C to 85 C 0 C to 70 C for ADV7183BKSTZ 2 The min max specifications are guaranteed
121. nce filters SH1 to SH5 and wideband mode Auto selection 1 5 MHz Auto selection 2 17 MHz Automatically selects a C filter for the specified bandwidth SH1 SH2 SH3 SH4 5 5 lolo Wideband mode Rev B Page 75 of 100 ADV7183B Bits Subaddress Register Bit Description 716 154 3 2 1 0 Comments Notes 0 18 Shaping WYSFM 4 0 Wideband Y shaping 0 0 0 0 0 Reserved Do not use Filter filter mode allows the user to select olo 1 Reserved Do not use II 21277911 input signals it is also used when 0 0 0 14 1 SVHS2 good quality input CVBS signal is SVHS3 detected For all other inputs the 1 1 SVHS4 shaping filter chosen is controlled by 5 4 01 1 1 0 5 5 5 1 11 1 SVHS6 0 1 0 O O SVHS7 0 1 010 1 5 5 8 0 1 0 1 0 SVHS9 0 1 O 1 1 SVHS 10 011 110 0 SVHS 11 011 110 1 SVHS 12 011 1 1 0 SVHS 13 0 1 1 1 1 SVHS 14 110101010 SVHS 15 1101001 SVHS16 11010110 SVHS 17 110101111 SVHS 18 CCIR 601 110 1 0 0 Reserved Do not use Reserved Do not use 111 1 1 1 Reserved Do not use Reserved 010 Set to default WYSFMOVR
122. nd Cb to be passed through the decoder undistorted TIM OE Timing signals output 0 HS VS F three stated Controlled by TOD enable 1 HS VS F forced active Reserved x x Reserved 1 BT656 4 Allows the user to select 0 BT656 3 compatible an output mode compatible with 1 BT656 4 compatible ITU R BT656 3 4 Rev B Page 72 of 100 ADV7183B Bits Subaddress Register Bit Description 7161543 Comments Notes 0 07 Autodetect AD PAL PAL B G I H autodetect Disable Enable enable Enable AD NTSC 5 autodetect Disable enable Enable AD PALM EN PAL M autodetect Disable enable Enable AD PALN PAL N autodetect 0 Disable enable 1 Enable AD P60 EN PAL60 autodetect 0 Disable enable 1 Enable AD N443 EN NTSC443 autodetect 0 Disable enable 1 Enable AD SECAM EN SECAM autodetect 0 Disable enable 1 Enable AD 5 525 EN SECAM 525 0 Disable autodetect enable 1 Enable 0 08 Contrast CON 7 0 Contrast adjust This is the 10 010 0 gain 1 0 00 0 Register user control for contrast adjustment 0 80 Gain 1 OxFF Gain 2 0 09 Reserved Reserved 010 01 0 Ox0A Brightness BRI 7 0 This register controls the 0101000 0x00 OIRE Register brightness of the video signal Ox7F 100IRE 0x80 100IRE OxOB Hue HUE 7 0 This register contains t
123. nes of memory Fixed luma comb 5 line All lines of memory Fixed luma comb 3 line Bottom lines of memory CCMP 2 0 Chroma Comb mode PAL 3 line adaptive for CTAPSN 01 4 line adaptive for CTAPSN 10 5 line adaptive for CTAPSN 11 Disable chroma comb Fixed 2 line for CTAPSN 01 Top lines of memory Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 Fixed 3 line for CTAPSN 01 All lines of memory Fixed 4 line for CTAPSN 10 Fixed 5 line for CTAPSN 11 Fixed 2 line for CTAPSN 01 Bottom lines of memory Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 CTAPSP 1 0 Chroma comb taps PAL Not used Adapts 5 lines 3 lines 2 taps Adapts 5 lines 3 lines 3 taps Adapts 5 lines 4 lines 4 taps Ox3A Reserved Set as default PWRDN ADC 2 Enables power down of ADC2 ADC2 normal operation Power down ADC2 PWRDN ADC 1 Enables power down of ADC1 normal operation Power down PWRDN ADC 0 Enables power down of ADCO ADCO normal operation Power down ADCO Reserved Set as default 0x3D Manual Window Control Reserved Set to default CKILLTHR 2 0 Kill at 0 5 Kill at 1 5 Kill at 2 5 Kill at 4
124. ng NVBEGDELE Delay V bit going 0 No delay high by one line relative to NVBEG 1 Additional delay by 1 even field line NVBEGDELO Delay V bit going 0 No delay high by one line relative NVBEG 1 Additional delay by 1 odd field line OxE6 NTSC V NVEND 4 0 Number of lines after 010 1 0 0 NTSC default BT 656 Bit End Icount rollover to set V low NVENDSIGN 0 Set to low when manual programming 1 Not suitable for user programming NVENDDELE Delay V bit going 0 low one line relative 1 Additional delay by 1 even field line NVENDDELO Delay V bit going 0 No delay low by one line relative to NVEND 1 Additional delay by 1 odd field line Rev B Page 85 of 100 ADV7183B Bits Subaddress Register Bit Description 4 3 Comments Notes OxE7 NTSC F Bit NFTOG 4 0 Number of lines after 0 0 NTSC default Toggle rollover to toggle signal NFTOGSIGN Set to low when manual programming Not suitable for user programming NFTOGDELE Delay F transition by No delay one line relative to NFTOG even Additional delay by 1 field line NFTOGDELO Delay F transition by No delay one line relative to NFTOG odd Additional delay by 1 field line OxE8 PAL V Bit PVBEG 4 0 Number of lines after 0 0 PAL default BT 656 Begin Icount rollover to se
125. nmasks SD V LOCK CHNG Q Register bit SD H LOCK MSKB Masks SD H LOCK CHNG Q bit Register Unmasks SD_H_LOCK_CHNG_Q Access bit Page 2 2 SD AD CHNG 5 0 Masks SD AD CHNG bit 1 Unmasks SD AD CHNG Q bit SCM LOCK CHNG MSKB 0 Masks SCM LOCK CHNG Q bit 1 Unmasks SCM LOCK CHNG bit PAL SW LK CHNG MSKB 0 Masks PAL SW LK CHNG bit 1 Unmasks PAL SW LK CHNG Q bit Reserved x Not used Reserved Not used Rev B Page 70 of 100 The following registers are located in the Common and Register Access Page 1 Table 86 Interrupt Register Map Details ADV7183B Subaddress Register Bit Description Bits 7615 4 Comments Notes 0 00 Input Control INSEL 3 0 The INSEL bits allow the user to select an input channel as well as the input format CVBS in on AIN1 CVBS in on AIN2 CVBS in on AIN3 CVBS in on AIN4 CVBS in on AINS CVBS in on AIN6 Composite Y on AIN1 C on AIN4 Y AIN2 5 Y on AIN3 C on AIN6 S Video o Y on AINT Pr on Pb on 5 o Y on AIN2 Pr on AIN3 Pb on AING YPbPr CVBS in on AIN7 CVBS in on AIN8 CVBS in on AIN9 CVBS in on AIN10
126. no bearing on PAL When BT656 4 is 0 default the BT656 3 specification is used The V bit goes low at EAV of Line 10 and Line 273 When 656 4 is 1 the BT656 4 specification is used The V bit goes low at EAV of Line 20 and Line 283 SD DUP AV 1 16 BIT INTERFACE LS GB RR NUN INTERLEAVED s ICE IER IER CD CR CR CODE SECTION 1 2 AV CODE SECTION 16 BIT INTERFACE AV CODE SECTION SD DUP AV Duplicate AV Codes Address 0 03 0 Depending on the output interface width it can be necessary to duplicate the AV codes from the luma path into the chroma path In an 8 bit wide output interface Cb Y Cr Y interleaved data the AV codes are defined as 00 00 with AV as the transmitted word that contains information about H V E In this output interface mode the following assignment takes place Cb FE Y 00 Cr 00 and Y AV In a 16 bit output interface where Y and Cr Cb are delivered via separate data buses the AV code is over the whole 16 bits The SD DUP AV bit allows the user to replicate the AV codes on both busses so the full AV sequence can be found on the Y bus and on the Cr Cb bus See Figure 19 When SD_DUP_AV is 0 default the AV codes are in single fashion for 8 bit interleaved data output When SD_DUP_AV is 1 the AV codes are duplicated for 16 bit interfaces VBI_EN Vertical Blanking Interval Data Enable Address 0 03 7
127. nses of filters The data format at this point is CVBS for CVBS inputs COMBINED Y ANTIALIAS CCIR MODE SHAPING FILTER RESAMPLE 40 AMPLITUDE dB 5 120 0 2 4 6 8 10 12 MHz Figure 13 S VHS 18 Extra Wideband Filter CCIR 601 Compliant 04997 013 COMBINED Y ANTIALIAS PAL NOTCH FILTERS RESAMPLE chroma only for Y C U V interleaved for YPrPb input formats Chroma Antialias Filter CAA The ADV7183B samples the CVBS by a factor of 2 and the Chroma PrPb by a factor of 4 A decimating filter CAA is used to preserve the active video band and to remove any out of band components The CAA filter has a fixed response Chroma Shaping Filters CSH The shaping filter block CSH can be programmed to perform a variety of low pass responses It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression Digital Resampling Filter This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actual response is 0 chosen by the system without user intervention 10 The plots in Figure 16 show overall response of all filters 20 together a 5 30 gt amp 40 50 60 70 0 2 4 6 8 10 12 04997 014
128. omatic gain Table 39 CAGT Function 1 Assuming YPrPb is selected as input format Selecting PAL with pedestal selects BETACAM Selecting PAL without pedestal selects BETACAM variant Selecting NTSC with pedestal selects BETACAM Selecting NTSC without pedestal selects BETACAM variant CAGT 1 0 Description 00 Slow 2 sec 01 Medium TC 1 sec 10 Fast TC 0 2 sec 11 default Adaptive Table 40 Betacam Levels Name Betacam mV Betacam Variant mV SMPTE mV MII mV Y Range 714 includes 7 596 pedestal 0 to 714 0 to 700 700 includes 7 596 pedestal Pb and Pr Range 467 to 467 505 to 505 350 to 350 324 to 4324 Sync Depth 286 286 300 300 Rev B Page 32 of 100 ADV7183B CG 11 0 Chroma Gain Address 0x2D 3 0 Address Ox2E 7 0 CMG 11 0 Chroma Manual Gain Address 0x2D 3 0 Address Ox2E 7 0 Chroma Gain 11 0 is a dual function register If written to a desired manual chroma gain can be programmed This gain becomes active if the CAGC 1 0 mode is switched to manual fixed gain Refer to Equation 2 for calculating a desired gain If read back this register returns the current gain value Depending on the setting in the CAGC 1 0 bits one of these gain values is returned e Chroma manual gain value 1 0 set to chroma manual gain mode e Chroma automatic gain value CAGC 1 0 set to any of the automatic modes Table 41 CG CMG F
129. on 0x00 default Offset of the luma channel OIRE Ox7F Offset of the luma channel 100IRE OxFF Offset of the luma channel 100IRE DEF Y 5 0 Default Value Y Address 0x0C 7 2 If the ADV7183B loses lock on the incoming video signal or if there is no input signal the DEF Y 5 0 bits allow the user to specify a default luma value to be output This value is used if TheDEF VAL AUTO EN bit is set to high and the ADV7183B lost lock to the input video signal This is the intended mode of operation automatic mode TheDEF VAL EN bit is set regardless of the lock status of the video decoder This is a forced mode that may be useful during configuration The DEF Y 5 0 values define the 6 MSBs of the output video The remaining LSBs are padded with 0s For example in 8 bit mode the output is 7 0 DEF Y 5 0 0 0 DEF Y 5 0 is 0x0D blue is the default value for Y Register 0 0 has a default value of 0x36 DEF C 7 0 Default Value C Address 0x0D 7 0 The DEF C 7 0 register complements the DEF Y 5 0 value It defines the 4 MSBs of Cr and Cb values to be output if TheDEF VAL AUTO EN bit is set to high and the ADV7183B cannot lock to the input video automatic mode TheDEF VAL EN bit is set to high forced output The data that is finally output from the ADV7183B for the chroma side is Cr 7 0 DEF C 7 4 0 0 0 0 Cb 7 0 DEF C 3 0 0 0 0 0 DEF C 7 0 is 0x7C blue is the
130. oning CC wide screen signaling WSS copy generation management system CGMS EDTV Gemstar 1x 2x and extended data service XDS The ADV7183B is fully Macrovision certified detection circuitry enables Type I II and III protection levels to be identified and reported to the user The decoder is also fully robust to all Macrovision signal inputs Rev B Page 4 of 100 ADV7183B 1400 26670 TOHLNOO LNdLNO NOILO313GQOlnV NOILO3 13G quvaNvis NOISIAOHOVIN 7OHINOO 211 IGA 1 G3ZISSHLNAS TOHLNOO 1V8015 AY340934 M OHLNO9 viva AOVAYSLNI 1 5 a1anvsau 1041N09 aowaa oN az 146 VWOHHO NIV VINOHHO VWOHHO VWOYHD 2211 AY340938 5 254 SA 2 SH 2 NOLLH3SNI 5 3009 JOHLNO9 al OR tes gt _ 0010 2 5542 4 ONAS MI Y viva TAS Qe HP Sano vn NIVO vn EINI viva 2 NIV 16 FUNCTIONAL BLOCK DIAGRAM Figure 1 Rev B Page 5 of 100 ADV7183B SPECIFICATIONS ELECTRICAL CHARACTERISTICS At
131. ower supply pin with 0 1 uF and 10 nF capacitors The fundamental idea is to have decoupling capacitor within about 0 5 cm of each power pin Also avoid placing the capacitor on the opposite side of the PC board from the ADV7183B as doing so interposes resistive vias in the path The decoupling capacitors should be located between the power plane and the power pin Current should flow from the power plane to the capacitor to the power pin Do not make the power connection between the capacitor and the power pin Placing a via underneath the 100 nF capacitor pads down to the power plane is generally the best approach see Figure 41 VIA TO SUPPLY VIA TO GND 04997 041 1 Figure 41 Recommended Power Supply Decoupling It is very important to maintain low noise and good stability of PVDD Careful attention must be paid to regulation filtering and decoupling It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups AVDD DVDD DVDDIO and PVDD Some graphic controllers use substantially different levels of power when active during active picture time and when idle during horizontal and vertical sync periods This can result in a measurable change in the voltage supplied to the analog supply regulator which can in turn produce changes in the regulated analog supply voltage This can be mitigated by regulating the analog supply or at least PVDD from a different cleaner powe
132. persists until it is masked or cleared For example if the ADV7183B loses lock an interrupt is Multiple Interrupt Events If Interrupt Event 1 occurs and then Interrupt Event 2 occurs before the system controller has cleared or masked Interrupt Event 1 the ADV7183B will not generate a second interrupt signal The system controller should check all unmasked interrupt status bits as more than one can be active Macrovision Interrupt Selection Bits The user can select between pseudo sync pulse and color stripe detection as shown in this section generated and INTRQ pin goes low If the ADV7183B returns to the locked state INTRQ continues to drive low until the SD LOCK bit is either masked or cleared Interrupt Drive Level The ADV7183B resets with open drain enabled and all interrupts masked off Therefore INTRQ is in a high impedance state after reset 01 or 10 has to be written to INTRQ OP SEL 1 0 for a logic level to be driven out from INTRQ pin It is also possible to write to a register in the ADV7183B that manually asserts the INTRQ pin This bitis MPU STIM INTRQ MV INTRQ SEL 1 0 Macrovision Interrupt Selection Bits Address 0x40 Interrupt Space 5 4 Table 78 MV INTRQ SEL MV INTRQ SEL 1 0 Description 00 01 default 10 11 Reserved Pseudo sync only Color stripe only Either pseudo sync or color stripe Additional information relating to the interrupt system is deta
133. put driver LLC pin For more information refer to the Drive Strength Selection Sync and the Drive Strength Selection Data sections Table 12 DR_STR_C Function DR_STR_C 1 0 Description 00 Low drive strength 1x 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x Drive Strength Selection Sync DR_STR_S 1 0 Address 0xF4 1 0 The DR_STR_S 1 0 bits allow the user to select the strength of the synchronization signals with which HS VS and F are driven For more information refer to the Drive Strength Selection Clock and the Drive Strength Selection Data sections Table 13 DR_STR_S Function DR_STR_S 1 0 Description 00 Low drive strength 1x 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x Enable Subcarrier Frequency Lock Pin EN_SFL_PIN Address 0 04 1 The EN_SFL_PIN bit enables the output of subcarrier lock information also known as GenLock from the ADV7183B to an encoder in a decoder encoder back to back arrangement When EN_SFL_PIN is 0 default the subcarrier frequency lock output is disabled When EN_SFL_PIN is 1 the subcarrier frequency lock infor mation is presented on the SFL pin Polarity LLC Pin PCLK Address 0 37 0 The polarity of the clock that leaves the ADV7183B via the LLCI and LLC2 pins can be inverted using the PCLK bit Changing the pol
134. r depending on the CVBS video source quality good vs bad Auto wide notch for poor quality sources or wide band filter with comb for good quality input Auto narrow notch for poor quality sources or wideband filter with comb for good quality input Decoder selects optimum Y shaping filter depending on CVBS quality SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 CCIR601 PAL NN1 PAL NN2 PAL NN3 PAL WN 1 PAL WN 2 NTSC NTSC NN2 NTSC NN3 NTSC WN1 NTSC WN2 NTSC WN3 lolololololololololololololo s olololololololo lolololololo ol o o lolo lolo lolo o lo olo lolo Ol Reserved If one of these modes is selected the decoder does not change filter modes Depending on video quality a fixed filter response the one selected is used for good and bad quality video 2 0 C Shaping Filter mode allows the selection from a range of low pass chromina
135. r CTAPSP 11 YCMP 2 0 Luma Comb Mode PAL Address 0x39 2 0 Table 51 YCMP Function YCMP 2 0 Description Configuration Oxx default Adaptive comb mode Adaptive 5 lines 3 taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb top lines of line memory Fixed 3 lines 2 taps luma comb 110 Fixed luma comb all lines of line memory Fixed 5 lines 3 taps luma comb 111 Fixed luma comb bottom lines of line memory Fixed 3 lines 2 taps luma comb Rev B Page 36 of 100 ADV7183B AV CODE INSERTION AND CONTROLS This section describes based controls that affect e Insertion of AV codes into the data stream e Data blanking during the vertical blank interval VBI e The range of data values permitted in the output data stream e The relative delay of vs chroma signals Some of the decoded VBI data is inserted during the horizontal blanking interval See the Gemstar Data Recovery section for more information BT656 4 ITU Standard BT R 656 4 Enable Address 0x04 7 The ITU has changed the position for toggling of the V bit within the SAV EAV codes for NTSC between revisions 3 and 4 The BT656 4 standard bit allows the user to select an output mode that is compliant with either the previous or the new standard For more information review the standard at www itu int Note that the standard change affects NTSC only and has
136. r source such as a 12 V supply It is also recommended to use a single ground plane for the entire board This ground plane should have a space between the analog and digital sections of the PCB see Figure 42 ADV7183B ANALOG DIGITAL SECTION SECTION Figure 42 PCB Ground Layout 04997 042 Experience shows that the noise performance is the same or better with a single ground plane Using multiple ground planes can be detrimental because each separate ground plane is smaller and long ground loops can result In some cases using separate ground planes is unavoidable For those cases it is recommended to place a single ground plane under the ADV7183B The location of the split should be under the ADV7183B For this case it is even more important to place components wisely because the current loops will be much longer current takes the path of least resistance An example of a current loop power plane to ADV7183B to digital output trace to digital data receiver to digital ground plane to analog ground plane PLL Place the PLL loop filter components as close as possible to the ELPF pin Do not place any digital or other high frequency traces near these components Use the values suggested in Figure 46 with tolerances of 10 or less DIGITAL OUTPUTS BOTH DATA AND CLOCKS Try to minimize the trace length the digital outputs have to drive Longer traces have higher capacitance which requires more current which causes more
137. rds 9 0 0 CCAP Word2 3 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 73 PAL CCAP Data Full Byte Mode Byte DI9 DI8 DI7 0161 0151 0141 0131 0121 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 0 1 0 1 0 0 0 500 5 0 0 0 0 0 1 0 0 Data count 6 CCAP Word1 7 0 0 0 User data words 7 CCAP Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5 0 Checksum Rev B Page 55 of 100 ADV7183B GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 The 16 bits of the GDECEL 15 0 are interpreted as a collection of 16 individual line decode enable signals Each bit refers to a line of video in an even field Setting the bit enables the decoder block trying to find Gemstar or closed caption compatible data on that particular line Setting the bit to 0 prevents the decoder from trying to retrieve data See Table 74 and Table 75 To retrieve closed caption data services on NTSC Line 284 GDECEL 11 must be set To retrieve closed caption data services on PAL Line 335 GDECEL 14 must be set The default value of GDECEL 15 0 is 0x0000 This setting in
138. reference clock frequency can cause autodetection issues and impair the ADV7183B performance Load capacitor values are dependant on crystal attributes The load capacitance given in a crystal data sheet specifies the parallel resonance frequency within the tolerance at 25 C Therefore it is important to design a circuit that matches the load capacitance to achieve the frequency stipulated by the manufacturer For accurate crystal circuit design and optimization an applications note on crystal design considerations is available for more information XTAL XTAL1 Rz1MO 04997 047 1 XTAL T 28 63636MHz d Figure 44 Crystal Circuit Follow these guidelines to ensure correct operation the correct frequency crystal which is 28 63636 MHz Tolerance is 50 ppm or higher e Usea parallel resonant crystal e 1 shunt resistor across pins XTAL and XTALI as 15 shown in Figure 44 Know Croan the crystal part number selected The value of Capacitor C1 and Capacitor C2 must match Croan for the specific crystal part number in the user s system Use following guideline to find Croan 1 2 2 Croap Cs Cpg where is pin to ground capacitance approximately 4 pF to 10 pF Cs is the PCB stray capacitance approximately 2 pF to For Example 30 pF 2 30 3 4 lt 50 Therefore two 47 capacitors may be selected for
139. rupt 00 w 75 0x4B PAL_SW_LK SCM_LOCK_ SD_AD_CH SD_H_LOCK SD_V_LOCK SD_OP_ Clear 3 0000 CHNG CLR CHNG CLR NG CLR CHNG CLR CHNG CLR CHNG CLR Interrupt 00 rw 76 Ox4C PAL SW LK SCM_LOCK_ SD AD SD 1 50 VLOCK SD OP Maskb 3 0000 _CHNG_ CHNG_ CHNG_ _CHNG_ _CHNG_ CHNG _ MSKB MSKB MSKB MSKB MSKB MSKB 1 To access the Interrupt Register Map the Register Access page 1 0 in Register Address must be programmed to 01b Rev B Page 66 of 100 Table 85 Interrupt Register Map Details ADV7183B Bit Subaddress Register Bit Description 716 514 3 2 1 0 Comments Notes 0 40 Interrupt INTRO OP SEL 1 0 0 0 Opendrain Config 1 Interrupt Drive Level Select low when active 1 O Drive high when active Register 1 1 Reserved Access MPU_STIM_INTRQ 1 0 0 Manual interrupt mode disabled Manual Set Mod anual Interrupt Set Mode Manual interrupt mode enabled Reserved x Not used MV_INTRQ_SEL 1 0 010 Reserved Macrovision Interrupt 0 1 Pseudo sync only Select 110 Color stripe only 111 Pseudo sync or color stripe INTRQ_DUR_SEL 1 0 010 3 Xtal periods Interrupt Duration Select 1 15 Xtal periods 110 63 Xtal periods 111 Active until cleared 0 41 Reserved 0 42 Interrupt SD LOCK 0 Nochange
140. rved on tuner outputs Figure 36 and Figure 37 show IF filter compensation for NTSC and PAL COMMON SPACE ADDRESS 0x00 gt ADDRESS Ox0E 6 5 00b ADDRESS OxOE 6 5 01b The options for this feature are as follows SPACE SPACE REGISTER ACCESS PAGE 1 REGISTER ACCESS PAGE 2 ADDRESS 0x40 gt ADDRESS 0x40 gt 0x4C 8 Bypass mode default NORMAL REGISTER SPACE INTERRUPT REGISTER 2 NTSC consists of three filter characteristics Figure 38 Register Access Page 1 and Page 2 e PAL consists of three filter characteristics Rev B Page 57 of 100 ADV7183B Interrupt Request Output Operation When an interrupt event occurs the interrupt pin INTRQ goes low with a programmable duration given by INTRQ_OP_SEL 1 0 Interrupt Duration Select Address 0x40 Interrupt 1 0 Table 77 INTRQ OP SEL INTRQ_DUR_SEL 1 0 INTRQ_DURSEL 1 0 Interrupt Duration Select Address 0x40 Interrupt Space 7 6 Table 76 INTRQ DUR SEL INTRQ OP SEL 1 0 Description 00 default Open drain 01 Drive low when active 10 Drive high when active 11 Reserved INTRQ DURSEL 1 0 Description 00 default 01 10 11 3 Xtal periods 15 Xtal periods 63 Xtal periods Active until cleared When the active until cleared interrupt duration is selected and the event that caused the interrupt is no longer in force the interrupt
141. s CSH that have selectable responses e Gain Control Automatic gain control can operate on several different modes including gain based on the color subcarrier s amplitude gain based on the depth of the horizontal sync pulse on the luma channel or fixed manual gain e Chroma Resample The chroma data is digitally resampled to keep it perfectly aligned with the luma data The resampling is done to correct for static and dynamic line length errors of the incoming video signal e Chroma 2 Comb The two dimensional 5 line superadaptive comb filter provides high quality Y C separation when the input signal is CVBS Code Insertion At this point the demodulated chroma Cr and Cb signal is merged with the retrieved luma values AV codes as per ITU R BT 656 can be inserted Rev B Page 20 of 100 SYNC PROCESSING ADV7183B extracts syncs embedded in the video data stream There is currently no support for external HS VS inputs The sync extraction has been optimized to support imperfect video sources such as VCRs with head switches The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm The raw sync information is sent to a line length measurement and prediction block The output of this is then used to drive the digital resampling section to ensure the ADV7183B outputs 720 active pixels per line
142. s Refer to Figure 46 for a recommended capacitor network for this pin 48 49 CAPY1 CAPY2 ADC s Capacitor Network Refer to Figure 46 for a recommended capacitor network for this pin 54 55 CAPC1 CAPC2 ADC s Capacitor Network Refer to Figure 46 for a recommended capacitor network for this pin Rev B Page 12 of 100 ANALOG FRONT END ADV7183B INTERNAL MAPPING FUNCTIONS 04997 006 Figure 6 Internal Pin Connections ANALOG INPUT MUXING The ADV7183B has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder Figure 6 outlines the overall structure of the input muxing provided in the ADV7183B As seen in Figure 6 the analog input muxes can be controlled by functional registers INSEL or manually Using INSEL 3 0 simplifies the setup of the muxes and minimizes crosstalk between channels by pre assigning the input channels This is referred to as ADI recommended input muxing Control via an manual override ADC_sw_man_en ADCO sw and ADC1_sw ADC2_sw is provided for applications with special requirements for example number combinations of signals that would not be served by the pre assigned input connections This is referred to as manual input muxing Refer to Figure 7 for an overview of the two methods of controlling the ADV7183B s input muxing ADI Recommended Input Muxing A maximum of 12 CVBS inputs can be connec
143. s disregarded PWRDN Address 0x0F 5 Setting the PWRDN bit switches the ADV7183B into a chip wide power down mode The power down stops the clock from entering the digital section of the chip thereby freezing its operation No bits are lost during power down The PWRDN bit also affects the analog blocks and switches them into low current modes The interface is unaffected and remains operational in power down mode The ADV7183B leaves the power down state if the PWRDN bit is set to 0 via or if the overall part is reset using the RESET pin PDBP must be set to 1 for the PWRDN bit to power down the ADV7183B When PWRDN is 0 default the chip is operational When PWRDN is 1 the ADV7183B is in chip wide power down ADC Power Down Control The ADV7183B contains three 10 bit ADCs ADC 0 ADC 1 and ADC 2 If required each ADC can be powered down individually The ADCs should be powered down when in CVBS mode ADC 1 and ADC 2 should be powered down to save on power consumption S Video mode ADC 2 should be powered down to save on power consumption PWRDN ADC 0 Address 0x3A 3 When PWRDN ADC 0150 default the ADC is in normal operation When PWRDN 015 1 ADC 0 is powered down PWRDN ADC 1 Address 0x3A 2 When PWRDN ADC 1 is 0 default the ADC is in normal operation When PWRDN ADC 1 is 1 1 is powered down PWRDN 2 Address 0 3 1 When PWRDN ADC
144. s split into half bytes and inserted default When GDECAD is 1 the data is output straight in 8 bit format Table 74 NTSC Line Enable Bits and Corresponding Line Numbering Line Number Line 3 0 ITU R BT 470 Enable Bit Comment 0 10 GDECOL O Gemstar 1 11 GDECOL 1 Gemstar 2 12 GDECOL 2 Gemstar 3 13 Gemstar 4 14 GDECOL 4 Gemstar 5 15 GDECOL 5 Gemstar 6 16 GDECOL 6 Gemstar 7 17 GDECOL 7 Gemstar 8 18 GDECOL 8 Gemstar 9 19 GDECOL 9 Gemstar 10 20 GDECOL 10 Gemstar 11 21 GDECOL 11 Gemstar or closed caption 12 22 GDECOL 12 Gemstar 13 23 GDECOL 13 Gemstar 14 24 GDECOL 14 Gemstar 15 25 GDECOL 15 Gemstar 0 273 10 GDECEL O0 Gemstar 1 274 11 GDECEL 1 Gemstar 2 275 12 GDECEL 2 Gemstar 3 276 13 GDECEL 3 Gemstar 4 277 14 GDECEL 4 Gemstar 5 278 15 GDECEL 5 Gemstar 6 279 16 GDECEL 6 Gemstar 7 280 17 GDECEL 7 Gemstar 8 281 18 GDECEL 8 Gemstar 9 282 19 GDECEL 9 Gemstar 10 283 20 GDECEL 10 Gemstar 11 284 21 GDECEL 11 Gemstar or closed caption 12 285 22 GDECEL 12 Gemstar 13 286 23 GDECEL 13 Gemstar 14 287 24 GDECEL 14 Gemstar 15 288 25 GDECEL 15 Gemstar Rev B Page 56 of 100 ADV7183B Table 75 PAL Line Enable Bits and Corresponding Line Numbering Line Number Line 3 0 ITU R BT 470 Enable Bit Comment 12 8 GDECOL O Not valid a 13 9 Not valid 14 10 GDEC
145. set Cr 1000 0000 rw 226 OxE2 SD Saturation Cb 1000 0000 rw 227 OxE3 SD Saturation Cr 1000 0000 rw 228 OxE4 NTSC V Bit Begin 0010 0101 rw 229 OxE5 NTSC V Bit End 0000 0100 rw 230 OxE6 NTSC F Bit Toggle 01100011 rw 231 OxE7 PAL V Bit Begin 01100101 rw 232 OxE8 PAL V Bit End 0001 0100 rw 233 OxE9 PAL F Bit Toggle 01100011 rw 234 OxEA Reserved XXXX XXXX rw 235 to 243 OxEB to OxF3 Rev B Page 63 of 100 ADV7183B Subaddress Register Name Reset Value rw Dec Hex Drive Strength xx01 0101 rw 244 OxF4 Reserved XXXX XXXX rw 245 to 247 OxF5 to OxF7 IF Comp Control 0000 0000 rw 248 OxF8 VS Mode Control 0000 0000 rw 249 OxF9 Table 83 Common and Normal Page 1 Register Map Bit Names Register Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Input Control VID SEL 3 VID SEL 2 VID SEL 1 VID SEL O INSEL 3 INSEL 2 INSEL 1 INSEL O Video Selection ENHSPLL BETACAM ENVSPROC Reserved Output Control VBI EN TOD OF SEL 3 OF SEL 2 OF SEL 1 OF SEL O SD DUP AV Extended Output Control BT656 4 TIM OE BL C VBI EN SFL PI RANGE Reserved Reserved Autodetect Enable AD SEC525 EN AD SECAM EN AD N443 EN AD P60 EN AD PALN EN AD PALM EN AD NTSC AD PAL EN Contrast CON7 CON 6 CON 5 CON 3 CON 2 CON 1 CON O Reserved Brightness BRI 7 BRI 6 BRI 5 BRI 4 BRI 3 BRI 2 BRI 1 BRI O Hue
146. ss Register Bit Description 7615143 2 1 0 Comments Notes 0 51 Lock 2 01 Count into lock determines 0 O O 1line of video Count the number of lines the system must 11 2lines of video remain in lock before showing a o 1 5 lines of video locked status O 1 1 10 lines of video 1 0 0 100 lines of video 1 O 1 500 lines of video 1 1 0 1000 lines of video 1 1 1 100000 lines of video COL 2 0 Count out of lock 01010 1 line of video determines the number of lines the 0 01 2 lines of video system must remain out of lock zli before showing a lost locked status SS 01111 10 lines of video 1 0 0 100 lines of video 11011 500 lines of video 11110 1000 lines of video 11111 100000 lines of video SRLS Select raw lock signal Selects 0 Over field with vertical the determination of the lock status info 1 Line to line evaluation FSCLE Fsc lock enable 0 Lock status set only by horizontal lock 1 Lock status set by horizontal lock and subcarrier lock Ox8F Free Run Reserved 0 0 0 0 Set to default Line LLC_PAD_SEL 2 0 Enables manual LLC1 nominal 27 MHz Length 1 selection of clock for LLC1 pin selected out on LLC1 pin 11011 LLC2 nominally For 16 bit 4 2 2 out 13 5 MHz selected out on OF_SEL 3 0 0010 LLC1 pin Reserved 0 Set to default 0x90 VBI Info WSSD Screen signaling detected 0 No WSS detected Read only status bits Read Only 1 WSS detec
147. structs the decoder not to attempt to decode Gemstar or CCAP data from any line in the even field GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 The 16 bits of the GDECOL 15 0 form a collection of 16 individual line decode enable signals See Table 74 and Table 75 To retrieve closed caption data services on NTSC Line 21 11 must be set To retrieve closed caption data services on PAL Line 22 GDECOL 14 must be set The default value of GDECOL 15 0 is 0x0000 This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the odd field GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 The decoded data from Gemstar compatible transmissions or closed caption is inserted into the horizontal blanking period of the respective line of video There is a potential problem if the retrieved data bytes have the value 0x00 or OxFE In an ITU R BT 656 compatible data stream those values are reserved and used only to form a fixed preamble The GDECAD bit allows the data to be inserted into the horizontal blanking period in two ways e Insert all data straight into data stream even reserved values of 0x00 and OxFF if they occur This can violate the output data format specification ITU R 1364 e Split all data into nibbles and insert the half bytes over double the number of cycles in a 4 bit format When GDECAD is 0 the data i
148. sync tip operation for the gain control in the algorithm off luma path 011 0 Peak white Blank level to sync tip algorithm on 011 1 Reserved Reserved 11011 Reserved 1 110 Reserved 1 11 Freeze gain Reserved 1 Setto 1 Rev B Page 77 of 100 ADV7183B Bits Subaddress Register Bit Description 7161543 Comments Notes 0 20 1 81 Chroma manual gain can 0 CAGC 1 0 settings Gain be used to program a desired decide in which mode Control 1 manual chroma gain Reading back 1 0 operates from this register in AGC mode gives the current gain Reserved Setto 1 1 0 Chroma automatic gain 010 Slow 2 sec Has an effect only if timing allows adjustment of the ol 1 Medium TC 1 sec CAGC 1 0 is set to i t in 10 chroma AGC tracking speed il Fast TC 02 sec auto gain 10 Adaptive 2 CMG 7 0 Chroma manual gain 0101000 1 0 7504 is Min value is 04 Gain lower 8 bits See CMG 11 8 for 1 in NTSC G 60 dB Control 2 description CMG 11 0 7414 gain is Max value is 3750 1in PAL G 5 Ox2F Luma Gain LMG 11 8 Luma manual gain can x LAGC 1 0 settings decide Control 1 be used to program a desired in which mode LMG 11 0 manual chroma gain or to read back operates the actual gain
149. t V high PVBEGSIGN Set to low when manual programming Not suitable for user programming PVBEGDELE Delay V bit going No delay high by one line relative to PVBEG Additional delay by 1 even field line PVBEGDELO Delay V bit going No delay high by one line relative to PVBEG Additional delay by 1 odd field line OxE9 PAL V Bit PVEND 4 0 Number of lines after 110 PAL default BT 656 End rollover to set V low PVENDSIGN Set to low when manual programming Not suitable for user programming PVENDDELE Delay V bit going low No delay by one line relative to PVEND Additional delay by 1 even field line PVENDDELO Delay V bit going No delay low by one line relative to PVEND Additional delay by 1 odd field line PAL F Bit PFTOG 4 0 Number of lines after 0 0 PAL default BT 656 Toggle rollover to toggle signal PFTOGSIGN Set to low when manual programming Not suitable for user programming PFTOGDELE Delay F transition by No delay one line relative to PFTOG even Additional delay by 1 field line PFTOGDELO Delay F transition by No delay one line relative to PFTOG odd Additional delay by 1 field line Rev B Page 86 of 100 ADV7183B Bits Subaddress Register Bit Description 716 5 413 2 0 Comments Notes OxF4 Drive DR STR S 1
150. t to 0 PVS Sets the VS polarity 0 Active high 1 Active low Reserved 0 Set to 0 PHS Sets HS polarity 0 Active high 1 Active low 0x38 NTSC YCMN 2 0 Luma 0 O O Adaptive 3 line 3 tap luma oe comb mode NTSC 1 0 O Use low pass notch 110 1 Fixed luma comb 2 line Top lines of memory 1 1 0 Fixed luma comb 3 Line lines of memory 1 1 1 Fixed luma comb 2 line Bottom lines of memory CCMN 2 0 Chroma 3 line for comb mode NTSC CTAPSN 01 4 line for CTAPSN 10 5 line adaptive for CTAPSN 11 11010 Disable chroma comb 11011 Fixed 2 line for Top lines of memory CTAPSN 01 Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 1 110 Fixed 3 line for All lines of memory CTAPSN 01 Fixed 4 line for CTAPSN 10 Fixed 5 line for CTAPSN 11 11111 Fixed 2 line for Bottom lines of CTAPSN 01 memory Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 CTAPSN 1 0 Chroma 010 Adapts 3 lines 2 lines comb taps NTSC 0 1 Not used 110 Adapts 5 lines 3 lines 111 5 lines 4 lines Rev 79 of 100 ADV7183B Subaddress Register Bit Description Bits Comments Notes 0x39 PAL Comb Control YCMP 2 0 Luma Comb mode PAL Adaptive 5 line 3 tap luma comb Use low pass notch Fixed luma comb Top li
151. tated The timing pins HS VS FIELD can be forced active via the TIM_OE bit For more information on three state control refer to the Three State LLC Driver and the Timing Signals Output Enable sections Individual drive strength controls are provided via the DR STR XX bits The ADV7183B supports three stating via a dedicated pin When set high the OE pin three states the output drivers for the P15 to PO HS VS FIELD and SFL pins The output drivers are three stated if the TOD bit or the OE pin is set high When TOD is 0 default the output drivers are enabled When TOD is 1 the output drivers are three stated Three State LLC Driver TRI LLC Address 0x1D 7 This bit allows the output drivers for the LLC1 and LLC2 pins of the ADV7183B to be three stated For more information on three state control refer to the Three State Output Drivers and the Timing Signals Output Enable sections Individual drive strength controls are provided via the DR STR XX bits When TRI LLC is 0 default the LLC pin drivers work according to the STR C 1 0 setting pin enabled When TRI LLC is 1 the LLC pin drivers are three stated Timing Signals Output Enable OE Address 0x04 3 OE bit should be regarded as an addition to the TOD bit Setting it high forces the output drivers for HS VS and FIELD pins into the active driving state even if the TOD bit is set If set to low the HS VS and FIELD pins are
152. tection Although this product features 1 proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance m degradation or loss of functionality ESD SENSITIVE DEVICE Page 10 of 100 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS aan x 2 ain WwogtFPrezSoegoaagmods rlozZzZaagaaaAAZZHH 2 lt 4 80 179 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 2 vs 1 60 5 5 2 T 59 AIN11 DGND 3 58 AIN4 DVDDIO 4 57 AIN10 11 5 56 10 6 55 2 Po ADV7183B P8 8 TOP VIEW 53 AGND DGND 9 Not to Scale 52 CML 10 51 REFOUT INTRQ 11 50 AVDD SFL 12 49 CAPY2 NC 13 48 CAPY1 DGND 14 47 AGND DVDDIO 15 46 AIN3 NC 16 45 AIN9 NC 17 44 AIN2 NC 18 43 AIN8 7 19 42 AIN1 P6 20 41 AIN7 21 22 23 2411 25 26 27 28 29 30 31 32 3311 34 35 36 37 38 39 40 CONNECT 2 o 5828 8 2 gt 8 lt lt 3 Figure 5 80 Lead LOFP Pin Configuration Rev 11 of 100 ADV7183B ADV7183B Table 7 Pin Function Descriptions Pin No Mnemonic Type Description 3 9 14 3
153. ted CCAPD Closed caption data 0 CCAP signals detected 1 CCAP sequence detected EDTVD EDTV sequence 0 EDTV sequence detected 1 EDTV sequence detected CGMSD CGMS sequence 0 CGMS transition detected 1 CGMS sequence decoded Reserved x x 0x91 WSS1 WSS1 7 0 Read Only wide screen signaling data 0 92 552 WSS2 7 0 X X x x x WSS2 7 6 are Read Only Wide screen signaling data undetermined 0 93 WSS2 WSS2 7 0 X X X X X Read Only Wide screen signaling data 0 94 EDTV2 EDTV2 7 0 Read Only EDTV data register 0 95 EDTV3 EDTV3 7 0 X X x x EDTV3 7 6 are EDTV3 5 is reserved Read Only EDTV data register undetermined for future use 0x96 CGMS1 CGMS1 7 0 Read Only CGMS data register Rev B Page 82 of 100 ADV7183B Bits Subaddress Register Bit Description 7161543 Comments Notes 0 97 CGMS2 CGMS2 7 0 X X x Read Only CGMS data register 0x98 CGMS3 CGMS3 7 0 X X CGMS3 7 4 are Read Only CGMS data register undetermined 0x99 CCAP1 CCAP1 7 0 X X CCAP1 7 contains parity Read Only Closed caption data register bit for byte 0 Ox9A CCAP2 CCAP2 7 0 X X CCAP2 7 contains parity Read Only Closed caption data register bit for byte 0 Ox9B Letterbox 1 LB LCT 7 0 X
154. ted and decoded by the ADV7183B As seen in Figure 5 this means the sources will have to be connected to adjacent pins on the IC This calls for a careful design of the PCB layout such as ground shielding between all signals routed through tracks that are physically close together INSEL 3 0 Input Selection Address 0x00 3 0 The INSEL bits allow the user to select an input channel as well as the input format Depending on the PCB connections only a subset of the INSEL modes is valid The INSEL 3 0 not only switches the analog input muxing it also configures the standard definition processor core to process CVBS Comp S Video Y C or component YPbPr format Rev B Page 13 of 100 ADV7183B CONNECTING ANALOG SIGNALS TO ADV7183B ADI RECOMMENDED YES INPUT MUXING SEE TABLE 9 SET INSEL 3 0 FOR REQUIRED MUXING CONFIGURATION SET INSEL 3 0 TO CONFIGURE ADV7183B TO DECODE VIDEO FORMAT CVBS 0000 YC 0110 YPrPb 1001 USE MANUAL INPUT MUXING ADC SW MAN ADCO SW ADC1 SW ADC2 SW 04997 007 Figure 7 Input Muxing Overview Table 8 Input Channel Switching Using INSEL 3 0 Table 9 Input Channel Assignments Description INSEL 3 0 Analog Input Pins Video Format 0000 default CVBS1 AIN1 Composite 0001 CVBS2 AIN2 Composite 0010 CVBS3 AIN3 Composite 0011 CVBS4 AIN4 Composite 0100 CVBS5 AIN5 Composite 0101 CVBS6 AIN6 Composite 0110 Y1 AIN1 Y C C1
155. th is fed to the combs A wide split filter selection eliminates dot crawl but shows imperfections on diagonal lines the opposite is true for selecting a narrow bandwidth split filter CTAPSP 1 0 Chroma Comb Taps PAL Address 0x39 7 6 Table 49 CTAPSP Function CTAPSP 1 0 Description 00 Do not use 01 PAL chroma comb adapts 5 lines 3 taps to 3 lines 2 taps cancels cross luma only 10 PAL chroma comb adapts 5 lines 5 taps to 11 default 3 lines 3 taps cancels cross luma and hue error less well PAL chroma comb adapts 5 lines 5 taps to 4 lines 4 taps cancels cross luma and hue error well CCMP 2 0 Chroma Comb Mode PAL Address 0x39 5 3 Table 50 CCMP Function CCMP 2 0 Description Configuration Oxx default 100 101 110 111 Adaptive comb mode Adaptive 3 line chroma comb for CTAPSP 01 Adaptive 4 line chroma comb for CTAPSP 10 Adaptive 5 line chroma comb for CTAPSP 11 Disable chroma comb Fixed chroma comb top lines of line memory Fixed 2 line chroma comb for CTAPSP 01 Fixed 3 line chroma comb for CTAPSP 10 Fixed 4 line chroma comb for CTAPSP 11 Fixed chroma comb all lines of line memory Fixed 3 line chroma comb for CTAPSP 01 Fixed 4 line chroma comb for CTAPSP 10 Fixed 5 line chroma comb for CTAPSP 11 Fixed chroma comb bottom lines of line memory Fixed 2 line chroma comb for CTAPSP 01 Fixed 3 line chroma comb for CTAPSP 10 Fixed 4 line chroma comb fo
156. ts back a midcount via LB LCM 7 0 If no subtitles are found LB LCM 7 0 reports the same number asLB LCB 7 0 There is a 2 field delay in the reporting of any line count parameters There is no letterbox detected bit The user is asked to read the LB LCT 7 0 and LB LCB 7 0 register values and to conclude whether or not the letterbox type video is present in software LB 7 0 Letterbox Line Count Top Address 0x9B 7 0 LB LCM 7 0 Letterbox Line Count Mid Address 0x9C 7 0 LB LCB 7 0 Letterbox Line Count Bottom Address 0x9D 7 0 Table 62 LB LCx Access Information Signal Name Address Register Default Value LB LCT 7 0 Ox9B Readback only LB LCM 7 0 9 Readback only LB_LCB 7 0 Ox9D Readback only LB TH 4 0 Letterbox Threshold Control Address 0xDC 4 0 Table 63 LB_TH Function LB TH 4 0 Description 01100 default Default threshold for detection of black lines 01101 to 10000 Increase threshold need larger active video content before identifying nonblack lines 00000 to 01011 Decrease threshold even small noise levels can cause the detection of nonblack lines LB SL 3 0 Letterbox Start Line Address 0xDD 7 4 The LB SL 3 0 bits are set at 0100b by default This means the letterbox detection window starts after the EDTV VBI data line For an NTSC signal this window is from Line 23 to Line 286 Changing the bits to 0101 the detection window starts on Line 24 and ends
157. ts between PWRDN bit or PIN controlled by pin Bit has priority pin disregarded Reserved 0 0 Set to default PWRDN Power down places the 0 System functional decoder in a full power down mode 1 Powered down See PDBP OxOF Bit 2 Reserved 0 Set to default RES Chip reset loads all PC bits with 0 Normal operation default values 1 Start reset sequence Executing reset takes approximately 2 ms This bit is self clearing 0x10 Status IN_LOCK In lock right now 1 Provides information LOST LOCK Lost lock since lastread 1 about ead Ony FESC LOCK FOLLOW_PW Peak white AGC mode active 1 AD_RESULT 2 0 Autodetection NTSM MJ Detected standard result reports the standard of the 1 NTSC 443 input video o lilo PALM 01111 160 110140 PAL B G H I D 1 0 1 SECAM 1 110 PAL combination 1 111 525 COL KILL Color 15 active 1 Color kill Ox11 IDENT IDENT 7 0 Provides identification x ADV7183B 0x13 Read Only on the revision of the part 0x12 Status MVCS DET MV color striping detected 1 detected Register 2 MVCS MV color striping type 0 Type 2 Read Only 1 3 5 MV pseudo sync 1 detected detected MV DET MV pulses detected 1 detected LLNSTD Nonstandard line length 1 detected FSCNSTD Fsc frequency nonstandard 1 detected Reserved 0 13 Sta
158. tus Ox4C Register SD vertical sync lock status has respectively Access changed Page 2 SD_H_LOCK_CHNG_Q No change in SD horizontal sync lock status SD horizontal sync lock status has changed SD_AD_CHNG_Q x No change in AD_RESULT 2 0 SD autodetect changed bits in Status Register 1 AD_RESULT 2 0 bits in Status Register 1 have changed SCM_LOCK_CHNG_Q 0 No change in SECAM lock status SECAM Lock 1 SECAM lock status has changed PAL SW LK CHNG x No change in PAL swinging burst lock status PAL swinging burst lock status has changed Reserved x Not used Reserved Not used Rev B Page 69 of 100 ADV7183B Bit Subaddress Register Bit Description 61514 3 5 Notes Ox4B Interrupt SD OP CHNG CLR Do not clear Clear 3 Clears SD OP CHNG Q bit SD V LOCK CHNG CLR Do not clear Write Only Clears SD V LOCK CHNG Q bit Register SD H LOCK CHNG CLR Do not clear Clears SD_H_LOCK_CHNG_Q bit Register Access SD_AD_CHNG_CLR 0 Do not clear Page 2 1 Clears SD_AD_CHNG_Q bit SCM_LOCK_CHNG_CLR 0 Do not clear 1 Clears SCM_LOCK_CHNG_Q bit PAL_SW_LK_CHNG_CLR 0 Do not clear 1 Clears PAL_SW_LK_CHNG_Q bit Reserved x Not used Reserved Not used Ox4C Interrupt SD OP CHNG MSKB Masks SD OP CHNG Q bit Mask 2 Unmasks SD OP CHNG bit SD V LOCK CHNG MSKB Masks SD V LOCK CHNG bit Read Write U
159. tus INST HLOCK 1 horizontal lock Unfiltered Register 3 achieved Read Only GEMD 1 Gemstar data detected SD OP 50HZ SD 60 Hz detected SD Field rate detect Reserved SD 50 Hz detected FREE RUN ACT 1 mode active Blue screen output STD FLD LEN 1 field length standard Correct field length found INTERLACED 1 interlaced video Field sequence found detected PAL SW LOCK 1 swinging burst Reliable swinging detected burst sequence 0 14 Analog Reserved 0 Set to default Clamp CCLEN Current clamp enable allows 0 Current sources switched Control the user to switch off the current off sources in the analog front 1 Current sources enabled Reserved 0 Set to default Rev B Page 74 of 100 ADV7183B Subaddress Register Bit Description Comments Notes 0x15 Digital Clamp Control 1 Reserved Set to default DCT 1 0 Digital clamp timing determines the time constant of the digital fine clamp circuitry Slow TC 1 sec Medium TC 0 5 sec Fast 0 1 sec dependent on video Reserved Set to default 0x17 Shaping Filter Control YSFM 4 0 Selects Y Shaping Filter mode when in CVBS only mode Allows the user to select a wide range of low pass and notch filters If either auto mode is selected the decoder selects the optimum Y filte
160. ty Y C separation can be achieved by using the internal comb filters of the ADV7183B Comb filtering however relies on the frequency relationship of the luma component multiples of the video line rate and the color subcarrier Fsc For good quality CVBS signals this relationship is known the comb filter algorithms can be used to separate out luma and chroma with high accuracy For nonstandard video signals the frequency relationship may be disturbed and the comb filters may not be able to optimally remove all crosstalk artifacts without the assistance of the shaping filter block An automatic mode is provided The ADV7183B evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard YFSM WYSFMOVR and WYSEM allow the user to manually override the automatic decisions in part or in full The luma shaping filter has three control registers e 4 0 allows the user to manually select a shaping filter mode applied to all video signals or to enable an automatic selection dependent on video quality and video standard WYSFMOVR allows the user to manually override the WYSEM decision WYSFM 4 0 allows the user to select a different shaping filter mode for good quality CVBS component YPrPb and S VHS Y C input signals In automatic mode the system preserves the maximum possible bandwidth for good CVBS sources since they can succ
161. ual user settings see Table 56 and Figure 22 for NTSC see Table 57 and Figure 27 for PAL HVSTIM Horizontal VS Timing Address 0x31 3 The HVSTIM bit allows the user to select where the VS signal is being asserted within a line of video Some interface circuitry can require VS to go low while HS is low When HVSTIM is 0 default the start of the line is relative to HSE When HVSTIM is 1 the start of the line is relative to HSB VSBHO VS Begin Horizontal Position Odd Address 0x32 7 The VSBHO and VSBHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low When VSBHO is 0 default the VS pin goes high at the middle ofa line of video odd field When VSBHO is 1 the VS pin changes state at the start of a line odd field VSBHE VS Begin Horizontal Position Even Address 0x32 6 The VSBHO and VSBHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state when only HS is high low When VSBHE is 0 the VS pin goes high at the middle of a line of video even field When VSBHE is 1 default the VS pin changes state at the start of a line even field VSEHO VS End Horizontal Position Odd Address 0x33 7 The VSEHO and VSEHE bits select the position within a line at which the VS pin
162. unction CKILLTHR 2 0 Color Kill Threshold Address 0 30 6 4 The CKILLTHR 2 0 bits allow the user to select a threshold for the color kill function The threshold applies only to QAM based NTSC and PAL or FM modulated SECAM video standards To enable the color kill function the CKE bit must be set For settings 000 001 010 and 011 chroma demodulation inside the ADV7183B may not work satisfactorily for poor input video signals Table 42 CKILLTHR Function CG 11 0 CMG 11 0 Read Write Description CMG 11 0 Write Manual gain for chroma path CG 11 0 Read Currently active gain 0 lt lt 4095 _ Chroma Gain 0 4 2 1024 For example freezing automatic gain loop and reading back the CG 11 0 register results in a value of 0x47A 1 Convert the readback value to decimal 0x47A 1146d 2 Apply Equation 2 to convert readback value 1146 1024 1 12 CKE Color Kill Enable Address 0x2B 6 The color kill enable bit allows the optional color kill function to be switched on or off For QAM based video standards PAL and NTSC and FM based systems SECAM the threshold for the color kill decision is selectable via the CKILLTHR 2 0 bits If color kill is enabled and if the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines color processing is switched off black and white output To switch the color processing back on
163. upled into the decoder its dc value needs to be restored This process is referred to as clamping the video This section explains the general process of clamping on the ADV7183B and shows the different ways in which a user can configure its behavior The ADV7183B uses a combination of current sources and a digital processing block for clamping as shown in Figure 10 The analog processing channel shown is replicated three times inside the IC While only one single channel and only one ADC is needed for a CVBS signal two independent channels are needed for Y C S VHS type signals and three independent channels are needed to allow component signals YPrPb to be processed FINE COARSE CURRENT CURRENT SOURCES SOURCES ANALOG The clamping can be divided into two sections e Clamping before the ADC analog domain current sources Clamping after the ADC digital domain digital processing block The ADCs can digitize an input signal only if it resides within the ADC s 1 6 V input voltage range An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range The primary task of the analog clamping circuits is to ensure the video signal stays within the valid ADC input window so that the analog to digital conversion can take place It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the ADC range After
164. variations As shown in Figure 17 the ADV7183B can decode a video signal providing it fits into the ADC window Two components to this are the amplitude of the input signal and the dc level on which it resides The dc level is set by the clamping circuitry see the Clamp Operation section If the amplitude of the analog video signal is too high clipping can occur resulting in visual artifacts The analog input range of the ADC together with the clamp level determines the maximum supported amplitude of the video signal The minimum supported amplitude of the input video is determined by the ADV7183B s ability to retrieve horizontal and vertical timing and to lock to the color burst if present There are two gain control units one each for luma and chroma data Both can operate independently of each other The chroma unit however can also take its gain value from the luma path The possible AGC modes are summarized in Table 33 It is possible to freeze the automatic gain control loops This causes the loops to stop updating and the AGC determined gain at the time of the freeze to stay active The ACG determined gain stays active until the automatic gain control loop is either unfrozen or the gain mode of the operation is changed The currently active gain from any of the modes can be read back Refer to the description of the dual function manual gain registers LG 11 0 Luma Gain and CG 11 0 Chroma Gain in the Luma Gain
165. ved 101 Reserved 110 Reserved 111 Freeze gain LAGT 1 0 Luma Automatic Gain Timing Address Ox2F 7 6 The luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control Note that this register has an effect only if the LAGC 2 0 register is set to 001 010 011 or 100 automatic gain control modes If peak white AGC is enabled and active see the STATUS 1 7 0 Address 0x10 7 0 section the actual gain update speed is dictated by the peak white AGC loop and as a result the LAGT settings have no effect As soon as the part leaves peak white AGC LAGT becomes relevant again The update speed for the peak white algorithm can be custom ized by the use of internal parameters Contact ADI sales for more information LG 11 0 Luma Gain Address 0x2F 3 0 Address 0x30 7 0 LMG 11 0 Luma Manual Gain Address Ox2F 3 0 Address 0x30 7 0 Luma gain 11 0 is a dual function register If written to a desired manual luma gain can be programmed This gain becomes active if the LAGC 2 0 mode is switched to manual fixed gain Equation 1 shows how to calculate a desired gain If read back this register returns the current gain value Depending on the setting in the LAGC 2 0 bits one of these gain values is returned e Luma manual gain value LAGC 2 0 set to luma manual gain mode e Luma automatic gain value LAGC 2 0 set to any of the automatic modes Tabl
166. window and if the polarity of the parity bit matches the data transmitted When CCAPD is 0 no CCAP sequences are detected and confidence in the decoded data is low When CCAPD is 1 the CCAP sequence is detected and confidence in the decoded data is high EDTVD EDTV Sequence Detected Address 0 90 2 A Logic 1 for this bit indicates the data the EDTV1 2 3 registers is valid The EDTVD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the data transmitted When EDTVD is 0 no EDTV sequence is detected and confidence in the decoded data is low When EDTVD is 1 an EDTV sequence is detected and confidence in the decoded data is high CGMSD CGMS A Sequence Detected Address 0x90 3 Logic 1 for this bit indicates that the data in the CGMSI 2 3 registers is valid The CGMSD bit goes high if a valid CRC checksum has been calculated from a received CGMS packet When CGMSD is 0 no CGMS transmission is detected and confidence in the decoded data is low When CGMSD is 1 the CGMS sequence is decoded and confidence in the decoded data is high CRC_ENABLE Address 0 2 2 For certain video sources the CRC data bits can have an invalid format In these circumstances the CRC checksum validation procedure can be disabled The CGMSD bit goes high if the rising edge of the start bit is detected within a time window When CRC_ENABLE is 0
167. x50 0x52 0x58 0x77 0 7 0 70 OxD5 OxD7 0 4 0 9 OxOE 0x83 0x01 0x00 0 41 OxFA 0x16 0 80 0 20 0 18 OxED OxC5 0 93 0 00 0 48 OxAO OxEA Ox3E Ox3E OxOF 0 00 CVBS AIN4 Force PAL only mode Enable PAL autodetection only Slow down digital clamps Set CSFM to SH1 Stronger dot crawl reduction Power down ADC 1 and ADC 2 Set higher DNR threshold ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Rev B Page 93 of 100 ADV7183B PCB LAYOUT RECOMMENDATIONS The ADV7183B is a high precision high speed mixed signal device To achieve the maximum performance from the part it is important to have a PCB board with a good layout This section provides guidelines for designing a board using the ADV7183B ANALOG INTERFACE INPUTS Care should be taken when routing the inputs on the PCB Track lengths should be kept to minimum and 75 trace impedances should be used when possible Trace impedances other than 75 Q also increase the chance of reflections POWER SUPPLY DECOUPLING It is recommended to decouple each p
168. ystem Autodetection of SD Modes To guide the autodetection system individual enable bits are provided for each of the supported video standards Setting the relevant bit to 0 inhibits the standard from being detected automatically Instead the system picks the closest of the remaining enabled standards The results of the autodetection can be read back via the status registers See the Global Status Registers section for more information VID_SEL 3 0 Address 0x00 7 4 Table 18 VID_SEL Function VID_SEL Description 0000 default Autodetect PAL BGHID lt gt NTSC J no pedestal SECAM 0001 Autodetect PAL BGHID lt gt NTSC M pedestal SECAM 0010 Autodetect PAL N pedestal lt gt NTSC J no pedestal SECAM 0011 Autodetect PAL N pedestal lt gt NTSC M pedestal SECAM 0100 NTSC J 1 0101 NTSC M 1 0110 PAL60 0111 NTSC 43 1 1000 PAL B G H I D 1001 PAL N PAL BGHID with pedestal 1010 PAL M without pedestal 1011 PAL M 1100 PAL Combination N 1101 PAL COMBINATION N with pedestal 1110 SECAM 1111 SECAM with pedestal AD SEC525 EN Enable Autodetection of SECAM 525 Line Video Address 0x07 7 Setting AD SEC525 EN to 0 default disables the autodetection of a 525 line system with a SECAM style FM modulated color component Setting AD SEC525 EN to 1 enables the detection Rev B Page 21 of 100 ADV7183B AD_SECAM_EN Enable Autodetection of SECAM Address 0

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