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MICRON SYNCHRONOUS DRAM 128Mb x4 x8 x16 SDRAM

1. H H H d I d i 1 1 1 1 9 H d rn Cs 99 CONTROL l 2u LOGIC WE gt 0 Za n 9 BANK3 CASH _ 28 2 H BANK1 H t H 1 i 1 H H LJ 1 REFRESH i5 COUNTER EY MODE REGISTER ROW i2 BANKO ADDRESS ROW BANKO H 12 ADDRESS MEMORY 1 IN LATCH ARRAY Z 12 amp 4 096 x 1 024 x 8 DECODER H I SENSE AMPLIFIERS DATA 8 OUTPUT 1 4096 REGISTER i i 4 1 i E VO GATING 8 DQo DQM MASK LOGIC 297 BANK READ DATA LATCH A0 A11 7a ADDRESS Be CONTROL WRITE DRIVERS BAO REGISTER LOGIC DATA h 2 I INPUT H REGISTER 3 H Po 8 H P H COLUMN H DECODER COLUMN H 1 ADDRESS 10 10 COUNTER LATCH 1 1 1 1 i i i E i i i 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 6 2001 Micron Technology Inc Micron 128Mb x4 x8 x16 SDRAM FUNCTIONAL BLOC
2. co Z77770 n C en tac tac tac tac tac E lt gt lt gt tac toH toH toH toH PESCE a PR ra PUE EQ IUE DQ t Dour m Dour m 1 Dour m 2X y A Dour b uz tRCD BANK 0 CAS Latency BANK 0 BANK 0 tRCD BANK 0 E gt gt m gt RAS BANK 0 m RC BANK 0 m tRRD tRCD BANK 3 CAS Latency BANK 3 gt DON T CARE RA UNDEFINED TIMING PARAMETERS 7E 75 8E 7E 75 8E SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS 3 5 4 5 4 6 ns tCMH 0 8 0 8 1 ns 2 5 4 6 6 ns tcMS 1 5 1 5 2 ns tAH 0 8 0 8 1 ns uz 1 1 1 ns tAS 1 5 1 5 2 ns tOH 3 3 3 ns 2 5 2 5 3 ns tRAS 44 120 000 44 120 000 50 120 000 ns tcL 2 5 2 5 3 ns tRC 60 66 70 ns tcK 3 7 7 5 8 ns tRCD 15 20 20 ns tCK 2 75 10 10 ns tRP 15 20 20 ns tCKH 0 8 0 8 1 ns tRRD 14 15 20 ns CKS 1 5 1 5 2 ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 4 and the CAS latency 2 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 46 2001 Micron Technology Inc Micron 128Mb x4 x8 x16 SDRAM READ FULL PA
3. BA0 BA1 0 Z 77 BANK 0 I I BANK 1 Z 1 2 BANK 0 S tos tpH 1 5 tDH ips tpH 1 5 tpH 105 tps tps tp gt gt j gt ll ls gt DQ Dinm VK QM oam QX sma a WK Din b WIN spa a KK ono WX RCD BANK 0 BANK 0 tRP BANK 0 tRCD BANK 0 _ RAS BANK 0 _ tRC BANK 0 RRD RCD BANK 1 tWR BANK 1 DON T CARE TIMING PARAMIETERS 7E 75 8E 7E 75 8E SYMBOL MIN MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS 08 1 ns tDH 0 8 0 8 1 ns tAS 15 15 2 ns tps 1 5 1 5 2 ns cH 25 25 3 ns tRAS 37 120 000 44 120 000 50 120 000 ns ta 25 25 3 ns tRC 60 66 70 ns k 7 75 8 ns tRCD 15 20 20 ns 2 75 10 ns 15 20 20 ns cH 1 ns tRRD 14 15 20 ns teks 15 15 2 ns twR 1CLK 1CLK 1CLK 0 8 1 ns 7ns 7 5ns 7ns 15 15 2 ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 4 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MS
4. RES KRAN GES MAAR SURES 128Mb x4 x8 x16 dicron x HORE SYNCHRONOUS peer Lee DRAM MT48LC8M 16A2 2 Meg x 16 x 4 banks For the latest data sheet please refer to the Micron Web site www micron com dramds SERT RES PC100 and PC133 compliant Fully synchronous all signals registered on positive PIN ASSIGNMENT Top View edge of system clock Internalpipelined operation column address can be 54 Pin TSOP changed every clock cycle 4 x8 x16 x16 x8 x4 Internal banks for hiding row access precharge V J cco Programmable burst lengths 1 2 4 8 or full page 55 m beds DO N Auto Precharge includes CONCURRENT AUTO A EE PRECHARGE and Auto Refresh Modes bus bel m 20 m poi OS Self Refresh Mode standard and low power NE N Mee on We fue 64ms 4 096 cycle refresh NC DQ2 DQ4 8 47 2011 DQ5 NC LVTTL compatible inputs and outputs es bon 5 a Mond MEM Single 3 3V 0 3V power supply DQ6 11 44 209 004 002 VssQ 12 43 VDDQ ul NC NC DQ7 13 42 En DQ8 NC NC OPT
5. 128Mb x4 x8 x16 Micron POWER DOWN MODE 1 Tn 1 Tn 2 gt _ i NIE A tcu Bi Ws 4 5 tcks tcKs lt oe WT tcKs tCKH tcMs tcMH COMMAND PRECHARGE NOP NOP MMM ALL BANKS A10 SINGLE BANK tas BAO BAI X BANK S WML BANK High Z 0 Two clock cycles Input buffers gated off while in power down mode Precharge all All banks idle enter J All banks idle active banks power down mode Exit power down mode V DON T CARE TIMING PARAMETERS 7E 75 8E 7E 75 8E SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS tAH 0 8 0 8 1 ns 2 7 5 10 10 ns tas 1 5 1 5 2 ns tCKH 0 8 0 8 1 ns 2 5 2 5 3 ns tcKS 1 5 1 5 2 ns tcL 2 5 2 5 3 ns tCMH 0 8 0 8 1 ns 3 7 7 5 8 ns tcMS 1 5 1 5 2 ns CAS latency indicated in parentheses NOTE 1 Violating refresh requirements during power down may result in a loss of data 128Mb x4 x8 x16 SDRAM Micron Technology Inc s the right to change produc cific without notice 128MSDRAM_E p65 Rev E Pub 1 02 38 2001 a n Te chnology Inc Micron CLK COMMAND y READ DQM DQML DQMH A0 A9 A11 DQ 128Mb x4 x8 x16 SDRAM CLOCK SUSPEND MODE
6. 31 Absolute Maximum Ratings 33 DC Electrical Characteristics and Operating Conditions 33 Specifications and Conditions 33 Ca PACHA CC 34 AC Electrical Characteristics and Recommended Operating Conditions Timing Table 34 Timing Waveforms Initialize and Load mode register 37 Power Down NI006_ a 38 Clock Suspend Mode 39 Auto Refresh Mode sese 40 Self Refresh 41 Reads Read Without Auto Precharge 42 Read With Auto Precharge 43 Single Read Without Auto Precharge 44 Single Read With Auto Precharge 45 Alternating Bank Read Accesses 46 Read Full Page Burst 47 Read DOM Operation 48 Writes Write Without Auto Precharge 49 Write With Auto Precharge 50 Single Write Without Auto Precharge 51 Single Write With Auto Precharge 52 Alternating Bank Write Accesses 53 Write Full Page Burst 54 Write DOM Operation 55 Micron Technology Inc reserves the right to
7. 5 30 sns n gu _ G 11 86 11 66 PIN 1 ID 10 24 10 08 HgGBBHHBBHHBBBHHBHSSAOBBSHgHBH Y fx 75 2X 1 00 2X 25 gt 05 60 QI 10 wa 40 1 2 MAX 80 DETAIL NOTE 1 All dimensions in millimeters or typical where noted 2 Package width and length do not include mold protrusion allowable mold protrusion is 0 25mm per side 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM_E p65 Rev Pub 1 02 56 2001 Micron Technology Inc 128Mb x4 x8 x16 dicron SDRAM FBGA FB PACKAGE 60 BALL 8mm x 16mm WO 0 850 0 075 0 325 0 025 0 205 SEATING PLANE 1 Y 0 10 5 60 _ 2 40 0 05 CTR 20 45 0 05 TYP 0 80 TYP 1 ID N oo 8 00 0 05 4 26 16 00 0 10 DO 11 20 pea e 0 80 5 60 0 05 6 2 80 0 05 1 20 4 00 0 05 m 8 00 0 10 Bottom View NOTE 1 All dimensions in mi
8. 7 75 8 ns tRC 60 66 70 ns 2 75 10 ns tRCD 15 20 20 ns cH 08 1 ns 15 20 20 ns teks 15 15 2 ns twR 14 15 15 ns os 08 ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 1 and the WRITE burst is followed by a manual PRECHARGE 2 15ns is required between lt Din m gt and the PRECHARGE command regardless of frequency 3 x16 A9 and A11 Don t Care x8 A11 Don t Care 4 PRECHARGE command not allowed else RAS would be violated 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 5 1 2001 Micron Technology Inc x 128Mb x4 x8 x16 qaicron SINGLE WRITE WITH AUTO PRECHARGE T0 Ti T2 T3 T4 T5 T6 T T8 T9 ak _ lt uM Nm J 4 Fc 4 4 4 teks ICKH ee 7 7 7 UE A US tems tcMH COMMAND yx ACTIVE XX XX XX WRITE XX NOP XX NOP XX ACTIVE XX NOP X tems tcMH oou V as an MMMM MM MM tas tAH ENABLE AUTO PRECHARGE MLL J Z tas BAO BANK Y 7 Wa Y Y BANK X7 Y WK BANK W 77 y 77 tps DH x X gt 77 J twR m t
9. reserves the right to change products or specifications without notice 128MSDRAM_E p65 Rev E Pub 1 02 2001 Micron Technology Inc 128Mb x4 x8 x16 Macron SDRAM CLK l l l COMMAND READ READ READ READ NOP NOP l l BANK BANK BANK ADDRESS COLn COLa COL x COL m l I l l l l Dout Dour Dour Dour La CAS Latency 2 T6 T1 e LA tLe tLe Ld Le L COMMAND READ X READ b READ X READ X NOP X NOP X NOP X T ADDRESS COL n COL a COL x COL m pues T Dout Dout Dout Dout x m DQ CAS Latency 3 NOTE Each READ command may be to any bank DQM is LOW DON T CARE Figure 8 Random READ Accesses 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM_E p65 Rev E Pub 1 02 1 8 2001 Micron Technology Inc Micron Data from any READ burst may be truncated with a subsequent WRITE command and data from a fixed length READ burst may be immediately followed by data from a WRITE command subject to bus turnaround limitations The WRITE burst may be initiated on the clock edge immediately fol
10. no longer at the 1 5V crossover point Refer to Micron Technical Note TN 48 09 for more details Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid Vin or Vit levels Ipp specifications are tested after the device is prop erly initialized Timing actually specified by CKS clock s specified as a reference only at minimum cycle rate 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 18 19 20 128Mb x4 x8 x16 SDRAM Timing actually specified by WR plus clock s specified as a reference only at minimum cycle rate Timing actually specified by WR Required clocks are specified byJEDEC functionality and are not dependent on any timing parameter The Ipp current will increase or decrease propor tionally according to the amount of frequency alter ation for the test condition Address transitions average one transition every two clocks CLK must be toggled a minimum of two times during this period 21 Based on 1005 for 8E and CK 7 515 for 75 and 7E 22 Vin overshoot MAX VppQ 2V fora pulse width 23 24 34 PC133 specifies minimum of 2 5pF 36 36 lt 3ns and the pulse width cannot be greater than one third ofthe cycle rate Vit undershoot Vit MIN 2V for a pulse width lt 3ns The clock frequency must remain constant stable clock is defined as a signal cycling wi
11. ns ACTIVE banka to ACTIVE bank B command 15 20 ng Transition time tT 1 2 ns 7 WRITE recovery time tWR 1 CLK 24 7ns 14 ns 25 Exit SELF REFRESH to ACTIVE command tXSR 67 75 80 ns 20 34 128Mb x4 x8 x16 Macron 3 SDRAM AC FUNCTIONAL CHARACTERISTICS Notes 5 6 7 8 9 11 notes appear on page 36 PARAMETER SYMBOL 7E 75 8E UNITS NOTES READ WRITE command to READ WRITE command tccD 1 1 1 17 to clock disable or power down entry mode tCKED 1 1 1 tcK 14 CKE to clock enable or power down exit setup mode tPED 1 1 1 tcK 14 DQM to input data delay tDQD 0 0 0 17 DQM to data mask during WRITEs tDQM 0 0 0 17 DQM to data high impedance during READs 607 2 2 2 17 WRITE command to input data delay tDWD 0 O 17 Data in to ACTIVE command tDAL 4 5 4 115 21 Data in to PRECHARGE command tDPL 2 2 2 tcK 16 21 Last data in to burst STOP command 1 1 1 tcK 17 Last data in to new READ WRITE command 1 1 1 tcK 17 Last data in to PRECHARGE command tRDL 2 2 2 tcK 16 21 LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 2 26 Data out to high impedance from PRECHARGE command CL 3 ROH 3 3 3 3 tcK 17 CL 2 ROH 2 2 2 2 tcK 17 Micron NOTES 1 2 3 Di 10 11 12 13 14 All voltages referenced to Vss This parameter is samp
12. 1 TO T T2 T3 T4 T5 T6 T7 T8 T9 A tcH 4 4 4 4 4 4 tcks tcKH Z V Ul NOP XX Z tcMH M Z Z Z ZF Z Z Jom couv 2x tAH Z z Com MMMM X n tac TIMING PARAMETERS tac tHz tps toH Carmel y WED WWD 7E 75 8E SYMBOL MIN MAX MIN MAX MIN MAX UNITS 3 5 4 5 4 6 ns 2 5 4 6 6 ns tAH 0 8 0 8 1 ns tas 1 5 1 5 2 ns tCH 2 5 2 5 3 ns tcL 2 5 2 5 3 ns tcK 3 7 7 5 8 ns tcK 2 7 5 10 10 ns tcKH 0 8 0 8 1 ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 2 the CAS latency 3 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 128Mb x4 x8 x16 SDRAM 128MSDRAM_E p65 Rev E Pub 1 02 DON T CARE UNDEFINED 7 75 8E SYMBOL MIN MAX MIN MAX MIN MAX UNITS tCKS 1 5 1 5 2 ns tCMH 0 8 0 8 1 ns tcMS 1 5 1 5 2 ns tDH 0 8 0 8 1 ns tps 1 5 1 5 2 ns tHZ 3 5 4 5 4 6 ns tHZ 2 5 4 6 6 ns uz 1 1 1 ns tOH 3 3 3 ns 39 and auto precharge is disabled
13. 4 Interrupt Burst Precharge Idle i Internal tRP BANK n 2 BANK 1 La States BANK Page Active READ with Burst of 4 Precharge q Ree 1 k m mm mm mmm mm m mm mmm mm ADDRESS PA maza 1 l DQ U l Dour Dour Dour Dour 1 d 4 1 CAS Latency 3 BANK NOTE DQM is LOW lt CAS Latency 3 BANK Figure 24 READ With Auto Precharge Interrupted by a READ L4 L4 COMMAND FG H NOP X Nor NOP X NOP H NOP X i ee ee eer m BANK n READ with Burst of 4 Interrupt Burst Precharge Idle hi 1 Internal RP BANK n 8 BANK m 1 C ud States Page Active WRITE with Burst of 4 Write Back g Ls s s sms s ee ee lm ADDRESS ZZ M 1 777 DON NEE DADA DQ I N k 4 Md 1 M2 T CAS Latency 3 BANK NOTE 1 DQM is HIGH at 2 to prevent Dout a 1 from contending with Din d at T4 DON T CARE Figure 25 READ With Auto Precharge Interrupted by a WRITE 128Mb x4 x8 x16 SDRAM 2 128MSDRAM_E p65 Rev E Pub 1 02 6 Micron Technology Inc reserves
14. Latency 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 11 128Mb x4 x8 x16 SDRAM Operating Mode The normal operating mode is selected by setting M7 and MB to zero the other combinations of values for M7 and MB are reserved for future use and or test modes The programmed burst length applies to both READ and WRITE bursts Test modes and reserved states should not be used because unknown operation or incompatibility with fu ture versions may result Write Burst Mode When M9 0 the burst length programmed via M0 M2 applies to both READ and WRITE bursts when M9 1 the programmed burst length applies to READ bursts but write accesses are single location nonburst accesses Table 2 CAS Latency ALLOWABLE OPERATING FREQUENCY MHz CAS LATENCY 3 lt 143 lt 133 lt 125 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc d 128Mb x4 x8 x16 Micron 1 Commands Truth Table 1 provides a quick reference of available following the Operation section these tables provide commands This is followed by a written description of current state next state information each command Three additional Truth Tables appear TRUTH TABLE 1 COMMANDS AND DQM OPERATION Note 1 NAME FUNCTION CS RAS CAS WE DQM ADDR DQs NOTES COMMAND
15. Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc s 128Mb x4 x8 x16 qaicron AUTO REFRESH MODE teks tcKH tcMS tcMH COMMAND PRECHARGE NOP AUTO ACTIVE REFRESH ALL BANKS SINGLE BANK 5 x 5 Precharge all DON T CARE active banks TIMING PARAMETERS 75 8E MIN MAX MIN MAX UNITS 08 i ns 1 5 2 ns 2 5 3 ns 2 5 3 ns 7 5 8 ns 10 10 CAS latency indicated in parentheses NOTE 1 Each AUTO REFRESH command performs a refresh cycle Back to back commands are not required 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change produc cific without notice 128MSDRAM_E p65 Rev E Pub 1 02 40 2001 a n Te chnology Inc r 128Mb x4 x8 x16 qaicron SELF REFRESH MODE TO T1 T2 Tn 4 1 1 2 tc Fette dr i teks 2 tRAS min lt CKE A SA tcks tems COMMAND XX Z A e z or COMMAND AUTO INHIBIT REFRESH ALL BANKS vo X MINIMA as AH Bao Bat X wa 77777 LLL LLL DQ High Z y 6 tgp KSR Precharge all Enter self refresh mode Exit self refresh mode active banks R
16. earliest valid stage within a burst The user must not issue another command to the same bank until the precharge time is completed This is determined as if an explicit PRECHARGE command was issued at the earliest possible time as described for each burst type in the Operation section of this data sheet BURST TERMINATE The BURST TERMINATE command is used to trun cate either fixed length or full page bursts The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated as shown in the Operation section of this data sheet Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS BEFORE RAS CBR REFRESH in conventional DRAMs This command is nonpersistent so it must be issued each time a refresh is required All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command The AUTO REFRESH command should not be issued until the minimum has been met after the PRECHARGE command as shown in the operation sec tion The addressing is generated by the internal refresh controller This makes the address bits Don t Care duringan AUTO REFRESH command The 122Mb SDRAM requires 4 096 AUTO REFRESH cycles every 64ms regardless of width option Providing distributed AUTO REFRESH comman
17. last desired data element of a longer burst TO T1 T2 FII 1 BURST NEXT COMMAND WRITE TERMINATE COMMAND ADDRESS 4 00 S Y DATA gt Figure 19 Terminating a WRITE Burst CLK WLLL Lp o ZDK Bank Selected Figure 20 PRECHARGE Command A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 128Mb x4 x8 x16 SDRAM 128MSDRAM_E p65 Rev E Pub 1 02 128Mb x4 x8 x16 SDRAM PRECHARGE The PRECHARGE command see Figure 20 is used to deactivate the open row in a particular bank or the open row inall banks The bank s will be available for a subse quent row access some specified time after the PRECHARGE command is issued Input A10 determines whether one or all banks are to be precharged and in the case where only one bank is to be precharged inputs BAO BAI select the bank When all banks are to be precharged inputs BAO BAI are treated as Don t Care Once a bank has been precharged it is in the idle state and must be activated prior to any READ or WRITE com mands being issued to that bank POWER DOWN Power down occurs if CKE is registered LOW coinci dent with a NOP or COMMAND INHIBIT when no ac cesses are in progress If power down occurs when all banks are idle this mode is referred to as precharge power down if power down occu
18. ns tAC 2 5 4 6 6 ns tcMS 1 5 1 5 2 ns tAH 0 8 0 8 1 ns tHz 3 5 4 5 4 6 ns tas 1 5 1 5 2 ns tHz 2 5 4 6 6 ns tCH 2 5 2 5 3 ns uz 1 1 1 ns 2 5 2 5 3 ns tOH 3 3 3 ns 3 7 7 5 8 ns tRAS 37 120 000 44 120 000 50 120 000 ns 2 7 5 10 10 ns tRC 60 66 70 ns tCKH 0 8 0 8 1 ns tRCD 15 20 20 ns tcks 1 5 1 5 2 ns tRP 15 20 20 ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 1 and the CAS latency 2 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 3 READ command not allowed else tRAS would be violated 128Mb x4 x8 x16 SDRAM 128MSDRAM_E p65 Rev E Pub 1 02 45 Micron Technology Inc re serves the right to change products or specifications without notice 2001 Micron Technology Inc 128Mb x4 x8 x16 qaicron ALTERNATING BANK READ ACCESSES TO T1 T2 T3 T4 T5 T6 T7 T8 tcL CLK m Pi P e 4 4 4 i xe TF Z VE WW WW COMMAND y ACTIVE XX NOP XX READ XX NOP XX ACTIVE XX NOP XX READ XX NOP x ACTIVE xZ vovi bow ZZ D 70 D 10 lt X w 5277700770 EX v 0 tas tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE lt JC row XU DB DTI em XL tas
19. of a longer burst Following the PRECHARGE command a subsequent command to the same bank cannot beissued until RP is met Note that part of the row precharge time is hidden during the access of the last data element s In the case of a fixed length burst being executed to completion aPRECHARGE command issued at the opti mum time as described above provides the same op eration that would result from the same fixed length burst with auto precharge The disadvantage of the COMMAND 4 READ z noe wor ae NOP vw Y X ADDRESS Cer LINDA LA E f En Es APA sone emn Za U CAS Latency 3 NOTE DQM is LOW DON T CARE Figure 11 READ to PRECHARGE 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 20 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc 128Mb x4 x8 x16 cron PRECHARGE command is that it requires that the com mand and address buses be available at the appropriate time to issue the command the advantage of the PRECHARGE command is thatit can be used to truncate fixed length or full page bursts Full page READ bursts can be truncated with the BURST TERMINATE command and fixed length READ bursts may be truncated with a BURST TERMINATE com mand provided that auto precharge was not activated The BURST TER
20. specifications without notice 2001 Micron Technology Inc 128Mb x4 x8 x16 qaicron PIN DESCRIPTIONS TSOP PIN NUMBERS SYMBOL DESCRIPTION 38 CLK Clock CLK is driven by the system clock All SDRAM input signals are sampled on the positive edge of CLK CLK also increments the internal burst counter and controls the output registers Clock Enable CKE activates HIGH and deactivates LOW the CLK signal Deactivating the clock provides PRECHARGE POWER DOWN and SELF REFRESH operation all banks idle ACTIVE POWER DOWN row active in any bank or CLOCK SUSPEND operation burst access in progress CKE is synchronous except after the device enters power down and self refresh modes where CKE becomes asynchronous until after exiting the same mode The input buffers including CLK are disabled during power down and self refresh modes providing low standby power CKE may be tied HIGH Chip Select CS enables registered LOW and disables registered HIGH the command decoder All commands are masked when CS is regis tered HIGH CS provides for external bank selection on systems with multiple banks CS is considered part of the command code 16 17 18 WE CASH Command Inputs WE CAS and RAS along with CS define the RAS command being entered 39 x4 x8 DQM Input Output Mask DQM is an input mask signal for write accesses and an output enable signal for read accesses Input data is masked when x16 DQML DQM i
21. x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 3 1 2001 Micron Technology Inc 7 128Mb x4 x8 x16 Macron SDRAM NOTE continued 4 AUTO REFRESH SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle 5 A BURST TERMINATE command cannot be issued to another bank it applies to the bank represented by the current state only 6 All states and sequences not shown are illegal or reserved 7 READs or WRITEs to bank m listed in the Command Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled 8 CONCURRENT AUTO PRECHARGE Bank n will initiate the auto precharge command when its burst has been interrupted by bank m s burst 9 Burst in bank n continues as initiated 10 For a READ without auto precharge interrupted by a READ with or without auto precharge the READ to bank m will interrupt the READ on bank n CAS latency later Figure 7 11 For a READ without auto precharge interrupted by a WRITE with or without auto precharge the WRITE to bank m will interrupt the READ on bank n when registered Figures 9 and 10 DOM should be used one clock prior to the WRITE command to prevent bus contention 12 For a WRITE without auto precharge interrupted by a READ with or without auto precharge the READ to bank m will interrupt the WRITE
22. 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 12 34 5 6 7 0 1 0 3 2 5 4 7 6 1 O 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 Ful 11 9 C Cn 1 Cn 2 Page Cana C Not Supported y location 0 y NOTE 1 For full page accesses 2 048 4 1 024 x8 y 512 x16 For a burst length of two A1 A9 A11 x4 A1 A9 x8 or A1 A8 x16 select the block of two burst AO selects the starting column within the block For a burst length of four A2 A9 A11 x4 A2 A9 x8 or A2 A8 x16 select the block of four burst 1 select the starting column within the block For a burst length of eight A3 A9 A11 x4 A3 A9 x8 or A3 A8 x16 select the block of eight burst AO A2 select the starting column within the block For a full page burst the full row is selected and A0 A9 A11 x4 A0 A9 x8 or 8 x16 select the starting column Whenever a boundary of the block is reached within a given sequence above the following access wraps within the block For a burst length of one A0 A9 A11 x4 A0 A9 x8 or AO A8 x16 select the unique column to be accessed and mode register bit M3 is ignored Micron Technology Inc reserves the right to change products or s
23. 5 mcum 133 MHz EN gt Ans 1 5ns 0 8ns 2 Off center parting line 125 MHz 2ns Ins 3 Consult Micron for availability L3 100 MHz EMEN 0 8ns 4 Not recommended for new designs 8 3 45 100 MHz m ns ins 5 Shown for PC100 compatability 6 See page 59 for FBGA Device Marking Table CL CAS READ latency 128Mb x4 x8 x16 SDRAM 1 Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 2001 Micron Technology Inc PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE s 128Mb x4 x8 x16 qvicron FBGA BALL ASSIGNMENT Top View 32 Meg x 4 16 Meg x 8 8 x 16mm and 11 x 13mm 8 x 16mm 11 x 13mm 1 2 3 4 5 6 8 1 2 8 4 5 6 Ti 8 Ce 1E 1E 1E ed E es 1E 1E IL 1E Eel ee x z z 5 A A Uv z ir A Q m w gt v 2 x a m gt gt Depopulated Balls Depopulated Balls 128Mb x4 x8 x16 SDRAM 2 Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 2001 Micron Technology Inc Micron 128Mb SDRAM PART NUMBERS PART NUMBER ARCHITECTURE MT48LC32M4A2TG 32 Meg x4 MT48LC32M4A2FC 32 Meg x4 MT48LC32M4A2FB 32 Meg x4 MT48LC16M8A2TG 16 Meg x8 MT48LC16M8A2FC 16 Meg x8 MT48LC16M8A2FB 16 Meg x8
24. 5 2 ns ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 1 the CAS latency 2 and the READ burst is followed by a manual PRECHARGE 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 3 PRECHARGE command not allowed or RAS would be violated 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 44 2001 Micron Technology Inc Micron 128Mb x4 x8 x16 SDRAM SINGLE READ WITH AUTO PRECHARGE teks Ul Ul Ul Ul 7 Ul Ul Uy tcMs COMMAND ACTIVE NOP XX XX READ YOK ACTIVE X NOP X7 77 pam cama Z Z lt E A0 A9 A11 R w Xe Z WN on wo X lt SCL gt BAO BAI X BANK x W YW X BANK X7 o DQ RCD CAS Latency tuz tRAS tRC DON T CARE RA UNDEFINED TIMING PARAMETERS 7E 75 8E 7E 75 8E SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS tAC 3 5 4 5 4 6 ns tCMH 0 8 0 8 1
25. 8 DOM i iow ns Latency 3 BANK m g sil is Figure 26 WRITE With Auto Precharge Interrupted by a READ TO T1 T2 T3 T4 5 T6 T7 OC ou 1 1 l l l COMMAND wo WRTA wor V nos Bac e y C9 H so X H T T T om s wow ws m ls EUER aG EUROS E EROR SUR EORR BANK n Page Active WRITE with of4 Interrupt Burst Write Back Precharge Internal LWR BANK n JRP BANK n Stat i EET Page Active WRITE with Burst of 4 Write Back d BANK m DQ pa rim h po h on on Va 1 2 WU 1 2 d 3 NOTE 1 DQM is LOW DON T CARE Figure 27 WRITE With Auto Precharge Interrupted by a WRITE 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 27 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron TRUTH TABLE 2 128Mb x4 x8 x16 SDRAM Notes 1 4 CKE 1 CKE CURRENT STATE COMMAND ACTION NOTES L L Power Down X Maintain Power Down Self Refresh X Maintain Self Refresh Clock Suspend X Maintain Clock Suspend L H Power Down COMMAND INHIBIT or NOP Exit Power Down 5 Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6 Clock Suspend X Exit Clock Suspend 7 H L All Banks Idle COMMAND INHIBIT or NOP Power Down Entry All Banks Idle AUTO REFRESH Self Refresh
26. CKE HIGH RAS I 2 ve TI A0 A9 A11 x4 A0 A8 x16 y ADDRESS A9 A11 x16 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE I BANK 7777 DX ses 8 Figure 5 READ Command 128Mb x4 x8 x16 SDRAM 128MSDRAM_E p65 Rev E Pub 1 02 128Mb x4 x8 x16 SDRAM Upon completion ofa burst assuming no other com mands have been initiated the DQs will go High Z A full page burst will continue until terminated At the end of the page it will wrap to column 0 and continue Data from any READ burst may be truncated with a subsequent READ command and data from a fixed length READ burst may be immediately followed by data from a READ command In either case a continuous flow of data can be maintained The first data element from the new burst follows either thelast element of a completed burst or the last desired data element of a longer burst that is being truncated The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid where x equals the CAS latency minus one TO T T2 T8 SEE i i 4 COMMAND X READ XX NOP XX NOP M tow DQ Dour tAC CAS Latency 2 TO Ti T2 T3 T4 CLK i COMMAND ZX READ NOP NOP H uz to dz Dour e tAC gt CAS Latency 3 DQ DON
27. CTRICAL CHARACTERISTICS AND OPERATING CONDITIONS Notes 1 5 6 notes appear on page 36 Vpp VppQ 3 3V 0 3V PARAMETER CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage 3 36 V Input High Voltage Logic 1 Allinputs 2 v Input Low Voltage Logic 0 Allinputs w v Input Leakage Current 5 5 Any input OV lt Vin lt Vpp All other pins not under test OV Output Leakage Current DQs are disabled OV lt Vout lt VoL 0 4 V Output High Voltage lout 4mA Output Low Voltage lout 4mA Ipp SPECIFICATIONS AND CONDITIONS Notes 1 5 6 11 13 notes appear on page 36 Vpp VpbQ 3 3V 0 3V MAX bia Ras Bea NOTES Operating Current Active Mode 3 18 Burst 2 READ or WRITE RC MIN 19 32 Standby Current Power Down Mode 32 All banks idle CKE LOW Standby Current Active Mode 3 12 CKE HIGH CS HIGH banks active after tRCD met 19 32 PARAMETER CONDITION No accesses in progress Operating Current Burst Mode Continuous burst 3 18 READ or WRITE All banks active 19 32 Auto Refresh Current tRFC MIN 3 12 CKE HIGH CS HIGH 15 6255 18 19 Self Refresh Current CKE lt 0 2V Standard 1207 2 2 2 4 Low power L 1207 1 1 1 128Mb x4 x8 x16 SDRAM 128MSDRAM_E p65 Rev E Pub 1 02 3 3 Micron Technology
28. DRAM E p65 Rev E Pub 1 02 53 2001 Micron Technology Inc 128Mb x4 x8 x16 qaicron WRITE FULL PAGE BURST x Perea PLLA Um AKAK 47 ar a commano X nerve JC so QC wan QC e OQ or 0X nor DUX o ose n LE HD m LI vo I TL BD OO vos TED II a CE mimi Full page burst does not 512 x16 locations within same row self terminate Can use 1 024 x8 locations within same row BURST TERMINATE 2 048 x4 locations within same row command to stop 2 3 Full page completed 2 DON T CARE TIMING PARAMETERS 7 75 8E 7E 75 8E SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS tAH 0 8 0 8 1 ns CKS 1 5 1 5 2 ns tas 1 5 1 5 2 ns tCMH 0 8 0 8 1 ns tcH 2 5 2 5 3 ns tcMS 1 5 1 5 2 ns tcL 2 5 2 5 3 ns tDH 0 8 0 8 1 ns 3 7 75 8 ns tps 1 5 1 5 2 ns tCK 2 7 5 10 10 ns RCD 15 20 20 ns tCKH 0 8 0 8 1 ns CAS latency indicated in parentheses NOTE 1 x16 A9 and A11 Don t Care x8 A11 Don t Care 2 WR must be satisfied prior to PRECHARGE command 3 Page left open no 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without noti
29. Entry Reading or Writing VALID Clock Suspend Entry H H See Truth Table 3 NOTE provided that CKS is met CKE is the logic state of CKE at clock edge n CKE was the state of CKE at the previous clock edge Current state is the state of the SDRAM immediately prior to clock edge n COMMAND is the command registered at clock edge n and ACTION is a result of COMMAND All states and sequences not shown are illegal or reserved Exiting power down at clock edge n will put the device in the all banks idle state in time for clock edge n 1 Exiting self refresh at clock edge n will put the device in the all banks idle state once XSR is met COMMAND INHIBIT NOP commands should be issued on any clock edges occurring during the XSR period A minimum of two NOP commands must be provided during XSR period clock edge n 7 128Mb x4 x8 x16 SDRAM 28 Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 After exiting clock suspend at clock edge n the device will resume operation and recognize the next command at 2001 Micron Technology Inc Micron 128Mb x4 x8 x16 SDRAM TRUTH TABLE 3 CURRENT STATE BANK COMMAND TO BANK Notes 1 6 notes appear below and on next page CURRENT STATE CS RAS CAS WE COMMAND ACTION NOTES Any H x x x C
30. GE BURST TO Ti T2 T3 T4 T5 T6 q T Tn 2 Tn 3 Tn 4 T lt 4 4 4 4 4 4 4 tcks lt FTU Ul Ul WW tcMS yx ACTIVE NOP tcMs AX NOP Burst re RCD tz CAS Latency 512 x16 locations within same row 1 024 x8 locations within same row 2 048 x4 locations within same row Full page completed E conta ls Ls 40 20 oon a VOT eT TTI LI YT CL so VOI LLL LL va our m 1 tuz DON T CARE CAS latency indicated in parentheses NOTE 1 For this example the CAS latency 2 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 3 Page left open 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 47 Full page burst does not self terminate w UNDEFINED Can use BURST TERMINATE command TIMING PARAMETERS 7E 75 8E 7E 75 8E SYMBOL MNI MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MIN MAX UNITS tac 3 5 4 5 4 6 ns tCKS 1 5 1 5 2 ns tAC 2 5 4 6 6 ns tcMH 0 8 0 8 1 ns tAH 0 8 0 8 1 ns tc
31. INHIBIT NOP H X X X X X X NO OPERATION NOP L H H H X X X ACTIVE Select bank and activate row L L H H X Bank Row X 3 READ Select bank and column and start READ burst L H L H L H8 Bank Col X 4 WRITE Select bank and column and start WRITE burst L H L L UH Bank Col Valid 4 BURST TERMINATE L H H L X X Active PRECHARGE Deactivate row in bank or banks L L H L X Code X 5 AUTO REFRESH or SELF REFRESH L L L H X X X 6 7 Enter self refresh mode LOAD MODE REGISTER L L L L X Op Code X Write Enable Output Enable L Active Write Inhibit Output High Z H High Z NOTE 1 CKE is HIGH for all commands shown except SELF REFRESH 2 A0 A11 define the op code written to the mode register 3 A0 A11 provide row address and BAO BA1 determine which bank is made active 4 A0 A9 11 x4 A0 A9 x8 or A0 A8 x16 provide column address A10 HIGH enables the auto precharge feature nonpersistent while A10 LOW disables the auto precharge feature BAO BA1 determine which bank is being read from or written to 5 A10 LOW BAO BA1 determine the bank being precharged A10 HIGH banks precharged and BAO 1 are Don t Care 6 This command is AUTO REFRESH if CKE is HIGH SELF REFRESH if CKE is LOW 7 Internal refresh counter controls row addressing all inputs and I Os are Don t Care except for 8 Activates or deactivates the DQs during WRITEs zero clock delay and READs two clock delay 128Mb x4 x8
32. IONS MARKING 007 mi 13 42 wa NC Configurations NC NCDQML 15 40 NC 32Meg x4 8Meg 4 x4banks 32M4 Se 16 x8 4 8 x4banks 16M8 pes 15 of 8 Meg x16 2 Meg x16 x4 banks 8M16 BAO EH 20 35 11 BAI 21 34 H ag WRITE Recovery WR a A 22 A8 WR 2 CLK A2 A0 23 32 A7 A1 24 Er A6 Package Pinout A2 Hmm 25 Er A5 Plastic Package OCPI gt m a 54 pin TSOP II 400 mil TG N 60 ball FBGA 8mm x 16mm 35 Note The symbol indicates signal is active LOW A dash 60 ball FBGA 11mm x 13mm FC 36 indicates x8 and x4 pin function is same as x16 pin function Timing Cycle Time 32 Meg x 4 16 Meg x 8 8 Meg x 16 10ns CL 2 PC100 8E 35 Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks 7 5ns CL 3 PC133 75 Refresh Count 4K 4K 4K 7 5ns CL 2 PC133 7E Row Addressing 4K A0 A11 4K A0 A11 4K A0 A11 Self Refresh Bank Addressing 4 BAO 4 BAO BA1 4 BAO BA1 ET REIES Column Addressing 2K A0 A9 A11 1K A0 A9 512 A0 A8 Standard None Low power L KEY TIMING PARAMETERS Operating Temperature Range Commercial 0 C to 70 C None iLAN 5 3 ACCESS TIME HOLD Industrial 40 C to 85 C IT GRADE FREQUENCY TIME Part Number Example 0 8ns MT48LC16M8A2TG 7E L issunz p saw ism um NOTE 1 Refer to Micron Technical Note TN 48 0
33. Inc Micron 128Mb x4 x8 x16 SDRAM READ WITH AUTO PRECHARGE T2 tcL T3 T4 5 T8 tH u Z Z Z Z COMMAND ACTIVE tcMS DQM DQML DQMH WM tcMH Z A0 A9 A11 X ROW x Xcowu MN lt ENABLE AUTO wo X BA0 BA1 X BANK ZZ ZZ XU __tac to toH uu aon Dout m 3 tHZ DQ uTm 2 RCD CAS Latency tRAS E tRC DON T CARE RX UNDEFINED TIMING PARAMETERS 7E 75 8E 7E 75 8E SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS tac 3 5 4 5 4 6 ns tCMH 0 8 0 8 1 ns tAC 2 5 4 6 6 ns tcMS 1 5 1 5 2 ns 0 8 0 8 1 ns tHZ 3 5 4 5 4 6 ns tAS 1 5 1 5 2 ns tHZ 2 5 4 6 6 ns CH 2 5 2 5 3 ns uz 1 1 1 ns 2 5 2 5 3 ns 3 3 3 ns tcK 3 7 75 8 ns 37 120000 44 120 000 50 120 000 ns tcK 2 7 5 10 10 ns tRC 60 66 70 ns tCKH 0 8 0 8 1 ns RCD 15 20 20 ns tcKs 1 5 1 5 2 ns tRP 15 20 20 ns CAS latency indicated in parentheses NOTE 1 For this example the b
34. Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron CAPACITANCE Note 2 notes appear on page 36 128Mb x4 x8 x16 SDRAM PARAMETER TSOP TG Package SYMBOL MIN MAX UNITS NOTES Input Capacitance CLK 2 5 3 5 pF 29 Input Capacitance All other input only pins Ci2 2 5 3 8 pF 30 Input Output Capacitance DQs Cio 4 0 6 0 pF 31 PARAMETER FBGA FB Package Input Capacitance CLK Input Capacitance All other input only pins Input Output Capacitance DQs AC OPERATING CONDITIONS Notes 5 6 8 9 11 notes appear on page 36 35 E PARAMETER _ SYMBOL MIN MAX MAX MIN MAX UNITS NOTES Access time from CLK pos edge CL 3 3 5 4 5 4 6 ns 27 sa s 6 m aadress hodim 08 ns Address setup time tAS ns CLK high level width CH ns ns Clock cycle time CL 3 tcK 3 ns 23 0 m 23 98 ns ns CSS RAS CASE WER DOM holdtime MH 08 08 ns ns Data in hold time DH 0 8 0 8 1 ns ng Data out high impedance time 3 1 2 3 54 54 6 ns 10 ns ns E m 28 720 000 ns ACTIVE to ACTIVE command period amp 66 m ng ns Refresh period 4096 WE Ja a 5 AUTO REFRESH period leo 7 ns
35. K DIAGRAM 8 Meg x 16 SDRAM Sen ee ee ee ee ee a H LI H LI H LI E LI H LI H LI H E LI H r L x gt H H H H CONTROL H gu LOGIC wes Za 4 29 BANK3 cast 66 5 BANK2 1 RAS yd 1 1 4 H LI B H K REFRESH 15 MODE REGISTER COUNTER I ROW 12 ADDRESS BANKO 12 MUX MEMORY 2 2 O lt DOML 12 4 096 x 512 x 16 1 DQMH 1 t n i 1 SENSE AMPLIFIERS N DATA 16 OUTPUT 4096 REGISTER H lt H 2 GATING 16 DQo DQM MASK LOGIC L 2015 A BANK READ DATA LATCH A11 7a ADDRESS MMC CONTROL WRITE DRIVERS BAO 1 REGISTER LOGIC DATA h 2 16 INPUT 1 lt gt Po 512 REGISTER NN i116 i p H COLUMN 1 DECODER COLUMN ADDRESS 9 H 9 COUNTER LATCH H x H H H H H i H H H H H 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 Micron Technology Inc reserves the right to change products or
36. MINATE command should be issued x cycles before the clock edge at which the last desired data element is valid where x equals the CAS latency minus one This is shown in Figure 12 for each possible CAS latency data element n 3 is the last desired data ele ment of a longer burst I I I I soo LAL pem ise DQ Eo Dour Dour Dour n 1 n 2 n 3 I CAS Latency 2 BURST COMMAND C READ NOP K NOP M ind Meter A NOP M NOP M ind M 2 cycles sus HE CMC iC DQ CAS Latency 3 NOTE DQM is LOW DON T CARE Figure 12 Terminating a READ Burst 128Mb x4 x8 x16 SDRAM 128MSDRAM_E p65 Rev E Pub 1 02 Micron Technology Inc s the right to change produc cific without notic 082001 a n Tecinolo inc Micron WRITEs WRITE bursts are initiated with a WRITE command as shown in Figure 13 The starting column and bank addresses are pro vided with the WRITE command and auto precharge is either enabled or disabled for that access If auto precharge is enabled the row being accessed is precharged at the completion of the burst For the ge neric WRITE commands used in the following illustra tions auto precharge is disabled During WRITE bursts the first valid data in element will be registered coincident with the WRITE command Subsequent data elements will be re
37. MS 1 5 1 5 2 ns tas 1 5 1 5 2 ns tHZ 3 5 4 5 4 6 ns 2 5 2 5 3 ns tHZ 2 5 4 6 6 ns tcL 2 5 2 5 3 ns uz 1 1 1 ns tcK 3 7 7 5 8 ns toH 3 3 3 ns tcK 2 7 5 10 10 ns tRCD 15 20 20 ns tcKH 0 8 0 8 1 ns Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron CLK COMMAND 128Mb x4 x8 x16 SDRAM READ DQM OPERATION TO T1 T2 T3 T4 T5 T6 T7 T8 tcL 4 d 7 VU lt CT CT TT WW CMS tcMH ACTIVE NOP READ XX NOP XX NOP XX NOP XX NOP XX NOP XX NOP x tcMS tcMH nov sa Jon sm ZZ soo eni X w S E tac i s I DON T CARE RA UNDEFINED TIMING PARAMETERS Mol MIN MIN MAK MIN S M MAX MAX a a tea tas x tas 15 15 2 ns tHZ 3 5 4 5 4 6 ns 25 x F 3 7 75 8 ns tOH 3 3 3 ns e os T 5 RCD 15 20 20 ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 4 and the CAS latency 2 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 128
38. MT48LC8M16A2TG 8 Meg x 16 See page 59 for FBGA Device Marking Table GENERAL DESCRIPTION The Micron 128Mb SDRAM is a high speed CMOS dynamicrandom access memory containing 134 217 728 bits It is internally configured as a quad bank DRAM with asynchronous interface all signals registered on the positive edge of the clocksignal CLK Each ofthe x4 s 33 554 432 bit banks is organized as 4 096 rows by 2 048 columns by 4 bits Each of the x8 s 33 554 432 bit banks is organized as 4 096 rows by 1 024 columns by 8 bits Each of the x16 s 33 554 432 bit banks is organized as 4 096 rows by 512 columns by 16 bits Read and write accesses to the SDRAM are burst ori ented accesses start at a selected location and continue for a programmed number oflocations in a programmed sequence Accesses begin with the registration of an AC TIVE command which is then followed by a READ or WRITE command The address bits registered coinci dent with the ACTIVE command are used to select the bank and row to be accessed BAI select the bank 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 128Mb x4 x8 x16 SDRAM 0 11 select the row The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access The SDRAM provides for programmable READ or WRITE burst lengths of 1 2 4 or 8 locations or the full page with a burst terminate
39. Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 48 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc 128Mb x4 x8 x16 qaicron WRITE WITHOUT AUTO PRECHARGE LL FI T UT UT w 4 SHE Jod QC m OX m XC m rese or XX acme XT cone ons Z TE JD T MM fom Z Q II 7 DON T CARE TIMING PARAMETERS 75 8E 7E 75 8E SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS 0 8 1 ns tcMS 1 5 1 5 2 ns 1 5 2 ns tDH 0 8 0 8 1 ns 2 5 3 ns tps 1 5 1 5 2 ns 2 5 3 ns RAS 37 120 000 44 120 000 50 120 000 ns 7 5 8 ns tRC 60 66 70 ns 10 10 ns tRCD 15 20 20 ns 0 8 1 ns 15 20 20 ns 1 5 2 ns twR 14 15 15 ns 0 8 1 ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 4 and the WRITE burst is followed by a manual PRECHARGE 2 15ns is required between lt Din m 3 gt and the PRECHARGE command regardless of frequency 3 x16 A9 and A11 Don t Care x8 A11 Don t Ca
40. OMMAND INHIBIT NOP Continue previous operation L H H H NO OPERATION NOP Continue previous operation L L H H ACTIVE Select and activate row Idle L L L H AUTO REFRESH L L L L LOAD MODE REGISTER 7 L L H L PRECHARGE 11 L H L H READ Select column and start READ burst 10 Row Active L H L L WRITE Select column and start WRITE burst 10 L L H L PRECHARGE Deactivate row in bank or banks 8 Read L H L H READ Select column and start new READ burst 10 Auto L H L L WRITE Select column and start WRITE burst 10 Precharge L L H L PRECHARGE Truncate READ burst start PRECHARGE 8 Disabled L H H L BURST TERMINATE 9 Write L H L H READ Select column and start READ burst 10 Auto L H L L WRITE Select column and start new WRITE burst 10 Precharge L L H L PRECHARGE Truncate WRITE burst start PRECHARGE 8 Disabled L H H L BURST TERMINATE 9 NOTE 1 This table applies when CKE was HIGH and CKE is HIGH see Truth Table 2 and after XSR has been met if the previous state was self refresh 2 This table is bank specific except where noted i e the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state Exceptions are covered in the notes below 3 Current state definitions Idle Row Active Read Write The bank has been precharged and RP has been met A row in the bank has been activated and RCD has been met No data bursts accesses and no regi
41. PRECHARGE NOP x Kor NOP b XX NOP XX ACTIVE XX w DD MMM MMM DD I e DD e X t ALLBANKS As ML K DI C MEL OE pq Lg ne 100 1 t t t t MIN EN RFC ap RD MRD Power up and N AUTO REFRESH N AUTO REFRESH N Program Mode Register gt 3 4 CLK stable all banks DON T CARE TIMING PARAMETERS 7E 75 8E 7E 75 8 SYMBOL MIN MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS tAH 0 8 0 8 1 ns tcKS 1 5 1 5 2 ns tas 1 5 1 5 2 ns tCMH 0 8 0 8 1 ns tCH 2 5 2 5 3 ns tcMS 1 5 1 5 2 ns tcL 2 5 2 5 3 ns tMRD3 2 2 2 tcK tcK 3 7 7 5 8 ns tRFC 66 66 70 ns tcK 2 7 5 10 10 ns tRP 15 20 20 ns tcKH 0 8 0 8 1 ns CAS latency indicated in parentheses NOTE 1 If CS is HIGH at clock HIGH time all commands applied are NOP with CKE a Don t Care 2 The mode register may be loaded prior to the AUTO REFRESH cycles if desired 3 JEDEC and PC100 specify three clocks 4 Outputs are guaranteed High Z after command is issued 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM_E p65 Rev E Pub 1 02 37 2001 Micron Technology Inc
42. RITE M wm mH vr H BANK BANK BANK 7 ADDRESS x SEXES NOTE Each WRITE command may be to any bank DQM is LOW Figure 16 Random WRITE Cycles TO T1 T2 T3 T4 T5 quu o Le Xenon pete Z VUDU 24 Z M The WRITE command may be to any bank and the READ command may be to any bank DQM is LOW CAS latency 2 for illustration COMMAND 4 ae M NOP X l l BANK COLn TANG ADDRESS 4 I l Din Dx DQ 4 n n 1 Figure 17 WRITE to READ 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 128Mb x4 x8 x16 SDRAM least one clock plus time regardless of frequency In addition when truncating a WRITE burst the DQM signal must be used to mask input data for the clock edge prior to and the clock edge coincident with the PRECHARGE command An example is shown in Figure 18 Data 1 is either the last of a burst of two or the last desired of a longer burst Following the PRECHARGE command a subsequent command to the same bank cannot be issued until is met In the case of a fixed length burst being executed to completion a PRECHARGE command issued at the opti mum time as described above provides the same op eration that would result from the same fixed length burst with auto precharge The disadvantage of the PRECHARGE command is that it requires that the com man
43. Row W t t have aul ALL BANKS X TTD YUM ZZ NK x tas tay DISABLE AUTO PRECHARGE SINGLE BANKS BAO BA1 x BANK BANK YY 00 YY TK BANKS 977777 YJ BANK WJ tac tac tac tac toH toH toH toH DQ uz Dour m 1 Dour m42 Dour m43 RCD CAS Latency tgp tRAS 2 tRC 2 DON T CARE W UNDEFINED TIMING PARAMETERS 7E 75 8E 7E 75 8E SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS tAC 3 5 4 5 4 6 ns tcMH 0 8 0 8 1 ns tAC 2 5 4 6 6 ns tcMS 1 5 1 5 2 ns tAH 0 8 0 8 1 ns tHZ 3 5 4 5 4 6 ns tas 1 5 1 5 2 ns tHZ 2 5 4 6 6 ns tcH 2 5 2 5 3 ns uz 1 1 1 ns 2 5 2 5 3 ns tOH 3 3 3 ns tcK 3 7 75 8 ns tRAS 37 120 000 44 120 000 50 120 000 ns tcK 2 7 5 10 10 ns tRC 60 66 70 ns tcKH 0 8 0 8 1 ns tRCD 15 20 20 ns tCKS 1 5 1 5 2 ns 15 20 20 ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 4 the CAS latency 2 and the READ burst is followed by a manual PRECHARGE 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 128Mb x4 x8 x16 SDRAM 2 Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 4 2001 Micron Technology
44. S G coun DON T CARE Figure 23 Clock Suspend During READ Burst Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron CONCURRENT AUTO PRECHARGE An access command READ or WRITE to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs unless the SDRAM supports CONCURRENT AUTO PRECHARGE Micron SDRAMs support CONCURRENT AUTO PRECHARGE Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below READ with Auto Precharge 1 Interrupted by a READ with or without auto precharge A READ to bank m will interrupt a READ on bank n CAS latency later The PRECHARGE to 128Mb x4 x8 x16 SDRAM bank n will begin when the READ to bank m is regis tered Figure 24 Interrupted by a WRITE with or without auto precharge A WRITE to bank m will interrupt a READ on bank n when registered DQM should be used two clocks prior to the WRITE command to prevent bus contention The PRECHARGE to bank n will begin when the WRITE to bank m is registered Figure 25 READ AP READ AP COMMAND Nor M BANKn NOR X BANK m T T T T y Cc Ce ye a T m m M i J m BANK Page Active READ with Burst of
45. T CARE UNDEFINED Figure 6 CAS Latency Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc 128Mb x4 x8 x16 4Micron This is shown in Figure 7 for CAS latencies of two and ture A READ command can be initiated on any clock three data element 3is either the last ofa burst of four cycle following a previous READ command Full speed or the last desired of a longer burst The 128Mb SDRAM random read accesses can be performed to the same uses a pipelined architecture and therefore does not bank as shown in Figure 8 or each subsequent READ require the 2n rule associated with a prefetch architec may be performed to a different bank TO T1 T2 T3 T4 T5 T6 a j L LF LE LG LE Lo I I COMMAND READ NOP NOP NOP READ NOP NOP l X 1 cycle 9 rH CAS Latency 2 TO T1 T2 T3 T4 T5 T6 T7 a i1 L4 L4 L4 L4 COMMAND READ NOP NOP NOP READ NOP NOP NOP I I I I I I I X 2 cycles I ADDRESS WU DD DD UA CAS Latency 3 NOTE Each READ command may be to any bank DQM is LOW DON T CARE Figure 7 Consecutive READ Bursts 128Mb x4 x8 x16 SDRAM 1 7 Micron Technology Inc
46. TIVE command are used to select the bank and row to be accessed BAO and BAI select the bank A0 11 select the row The address bits x4 A0 A9 A11 x8 A0 A9 x16 A0 A8 registered coincident with the READ or WRITE command are used to select the starting col umn location for the burst access Priorto normal operation the SDRAM must be initial ized The following sections provide detailed informa tion covering device initialization register definition command descriptions and device operation Initialization SDRAMs must be powered up and initialized in a predefined manner Operational procedures other than those specified may result in undefined operation Once power is applied to Vpp and VppQ simultaneously and the clock is stable stable clock is defined as a signal cycling within timing constraints specified for the clock the SDRAM requires 100 delay prior to issuing any command other than a COMMAND INHIBIT or NOP Starting at some point during this 1001 period and con tinuing at least through the end of this period COM MAND INHIBIT or NOP commands should be applied Once the 100us delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied aPRECHARGE command should be applied All banks must then be precharged thereby placing the device in the all banks idle state Once in the idle state two AUTO REFRESH cycles must be performed After the AUTO REFRESH cycles are comp
47. a WRITE with auto precharge interrupted by a WRITE with or without auto precharge the WRITE to bank m will interrupt the WRITE on bank n when registered The PRECHARGE to bank n will begin after WR is met where WR begins when the WRITE to bank m is registered The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m Figure 27 128Mb x4 x8 x16 SDRAM 2 Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 3 2001 Micron Technology Inc Micron ABSOLUTE MAXIMUM RATINGS Voltage on Vpp VppQ Supply 128Mb x4 x8 x16 SDRAM Stresses greater than those listed under Absolute Maxi mum Ratings may cause permanent damage to the de Relative to 1V to 4 6V vice Thisisa stress rating only and functional operation Voltage on Inputs NC or I O Pins of the device at these or any other conditions above those Relative to 1V to 4 6V indicated in the operational sections of this specification Operating Temperature is not implied Exposure to absolute maximum rating T4 commercial 0 to 70 C conditions for extended periods may affect reliability Operating Temperature TA extended IT parts 40 C to 85 C Storage Temperature plastic 55 C to 150 C Power Dissipation eere 1W DC ELE
48. ce 128MSDRAM E p65 Rev E Pub 1 02 54 2001 Micron Technology Inc 128Mb x4 x8 x16 qaicron WRITE DQM OPERATION COMMAND X x NOP WRITE x NOP XX NOP XX NOP XX NOP xZ tems LET wo N NZK LT tps 1 5 tps SMM SO ES ES DON T CARE TIMING PARAMETERS 7E 75 8E 7E 75 8 SYMBOL MIN MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS tAH 0 8 0 8 1 ns tcKS 1 5 1 5 2 ns tas 1 5 1 5 2 ns tCMH 0 8 0 8 1 ns tCH 2 5 2 5 3 ns tcMS 1 5 1 5 2 ns tcL 2 5 2 5 3 ns tDH 0 8 0 8 1 ns tcK 3 7 7 5 8 ns tps 1 5 1 5 2 ns tcK 2 7 5 10 10 ns tRCD 15 20 20 ns tcKH 0 8 0 8 1 ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 4 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change produc cific without notic 128MSDRAM_E p65 Rev E Pub 1 02 55 102001 a n Te chnology Inc 7 128Mb x4 x8 x16 Macron SDRAM 54 PIN PLASTIC TSOP 400 mil 22 30 SEE DETAIL A 22 14 71 t gt 4 80 TYP 10 2X
49. change products or specifications without notice 2001 Micron Technology Inc Micron gt 1 i cse 3 CONTROL LOGIC WE 8 cast gt O 5 i H 6 RAS _ y o MODE REGISTER ADDRESS REGISTER FUNCTIONAL BLOCK DIAGRAM 32 Meg x 4SDRAM REFRESH COUNTER Fy BANK2 BANK3 r4 BANKO ROW ADDRESS LATCH amp DECODER r4 BANKO 2096 MEMORY ARRAY 4 096 x 2 048 x 4 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 BANK CONTROL LOGIC COLUMN ADDRESS COUNTER LATCH 11 SENSE AMPLIFIERS VO GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS COLUMN DECODER 128Mb x4 x8 x16 SDRAM DATA 4 OUTPUT REGISTER DQM DATA 4 INPUT REGISTER DQO DQ3 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc 7 128Mb x4 x8 x16 Macron 3 SDRAM FUNCTIONAL BLOCK DIAGRAM 16 Meg x 8 SDRAM
50. d and address buses be available at the appropriate time to issue the command the advantage of the PRECHARGE command is that it can be used to truncate fixed length or full page bursts TO TI T2 T3 T4 T5 T6 1j ru CLK l l tWR tCK gt 15ns l 1 D RP 1 COMMAND Ue WRITE X NOP NOP K NOP ACTIVE X NOP X ADDRESS 1 us ES d 2 7 l wr 1 DED IM I VDU 4 1 tre L L X NOP M ACTIVE X T T 1 i COMMAND WRITE Cm ym X li li I I BANK BANK BANK a ADDRESS 1 corn Z mU KEDU 2 ow X l twr Z DQM could remain LOW in this example if the WRITE burst is a fixed length of two DON T CARE l D D pq inn l NOTE Figure 18 WRITE to PRECHARGE Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc 23 Micron Fixed length or full page WRITE bursts can be trun cated with the BURST TERMINATE command When truncating a WRITE burst the input data applied coinci dent with the BURST TERMINATE command will be ignored The last data written provided that DQM is LOWat that time will be the input data applied one clock previous to the BURST TERMINATE command This is shown in Figure 19 where data n is the
51. d every 15 625 will meet the refresh requirement and ensure that each rowis refreshed Alter natively 4 096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate once every 64ms SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM even if the rest of the system is powered down When in the self refresh mode the SDRAM 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 128Mb x4 x8 x16 SDRAM retains data without external clocking The SELF RE FRESH command is initiated like an AUTO REFRESH command except CKE is disabled LOW Once the SELF REFRESH command is registered all the inputs to the SDRAM become Don t Care with the exception of CKE which must remain LOW Once self refresh mode is engaged the SDRAM pro vides its own internal clocking causing it to perform its own AUTO REFRESH cycles The SDRAM mustremain in self refresh mode for a minimum period equal to RAS and may remain in self refresh mode for an indefinite period beyond that The procedure for exiting self refresh requires a se quence of commands First CLK must be stable stable clock is defined as a signal cycling within timing con straints specified for the clock pin prior to CKE going back HIGH Once CKE is HIGH the SDRAM must have NOP commands issued a minimum of two clocks for XSR because time is required for the completion of any internal refresh in progress Upon ex
52. d start READ burst 7 8 16 Precharge L H L L WRITE Select column and start new WRITE burst 7 8 17 L L H L PRECHARGE 9 NOTE 1 This table applies when CKE was HIGH and CKE is HIGH see Truth Table 2 and after XSR has been met if the previous state was self refresh 2 This table describes alternate bank operation except where noted i e the current state is for bank n and the commands shown are those allowed to be issued to bank m assuming that bank m is in such a state that the given command is allowable Exceptions are covered in the notes below 3 Current state definitions Idle The bank has been precharged and RP has been met Row Active A row in the bank has been activated and tRCD has been met No data bursts accesses and no register accesses are in progress Read READ burst has been initiated with auto precharge disabled and has not yet terminated or been terminated Write A WRITE burst has been initiated with auto precharge disabled and has not yet terminated or been terminated Read w Auto Precharge Enabled Starts with registration of a READ command with auto precharge enabled and ends when has been met Once RP is met the bank will be in the idle state Write w Auto Precharge Enabled Starts with registration of a WRITE command with auto precharge enabled and ends when has been met Once RP is met the bank will be in the idle state Continued on next page 128Mb
53. e if DQM was LOW during T4 in Figure 10 then the WRITEs at T5 and T7 would be valid while the WRITE at T6 would be invalid The DQM signal must be de asserted prior to the WRITE command DQM latency is zero clocks for input buffers to ensure that the written data is not masked Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle and Figure 10 shows the case where the additional NOP is needed CLK DQM COMMAND ADDRESS DQ NOTE CAS latency of three is used for illustration The READ command may be to any bank and the WRITE command may be to any bank DON T CARE Figure 10 READ to WRITE With Extra Clock Cycle Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron A fixed length READ burst may be followed by or truncated with a PRECHARGE command to the same bank provided that auto precharge was not activated and a full page burst may be truncated with a PRECHARGE command to the same bank The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid where x equals the CAS latency minus one This is shown in Figure 11 for each possible CAS latency data element 3 is either the last of a burst of four or the last 1 128Mb x4 x8 x16 1 SDRAM desired
54. ed 36 Address input A12 for the 256Mb and 512Mb devices 3 9 43 49 Supply DQ Power Isolated DQ power on the die for improved noise immunity 6 12 46 52 Supply DQ Ground Isolated DQ ground on the die for improved noise immunity 1 14 27 Supply Power Supply 3 3V 0 3V 28 41 54 Supply Ground 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM_E p65 Rev E Pub 1 02 8 2001 Micron Technology Inc Micron FUNCTIONAL DESCRIPTION In general the 128Mb SDRAMs 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks and 2 Meg x 16 x 4 banks are quad bank DRAMs that operate at 3 3V and include synchro nous interface all signals are registered on the positive edge of the clock signal CLK Each of the x4 s 33 554 432 bit banks is organized as 4 096 rows by 2 048 columns by 4 bits Each of the x8 s 33 554 432 bit banks is organized as 4 096 rows by 1 024 columns by8 bits Each of the x16 s 33 554 432 bit banks is organized as 4 096 rows by 512 columns by 16 bits Read and write accesses to the SDRAM are burst ori ented accesses start at a selected location and continue for a programmed number oflocations in a programmed sequence Accesses begin with the registration of an AC TIVE command which is then followed by a READ or WRITEcommand The address bits registered coincident with the AC
55. equent ACTIVE command to another bank can be issued while the first bank is being accessed which results in a reduction of total row access overhead The minimum time interval between successive ACTIVE com mands to different banks is defined by RRD 128Mb x4 x8 x16 ZU NU A0 A10 A11 BAO BA1 Figure 3 Activating a Specific Row Specific Bank QtRCD DON T CARE Figure 4 Example Meeting MIN When 2 lt tRCD MIN ICK lt 3 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 15 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron READs READ bursts are initiated with a READ command as shown in Figure 5 The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access Ifauto precharge is enabled the row being accessed is precharged at the completion of the burst For the generic READ com mands used in the following illustrations auto precharge is disabled During READ bursts the valid data out element from the starting column address will be available following the CAS latency after the READ command Each subse quent data out element will be valid by the next positive clock edge Figure 6 shows general timing for each pos sible CAS latency setting CLK I
56. estart refresh time base CLK stable prior to exiting DON T CARE self refresh mode TIMING PARAMETERS 7E 75 8E 7E 75 8 SYMBOL MIN MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS tAH 0 8 0 8 1 ns tcKS 1 5 1 5 2 ns tas 1 5 1 5 2 ns CMH 0 8 0 8 1 ns tCH 2 5 2 5 3 ns tcMS 1 5 1 5 2 ns tcL 2 5 2 5 3 ns tRAS 37 120 000 44 120 000 50 120 000 ns tcK 3 7 7 5 8 ns tRP 15 20 20 ns tcK 2 7 5 10 10 ns tXSR 75 75 80 ns tCKH 0 8 0 8 1 ns CAS latency indicated in parentheses NOTES 1 No maximum time limit for Self Refresh RAS max applies to non Self Refresh mode 2 XSR requires minimum of two clocks regardless of frequency or timing 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change produc cific without notic 128MSDRAM_E p65 Rev E Pub 1 02 41 2001 Ns n Te chnology Inc 128Mb x4 x8 x16 Macron SDRAM READ WITHOUT AUTO PRECHARGE TO T1 T2 T3 T4 T5 T6 T7 T8 CLK CK a ee tcH 4 5 5 4 4 FU 4 UE UE UU MS CMH COMMAND y ACTIVE XX READ XX NOP XX NOP WX 0 NOP XX ACTIVE Ws tems DAME DOMH YW tas A0 A9 11 YZ CGotuuN Y M y WY YU
57. gistered on each successive positive clock edge Upon completion of a fixed length burst assuming no other commands have been initiated the DQs will remain High Z and any addi tional input data will be ignored see Figure 14 A full page burst will continue until terminated At the end of the page it will wrap to column 0 and continue Data for any WRITE burst may be truncated with a subsequent WRITE command and data fora fixed length WRITE burst may be immediately followed by data for a WRITE command The new WRITE command can be issued on any clock following the previous WRITE com mand and the data provided coincident with the new TUN TI Z case D LL wes TD i LL 0 A9 is x4 0 A3 x8 tte Mets NIL s At Zx 1 ENABLE AUTO PRECHARGE A DISABLE AUTO PRECHARGE 1 SLL Figure 13 WRITE Command 1 COLUMN ADDRESS T BAO 1 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 22 128Mb x4 x8 x16 SDRAM command applies to the new command An example is shown in Figure 15 Data n 1 is either the last of a burst of two or the last desired of a longer burst The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 27 rule associated with a prefetch archi tecture A WRITE command can be initiated on any clock cycle following a previous WRITE command Full speed random write accesses wi
58. he clock is suspended See examples in Figures 22 and 23 TO T1 T2 T3 T4 T5 CLK LT S ba pA I I I CKE I I I I I I I I I INTERNAL CLOCK u I COMMAND wor were NOP ADDRESS Zm Zam om LK CE NOTE For this burst length 4 or greater and DM is LOW Figure 22 Clock Suspend During WRITE Burst 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 25 128Mb x4 x8 x16 SDRAM Clock suspend mode is exited by registering CKE HIGH the internal clock and related operation will re sume on the subsequent positive clock edge BURST READ SINGLE WRITE The burst read single write mode is entered by pro gramming the write burst mode bit M9 in the mode register to a logic 1 In this mode all WRITE commands result in the access of a single column location burst of one regardless of the programmed burst length READ commands access columns according to the programmed burst length and sequence just as in the normal mode of operation M9 0 CLK CKE INTERNAL CLOCK an is COMMAND 4 jc NOP NOP ZZ NOP NOP X M Y ni Md 20 TY 02 DAL pQ g i X X d X ED NOTE For this example CAS latency 2 burst length 4 or greater and DQM is LOW BANK ADDRES
59. hout notice 9 2001 Micron Technology Inc 128Mb x4 x8 x16 dicron SDRAM NOTE continued 5 The following states must not be interrupted by any executable command COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states Refreshing Starts with registration of AUTO REFRESH command and ends when tRC is met Once RC is met the SDRAM will be in the all banks idle state Accessing Mode Register Starts with registration of a LOAD MODE REGISTER command and ends when MRD has been met Once MRD is met the SDRAM will be in the all banks idle state Precharging All Starts with registration of a PRECHARGE ALL command and ends when RP is met Once RP is met all banks will be in the idle state All states and sequences not shown are illegal or reserved Not bank specific requires that all banks are idle May or may not be bank specific if all banks are to be precharged all must be in a valid state for precharging Not bank specific BURST TERMINATE affects the most recent READ or WRITE burst regardless of bank READs or WRITEs listed in the Command Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled 11 Does not affect the state of the bank and acts as a NOP to that bank O VO OO 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications witho
60. iting the self refresh mode AUTO REFRESH commands must be issued every 15 625us or less as both SELF REFRESH and AUTO REFRESH utilize the row re fresh counter Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron Operation BANK ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM a row in that bank must be opened This is accomplished via the ACTIVE com mand which selects both the bank and the row to be activated see Figure 3 After opening a row issuing an ACTIVE command a READ or WRITE command may be issued to that row subject to the RCD specification RCD MIN should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE com mand can be entered For example a RCD specification of 20ns with a 125 MHz clock 8ns period results in 2 5 clocks rounded to 3 This is reflected in Figure 4 which covers any case where 2 lt RCD MIN tCK lt 3 The same procedure is used to convert other specification limits from time units to clock cycles Asubsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed precharged The mini mum time interval between successive ACTIVE com mands to the same bank is defined by tRC Asubs
61. led Vpp VppQ 3 3 f 1 MHz T 25 C pin under test biased at 1 4V is dependent on output loading and cycle rates Specified values are obtained with minimum cycle time and the outputs open Enables on chip refresh and address counters The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range 0 C x T lt 70 C and 40 C lt T lt 85 C for IT parts is ensured An initial pause of 100ps is required after power up followed by two AUTO REFRESH commands before proper device operation is ensured and VDDQ must be powered up simultaneously Vss and VssQ mustbeatsame potential The two AUTO REFRESH command wake ups should be repeated any time the refresh requirement is exceeded AC characteristics assume tT Ins In addition to meeting the transition rate specifica tion the clockand CKE musttransit between Vin and Vit or between Vir and in a monotonic manner Outputs measured at 1 5V with equivalent load ZEE 1 HZ defines the time at which the output achieves the open circuit condition it is not a reference to Vou or Vor The last valid data element will meet OH before going High Z 50pF AC timing and Ipp tests have Vit with timing referenced to 1 5V crossover point If the in put transition time is longer than 1 ns then the timing is referenced at MAX and Vin MIN and
62. lete the SDRAM is ready for mode register pro gramming Because the mode register will power up in an unknown state it should be loaded prior to applying any operational command 128Mb x4 x8 x16 SDRAM 128MSDRAM_E p65 Rev E Pub 1 02 128Mb x4 x8 x16 SDRAM Register Definition MODE REGISTER The mode register is used to define the specific mode of operation of the SDRAM This definition includes the selection ofa burst length a burst type a CAS latency an operating mode and a write burst mode as shown in Figure 1 The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power Mode register bits M0 M2 specify the burst length M3 specifies the type of burst sequential or interleaved M4 M6 specify the CAS latency M7 and M8 specify the operating mode M9 specifies the write burst mode and M10 and M11 are reserved for future use The mode register must be loaded when all banks are idle and the controller must wait the specified time before initiating the subsequent operation Violating ei ther of these requirements will result in unspecified op eration Burst Length Read and write accesses to the SDRAM are burst ori ented with the burst length being programmable as shown in Figure 1 The burst length determines the maxi mum number of column locations that can be accessed for a given READ or WRITE command Bur
63. llimeters 2 Recommended Pad size for PCB is 0 33mm 0 025mm 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 57 2001 Micron Technology Inc 1 128 x4 x8 x16 Macron ey SDRAM FBGA FC PACKAGE 60 BALL 11mm x 13mm 0 850 0 075 0 325 0 025 0 205 MAX SEATING PLANE 0 10 H 5 60 2 40 0 05 CTR 0 45 0 05 0 80 PIN 1 ID 6 50 0 05 cea Poco b 8 em 13 00 0 10 I D4 20 5 60 0 05 s ee 0 80 bo 2 80 0 05 1 20 MAX 5 50 0 05 11 00 0 10 Bottom View NOTE 1 All dimensions in millimeters 2 Recommended Pad size for PCB is 0 33mm 0 025mm 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM_E p65 Rev Pub 1 02 58 2001 Micron Technology Inc 128Mb x4 x8 x16 ficron SDRAM FBGA DEVICE MARKING DBFCF Due to the size of the package Micron s standard part number is not printed on the top of each device Instead Speed Grade an abbreviated device mark comprised of a five digit D 8E alphanumeric codeis used The abbreviated device ma
64. lowing the last or last de sired dataelement from the READ burst provided that I O contention can be avoided In a given system design there may be a possibility that the device driving the input data will go Low Z before the SDRAM DQs go High Z In this case at least a single cycle delay should occur between the last read data and the WRITE command The DQM input is used to avoid I O contention as shown in Figures 9 and 10 The DQM signal must be asserted HIGH at least two clocks prior to the WRITE command DQM latency is two clocks for output buffers TO T1 T2 T3 T4 COMMAND 4 H NOP i NOP Y E X l BANK BANK ADDRESS 1 W COLD i HZ pe l l l i lr tbs NOTE CAS latency of three is used for illustration The READ command may be to any bank and the WRITE command may be to any bank If a burst of one is used then DQM is not required Figure 9 READ to WRITE 128Mb x4 x8 x16 SDRAM 128MSDRAM_E p65 Rev E Pub 1 02 19 128Mb x4 x8 x16 SDRAM to suppress data out from the READ Once the WRITE command is registered the DQs will go High Z or re main High Z regardless of the state of the DQM signal provided the DQM was active on the clock just prior to the WRITE command that truncated the READ com mand Ifnot the second WRITE will be an invalid WRITE For exampl
65. mined by the burst length the burst type and the starting col umn address as shown in Table 1 A11 A10 A9 A8 A7 A5 4 A2 Al AD Address Bus EY YYY EY Y TY 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx Reserved WB Op Mode CAS Latency BT Burst Length Should program M11 M10 0 0 to ensure compatibility Burst Length with future devices M2 M1 MO M3 0 M3 1 1 1 0 0 1 2 2 4 4 0 1 1 8 8 100 Reserved Reserved Reserved Reserved 110 Reserved Reserved 3 c4 Full Page Reserved Y M3 Burst Type 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 000 Reserved 0 0 1 Reserved 2 011 3 100 Reserved 1 70 4 Reserved 110 Reserved 4 T1 Reserved M8 M7 M6 MO Operating Mode 0 0 Defined Standard Operation All other states reserved Y M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access Figure 1 Mode Register Definition 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 128Mb x4 x8 x16 SDRAM Table 1 Burst Definition Burst Starting Column Order of Accesses Within a Burst Length Address Type Sequential Interleaved AO o o o1 1 0 1 0 AT 0 0 0123 0 1 2 3 1 2 3 0 1 0 3 2 2 3 0 1 2 3 0 1 3 0 1 2 3 2 1 0 0 O 0
66. n the BAO BAI inputs selects the bank and the address provided on inputs A0 A9 A11 x4 A0 A9 x8 or A0 A8 x16 selects the starting column location The value on input A10 determines whether or not auto precharge is used If auto precharge is selected the row being accessed will be precharged at the end of the READ burst if auto precharge is not se lected the row will remain open for subsequent accesses Read data appears on the DQs subjectto thelogiclevelon the DQM inputs two clocks earlier If a given DQM signal was registered HIGH the corresponding DQs will be High Z two clocks later ifthe DQM signal was registered LOW the DQs will provide valid data WRITE The WRITE command is used to initiate a burst write access to an active row The value on the BAO 1 inputs selects the bank and the address provided on inputs A0 AQ A11 x4 A0 A9 x8 or A0 A8 x16 selects the starting column location The value on input A10 determines 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 13 128Mb x4 x8 x16 SDRAM whether or not auto precharge is used If auto precharge is selected the row being accessed will be precharged at the end of the WRITE burst if auto precharge is not selected the row will remain open for subsequent ac cesses Input data appearing on the DQs is written to the memory array subject to the DOM input logic level ap pearing coincident with the data If a given DQM signalis registe
67. on bank n when registered Figure 17 with the data out appearing CAS latency later The last valid WRITE to bank n will be data in registered one clock prior to the READ to bank m 13 For a WRITE without auto precharge interrupted by a WRITE with or without auto precharge the WRITE to bank m will interrupt the WRITE on bank n when registered Figure 15 The last valid WRITE to bank n will be data in registered one clock prior to the READ to bank m 14 For a READ with auto precharge interrupted by a READ with or without auto precharge the READ to bank m will interrupt the READ on bank n CAS latency later The PRECHARGE to bank n will begin when the READ to bank m is registered Figure 24 15 For a READ with auto precharge interrupted by a WRITE with or without auto precharge the WRITE to bank m will interrupt the READ on bank n when registered DOM should be used two clocks prior to the WRITE command to prevent bus contention The PRECHARGE to bank n will begin when the WRITE to bank m is registered Figure 25 16 For a WRITE with auto precharge interrupted by a READ with or without auto precharge the READ to bank m will interrupt the WRITE on bank n when registered with the data out appearing CAS latency later The PRECHARGE to bank n will begin after WR is met where WR begins when the READ to bank m is registered The last valid WRITE to bank n will be data in registered one clock prior to the READ to bank m Figure 26 17 For
68. option An auto precharge function may be enabled to provide a self timed row precharge that is initiated at the end of the burst sequence The 128Mb SDRAM uses an internal pipelined architecture to achieve high speed operation This architecture is compatible with the 27 rule of prefetch architectures butit also allows the column address to be changed on every clock cycle to achieve a high speed fully random access Precharging one bank while access ing one of the other three banks will hide the precharge cycles and provide seamless high speed random access operation The 128Mb SDRAM is designed to operate in 3 3V memory systems Anauto refresh modeis provided along with a power saving power down mode All inputs and outputs are LVTTL compatible SDRAMs offer substantial advances in DRAM operat ing performance including the ability to synchronously burst data at a high data rate with automatic column address generation the ability to interleave between in ternal banks in order to hide precharge time and the capabilityto randomly change column addresses on each clock cycle during a burst access Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron TABLE OF CONTENTS Functional Block Diagram 32 Meg x 4 5 Functional Block Diagram 16 Meg x 8 6 Functional Block Diagram 8 Meg x 16 7 Pin D sc
69. pecifications without notice 2001 Micron Technology Inc Micron CAS Latency The CAS latency is the delay in clock cycles between the registration of aREAD command and the availability of the first piece of output data The latency can be set to two or three clocks Ifa READ command is registered at clock edge and the latency is m clocks the data will be available by clock edge The DQs will start driving as a result of the clock edge one cycle earlier 1 and provided that the relevant access times are met the data will be valid by clock edge n m For example assuming that the clock cycle time is such that all relevant access times are met ifa READ command is registered at TO and the latency is programmed to two clocks the DQs will start driving after 1 and the data will be valid by T2 as shown in Figure 2 Table 2 below indicates the operating frequen cies at which each CAS latency setting can be used Reserved states should not be used as unknown op eration or incompatibility with future versions may result TO T2 T3 SES 4 A 4 1 COMMAND X READ XX NOP XX NOP XX N OO WAQYAY tAC DQ CAS Latency 2 TO T1 T2 T3 T4 1 1 COMMAND X READ NOP YOK NOP uz toH DQ Dour Q tAC CAS Latency 3 DON T CARE 8 UNDEFINED Figure 2 CAS
70. re 128Mb x4 x8 x16 SDRAM 49 Micron Technology Inc reserves the right to change products or specifications without notice 2001 M SDRAI 128MSDRAM E p65 Rev E Pub 1 02 1 icron Technology Inc Micron 128Mb x4 x8 x16 SDRAM WRITE WITH AUTO PRECHARGE x PES 1 2 C XQ 7 7 7 lt COMMAND 5 wor XX we X wo XX wo XX wo XX wo wo XX active 7 nts Zs 1 1 D 5 ENABLE AUTO PRECHARGE A10 ROW B Y tas lt MM EER X Z ROW W BAO BAI VE BANK cy Z Z xZ 1 5 tpH tps tpH 1 5 tpH 1 5 tpH DQ Din m Y omer ON SERO y y YY 77 YW RCD p twR is trp RAS gt DON T CARE TIMING PARAMETERS 5 3E SYMBOL MIN MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN UNITS Ww os 08 1 ns xw up ul f ns wo 2 ns os ns xw as 25 3 ns 55 15 ns a s 25 3 ns 120 000 ns rae 7 75 8 ns mc 6 f ns rae 7s _ m 10 ns wo fa ns EE 08 1 ns ns tCKS 1 5 2 ns 1 CLK 1 CLK _ CAS latency indicated in parentheses NOTE 1 For
71. red LOW the corresponding data will be written to memory ifthe DQM signal is registered HIGH the corre sponding data inputs will be ignored and a WRITE will not be executed to that byte column location PRECHARGE The PRECHARGE command is used to deactivate the openrowinaparticularbankorthe open rowin all banks The bank s will be available for a subsequent row access a specified time after the PRECHARGE command is issued Input A10 determines whether one or all banks are to be precharged and in the case where only one bank is to be precharged inputs BAO BA1 select the bank Otherwise BAO BAI are treated as Don t Care Once bank has been precharged it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank AUTO PRECHARGE Auto precharge is a feature which performs the same individual bank PRECHARGE function described above without requiring an explicit command This is accom plished by using A10 to enable auto precharge in con junction with a specific READ or WRITE command A PRECHARGE of the bank row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst except in the full page burst mode where auto precharge does not apply Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command Auto precharge ensures that the precharge is initiated at the
72. ripBOnDS oett eee tiennent e nere etes 8 Functional Description 9 Initializati n siete tentent 9 Register Definition eret 9 mode register encre rere 9 Butst LENG 9 Burst TYPE i eret e es 10 CAS Latency etre rehenes 11 Operating Mode 11 Write Burst Mode _ aa aaaasassskaan 11 COMMANAS T 12 Truth Table 1 Commands and DQM Operation 12 Command Inhibit esee 13 No Operation NOD eene 13 Load mode register 13 P uid 13 uenia dudo PINE Ee 13 MT 13 Piti 13 Auto PLECH Ar S Css 13 Burst Terminate a nerit entender 13 AUtO 14 Self Refresh 14 Operation oie 15 Bank Row Activation 15 16 WTS 22 ie e er ROI RETE 24 24 Clock Suspend uz eR eerta 25 Burst Read Single Write 25 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 128Mb x4 x8 x16 Concurrent Auto Precharge 26 Truth Table 2 CKE 28 Truth Table 3 Current State Same Bank 29 Truth Table 4 Current State Different Bank
73. rks 75 are cross referenced to Micron part numbers in Table 1 ee Width 1 05 x4 x8 D x16 Device Density F 128Mb Product Type B 3 3V SDR SDRAM 60 ball FB 8mm x 16mm 3 3V SDR SDRAM 60 ball FC 11mm x 13mm Product Group D DRAM Z DRAM ENGINEERING SAMPLE CROSS REFERENCE FOR FBGA DEVICE MARKING ENGINEERING PRODUCTION PART NUMBER ARCHITECTURE FBGA SAMPLE MARKING MT48LC32M4A2FC 75 ZCFBF DCFBF MT48LC32M4A2FC 7E ZCFBN DCFBN MT48LC32M4A2FB 75 ZBFBF DBFBF MT48LC32M4A2FB 7E ZBFBN DBFBN MT48LC16M8A2FC 75 ZCFCF DCFCF MT48LC16M8A2FC 7E ZCFCN DCFCN MT48LC16M8A2FB 75 ZBFCF DBFCF MT48LC16M8A2FB 7E 16 Meg x 8 60 ball 8x16 ZBFCN DBFCN 8000 S Federal Way P O Box 6 Boise ID 83707 0006 Tel 208 368 3900 E mail prodmktg micron com Internet http www micron com Customer Comment Line 800 932 4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology Inc 128Mb x4 x8 x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM_E p65 Rev E Pub 1 02 59 2001 Micron Technology Inc
74. rp tRAS tac DON T CARE TIMING PARAMETERS SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN UNITS A os fos ns us uu fis 2 ns Fw pu 2 ns M fos ns 9 25 5 3 ns 55 _ s ns wu pes 25 3 ns 44 120 000 ns rae 7 75 8 ns wc 5 fe ns 725 Ln 10 ns m 73 f ns EE 08 ns ss ns 1 5 2 ns 1CLK 1CLK 0 8 1 ns 7ns 7 5ns CAS latency indicated in parentheses NOTE 1 For this example the burst length 1 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 3 WRITE command not allowed else RAS would be violated 128Mb x4 x8 x16 SDRAM 2 Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 5 2001 Micron Technology Inc 128Mb x4 x8 x16 qaicron ALTERNATING BANK WRITE ACCESSES ec E T3 T4 T5 T6 T T8 T9 A tcu a TZ T COMMAND y ACTIVE WRITE XX NOP XX ACTIVE WRITE XX NOP XX ACTIVE W tems vone um 0 TD D 0 D ZC 4 6 gt A0 A9 A11 ROW x ROW xz corum b X Y ROW W xo Y 5777 EEK
75. rs when there is a row active in any bank this mode is referred to as active power down Entering power down deactivates the in put and output buffers excluding CKE for maximum power savings while in standby The device may not remain in the power down state longer than the refresh period 64ms since no refresh operations are performed in this mode The power down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge meeting CKS See Figure 21 a 4 4 amp i 4 4 des LEM CKE Ki Y COMMAND 7 7 ACTIVE x All banks idle RCD Input buffers gated off M RAS Enter power down mode Exit power down mode RC DON T CARE Figure 21 Power Down Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron CLOCK SUSPEND The clock suspend mode occurs when a column ac cess burst is in progress and CKE is registered LOW In the clock suspend mode the internal clock is deacti vated freezing the synchronous logic For each positive clock edge on which CKE is sampled LOW the next internal positive clock edge is suspended Any command or data present on the input pins at the time of a suspended internal clock edge is ignored any data present on the DQ pins remains driven and burst counters are not incremented as long as t
76. s sampled HIGH during a WRITE cycle The output buffers are DQMH placed in a High Z state two clock latency when DQM is sampled HIGH during a READ cycle On the x4 and x8 DQML Pin 15 is a NC and DQMH is DQM On the x16 DQML corresponds to DQ0 DQ7 and DQMH corresponds to DQ8 DQ15 DQML and DQMH are considered same state when referenced as DQM 20 21 Bank Address Inputs BAO and define to which bank the ACTIVE READ WRITE or PRECHARGE command is being applied 23 26 29 34 22 35 Address Inputs A0 A11 are sampled during the ACTIVE command row address A0 A11 and READ WRITE command column address A0 A9 A11 x4 A0 A9 x8 A0 A8 x16 with A10 defining auto precharge to select one location out of the memory array in the respective bank A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged A10 HIGH or bank selected by BAO BA1 A10 LOW The address inputs also provide the op code during a LOAD MODE REGISTER command 2 4 5 7 8 10 11 13 42 200 0015 x16 I O Data Input Output Data bus for x16 4 7 10 13 42 45 48 and 51 are 44 45 47 48 50 51 53 NCs for x8 and 2 4 7 8 10 13 42 45 47 48 51 and 53 are NCs for x4 2 5 8 11 44 47 50 53 000 007 8 Data Input Output Data bus for x8 2 8 47 53 are NCs for x4 5 11 44 50 000 003 4 Data Input Output Data bus for x4 40 No Connect These pins should be left unconnect
77. st lengths of 1 2 4 or 8 locations are available for both the sequential and the interleaved burst types and a full page burst is available for the sequential type The full page burst is used in conjunction with the BURST TERMINATE com mand to generate arbitrary burst lengths Reserved states should not be used as unknown op eration or incompatibility with future versions may re sult When a READ or WRITE commandis issued a block of columns equal to the burst length is effectively selected All accesses for that burst take place within this block meaning that the burst will wrap within the block if a boundary is reached The block is uniquely selected by 1 9 11 x4 A1 A9 x8 or A1 A8 x16 when the burst length is set to two by A2 A9 A11 x4 A2 A9 x8 or A2 A8 x16 when the burstlengthis set to four and by A3 A9 11 x4 A3 A9 x8 or A3 A8 x16 when the burst length is set to eight The remaining least significant address bit s is are used to select the starting location within the block Full page bursts wrap within the page if the boundary is reached Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3 The ordering of accesses within a burst is deter
78. ster accesses are in progress A READ burst has been initiated with auto precharge disabled and has not yet terminated or been terminated A WRITE burst has been initiated with auto precharge disabled and has not yet terminated or been terminated 4 The following states must not be interrupted by a command issued to the same bank COMMAND INHIBIT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states Allowable commands to the other bank are determined by its current state and Truth Table 3 and according to Truth Table 4 Precharging Row Activating Read w Auto Precharge Enabled Write w Auto Precharge Enabled 128Mb x4 x8 x16 SDRAM 128MSDRAM E p65 Rev E Pub 1 02 Starts with registration of a PRECHARGE command and ends when is met Once is met the bank will be in the idle state Starts with registration of an ACTIVE command and ends when RCD is met Once RCD is met the bank will be in the row active state Starts with registration of a READ command with auto precharge enabled and ends when RP has been met Once RP is met the bank will be in the idle state Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met Once RP is met the bank will be in the idle state Continued on next page 2 Micron Technology Inc reserves the right to change products or specifications wit
79. the right to change products or specifications without notice 2001 Micron Technology Inc Micron WRITE with Auto Precharge 3 Interrupted by a READ with or without auto precharge A READ to bank m will interrupt a WRITE on bank n when registered with the data out appear ing CAS latency later The PRECHARGE to bank will begin after WR is met where WR begins when the READ to bank m is registered The last valid WRITE to bank n will be data in registered one clock prior to the READ to bank m Figure 26 128Mb x4 x8 x16 SDRAM Interrupted by a WRITE with or without auto precharge A WRITE to bank mwillinterrupta WRITE on bank n when registered The PRECHARGE to bank n will begin after WR is met where WR begins when the WRITE to bank is registered The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m Figure 27 TO T1 T2 T3 TA T5 T6 T7 UM 1 l l l l l I ae CEES cA A BANK n Page Active WRITE with Burst of 4 Interrupt Burst Write Back Precharge 1 dista SEA 1 tates BANK Page Active READ with Burst of 4 2 m m m m m m m m m m m m m m mm k m m m mim m m m mim m m m mm m m mm ADDRESS 2700622507 A i i
80. thin a page can be performed to the same bank as shown in Figure 16 or each subsequent WRITE may be performed to a different bank CLK d 1 1 J COMMAND M NOP X Z X 9 H ADDRESS DUMU DQ 5 NOTE Burst length 2 DQM is LOW Figure 14 WRITE Burst TO T1 2 1 1 COMMAND NOP ES Din DQ n n 1 b NOTE DQM is LOW Each WRITE command may be to any bank DON T CARE Figure 15 WRITE to WRITE Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron Data for any WRITE burst may be truncated with a subsequent READ command and data for a fixed length WRITE burst may be immediately followed by a READ command Once the READ command is registered the data inputs will be ignored and WRITEs will not be executed An example is shown in Figure 17 Datan 115 either the last of a burst of two or the last desired of a longer burst Data for a fixed length WRITE burst may be followed by or truncated with a PRECHARGE command to the same bank provided that auto precharge was not acti vated and a full page WRITE burst may be truncated with a PRECHARGE command to the same bank The PRECHARGE command should be issued WR after the clock edge at which the last desired input data element is registered The auto precharge mode requires a WR of at TO 1 2 T3 FA COMMAND WRITE Lp W
81. thin timing constraints specified for the clock pin during access or precharge states READ WRITE including WR and PRECHARGE commands CKE may be used to reduce the data rate Auto precharge mode only The precharge timing budget begins 7ns for 7E 7 5ns for 75 and 7ns for 8E after the first clock delay after the last WRITE is executed May not exceed limit set for precharge mode Precharge mode only JEDEC and PC100 specify three clocks AC for 75 7E at CL 3 with no load is 4 6ns and is guaranteed by design Parameter guaranteed by design PC100 specifies a maximum of 4pF PC100 specifies a maximum of 5pF PC100 specifies a maximum of 6 5pF For 8E CL 2 and 10ns for 75 CL 3 and 7 5ns for 7E CL 2 and 7 5115 is HIGH during refresh command period MIN else CKE is LOW The limit is actu ally a nominal value and does not result in a fail value PC133 specifies a minimum of 2 5pF PC133 specifies a minimum of 3 0pF Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc 128Mb x4 x8 x16 Micron INITIALIZE AND LOAD MODE REGISTER TO T1 T Tn 1 To 1 1 2 3 CLK a lt ZZ Ul Ur 7 W NU tcMS cMs 5 tcMH E J las aL ee e i COMMAND
82. this example the burst length 4 2 x16 and A11 Don t Care x8 A11 Don t Care 128Mb x4 x8 x16 SDRAM 128MSDRAM_E p65 Rev E Pub 1 02 50 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc x 128Mb x4 x8 x16 qaicron SINGLE WRITE WITHOUT AUTO PRECHARGE TO T1 T2 T3 T4 T5 T6 T7 T8 m Ja m 4 4 4 4 4 4 lt lt 7 97 7 7 Ul 7 7 Wi X T tems COMMAND y ACTIVE XX WRITE XX 4 XX nop4 ACTIVE tems Z77770 N tas MMMM gt ee tas ALL BANKS Zm tas tay DISABLE AUTO PRECHARGE SINGLE BANK ee MMMM Ea MMM tos MMM OO RCD twr 2 trp tRAS BH g DON T CARE TIMING PARAMETERS 75 8E 7E 75 8E SYMBOL MIN MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS AH 08 1 ns tcMS 1 5 1 5 2 ns 15 2 ns tDH 0 8 0 8 1 ns cH 25 25 3 ns tps 1 5 1 5 2 ns ta 25 25 3 ns tRAS 37 120 000 44 120 000 50 120 000 ns k
83. urst length 4 and the CAS latency 2 2 x16 A9 and A11 Don t Care x8 A11 Don t Care 128Mb x4 x8 x16 SDRAM 128MSDRAM_E p65 Rev E Pub 1 02 43 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc 128Mb x4 x8 x16 Macron SDRAM SINGLE READ WITHOUT AUTO PRECHARGE UD Ul Ul Ul Ul XU commano KX wor XX nao XX wor XX woe necne nor MC nave MMMM TT DD DDR X row 77m oor XD ZI SINGLE BANKS tas DISABLE AUTO PRECHARGE gt BAO BAI x BANK YZ d Y toH lt D Dourm Q lt tuz CAS Latency tgp m 1 m tRAS tRC DON T CARE UNDEFINED TIMING PARAMETERS 7E 75 8E SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN UNITS 54 5 4 6 ns xw os os Th ns Pacey 5 6 6 ms 315 pis 2 ns os 03 i ns sa 34 ns s 13 15 2 ns wm fsa ef ns 25 3 ns ns 25 3 ns oe aj ns 75 D ns aa 125 000 ns D 10 ns Wc fo s ns os 08 ns ns x 15 1
84. ut notice 128MSDRAM E p65 Rev E Pub 1 02 30 2001 Micron Technology Inc 128Mb x4 x8 x16 dicron 3 SDRAM TRUTH TABLE 4 CURRENT STATE BANK n COMMAND TO BANK m Notes 1 6 notes appear below and on next page CURRENT STATE CS RAS CAS WE COMMAND ACTION NOTES Any H x x x COMMAND INHIBIT NOP Continue previous operation L H H H NO OPERATION NOP Continue previous operation Idle X X X X Any Command Otherwise Allowed to Bank m Row L L H H ACTIVE Select and activate row Activating L H L H READ Select column and start READ burst Active or L H L L WRITE Select column and start WRITE burst Precharging L L H L PRECHARGE Read L L H H ACTIVE Select and activate row Auto L H L H READ Select column and start new READ burst 7 10 Precharge L H L L WRITE Select column and start WRITE burst 7 11 Disabled L L H L PRECHARGE 9 Write L L H H ACTIVE Select and activate row Auto L H L H READ Select column and start READ burst 7 12 Precharge L H L L WRITE Select column and start new WRITE burst 7 13 Disabled L L H L PRECHARGE 9 Read L L H H ACTIVE Select and activate row With Auto L H L H READ Select column and start new READ burst 7 8 14 Precharge L H L L WRITE Select column and start WRITE burst 7 8 15 L L H L PRECHARGE 9 Write L L H H ACTIVE Select and activate row With Auto L H L H READ Select column an
85. x16 SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 128MSDRAM E p65 Rev E Pub 1 02 1 2 2001 Micron Technology Inc Micron COMMAND INHIBIT The COMMAND INHIBIT function prevents new com mands from being executed by the SDRAM regardless of whether the CLK signal is enabled The SDRAM is effec tively deselected Operations already in progress are not affected NO OPERATION NOP The NO OPERATION NOP command is used to per form a NOP to an SDRAM which is selected CS is LOW This prevents unwanted commands from being regis tered during idle or wait states Operations already in progress are not affected LOAD MODE REGISTER The mode register is loaded via inputs A0 A11 See mode register heading in the Register Definition section The LOAD MODE REGISTER command can only be is sued when all banks are idle and a subsequent execut able command cannot be issued until MRD is met ACTIVE The ACTIVE command is used to open or activate a row in a particular bank for a subsequent access The value on the BAO BAI inputs selects the bank and the address provided on inputs A0 A11 selects the row This row remains active or open for accesses until a PRECHARGE command is issued to that bank A PRECHARGE command must be issued before openinga different row in the same bank READ The READ command is used to initiate a burst read access to an active row The value o

MICRON SYNCHRONOUS DRAM 128Mb x4 x8 x16 SDRAM

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