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MICRON SYNCHRONOUS DRAM 512Mb x4 x8 x16 DDR SDRAM

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1. gt O ck gt O CK 96 cs O CONTROL i i Su LOGIC gt X gt CASH gt Q 2 2 RASH po __ REFRESH BANK1 COUNTER 1 ro X 1 1 1 MODE REGISTERS ROWS a BANKO ADDRESS A ROW BANKO MUX ADDRESS MEMORY 4 13 LATCH ARRAY im amp 8 192 x 512 x 32 DATA DLL DECODER 16 2 32 Reap 16 SENSE AMPLIFIERS LATCH 16 gt DQS 2 P 6 GENERATOR Bore COLO LDM UDM VO GATING 4 ieit 295 DM MASK LOGIC 32 REGISTERS 1295 2 2 1 9 vas A0 A12 ADDRESS CONTROL MASK 74 lt BAO BA1 REGISTER LOGIC 2 i 2 write 4 7 2 2 gt 512 32 FIFO 4 32 amp RCVRS 4 gt gt DRIVERS E la sj 16 16 4 COLUMN ck DATA la i DECODER out m COLUMN 4 1 ADDRESS 9 10 1 COUNTER LATCH COLO 1 EN EE 512Mb x4 8 x16 DDR SDRAM 6 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pu
2. 1 4 1005 MAX 12055 ZA DIO UC OK Da AY NY LLL DON T CARE TRANSITIONING DATA NOTE 1 RE data in for column b 2 5 Wind nt of data sapere See TE nterrupted burst of 4 is cate one data element is tWR enced from the firs pe adu a edge a he s pai 5 PRECHARGE WRITE commands hes due 6 Soci iui wi ith the WRITE command a Utd o pre echar xn s dis able 7 DQS is required 2 2 idi se to re register 8 Ha e bur em d aos sed DM would be requ red at T3 a TI ot at T4 T4n because the PRECHARGE and would ma last two data elements 9 comman d Figure 24 WRITE to PRECHARGE Odd Number of Data Interrupting Micron PRECHARGE The PRECHARGE command Figure 25 is used to deactivate the open row in a particular bank or the open row in all banks The bank s will be available for a subsequent row access some specified time af ter the PRECHARGE command is issued Input 10 CK CK CKE HIGH wee 77 ML ALL BANKS A10 ONE BANK 1 IA 2 BA Bank Address if A10 is LOW otherwise Don t Care DON T CARE
3. 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 BANK3 1 REFRESH ll 1 COUNTER i ROW 13 BANKO ADDRESS ROW BANKO MUX ADDRESS MEMORY LATCH ARRAY 13 amp 8 192 x 2 048 x 8 DATA DLL DECODER 4 gt Y 8 4 i READ MUX SENSE AMPLIFIERS LATCH DRVRS ae gt 12 pos 1 GENERATOR i DQO 94 Do3 2 GATING 4 INPUT DQs DM MASK LOGIC 8 REGISTERS i BANK i CONTROL i esses MASK LOGIC 7 re 1 2 write 4 1 114 gt 8 FIFO 2 4 7 i amp 4 4 RCVRS je DRIVERS S Ae PR in COLUMN 4 4 ADDRESS 1 12 COUNTER LATCH 0 1 4 Micron Technology Inc reserves the right to change products specifications without notice 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM Micron FUNCTIONAL BLOCK DIAGRAM 64 Meg x 8
4. gt 0 1 gt O cs gt o CONTROL Su LOGIC wet gt 50 gt gt 0 5 SANG BANK3 RASH 1 5 BANK1 REFRESH 1 MODE REGISTERS COUNTER F P pow BANKO ADDRESS ROW BANKO eK 1 Bp MUX ADDRESS MEMORY i IN LATCH ARRAY i amp 8192 x 1024 x 16 DATA DLL DECODER 8 EN 1 16 8 1 READ MUX 7 SENSE AMPLIFIERS LATCH 8 prves gt i 6 095 J 1 i GENERATOR 5 coto 104 9 2 GATING 4 INPUT pas LL DM MASK LOGIC 16 REGISTERS 0 12 4 BANK 0 005 A12 ADDRESS er Dm CONTROL MASK 15 REGISTER LOGIC 4 1 2 write 4 1 1 gt 16 FIFO 2 amp 4 RCVRS 4 i DRIVERS 16 Sp 4 7 8 COLUMN ck k s PA DECODER out in 1 COLUMN 4 T 4 1 ADDRESS 10 1 11 COUNTER LATCH i 1 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM FUNCTIONAL BLOCK DIAGRAM 32 Meg x 16
5. LOW 50 ACTIVE STANDBY CURRENT CS HIGH CKE HIGH One bank IDD3N 35 30 mA 22 Active Precharge tRAS MAX tCK MIN DQ DM and DQS inputs changing twice per clock cycle Address and other control inputs changing once per clock cycle OPERATING CURRENT Burst 2 Reads Continuous burst One bank 15548 TBD TBD mA 22 48 active Address and control inputs changing once per clock cycle tCK tCK MIN lout OMA OPERATING CURRENT Burst 2 Writes Continuous burst One bank Ippaw TBD TBD 22 active Address and control inputs changing once per clock cycle tCK tCK MIN DQ DM and 20 inputs changing twice per clock cycle AUTO REFRESH CURRENT tRC 7 8125ys 1005 6 6 27 50 tRC 1506 TBD TBD mA 22 50 SELF REFRESH CURRENT CKE lt 0 2V Standard 1557 TBD TBD mA 11 Low power L 7 TBD TBD mA 11 OPERATING CURRENT Four bank interleaving READs BL 4 with auto 1508 TBD TBD mA 22 49 precharge RC tRC MIN RC MIN Address and control inputs change only during Active READ or WRITE commands 512Mb x4 x8 x16 DDR SDRAM 46 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc 512Mx4x8x16DDR B p65 Rev B Pub 4 01 ADVANCE 4 x4 x8 x16 DDR SDRAM CAPACITANCE x16 Note 13 notes appear on pages 50 53
6. PARAMETER SYMBOL MIN MAX UNITS NOTES Delta Input Output Capacitance DQ0 DQ7 LDQS LDM DCoL 0 50 pF 24 Delta Input Output Capacitance DQ8 DQ15 UDQS UDM DCiou 0 50 pF 24 Delta Input Capacitance Command and Address 0 50 pF 29 Delta Input Capacitance CK CK Dc2 0 25 pF 29 Input Output Capacitance DQs LDQS UDQS LDM UDM Cio 4 0 5 0 pF Input Capacitance Command and Address 2 0 3 0 pF Input Capacitance CK CK Ci2 2 0 3 0 pF Input Capacitance CKE Ci3 2 0 3 0 pF Ipp SPECIFICATIONS AND CONDITIONS x16 Notes 1 5 10 12 14 notes appear on pages 50 53 0 C lt lt 70 2 5V 0 2V 2 5V 0 2V PARAMETER CONDITION NOTES OPERATING CURRENT One bank Active Precharge tRC MIN 22 48 tCK MIN DQ DM and DQS inputs changing once per clock cyle Address and control inputs changing once every two clock cycles OPERATING CURRENT One bank Active Read Precharge Burst 2 22 48 tRC tCK MIN lout OMA Address and control inputs changing once per clock cycle PRECHARGE POWER DOWN STANDBY CURRENT All banks idle 23 32 Power down mode tCK tCK MIN CKE LOW 50 IDLE STANDBY CURRENT CS HIGH banks idle tCK MIN 51 CKE HIGH Address and other control inputs changing once per clock cycle Vin Vrer for DQ DOS and DM ACTIVE POWER DOWN STANDBY CURRENT One bank active 23
7. DABS RAB MAU MPRA Micron DOUBLE DATA RATE DDR SDRAM RHS a FEATURES e 2 5V 0 2V VDDQ 2 5V 0 2V Bidirectional data strobe DQS transmitted received with data i e source synchronous data capture x16 has two one per byte Internal pipelined double data rate DDR architecture two data accesses per clock cycle e Differential clock inputs CK and Commands entered on each positive CK edge DQS edge aligned with data for READs center aligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask DM for masking write data x16 has two one per byte Programmable burst lengths 2 4 or 8 x16 has programmable IOL IOV Concurrent auto precharge option is supported Auto Refresh and Self Refresh Modes Longer lead TSOP for improved reliability OCPL 2 5V I O SSTL 2 compatible OPTIONS MARKING Configuration 128Megx4 32Megx4 x4 banks 128M4 64Megx8 16Megx8 x4banks 64M8 32 Megx16 8Megx16x4banks 32 16 Plastic Package OCPL 66 pin TSOP standard 22 3mm length TG 400 mil width 0 65mm pin pitch Timing Cycle Time 7 5ns CL 2 DDR266B 75Z 7 5ns CL 2 5 DDR266B 75 10ns CL 2 DDR200 2 8 Self Refresh Standard none Low Power L NOTE 1 Supports PC2100 modules with 2 3 3 timing 2 Supports PC2100 modules with 2 5 3 3 timi
8. 4 A0 A9 A11 A12 VAS V WE Ui WW X MK ACT X ere XX XX nop XX X MMM a tata BAO BA1 MS MMM LLL lt 1 1 tRP 1 1 1 1 tDQSS Nom MN 005 LL EEO fi i 5 RWpRES QVPRE DQSL tDQSH D E NOTE ALD RN ANAN ATTE tps J V toH DI n data out from column n subsequent elements are provided in the programmed order Burst length 4 in the case shown Disable auto precharge DON T CARE Don t Care if A10 is HIGH at T8 PRE PRECHARGE ACT ACTIVE RA Row Address BA Bank Address NOP commands are shown for ease of illustration other commands may be valid at these times tDSH is applicable during 055 is referenced from 4 5 tDSS is applicable during 0055 and is referenced from CK T5 or T6 TRANSITIONING DATA TIMING PARAMETERS Ke 5 ns Ke ns 2055 0 75 0 2 75Z 75 MIN UNITS SYMBOL MIN MAX MIN DSH 0 2 ns ns 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4
9. sess 50mA DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS Notes 1 5 16 notes appear on pages 50 53 0 C lt T lt 70 Voo 2 5V x0 2V 2 5V 0 2V PARAMETER CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage Vop 2 3 V 36 41 Supply Voltage VDDQ 36 41 Input Low Logic 0 Voltage VREF 0 15 28 INPUT LEAKAGE CURRENT Any input OV lt lt Vpp OV lt Vin lt 1 35V All other pins not under test OV OUTPUT LEAKAGE CURRENT DQs are disabled OV lt Vout lt VDDQ OUTPUT LEVELS Full drive option x4 x8 x16 High Current Vout 0 373 minimum Vrer minimum 2 37 39 Low Current Vout 0 373V maximum Vrer maximum OUTPUT LEVELS Reduced drive option x16 only High Current Vout 0 763 minimum Varr minimum 38 39 Low Current Vout 0 763V maximum Vref maximum AC INPUT OPERATING CONDITIONS Notes 1 5 14 16 notes appear on pages 50 53 0 C lt T lt 70 Voo 2 5V 0 2V VDDQ 2 5V 0 2V PARAMETER CONDITION SYMBOL UNITS NOTES Input High Logic 1 Voltage VREF 0 310 14 28 40 Input Low Logic 0 Voltage rer 0 310 ez 28 40 Reference Voltage VntF AC 0 49 x VDDQ 0 51 x VDDQ V 512Mb x4 x8 x16 DDR SDRAM 43 Micron Technology Inc reserves the right to change products or specifications without notice 51
10. 200 40 uno ns PACTVEIoREADwithAutoprechargeconmand war 3 3 m 45 ns m 30 ACTIVE to READ or WRITE delay tRCD ns PRECHARGE command period tRP ns DQS read preamble tRPRE 42 DQS read postamble ACTIVE bankato ACTIVE bank b command tRRD ns DQS write preamble tWPRE DQS write preamble setup time WPRES ns 20 21 DQS write postamble WPST 19 Write recovery time twR ns Internal WRITE to READ command delay tWIR Data valid output window Dvw 0050 ns 25 REFRESH tO REFRESH commander were 03 0a 25 Average periodic refresh interval 78 78 78 ws 23 emissi o ns Exit SELF REFRESH to non READ command XSNR 75 80 ns Exit SELF REFRESH to READ command tXSRD 200 200 200 CK 512Mb x4 x8 x16 DDR SDRAM 48 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM SLEW RATE DERATING VALUES Note 14 notes appear on pages 50 53 0 C x lt 70 VopQ 2 5V 0 2V 2 5V 0 2V ADDRESS COMMAND SPEED SLEW RATE tis UNITS 752 75 0 500V ns 1 1 ns 752 75 0 400V ns 1 05 1 ns 752 75 0 300V ns 1 10 1 ns 752 75 0 200V ns 1 15 1 ns 8 0 500V ns 1 1 1 1 ns 8 0 400V ns 1 15 1 1 ns 8 0 300V ns
11. Figure 25 PRECHARGE Command ADVANCE 512Mb x4 x8 x16 DDR SDRAM determines whether one or all banks are to be precharged and in the case where only one bank is to be precharged inputs BAO BAI select the bank When all banks are to be precharged inputs BAO 1 are treated as Don t Care Once a bank has been precharged it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank POWER DOWN CKE NOT ACTIVE Unlike SDR SDRAMs DDR SDRAMs require CKE to be active at all times an access is in progress from the issuing of a READ or WRITE command until comple tion of the burst Thus a clock suspend is not supported For READs a burst completion is defined when the Read Postamble is satisfied For WRITEs a burst completion is defined when the Write Postamble is satisfied Power down Figure 26 is entered when CKE is reg istered LOW If power down occurs when all banks are idle this mode is referred to as precharge power down if power down occurs when there is a row active in any bank this mode is referred to as active power down Entering power down deactivates the input and output buffers excluding CK CK and CKE For maximum power savings the DLL is frozen during precharge power down Exiting power down requires the device to be at the same voltage and frequency as when it entered power down However power down duration is limited by the refresh requirements o
12. RAS RAS 23 44 CKE CKE CKE CS CS CS 24 43 NC NC NC NC NC NC 25 42 12 12 12 BAO 26 41 FH 11 11 11 1 1 1 27 40 9 9 9 A10 AP A10 AP 10 28 39 HH 8 A8 A8 0 0 A0 29 38 A7 A7 A7 A1 A1 A1 EH 30 37 A6 A6 A6 A2 A2 A2 31 36 5 5 5 32 35 4 4 4 VoD VDD 33 34 Vss Vss Vss 128 Meg x 4 64 Meg x 8 32 Meg x 16 Configuration 32Megx4x4banks 16Megx8x4banks 8 16x4banks Refresh Count amp amp amp RowAddressing 8K A0 A12 8K A0 A12 8K A0 A12 Bank Addressing 4 BAO BAT 4 BAO BAT 4 BAO BAT Column Addressing 4K A0 A9 A11 A12 2 0 9 A11 1K A0 A9 KEY TIMING PARAMETERS CLOCK RATE ACCESS 005 00 CL 2 5 WINDOW WINDOW SKEW 133 MHz 2 5ns 0 75ns 0 5ns 133 MHz 2 5ns 0 75ns 0 5ns 125 MHz 3 4ns 0 8 5 0 6ns Minimum clock rate CL 2 8 and CL 2 5 75 CL CAS Read Latency Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON S PRODUCTION DATA SHEET SPECIFICATIONS Micron 512Mb DDR SDRAM PART NUMBERS Note xx 75 75Z
13. most significant column address bit for a given con 0 A12 A11 10 9 8 7 A5 4 A3 A2 1 0 Address Bus G 1371271171079 7877 76 75 74 73 2 71 70 Mode Register Mx 0 Operating Mode CAS Latency BT Burst Length M14 and M13 BAO and BA1 must be 0 0 to select the ended 2 1 0 3 0 3 1 000 Reserved Reserved 0 0 1 2 2 0 10 4 4 0 1 1 8 8 100 Reserved Reserved 101 Reserved Reserved 110 Reserved Reserved 1 1 1 Reserved Reserved Y M3 Burst Type 0 Sequential 1 Interleaved CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2 5 Reserved M12 11 10 9 M8 M7 M6 MO Valid Valid Operating Mode o o o o o o Normal Operation Normal Operation Reset DLL e o e o All other states reserved Figure 1 Mode Register Definition 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 10 ADVANCE 512Mb x4 x8 x16 DDR SDRAM figuration The remaining least significant address bit s is are used to select the starting location within the block The programmed burst length applies to both READ and WRITE bursts Burst Type Accesses within a given burst may be programmed to be either s
14. 2204 X p i _ J H um Case 2 tAc max and tDQSCK max bes as DOSCK MAx i tRPRE tRPST gt i 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Li 1 1 1 1 1 1 1 1 1 1 1 1 1 1 pos i i 1 5 NE D M 0 s X T 2 tHZ max E NOTE 1 DO n data out from column n subsequent elements are provided in the programmed order 221 TRANSITIONING DATA 1 2 Burst length 4 in the case shown 3 Enable auto precharge DON T CARE 4 ACT ACTIVE RA Row Address BA Bank Address 5 6 7 NOP commands are shown for ease of illustration other commands may be valid at these times The READ command can only be applied at T3 if tRAP is satisfied at T3 Refer to figure 27 27A and 28 for detailed DQS and DQ timing 512Mb x4 x8 x16 DDR SDRAM 64 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM BANK WRITE WITHOUT AUTO PRECHARGE oie a Ne oe IN CKE a COMMAND
15. 32 Power down mode tCK tCK MIN CKE LOW 50 ACTIVE STANDBY CURRENT CS HIGH CKE HIGH One bank 22 Active Precharge tRAS MAX tCK MIN DQ DM and DQS inputs changing twice per clock cycle Address and other control inputs changing once per clock cycle OPERATING CURRENT Burst 2 Reads Continuous burst One bank 22 48 active Address and control inputs changing once per clock cycle tCK MIN lout OMA OPERATING CURRENT Burst 2 Writes Continuous burst One bank 22 active Address and control inputs changing once per clock cycle tCK tCK MIN DQ DM and 20 inputs changing twice per clock cycle AUTO REFRESH CURRENT tRC 7 8125us 5 6 6 27 50 RC 7 81255 los 6 6 27 50 SELF REFRESH CURRENT CKE lt 0 2V Standard 1006 TBD TBD 11 Low power L 11 OPERATING CURRENT Four bank interleaving READs BL 4 with 7 TBD TBD 22 49 auto precharge with RC tRC MIN RC MIN Address and control inputs change only during Active READ or WRITE commands 512Mb x4 x8 x16 DDR SDRAM 47 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc Micron 512Mb x4 x8 x16 DDR SDRAM ADVANCE ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Notes 1 5 14 17 33 notes appear on pages 50 53 0 C lt TA lt
16. 70 0 2 5V 0 2V 2 5V 0 2V ACCHARACTERISTICS PARAMETER SYMBOL UNITS NOTES Access window of DQs from CK CK tac ns CK high level width tCH 30 CK low level width 30 Clock cycle time CL 2 5 tCK 2 5 ns 45 52 CL 2 2 ns 45 52 DQ and DM input hold time relative to DQS ns 26 31 DQ and DM input setup time relative to DQS tps ns 26 31 DQ and DM input pulse width for each input tDIPW ns 31 Access window of DQS from CK CK tDQSCK ns DQS input high pulse width tDQSH DQS input low pulse width tDQSL DQS DQ skew DQS to last DQ valid per group per access 0050 ns 25 26 Write command to first DQS latching transition tpass DQS falling edge to CK rising setup time tpss DQS falling edge from CK rising hold time tDSH Half clock period ns 34 Data out high impedance window from CK CK ns 18 42 Data out low impedance window from CK CK ns 18 43 Address and control input hold time fast slew rate ns 14 Address and control input setup time fast slew rate ns 14 Address and control input hold time slow slew rate ns 14 snot owe m M ns 20 005 hold DQS to first DQ to go non valid per access tHP ns 25 26 al a e DaWdsewud os ACTIVEtGPRECHARGEConmand as 38 40
17. Curves a The full variation in driver pull down current from minimum to maximum process tempera ture and voltage will lie within the outer bounding lines of the V I curve of Figure A b The variation in driver pull down current within nominal limits of voltage and tempera ture is expected but not guaranteed to lie within the inner bounding lines of the V I curve of Figure A The full variation in driver pull up current from minimum to maximum process tempera ture and voltage will lie within the outer bounding lines of the V I curve of Figure B d The variation in driver pull up current within nominal limits of voltage and temperature is expected but not guaranteed to lie within the inner bounding lines of the V I curve of Figure B Figure A Pull Down Characteristics T T lour mA Vout V 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 ADVANCE 512Mb x4 x8 x16 DDR SDRAM e The full variation in the ratio of the maximum to minimum pull up and pull down current should be between 71 and 1 4 for device drain to source voltages from 0 1V to 1 0 Volt and at the same voltage and temperature f The full variation in the ratio of the nominal pull up to pull down current should be unity 10 for device drain to source voltages from 0 1V to 1 0 volt 38 Reduced Output Drive Curves a The full variation in driver pull down current from minimum to maximum process
18. DCio 0 50 pF 24 Delta Input Capacitance Command and Address 0 50 pF 29 Delta Input Capacitance CK CK DC2 0 25 pF 29 Input Output Capacitance DQs DQS DM 4 0 5 0 pF Input Capacitance Command and Address 2 0 3 0 pF Input Capacitance CK CK Ci2 2 0 3 0 pF Input Capacitance CKE 2 0 3 0 pF Ipp SPECIFICATIONS AND CONDITIONS x4 x8 Notes 1 5 10 12 14 notes appear on pages 50 53 0 C lt lt 70 VDDQ 2 5V 0 2V 2 5V 0 2V MAX PARAMETER CONDITION SYMBOL 75 75Z 8 UNITS NOTES OPERATING CURRENT One bank Active Precharge tRC MIN 1550 TBD TBD mA 22 48 DQ DM and DQS inputs changing once per clock cyle Address and control inputs changing once every two clock cycles OPERATING CURRENT One bank Active Read Precharge Burst 2 Ipp1 TBD TBD mA 22 48 tRC tCK MIN lout OMA Address and control inputs changing once per clock cycle PRECHARGE POWER DOWN STANDBY CURRENT All banks idle Ipp2P 3 3 mA 23 32 Power down mode tCK LOW 50 IDLE STANDBY CURRENT CS HIGH All banks idle tCK MIN IDD2F 35 30 mA 51 CKE HIGH Address and other control inputs changing once per clock cycle Vin Vrer for DQ DQS and DM ACTIVE POWER DOWN STANDBY CURRENT One bank active Ipp3P 3 3 mA 23 32 Power down mode tCK
19. H H H NO OPERATION NOP continue previous operation Idle X X X X Any Command Otherwise Allowed to Bank m Row L L H H ACTIVE select and activate row Activating L H L H READ select column and start READ burst Active or L H L L WRITE select column and start WRITE burst Precharging L L H L PRECHARGE Read L L H H ACTIVE select and activate row Auto L H L H READ select column and start new READ burst 7 Precharge L H L L WRITE select column and start WRITE burst 7 9 Disabled L L H L PRECHARGE Write L L H H ACTIVE select and activate row Auto L H L H READ select column and start READ burst 7 8 Precharge L H L L WRITE select column and start new WRITE burst 7 Disabled L L H L PRECHARGE Read L L H H ACTIVE select and activate row With Auto L H L H READ select column and start new READ burst 7 3a Precharge L H L L WRITE select column and start WRITE burst 7 9 3a L L H L PRECHARGE Write L L H H ACTIVE select and activate row With Auto L H L H READ select column and start READ burst 7 3a Precharge L H L L WRITE select column and start new WRITE burst 7 3a L L H L PRECHARGE NOTE 1 This table applies when CKE was HIGH and is HIGH see Truth Table 2 and after tXSNR has been met if the previous state was self refresh 2 This table describes alternate bank operation except where noted i e the current state is for bank n and the commands shown are those allowed to be issu
20. MAX MAX units 0 45 oss ns ns ns ns ns ns ns ns ns ns 0 75 P P 02 02 ns 66 Micron Technology Inc reserves the right to change products ev Pu Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM WRITE DM OPERATION 5 _ wu uc dM COMMAND XX ACT XX X nee XX nop TDK XX PRE X ERES IZ e NOU e LL x16 A9 A11 A12 BA1 Bank x MM ZMK X ps Nf A WPRES tWPRE tDQSL 5 wPST OR BR inei mud 5 J NOTE 1 DI n data out from column n subsequent elements are provided the programmed order 2 TRANSITIONING DATA Burst length 4 in the case shown Disable auto precharge DON T CARE Don t Care if A10 is HIGH at T8 PRE PRECHARGE ACT ACTIVE RA Row Address BA Bank Address NOP commands are shown for ease of illustration other commands may be valid at these times tDSH is applicable during 055 and is referenced from CK T4 or T5 toss is applicable durin
21. READs and center aligned with data for WRITEs The x16 offering has two data strobes one for the lower byte and one for the upper byte The 512Mb DDR SDRAM operates from a differen tial clock CK and the crossing of CK going HIGH and going LOW will be referred to as the positive edge of CK Commands address and control signals are registered at every positive edge of CK Input data is registered on both edges of DQS and output data is referenced to both edges of DQS as well as to both edges of CK Read and write accesses to the DDR SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence Accesses begin with the regis 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 tration of an ACTIVE command which is then followed by a READ or WRITE command The address bits regis tered coincident with the ACTIVE command are used to select the bank and row to be accessed The address bits registered coincident with the READ or WRITE com mand are used to select the bank and the starting col umn location for the burst access The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2 4 or 8 locations An auto precharge function may be enabled to provide a self timed row precharge that is initiated at the end of the burst access As with standard SDR SDRAMs the pipelined multibank architecture of DDR SDRAMs
22. Shown with nominal tDQSCK and 2050 6 Example applies only when READ commands are issued to same device Figure 8 Consecutive READ Bursts ADVANCE x4 x8 x16 DDR SDRAM CK COMMAND ADDRESS DQS DQ CK COMMAND Coe XD Cen XU OD ADDRESS i ALD EDD CMD DUL MN FX o DON T CARE TRANSITIONING DATA NOTE 1 DO n or b data out from column n or column b 2 Burst length 4 or 8 if 4 the bursts are concatenated if 8 the second burst interrupts the first 3 Three subsequent elements of data out appear in the programmed order following DO n 4 Three or seven subsequent elements of data out appear in the programmed order following DO b 5 Shown with nominal tDQSCK 0050 6 Example applies when READ commands are issued to different devices or nonconsecutive READs Figure 9 Nonconsecutive READ Bursts 512Mb x4 x8 x16 DDR SDRAM 20 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc COMMAND COMMAND ADVANCE 512Mb x4 x8 x16 DDR SDRAM ADDRESS DQS DQ CK CK ADDRESS DQS i 29 _ Go X 99 DON T CARE TRANSITIONING DATA NOTE 1 DO n or x or b or g data out
23. T3 XTn gt DQ First data no longer valid T2 T2n T3 T3n 200 207 and 1095 collectively6 T2 T2n T3 T3n Data Valid Data Valid Data Valid Data Valid i window window window window 129503 20503 120503 109503 29 Q Q Q Q 9 5 UDQS a DQ Last data valid 007 DQ 007 DQ D DQ DQ First data no longer valid 2 1 ct D DQ Last data valid DQ First data no longer valid 008 2015 UDQS collectively Data Valid Data Valid Data Valid Data Valid window window window window NOTE 1 DQs transitioning after DQS transition define 0050 4 tQH is derived from tHP tHP tQHS window LDQS defines the lower byte and 5 tHP is the lesser of tCL or tCH clock transition UDQS defines the upper byte collectively when a bank is active 2 000 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 or DQ7 6 The data valid window is derived for each 3 10050 is derived at each DQS clock edge and is not 005 transition and is minus 10050 cumulative over time and begins with DQS transition 7 DQ8 DQ9 DQ10 D11 DQ12 DQ13 DQ14 or DQ15 and ends with the last valid transition of DQs Figure 29 A x16 Data Output Timing 0050 and Data Valid Window 512Mb x4 x8 x16 DDR SDRAM 57 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 M
24. are provided in the programmed order 2 1 TRANSITIONING DATA 1 2 Burst length 4 in the case shown 3 Disable auto precharge DON T CARE 4 Don t Care if A10 is HIGH at T5 5 PRE PRECHARGE ACT ACTIVE RA Row Address BA Bank Address 6 7 8 NOP commands are shown for ease of illustration other commands may be valid at these times The PRECHARGE command can only be applied at T5 if RAS minimum is met Refer to figure 27 27A and 28 for detailed DQS and DQ timing 512Mb x4 x8 x16 DDR SDRAM 63 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev Pub 4 01 2001 Micron Technology Inc ADVANCE x4 x8 x16 DDR SDRAM BANK READ WITH AUTO PRECHARGE 71 0 VEU X LT LLL OK e 7777 sone WWE cL 2 tRAS E ZEN 7 77 TL 7 1 Z ZZ 7 77 7 m gH m m H HM NM m m E m JL m m a m m m m m m m Ir mmu BH m m E E HE NM BH RN 15 m m mt Case 1 tac miny and tpQscKminy 1 tDQSCK min 4 tLZ min
25. from a properly terminated bus will provide signifi cantly different voltage values Vin overshoot VppQ 1 5V for a pulse width lt 3ns and the pulse width can not be greater than 1 3 of the cycle rate VIL undershoot VIL MIN 1 5V for a pulse width lt 3ns and the pulse width can not be greater than 1 3 of the cycle rate 41 and must track each other This maximum value is derived from the referenced test load In practice the values obtained in a typical terminated design may reflect up to 310ps less for HZmax and the last DVW HZ MAX will prevail over IDQSCK MAX RPST MAX condition For slew rates greater than 1V ns the LZ transition will start about 310ps earlier LZ MIN will prevail over a DQSCK MIN condition During initialization VDDQ Vrr and Vrer must be equal to or less than Vpp 0 3V Alternatively may be 1 35V maximum during power up even if Vpp Vppo are 0 volts provided a minimum of 42 ohms of series resistance is used between the supply and the input pin 40 43 44 Figure C Pull Down Characteristics lout mA Vout V 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 45 51 52 lour mA 53 ADVANCE 512Mb x4 x8 x16 DDR SDRAM The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz As such future die ma
26. or 8 ADVANCE 512Mb x4 x8 x16 DDR SDRAM PART NUMBER MT46V128M4TG xx MT46V128M4TG xxL CONFIGURATION 128 Meg x4 Full Drive 128 Meg x4 Full Drive DRIVE LEVEL REFRESH OPTION Standard Low Power MT46V64M8TG xx 64 Meg x 8 Full Drive Standard MT46V64M8TG xxL 64 Meg x 8 Full Drive Low Power MT46V32M16TG xx 32 Meg x 16 Programmable Drive Standard MT46V32M16TG xxL 32 Meg x 16 Low Power Programmable Drive GENERAL DESCRIPTION The 512Mb DDR SDRAM is a high speed CMOS dynamic random access memory containing 536 870 912 bits It is internally configured as a quad bank DRAM The 512Mb DDR SDRAM uses a double data rate architecture to achieve high speed operation The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I O pins Asingle read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n bit wide one clock cycle data transfer at the internal DRAM core and two corresponding n bit wide one half clock cycle data transfers at the I O pins A bidirectional data strobe DQS is transmitted ex ternally along with data for use in data capture at the receiver DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs DQS is edge aligned with data for
27. or specifications without notice 512Mx4x8x16DDR B p65 Rev Pub 4 01 2001 Micron Technology Inc Micron FUNCTIONAL DESCRIPTION The 512Mb DDR SDRAM is a high speed CMOS dynamic random access memory containing 536 870 912 bits The 512Mb DDR SDRAM is internally configured as a quad bank DRAM The 512Mb DDR SDRAM uses a double data rate architecture to achieve high speed operation The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I O pins A single read or write access for the 512Mb DDR SDRAM consists of a single 2n bit wide one clock cycle data transfer at the internal DRAM core and two correspond ing n bit wide one half clock cycle data transfers at the I O pins Read and write accesses to the DDR SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence Accesses begin with the regis tration of an ACTIVE command which is then followed by a READ or WRITE command The address bits regis tered coincident with the ACTIVE command are used to select the bank and row to be accessed BAO BAI select the bank 0 12 select the row The address bits registered coincident with the READ or WRITE com mand are used to select the starting column location for the burst access Prior to normal operation the DDR SDRAM must be initialized The fol
28. tempera ture and voltage will lie within the outer bounding lines of the V I curve of Figure C b The variation in driver pull down current within nominal limits of voltage and tempera ture is expected but not guaranteed to lie within the inner bounding lines of the V I curve of Figure C c The full variation in driver pull up current from minimum to maximum process tempera ture and voltage will lie within the outer bounding lines of the V I curve of Figure D d The variation in driver pull up current within nominal limits of voltage and temperature is expected but not guaranteed to lie within the inner bounding lines of the V I curve of Figure D e The full variation in the ratio of the maximum to minimum pull up and pull down current should be between 71 and 1 4 for device drain to source voltages from 0 1V to 1 0 Volt and at the same voltage and temperature f The full variation in the ratio of the nominal pull up to pull down current should be unity 10 for device drain to source voltages from 0 1V to 1 0 Volt Figure B Pull Up Characteristics Minimum lour mA 0 0 0 5 1 0 1 5 2 0 2 5 VDDQ Vout V Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron NOTES continued 39 The voltage levels used are derived from a minimum Vpn level and the refernced test load In practice the voltage levels obtained
29. the Command Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled 8 Requires appropriate DM masking 9 A WRITE command may be applied after the completion of the READ burst otherwise a BURST TERMI NATE must be used to end the READ burst prior to asserting a WRITE command 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 42 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc ADVANCE 512Mb 4 x8 x16 Macr on DDR SDRAM ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Vpp Supply Voltage Relative to Vss 1V to 3 6V Maximum Ratings may cause permanent damage to VDDQ Supply Voltage Relative to Vss 1V to 3 6V the device This is a stress rating only and functional Vrer and Inputs Voltage Relative to 55 1V to 3 6V operation of the device at these or any other conditions Pins Voltage Relative to Vss 0 5V to 0 5V above those indicated in the operational sections of Operating Temperature ambient 0 C to 70 C this specification is not implied Exposure to absolute Storage Temperature plastic 55 C to 150 C maximum rating conditions for extended periods may Power Dissipation IW affect reliability Short Circuit Output Current
30. 0 4 19 2 13 6 15 7 19 2 18 7 13 0 23 6 16 9 19 3 13 0 23 6 0 6 19 9 22 1 15 7 28 0 19 4 22 9 15 7 28 0 25 0 18 2 32 2 21 5 26 5 18 2 32 2 24r 282 208 358 233 301 204 358 0s 313 224 398 28 336 216 395 32 250 31 18 432 ap zi 403 221 467 500 278 31 222 500 283 458 223 533 61 286 484 224 563 587 287 s07 226 587 289 529 227 614 5 289 550 227 635 655 290 568 228 656 er 292 587 229 67 8 292 600 29 698 ne 293 12 230 716 55 29 733 296 638 232 7564 399 558 233 797 NOTE The above characteristics are specified under best worst and nominal process variation conditions 512Mb x4 x8 x16 DDR SDRAM 5 5 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc ADVANCE 4 512Mb x4 x8 x16 DDR SDRAM T1 T2 T2n T3 T3n T4 DQ First data no longer valid DQ Last data valid DQ First data no longer valid All DQs and 005 collectively lt 23 T T3n gt Earliest signal transition 22 Latest signal transition gt Data Data Data Data Vali
31. 01 65 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM BANK WRITE WITH AUTO PRECHARGE COMMAND X Ken XX 5 Xi OK Xi NOP X e ND e VC DD DR 00 x16 A0 A8 U MM 7X E X UL 7 7 VLA Wh x16 9 11 12 My DUI 7 7 m I LL ne ZZ Jes X VITE JL gt gt 1 RAS T tRP LLL 2 7 77 VB tWpRES WPRE tDQSL DQSH LLL 220 759 tps ton 222 TRANSITIONING DATA DI n data out from column n subsequent elements are provided in the programmed order Burst length 4 in the case shown DON T CARE Enable auto precharge NOTE 1 2 3 4 ACT ACTIVE RA Row Address BA Bank Address 5 6 7 NOP commands are shown for ease of illustration other commands may be valid at these times tDSH is applicable during 055 and is referenced from CK T4 or T5 tDSS is applicable during 055 and is referenced from CK T5 or TIMING PARAMETERS iN
32. 1 20 1 1 ns 8 0 200V ns 1 25 1 1 ns SLEW RATE DERATING VALUES Note 31 notes appear on pages 50 53 0 C x lt 70 VopQ 2 5V 0 2V 2 5V 0 2V DQ DM DQS 8 gs exi eswm 9e 9 l a T vm 5 95 l a T ewm e me Pe o os 1 512Mb x4 x8 x16 DDR SDRAM 49 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc Micron NOTES 1 2 10 11 All voltages referenced to Vss Tests for AC timing and electrical AC and DC characteristics may be conducted at nominal reference supply voltage levels but the related specifications and device operation are guaran teed for the full voltage range specified Outputs measured with equivalent load VTT 500 Reference Point 30pF AC timing and tests may use a swing of up to 1 5V in the test environment but input timing is still referenced to Vrer or to the crossing point for CK CK and parameter specifications are guaranteed for the specified AC input levels under normal use conditions The minimum slew rate for the input signals used to test the device is 1V ns in the range between and Vin ac The AC and DC input level specifications are as defined in the SSTL_2 Standard 1 th
33. 16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 ADVANCE 512Mb x4 x8 x16 DDR SDRAM Random 30 Write to Read Uninterrupting 31 Write to Read Interrupting 32 Write to Read Odd Interrupting 33 Write to Precharge Uninterrupting 34 Write to Precharge Interrupting 35 Write to Precharge Odd Interrupting 36 PRECH ALS c IE 37 POW DOWD 37 Truth Table 2 38 Truth Table 3 Current State Same 0 0 39 Truth Table 4 Current State Different Bank 41 Operating Conditions Absolute Maximum Ratings esse 43 DC Electrical and Operating Conditions 43 AC Input Operating Conditions 43 Clock Input Operating Conditions 44 Capacitance x4 x8 sssssssssssseeeeeeeeee 45 Specifications and Conditions x4 x8 45 Capacitance x16 eene 46 Specifications and Conditions x16 46 AC Electrical Characteristics Timing Table 47 Slew Rate Derating Table 48 Data Valid Window Derating 52 Voltage and Timing Waveforms Nominal Output Drive 53 Reduced Output Drive Curves x16
34. 184 339 240 277 184 3388 46 8 06 346 277 494 405 277 544 07 394 442 322 568 1 49 322 618 08 437 498 368 632 4 531 360 695 09 475 552 396 699 438 594 382 773 10 513 603 426 763 460 655 387 852 93 0 100 6 108 1 14 593 784 4 4 991 505 897 396 15 5 123 0 16 605 859 480 1084 510 1013 401 1304 136 7 144 2 19 953 1196 515 1187 404 150 5 156 9 21 628 991 496 1265 518 1293 406 163 2 169 6 176 0 24 1028 500 1350 523 145 2 40 9 1813 25 646 1038 502 1373 525 1505 41 0 187 6 2 6 192 9 198 2 NOTE The above characteristics are specified under best worst and nominal process variation conditions 512Mb x4 x8 x16 DDR SDRAM 54 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 Micron DDR SDRAM REDUCED OUTPUT DRIVE CHARACTERISTICS PULL DOWN CURRENT mA PULL UP CURRENT mA VOLTAGE NOMINAL NOMINAL NOMINAL NOMINAL V MINIMUM MAXIMUM LOW HIGH MINIMUM MAXIMUM 0 1 3 4 3 8 2 6 5 0 3 5 4 3 2 6 5 0 0 2 6 9 7 6 5 2 9 9 6 9 7 8 5 2 9 9 11 4 7 8 14 6 10 3 12 0 7 8 14 6 0 4 136 15 1 1
35. 2Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM VDDQ 2 3V minimum 1 670V for SSTL2 termination System Noise Margin Power Ground Crosstalk Signal Integrity Attenuation 1 560V ViHAC 1400V 1 300V ioy AC Noise 1 250V 1 225V seo Vvrer AC Noise 1 100V 0 940 VILAC Vinac Provides margin between Vol and VoL 0 83V2 for M Receiver SSTL2 termination NOTE 1 VoH MIN with test load is 1 927V 2 VoL MAX with test load is 0 373V 3 Numbers in diagram reflect nomimal V values utilizing circuit below Transmitter 250 250 Reference Point Figure 27 Input Voltage Waveform 512Mb x4 x8 x16 DDR SDRAM 44 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 decr on DDR SDRAM CLOCK INPUT OPERATING CONDITIONS Notes 1 5 15 16 30 notes appear on pages 50 53 0 C x T4 lt 70 C 2 5V x0 2V VDDQ 2 5V 0 2V PARAMETER CONDITION SYMBOL MIN MAX UNITS NOTES Clock Input Mid Point Voltage CK and CK 1 15 1 35 Clock Input Voltage Level CK and CK Vin Dc 0 3 VDDQ 0 3 Clock Input Dif
36. DDR SDRAM CK CK COMMAND KMD Cer OD NOP READ XD CoM NOP o 4 i MMM OM ca DX e on MD ZZ aat ZZ LK EC X ov pow 24 TRANSITIONING DATA 1 b data in for column m 2 interrupted burst of 4 e own two data elements are written 3 2 subsequent element of is a pli ied in the programmed o Piu owing DI b 4 tWTR is referenced from the fir st positive CK edge after the last data 5 A10 is LOW with the WRITE comma iuba a o prechar ies abled 6 DQS is required at T2 and T2n nominal case to regist 7 If the burst of 8 was used bid would 2 required a 5 Tan because the READ comman d would mask the last two data elem Figure 20 WRITE to READ Interrupting ADVANCE x4 x8 x16 DDR SDRAM 12055 10055 CL 2 ZZ OU MBA _ _ WM EMU X 4 Y CMLL NOTE 1 data in for column b DON T CARE E TRANSITIONING DATA 2 An interr rupted bur urst of 4 is shown one data element is written 3 twT WTR is referenced from the firs rst pos dis e CK edge after the last desir ed data in pair not the last two data elements 4 A10 is LOW with the WRITE ds nd auto pr s disabled 5 DQS is required d T2 and T2n n
37. E command as shown in Figure 14 The starting column and bank addresses are pro vided with the WRITE command and auto precharge is either enabled or disabled for that access If auto precharge is enabled the row being accessed is precharged at the completion of the burst For the ge neric WRITE commands used in the following illustra tions auto precharge is disabled During WRITE bursts the first valid data in ele ment will be registered on the first rising edge of DQS following the WRITE command and subsequent data elements will be registered on successive edges of DQS The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble the LOW state on DQS following the last data in ele ment is known as the write postamble The time between the WRITE command and the first corresponding rising edge of DQS DQSS is speci fied with a relatively wide range from 75 percent to 125 percent of one clock cycle All of the WRITE diagrams show the nominal case and where the two extreme cases i e 0055 MIN and 0055 MAX might not be intuitive they have also been included Figure 15 shows the nominal case and the extremes of 0055 for a burst of 4 Upon completion of a burst assuming no other commands have been initiated the DQs will re main High Z and any additional input data will be ig nored Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE comm
38. Figure 14 WRITE Command prior to the WTR period are written to the internal ar ray and any subsequent data in should be masked with DM as shown in Figure 21 Data for any WRITE burst may be followed by a subsequent PRECHARGE command To follow a WRITE without truncating the WRITE burst WR should be met as shown in Figure 22 Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Fig ures 23 and 24 Note that only the data in pairs that are registered prior to the WR period are written to the internal array and any subsequent data in should be masked with DM as shown in Figures 23 and 24 After the PRECHARGE command a subsequent command to the same bank cannot be issued until is met Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc ADVANCE J 512Mb x4 x8 x16 DDR SDRAM TO 1 T2 T2n T3 UK Seu A Ios A _ 4 tDQSS MAX uu DQS 0055 DQ 652 Ke AN ON ANN DON T CARE TRANSITIONING DATA NOTE 1 DI b data in for column b 2 Three subsequent elements of data in are applied in the programmed order following DI b 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 3 An uninterrupted burst of 4 is shown 4 A10 is LOW with the WRITE command auto precharge is disa
39. H H Bank Row 3 READ Select bank and column and start READ burst L H L H Bank Col 4 WRITE Select bank and column and start WRITE burst L H L L Bank Col 4 BURST TERMINATE L H H L X 8 PRECHARGE Deactivate row in bank or banks L L H L Code 5 AUTO REFRESH or SELF REFRESH L L L H X 6 7 Enter self refresh mode LOAD MODE REGISTER L L L L Op Code 2 TRUTH TABLE 1A DM OPERATION Note 10 NAME FUNCTION DM DQs NOTES Write Enable L Valid Write Inhibit X NOTE 1 CKE is HIGH for all commands shown except SELF REFRESH 2 BAO BAT select either the mode register or the extended mode register BAO 0 1 0 select the mode register 1 BA1 0 select extended mode register other combinations of BAO BA1 are reserved A0 A12 provide the op code to be written to the selected mode register 3 BAO BA1 provide bank address and A0 A12 provide row address BAO BA1 provide bank address 0 provide column address where i 9 for x16 9 11 for x8 and 9 11 12 for x4 A10 HIGH enables the auto precharge feature nonpersistent and A10 LOW disables the auto precharge feature 5 A10 LOW BAO BA1 determine which bank is precharged A10 HIGH all banks are precharged and BAO BA1 are Don t Care 6 This command is AUTO REFRESH if CKE is HIGH SELF REFRESH if CKE is LOW 7 Internal refresh counter controls row addressing all inputs and I Os are Don t Care except for CKE Applies only to read bursts with
40. RCD specification RCD MIN should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE CAS command can be entered For example a RCD specifi cation of 20ns with a 133 MHz clock 7 5ns period re sults in 2 7 clocks rounded to 3 This is reflected in Figure 5 which covers any case where 2 lt RCD MIN lt 3 Figure 5 also shows the same case for RCD the same procedure is used to convert other specification 0 12 limits from time units to clock cycles A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed precharged The mini BAO 1 mum time interval between successive ACTIVE com mands to the same bank is defined by RA Row Address A subsequent ACTIVE command to another bank BA Bank Address can be issued while the first bank is being accessed which results in a reduction of total row access over Fi head The minimum time interval between successive p igure 4 ACTIVE commands to different banks is defined by Activating a Specific Row in tRRD a Specific Bank TO T1 T2 T3 T4 T5 T6 T7 sete iy i pas Ste le ee ene gaa EE ETA COMMAND YX now DON T CARE Figure 5 Example Me
41. abled L H H L BURST TERMINATE 9 Write L H L H READ select column and start READ burst 10 11 Auto L H L L WRITE select column and start new WRITE burst 10 Precharge L L H L PRECHARGE truncate WRITE burst start PRECHARGE 8 11 Disabled NOTE 1 This table applies when CKE was HIGH and is HIGH see Truth Table 2 and after tXSNR has been met if the previous state was self refresh 2 This table is bank specific except where noted i e the current state is for a specific bank and the com mands shown are those allowed to be issued to that bank when in that state Exceptions are covered in the notes below 3 Current state definitions Idle The bank has been precharged and has been met Row Active A row in the bank has been activated and tRCD has been met No data bursts accesses and no register accesses are in progress Read A READ burst has been initiated with auto precharge disabled and has not yet terminated or been terminated Write A WRITE burst has been initiated with auto precharge disabled and has not yet terminated or been terminated 4 The following states must not be interrupted by a command issued to the same bank COMMAND INHIBIT or NOP commands or allowable commands to the other bank should be issued on any clock edge occur ring during these states Allowable commands to the other bank are determined by its current state and Truth Table 3 and according to Truth Table 4 Prechargi
42. alid data window are depicted in Figure 27 A detailed explana tion of DQSCK DQS transition skew to CK and data out transition skew to CK is depicted in Figure 28 Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command In either case a continuous flow of data can be maintained The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated The new READ command should be issued x cycles after the first READ com mand where x equals the number of desired data ele ment pairs pairs are required by the 2n prefetch ar chitecture This is shown in Figure 8 A READ com mand can be initiated on any clock cycle following a previous READ command Nonconsecutive read data is shown for illustration in Figure 9 Full speed random read accesses within a page or pages can be performed as shown in Figure 10 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 ADVANCE 512Mb x4 x8 x16 DDR SDRAM wet lU Mason sn x16 A0 A9 x16 A11 A12 EN AP A10 DIS AP BAG 8 CA Column Address BA Bank Address EN AP Enable Auto Precharge DIS AP Disable Auto Precharge DON T CARE Figure 6 READ Command 1 7 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Mic
43. allows for con current operation thereby providing high effective bandwidth by hiding row precharge and activation time An auto refresh mode is provided along with a power saving power down mode All inputs are com patible with the JEDEC Standard for SSTL 2 All full drive strength outputs are SSTL 2 Class II compat ible NOTE 1 Thefunctionality and the timing specifications discussed in this data sheet are for the DLL enabled mode ofoperation 2 Throughoutthe data sheet the various figures and text refer to DQs as DQ The DQ term is to be interpreted as any and all DQ collectively unless specifically stated otherwise Additionally the x16 is divided in to two bytes the lower byte and upper byte For the lower byte 000 through DQ7 DM refers to LDM and DQS refers to LDQS and for the upper byte DQ8 through DQ15 DM refers to UDM and DQS refers to UDQS Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron TABLE OF CONTENTS Functional Block Diagram 128 Meg x 4 4 Functional Block Diagram 64 Meg x 8 5 Functional Block Diagram 32 Meg x 16 6 Pin Descriptions 7 Functional Description 2 1 9 INitialiZatiON 9 Register Definition 1 9 Mode Register 9 Burst Length
44. and In either case a continuous flow of input data can be maintained The new WRITE command can be issued on any positive edge of clock following the previous WRITE command The first data element from the new burst is applied after either the last element of a com pleted burst or the last desired data element of a longer burst which is being truncated The new WRITE com mand should be issued x cycles after the first WRITE command where x equals the number of desired data element pairs pairs are required by the 2n prefetch architecture Figure 16 shows concatenated bursts of 4 An ex ample of nonconsecutive WRITEs is shown in Figure 17 Full speed random write accesses within a page or pages can be performed as shown in Figure 18 Data for any WRITE burst may be followed by a subsequent READ command To follow a WRITE with out truncating the WRITE burst WTR should be met as shown in Figure 19 Data for any WRITE burst may be truncated by a subsequent READ command as shown in Figure 20 Note that only the data in pairs that are registered 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 26 ADVANCE 512Mb x4 x8 x16 DDR SDRAM CK CK CKE HIGH cast 7 v MUL x4 0 9 A11 12 x16 A0 A9 X16 A11 A12 EN AP A10 DIS AP BAO 1 MULL CA Column Address BA Bank Address EN AP Enable Auto Precharge DIS AP Disable Auto Precharge DON T CARE
45. ation of the DDR SDRAM and is analogous to CAS BEFORE RAS CBR REFRESH FPM EDO DRAMS This com mand is nonpersistent so it must be issued each time a refresh is required The addressing is generated by the internal refresh controller This makes the address bits a Don t Care during an AUTO REFRESH command The 512Mb DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7 8125ys maximum To allow for improved efficiency in scheduling and switching between tasks some flexibility in the abso lute refresh interval is provided A maximum of eight AUTO REFRESH command can be posted to any given DDR SDRAM meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7 8125 6 70 3115 This maximum absolute interval is to allow 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR 65 Rev B Pub 4 01 ADVANCE 512Mb x4 x8 x16 DDR SDRAM future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles with out allowing excessive drift in AC between updates Although not a JEDEC requirement to provide for future functionality features CKE must be active High during the AUTO REFRESH period The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends later SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM even if the rest of the system is powere
46. auto precharge disabled this command is undefined and should not be used for READ bursts with auto precharge enabled and for WRITE bursts 9 DESELECT and NOP are functionally interchangeable Used to mask write data provided coincident with the corresponding data 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc 13 Micron DESELECT The DESELECT function CS HIGH prevents new commands from being executed by the DDR SDRAM The DDR SDRAM is effectively deselected Operations already in progress are not affected NO OPERATION NOP The NO OPERATION NOP command is used to instruct the selected DDR SDRAM to perform a NOP CS LOW This prevents unwanted commands from being registered during idle or wait states Operations already in progress are not affected LOAD MODE REGISTER The mode registers are loaded via inputs 0 12 See mode register descriptions in the Register Defini tion section The LOAD MODE REGISTER command can only be issued when all banks are idle and a subse quent executable command cannot be issued until is met ACTIVE The ACTIVE command is used to open or activate a row in a particular bank for a subsequent access The value on the BAO BAI inputs selects the bank and the address provided on inputs 0 12 selects the row This
47. b 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 Macr on DDR SDRAM PIN DESCRIPTIONS TSOP PIN NUMBERS SYMBOL DESCRIPTION 45 46 CK CK Clock CK and CK are differential clock inputs All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK Output data DQs and DQS is referenced to the crossings of CK and CK Clock Enable CKE HIGH activates and CKE LOW deactivates the internal clock input buffers and output drivers Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operations all banks idle or ACTIVE POWER DOWN row ACTIVE in any bank CKE is synchronous for POWER DOWN entry and exit and for SELF REFRESH entry CKE is asynchronous for SELF REFRESH exit and for disabling the outputs CKE must be maintained HIGH throughout read and write accesses Input buffers excluding CK CK and CKE are disabled during POWER DOWN Input buffers excluding CKE are disabled during SELF REFRESH CKE is an SSTL 2 input but will detect an LVCMOS LOW level after Voo is applied Chip Select CS enables registered LOW and disables regis tered HIGH the command decoder All commands are masked when CS is registered HIGH CS provides for external bank selection on systems with multiple banks CS is considered part of the command code 23 22 21 RAS CAS Command Inputs RAS CAS and WE along with CS define the WE command being e
48. banks are idle and no bursts are in progress and the controller must wait the specified time before initiating the subsequent operation Violating either of these requirements will result in unspecified opera tion Mode register bits A0 A2 specify the burst length A3 specifies the type of burst sequential or inter leaved A4 A6 specify the CAS latency and A7 A12 specify the operating mode Burst Length Read and write accesses to the DDR SDRAM are burst oriented with the burst length being program mable as shown in Figure 1 The burst length deter mines the maximum number of column locations that can be accessed for a given READ or WRITE command Burst lengths of 2 4 or 8 locations are available for both Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron the sequential and the interleaved burst types Reserved states should not be used as unknown operation or incompatibility with future versions may result When a READ or WRITE command is issued a block of columns equal to the burst length is effectively se lected All accesses for that burst take place within this block meaning that the burst will wrap within the block if a boundary is reached The block is uniquely se lected by Al Ai when the burst length is set to two by A2 Ai when the burst length is set to four and by A3 Ai when the burst length is set to eight where Ai is the
49. bled Figure 15 WRITE Burst ADVANCE 512Mb x4 x8 x16 DDR SDRAM COMMAND WRITE WRITE idi tDQSS NOM aan 00 2 IML lames 0 0 0 NA 2 2 2 DON T CARE TRANSITIONING DATA NOTE 1 DI b etc data in for column b etc 2 Three subsequent elements of data in are applied in the programmed order following DI b 3 Three subsequent elements of data in are applied in the programmed order following DI n 4 An uninterrupted burst of 4 is shown 5 Each WRITE command may be to any bank Figure 16 Consecutive WRITE to WRITE 512Mb x4 x8 x16 DDR SDRA 28 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Tecl ADVANCE 512Mb x4 x8 x16 DDR SDRAM COMMAND oD 077 X2 CXD ADDRESS EX EDU TTD TTD tDQSS NOM 2055 005 LAN IN RON DON T TRANSITIONING DATA NOTE 1 DI b etc data in for column b etc 2 Three subsequent elements of data in are applied in the programmed order following DI b 3 Three subsequent elements of data in are applied in the programmed order following DI n 4 An uninterrupted burst of 4 is shown 5 Each WRITE command may be to any bank FIGURE 17 Nonconsecu
50. d Valid Valid Valid window window window window NOTE 1 DQs transitioning after DQS transition define 0050 window DQS transitions at T2 and at T2n are an early DQS at T3 is a nominal DQS and at T3n is a late DQS 2 For a x4 only two DQs apply 3 tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid transition of DQs 4 tQH is derived from tHP tQH tHP tQHS 5 tHP is the lesser of tCL or tCH clock transition collectively when a bank is active 6 The data valid window is derived for each DQS transitions and is defined as minus tDQSQ Figure 29 x4 x8 Data Output Timing DQSQ QH and Data Valid Window 512Mb x4 x8 x16 DDR SDRAM 56 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM 0 0A tup tup s tp tH tp s tup 5 gt 4 4 gt i 129503 209503 29503 00503 gt 1095 DQ Last data valid 2 DQ2 DQ2 202 202 DQ2 DQ 5 DQ First data no longer valid 2 DQ Last data valid A T2 X Tan D
51. d down When in the self refresh mode the DDR SDRAM retains data without external clocking The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled LOW The DLL is automatically disabled upon entering SELF RE FRESH and is automatically enabled upon exiting SELF REFRESH 200 clock cycles must then occur before a READ command can be issued Input signals except CKE are Don t Care during SELF REFRESH The procedure for exiting self refresh requires a se quence of commands First CK must be stable prior to CKE going back HIGH Once CKE is HIGH the DDR SDRAM must NOP commands issued for XSNR because time is required for the completion of any in ternal refresh in progress A simple algorithm for meet ing both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other com mand Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM Operations BANK ROW ACTIVATION Before any READ or WRITE commands can be is sued to a bank within the DDR SDRAM a row in that bank must be opened This is accomplished via the ACTIVE command which selects both the bank and the row to be activated as shown in Figure 4 After a row is opened with an ACTIVE command a READ or WRITE command may be issued to that row RAS subject to the
52. e is the state of the DDR SDRAM immediately prior to clock edge n 3 COMMAND is the command registered at clock edge n and ACTION is a result of COMMAND 4 All states and sequences not shown are illegal or reserved 5 DESELECT NOP commands should be issued any clock edges occurring during the period A minimum of 200 clock cycles is needed before applying a READ command for the DLL to lock 512Mb x4 x8 x16 DDR SDRAM 38 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev Pub 4 01 2001 Micron Technology Inc ADVANCE 7 512Mb x4 x8 x16 dcr on DDR SDRAM TRUTH TABLE 3 CURRENT STATE BANK n COMMAND TO BANK n Notes 1 6 notes appear below and on next page CURRENT STATE CS IRAS CAS WE COMMAND ACTION NOTES Any H X X X DESELECT NOP continue previous operation L H H H NO OPERATION NOP continue previous operation L L H H ACTIVE select and activate row Idle L L L H AUTO REFRESH 7 L L L L LOAD MODE REGISTER 7 L H L H READ select column and start READ burst 10 Row Active L H L L WRITE select column and start WRITE burst 10 L L H L PRECHARGE deactivate row in bank or banks 8 Read L H L H READ select column and start new READ burst 10 Auto L H L L WRITE select column and start WRITE burst 10 12 Precharge L L H L PRECHARGE truncate READ burst start PRECHARGE 8 Dis
53. e limit The device will operate with a greater value for this parameter but system performance bus turnaround will degrade accordingly This is not a device limit The device will operate with a negative value but system performance could be degraded due to bus turnaround It is recommended that DQS be valid HIGH or LOW on or before the WRITE command The case shown DQS going from High Z to logic LOW applies when no WRITEs were previously in progress on the bus If a previous WRITE was in progress DQS could be HIGH during this time depending on DQSS MIN or for Ipp measurements is the smallest multiple of CK that meets the minimum absolute value for the respective parameter RAS max for measurements is the largest multiple of CK that meets the maximum absolute value for The refresh period 64ms This equates to an Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron NOTES continued 24 25 26 27 average refresh rate of 7 8125us However AUTO REFRESH command must be asserted at least once every 70 3118 burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed The I O capacitance per DQS and DQ byte group will not differ by more than this maximum amount for any given device The valid data window is derived by achieving other specifica
54. e receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above below the DC input LOW HIGH level is expected to equal 0 2 of the transmit ting device and to track variations in the DC level of the same Peak to peak noise non common mode on may not exceed 2 percent of the DC value Thus from VppQ 2 Vrer is allowed 25mvV for DC error and an additional 25mvV for AC noise This measurement is to be taken at the nearest VnEr by pass capacitor Vit is not applied directly to the device Vrr is a system supply for signal termination resistors is expected to be set equal and must track variations in the DC level of Vnzr Vip is the magnitude of the difference between the input level on CK and the input level on CK The value of Vix is expected to equal VbppQ 2 of the transmitting device and must track variations in the DC level of the same Ipp is dependent on output loading and cycle rates Specified values are obtained with minimum cycle time at CL 2 for 75Z and 8 CL 2 5 for 75 with the outputs open Output Enables on chip refresh and address counters 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 50 12 13 14 15 16 17 18 19 20 21 22 23 ADVANCE 512Mb x4 x8 x16 DDR SDRAM sp
55. ecifications are tested after the device is properly initialized and is averaged at the defined cycle rate This parameter is sampled Vpp 2 5V 0 2V VDDQ 2 5V 0 2V Vss f 100 MHz 25 C Vour pc 0 2 Vour peak to peak 0 2V DM input is grouped with I O pins reflecting the fact that they are matched in loading Command Address input slew rate 0 5V ns For 75 with slew rates 1V ns and faster 15 and are reduced to 900ps If the slew rate is less than 0 5V ns timing must be derated 15 has an additional 50ps per each 100mV ns reduction in slew rate from the 500mV ns has Ops added that is it remains constant If the slew rate exceeds 4 5V ns functionality is uncertain The CK CK input reference level for timing referenced to CK CK is the point at which CK and CK cross the input reference level for signals other than CK CK is Inputs are not recognized as valid until VREF stabilizes Exception during the period before stabilizes CKE lt 0 3 x VDDQ is recognized as LOW The output timing reference level as measured at the timing reference point indicated in Note 3 is Vrr HZ and 12 transitions occur in the same access time windows as valid data transitions These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving HZ or begins driving LZ The maximum limit for this parameter is not a devic
56. ed to bank m assuming that bank m is in such a state that the given command is allowable Exceptions are covered in the notes below Notes continued on next page 512Mb x4 x8 x16 DDR SDRAM 41 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc ADVANCE d 512Mb x4 x8 x16 DDR SDRAM NOTE continued 3 Current state definitions Idle The bank has been precharged and RP has been met Row Active A row in the bank has been activated and tRCD has been met No data bursts accesses and no register accesses are in progress Read A READ burst has been initiated with auto precharge disabled and has not yet terminated or been terminated Write A WRITE burst has been initiated with auto precharge disabled and has not yet terminated or been terminated Read with Auto Precharge Enabled See following text 3a Write with Auto Precharge Enabled See following text 3a 3a 3b The read with auto precharge enabled or WRITE with auto precharge enabled states can each be broken into two parts the access period and the precharge period For read with auto precharge the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE com mand that still accesses all of the data in the burst For write w
57. egister must be loaded when all banks are idle and no bursts are in progress and the controller must wait the specified time before initiat ing any subsequent operation Violating either of these requirements could result in unspecified operation Output Drive Strength The normal drive strength for all outputs are speci fied to be SSTL2 Class II The x16 supports an option for reduced drive This option is intended for the sup port of the lighter load and or point to point environ ments The selection of the reduced drive strength will alter the DQs and DQSs from SSTI2 Class II drive strength to a reduced drive strength which is approxi mately 54 of the SSTL2 Class II drive strength The Micron 32Meg x16 device supports a programmable drive strength option DLL Enable Disable The DLL must be enabled for normal operation DLL enable is required during power up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evalua tion When the device exits self refresh mode the DLL is enabled automatically Any time the DLL is enabled 200 clock cycles must occur before a READ command can be issued 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 ADVANCE 512Mb x4 x8 x16 DDR SDRAM 1 12 11 10 A9 A8 A7 A5 A4 A2 A1 0 Address Bus ti 13 A2 11 10 9 8 77 6 5 4 3 E 0111 Operating M
58. ency is the delay in clock cycles be tween the registration of a READ command and the availability of the first bit of output data The latency can be set to 2 or 2 5 clocks as shown in Figure 2 If a READ command is registered at clock edge n and the latency is m clocks the data will be available nominally coincident with clock edge n m Table 2 indicates the operating frequencies at which each CAS latency setting can be used Reserved states should not be used as unknown operation or incompatibility with future versions may result T2n T3n re ue E P ot COMMAND x NOP D 005 tan DQ amp X 2 bu T3n ARX COMMAND READ DC IK NOP DD x oer _ Burst Length 4 in the cases shown Shown with nominal and nominal tDSDQ TRANSITIONING DATA DON T CARE Figure 2 CAS Latency 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 ADVANCE 512Mb x4 x8 x16 DDR SDRAM Table 2 CAS Latency CL ALLOWABLE OPERATING FREQUENCY MHz SPEED CL 2 cL 2 5 75Z 75 lt f lt 133 75 lt f lt 133 75 75 lt f lt 100 75 lt f lt 133 8 75 lt f lt 100 75 lt lt 125 Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 A12 each
59. equential or interleaved this is referred to as the burst type and is selected via bit M3 The ordering of accesses within a burst is deter mined by the burst length the burst type and the start ing column address as shown in Table 1 Table 1 Burst Definition Burst Starting Column Order of Accesses Within a Burst Length Address Type Sequential Type Interleaved 0 1 0 1 1 0 1 0 0 1 2 3 0 1 2 3 1 2 3 0 1 0 3 2 2 3 0 1 2 3 0 1 3 0 1 2 3 2 1 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 NOTE 1 For a burst length of two A1 Ai select the two data element block AO selects the first access within the block 2 For a burst length of four A2 Ai select the four data element block 0 1 select the first access within the block 3 For a burst length of eight A3 Ai select the eight data element block 0 2 select the first access within the block 4 Whenever a boundary of the block is reached within a given sequence above the following access wraps within the block Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron Read Latency The READ lat
60. eting tRCD MIN When 2 lt RCD RRD lt 512Mb x4 x8 x16 DDR SDRAM 1 6 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev Pub 4 01 2001 Micron Technology Inc Micron READs READ bursts are initiated with a READ command as shown in Figure 6 The starting column and bank addresses are pro vided with the READ command and auto precharge is either enabled or disabled for that burst access If auto precharge is enabled the row being accessed is precharged at the completion of the burst For the ge neric READ commands used in the following illustra tions auto precharge is disabled During READ bursts the valid data out element from the starting column address will be available fol lowing the CAS latency after the READ command Each subsequent data out element will be valid nominally at the next positive or negative clock edge at the next crossing of CK and CK Figure 7 shows general timing for each possible CAS latency setting DQS is driven by the DDR SDRAM along with output data The initial LOW state on DQS is known as the read preamble the LOW state coincident with the last data out element is known as the read postamble Upon completion ofa burst assuming no other com mands have been initiated the DQs will go High Z A detailed explanation of 10050 valid data out skew data out window hold the v
61. f the burst length is 2 the BST command shown can be NOP 4 One subsequent element of data out appears in the programmed order following DO n 5 Data in elements are applied following DI b in the programmed order 6 Shown with nominal tDQSCK and tDQSQ 7 BST BURST TERMINATE command page remains open XC Figure 12 READ to WRITE ADVANCE 512Mb x4 x8 x16 DDR SDRAM UK UX XD LLL m 2 v 2 2 2 1 1 1 i 1 1 DQ CK CK COMMANDS ADDRESS DQS DON T CARE TRANSITIONING DATA 1 DO n data out from column n 2 Burst length 4 or an interrupted burst of 8 3 Three subsequent elements of data out appear in the programmed order following DO n 4 Shown with nominal tDQSCK and 2050 5 READ to PRECHARGE equals two clocks which allows two data pairs of data out 6 A READ command with AUTO PRECHARGE enabled would cause a precharge to be performed at x number of clock cycles after the READ command where x 2 7 PRE PRECHARGE command ACT ACTIVE command Figure 13 READ to PRECHARGE 512Mb x4 x8 x16 DDR SDRAM 2 5 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc Micron WRITEs WRITE bursts are initiated with a WRIT
62. f the device While in power down CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM while all other input signals are Don t Care The power down state is synchronously exited when CKE is registered HIGH in conjunction with a NOP or DESELECT command A valid executable command may be applied one clock cycle later Ta1 Ta2 COMMAND VALID XX NOP UN NOP VX VALID READ WRITE access progress Enter power down mode Exit power down mode DON T CARE Figure 26 Power Down 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 37 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 Micron DDR SDRAM TRUTH TABLE 2 CKE Notes 1 4 CKE 1 CKE CURRENT STATE COMMAND ACTION NOTES L L Power Down X Maintain Power Down Self Refresh X Maintain Self Refresh L H Power Down DESELECT or NOP Exit Power Down Self Refresh DESELECT or NOP Exit Self Refresh 5 H L All Banks Idle DESELECT or NOP Precharge Power Down Entry Bank s Active DESELECT or NOP Active Power Down Entry All Banks Idle AUTO REFRESH Self Refresh Entry H H See Truth Table 3 NOTE 1 is the logic state of CKE at clock edge was the state of CKE at the previous clock edge 2 Current stat
63. ferential Voltage CK and CK 0 36 VDDQ 0 6 Clock Input Differential Voltage CK and 0 7 VDDQ 0 6 Clock Input Crossing Point Voltage CK CK Vix ac 0 5 x VDDQ 0 2 0 5 x VDDQ 0 2 2 80 Maximum Clock Level CK 1 45v 54 4 1 2 VID DO 1 25v VIX AC VID 1 05 ________ 4 CK 0 30 Minimum Clock Level NOTE 1 This provides a minimum of 1 15v to a maximum of 1 35v and is always half of VDDQ 2 CK and CK must cross in this region 3 CK and CK must meet at least MD DC min when static and is centered around VMP DC 4 CK and CK must have a minimum 700mv peak to peak swing 5 CK or CK may not be more positive than DDQ 0 3v or more negative than Vss 0 3v 6 For AC operation all DC clock requirements must also be satisfied 7 Numbers in diagram reflect nominal values FIGURE 28 SSTL 2 CLOCK INPUT 512Mb x4 x8 x16 DDR SDRAM Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 45 2001 Micron Technology Inc Micron CAPACITANCE x4 x8 Note 13 notes appear on pages 50 53 ADVANCE 512Mb x4 x8 x16 DDR SDRAM PARAMETER SYMBOL MIN MAX UNITS NOTES Delta Input Output Capacitance DQs DQS DM
64. fications without notice 512Mx4x8x16DDR B p65 Rev Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM BANK READ WITHOUT AUTO PRECHARGE CKE Y COMMAND oF XX ACT XK uad READ XX 6 XX PRE nop X e i p ONBBANES o tis UH i i pe cl TE MMM MMMM DMM e DD cL 2 MEM RAS ME gt MMM LLL TOPPER COPECO eee ee ee ee ee ee ee ee ee ee Case 1 and tDQSCK min tDQSCK mIN i tRPST 095 REN Ene twm J J tHZ Min J m m m m m m mm m m h m m mim m m M m m m m m mm m m m m m m m m m u m m DOScK MA gt Case 2 and tDQSCK max tRPRE tRPST 005 tLZ MAX i i i 1 1 7 DO gt is CT X tLZ max _ A HZ MAX 27 NOTE 1 DOn data out from column n subsequent elements
65. from column n or column x or column b or column 0 2 Burst length 2 or 4 or 8 if 4 or 8 the following burst interrupts the previous 3 n or x or b or g indicates the next data out following DO n or DO x or DO b or DO respectively 4 READs are to an active row in any bank 5 Shown with nominal tDQSCK 0050 Figure 10 Random READ Accesses Micron READs continued Data from any READ burst may be truncated with a BURST TERMINATE command as shown in Figure 11 The BURST TERMINATE latency is equal to the READ CAS latency the BURST TERMINATE command should be issued x cycles after the READ command where x equals the number of desired data element pairs pairs are required by the 2n prefetch architec ture Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued If truncation is necessary the BURST TER MINATE command must be used as shown in Figure 12 The 10055 MIN case is shown the 10055 case has a longer bus idle time 10055 MIN 0055 MAX are defined in the section on WRITEs 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR 65 Rev B Pub 4 01 22 ADVANCE 512Mb x4 x8 x16 DDR SDRAM A READ burst may be followed by or truncated with a PRECHARGE command to the same bank provided that auto precharge was not activated The PRECHARGE command should be issued x cycles after the READ command where x eq
66. g 10055 and is referenced from 5 6 TIMING PARAMETERS 752 MIN MAX UNITS MIN M MAX UNITS DSH 02 ns s w 1 n ns 0 75 j 7 02 02 42 ns x ee DDR SDRAM re 67 Micron Technology Inc reserves the right to change products or specifications without notice B p65 Rev B Pu Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM TG OPTION 66 PIN PLASTIC TSOP 400 MIL 22224008 SEE DETAIL A 0 71 lt t 0 65 TYP 0 10 2X v 0 32 x 075 TYP mgHRRBHBBBBHRSRHRHRRRBBBRBBSRHRHOE n eu ll S G 11 76 0 10 10 16 0 08 HWkuugHEEBEBBEHHHHHBHHEBBEBERBBUBU MT 0 15 503 GAGE PLANE 0 25 Y WWW 0 10 en 1 4 0 10 4 0 80 1 20 MAX 0 50 0 10 DETAIL A MAX NOTE 1 Alldimensions in millimeters MIN or typical here noted 2 Package width and length do not include mold protrusion allowable mold protrusion is 0 25mm per side 8000 S Federal Way P O Box 6 Boise ID 83707 0006 Tel 208 368 3900 E mail prodmktg micr
67. icron Technology Inc ADVANCE 512Mb x4 x8 x16 Micron DDR SDRAM CK a re en CK 4 ON I NT Nc pea 71 tpQsCK tax 2 MIN N tDQSCK min DQS or LDQS UDQS DQ Last data valid DQ First data valid yee All DQs collectively 20 r 1727 B D tizan A min I MAX 1 tDQSCK is the DQS output window relative to CK and is the long term component of DQS skew 2 DQs transitioning after DQS transition define 10050 window 3 All DQs must transition by tDQSQ after DQS transitions regardless of tAC 4 tACis the DQ output window relative to CK and is the long term component of DQ skew 5 6 7 NOTE and the first valid signal transition 2 are the latest valid signal transition READ command with CL 2 issued at TO Figure 30 Data Output Timing and tDQSCK tps _ ton NOTE 1 tDSH min generally occurs during tDQSS min 2 055 generally occurs during 0055 77 DON T CARE 3 WRITE command issued at TO 4 For x16 LDQS controls the lower byte and UDQS controls the upper byte TRANSITIONING DATA Figure 31 Data Input Timing 512Mb x4 x8 x16 DDR SDRAM 58 Micron Technology Inc reserves the right to change products or
68. ith auto precharge the precharge period begins when tWR ends with tWR measured as if auto precharge was disabled The access period starts with registration of the command and ends where the precharge period or tRP begins This device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled any command to other banks is allowed as long as that command does not interrupt the read or write data transfer already in process In either case all other related limitations apply e g contention between read data and write data must be avoided The minimum delay from a READ or WRITE command with auto precharge enabled to a command to a different bank is summarized below From Command To Command Minimum delay with concurrent auto precharge WRITE w AP READ or READ w AP 1 BL 2 WRITE or WRITE w AP BL 2 tCK PRECHARGE 1 1 READ w AP READ or READ w AP BL 2 WRITE or WRITE w AP BL 2 CK PRECHARGE 1 1 CL CAS Latency CL rounded up to the next integer BL Bust Length 4 AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle 5 ABURST TERMINATE command cannot be issued to another bank it applies to the bank represented by the current state only 6 All states and sequences not shown are illegal or reserved 7 READs or WRITEs listed in
69. ks 4 DM DQ and DQS signals are all Don t Care High Z for operations shown 5 The second AUTO REFRESH is not required and is only shown as an example of two back to back AUTO REFRESH commands TIMING PARAMETERS SYMBOL MAX UNITS i tCK 2 5 i ns tCK 2 ns 512Mb x4 x8 x16 DDR SDRAM 61 Micron Technology Inc rese the right to change products cific ithout notic 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 M nte chnolo bovine ADVANCE 512Mb x4 x8 x16 DDR SDRAM SELF REFRESH MODE CK CKE COMMAND ADDR DQS DQ DM tRp2 tXSNR txsRD3 Enter Self Refresh Mode Exit Self Refresh Mode DON T CARE NOTE 1 Clock must be stable before exiting self refresh mode That is the clock must be cycling within specifications by TaO 2 Device must be in the all banks idle state prior to entering self refresh mode 3 XSNR is required before any non READ command can be applied and XSRD 200 cycles of is required before a READ command can be applied 4 AR AUTO REFRESH command TIMING PARAMETERS SYMBOL 2 5 2 20 29 2 512Mb x4 x8 x16 DDR SDRAM 62 Micron Technology Inc reserves the right to change products or speci
70. ll banks idle state Precharging All Starts with registration of a PRECHARGE ALL command and ends when is met Once RP is met all banks will be in the idle state 6 All states and sequences not shown are illegal or reserved 7 Not bank specific requires that all banks are idle and bursts are not in progress 8 May or may not be bank specific if multiple banks are to be precharged each must be in a valid state for precharging 9 Not bank specific BURST TERMINATE affects the most recent READ burst regardless of bank 10 READs or WRITEs listed in the Command Action column include READs WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled 11 Requires appropriate DM masking 12 A WRITE command may be applied after the completion of the READ burst otherwise a BURST TERMI NATE must be used to end the READ burst prior to asserting a WRITE command 512Mb x4 x8 x16 DDR SDRAM 40 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 Mcr on DDR SDRAM TRUTH TABLE 4 CURRENT STATE BANK n COMMAND TO BANK m Notes 1 6 notes appear below and on next page CURRENT STATE CS RAS CAS WE COMMAND ACTION NOTES Any H X X X DESELECT NOP continue previous operation L
71. lowing sections provide detailed in formation covering device initialization register defi nition command descriptions and device operation Initialization DDR SDRAMs must be powered up and initialized in a predefined manner Operational procedures other than those specified may result in undefined opera tion Power must first be applied to Vpn and VppQ simul taneously and then to Vrer and to the system Vrr must be applied after to avoid device latch up which may cause permanent damage to the device VreF can be applied any time after VDDQ but is expected to be nominally coincident with Vrr Except for CKE inputs are not recognized as valid until after Vrer is applied CKE is an SSTL 2 input but will detect an LVCMOS LOW level after is applied Maintaining an LVCMOS LOW level on CKE during power up is re quired to ensure that the DQ and DQS outputs will be in the High Z state where they will remain until driven in normal operation by a read access After all power supply and reference voltages are stable and the clock is stable the DDR SDRAM requires 200 delay prior to applying an executable command Once the 200ps delay has been satisfied a DESE 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 ADVANCE 512Mb x4 x8 x16 DDR SDRAM LECT or NOP command should be applied and CKE should be brought HIGH Following the NOP command a PRECHARGE ALL command should be ap
72. ng 3 Supports PC1600 modules with 2 2 2 timing 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev Pub 4 01 1 ADVANCE 512Mb x4 x8 x16 DDR SDRAM MT46V128M4 32 Meg x 4 x4 banks MT46V64M8 16 Meg x 8 x4 banks MT46V32M16 8Megx 16 x 4 banks For the latest data sheet revisions please refer to the Micron Website www micron com datasheets PIN ASSIGNMENT TOP VIEW 66 Pin TSOP x4 x8 x16 x16 x8 x4 VDD VDD LH 1e 66 Vss Vss Vss NC DQO DQ0 2 65 DQ15 007 NC VDDQ VDDQ VDDQ 3 64 VssQ VssQ VssQ NC 091 4 63 014 NC NC DQO 002 5 62 0913 006 09 VsQ 0 6 61 VopQ 009 VppQ NC NC 7 60 m 0012 NC NC NC 002 21004 8 59 m DQ11 005 NC VDDQ VDDQ VDDQ 9 58 VssQ VssQ VssQ NC NC 005 10 57 0010 NC NC 001 006 11 56 009 004 0092 559 VssQ VssQ 12 55 LL VDDQ VDDQ NC 007 13 54 DQ8 NC NC NC NC NC LH 14 53 NC NC NC VDDQ 550 LH 15 52 VssQ VssQ VssQ NC NC 1005 16 51 0005 005 DQS NC NC NC 17 50 DNU DNU DNU VDD VDD VDD 18 49 VREF VREF VREF DNU DNU DNU 19 48 Vss Vss Vss NC NC LDM 20 47 H1 UDM DM DM WE WES WE 21 46 H1 CK CK CK CAS CAS CASH 22 45 CK CK CK
73. ng Starts with registration of a PRECHARGE command and ends when is met Once tRP is met the bank will be in the idle state Row Activating Starts with registration of an ACTIVE command and ends when is met Once is met the bank will be in the row active state Read w Auto Precharge Enabled Starts with registration of a READ command with auto precharge enabled and ends when has been met is met the bank will be in the idle state Write w Auto Precharge Enabled Starts with registration of a WRITE command with auto precharge enabled and ends when has been met is met the bank will be in the idle state 512Mb x4 x8 x16 DDR SDRAM 39 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM NOTE continued 5 The following states must not be interrupted by any executable command COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states Refreshing Starts with registration of an AUTO REFRESH command and ends when is met Once is met the DDR SDRAM will be in the all banks idle state Accessing Mode Register Starts with registration of a LOAD MODE REGISTER command and ends when has been met tMRD is met the DDR SDRAM will be in the a
74. ntered 47 DM Input Data Mask DM is an input mask signal for write data Input 20 47 LDM UDM data is masked when DM is sampled HIGH along with that input data during a WRITE access DM is sampled on both edges of DQS Although DM pins are input only the DM loading is designed to match that of DQ and DQS pins For the x16 LDM is DM for DQO DQ7 and UDM is DM for DQ8 DQ15 Pin 20 is a NC on x4 and x8 26 27 BAO BA1 Bank Address Inputs BAO and BA1 define to which bank an ACTIVE READ WRITE or PRECHARGE command is being applied 29 32 35 40 A0 A12 Address Inputs Provide the row address for ACTIVE commands and 28 41 42 the column address and auto precharge bit A10 for READ WRITE commands to select one location out of the memory array in the respective bank A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A10 LOW bank selected by BAO 1 or all banks A10 HIGH The address inputs also provide the op code during a MODE REGISTER SET command BAO and BA1 define which mode register mode register or extended mode register is loaded during the LOAD MODE REGISTER command Data Input Output Data bus for x16 4 7 10 13 54 57 60 and 63 are NC for x8 2 4 7 8 10 13 54 57 59 60 63 and 65 for x4 continued on next page 512Mb x4 x8 x16 DDR SDRAM 7 Micron Technology Inc reserves the right to change products or specifications without n
75. nterrupting Micron ADVANCE 512Mb x4 x8 x16 DDR SDRAM SSS SSS Se SS SS SS SS Se tDQss 10955 095 Da mam vam meme DON T CARE TRANSITIONING DATA s applied in the programmed order following DI b written s referenced from the first positiv ones the last data in pai 5 The PRECHARGE and WRITE commands e bank sa 6 A10 is LOW with the WRITE comma d au o precha rge is s disabled 7 DQS is required is nd T2n nomin 2 st of 8 was sed DM wo feat red 4 nd T3n and not at T4 and T4n because the PRECHARGE and would ma Maud last two data nts 9 d Figure 23 WRITE to Precharge Interrupting Micron Technology Inc reserves the right to change products or specifications without notice 001 Micron Technology Inc ADVANCE 3 512Mb x4 x8 x16 DDR SDRAM TO T1 Tin T2 T2n T3 T4 T5 T6 22 j 2 205 NOM 42955 27 0 ee ee LLL LLL Lee 1 4 4 tDQSS MIN 10055 09 fl TT
76. ode DS DLL Register Ex EO DLL 0 Enable 1 Disable E12 Drive Strength 0 Normal 1 Reduced Y E23 QFC Function 0 Disabled Reserved 12 E11 E10 E9 EB E7 E6 E5 E4 E2 E1 E0 Operating Mode Valid Reserved J Reserved NOTE 1 E14 and E13 BAO and BA1 must be 1 0 to select the Extended Mode Register vs the base Mode Register 2 The reduced drive strength option is not supported on the x4 and x8 versions and is only available on the x16 version The QFC option is not supported w Figure 3 Extended Mode Register Definition Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron COMMANDS Truth Table 1 provides a quick reference of avail able commands This is followed by a verbal descrip tion of each command Two additional Truth Tables TRUTH TABLE 1 COMMANDS ADVANCE 512Mb x4 x8 x16 DDR SDRAM appear following the Operation section these tables provide current state next state information Note 1 NAME FUNCTION CS RAS CAS WE ADDR NOTES DESELECT NOP H X X X X 9 NO OPERATION NOP L H H H X 9 ACTIVE Select bank and activate row L L
77. ominal c se to ak ister DM GIE the E Was sed M uld not be ired at T4n bec ecause the READ command would mask the last four data 2 21 WRITE to READ Odd Number of Data Interrupting ADVANCE 512Mb x4 x8 x16 DDR SDRAM TO T1 Tin T2 T2n T3 T4 T5 T6 S Ee comune Ke OK UC 007 XD eX x Ce MOK re MK X ADDRESS Ke DUD A eee DQSS NOM _ DQss raa aaa aaa aaa a a a aa DQSS MIN Zn SUP O LA 29 22 bin eee ee ee 4 ee ee eee ee 1 tDQSS MAX iDQss Da E P TTT on N ANA CARE TRANSITIONING DATA NOTE 1 os data in for column b 2 Thre ed equen nts are applied in the programmed order following DI 3 indie ed burst of 4 is 4 tWR E ced from the firs 2 sit 2 edge after the la api 5 The PRECHARGE nd WRITE commands o the same 2 How PRECHARGE and WRITE commands be to different devices whi ch case is a iis the PRECHARGE command could be applied earlie 6 A10 is ON WRITE command auto precharge is disabled 7 PRE PRECHARGE comman d Figure 22 WRITE to PRECHARGE Uni
78. on com Internet http www micron com Customer Comment Line 800 932 4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology Inc 512Mb x4 x8 x16 DDR SDRAM 68 Micron Technology Inc reserves the right to change products or specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc
79. only 54 Output Timing 10080 and x4 8 55 Output Timing 0050 and 16 56 Output Timing and DQSCK 57 Input Tain 57 Input Voltage eet ree eret ier eost 58 Initialize and Load Mode Registers 59 Power Down Mode esee 60 Auto Refresh 61 Self Refresh Mode sse 62 Reads Bank Read Without Auto Precharge 63 Bank Read With Auto Precharge 64 Writes Bank Write Without Auto Precharge 65 Bank Write With Auto Precharge 66 Write DM Operation 67 66 pin TSOP TG dimensions 68 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron COMMAND DECODE CONTROL LOGIC MODE REGISTERS 13 ADVANCE 512Mb x4 x8 x16 DDR SDRAM FUNCTIONAL BLOCK DIAGRAM 128 Meg x 4 A0 A12 BAO ADDRESS REGISTER BANK2 BANK1 z
80. otice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM PIN DESCRIPTIONS continued TSOP PINNUMBERS SYMBOL TYPE DESCRIPTION 2 5 8 11 56 59 62 65 DQO 7 Data Input Output Data bus for x8 2 8 59 and 65 are for 4 5 11 56 62 000 3 Data Input Output Data bus for x4 51 DQS Data Strobe Output with read data input with write data DQS is 16 51 LDQS UDQS edge aligned with read data centered write data It is used to capture data For the x16 LDQS is DQS for 200 007 and UDQS is DQS for DQ8 DQ15 Pin 16 is NC on x4 and x8 50 DNU Do Not Use Must float to minimize noise 3 9 15 55 61 VDDQ Supply DQ Power Supply 2 5V 0 2V Isolated on the die for improved noise immunity 6 12 52 58 64 VssQ Supply DQ Ground Isolated on the die for improved noise immunity 1 18 33 VoD Supply Power Supply 2 5V 0 2V 34 48 66 Vss Supply Ground 49 VREF Supply SSTL_2 reference voltage 14 17 19 25 43 53 NC Connect These pins should be left unconnected RESERVED NC PINS 17 13 Address input for 1Gb devices NOTE 1 NC pins not listed may also be reserved for other uses now or in the future This table simply defines specific NC pins deemed to be of importance 512Mb x4 x8 x16 DDR SDRAM 8 Micron Technology Inc reserves the right to change products
81. own mode shown is active power down 2 No column accesses are allowed to be in progress at the time power down is entered TIMING PARAMETERS 75Z SYMBOL MIN MAX MIN MIN UNITS SYMBOL MIN MIN tCH 045 055 045 055 045 055 tCK 2 0 45 055 045 0 55 0 45 0 55 2 5 75 13 75 13 8 13 ns ADVANCE 512Mb x4 x8 x16 DDR SDRAM AUTO REFRESH MODE WU XX U 708 W DE WU QN COMMAND Kee IK PRE XX ez AR E X AR XX E X E XI act m 11 UY TMK X ZL m TK tis sos TNE SUI TT 277771777 cs LLL LLL LLL LLL Do 22 UK 2222 7 ZAR 7 Zi tgp a lt DON T CARE NOTE 1 PRE PRECHARGE ACT ACTIVE AR AUTO REFRESH RA Row Address BA Bank Address 2 NOP commands are shown for ease of illustration other valid commands may be possible at these times CKE must be active during clock positive transitions 3 Don t Care if A10 is HIGH at this point A10 must be HIGH if more than one bank is active i e must precharge all active ban
82. plied Next a LOAD MODE REGISTER command should be issued for the extended mode register 1 LOW and BAO HIGH to enable the DLL followed by another LOAD MODE REGISTER command to the mode register BAO BA1 both LOW to reset the DLL and to program the operating parameters Two hundred clock cycles are required between the DLL reset and any READ com mand A PRECHARGE ALL command should then be applied placing the device in the all banks idle state Once in the idle state two AUTO REFRESH cycles must be performed RFC must be satisfied Addition ally LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated i e to pro gram operating parameters without resetting the DLL is required Following these requirements the DDR SDRAM is ready for normal operation Register Definition MODE REGISTER The mode register is used to define the specific mode of operation of the DDR SDRAM This definition includes the selection of a burst length a burst type a CAS latency and an operating mode as shown in Fig ure 1 The mode register is programmed via the MODE REGISTER SET command with BAO 0 and BAI 0 and will retain the stored information until it is pro grammed again or the device loses power except for bit A8 which is self clearing Reprogramming the mode register will not alter the contents of the memory provided it is performed cor rectly The mode register must be loaded reloaded when all
83. put logic level appearing coincident with the data If a given DM signal is registered LOW the corresponding data will be written to memory if the DM signal is registered HIGH the corresponding data in puts will be ignored and a WRITE will not be executed to that byte column location PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks The bank s will be available for a subsequent row access a specified time after the precharge command is issued Except in the case of concurrent auto precharge where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters Input A10 determines whether one or all banks are to be precharged and in the case where only one bank is to be precharged inputs BAO BAT select the bank Other wise BA1 are treated as Don t Care Once a bank has been precharged it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank A PRECHARGE command will be treated as a NOP if there is no open row in that bank idle state or if the previously open row is already in the process of precharging AUTO PRECHARGE Auto precharge is a feature which performs the same individual bank precharge function described above but without requiring an explicit command This is accompli
84. quired by the Micron device JEDEC specifies resetting the DLL with A8 H tMRD is required before any command can be applied and 200 cycles of CK are required before a READ command can be issued The two AUTO REFRESH commands at 0 may be applied prior to the LOAD MODE REGISTER LMR command at Although not required by the Micron device JEDEC specifies issuing another LMR command 8 1 prior to activating any bank PRE PRECHARGE command LMR LOAD MODE REGISTER command AR AUTO REFRESH command ACT ACTIVE command RA Row Address Bank Address TIMING PARAMETERS SYMBOL MAX UNITS tCK 2 5 ns 2 ns ns 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc 59 Pub 4 01 ADVANCE 4 512Mb x4 x8 x16 DDR SDRAM POWER DOWN MODE D n LU 277 lt IEEE Enter 2 Exit Power Down Power Down Mode Mode DON T CARE NOTE 1 If this command is a PRECHARGE or if the device is already in the idle state then the power down mode shown is precharge power down If this command is an ACTIVE or if at least one row is already active then the power d
85. ron Technology Inc Micron COMMAND ADDRESS DQS DQ COMMAND ADDRESS DQS DQ ADVANCE 512 4 8 16 1 DDR SDRAM READ 377 NOP 7 NOR XD Bank a J _Coln 200 ga aX 2 5 _ NOTE 1 DO n data out from column n 2 Burst length 4 3 Three subsequent elements of data out appear in the programmed order following DO n 4 Shown with nominal tDQSCK and 0050 Figure 7 DON T CARE TRANSITIONING DATA READ Burst ADVANCE 512Mb x4 x8 x16 DDR SDRAM COMMAND Wy T nor X appress 7 Bank MOL DQ TO T1 T2 T2n T3 T3n T4 T4n 5 5 LOUER URS Fe RUE e 0 See command wean nor wear KYK w XA w XA ADDRESS Bank til XL x n 7 005 DQ ea eS 09 05 X DON T CARE TRANSITIONING DATA NOTE 1 DO n or b data out from column n or column b 2 Burst length 4 or 8 if 4 the bursts are concatenated if 8 the second burst interrupts the first 3 Three subsequent elements of data out appear in the programmed order following DO n 4 Three or seven subsequent elements of data out appear in the programmed order following DO b 5
86. row remains active or open for accesses until a PRECHARGE command is issued to that bank A PRECHARGE command must be issued before open ing a different row in the same bank READ The READ command is used to initiate a burst read access to an active row The value on the BAO BAI inputs selects the bank and the address provided on inputs AO Ai where i 9 for x16 9 11 for x8 or 9 11 and 12 for x4 selects the starting column location The value on input 10 determines whether or not auto precharge is used If auto precharge is selected the row being accessed will be precharged at the end of the READ burst if auto precharge is not selected the row will remain open for subsequent accesses WRITE The WRITE command is used to initiate a burst write access to an active row The value on the BAO 1 inputs selects the bank and the address provided on inputs 0 where i 9 for x16 9 and 11 for x8 or 9 11 and 12 for x4 selects the starting column location The value on input 10 determines whether or not auto precharge is used If auto precharge is selected the row being ac cessed will be precharged at the end of the WRITE burst if auto precharge is not selected the row will remain open for subsequent accesses Input data 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 14 ADVANCE 512Mb x4 x8 x16 DDR SDRAM appearing on the DQs is written to the memory array subject to the DM in
87. s timing must be derated 50ps must be added to 05 and for each 100mv ns reduction in slew rate If slew rate exceeds 4V ns functionality is uncertain must not vary more than 4 if is not active while any bank is active DERATING DATA VALID WINDOW 3 8 75 tCK 10ns A 8 CK 10ns m 75 7 5ns e 8 CK 8ns ns 50 50 49 5 50 5 49 51 48 5 52 5 48 52 10959 47 5 53 5 47 53 46 5 54 5 46 54 45 5 55 5 45 55 Clock Duty Cycle 512Mb x4 x8 x16 DDR SDRAM 512Mx4x8x16DDR B p65 Rev B Pub 4 01 51 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron NOTES continued 33 The clock is allowed up to 150ps of jitter Each timing parameter is allowed to vary by the same amount 34 HPmin is the lesser of CL minimum and minimum actually applied to the device CK and CK inputs collectively during bank active 35 READs and WRITEs with autoprecharge are not allowed to be issued until RAS min be satisfied prior to the internal precharge com mand being issued 36 Any positive glitch must be less than 1 3 of the clock cycle and not more than 400mV or 2 9 volts whichever is less Any negative glitch must be less than 1 of the clock cycle and not exceed either 300mV or 2 2 volts whichever is more positive 37 Normal Output Drive
88. set to zero and bits A0 A6 set to the desired values A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9 A12 each set to zero bit A8 set to one and bits AO A6 set to the desired values Although not required by the Micron device JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL it should always be followed by a LOAD MODE REGIS TER command to select normal operating mode All other combinations of values for A7 A12 are re served for future use and or test modes Test modes and reserved states should not be used because un known operation or incompatibility with future ver sions may result Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron EXTENDED MODE REGISTER The extended mode register controls functions be yond those controlled by the mode register these ad ditional functions are DLL enable disable and output drive strength These functions are controlled via the bits shown in Figure 3 The extended mode register is programmed via the LOAD MODE REGIS TER command to the mode register with BAO 1 and BAI 0 and will retain the stored information until it is programmed again or the device loses power The en abling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register BAO 1 both LOW to reset the DLL The extended mode r
89. shed by using 10 to enable auto precharge in conjunction with a specific READ or WRITE command A precharge of the bank row that is addressed with the READ or WRITE command is auto matically performed upon completion of the READ or WRITE burst Auto precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command This device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank Auto precharge ensures that the precharge is initi ated at the earliest valid stage within a burst This earliest valid stage is determined as if an explicit PRECHARGE command was issued at the earliest pos sible time without violating tRAS MIN as described for each burst type in the Operation section of this data sheet The user must not issue another command to the same bank until the precharge time is completed Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron BURST TERMINATE The BURST TERMINATE command is used to trun cate READ bursts with auto precharge disabled The most recently registered READ command prior to the BURST TERMINATE command will be truncated as shown in the Operation section of this data sheet The open page which the READ burst was terminated from remains open AUTO REFRESH AUTO REFRESH is used during normal oper
90. specifications without notice 512Mx4x8x16DDR B p65 Rev B Pub 4 01 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 DDR SDRAM Micron INITIALIZE AND LOAD MODE REGISTERS VDD VDDQ Avro vrr VREF CK 2 f LVCMOS Wo e t i a LOW LEVEL 77 lt 7 7 WU Z COMMANDS gt PRE X LMR XX LMR PRE AR XX AR XX ACT 1 DM YUL 0 9 11 12 5 ALL BANKS ALL BANKS 7 III LK o0858 8H 1045 st t 1 A v TILL ORES XE ILL LLL LIL KL oos 34 i i f 1 igh Z 1 f f f 200ps ul tRP tMRD tRP tRFC Power up Load Extended lt and Mode Register 200 cycles of CK3 CK stable Load Mode Register2 1 DON T CARE NOTE 1 is not applied directly to the device however tVTD should be greater than or equal to zero to avoid device latch up VDDQ VDDQ Vr and Vner must be equal to or less than 0 3V Alternatively Vrr may be 1 35V maximum during power up even if are 0 volts provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin Although not re
91. tions HP 2 0080 HP QHS The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived The clock is allowed a maximum duty cycle variation of 45 55 Functionality is uncertain when operating beyond a 45 55 ratio The data valid window derating curves are provided below for duty cycles ranging between 50 50 and 45 55 Referenced to each output group x4 DQS with 200 003 x8 DQS with 200 007 x16 LDQS with 200 007 and UDQS with DQ8 DQI5 This limit is actually a nominal value and does not result in a fail value CKE is HIGH during REFRESH command period RFC MIN else 28 29 30 31 32 ADVANCE 512Mb x4 x8 x16 DDR SDRAM CKE is LOW i e during standby To maintain a valid level the transitioning edge of the input must a Sustain a constant slew rate from the current AC level through to the target AC level Or ViH AC b Reach at least the target AC level c After the AC target level is reached continue to maintain at least the target DC level Vit pc or The Input capacitance per pin group will not differ by more than this maximum amount for any given device JEDEC specifies CK and CK input slew rate must be gt 1V ns 2V ns if measured differentially DQ and DM input slew rates must not deviate from DQS by more than 10 If the DQ DM DQS slew rate is less than 0 5V n
92. tive WRITE to WRITE du x8 x16 DDR SDRAM 29 Micron Technology Inc reserves the right to change products or he ADVANCE 512Mb x4 x8 x16 DDR SDRAM COMMAND ADDRESS DQS DQ DM 512Mb x4 x8 x16 DDR SDRAI X D K O DEED tDass NOM DON T CARE TRANSITIONING DATA NOTE 1 DI b etc data in for column b etc 2 b etc the next data in following DI b etc according to the programmed burst order 3 Programmed burst length 2 4 or 8 in cases shown 4 Each WRITE command may be to any bank Figure 18 Random WRITE Cycles ADVANCE 512Mb x4 x8 x16 DDR SDRAM 1 055 NOM DQS OO MMMM 5 CTT DON T CARE 28 TRANSITIONING DATA NOTE 1 DI b data in for column b Pis ubsequent elements of data e applied in the programmed order following DI b 3 An uninterrupted burst of 4 4 tWTR is referenced from the firs ro d edge after the last data in pai 5 The READ an ommands However the READ nd WRITE ommands to different device which case 4 otr ired nd the READ command could be RAM 6 A10 is LOW with the WRITE c ommand a ut o precharge is disabled Figure 19 WRITE to READ Uninterrupting ADVANCE d 512Mb x4 x8 x16
93. trant 9 Burst TYPE ee ttt rendent 10 Read Latency 11 Operating Mode 11 Extended Mode Register 12 DLL Enable Disable 12 Commiandis 13 Truth Table 1 13 Truth Table 1A DM Operation 000 0000 13 pigro E 14 No Operation NOP eene 14 Load Mode Register 14 DER UEM ap 14 Gr M Pn 14 WHILE o Re Ree 14 ade osa deoa 14 Auto uis eoram 14 Burst Terminate oorsee 14 Auto Refresh 15 15 ies 16 Bank Row Activation 16 Reads CREE RR 17 Redd err MR 18 Consecutive Read Bursts 19 Nonconsecutive Read Bursts 20 Random Read ACCESSES 21 Terminating a Read 23 Read to WE 24 Read to Precharge 25 WV TIERS mr LE 26 8 T 27 Consecutive Write to Write 28 Nonconsecutive Write to Write 29 512Mb x4 x8 x
94. uals the number of desired data element pairs pairs are required by the 2n prefetch architecture This is shown in Figure 13 Following the PRECHARGE command a subsequent command to the same bank cannot be issued until fRP is met Note that part of the row precharge time is hid den during the access of the last data elements Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 Micron DDR SDRAM ai WM WEM uuum Ns st sea N ee ee gee CL 2 DOS X 1 1 MESE COMMAND ADDRESS 005 NOTE 1 DO data out from column DON T CARE TRANSITIONING DATA 2 Burst length 4 3 Subsequent element of data out appears in the programmed order following DO n 4 Shown with nominal tDQSCK and 0050 5 BST BURST TERMINATE command page remains open Figure 11 Terminating a READ Burst COMMAND ADDRESS DQS DQ D CK CK COMMAND ADDRESS DQS DQ DM ADVANCE 512Mb x4 x8 x16 DDR SDRAM 79 06 T4 T5n KOE NOTE 1 DO n data out from column DON T CARE TRANSITIONING DATA 2 DI b data in from column b 3 Burst length 4 in the cases shown applies for bursts of 8 as well i
95. y not reflect this option Reserved for future use Reserved for future use Random addressing changing 50 of data changing at every transfer Random addressing changing 100 of data changing at every transfer CKE must be active high during the entire time a refresh command is executed That is from the time the AUTO REFRESH command is registered CKE must be active at each rising clock edge until REF later IDD2N specifies the DQ DQS and DM to be driven to a valid high or low logic level IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable Although IDD2F IDD2N and IDD2Q are similar IDD2F is worst case Whenever the operating frequency is altered not including jitter the DLL is required to be reset and followed by 200 clock cycles Figure D is Minimum Eee ce So 25 2 EE oe es Nomi _ MEC Eq GN UL aro See NN HEN __ 0 1 0 6 0 8 1 0 Vout V Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc ADVANCE 512Mb x4 x8 x16 cron DDR SDRAM NORMAL OUTPUT DRIVE CHARACTERISTICS PULL DOWN CURRENT mA PULL UP CURRENT mA VOLTAGE NOMINAL NOMINAL V LOW MINIMUM MAXIMUM 0 1 6 0 i 4 6 10 0 13 5 9 2 200 298 04 241 266

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