intersil EL7154 Manual
Contents
1. mi D h X 45 N 2 1 p i p A SEE DETAIL a Y A2 irae ie SEATING f PLANE 0 010 PLANE AT L 4 24 KB 0 016 gt b DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY SO CHES BT aA SYMBOL SO 8 SO 14 0 150 SOL 16 5601 20 SOL 24 SOL 28 TOLERANCE NOTES A 0 068 0 068 0 068 0 104 0 104 0 104 0 104 MAX 1 0 006 0 006 0 006 0 007 0 007 0 007 0 007 0 003 2 0 057 0 057 0 057 0 092 0 092 0 092 0 092 0 002 b 0 017 0 017 0 017 0 017 0 017 0 017 0 017 0 003 0 009 0 009 0 009 0 011 0 011 0 011 0 011 0 001 0 193 0 341 0 390 0 406 0 504 0 606 0 704 0 004 1 3 E 0 236 0 236 0 236 0 406 0 406 0 406 0 406 0 008 E1 0 154 0 154 0 154 0 295 0 295 0 295 0 295 0 004 2 3 e 0 050 0 050 0 050 0 050 0 050 0 050 0 050 Basic 0 025 0 025 0 025 0 030 0 030 0 030 0 030 0 009 L1 0 041 0 041 0 041 0 056 0 056 0 056 0 056 Basic h 0 013 0 013 0 013 0 020 0 020 0 020 0 020 Reference N 8 14 16 16 20 24 28 Reference Rev M 2 07 NOTES 1 Plastic or metal protrusions of 0 006 maximum per side are not included 2 Plastic interlead protrusions of 0 010 maximum per side are not included 3 Dimensions and 1 are measured at Datum Plane 4 Dimensioning and tolerancing per ASME Y14 5M 1994 7 intersil FN7278 2 March 8 2007 EL7154 Plastic Dual In Line Packag2. Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied IMPORTANT NOTE All parameters having Min Max specifications are guaranteed Typical values are for information purposes only Unless otherwise noted all tests are at the specified temperature and are pulsed tests therefore T Tc TA DC Electrical Specifications TA 25 C Vpp 12V Vy 12V V 3V unless otherwise specified 3 intersil PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS INPUT Logic 1 Input Voltage 2 4 V Logic 1 Input Current VDD 0 1 10 HA VIL Logic 0 Input Voltage 0 6 V IL Logic 0 Input Current OV 0 1 10 HA Vuvs Input Hysteresis 0 3 i V Intersil Pull Down Resistance louT 100mA 2 4 lout Output Leakage Current Vpp GND 0 2 10 Peak Output Current Source Sink 4 0 A Ipc Continuous Output Current Source Sink 200 mA POWER SUPPLY Is Power Supply Current Inputs 1 2 5 mA Vs Operating Voltage 4 5 16 V Current to GND Pin 4 1 10 Off Leakage at Vy Pin 8 0V 1 10 Electrical Specifications 25 C unless otherwise spe
3. aterials and 100 matte tin plate termination finish which are ROHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 Nominal Operating Voltage Range PIN MIN MAX VL 3 0 Vpp to Vi 5 5 we WAAL BDTI Vpp to 0 5 15 Vpp 5 15 ntersi 2 intersil FN7278 2 March 8 2007 7154 Absolute Maximum Ratings 25 C Supply Vpp to VL Vy to VL to GND VETO EDU 16 5V Vp to es ccs kare UR cR RE nr 5V Input 0 3V below V to 0 3V above Vpp Peak Output 2 4A Thermal Information Storage Temperature 65 C to 150 C Ambient Operating Temperature 40 C to 85 C Operating Junction 125 C Power Dissipation SOS is CHI 570mW s Ue RR eive 1050mW Pb free reflow see link below http www intersil com pbfree Pb FreeReflow asp Pb free PDIPs be used for through hole wave solder processing only They are not intended for use in Reflow solder processing applications CAUTION Stresses above those listed in Absolute
4. cified PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS SWITCHING CHARACTERISTICS Vpp Vy 12V Vj 3V tR Rise Time C 100pF 4 25 ns C 2000pF 20 te Fall Time C 100pF 4 25 ns C 2000pF 20 tp 1 Turn Off Delay Time C 2000pF 20 25 ns tp 2 Turn On Delay Time C 2000pF 10 25 ns tp 1 Three State Delay 25 ns tp 2 Three State Delay 25 ns FN7278 2 March 8 2007 EL7154 Timing Table Input Inverted Output Standard Test Configuration STATE SIGNAL IN 4 intersil FN7278 2 March 8 2007 EL7154 Typical Performance Curves Tj 125 C 9 25 50 75 100 125 150 FIGURE 1 POWER DERATING CURVES 10 00 In mA p lt 10 00 5 0 9 V 20 0 2 500 div V FIGURE 3 INPUT CURRENT vs VOLTAGE E 0 B 1 Input 0 7 All Inputs 6 5 G 4 gt a 5 Qa aA 2 1 9 5 10 15 Supply Voltage FIGURE 5 QUIESCENT SUPPLY CURRENT 200 Yon 15 Yd 20 E Vgp 10V 8 gt Yon 5 a 2 n gt a 2000 pF 0 2 10 kHz 100 kHz MHz 10 MHz Frequen
5. cy FIGURE 7 AVERAGE SUPPLY CURRENT vs VOLTAGE AND FREQUENCY 2 0 7 High Limit 2 4 1 8 1 6 _ gt Hysteresis 1 4 o gt 42 a 1 0 Low Limit 0 8 5 10 15 Supply Voltage FIGURE 2 SWITCH THRESHOLD vs SUPPLY VOLTAGE V Supply 15 10 5 0 0 4 0 M N CHANNEL I Sink 2 0 2 0 P CHANNEL Source 4 0 9 5 10 15 V Supply FIGURE 4 PEAK DRIVE vs SUPPLY VOLTAGE m nters n e 2 3 Pull Down a v E 5 a 5 Pull Up 1 9 5 10 15 Supply Voltage FIGURE 6 ON RESISTANCE vs SUPPLY VOLTAGE 100 Vpp 10V 80 E 2 60 E 5 40 E X 2 20 tr 200 2 000 20 000 Load Capacitance pF FIGURE 8 RISE FALL TIME vs LOAD 5 intersil FN7278 2 March 8 2007 EL7154 Typical Applications INPUT FIGURE 9 PIN DRIVER FIGURE 10 ADJUSTABLE AMPLITUDE PULSE GENERATOR 12 Vi DD Vpp O 0 1 wr LOAD PULL UP Vour NO INVERTING INPUT INPUT os NA COMA Alrerside INPUT FIGURE 13 RESONANT GATE DRIVER 6 intersil FN7278 2 c March 8 2007 EL7154 Small Outline Package Family SO
6. edance 2 50 Low quiescent current 5mA Wide operating voltage 4 5V to16V Isolated P Channel device Separate ground and V pins Pb free plus anneal available ROHS compliant Applications C Level shifting below GND IGBT drivers CCD drivers 1 CAUTION These devices are sensitive to electrostatic discharge follow proper Handling Procedures 1 888 INTERSIL or 1 888 468 3774 Intersil and design is a registered trademark of Intersil Americas Inc Copyright Intersil Americas Inc 1996 2005 2007 All Rights Reserved All other trademarks mentioned are the property of their respective owners 7154 Ordering Information PART PART TAPE AND PKG NUMBER MARKING REEL PACKAGE DWG EL7154CN EL7154CN 8 Ld PDIP MDP0031 EL7154CNZ EL7154CN Z 8 Ld PDIP MDP0031 Pb free EL7154CS 7154CS 8 Ld SOIC MDP0027 EL7154CS T7 7154CS 7 8 Ld SOIC MDP0027 EL7154CS T13 7154CS 13 8 Ld SOIC MDP0027 EL7154CSZ 7154CSZ 8 Ld SOIC MDP0027 See Note Pb free EL7154CSZ T7 7154CSZ 7 8 Ld SOIC MDP0027 See Note Pb free EL7154CSZ T13 7154CSZ 13 8 Ld SOIC MDP0027 See Note Pb free Pb free PDIPs can be used for through hole wave solder processing only They are not intended for use in Reflow solder processing applications NOTE Intersil Pb free plus anneal products employ special Pb free material sets molding compounds die attach m
7. es PDIP lt gt E N rrr MM PIN 1 t INDEX SEATING OI m V PEANG j Y e LJ tJ LJ LJ LJ 5 en 1 2 2 e eB b2 MDP0031 PLASTIC DUAL IN LINE PACKAGE INCHES SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES A 0 210 0 210 0 210 0 210 0 210 MAX A1 0 015 0 015 0 015 0 015 0 015 MIN A2 0 130 0 130 0 130 0 130 0 130 20 005 b 0 018 0 018 0 018 0 018 0 018 0 002 b2 0 060 0 060 0 060 0 060 0 060 0 010 0 015 0 010 0 010 0 010 0 010 0 010 0 004 0 002 D 0 375 0 750 0 750 0 890 1 020 0 010 1 E 0 310 0 310 0 310 0 310 0 310 0 015 0 010 1 0 250 0 250 0 250 0 250 0 250 0 005 2 e 0 1 Basi 5 eA 0 300 t S 0 345 0 025 L 0 125 0 010 N 8 14 16 18 20 Reference Rev C 2 07 NOTES All Intersil U S products are manufactured assembled and tested utilizing 1509000 quality systems Intersil Corporation s quality certifications can be viewed at www intersil com design quality Plastic or metal protrusions of 0 010 maximum per side are not included Plastic interlead protrusions of 0 010 maximum per side are not included Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane Dimension eB is measured with the lead ti
8. intersil Data Sheet High Speed Monolithic Pin Driver The EL7154 three state pin driver is particularly well suited for ATE and level shifting applications The 4A peak drive capability makes the EL7154 an excellent choice when driving high speed capacitive lines The P Channel MOSFET is completely isolated from the power supply providing a high degree of flexibility Pin 7 can be grounded and the output can be taken from pin 8 when a source follower output is desired The N Channel MOSFET has an isolated drain but shares a common bus with pre drivers and level shifter circuits This is necessary to ensure that the N Channel device can turn off effectively when V goes below GND In some power FET and IGBT applications negative drive is desirable to insure effective turn off The EL7154 can be used in these applications by returning Vi to a moderate negative potential Pinout EL7154 8 LD PDIP 8 LD SOIC TOP VIEW Truth Table THREE STATE INPUT Pout Nout 0 0 Open Open 0 1 1 0 1 1 LOW Manufactured under U S Patent Nos 5 334 883 5 341 047 5 352 578 5 352 389 5 351 012 5 374 898 EL7154 March 8 2007 FN7278 2 Features Comparatively low cost Three State output 3V and 5V Input compatible Clocking speeds up to 10MHz 20ns Switching delay time 4A Peak drive solated drains Low output imp
9. ps unconstrained 8 and 16 lead packages have half end leads as shown Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 8 intersil FN7278 2 March 8 2007
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intersil EL7154 Manual