intersil ISL6423B handbook
Contents
1. Temperature Shutdown Threshold 150 Temperature Shutdown Hysteresis 20 OTFI FLT released Vo 76V 10 pA FLT asserted Isink 3 2mA 0 4 V NOTES 5 Internal digital soft start 6 EXTM TXT and SELVTOP and addr 0 1 pins have 200k internal pulldown resistors 7 On exceeding this backward current limit threshold for a period of 2ms the device enters the Backward dynamic current limit mode 350mA typ and the BCF I C bit is set The dynamic current limit duty ratio during a back current fault is ON 2ms OFF 50ms The output will remain clamped to the fault output voltage till released On removal of the fault condition the device returns to normal operation 8 In the Dynamic current limit mode the output is ON for 51 and OFF for 900ms But remains continuously ON in the Static mode When tone is ON the minimum current limit is 50mA lower the values indicated in the table Tone Waveform 22kHz 22kHz 22kHz Ne INTERNAL TONE INTERNAL TONE EXTERNAL TONE RETURNS TO NOMINAL 1 PERIOD Tr 10ps Tr 10 5 TYP AFTER THE LAST EXTM RISING EDGE T gt 55 NOTES 9 The signal pin TXT changes the decoder threshold during tone transmit and receive TTH allows threshold control through 2 10 The tone rise and fall times not shown due to resolution of graphics It is 10ps typ for 22kHz 11 The EXTM pins have input thresholds of Vil max 0 8V and Vih min 1 72. 0 27V 2 0 3 0 mA Output Backward Leakage Current EN Q 28V 3 9 17 mA Output Backward VAYA 1 Od nt S4 mA Output Backward Current Limit EN 1 VopAuL T 19V Note 7 350 mA Output Backward Voltage EN 0 27 V Output Under Voltage OUVF bit is asserted high Measured from 6 2 96 Asserted high during soft start the typ output set value Output Over Voltage OUVF bit is asserted high Measured from 2 6 Asserted high during soft start the typ output set value TXT EXTM SELVTOP AND ADDR 0 1 INPUT PINs Note 8 Asserted LOW 0 8 Asserted HIGH 1 7 Input Current 25 CURRENT SENSE CS Input Bias Current IBIAS 700 Overcurrent Threshold Vcs Static current mode DCL 325 450 500 mV ERROR AMPLIFIER Open Loop Voltage Gain AOL 93 dB Gain Bandwidth Product GBP 14 MHz PWM Maximum Duty Cycle 90 93 96 Minimum Pulse Width 20 ns 6 intersil FN6412 1 April 10 2007 Electrical Specifications Vcc 12V 20 C to 85 C unless otherwise noted Typical values are at TA 25 EN VBOT ENT L DCL L lout 12mA unless otherwise noted See software description section for 2 access to the system Continued PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OSCILLATOR Oscillator Frequency fo Fixed at 20 396 440 484 kHz Thermal Shutdown
3. 1 SELVTOP X Vout 13V Vgoost 13V VDROP 0 1 1 1 X X 0 1 VSPEN 1 SELVTOP X Vout 14V Vgoost 14V Vprop 0 1 1 1 X X 1 O0 VSPEN 1 SELVTOP X Voyt 18V Vgoost 18V VpRop 0 1 1 1 X X 1 1 VSPEN 1 SELVTOP X Vout 19V Vpoosr 19V 0 1 1 0 X X X X PWM and Linear for channel 1 disabled NOTE X indicates Read Only and is a Don t Care for the Write mode Received Data 2 bus READ MODE The ISL6423B can provide to the ib a copy of the system register information via the 2C bus in m ied The read mode i Vi darn address with MN B3 th ste generated clock bits the ISL6423B issues a byte on the SDA data bus line MSB transmitted first At the ninth clock bit the MCU master can Acknowledge the reception starting in this way the transmission of another byte from the ISL6423B Not acknowledge stopping the read mode communication The read only bits of the register SR1 convey diagnostic information about the ISL6423B as indicated in the Table 7 Power On Interface Reset The IC interface built into the ISL6423B is automatically reset at power on The 2 interface block will receive a Power OK logic signal from the UVLO circuit This signal will go HIGH when chip power is OK As long as this signal is LOW the interface will not respond to any 2 commands and the system register SR1 thru SR4 are all initialized to all zero thus keeping th
4. 0 1 0 14 3V 0 0 1 18 3V 0 1 x 1 19 3V 1 0 0 13 3V 1 0 1 x 14 3V 1 1 0 18 3V 1 1 1 19 3V Bus Interface for ISL6423B Refer to Philips 2 Specification Rev 2 1 Data transmission from main microprocessor to the ISL6423B and vice versa takes place through the two wire 2 bus interface consisting of the two lines SDA and SCL Both SDA and SCL are bidirectional lines connected to a positive supply voltage via a pull up resistor Pull up resistors to positive supply voltage must be externally connected When the bus is free both lines are HIGH The output stages of ISL6423B will have an open drain open collector in order to perform the wired AND function Data on the I C bus can be transferred up to 100Kbps in the standard mode or up to 400Kbps in the fast mode The level of logic and logic 1 is dependent of associated value of Vpp as per electrical specification table One clock pulse is generated for each data bit transferred Data Validity The data on the SDA line must be stable during the HIGH period of the clock The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW Refer to Figure 4 ALLOWED DATA VALID FIGURE 4 DATA VALIDITY START and STOP Conditions As shown in Figure 5 START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH The STOP condition is a LOW to HIGH transiti
5. 138 5 50 11 1 0 118 5 3 0 11 Rev 0 6 05 NOTES 1 These package dimensions are within allowable dimensions of JEDEC MO 153 AET Issue E eae and tolerancing ANSI Y14 5M 1982 B io YA es a op 4 mol flasi protrusions or gate j te Wurrs shall not exceed BOTTOM VIE b iiis E1 Le not ES interlead flash or protrusions Interlead flash and protrusions shall not exceed 0 15mm 0 006 inch per side 5 The chamfer on the body is optional If it is not present a visual index feature must be located within the crosshatched area L is the length of terminal for soldering to a substrate N is the number of terminal positions Terminal numbers are shown for reference only Dimension b does not include dambar protrusion Allowable dambar protrusion shall be 0 08mm 0 003 inch total in excess of b dimension at maximum material condition Minimum space between protrusion and adjacent lead is 0 07mm 0 0027 inch 10 Controlling dimension MILLIMETER Converted inch dimen sions are not necessarily exact Angles in degrees 11 Dimensions P and P1 are thermal and or electrical enhanced variations Values shown are maximum size of exposed pad within lead count and body size ON All Intersil U S products are manufactured assembled and tested utilizing ISO9000 quality systems Intersil Corporation s quality certifications can be viewed at www intersil com design quality Int
6. E 9 COMMAND REGISTER SR3 CONFIGURATION SR3H SR3M SR3L DCL VSPEN X ISELH ISELL FUNCTION 0 1 0 X X X X X SR3 is selected 0 1 0 0 X X 0 0 lout limit threshold 305mA typ 0 1 0 0 X X 0 1 lout limit threshold 570mA typ 0 1 0 0 X X 1 0 lout limit threshold 705mA typ 0 1 0 0 X X 1 1 lout limit threshold 890mA typ 0 1 0 1 X X X X Dynamic current limit NOT selected 0 1 0 0 X X X Dynamic current limit selected 0 1 0 X 0 X X X SELVTOP H W pin Enabled 0 1 0 X 1 X X X SELVTOP H W pin Disabled NOTE X indicates Read Only and is a Don t Care for the Write mode 12 intersil FN6412 1 April 10 2007 TABLE 10 CONTROL REGISTER SR4 CONFIGURATION SR4H SR4M SR4L EN X x VTOP VBOT FUNCTION 0 1 1 1 X X 0 0 SR4 is selected 0 1 1 X X 0 0 VSPEN SELVTOP 0 Vout 13V Vgoost 13V Vprop 0 1 1 1 x x 0 1 VSPEN SELVTOP 0 Vout 14V Vgoost 14V VpRoP 0 1 1 1 X X 1 0 VSPEN SELVTOP 0 Vout 13V Vgoost 13V 0 1 1 1 X X 1 1 VSPEN SELVTOP 0 Vout 14V Vgoost 14V Vprop 0 1 1 1 x x 0 0 VSPEN 0 SELVTOP 1 Voyt 18V Vgoost 18 0 1 1 1 X X 0 1 VSPEN 0 SELVTOP 1 Vout 18V Vgoost 18V VpRop 0 1 1 1 X X 1 0 VSPEN 0 SELVTOP 1 Vout 19V Vgoost 19V Vpgop 0 1 1 1 x x 1 1 VSPEN 0 SELVTOP 1 Vout 19V Vgoost 19V VpRop 0 1 1 1 X x 0 0 VSPEN
7. External Modulation Input Internal Over Temperature Protection and Diagnostics dfa aterert Flags FLT signal LNB Short Circuit Protection and Diagnostics QFN EPTSSOP Packages Pb Free Available RoHS Compliant Applications LNB Power Supply and Control for Satellite Set Top Box Ordering Information PART PART TEMP PKG NUMBER MARKING C PACKAGE DWG ISL6423BERZ 6423BERZ 20 to 85 2414 4x4 QFN L24 4x4D Note Pb free ISL6423BEVEZ ISL6423BEVEZ 20 to 85 28 Ld EPTSSOP M28 173B Note Pb free NOTE Intersil Pb free plus anneal products employ special Pb free material sets molding compounds die attach materials and 100 matte tin plate termination finish which are ROHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 Add T suffix for tape and reel 1 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 1 888 468 3774 Intersil and design is a registered trademark of Intersil Americas Inc Copyright Intersil Americas Inc 2006 2007 All Rights Reserved All other trademarks mentioned are the property of their respective owners Pinouts ISL6423B 28 LD EPTSSOP TOP VIEW vec 1 28 CPSWIN Nc 2 CPSWOUT F
8. I C bus These will be written by the microprocessor as shown below The spare bits of registers can be used for other functions 11 intersil FN6412 1 April 10 2007 TABLE 7 STATUS REGISTER SR1 CONFIGURATION SR1H SR1M 581 OTF CABF OUVF OLF BCF FUNCTION 0 0 0 X X X X X SR1 is selected 0 0 0 X X X 0 X lout lt set limit Normal Operation 0 0 0 X X X 1 X lout gt Static Dynamic Limiting Mode Power blocks disabled 0 0 0 X X X X 0 lobck x set limit Normal Operation 0 0 0 X X X X 1 lobck gt Dynamic Limiting Mode Power blocks disabled 0 0 0 X X 0 X X ViN Vour Within specified range 0 0 0 X X 1 X X Vin VouT is not within specified range 0 0 0 X 0 X X X Cable is connected lo is gt 20mA 0 0 0 X 1 X X X Cable is open lo lt 2 0 0 0 0 X X X X Tj 130 C Normal operation 0 0 0 1 X X X X Tj gt 150 C Power blocks disabled TABLE 8 TONE REGISTER SR2 CONFIGURATION SR2H SR2M SR2L ENT MSEL TTH FUNCTION 0 0 1 X X X X X SR2 is selected 0 0 1 0 0 X X X Int Tone 22kHz modulated by EXTM Ty Tr 10us typ 0 0 1 0 1 X X X Ext 22k modulated input Ty Tr 10ps typ 0 0 1 1 0 X X X Int Tone 22kHz modulated by ENT bit Ty Tr 10us typ 0 0 1 X X ecoder e is set af200hV max s WA CON Es ool Sits NOTE X indicates Read Only and is a Don t Care for the Write mode TABL
9. LT 3 26 CPVOUT SGND 4 25 EXTM SGND 5 24 SDA TCAP 6 23 SCL ADDRO 22 TDOUT ADDR1 TDIN BYPASS 9 20 vo PGND 19 NC GATE 18 NC VSW 12 AGND NC SELVTOP cs TXT ww BDTI C comi ntersi l SGND EXTM TCAP SDA ADDRO SCL ADDR1 TDOUT BYPASS TDIN PGND vo ray 7 110 1111 1121 o 8 s m z 7 o o S 5 7 i FN6412 1 2 intersil April 10 2007 I S123u1 2002 OT T ZlV9Nd Block Diagram 70 GATE E w 1 PGND 6 1 1 1 CS ILIM1 cs p 1 1 TDOUT TDIN ON CHIP LINEAR UVLO POR SOFT START NOTE 1 Pinouts shown are for the QFN package PROTECTION LOGIC SCHEME 1 oc1 COMPENSATION 11 17 16 3 4 L LI OLFIBCE TIC OVERCURRENT gt d 2 z aj lt SELVTOP OUVF Ici OLFIBCF 2 ENT INTERFACE VTOP VBOT SLOPE ST I i EXT TONE CKT ENT1 He INT 5V 3 SOFT START 2 E EN1 EN2 e g S g 1 2 18 20 21 19 THERMAL SHUTDOWN I S123u1 2002 OT T ZlV9Nd Typical Application Schematic QFN E o X FLT BAR lt EXTM c29 R11 44 100 SDA in C25 47n Aem S lt SCL L4 220pH 1 2 alo NIN F FE 99 lt VLNB n oo ee e PRG cx ADDR1 SL6423bER TDO ASS A 08 1 5KE24 Q4 2N2222A SRIN TPC6002 lt TXT lt TDOUT lt SELVTO
10. Note 8 900 ms Dynamic Overload Protection On Time TON 51 ms Static Output Current Limiting IMAX DCL 1 Note 8 1000 mA Cable Fault CABF Threshold ICAB EN 1 Vo 19V No Tone 2 10 20 mA 5 intersil FN6412 1 April 10 2007 Electrical Specifications Vcc 12V T4 20 C to 85 C unless otherwise noted Typical values are at TA 25 VBOT ENT L DCL L lout 12mA unless otherwise noted See software description section for 2 access to the system Continued PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS TONE OSCILLATOR Tone Frequency ftone ENT 20 0 22 0 24 0 kHz Tone Amplitude Vtone ENT lo 5mA 500 680 800 mV Tone Duty Cycle dctone ENT H 40 50 60 Tone Rise or Fall Time Tr Tf ENT H 5 10 14 us TONE DECODER Input Amplitude Vtdin 200 1000 mV Frequency Capture Range Ftdin 17 5 26 5 kHz Input Impedance Zdet 8 6 Detector Output Voltage Vtdout L Tone Present 3mA 0 4 V Detector Output Leakage Itdout H Tone absent Vo 6V 10 Tone Decoder Rx Threshold VRXth TXT L and TTH 0 Note 9 100 150 200 mV Tone Decoder Tx Threshold VTXth TXT H and TTH 0 Note 9 400 450 500 mV LINEAR REGULATOR Drop out Voltage lout 750mA 5 0 8 1 05 V Output Backward Leakage Current EN
11. P NOTE SDA and SCL require pull up to the required logic level CMS06 L c22 C18 C19 C20 56 10 10 10 o o o o Absolute Maximum Ratings Supply Voltage Logic Input Voltage Range SDA SCL ENT DSQIN 1 and 2 SEL18V 1 and 2 0 5V to 7V 8 0V to 18 0V Thermal Information Thermal Resistance Typical Notes 2 3 QFN Package Notes 2 3 EPTSSOP Package Notes 2 3 Maximum Junction Temperature Note 4 Maximum Storage Temperature Range Operating Temperature Range 03A C W 38 40 C to 150 C 20 C to 85 C 03c CC W 4 5 CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTES 2 03A is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features See Tech Brief TB379 3 For 05c the case temp location is the center of the exposed metal pad on the package underside 4 150 C max junction temperature is intended for short periods of time to prevent shortening the lifetime Operation close to 150 C junction may trigger the shutdown of the device even before 150 C since this number is specified as typical Electrical Specificati
12. SEE DETAIL X Fnter si 1 C BASEPLANE SEATING PLANE oo8 SIDE VIEW 0 5 24 0 25 ih 0 00 MIN 24X 0 6 0 05 MAX DETAIL X NOTES 1 Dimensions are in millimeters Dimensions in for Reference Only 2 Dimensioning and tolerancing conform to AMSE Y14 5m 1994 3 Unless otherwise specified tolerance Decimal 0 05 4 Dimension b applies to the metallized terminal and is measured between 0 15mm and 0 30mm from the terminal tip 5 Tiebar shown if present is a non functional feature 6 The configuration of the pin 1 identifier is optional but must be located within the zone indicated The pin 1 indentifier may be either a mold or mark feature 15 intersil FN6412 1 April 10 2007 Thin Shrink Small Outline Exposed Pad Plastic Packages EPTSSOP M28 173B 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0 047 1 20 1 0 002 0 006 0 05 0 15 2 0 031 0 051 0 80 1 05 0 0075 0 0118 0 19 0 30 9 C 0 0035 0 0079 0 09 0 20 D 0 378 0 386 9 60 9 80 3 E1 0 169 0 177 4 30 4 50 4 e 0 026 BSC 0 65 BSC E 0 246 0 256 6 25 6 50 L 0 0177 0 0295 0 45 0 75 6 ems 155303 0
13. T of the linear for a period greater that 2ms the output is disabled for a period of 50ms and the BCF bit is set If the 19 3V remains connected the output will cycle through the ON 2ms OFF 50ms The output will return to the setpoint when the fault is removed bit is set high during the 50ms OFF period Thermal Protection This IC is protected against overheating When the junction temperature exceeds 150 typical the step up converter and the linear regulator are shut off and the OTF bit of the SR is set HIGH When the junction is cooled down to 130 C typical normal operation is resumed and the OTF bit is reset LOW If a part is repeatedly driven to the shutdown gt and t ip is l BEI d B ourth occurrence am is Itch BET T bar low This OTF counter and FLT bar can be reset the chip restarted by either a power down up and reload the 2 or power can be left on and the reset accomplished by toggling the I C bit EN low then back high External Output Voltage Selection When the I C bit VSPEN is set high the output voltage can be selected by the 2 bus Additionally the package offers the pin SELVTOP for independent 13 thru 19V output voltage selection when the VSPEN bit is set low A summary of the voltage control is given in Table 1 For further details refer to the individual registers SR1 and SR3 TABLE 1 VSPEN VTOP VBOT SELVTOP VOUT 0 0 0 13 3V
14. TTH Tone THreshold is the OR of the signal pin TXT ww BDTI C com ntersi Electrical Characteristics TABLE 12 TEST PARAMETER CONDITION MIN TYP MAX Input Logic SDA SCL 2 0V High VIH Input Logic SDA SCL 0 8V Low VIL Input Logic SDA SCL 10 Current IIL 0 4V lt Vpp lt 3 3V Input Logic VOL 0 4V 3mA Current IOL Input SDA SCL 165mV 200mV 235mV Hysteresis SCL Clock 0 100kHz 400kHz Frequency Input Filter 50ns Spike reject 14 intersil FN6412 1 April 10 2007 Package Outline Drawing L24 4x4D 24 LEAD QUAD FLAT NO LEAD PLASTIC PACKAGE Rev 2 10 06 PIN 1 INDEX AREA ax 0 15 4 00 Mo 4 00 TOP VIEW 3 8TYP TYPICAL RECOMMENDED LAND PATTERN AX 25 20X 0 50 _ PIN 1 CORNER 19 24 C 0 25 18 1 f LJ 2 50 0 15 13 12 7 o 0 4 0 1 B 24x 0 23 48 07 BOTTOM VIEW
15. V FIGURE 1 TONE WAVEFORM 7 intersil 6412 1 s April 10 2007 Typical Performance Curves 0 80 0 80 0 70 0 70 0 60 0 60 lour max lour max 0 50 0 50 lt lt 5 0 40 E 0 40 2 o 0 30 0 30 0 20 0 20 0 10 0 10 0 00 0 00 0 20 40 60 80 0 20 40 60 80 TEMPERATURE TEMPERATURE FIGURE 2 OUTPUT CURRENT DERATING EPTSSOP FIGURE 3 OUTPUT CURRENT DERATING 4x4 QFN Functional Pin Description SYMBOL FUNCTION SDA Bidirectional data from to I2C bus SCL Clock from I2C bus VSW Input of the linear post regulator PGND Dedicated ground for the output gate driver of respective PWM CS Current sense input con imjt is SGND al gro e sense resistor Rsc at this pin for desired peak overcurrent valye fogthe boost FET The helstatif mode C t Ert er S ellc TCAP Capacitor for setting rise and fall time of the output voltage Typical value is 0 1 BYPASS Bypass capacitor for internal 5V TXT TXT is the Tone Transmit signal input used to change the Tone Decoder Threshold from TXT 0 200mV max during Receive to TXT 1 400mV min during Transmit VCC Main power supply to the chip GATE This output drives the boost FET gate The output is held low when Vcc is below the UVLO threshold VO Output voltage for the LNB is available at VO pin ADDRO amp ADDR1 Logic comb
16. ator makes an ideal choice for advanced satellite set top box and personal video recorder applications The device utilizes built in DC DC step up converters that operates from a single supply source ranging from 8V to 14V and generates the voltage needed to enable the linear post regulator to work with a minimum of dissipated power An undervoltage lockout circuit disables the device when VCC drops below a fixed threshold 7 5V typ DiSEqC Encoding The internal oscillator is factory trimmed to provide a tone of 22kHz in accordance with DiSEqC EUTELSAT standards No further adjustment is required The tone oscillator can be controlled either by the 2 interface ENT bit or by a dedicated pin EXTM that allows immediate DiSEqC data encoding separately for each LNB All the functions of this IC are controlled via the 12 bus by writing to the system registers The same registers can be read back and four bits will report the diagnostic status The internal oscillator operates the converters at twenty times the 22k tone frequency The device offers full 2 compatibility supports 2 5 3 3V or 5V logic up an operational speed of 400kHz If the Tone Enable ENT bit is set LOW and the MSEL bits set LOW through 2 tiva he internal tone sigri th of C 680mVpp typical e THe pr of this signal usually provides the LNB with information about the band to be received Burst coding of the tone
17. can be accomplished due to the fast response of the EXTM input and rapid tone response This allows implementation of the DiSEqC EUTELSAT protocols When the ENT bit is set HIGH a continuous 22kHz tone is generated regardless of the EXTM pin logic status for the regulator channel LNB A The ENT bit must be set LOW when the EXTM pin is used for DiSEqC encoding The EXTM accepts an externally modulated tone command when the MSEL I C bit is set HIGH and ENT is set LOW DiSEqC Decoder TDIN is the input to the tone decoder It accepts and the tone signal derived from the Voyrt thru the 10nF decoupling capacitor The detector threshold can be set to 200mV max in the Receive mode and to 400mV min in the Transmit mode by means of the logic presented to the TXT pin If tone is detected the open drain pin TDOUT is asserted low This enables the tone diagnostics to be performed apart from the normal tone detection function Linear Regulator The output linear regulator will sink and source current This feature allows full modulation capability into capacitive loads as high as 0 75 In order to minimize the power dissipation the output voltage of the internal step up converter is adjusted to allow the linear regulator to work at minimum dropout When the device is put in the shutdown mode EN LOW the PWM power block is disabled When the regulator blocks are active EN HIGH and VSPEN LOW the output can be controlled via I2C lo
18. ck and five I C bits will report the diagnostic status Separate enable command sent on the 2 bus provides for standby mode control for the PWM and linear combination disabling the output and forcing a shutdown mode The output channel is capable of providing 750mA of continuous current The overcurrent limit can be digitally programmed to four levels The External modulation input EXTM can accept a modulated Diseqc command and transfer it symmetrically to the output Alternatively the EXTM pin can be used to modulate the continuos internal tone The FLT pin serves as an interrupt for the processor when any condition turns OFF the LNB controller Over Temperature Overcurrent Disabled The nature of the Disable can be read of the I2C registers April 10 2007 Features Single Chip Power solution ISL6423B FN6412 1 Operation for 1 Tuner 1 Dish Applications Integrated DC DC Converter and 2 Interface Switch Mode Power Converter for Lowest Dissipation Boost PWMs with gt 92 Efficiency Selectable 13 3V or 18 3V Outputs Digital Cable Length Compensation 1V 12 and Pin Controllable Output Output Back Bias Capability of 28V e 1C Compatible Interface for Remote Device Control Registered Slave Address 0001 00XX e 2 5V 3 3V 5V Logic Compatible External Pin to Toggle Between V and Polarization Built In Tone Oscillator Factory Trimmed to 22kHz Facilitates DiSEqC EUTELSAT Encoding
19. e power blocks disabled Once the Vcc rises above UVLO the POWER OK signal to the I C is asserted high and the 2 interface becomes operative and the SR s can be configured by the main microprocessor About 400mV of hysteresis is provided in the UVLO threshold to avoid false triggering of the Power On reset circuit 2 comes up with EN 0 EN goes HIGH at the same time as or later than all other 2 data for that PWM becomes valid ADDRO and ADDR1 Pins Connecting these pin to GND the chip 2 interface address is 0001000 but it is possible to pore four Ter o the logic levels TABLE 11 ADDRESS PIN CHARACTERISTICS VADDR ADDR1 ADDRO Vappr 1 0001000 0 0 VADDR 2 0001001 0 1 3 0001010 1 0 VADDR 4 0001011 1 1 13 intersil FN6412 1 April 10 2007 PC Bit Description BIT NAME DESCRIPTION EN ENable Output for channels 1 and 2 VTOP Voltage TOP select i e 18V 19V for channels 1 and 2 VBOT Voltage BOTtom select i e 13V 14V for channels 1 and 2 ENT ENable Tone MSEL Modulation SELect DCL Dynamic Current Limit select VSPEN Voltage Select Pin ENable ISELH Current limit I SELect High and Low bit and ISELL OTF Over Temperature Fault bit CABF CABle Fault or open status bit OUVF Over and Under Voltage Fault status bit OLF Over Load Fault status bit BCF Backward Current Fault bit
20. er than 51ms will shutdown the output for 900ms during which the I C bit OLF is set high At the end of 900ms the OLF bit is returned to the low state a soft start cycle 20ms long is initiated to ramp VSW and Vout back up If the fault is still present the overcurrent will be reached early in the soft start cycle and the 51ms shutdown timer will be started again If the fault is still present at the end of the 51ms the OLF bit is again set high and the device once again enters the 900ms OFF time This dynamic operation greatly reduces the power dissipation in a short circuit condition while still ensuring excellent power on start up in most conditions 9 intersil FN6412 1 April 10 2007 However there could be some cases in which a highly capacitive load on the output may cause a difficult start up when the dynamic protection is selected This can be solved by initiating any power start up in static mode DCL HIGH and then switching to the dynamic mode DCL LOW after a predetermined interval When in static mode the OLF bit goes HIGH when the current clamp limit is reached and returns LOW at the end of initial power on soft start In the Static mode the output current through the linears is limited to 990mA typ When a 19 3V line is connected onto a VOUT1 or 2 that has been set to 13 3V the linear will then enter a back current limited state When a back current of greater than 140mA typical is sensed at the lower FE
21. ersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 16 intersil FN6412 1 April 10 2007
22. gic to be 13V 14V or 18V 19V typical by means of the VTOP and VBOT bits Voltage Select for remote controlling of non DiSEqC LNBs When the regulator blocks are active EN HIGH and VSPEN HIGH the VBOT and SELVTOP pin will control the output between 13V and 14V and the VTOP and SELVTOP pin will control the output between 18V and 19V Output Timing The output voltage rise and fall times can be set by an the external capacitor on the TCAP pin The output rise and fall times is given by the equation _ 327 6T SUA EQ 1 Where C is the TCAP value in nF T is the required transition time in ms and AV is the differential transition voltage from range in Volts h m V TGAP is 0 15uF Too large a value of TCAP prevents the output from rising to the nominal value within the soft start time when the error amplifier is released Too small a value of the TCAP can cause high peak currents in the boost circuit For example a 10V ms slew on a 80uF VSW capacitor with an inductor of 15uH can cause a peak inductor current of approximately 2 3A Current Limiting Dynamic current limiting block has four thresholds that can be selected by the ISEL H and ISEL L bits of the SR Refer to Table 8 and Table 9 for threshold selection using these bits The DCL bit has to be set to low for this mode of operation In the dynamic overcurrent mode a fault exceeding the selected overcurrent threshold for a period great
23. ination at the ADDRO amp 1 can select four different chip select addresses EXTM This pin can be used in two ways 1 As an input for externally modulated Diseqc tone signal which is transferred to the symmetrically onto 2 Alternatively apply a Diseqc modulation envelope which modulates an internal tone and then transfers it symmetrically onto Vout FLT This is an Open Drain output from the controller When the FLT goes low it indicates that an Over Temperature Over load fault UVLO or an 2 reset condition has occurred The processor should then look at the 2 register to get the actual cause of the error A high on the FLT indicates that the device is functioning normally CPVOUT CPSWIN A 47n charge pump decoupling capacitor is to be connected to CPVOUT Connect a 1 5n capacitor between CPSWIN and CPSWOUT CPSWOUT SELVTOP When this pin is low the is in the 13V 14V range selected by the I C bit VBOT When this pin is high the 18V 19V range selected by the I C bit VTOP The Voltage select pin enable VSPEN I C bit must be set low for the SELVTOP pins to be active Setting VSPEN high disables this pins and voltage selection will be done using the 12 bits VBOT and only TDIN TDOUT TDIN is the tone decoder input and TDOUT is the tone detector output TDOUT is an open drain output FN6412 1 8 i i Intersil April 10 2007 Functional Description The ISL6423B single output voltage regul
24. intersil Data Sheet Single Output LNB Supply and Control Voltage Regulator with I7C Interface for Advanced Satellite Set Top Box Designs The ISL6423B is a highly integrated voltage regulator and interface IC specifically designed for supplying power and control signals from advanced satellite set top box STB modules to the low noise blocks LNBs of singe antenna ports The device consists of a current mode boost PWM and a low noise linear regulator along with the circuitry required for 22kHz tone generation modulation and 2 device interface The device makes the total LNB supply design simple efficient and compact with low external component count The current mode boost converters provides the linear regulator with input voltage that is set to the final output voltages plus typically 0 8V to insure minimum power dissipation across each linear regulator This maintains constant voltage drop across the linear pass element while permitting adequate voltage range for tone injection The final regulated output voltage is available at output terminals to support the operation of an antenna ES for single tuners ANNE each PS olled in two ways full MUT an V bits or set the I C to the lower i e 13V 14V and switch to higher range i e 18V 19V with the SELVTOP pin All the functions on this IC are controlled via the 12 bus by writing 8 bits words onto the System Registers SR The same register can be read ba
25. mpler transmission it waits one clock without checking the slave acknowledging and sends the new data This approach though is less protected from error and decreases the noise immunity ISL6423B Software Description Interface Protocol The interface protocol is comprised of the following as shown below in Table 2 A start condition S A chip address byte MSB on left the LSB bit determines read 1 or write 0 transmission the assigned 2 slave address for the ISL6423B is 0001 OXXX A sequence of data 1 byte Acknowledge A stop condition P TABLE 2 INTERFACE PROTOCOL S 0 0 0 1 0 A1 A0 Rw Data 8 bits P System Register Format R W Read and Write bit R Read only bit All bits reset to O at Power On TABLE 3 STATUS REGISTER SR1 RW R W RW R R R R R SR1H SRIM SR1L OTF CABF OUVF OLF BCF TABLE 4 TONE REGISTER SR2 o TABLE 5 COMMAND REGISTER SR3 R W RW R W R W R W SR3H SR3M SR3L DCL VSPEN X ISELH ISELL TABLE 6 CONTROL REGISTER SR4 RW RWIRW R W RW SR4H SRAM SR4L VTOP VBOT Transmitted Data 2 bus WRITE mode When the R W bit in the chip is set to 0 the main microprocessor can write on the system registers SR2 thru SR4 of the ISL6423B via
26. on on the SDA line while SCL is HIGH A STOP condition must be sent before each START condition S P START STOP CONDITION CONDITION FIGURE 5 START AND STOP WAVEFORMS 10 intersil FN6412 1 April 10 2007 Byte Format Every byte put on the SDA line must be eight bits long The number of bytes that can be transmitted per transfer is unrestricted Each byte has to be followed by an acknowledge bit Data is transferred with the most significant bit first MSB Acknowledge The master microprocessor puts a resistive HIGH level on the SDA line during the acknowledge clock pulse Figure 6 The peripheral that acknowledges has to pull down LOW the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during this clock pulse Of course set up and hold times must also be taken into account The peripheral which has been addressed has to generate an acknowledge after the reception of each byte otherwise the SDA line remains at the HIGH level during the ninth clock pulse time In this case the master transmitter can generate the STOP information in order to abort the transfer The ISL6423B will not generate the acknowledge if the POWER OK signal from the UVLO is LOW Sc NS d DA FIGURE 6 ACKNOWLEDGE ON THE I C BUS Transmission Without Acknowledge Avoiding detection of the acknowledgement the microprocessor can use a si
27. ons Vcc 12V TA 20 C to 85 C unless otherwise noted Typical values are at TA 25 C EN VBOT L ENT L DCL L lour 12mA unless otherwise noted See software description section for 2 access to the system PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage Range 8 12 14 V Standby Supply Current EN L 1 5 3 0 mA Supply Current lin EN VBOT ENT No Load 4 0 8 0 mA UNDERVOLTAGE LOCKOUT Start Threshold 7 5 EC 7 95 Stop Threshold JL C conj nt er S 7 55 Start to Stop Hysteresis 50 400 500 mV SOFT START COMP Rise Time Note 5 Note 5 8196 Cycles Output Voltage Note 5 Voi Refer to Table 1 13 04 13 3 13 56 V Vo1 Refer to Table 1 14 02 14 3 14 58 V Vo1 Refer to Table 1 17 94 18 3 18 66 V Vo1 Refer to Table 1 19 00 19 3 19 68 V Line Regulation DVoi1 Vin 8V to 14V Vo 13 3V 4 0 40 0 mV DVO2 ym BV to 14V Vo 18 3V 4 0 60 0 mV Load Regulation DVoi lo to 350mA 50 80 mV DVO2 omA to 750mA 100 200 mV Dynamic Output Current Limiting IMAX DCL 0 ISEL H 0 ISEL L 0 Note 8 275 305 345 mA DCL 0 ISEL H 0 ISEL L 1 Note 8 515 570 630 mA DCL 0 ISEL H 1 ISEL L 0 Note 8 635 705 775 mA DCL 0 ISEL H 1 ISEL L 1 Note 8 800 890 980 mA Dynamic Overload Protection Off Time TOFF DCL 0 Output Shorted
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intersil ISL6423B handbook