intersil ISL6140/ISL6150 handbook
Contents
1. 1 000 15 000 0 800 12 000 T E 0 600 5 9 000 E gt E 0 400 gt 6 000 a a 0 200 3 000 0006 20 40 60 80 100 0 0005 20 40 60 80 100 VDD VOLTAGE V VDD V FIGURE 10 IDD vs VDD FIGURE 11 VGATE vs VDD 1 000 15 000 0 800 12 000 T E E 0 600 S 9 000 a 5 lt corp nt er a a 0 200 3 000 0 000 0 000 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 VDD VOLTAGE V VDD V FIGURE 12 IDD vs VDD 20V FIGURE 13 VGATE vs VDD 20V 0 95 14 5 0 93 14 3 gt lt 091 9 14 1 E S x 0 89 13 9 o lt 0 87 13 7 13 5 0 8540 10 60 110 40 10 60 110 TEMPERATURE TEMPERATURE FIGURE 14 IDD CURRENT VDD 80V FIGURE 15 GATE VOLTAGE AT VDD 80V 12 intersil ISL6140 ISL6150 Typical Performance Curves continued GATE VOLTAGE V CURRENT mA 14 5 14 0 13 5 13 0 REM ndi 12 5 12 0 40 10 60 110 TEMPERATURE FIGURE 16 GATE VOLTAGE VDD 17V 0 048 0 050 0 052 co 0 056 0 058 40 10 60 110 TEMPERATURE FIGURE 18 PULL UP CURRENT 0 34 0 32 gt 03 5 RENNES EC uc a 0 28 gt 0 26 0 24 40 10 60 110 TEMPERATURE FIGURE 20 PWRGD ISL62. PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0 0532 0 0688 1 35 1 75 0 0040 0 0098 0 10 0 25 B 0 013 0 020 0 33 0 51 9 0 0075 0 0098 0 19 0 25 D 0 1890 0 1968 4 80 5 00 3 E 0 1497 0 1574 3 80 4 00 4 e 0 050 BSC 1 27 BSC H 0 22841 0 2440 5 80 6 20 h 0 0099 0 0196 0 25 0 50 5 L 0 016 0 050 0 40 1 27 6 N 8 7 09 8 09 8 Rev 0 12 93 ml ntersi l All Intersil U S products are manufactured assembled and tested utilizing 1509000 quality systems Intersil Corporation s quality certifications can be viewed at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 18 intersil
3. 1 R5 9 09 1 R6 10 1 C1 150nF 25V C2 3 3nF 100V Q1 IRF530 100V 17A 0 110 CL 100pF 100V 1 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 321 724 7143 Intersil and design is a registered trademark of Intersil Americas Inc Copyright O Intersil Americas Inc 2003 All Rights Reserved other trademarks mentioned are the property of their respective owners ISL6140 ISL6150 Pin Description PWRGD ISL6140 L Version Pin 1 This digital output is an open drain pull down device The Power Good comparator looks at the DRAIN pin voltage compared to the internal VPG reference VPG is nominal 1 7V this essentially measures the voltage drop across the external FET and sense resistor If the voltage drop is small 1 7V is normal the PWRGD pin pulls low to VEE this can be used as an active low enable for an external module If the voltage drop is too large gt 1 7V indicates some kind of short or overload condition the pull down device shuts off and the pin becomes high impedance Typically an external pull up of some kind is used to pull the pin high many brick regulators have a pull up function built in PWRGD ISL6150 H Version Pin 1 This digital output is a variation of an open drain pull down device The Power Good comparator is the same as described above but the polarity of the output is
4. 4 5 for GATE WA 26 INRUSH CURRENT i S int bl Mi the load current equals zero Keep in mind that the tolerance of the sense resistor 196 Power Supply Ramp here and the IC Over Current trip voltage Vcg affect the accuracy of the trip point that s why the trip point doesn t Figure 27 shows the Power Supply voltage to the VDD pin necessarily equal the 2 5A design target with respect to GND at the VEE pin ramping up In this case the values chosen were R4 562K R5 5 9K R6 13 3K that sets the UV trip point around 38V and the OV trip point to 54V Note that the GATE starts at OV and stays there until the UV trip point 38V is exceeded then it ramps slowly based on the external components chosen up to around 13V where it is clamped it stays there until the power supply exceeds the OV trip point at 54V the GATE shut off is much faster than the turn on The total time scale is 2 seconds the VDD ramp speed was simply based on the inherent characteristic of the particular power supply used T 1 1 00 YeDIW POS 0 000 WV 100 1 Som DC 0 020 48 No cap Load Current 4 5 00 Pos 15 00 WV 10 0 1 iR DC iip MODE 250 0000 us 250 0000 us 50 o m REALTIME 2 47 3 90625 W x26 4 105 000 us 1 1612 2 31250 WV Gell il 0000 us DELTA Y 1 59375 W LTA X O000 us EN 7273 kee FIGURE 28 OVER CURRENT AT 2 3A 15 intersil ISL61
5. Typical Values for a representative system which assumes 36V to 72V supply range 48 nominal UV 37V OV 71V 1A of typical current draw 2 5 Amp Over Current 100uF of load capacitance CL equivalent RL of 48Q R V I 48V 1A R1 R2 R3 R4 R5 R6 C1 C2 Q1 0 020 196 100 5 18kQ 5 562kQ 1 9 09kQ 1 10kQ 1 150nF 25V 3 3nF 100V IRF530 100V 17A 0 110 7 DRAIN Applications Quick Guide to Choosing Component Values See Block Diagram for reference This section will describe the minimum components needed for a typical application and will show how to select component values Note that typical values may only be good for this application the user may have to select some component values to match the system Each block will then have more detailed explanation of how it works and alternatives R4 R5 R6 together set the Under Voltage UV and Over Voltage OV trip points When the power supply ramps up and down these trip points and their 20mV nominal hysteresis will determine when the gate is allowed to turn on and off the UV and OV do not affect the PWRGD output The input power supply is divided down such that when each pin is equal to the trip point nominal is 1 223V the comparator will switch Vuy 1 223 R4 R5 R6 R5 R6 Voy 1 223 R4 R5 R6 R6 The values of R4 562K R5 9 09K and R6 10K will give trip points of UV 37V and
6. R3 C2 are related to the gate driver as it controls the inrush current R2 prevents high frequency oscillations 10Q is a typical value R2 10Q R3 and C2 act as a feedback network to control the inrush current inrush Igate CL C2 where CL is the load capacitance including module input capacitance and Igate is the gate pin charging current nominally 45uA So choose a value of acceptable inrush for the system and then solve for C2 So 45 CL C2 Or C2 45uA CL C1 and R3 prevent Q1 from turning on momentarily when power is first applied Without them C2 would pull the gate of Q1 up to a voltage roughly equal to VEE C2 Cgs Q1 where Cgs is the FET gate source capacitance before the ISL6140 could power up and actively pull the gate low Place C1 in parallel with the gate capacitance of Q1 isolate them from C2 by R3 C1 Vinmax Vth Vth C2 Cgd where Vth is the FET s minimum gate threshold Vinmax is the maximum operating input voltage and Cgd is the FET gate drain capacitance Vinmax deltaVgate 5mA its value is not critical typical value is 18 Applications Inrush Current The primary function of the ISL6140 hot plug controller is to control the inrush current When a board is plugged into a li inp ci f th board s power j Is ansients as they harge up This can cause glitches the system power supply which can affect o
7. RL is 6200 for around 80mA The load VDD 60V capacitance is 100uF 100V The Sense Resistor R1 is n INY 0 02Q trip point at 2 5A well above the inrush current here 19 5 oil POS 30 00 v Note that the load current starts at 0 FET off reaches a peak of 850mA as the GATE voltage ramps and turns on the FET slowly and then settles out at 80mA once the CL is fully charged to the 48V The width of the inrush current pulse is 8ms wide For comparison with the same conditions but without the gate controlled FET the current was over 20A during a 130us pulse 4 2 10 0 V DIV POS 30 00 V TRI EGER NODE 200 000 ms 800 000 ms 1 80000 ae 200 as DIV REAL TINE x y2 r2 54 3750 V X2CF2 832 000 as 2 5 000 v Eo gt VOS P WBELTA X 2 00000 oS e REOR CAD GRE 20 0 1 OC Load oad 2 9 86 FIGURE 27 POWER SUPPLY RAMP Current Pos 80 00 9 19 0 1 OC Over Current at 2 3A In Figure 28 an Electronic Load Generator was used to ramp the load current no load resistor or capacitor was 4 5 00 connected The sense Resistor R1 is 0 020 that should make the nominal Over Current trip point 2 5A 10 0 1 inn OC The GATE is high clamped to around 13V keeping the _PWRGD bar TRLSEER NODE FET on as the EG pane to ramp up from zero the e mad WAN PT cg pymes i Hn Bi when the load C cea takes
8. Note that this is i at the same time MAS ofld be properly control the inrush current But if finer control is needed there are many variables involved to consider the number of pins in the connector the lengths of the pins the amount of mechanical play in the pin to connector interface the amount of extra time versus the shorter pin length the amount of input capacitance versus the ability of the power supply to charge it the manufacturing cost adder if any of different length pins etc Applications PWRGD PWRGD The PWRGD PWRGD outputs are typically used to directly enable a power module such as a DC DC converter The PWRGD ISL6140 is used for modules with active low enable L version PWRGD ISL6150 for those with active high enable H version The modules usually have a pull up device built in as well as an internal clamp If not an external pull up resistor may be needed since the output is open drain If the pin is not used it can be left open For both versions the PG comparator compares the DRAIN pin to VEE connected to the source of the FET if the voltage drop exceeds VPG 1 7V nominal that implies the drop across the FET is too high and the PWRGD pin should go in active power NO GOOD ISL6140 L version Figure 6 Under normal conditions DRAIN lt VPG the Q2 DMOS will turn on pulling PWRGD low enabling the module VDD VIN VOUT SECTION OF ISL6140 L VERSION O
9. OV 71V 6 intersil ISL6140 ISL6150 Q1 is the FET that connects the input supply voltage to the output load when properly enabled It needs to be selected based on several criteria maximum voltage expected on the input supply including transients as well as transients on the output side maximum current expected power dissipation and or safe operating area considerations due to the quick over current latch power dissipation is usually not a problem compared to systems where current limiting is used however worst case power is usually at a level just below the overcurrent shutdown Other considerations include the gate voltage threshold which affects the rps ow which in turn affects the voltage drop across the FET during normal operation and the maximum gate voltage allowed the IC clamp output is clamped to 14 R1 is the Over Current sense resistor if the input current is high enough such that the voltage drop across R1 exceeds the SENSE comparator trip point B0mV nominal the GATE pin will go low turning off the FET to protect the load from the excessive current A typical value for R1 is 0 029 this sets an Over Current trip point of V R 0 05 0 02 2 5A So to choose R1 the user must first determine at what level of current it should trip Take into account worst case variations for the trip point 50 10mV 20 and the R1 resistance typically 1 or 5 Note that under normal cond
10. carefully choose a FET to match up with the reduced GATE voltage shown in the spec table 2 intersil ISL6140 ISL6150 Absolute Maximum Ratings Supply Voltage VDD to 0 3V to 100V DRAIN PWRGD PWRGD Voltage 0 3V to 100V UV OV Input 0 3V to 60V SENSE GATE Voltage 0 3V to 20V ESD Rating Human Body Model Per MIL STD 883 Method 3015 7 2000V Operating Conditions Temperature Range 40 C to 85 C Temperature Range 0 C to 70 Supply Voltage Range 36V to 72V Thermal Information Thermal Resistance Typical Note 3 Oya C W 8 Lead SOIC iesu mactare d 95 Maximum Junction Temperature Plastic Package 150 Maximum Storage Temperature 65 C to 150 C Maximum Lead Temperature Soldering 10s 300 C CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTES 3 0jA is measured with the component mounted on a high effective thermal conductivity test board in free air See Tech Brief TB379 for details 4 Typical
11. the DRAIN and VEE are almost the same voltage When the DRAIN voltage is high compared to VPG Q3 DMOS turns off and the resistor and Q2 clamp the PWRGD pin to one diode drop 0 7V above the DRAIN pin This should be able to pull low against the module pull up current and disable the module H VERSION VPG 1 7V ACTIVE HIGH ENABLE MODULE ON OFF VIN VOUT FIGURE 9 ACTIVE HIGH ENABLE MODULE Applications 1 To help protect th th oj thie G in C is internally clamped up to an 80V supply it will not be any higher than 15V nominal 14V From about 18V down to 10V the GATE voltage will be around 4V below the supply voltage at 10V supply the minimum GATE voltage is 5 4V worst case is at 40 C Applications Optional Components In addition to the typical application and the variations already mentioned there are a few other possible components that might be used in specific cases See Figure 29 for some possibilities If the input power supply exceeds the 100V absolute maximum rating even for a short transient that could cause permanent damage to the IC as well as other components on the board If this cannot be guaranteed a voltage suppressor such as the SMAT70A D1 is recommended When placed from VDD to VEE on the board it will clamp the voltage If transients on the input power supply occur when the supply is near either the OV or UV trip points the GATE could turn on or off momenta
12. up device The value of R8 is determined by how much current you want when pulled low also affected by the VDD voltage and you want to pull it low enough for a good logic low level An LED can also be placedjn series with R8 if desired n that case the criteria nte SI 7 C3 used to d lay the Over Cutrent shutdown as described in the OV and UV section Applications Brick Regulators One of the typical loads used are DC DC regulators some commonly known as brick regulators partly due to their shape and because it can be considered a building block of a system For a given input voltage range there are usually whole families of different output voltages and current ranges There are also various standardized sizes and pinouts starting with the original full brick and since getting smaller half bricks and quarter bricks are now common Other common features may include all components except some filter capacitors are self contained in a molded plastic package external pins for connections and often an ENABLE input pin to turn it on or off A hot plug IC such as the ISL6140 is often used to gate power to a brick as well as turn it on Many bricks have both logic polarities available Enable Hi or Lo input select the ISL6140 L version and ISL6150 version to match There is little difference between them although the L version output is usually simpler to interface The Enable input o
13. 140 VOL 1mA VOLTAGE GATE VOLTAGE V CURRENT mA IMPEDANCE 7 5 7 0 6 5 6 0 5 5 5 0 7 40 10 60 TEMPERATURE FIGURE 17 GATE VOLTAGE VDD 10V 110 45 40 35 T nter 25 20 40 10 60 7 5 7 0 6 5 6 0 5 5 5 0 TEMPERATURE C FIGURE 19 GATE PULL DOWN CURRENT 110 40 10 60 FIGURE 21 PWRGD ISL6150 IMPEDANCE TEMPERATURE 110 13 intersil ISL6140 ISL6150 Typical Performance Curves continued TRIP VOLTAGE V VOLTAGE V 1 90 1 85 1 80 1 75 1 70 1 65 40 10 60 110 TEMPERATURE FIGURE 22 DRAIN PG UP TRIP VOLTAGE 0 55 0 53 0 51 el 0 47 0 45 40 10 60 TEMPERATURE FIGURE 24 DRAIN PG HYSTERESIS VOLTAGE 110 1 3 TRIP VOLTAGE V E a 1 1 40 FIGURE 23 DRAIN PG DOWN TRIP VOLTAGE 10 60 TEMPERATURE C 110 0 0550 0 0530 0 0510 OLTAGE V D E 0 0470 10 60 TEMPERATURE FIGURE 25 SENSE TRIP VOLTAGE 110 14 intersil ISL6140 ISL6150 Inrush Current In the example in Figure 26 the supply voltage is 48V and the load resistor
14. 40 ISL6150 GND GND SHORT PIN V IN R1 VEE NFET INSTEAD OF SW1 ca R7 CL 5 i C1 R2 C2 Q1 V OUT FIGURE 29 ISL6140 50 OPTIONAL COMPONENTS SHOWN WITH Optional Components see text for when they should be used e D1 is a voltage ww tp i 5 UV threshold D2 and D3 are i sio hirdady b ftint20mV hfisterpsis With R6 the both D2 and D3 the ISL6140 L version uses just D2 If neither is used short the path of either to connect the DRAIN pin to C2 and Q1 The 1N4148 is a typical diode SW1 is a push button switch that can manually reset the fault latch after an Over Current shutdown It can also be replaced by a transistor switch R10 C4 are used to filter the VDD voltage such that small transients on the input supply do not trigger UV or OV R7 and are used to delay the Over Current shutdown R7 should be shorted if not used See the Over Current section for more details R8 is a pull up resistor for PWRGD if there is no other component acting as a pull up device An LED can also be placed in series with R8 if desired See Figure 8 CL is any extra output Load capacitance which can also be considered input capacitance for the external module new thresholds with a rising and falling input are RES RE eRe BOT RIRS Vuv rising VUVH e TER R5 R6 RA e RO RA e 5 vgate
15. 5 are filtered out if longer spikes need to be filtered an additional RC time constant can be added to stretch the time See Figure 29 note that the FET must be able to handle the high currents for the additional time To disable the Over Current function connect the SENSE pin to VEE GATE Pin 6 This analog output driyes the gate of the Tr GATE pin is g or S abpve its trip point the OV pin is E below its trip point and there is no Over Current condition VSENSE VEE 50mvV If any of the conditions are violated the GATE pin will be pulled low to shut off the FET The Gate is driven high by a weak 45uA nominal pull up current source in order to slowly turn on the FET It is driven low by a strong 32mA nominal pull down device in order to shut off the FET very quickly in the event of an Over Current or shorted condition DRAIN Pin 7 This analog input compares the voltage of the external FET DRAIN to the internal VPG reference nominal 1 7V for the Power Good function Note that the Power Good comparator does NOT turn off the GATE pin However whenever the GATE is turned off by OV UV or SENSE the Power Good Comparator will usually then switch to the power NOT good state since an off FET will have the supply voltage across it VDD Pin 8 This is the most positive Power Supply pin It can range from 10 to 80V Relative to If operation down near 10V is expected the user should
16. E to set the OV level as desired a three resistor divider can set both OV and UV UV Under Voltage Pin 3 This analog input compares the voltage on the pin to an internal voltage reference nominal 1 223V When the input goes below the reference high to low transition that signifies an UV Under Voltage condition and the GATE pin is immediately pulled low to shut off the external FET Since there is 20mV of nominal hysteresis built in the GATE will remain off until the UV pin rises above a 1 243V nominal low to high threshold A typical application will use an external resistor divider from VDD to VEE to set the UV level as desired a three resistor divider can set both OV and UV If there is an Over Current condition the GATE pin is latched off and the UV pin is then used to reset the Over Current latch the pin must be externally pulled below its trip point and brought back up toggled in order to turn the GATE back on assuming the fault condition has disappeared VEE Pin 4 This is the most Negative Supply Voltage such as in a 48V system Most of the other signals are referenced relative to this pin even though it may be far away from what is considered a GND reference SENSE Pin 5 This analog input measures the voltage drop across an external sense resistor between SENSE and to determine if the current exceeds an Over Current trip point equal to nominal 50mV Rsense Noise spikes of less than 2
17. LHOV Figures 1 3 1 0 7 8 12 0 us UV Low to GATE Low tPHLUV Figures 1 0 6 1 3 3 0 us UV High to GATE High tPLHUV Figures 1 1 0 8 4 12 0 us SENSE High to GATE Low tPHLSENSE Figures 1 2 2 3 4 us ISL6140 L VERSION DRAIN Low to PWRGD Low tPHLPG Figures 1 4A 0 1 0 9 2 0 us DRAIN High to PWRGD High iPLHPG Figures 1 4A 0 1 0 7 2 0 us ISL6150 H VERSION DRAIN Low to PWRGD DRAIN High iPHLPG Figures 1 4B 5 0 1 0 9 2 0 us DRAIN High to PWRGD DRAIN Low iPLHPG Figures 1 4B 5 0 1 0 8 2 0 us 4 Intersil ISL6140 ISL6150 Test Circuit and Timing Diagrams ISL6140 ISL6150 FIGURE 1 TYPICAL TEST CIRCUIT 2V r tPHLOV tPLHOV 13V GATE ov 1V 1V FIGURE 3A OV TO GATE TIMING ww BDITCcormtnter si l DRAIN gt lt IPLHPG tPHLPG gt PWRGD FIGURE 4A DRAIN TO PWRGD TIMING ISL6140 FIGURE 4 DRAIN TO PWRGD PWRGD TIMING SENSE gt tPHLSENSE GATE FIGURE 2 SENSE TO GATE TIMING 2V tPHLUV 13V GATE 1V ov 1V FIGURE 3B UV TO GATE TIMING DRAIN tPLHPG 1 0V FIGURE 4B DRAIN TO PWRGD TIMING ISL6150 5 intersil ISL6140 ISL6150 ISL6140 ISL6150 Block Diagram GND Voc INTERNAL VOLTAGE AND REFERENCE GENERATOR GND 1 PWRGD 6150 Vcc 1 7V 1 PWRGD 6140 VuvL VovH PWRGD PWRGD Vcg 50 OUTPUT DRIVE LOGIC AND GATE DRIVE L 5 SENSE
18. N OFF VPG 1 7V MODULE VIN VOUT FIGURE 6 ACTIVE LOW ENABLE MODULE When the DRAIN is too high the Q2 DMOS will shut off high impedance and the pin will be pulled high by the external module or an optional pull up resistor or equivalent disabling the module If a pull up resistor is used it can be connected to any supply voltage that doesn t exceed the IC pin maximum ratings on the high end but is high enough to give acceptable logic levels to whatever signal it is driving An external clamp may be used to limit the range DRAIN FIGURE 7 ACTIVE LOW ENABLE OPTO ISOLATOR The PWRCGD can also drive an opto coupler such as a 4N25 as shown in Figure 7 or LED Figure 8 In both cases they are on active when power is good Resistors R12 or R13 are chosen based on the supply voltage and the amount of current needed by the loads VDD SECTION OF ISL6140 L VERSION R13 VPG 1 7V LED GREEN DRAIN FIGURE 8 ACTIVE LOW ENABLE WITH LED 9 intersil ISL6140 ISL6150 ISL6150 H version Figure 9 Under normal conditions DRAIN VPG the Q3 DMOS will be on shorting the bottom of the internal resistor to VEE and turning Q2 off If the pull up current from the external module is high enough the voltage drop across the 6 2kQ resistor will look like a logic high relative to DRAIN Note that the module is only referenced to DRAIN not VEE but under normal conditions the FET is on and
19. PWRGD signal is not used here 7 BOM Bill Of Materials R1 0 020 596 R2 100 5 R3 18 5 R4 562kO 1 R5 9 09kQ 1 R6 10 1 C1 150nF 25V C2 3 3nF 100V Q1 IRF530 100V 17A 0 110 48V IN R1 Q1 FIGURE 31 TYPICAL APPLICATION 17 intersil ISL6140 ISL6150 Small Outline Plastic Packages SOIC E d NOTES 1 Symbols are defined in the MO Series Symbol List in Section 2 2 of Publication Number 95 2 Dimensioning and tolerancing per ANSI Y14 5M 1982 3 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusion and gate burrs shall not exceed 0 15mm 0 006 inch per side 4 Dimension E does not include interlead or protrusions en lead flash and protrusions shall not e 010 inch per side 5 The chamfer on th I If egent a vi gt feature must be located itin the crosshatched area L is the length of terminal for soldering to a substrate N is the number of terminal positions Terminal numbers are shown for reference only The lead width B as measured 0 36mm 0 014 inch or greater above the seating plane shall not exceed a maximum value of 0 61mm 0 024 inch 10 Controlling dimension MILLIMETER Converted inch dimensions are not necessarily exact ON OD M8 15 JEDEC MS 012 AA ISSUE C 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
20. SL6150 The three resistors R4 R5 R6 is the recommended approach for most cases But if acceptable values can t be found then consider 2 separate resistor dividers one for each pin both from VDD to VEE This also allows the user to adjust or trim either trip point independently Note that the top of the resistor dividers is shown in Figure 29 as GND Short pin In a system where cards are plugged into a backplane or any other case where pins are plugged into an edge connector the user may want to take advantage of the order in which pins make contact Typically pins on either end of the card make contact first although you may not know which end is first If you combine that with designating a pin near the center as the short pin GND and make it shorter than the rest then it should be the last pin to make contact The advantage of doing this the VDD and VEE pin connections are made first The IC is powered up but since the top of the resistor divider is still open both the UV and OV pins are pulled low to VEE which will keep the gate off This allows the IC time to get initialized and also allows the power supply to charge up any input capacitance By the time the resistor divider makes contact the power supply voltage on the card is presumably stabilized and the IC ready to respond when the UV pin reaches the proper voltage the IC will turn on the GATE of the FET and starts the controlled inrush current charging
21. TOR Physical layout of R1 SENSE resistor is critical to avoid the possibility of false overcurrent occurrences Since it is in the main input to output path the traces should be wide enough to support both the normal current and up to the over current trip point Ideally trace routing between the R1 resistor and the ISL6140 18L6150 pin 4 VEE and 5 SENSE is direct and as short as possible with zero current in the sense lines See Figure 5 There is a short filter 3us nominal on the comparator current spikes shorter than this will be ignored Any longer pulse will shut down the output requiring the user to either FX down the system belowt M trip point usually tr If current pulses longer than the 3us are expected and need to be filtered then an additional resistor and capacitor can be added As shown in Figure 29 R7 and C3 act as a low pass filter such that the voltage on the SENSE pin won t rise as fast effectively delaying the shut down Since the ISL6140 ISL6150 has essentially zero current on the SENSE pin there is no voltage drop or error associated with the extra resistor R7 is recommended to be small 1000 is a good value The delay time is approximated by the added RC time constant modified by a factor relative to the trip point R C In 1 V t tg Vi V to where V t is the trip voltage nominally 50mV V to is the nominal voltage drop across the sense resistor before the over c
22. Vuv falling VUVL e R5 R6 R6 Since R6 is connected directly to the GATE output it will reduce the available gate current which will reduce the dv dt across the MOSFET and hence the inrush current The value of R6 should be kept as high as possible greater than 500K recommended so that it does not drag down the GATE voltage below the value required to ensure the MOSFET is fully enhanced 16 intersil ISL6140 ISL6150 GND GND 48 IN E 48V OUT FIGURE 30 SAMPLE LAYOUT NOT TO SCALE Figure 30 shows a sample component placement and NOTES routing for the typical application shown in Figure 31 1 Layout scale is approximate routing lines are just for illustration purposes they do not necessarily conform to normal PCB GND GN de p rules High current buses are wider shown with parallel CO ro S x 0 6 inches almost If of the area is just the FET D2PAK or similar SMD 220 package R5 ISL6140 3 R1 sense resistor is size 2512 all other R s and C s shown are 0805 they can all potentially use smaller footprints if desired LOAD 4 The RL and CL are not shown on the layout 5 R4 uses a via to connect to GND on the bottom of the board all other routing can be on top level Its even possible to eliminate the via for an all top level route R6 SENSE Le 6
23. fied at lead free peak reflow temperatures that meet or exceed the lead free requirements of IPC JEDEC J Std 020B 2 Add suffix T to Part Number for Tape and Reel Pinout ISL6140 OR ISL6150 8 LEAD SOIC TOP VIEW PWRGD 18 ov 2 DRAIN uv 31 6 GATE Vee 4 5 SENSE ISL6140 has active Low L version PWRGD output pin ISL6150 has active High H version PWRGD output pin ISL6140 ISL6150 FN9039 2 February 2004 Features Low Side External NFET Switch Operates from 10V to 80V 100V absolute max rating or 10V to 80V 100V absolute max rating Programmable Inrush Current Programmable Electronic Circuit Breaker Over Current shutdown Programmable Overvoltage Protection Programmable Undervoltage Lockout Power Good Control Output PWRGD Active High Version ISL6150 PWRGD active Low L Version ISL6140 Lead Free Available as an Option Applications VoIP Voice over Internet Protocol Servers Telecom systems at 48V Negative Power Supply Control rater st Related Literature SL6140 50EVAL1 Board Set Document AN9967 1516116 Hot Plug Controller Document FN4778 NOTE See www intersil com hotplug for more information Typical Application CL are the Load GND GND R5 ISL6140 R6 SENSE GATE LOAD 48V IN R1 48V OUT R1 0 020 1 R2 100 5 18 5 R4 562
24. ften has a pull up resistor or current Source or equivalent built in care must be taken in the 10 intersil ISL6140 ISL6150 ISL6150 H version output that the given current will create a high enough input voltage remember that current through the RPG 6 2 resistor generates the high voltage level see Figure 9 The input capacitance of the brick is chosen to match its system requirements such as filtering noise and maintaining regulation under varying loads Note that this input capacitance appears as the load capacitance of the ISL6140 ISL6150 The brick s output capacitance is also determined by the system including load regulation considerations However it can affect the ISL6140 ISL6150 depending upon how it is enabled For example if the PWRGD signal is not used to enable the brick the following could occur Sometime during the inrush current time as the main power supply starts charging the brick input capacitors the brick itself will start working and start charging its output capacitors and load that current has to be added to the inrush current In some cases the sum could exceed the Over Current shutdown which would shut down the whole system Therefore whenever practical it is advantageous to use the PWRGD output to keep the brick off at least until the input caps are charged up and then start up the brick to charge its output caps Typical brick regulators include models such as Lucent Ap
25. intersil PRELIMINARY Data Sheet Negative Voltage Hot Plug Controller The ISL6140 is an 8 pin negative voltage hot plug controller that allows a board to be safely inserted and removed from a live backplane Inrush current is limited to a programmable value by controlling the gate voltage of an external N channel pass transistor The pass transistor is turned off if the input voltage is less than the undervoltage threshold or greater than the overvoltage threshold A programmable electronic circuit breaker protects the system against shorts The active low PWRGD signal can be used to directly enable a power module with a low enable input ISL6150 is the same part but with an active high PWRCGD signal Ordering Information TEMP PKG PART NUMBER RANGE PACKAGE DWG ISL6140CB 0 to 70 8Ld SOIC 8 15 ISL6140CBZ 0 to 70 8 Ld SOIC 8 15 Note 1 Lead Free ISL6140lB 40 to 85 8Lead SOIC 8 15 ISL61401BZ 40 to 85 8 ISL6150CB 0 C 8 ISL6150CBZ 0 to 70 8 Ld SOIC M8 15 Note 1 Lead Free ISL61501B 40 to 85 8 Lead SOIC 8 15 ISL6150IBZ 40 to 85 8 Lead SOIC 8 15 Note 1 Lead Free NOTES 1 Intersil Lead Free products employ special lead free material sets molding compounds die attach materials and 100 matte tin plate termination finish which is compatible with both SnPb and lead free soldering operations Intersil Lead Free products are MSL classi
26. itions there will be a voltage drop across the resistor V IR so the higher the resistor value the bigger the voltage drop Also note that the Over Curre uld beset above the inrush lusithe T C otherwise it will m alternatike isto lower the inrush current further One rule of thumb is to set the Over Current 2 3 times higher than the normal current R1 V loc 0 05V loc typical 0 020 CL is the sum of all load capacitances including the load s input capacitance itself Its value is usually determined by the needs of the load circuitry and not the hot plug although there can be interaction For example if the load is a regulator then the capacitance may be chosen based on the input requirements of that circuit holding regulation under current spikes or loading filtering noise etc The value chosen will then affect how the inrush current is controlled Note that in the case of a regulator there may be capacitors on the output of that circuit as well these need to be added into the capacitance calculation during inrush unless the regulator is delayed from operation by the PWRGD signal for example RL is the equivalent resistive value of the load it determines the normal operation current delivered through the FET It also affects some dynamic conditions such as the discharge time of the load capacitors during a power down A typical value might be 48Q I V R 48 48 1A R2 C1
27. plications Layout Considerations For the minimum application there are only 6 resistors 2 capacitors one IC and one FET A sample layout is shown in Figure 30 It assumes the IC is 8 SOIC the FET is ina D2PAK or similar SMD 220 package Although GND planes are common with multi level PCBs for a 48V system the 48V rails both input and output act more like a GND than the top OV rail mainly because the IC signals are mostly referenced to the lower rail So if separate planes for each voltage are not an option consider prioritizing the bottom rails first Note that with the placement shown most of the signal lines are short and there should not be much interaction between them Although decoupling capacitors across the IC supply pins are often recommended in general this application may not need one nor even tolerate one For one thing a decoupling cap would add to or be swamped out by any other input capacitance it also needs to be charged up when power is applied But more importantly there are no high speed or any input signals to the IC that need to be conditioned If still desired consider the isolation resistor R10 as shown in Figure 29 JW050A1 E or Vicor VI J30 CY T inal 4 5 NAAT is M tife input C nt e r S and output 11 intersil ISL6140 ISL6150 Typical Performance Curves
28. reversed as follows If the voltage drop across the FET is too large gt 1 7V the open drain pull down device will turn on and sink current to the DRAIN pin If the voltage drop is small 1 7V a 2nd pull down device in series with a 6 2K resistor nominal sinks current to VEE if the external pull up current is low enough lt 1 for example the voltage drop across the resistor will be big enough to look like a logic high signal in this example 1mA 6 2kO 6 2V This pin can thus used as an ANM T al Lt Note that for both VerSi nsS altriougiT this 1s a digital functionally the logic high level is determined by the external pull up device and the power supply to which it is connected the IC will not clamp it below the VDD voltage Therefore if the external device does not have its own clamp or if it would be damaged by a high voltage then an external clamp might be necessary OV Over Voltage Pin 2 This analog input compares the voltage on the pin to an internal voltage reference nominal 1 223V When the input goes above the reference low to high transition that signifies an OV Over Voltage condition and the GATE pin is immediately pulled low to shut off the external FET Since there is 20mV of nominal hysteresis built in the GATE will remain off until the OV pin drops below a 1 203V nominal high to low threshold A typical application will use an external resistor divider from VDD to VE
29. rily One possible solution is to add a filter cap C4 to the VDD pin through isolation resistor R10 A large value of R10 is better for the filtering but be aware of the voltage drop across it For example a 1kQ resistor with 1mA of IDD would have 1V across it and dissipate 1mW Since the UV and OV comparators are referenced with respect to the VEE supply they should not be affected But the GATE clamp voltage could be offset by the voltage across the extra resistor If there are negative transients on the DRAIN pin blocking diodes may help limit the amount of current injected into the IC substrate General purpose diodes such as 1N4148 may be used Note that the 1516140 L version requires one diode while the 1516150 H version requires two diodes One consequence of the added diodes it that the Vp voltage is offset by each diode drop The switch SW1 is shown as a simple pushbutton It can be replaced by an active switch such as an NPN or the principle is the same pull the UV node below its trip point and then release it toggle low To connect an NFET for example the drain goes to UV the source to VEE and the gate is the input if it goes high relative to VEE it turns the NFET on and UV is pulled low Just make sure the NFET resistance is low compared to the resistor divider so that it has no problem pulling down against it R8 is a pull up resistor for PWRGD if there is no other component acting as a pull
30. ther boards as well as possibly cause some permanent damage to the power supply The key to allowing boards to be inserted into a live backplane then is to turn on the power to the board in a controlled manner usually by limiting the current allowed to flow through a FET switch until the input capacitors are fully charged At that point the FET is fully on for the smallest voltage drop across it In addition to controlling the inrush current the ISL6140 also protects the board against over current over voltage under voltage and can signal when the output voltage is within its expected range PWRGD Note that although this IC was designed for 48V systems it can also be used as a low side switch for positive 48V systems the operation and components are usually similar One possible difference is the kind of level shifting that may be needed to interface logic signals to the UV input to reset the latch or PWRGD output For example many of the IC functions are referenced to the IC substrate connected to the VEE pin But this pin may be considered 48V or GND depending upon the polarity of the system And input or output logic running at 5V or 3 3V or even lower might be externally referenced to either VDD or VEE of the IC instead of GND 7 intersil ISL6140 ISL6150 Applications Over Current CORRECT INCORRECT TO SENSE AND CURRENT SENSE RESISTOR FIGURE 5 SENSE RESIS
31. to Low Transition 1 165 1 203 1 232 OV Pin Hysteresis VovHY 7 20 50 mV OV Pin Input Current Vov VEE 0 05 0 5 uA 3 intersil ISL6140 ISL6150 Electrical Specifications Commercial 0 C to 70 or Industrial 40 C to 85 C Typical specs are at 25 C Continued VDD 48V 0V Unless Otherwise Specified All tests are over the full temperature range either TEST PART NUMBER LEVEL OR GRADE TEST OR PARAMETER SYMBOL CONDITIONS NOTES MIN MAX UNITS DRAIN PIN Power Good Threshold L to H VPGLH VDRAIN Low to High 1 55 1 70 1 87 V Transition Power Good Threshold H to L VPGHL VDRAIN VEE High to Low 1 10 1 25 1 42 V Transition Power Good Threshold Hysteresis VPGHY 0 30 0 45 0 60 V Drain Input Bias Current DRAIN VDRAIN 48V 10 35 60 1516140 PWRGD L VERSION PWRGD Output Low Voltage VoL VEE lt VPG 0 28 0 50 V lout 1mA lout 3mA 0 88 1 20 lout 5mA 145 1 95 V Output Leakage VDRAIN 48V VPWRGD 80V 0 05 10 uA ISL6150 PWRGD PIN H VERSION PWRGD Output Low Voltage PWRGD DRAIN VoL VpRAIN 5V lout 1mA 0 80 1 0 V PWRGD Output Impedance Rour VpRAIN VEE lt VPG 3 5 6 2 9 0 AC TIMING BD C eae ED LL C OV Low to High tP
32. urrent condition V is the voltage drop across the sense resistor while the over current is applied For example a system has a normal 1A current load and a 20mQ sense resistor for a 2 5A over current It needs to filter out a 50us current pulse at 5A So V t 50mV from spec V tg 20mV V IR 1A 20mQ Vi 100mV V IR 5A 20mo If R7 1000 then is around 1pF in es C Note that the FET must be rated to handle the higher current for the longer time since the IC is not doing current limiting the RC is just delaying the over current shutdown Applications OV and UV The UV and OV input pins are high impedance so the value of the external resistor divider is not critical with respect to input current Therefore the next consideration is total current the resistors will always draw current equal to the supply voltage divided by the total of R4 R5 R6 so the values should be chosen high enough to get an acceptable current However to the extent that the noise on the power supply can be transmitted to the pins the resistor values might be chosen to be lower A filter capacitor from UV to VEE or OV to UV is a possibility if certain transients need to be filtered Note that even some transients which will momentarily shut off the gate might recover fast enough such that the gate or the output current does not even see the interruption Finally take into account whether the resistor values are readily a
33. vailable or need to be custom ordered Tolerances of 1 are recommended for accuracy Note that for a typical 48V system with a 36V to 72V range the 36V or 72V is being divided down to 1 223V a significant scaling factor For UV the ratio is roughly 30 times every 3mV change on the UV pin represents roughly 0 1V change of power supply voltagg Gonversely an error of 3mV dup to the resistors e 6 V the supply trip i hel OViraft li 6 he amp ccuracy of the resistors comes into play The hysteresis of the comparators 20mV nominal is also multiplied by the scale factor of 30 for the UV pin 30 20mV 0 6V of hysteresis at the power supply and 60 for the OV pin 60 20mV 1 2V of hysteresis at the power supply With the three resistors the UV equation is based on the simple resistor divider 1 223 Vuy R5 R6 R4 R5 R6 or Vuy 1 223 R4 R5 R6 R5 R6 Similarly for OV 1 223 Voy R6 R4 R5 R6 or Voy 1 223 R4 R5 R6 R6 Note that there are two equations but 3 unknowns Because of the scale factor R4 has to be much bigger than the other two chose its value first to set the current for example 50V 500kQ draws 10044 and then the other two will be in the 10kO range Solve the two equations for two unknowns Note that some iteration may be necessary to select values that meet the requirement and are also readily available standard values 8 intersil ISL6140 I
34. value depends on VDD voltage see Figure 13 VGATE vs VDD 20V 5 PWRGD is referenced to DRAIN VewRGD VDpRAIN OV Electrical Specifications VDD 48V VEE 0V Unless Otherwise Specified All tests are over the full temperature range either Commercial 0 C to 70 or Industrial 40 C to 85 C Typical specs are at 25 TEST PART NUMBER LEVEL OR GRADE TEST OR PARAMETER SYMBOL CONDITIONS NOTES MIN MAX UNITS DC PARAMETRIC Supply Operating Range D 10 e 80 V o VIN C Gonddaat er sit DD GATE PIN Gate Pin Pull Up Current Ipu Gate Drive on VGATE VEE 30 45 60 Gate Pin Pull Down Current lpp Gate Drive off any fault condition 24 32 70 mA External Gate Drive delta 17V lt Vpp lt 80V 10 14 15 V VGATE Wene Vee 10V lt Vpp lt 17V 4 54 62 45 V SENSE PIN Circuit Breaker Trip Voltage VcB Vcg VsEeNsE VEE 40 50 60 mV SENSE Pin Current Isense VSENSE 50mV 0 0 5 UV PIN UV Pin High Threshold Voltage VUVH UV Low to High Transition 1 213 1 243 1 272 UV Pin Low Threshold Voltage UV High to Low Transition 1 198 1 223 1 247 UV Pin Hysteresis VUVHY 7 20 50 mV UV Pin Input Current liNUV Vuv VEE x 0 05 0 5 uA OV PIN OV Pin High Threshold Voltage VovH OV Low to High Transition 1 198 1 223 1 247 OV Pin Low Threshold Voltage VovL OV High
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intersil ISL6140/ISL6150 handbook