intersil 80C286/883 Manual
Contents
1. These signals may not be driven by the 80C286 883 during the time shown The worst case in terms of latest float time is shown FIGURE 5 EXITING AND ENTERING HOLD 138 80C286 883 Waveforms Continued BUS CYCLE TYPE ot TS 92 OSG 2 o1 Ts 42 p Te 92 pgo M 1 0 READ IF PROC EXT TO MEMORY MEMORY WRITE IF PROC EXT TO MEMORY MEMORY READ IF MEMORY TO PROC EXT ji 1 0 WRITE IF MEMORY TO PROC EXT MEMORY ADDRESS IF PROC EXT TO MEMORY TRANSFER I O PORT ADDRESS 00FA H IF MEMORY TO PROC EXT TRANSFER l 1 0 PORT ADDRESS OOFA H IF PROC EXT TO MEMORY TRANSFER MEMORY ADDRESS IF MEMORY TO PROC EXT TRANSFER SEE NOTE 1 SEE NOTE 2 gt lt 6 PEREA O I n NOTES 1 PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence The first bus operation will be either a memory read at operand address or I O read at port address OOFA H To prevent a second processor extension data operand transfer the worst case maximum time shown above is 3 x Q 12Ayax 4 Min The actual configuration dependent maximum time is 3 x T 12Ayax min N x 2 x N is the number of extra Tc states added to either the first or second bus operation of the processor extension data operand transfer sequence FIGURE 6 80C286 883 PEREQ PEACK TIMING FOR ONE TRANSFER ONLY BUS CYCLE TYPE AT LEAST 16 CLK PERIODS gt lt gt 43 UNKNOWN E UNKNO2. on the board ERROR D15 HOLD COD INTA LOCK OO O OOOO PIN 1 INDICATOR n no gt P C BOARD VIEW As viewed from the component side of the P C board ERROR D15 HOLD COD INTA LOCK OOOOOOOOOO O OOOOOO O PIN 1 INDICATOR 129 80C0286 883 Absolute Maximum Ratings Thermal Information Supply Voltage Input Output or I O Voltage Applied Storage Temperature Range Junction Temperature Lead Temperature Soldering 10s ESD Classification CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Oja is measured with the component mounted on an evaluation PC board in free air Thermal Resistance Typical PGA Package Gate Count Oja 8Jc 35 C W 6 C W 22 500 Gates GND 1 0V to Vcc 1 0V 65 C to 150 C Class 1 Operating Conditions Operating Voltage Range 4 5V to 5 5V Operating Temperature Range 55 C to 125 C System Clock CLK RISE Time From 1 0V to 3 6V 8ns Max System Clock CLK FALL Time from 3 6V to 1 0V 8ns Max Input RISE and FALL Time From 0 8V to 2 0V 80C286 10 883 80C286 12 883 TABLE 1 80C286 883 D C ELECTRICAL PERFORMANCE SPECIFICATIONS GROUP A Device Guaranteed and 100 Tested LIMITS SUB PARAME
3. TER SYMBOL CONDITIONS GROUPS TEMPERATURE own max UNITS CLK Input LOW Voltage Veo 4 5V 55 C lt T4 lt 1 Output LOW Voltage Output HIGH Voltage Input Leakage Current CLK Input HIGH Voltage Vo Vo Input Sustaining Current IBHL LOW Input Sustaining Current IBHH HIGH Input Sustaining Current on BUSY and ERROR Pins Active Power Supply locop Current Standby Power locsB Supply Current NOTES 2 IBHH Should be measured after raisi Output Leakage Current Voc 55V ene ois AOA Vee ABN SCE TSE 08S LV lon 20mA Voc 45V sostas so v lou 1 OO0nA Vec 4 5V Vin GND or Voc Vec 5 5V Pins 29 31 57 59 61 63 64 Vec 4 5V and 5 5V Vin 1 0V Note 1 Voc 4 5V and 5 5V Vin 3 0V Note 2 Voc 4 5V and 5 5V Vin GND Note 5 Vo GND or Voc Vec 5 5V Pins 1 7 8 10 28 32 34 80C286 10 883 Note 4 80C286 12 883 Note 4 Voc 5 5V Note 3 55 C lt Ty lt 12 2 3 2 3 2 3 2 3 2 3 2 3 2 3 1 1 Ig Should be measured after lowering Vy to GND and then raising to 1 0V on the following pins 36 51 66 67 ng Vix to Vcc and then lowering to 3 0V on the following pins 4 6 36 51 66 68 I cgp should be tested with the clock stopped in phase two of the processor clock cycle Viy Vec or GND Vec 5 5V outputs unloaded lecop Measured at 10MHz for the 80C286 10 883 and 12 5MHz for the 80C286 1 2 883 Viy 2 4V or 0 4V Voc 5 5V outputs un
4. WN lt SEE NOTE 3 DATA mess _ HILDA UNKNOWN S NOTES 1 Setup time for RESET may be violated with the consideration that 1 of the processor clock may begin one system CLK period later 2 Setup and hold times for RESET J must be met for proper operation but RESET 4 may occur during 61 or 02 3 The data bus is only guaranteed to be in a high impedance state at the time shown FIGURE 7 INITIAL 80C286 883 PIN STATE DURING RESET BUS HOLD BUS HOLD ACKNOWLEDGE WRITE CYCLE ACKNOWLEDGE gt e BUS CYCLE TYPE j CLK GEE NOTE R 80C286 883 Die Characteristics DIE DIMENSIONS GLASSIVATION 286 x 283 x 19 1mils Type Nitrox METALLIZATION Thickness 10kA Type Si Al WORST CASE CURRENT DENSITY 2 X 10 A cm Thickness 8kA LEAD TEMPERATURE 10s Soldering lt 300 C Metallization Mask Layout 80C286 883 All Intersil U S products are manufactured assembled and tested utilizing ISO9000 quality systems Intersil Corporation s quality certifications can be viewed at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time withoui otice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and eliable However no responsibility is assumed by Intersil
5. imtersil 800286 883 High Performance Microprocessor with Memory March 1997 Features This Circuit is Processed in Accordance to MIL STD 883 and is Fully Conformant Under the Provisions of Paragraph 1 2 1 Compatible with NMOS 80286 883 Static CMOS Design for Low Power Operation ICCSB 5mA Maximum ICCOP 185mA Maximum 80C286 10 883 ICCOP 220mA Maximum 80C286 12 883 Large Address Space 16 Megabytes Physical 1 Gigabyte Virtual per Task Integrated Memory Management Four Level Memory Protection and Support for Virtual Memory and Operating Systems Two 80C86 Upward Compatible Operating Modes 80C286 883 Real Address Mode Protected Virtual Address Mode Compatible with 80287 Numeric Data Co Processor Ordering Information 68 Pin PGA Management and Protection Description The Intersil 80C286 883 is a static CMOS version of the NMOS 80286 microprocessor The 80C286 883 is an advanced high performance microprocessor with specially optimized capabilities for multiple user and multi tasking sys tems The 80C286 883 has built in memory protection that supports operating system and task isolation as well as pro gram and data privacy within tasks The 80C286 883 includes memory management capabilities that map 230 one gigabyte of virtual address space per task into 224 bytes 16 megabytes of physical memory The 80C286 883 is upwardly compatible with 80C86 and 80C88 software the 80C286 883
6. instruction set is a super set of the 80C86 80C88 instruction set Using the 80C286 883 real address mode the 80C 286 883 is object code com patible with existing 80C86 and 80C88 software In pro tected virtual address mode the 80C286 883 is source code compatible with 80C86 and 80C88 software but may require upgrading to use virtual address as supported by the 800 286 883 s integrated memory management and protec tion mechanism Both modes operate at full 80C286 883 performance and execute a superset of the 80C86 and 80C88 instructions The 80C286 883 provides special operations to support the efficient implementation and execution of operating systems For example one instruction can end execution of one task save its state switch to a new task load its state and start execution of the new task The segment not present excep tion and restartable instructions 0 C to 70 C CGB0C286 12 CG80C286 16 CG80C286 20 asss 40 C to 85 C G80C286 10 IG80C286 12 O 55 C to 125 C MG80C286 10 883 MG80C286 12 883 ee ee S G68 B CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 321 724 7143 Intersil and design is a trademark of Intersil Americas Inc 128 Copyright Intersil Americas Inc 2002 All Rights Reserved FN2948 1 80C0286 883 Pinout 68 LEAD PGA COMPONENT PAD VIEW As viewed from underside of the component when mounted
7. ints of the Signals as Illustrated in Datasheet Waveforms Unless Otherwise Noted Device Guaranteed and 100 Tested 80C286 883 12 5MHz GROUP A PARAMETER SYMBOL CONDITIONS SUBGROUPS TEMPERATURE 5 HLDA Valid Delay 1 Voc 4 5V and 55 C lt T4 lt 125 C Note 5 5 5V C 100pF IL 2mA NOTES 1 Asynchronous inputs are INTR NMI HOLD PEREQ ERROR and BUSY This specification is given only for testing purposes to assure recognition at a specific CLK edge Delay from 1 0V on the CLK to 0 8V or 2 0V Delay from 1 0V on the CLK to 0 8V for Min HOLD time and to 2 0V for Max inactive delay Delay from 1 0V on the CLK to 2 0V for Min HOLD time and to 0 8V for Max active delay Delay from 1 0V on the CLK to 2 0V TABLE 3 80C286 883 ELECTRICAL PERFORMANCE SPECIFICATIONS 80C286 883 PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX CLK Input Capacitance FREQ 1MHz Ta 25 C Bae Other Input Capacitance FREQ 1MH E I O Capacitance FREQ 1MH 5 5 Output Load C 100pF Delay measured from address either reaching 0 8V or 2 0V valid to status going active reaching 0 8V or status going inactive reaching 2 0V Delay from 1 0V on the CLK to Float no current drive condition 4 IL 6MA Voy to Float IL 8MA Vo to Float The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested These parameters are char acterized u
8. loaded Igy should be measured after raisin g Vin to Vcc and then lowering to OV on pins 53 and 54 130 80C0286 883 TABLE 2 80C286 883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS AC Timings are Referenced to 0 8V and 2 0V Points of the Signals as Illustrated in Datasheet Waveforms Unless Otherwise Noted Device Guaranteed and 100 Tested PARAMETER System Clock 1 CLK Period System Clock 2 CLK Low Time System Clock CLK High Time Asynchronous Inputs SETUP Time Note 1 Asynchronous Inputs HOLD Time Note 1 Read Data HOLD Time READY SETUP Time Status PEACK Active Delay Note 4 Status PEACK Inactive Delay Note 3 Address Valid Delay Note 2 Write Data Valid Delay Note 2 Voc 4 5V and 5 5V Voc 4 5V and5 5V Voc 4 5V and5 5V and 5 5V Voc 4 5V and 5 5V Voc 4 5V and 5 5V C 100pF I 2mA Voc 4 5V and 5 5V C 100pF GROUP A SUBGROUPS 9 10 1 9 10 11 10 10 4 i 131 10 TEMPERATURE 55 C lt T4 lt 125 C oa 55 C lt T lt 125 C 55 C lt T4 lt 125 C ak DS ye a r NO fo D N fo 55 C lt T4 lt 125 C 55 C lt T4 lt 125 C 55 C lt T4 lt 125 C 55 C lt Ty lt 125 C 4 2 80C286 883 80C286 883 TABLE 2 80C286 883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Continued AC Timings are Referenced to 0 8V and 2 0V Po
9. nce only and no guarantee is inplied FIGURE 2 MAJOR CYCLE TIMING 80C286 883 Waveforms Continued BUS CYCLE TYPE Vou CLK lt gt PCLK SEE NOTE 1 6 INTR NMI i A x RE TX TX l ERROR BUSY SEE NOTE 2 NOTES 1 PCLK indicates which processor cycle phase will occur on the next CLK PCLK may not indicate the correct phase until the first cycle is performed NOTE These inputs are asynchronous The setup and hold times shown 1 When RESET meets the setup time shown the next CLK will assure recognition for testing purposes start or repeat 1 of a processor cycle FIGURE 3 80C286 883 ASYNCHRONOUS INPUT SIGNAL FIGURE 4 80C286 883 RESET INPUT TIMING AND SUBSE TIMING QUENT PROCESSOR CYCLE PHASE 137 80C0286 883 Waveforms Continued BUS CYCLE TYPE SEE NOTE 4 NOTE 3 SEE NOTE 3 Ae RESNE SEE NOTE 1 VALID m SEE NOTE 2 SEE NOTE 6 VALID IF WRITE af N Aa Ai 80C286 883 IF NPX TRANSFER NOTES 1 The data bus will be driven as shown if the last cycle before T in the diagram was a write Tc The 80C286 883 puts its status pins in a high impedance logic one state during Ty For HOLD request set up to HLDA refer to Figure 8 BHE and LOCK are driven at this time but will not become valid until Ts The data bus will remain in a high impedance state if a read cycle is performed
10. or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may resul from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com Spec Number 140
11. pon initial design and after major process and or design changes TABLE 4 APPLICABLE SUBGROUPS A CC 132 80C286 883 AC Electrical Specifications 820284 and 82C288 Timing Specifications Are Given For Reference Only And No Guarantee is Implied 82C284 Timing SYMBOL PARAMETER TEST CONDITION TIMING REQUIREMENTS a a E a E S a a a E a a E a TIMING RESPONSES 19 PCLK Delay 20 16 ns C 75pF Io 5mA loH 1mA NOTE 1 These times are given for testing purposes to ensure a predetermined action 82C288 Timing 10MHz 12 5MHz SYMBOL PARAMETER MN max MN max UNIT TEST CONDITION TIMING REQUIREMENTS TIMING RESPONSES MEE E S GG Ce frero e freee 133 80C286 883 lt tpoeLay MAX gt MIN gt i AC testing input rise and fall times are driven at 1ns per volt 80C286 883 80C0286 883 Waveforms READ CYCLE WRITE CYCLE READ ILLUSTRATED WITH ZERO ILLUSTRATED WITH ONE T OR Ts WAIT STATES WAIT STATE Ts Te Ts Te D 2 2 o1 2 o1 2 gt _ 43 lt _ a3 ac A OD OC OOK COD INTA 4 gt BHE Lock OO OOOO U NALD CONT C vap con C 80C286 883 od VALID WRITE DATA a SRDY N B SRDYEN 82C284 SEE NOTE 2 82C288 SEE NOTE 2 NOTES 1 The modified timing is due to the CMDLY signal being active 2 820254 and 82C288 Timing Waveforms are shown for refere
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intersil 80C286/883 Manual