intersil X9521 Manual
Contents
1. a 7 Rp2 WIPER 4 R COUNTER 8 DATA gt REGISTER w2 REGISTER SDA Rie COMMAND Rs NONVOLATILE DECODE amp gt MEMORY SCL CONTROL LOGIC THRESHOLD RESET LOGIC CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures prop 1 888 INTERSIL or 1 888 468 3774 Intersil and design is a registered trademark of Intersil Americas Inc 2000 Intersil Inc Patents Pending Copyright Intersil Americas Inc 2006 All Rights Reserved All other trademarks mentioned are the property of their respective owners X9521 Ordering Information PRESET FACTORY SHIPPED VIRIPx PART NUMBER PART MARKING THRESHOLD LEVELS x 2 3 TEMP RANGE C PACKAGE X9521V201 A X9521VIA Optimized for 3 3V system monitoring 40 to 85 20 Ld TSSOP X9521V20I B X9521VIB Optimized for 5V system monitoring 40 to 85 20 Ld TSSOP X9521V20IZ A Note X9521VZIA Optimized for 3 3V system monitoring 40 to 85 20 Ld TSSOP Pb free X9521V20IZ B Note X9521VZIB Optimized for 5V system monitoring 40 to 85 20 Ld TSSOP Pb free NOTE Intersil Pb free plus anneal products employ special Pb free material sets molding compounds die attach materials and 10096 matte tin plate termination finish which are RoHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow t2. The factory default setting for these bits are BL1 0 BLO 0 IMPORTANT NOTE If the Write Protect WP pin of the X9521 is active HIGH then all nonvolatile write opera tions to both the EEPROM memory and DCPs are inhib ited irrespective of the Block Lock bit settings See WP Write Protection Pin CONSTAT Register Write Operation The CONSTAT register is accessed using the Slave Address set to 1010010 Refer to Figure 4 Following the Slave Address Byte access to the CONSTAT regis ter requires an Address Byte which must be set to FFh Only one data byte is allowed to be written for each CONSTAT register Write operation The user must issue a STOP after sending this byte to the register to initiate the nonvolatile cycle that stores the BP1and BPO bits The X9521 will not ACKNOWLEDGE any data bytes written after the first byte is entered Refer to Figure 18 When writing to the CONSTAT register the bits CS7 CS5 and CSO must all be set to 0 Writing any other bit sequence to bits CS7 CS5 and CSO of the CONSTAT register is reserved Prior to writing to the CONSTAT register the WEL and RWEL bits must be set using a two step process with sequence requiring 3 steps er to set the Write aR he Sipo Lach WED This volatile operation so there is no delay after the write Operation preceded by a START and ended with a STOP Write a 06H to the CONSTAT Register to set the Reg ister Wr
3. S AWT 00 O0 2M R SLAVE ADDRESS BYTE Figure 9 b INSTRUCTION BYTE A C K M 7 K voo v DATA BYTE DCP Write Command Sequence 7 intersil FN8207 1 January 3 2006 X9521 S E 2 lt n lt 16 S Signals from t the Master t Slave Address Data Data o Address Byte 1 n p 4 DIS a Y A EA RAE N19 100000 ll A A J A A Signals from C C C C the Slave K K K K Figure 10 EEPROM Page Write Operation PO 0 or P1 1 PO 1 are reserved sequences and will result in no ACKNOWLEDGE after sending an Instruction Byte on SDA The factory default setting of all wiper position settings is with OOh stored in the NVM of the DCPs This corre sponds to having the wiper teminal Ry x x 1 2 at the lowes tap position Therefore the resistance between Rwx and Rj x is a minimum essentially only the Wiper Resistance Rw DCP Read Operation an Instruction Byte is issued on SDA Bits P1 PO of the Instruction Byte determine which DCP wiper position is to be read In this case the state of the WT bit is don t care If the Instruction Byte format is valid then another ACKNOWLEDGE is returned by the X9521 Following this ACKNOWLEDGE the master immediately issues another START condition and a valid Slave address byte with the R W bit set to 1 Then the X9521 issues an
4. Fiber Channel Gigabit Ethernet Laser Diode Control for Fiber Optic Modules FEATURES Two Digitally Controlled Potentiometers DCP s 100 Tap 10kQ 256 Tap 100kQ Non Volatile Write Protect Function 2kbit EEPROM Memory with Write Protect amp Block Lock 2 Wire industry standard Serial Interface Complies to the Gigabit Interface Converter GBIC specification Single Supply Operation 2 7V to 5 5V Hot Pluggable 20 Ld TSSOP BLOCK DIAGRAM ww BDTI C comln X9521 Dual DCP EEPROM Memory FN8207 1 January 3 2006 DESCRIPTION The X9521 combines two Digitally Controlled Potentiom eters DCP s and integrated EEPROM with Block Lock protection All functions of the X9521 are accessed by an industry standard 2 Wire serial interface The DCP s of the X9521 may be utilized to control the bias and modulation currents of the laser diode in a Fiber Optic module The 2kbit integrated EEPROM may be used to store module definition data The features of the X9521 are ideally suited to simplifying the design of fiber optic modules which comply to the Gi gabit Interface Converter GBIC specification The inte gration of these functions into one package significantly reduces board area cost and increases reliability of laser diode modules WIPER 8 WP PROTECT LOGIC COUNTER REGISTER Filo i EE
5. AT 252 6 4 BSC 252 6 4 l 260 6 6 i Y j y 07 1 20 0075 19 a La 002 05 0118 30 006 15 Wi MACC an uL nter si i 4 Seating Plane Lo 9 50 lE 78 k ATA 2 000 NM 029 75 42 Detail A 20X n y pang 031 80 A 041 1 05 A See Detail A t 0 65 ALL MEASUREMENTS ARE TYPICAL NOTE ALL DIMENSIONS IN INCHES IN PARENTHESES IN MILLIMETERS All Intersil U S products are manufactured assembled and tested utilizing ISO9000 quality systems Intersil Corporation s quality certifications can be viewed at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products
6. feci 400kHz eed Read memory array 3 rra mA PME Write nonvolatile memory Current into Vcc Pin Vspa Vcc RO X9521 Standby A WP Vss or Open Floating o coe With 2 Wire bus activity 3 50 j VscL Vcc when no bus activity No 2 Wire bus activity 50 else fac 400kHz i Input Leakage Current SCL SDA 0 1 10 pA Vix 4 2 GND to Vec LI Input Leakage Current WP 10 uA Vin Vss to Vcc with all other lai Analog Input Leakage 1 10 yA analog pins floating 5 _ ILO Output Leakage Current SDA 0 1 10 uA Vout anne vec X9521 is in Standby vi Input LOW Voltage SCL SDA WP 0 5 0 8 V vy 9 Input HIGH Voltage SCL SDA WP 2 0 Vee V VOLx SDA Output Low Voltage 0 4 V Isink 2 0mA Notes 1 The device enters the Active state after any START and remains active until 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect 200nS after a STOP ending a read operation or twc after a STOP ending a write operation Notes 2 The device goes into Standby 200nS after any STOP except those Bd initiate a high voltage write cycle tyc after a STOP that initiates by At er e Bits in the Slave Address a hig Byte Notes 3 Current thr Notes 4 ViN Voltage applied to input pin Notes 5 Vout Voltage applied to output pin Notes 6 Vi Min and VjH Max are for reference only and are not tested TIC CCO included 18 intersil FN8207 1 January 3 2006 X9521 A C CH
7. 0V Notes 2 Cb total capacitance of one bus line in pF Notes 3 Over recommended operating conditions unless otherwise specified Notes 4 twc is the time from a valid STOP condition at the end of a write sequence to the end of the self timed internal nonvolatile write cycle It is the minimum cycle time to be allowed for any nonvolatile write by the user unless Acknowledge Polling is used Notes 5 This parameter is not 100 tested 19 intersil FN8207 1 anuary 3 2006 X9521 POTENTIOMETER CHARACTERISTICS Limits Symbol Parameter Min Typ Max Units Test Conditions Notes RTOL End to End Resistance Tolerance 20 20 VRHx Ry Terminal Voltage x 1 2 Vss Voc V VRLx RL Terminal Voltage x 1 2 Vss Vcc V P 1 10 mW RTOTAL 10kQ DCP1 R i poner PAU 5 mW RTOTAL 100kQ DCP2 lw 1mA Vcc 5 V 200 400 Q VRHx Vcc Vni x Vss x 1 2 Rw DCP Wiper Resistance lw 1mA Vcc 2 7 V 400 1200 Q VRHx Vcc Vni x Vss x 1 2 lw Wiper Current 6 4 4 mA mV l sqt Hz RTOTAL 10kO DCP1 Noise V m sqt Hz RTOTAL 100kQ DCP2 Absolute Linearity 2 1 1 MI 4 Rw n actual Pw n expected Relative Linearity 9 1 1 MIO Rw n 1 Rw n MIl a 300 ppm C RrotaL 10kQ DCP1 RTOTAL Temperat f v C C E 4 te P i 1 0kQ DCP2 CwC Cw AALA TATT B 0 eim twer Wiper Response time 6 200 us See Figure 2
8. Read or Sequen tial EEPROM Read is once again available assuming that no access to a DCP or CONSTAT Register occur in the interim 10 intersil FN8207 1 January 3 2006 X9521 S WRITE Operation S READ Operation t t Signals from a Slave Address a Slave t the Master y Address Byte r Address sd t Pu t D f N SDA Bus N N ot o o o o A A A Signals from C s the Slave g i pata Dummy Write Figure 15 Random EEPROM Address Read Sequence Random EEPROM Read Random read operation allows the master to access any memory location in the array Prior to issuing the Slave Address Byte with the RW bit set to one the master must first perform a dummy write operation The master issues the START condition and the Slave Address Byte receives an ACKNOWLEDGE then issues an Address Byte This dummy Write operation sets the address pointer to the address from which to begin the random PLE I Hanemitiod as WiN ihe pier modas oweven EEPROM read operation the master now responds with an ACKNOWLEDGE indicating it requires additional data Fhe X9521 contin After the 9521 AAMAS ie DIRS ues C oi Pap Q a icknom Enee Byte the mast ally Lede another T ceeds Th te inat s ithe kead operation by condition and the Slave Address Byte with the R W bit not responding with an ACKNOWLEDGE and
9. al Ry is recalled to the correct position as per the last stored in the DCP NVM when the voltage applied to Vcc exceeds VTRip for a time exceeding tpu Therefore if ttrang is defined as the time taken for Vcc to settle above VTRIp Figure 7 then the desired wiper ter minal position is recalled by a maximum time trans tpu It should be noted that trang is determined by sys tem hot plug conditions DCP Operations In total there are three operations that can be performed on any internal DCP structure DCP Nonvolatile Write DCP Volatile Write DCP Read A nonvolatile write to a DCP will change the wiper position by simultaneously writing new data to the associated WCR and NVM Therefore the new wiper position setting is recalled into the WCR after Vcc of the X9521 is powered down and then powered back up A volatile write operation to a DCP however changes the wiper position by writing new data to the associated WCR only The contents of the associated NVM register remains unchanged Therefore when Vcc to the device is powered down then back up the wiper position reverts to that last position written to the DCP using a nonvolatile write operation Both volatile and nonvolatile write operations are executed using a three byte command sequence DCP Slave Address Byte Instruction Byte followed by a Data Byte See Figure 9 A DCP Read operation allows the user to read out
10. previous data one byte at a time See Figure 13 The master terminates the Data Byte loading by issuing a STOP condition which causes the X9521 to begin the nonvolatile write cycle As with the byte write operation all inputs are disabled until completion of the internal write cycle See Figure 10 for the address ACKNOWL EDGE and data transfer sequence Stops and EEPROM Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and receiving the subsequent ACKNOWLEDGE signal If the master issues a STOP within a Data Byte or before the X9521 issues a corresponding ACKNOWLEDGE the X9521 cancels the write operation Therefore the contents of the EEPROM array does not change 9 intersil FN8207 1 January 3 2006 address h 764 ans 4 1549 onn 11o address pointer ends here Addr 749 Figure 13 Example Writing 12 bytes to a 16 byte page starting at location 11 S Signals from t S theMaster 4 a Slave t r Address o SDA Bus Nro O 0001 Signals from A Y the Slave K Data Figure 14 Current EEPROM Address Read Sequence eon MWALBDTI C cond nt ers Read operations are initiated in the same manner as write operations with the exception that the R W bit of the Slave Address Byte is set to one There are three basic read operations Current EEPROM Address Read Ran d
11. the X9521 initiates an internal high voltage write cycle This cycle typically requires 5 ms During this time no further Read or Write commands can be issued to the device Write Acknowledge Polling is used to determine when this high voltage write cycle has been completed To perform acknowledge polling the master issues a START condition followed by a Slave Address Byte The Slave Address issued must contain a valid Internal Device Address The LSB of the Slave Address R W can be set to either 1 or O in this case If the device is still busy with the high voltage cycle then no ACKNOWL EDGE will be returned If the device has completed the write operation an ACKNOWLEDGE will be returned and the host can then proceed with a read or write opera tion Refer to Figure 5 Byte load completed by issuing STOP Enter ACK Polling Issue START Issue Slave Address Byte Read or Write ACK returned YES Issue STOP igh Voltage Cycle NO complete Continue command sequence Issue STOP Continue normal Read or Write command sequence PROCEED Figure 5 Acknowledge Polling Sequence BDTI C cope WIPER COUNTER REGISTER WCR WIPER RESISTOR FET ARRAY SWITCHES DECODER NON VOLATILE MEMORY NVM Figure 6 DCP Internal Structure DIGITALLY CONTROLLED POTENTIOMETERS DCP Functionality The X9521 includes two independent resisto
12. 5 VTRIP Vcc power up DCP recall threshold V tPU Vcc power up DCP recall delay time 6 25 50 75 ms Notes 1 Power Rating between the wiper terminal Rwx n and the end terminals Ryx or Rix for ANY tap position n x 1 2 Notes 2 Absolute Linearity is utilized to determine actual wiper resistance versus expected resistance Rwx n actual Rwx n expected 1 MI Maximum x 1 2 Notes 3 Relative Linearity is a measure of the error in step size between taps Rwx n 1 Rwx n MI 1 MI x 0 1 2 Notes 4 1 MI Minimum Increment Rtot Number of taps in DCP 1 Notes 5 Typical values are for Ta 25 C and nominal supply voltage Notes 6 This parameter is periodically sampled and not 100 tested 20 intersil FN8207 1 January 3 2006 X9521 APPENDIX 1 DCP1 100 Tap Tap position to Data Byte translation Table Tap Data Byte Position Decimal Binary 0 0 0000 0000 1 1 0000 0001 23 23 0001 0111 24 24 0001 1000 25 56 0011 1000 26 55 0011 0111 48 33 0010 0001 49 32 0010 0000 50 64 0100 0000 51 65 0100 0001 73 87 0101 0111 74 88 0101 1000 e s Www BDTI Cie nt 76 BDH G nter sl 98 97 0110 0001 99 96 0110 0000 21 intersil FN8207 1 January 3 2006 X9521 APPENDIX 2 DCP1 100 Tap tap position to Data Byte translation algorithm example Example 1 unsigned DCP1 TAP Position int tap pos i
13. ACKNOWLEDGE followed by Data Byte and finally the master issues a STOP condition The Data Byte read in this operation corresponds to the wiper A read of DCP c n EXT usffig the iti FA th F f CP pointed to by three byte MNT cb s nC t47 aga Pp Figure 11 The master issues the START condition and the Slave Address Byte 10101110 which specifies that a dummy write is to be conducted This dummy write operation sets which DCP is to be read in the preceding Read operation An ACKNOWLEDGE is returned by the X9521 after the Slave Address if received correctly Next It should be noted that when reading out the data byte for DCP1 100 Tap the upper most significant bit is an unknown For DCP2 256 Tap however all bits of the data byte are relevant See Figure 11 S WRITE Operation S READ Operation Signals from Slave Instruction Slave the Master r Address Byte r Address Data Byte o t A t EU A p rd SDA Bus o000f N10101111 Signals from c C C DCPx the Slave i i K E mr Bos BS er ae oe tn x 1 Dummy write PS x 2 Figure 11 DON T CARE DCP Read Sequence 8 intersil FN8207 1 January 3 2006 X9521 S t WRITE Operation S Signals from a t the Master r Slav
14. ARACTERISTICS See Figure 22 Figure 23 Figure 24 400kHz Symbol Parameter Min Max Units fscL SCL Clock Frequency 0 400 kHz tin 5 Pulse width Suppression Time at inputs 50 ns taa SCL LOW to SDA Data Out Valid 0 1 0 9 us tBUF 5 Time the bus free before start of new transmission 1 3 us tiow Clock LOW Time 1 3 us tHIGH Clock HIGH Time 0 6 us tSU STA Start Condition Setup Time 0 6 us tHD STA Start Condition Hold Time 0 6 us tsu DAT Data In Setup Time 100 ns tHD DAT Data In Hold Time 0 us tsu STO Stop Condition Setup Time 0 6 us tp 9 Data Output Hold Time 50 ns tg 9 SDA and SCL Rise Time 20 1Cb 2 300 ns te SDA and SCL Fall Time 20 1Cb 2 300 ns tsu wP WP Setup Time 0 6 us tHD wP WP Hold Time 0 uS oA C conii ntersit A C TEST CONDITIONS Input Pulse Levels 0 1Vcc to 0 9Vcc Input Rise and Fall Times 10ns Input and Output Timing Levels 0 5VCC Output Load See Figure 20 NONVOLATILE WRITE CYCLE TIMING Symbol Parameter Min Typ Max Units two Nonvolatile Write Cycle Time 5 10 ms CAPACITANCE Ta 25 C f 1 0 MHz Vcc 5V Symbol Parameter Max Units Test Conditions Cout 5 Output Capacitance SDA V1RO V2RO V3RO 8 pF Vout 0V Cin Input Capacitance SCL WP 6 pF Vin OV Notes 1 Typical values are for TA 25 C and Vcc 5
15. In addition to the preceding features the X9521 also operation us incorporates the following data protection functionality When reading the contents of the CONSTAT register The proper clock count and data bit sequence is the bits CS7 CS5 and CSO will always return 0 RA 4 required prior to the STOP bit in order to start a nonvol atile write cycle X9521 Write Permission Status Block Lock Write to CONSTAT Register ilis DCP Volatile Write DCP Nonvolatile Write to EEPROM ces BLO BL1 WP Permitted Write Permitted Permitted Volatile Bits Nonvolatile Bits x 1 1 NO NO NO NO NO 1 x 1 NO NO NO NO NO 0 0 1 YES NO NO NO NO X 1 0 NO NO Not in locked region YES YES 1 x 0 NO NO Not in locked region YES YES 0 0 0 YES YES Yes All Array YES YES 14 intersil FN8207 1 January 3 2006 X9521 ABSOLUTE MAXIMUM RATINGS Parameter Min Max Units Temperature under Bias 65 135 C Storage Temperature 65 150 C Voltage on WP pin With respect to Vss 1 0 15 V Voltage on other pins With respect to Vss 1 0 7 V Voltage on Rp Voltage on Ri x X 1 2 Referenced to Vss Voc V D C Output Current SDA 0 5 mA Lead Temperature Soldering 10 seconds 300 C Supply Voltage Limits Applied Vcc voltage referenced to Vss 2 7 5 5 V RECOMMENDED OPERATING CONDITIONS Temperature Min Max Units Indu
16. Nonvolatile below BL1 BLO Block Lock protection bits Nonvolatile The Block Lock protection bits BL1 and BLO are used to lnhibit a write operation from being performed to cer tain addresses of the EEPROM memory array nhibit a DCP write operation changing the wiper position 12 intersil FN8207 1 January 3 2006 X9521 ee i hy a RNA K A CS7 CS6CS5 C84 CS3 CS2CS1 CSO A V SLAVE ADDRESS BYTE V ADDRESS BYTE K M v CONSTAT REGISTER DATA IN Figure 18 CONSTAT Register Write Command Sequence The region of EEPROM memory which is protected locked is determined by the combination of the BL1 and BLO bits written to the CONSTAT register It is possible to lock the regions of EEPROM memory shown in the table below Protected Addresses Partition of array BL1 BLO Size locked 0 0 None Default None Default 0 1 COh FFh 64 bytes Upper 1 4 1 0 80h FFh 128 bytes Upper 1 2 1 1 OOh FFh 256 bytes All If the user attempts to perform a ws im ian O ro the whol tected region e e ero sC aborted without Chali date alray When the Block Lock bits of the CONSTAT register are set to something other than BL1 0 and BLO 0 then the wiper position of the DCPs cannot be changed i e DCP write operations cannot be conducted BL1 BLO DCP Write Operation Permissible 0 0 YES Default 0 1 NO 1 0 NO 1 1 NO
17. OM array as well as the CONSTAT register is aborted and no ACKNOWLEDGE is issued after a Data Byte TES succ Qe Noe CON 3 The WEL bit is a volatile latch that powers up in the dis abled LOW 0 state The WEL bit is enabled set by writing 00000010 to the CONSTAT register Once enabled the WEL bit remains set to 1 until either it is reset to 0 by writing 00000000 to the CONSTAT regis ter or until the X9521 powers down and then up again Writes to the WEL bit do not cause an internal high volt age write cycle Therefore the device is ready for another operation immediately after a STOP condition is executed in the CONSTAT Write command sequence See Figure 18 RWEL Register Write Enable Latch Volatile The RWEL bit controls the CONSTAT Register Write Enable status of the X9521 Therefore in order to write to any of the bits of the CONSTAT Register except WEL the RWEL bit must first be set to 1 The RWEL bit is a volatile bit that powers up in the disabled LOW 0 state It must be noted that the RWEL bit can only be set once the WEL bit has first been enabled See CONSTAT Register Write Operation The RWEL bit will reset itself to the default O state in one of three cases ipe n to any bits of completed See When the X9521 is powered down When attempting to write to a Block Lock protected region of the EEPROM memory See BL1 BLO Block Lock protection bits
18. START condition which is a HIGH to LOW transition of SDA while SCL is HIGH The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met See Figure 2 C compact Data Change l mw pos hi is 1 4 Stop Valid Start and Stop Conditions Data Stable Valid Data Changes on the SDA Bus Serial Stop Condition All communications must be terminated by a STOP condition which is a LOW to HIGH transition of SDA is HIGH The STOP cenditjon is also used to de ero p wer mode after a entel AS c in can only be issued after the transmitting device has released the bus See Figure 2 Serial Acknowledge An ACKNOWLEDGE ACK is a software convention used to indicate a successful data transfer The transmit ting device either master or slave will release the bus after transmitting eight bits During the ninth clock cycle the receiver will pull the SDA line LOW to ACKNOWL EDGE that it received the eight bits of data Refer to Figure 3 The device will respond with an ACKNOWLEDGE after recognition of a START condition if the correct Device Identifier bits are contained in the Slave Address Byte If a write operation is selected the device will respond with an ACKNOWLEDGE after the receipt of each subse quent eight bit word In the read mode the device will transmit eight bits of data release the SDA line then monitor the lin
19. any integer greater than 1 Figure 16 Sequential EEPROM Read Sequence FN8207 1 January 3 2006 11 intersil X9521 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CSO 0 0 0 BLI BLO RWEL WEL O NV NV Bit s Description CS7 CS5 Always 0 RESERVED BL1 BLO Sets the Block Lock partition RWEL Register Write Enable Latch bit WEL Write Enable Latch bit cso Always 0 RESERVED NOTE Bits labelled NV are nonvolatile See CONTROL AND STATUS REGISTER Figure 17 CONSTAT Register Format CONTROL AND STATUS REGISTER The Control and Status CONSTAT Register pro vides the user with a mechanism for changing and reading the status of various parameters of the X9521 See Figure 17 The CONSTAT vregister Jj vier del loth a and nonvolatile nva E Jdol off th STAT register retain their stored S ics even MS cc is powered down then powered back up The volatile bits however will always power up to a known logic state 0 irrespective of their value at power down A detailed description of the function of each of the CON STAT register bits follows WEL Write Enable Latch Volatile The WEL bit controls the Write Enable status of the entire X9521 device This bit must first be enabled before ANY write operation to DCPs EEPROM memory array or the CONSTAT register If the WEL bit is not first enabled then ANY proceeding volatile or nonvolatile write operation to DCPs EEPR
20. e Address Data o t Address Byte Byte p B f zs S f us S SDA Bus 10100000 g Ly A A Signalsfrom Internal C C the Slave L Address K Figure 12 EEPROM Byte Write Sequence 2kbit EEPROM ARRAY EEPROM Page Write Operations on the 2kbit EEPROM Array consist of either 1 2 or 3 byte command sequences All operations on the EEPROM must begin with the Device Type Identifier of the Slave Address set to 1010000 A Read or Write to the EEPROM is selected by setting the LSB of the Slave Address to the appropriate value R W Read 1 Write 0 In some cases when performing a Read or Write to the EEPROM an Address Byte may also need to be speci fied This Address Byte can contain the values OOh to MAN BDTI C c EEPROM Byt In order to perform an EEPROM Byte Write operation to the EEPROM array the Write Enable Latch WEL bit of the CONSTAT Register must first be set See BL1 BLO Block Lock protection bits Nonvolatile on page 12 For a write operation the X9521 requires the Slave Address Byte and an Address Byte This gives the master access to any one of the words in the array After receipt of the Address Byte the X9521 responds with an ACKNOWLEDGE and awaits the next eight bits of data After receiving the 8 bits of the Data Byte it again responds with an ACKNOWLEDGE The master then terminates the transfer by generating a STOP condition at which time the X9521 begins the internal write cycle to the nonvolatile
21. e for an ACKNOWLEDGE If an ACKNOWLEDGE is detected and no STOP condition is generated by the master the device will continue to transmit data The device will ter minate further data transmissions if an ACKNOWLEDGE is not detected The master must then issue a STOP condition to place the device into a known state 3 intersil FN8207 1 January 3 2006 X9521 SCL from Master Data Output from Trans Data O fro Rece mitter utput m iver Start Figure 3 DEVICE INTERNAL ADDRESSING Addressing Protocol Overview The user addressable internal components of the X9521 can be split up into three main parts Two Digitally Controlled Potentiometers DCPs EEPROM array Control and Status CONSTAT Register m NE P c l Acknowledge Acknowledge Response From Receiver The next three bits SA3 SA1 are the Internal Device Address bits Setting these bits to 000 internally selects the EEPROM array while setting these bits to 111 selects the DCP structures in the X9521 The CONSTAT Register may be selected using the Inter nal Device Address 010 The Least Significant Bit of the Slave Address SAO Byte is the R W bit This bit defines the operation to be performed on the device being addressed as defined in the bits SA3 SA1 When the R W bit is 1 then a READ operation is selected A 0 selects a WRITE Depending upon the operation to be id on eni of th
22. emperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 PIN CONFIGURATION www BDTI C cond 20 Pin TSSOP Rh2 g 1 20 1 Vec Rw2 12 190 NC Rio O 3 180 NC NC 4 17 NC NC 5 16 NC NC 6 15 NC WE CI 140 NC SCL 8 130 Ruy SDA r19 120 Rw 10 Intersil PIN ASSIGNM Pin Name Function 1 Rue Connection to end of resistor array for the 256 Tap DCP 2 2 Rw2 Connection to terminal equivalent to the Wiper of a mechanical potentiometer for DCP 2 3 Ri2 Connection to other end of resistor array for the 256 Tap DCP2 Write Protect Control Pin WP pin is a TTL level compatible input When held HIGH Write Protection is enabled In the enabled state this pin prevents all nonvolatile write operations Also when the Write Pro 7 WP tection is enabled and the device Block Lock feature is active i e the Block Lock bits are NOT 0 0 then no write volatile or nonvolatile operations can be performed in the device including the wiper position of any of the integrated Digitally Controlled Potentiometers DCPs The WP pin uses an internal pull down resistor thus if left floating the write protection feature is disabled Serial Clock This is a TTL level compatible input pin used to control the serial bus timing for data input 8 SCL and outp
23. er consisting of 02H 06H 02H will reset the There are a number of levels of data protection features BLO and BLO bits in the CONSTAT Register to O designed into the X9521 Any write to the device first It should be noted that a write to any nonvolatile bit of requires setting of the WEL bit n the CONSTAT register CONSTAT register will be ignored if the Write Protect A write to the CONSTAT register itself further requires pin of the X9521 is active HIGH See WP Write Pro the setting of the RWEL bit Block Lock protection of the device enables the user to inhibit writes to certain regions of the EEPROM memory as well as to all the DCPs One further level of data protection in the X9521 is incorpo CONSTAT Register Read Operation rated in the form of the Write Protection pin The contents of the CONSTAT Register can be read o any time by performing a eme dal inate te Protection Pin Using the Slav co an C Ome wA Pro Ui soy e e fon bae HIGH Address oye oU Ae isdljl s pe he X9521 ister read operation The X9521 resets itself after the t tection Pin byte is read The master should supply a STOP condition The table below X9521 Write Permission Status sum to be consistent with the bus protocol marizes the effect of the WP pin and Block Lock on the it issi tat fth ice After setting the WEL and or the RWEL bit s to a 1 WG paries SNE DENG GENIS interrupting a proceeding CONSTAT register write
24. ese individual parts a 1 2 or ol is All operations h fth She Address Byte MAE t n iTh address selects the part of the X9521 to be ibis and specifies if a Read or Write operation is to be per formed It should be noted that in order to perform a write opera tion to either a DCP or the EEPROM array the Write Enable Latch WEL bit must first be set See BL1 BLO Block Lock protection bits Nonvolatile on page 12 Slave Address Byte Following a START condition the master must output a Slave Address Byte Refer to Figure 4 This byte con sists of three parts The Device Type Identifier which consists of the most significant four bits of the Slave Address SA7 SA4 The Device Type Identifier must always be set to 1010 in order to select the X9521 operation Refer to Figure 4 com nkerstl z 1 0 1 0 RW M v PES Y J XxX Y J DEVICE TYPE INTERNAL READ IDENTIFIER DEVICE WRITE ADDRESS Internal Address Internally Addressed SA3 SA1 Device 000 EEPROM Array 010 CONSTAT Register 111 DCP Bit SAO Operation 0 WRITE 1 READ Figure 4 Slave Address Format 4 intersil FN8207 1 January 3 2006 X9521 Nonvolatile Write Acknowledge Polling After a nonvolatile write command sequence for either the EEPROM array the Non Volatile Memory of a DCP NVM or the CONSTAT Register has been correctly issued including the final STOP condition
25. instead set to one This is followed by an ACKNOWLEDGE from issuing a STOP condition the X9521 and then by the eight bit word The master ter minates the read operation by not responding with an ACKNOWLEDGE and instead issuing a STOP condition Refer to Figure 15 Address Byte and then goes into standby mode after the STOP bit All bus activity will be ignored until another START is detected Sequential EEPROM Read Sequential reads can be initiated as either a current address read or random address read The first Data The data output is sequential with the data from address n followed by the data from address n 1 The address counter for read operations increments through the entire memory contents to be serially read during one operation At the end of the address space the counter rolls over to address OOh and the device con tinues to output data for each ACKNOWLEDGE received Refer to Figure 16 A similar operation called Set Current Address also exists This operation is performed if a STOP is issued instead of the second START shown in Figure 15 In this case the device sets the address pointer to that of the S Signals from Slave A A A the Master Address C C C K K K E p SDA Bus 0001 V V V J u ue J an oo P Ga 5m p a K 1 2 n 1 n n is
26. ite Enable Latch RWEL AND the WEL bit This is also a volatile cycle The zeros in the data byte are required Operation preceded by a START and ended with a STOP Write a one byte value to the CONSTAT Register that has all the bits set to the desired state The CONSTAT register can be represented as OO0st010 in binary where st are the Block Lock Protection BL1 and BLO bits This operation is proceeded by a START and ended with a STOP bit Since this is a nonvolatile write cycle it will typically take 5ms to complete The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again If bit 2 is set to 1 in this third step 000s t110 then the RWEL bit is set but the BL1 and BLO bits remain unchanged Writing a second byte to the control register is not allowed Doing so aborts the write operation and the X9521 does not return an ACKNOWLEDGE 13 intersil FN8207 1 January 3 2006 X9521 WRITE Operation READ Operation S S Signals from t Slave Address t S a a Slave t the Master Address Byte r Address o t t p L po WMO687 CS0 SA Bus N N 01100101 r A A A Signals from J C C C the Slave K K K Pale Dummy Write Figure 19 CONSTAT Register Read Command Sequence For example a sequence of writes to the device CON DATA PROTECTION STAT regist
27. memory See Figure 12 During this internal write cycle the X9521 inputs are disabled so it does not respond to any requests from the master The SDA output is at high impedance A write to a region of EEPROM memory which has been protected with the Block Lock feature See BL1 BLO Block Lock protection bits Nonvolatile on page 12 suppresses the ACKNOWLEDGE bit after the Address Byte In order to perform an EEPROM Page Write operation to the EEPROM array the Write Enable Latch WEL bit of the CONSTAT Register must first be set See BL1 BLO Block Lock protection bits Nonvolatile on page 12 The X9521 is capable of a page write operation It is initi ated in the same manner as the byte write operation but instead of terminating the write cycle after the first data byte is transferred the master can transmit an unlimited number of 8 bit bytes After the receipt of each byte the X95217 responds with an ACKNOWLEDGE and the se fengngenen J one The page emi o t th counter reaches the end of the page it rolls over and goes back to 0 on the same page S S For example if the master writes 12 bytes to the page starting at location 11 decimal the first 5 bytes are writ ten to locations 11 through 15 while the last 7 bytes are written to locations O through 6 Afterwards the address counter would point to location 7 If the master supplies more than 16 bytes of data then new data overwrites the
28. nt QE int int areri int wcr val offset 0 block tap pos 25 if block lt 0 return unsigned 0O else if block 3 switch block case 1 wcr val 56 E tap pos 25 Bort Georg nt case 2 wcr val 64 offset tap pos 50 return unsigned wcr val return unsigned 01100000 case 0 return unsigned tap pos i wcr val riter si J case 3 i wcr val 120 offset tap pos 75 for i 0 i lt offset i wcr val return unsigned wcr val J for i20 i offset i wcr_val 1 l 22 intersil FN8207 1 January 3 2006 X9521 APPENDIX 2 DCP1 100 Tap tap position to Data Byte translation algorithm example Example 2 unsigned DCP100 TAP Position int tap pos optional range checking if tap pos lt 0 return unsigned Q set to min val else if tap pos gt 99 return unsigned 96 set to max val 100 Tap DCP encoding formula if tap_pos gt 74 return unsigned 195 tap pos else if tap pos 49 return unsigned 14 tap pos else if tap pos 24 return unsigned 81 tap pos else return tap pos ww BDTI C com ntersi 23 intersil FN8207 1 anuary 3 2006 X9521 20 LEAD PLASTIC TSSOP PACKAGE TYPE V X 025 65 BSC e 169 4 3
29. om EEPROM Read and Sequential EEPROM Read Current EEPROM Address Read Internally the device contains an address counter that maintains the address of the last word read incremented by one Therefore if the last read was to address n the next read operation would access data from address n 1 On power up the address of the address counter is undefined requiring a read or write operation for initial ization Upon receipt of the Slave Address Byte with the R W bit set to one the device issues an ACKNOWLEDGE and then transmits the eight bits of the Data Byte The master terminates the read operation when it does not respond with an ACKNOWLEDGE during the ninth clock and then issues a STOP condition See Figure 14 for the address ACKNOWLEDGE and data transfer sequence operation is not a don t care To terminate a read oper ation the master must either issue a STOP condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a STOP condition Another important point to note regarding the Current EEPROM Address Read is that this operation is not available if the last executed operation was an access to a DCP or the CONSTAT Register i e an operation using the Device Type Identifier 1010111 or 1010010 Immediately after an operation to a DCP or CONSTAT Register is performed only a Handom EEPROM Read is available Immediately following a Random EEPROM Read a Current EEPROM Address
30. r arrays These arrays respectively contain 99 and 255 discrete e t ecied in series The ELAS TE alent to the fixed als of a mechanical potentiometer Rp and Ri x inputs where x 1 2 At both ends of each array and between each resistor segment there is a CMOS switch connected to the wiper Ry output Within each individual array only one switch may be turned on at any one time These switches are controlled by the Wiper Counter Register WCR See Figure 6 The WCR is a volatile register On power up of the X9521 wiper position data is auto matically loaded into the WCR from its associated Non Volatile Memory NVM Register The Table below shows the Initial Values of the DCP WCR s before the contents of the NVM is loaded into the WCR DCP Initial Values Before Recall R4 100 TAP VL TAP 0 Ro 256 TAP Vy TAP 255 5 intersil FN8207 1 January 3 2006 X9521 Vcc Maximum Wiper Recall time Figure 7 DCP Power up The data in the WCR is then decoded to select and enable one of the respective FET switches A make before break sequence is used internally for the FET switches when the wiper is moved from one tap position to another Hot Pluggability Figure 7 shows a typical waveform that the X9521 might experience in a Hot Pluggable situation On power up Vcc applied to the X9521 may exhibit some amount of ringing before it s the BLT C The device NUM l t
31. see www intersil com 24 intersil FN8207 1 anuary 3 2006
32. strial 40 85 C NOTE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended peri ods may affect device reliability Figure 20 Equivalent A C Circuit BDTI C an i SDA 100pF Vv Figure 21 DCP SPICE Macromodel Roa 0 Rx NA ad Rix l I CH Boy iopP 10pF Cw i l 25pF l x 12 Rwx 15 intermsi I Sdn E X9521 TIMING DIAGRAMS Figure 22 Bus Timing SCL SDA IN SDA OUT Figure 23 WP Pin Timing Stop Start Condition Condition 16 intersil FN8207 1 M anuary 3 2006 X9521 Figure 25 DCP Wiper Position Timing Rwx x 1 2 n tap position si 0 1 0 1 1 1 O0 AW 00 0 0 0 P1 PO A D7 D6 D5 D4 D3 D2 D1 DO A S C C T AM v E n b KS v 7 K O R SLAVE ADDRESS BYTE INSTRUCTION BYTE DATA BYTE P BDTI C nd nt i 17 H e FN8207 1 intersil January 3 2006 X9521 D C OPERATING CHARACTERISTICS Symbol Parameter Min Typ Max Unit Test Conditions Notes Current into Vcc Pin X9521 Active Icc1
33. the ip itige oF t CP as stored in the Tite is ss using the Random Address Read command sequence consisting of the DCP Slave Address Byte followed by an Instruction Byte and the Slave Address Byte again Refer to Figure 11 Instruction Byte While the Slave Address Byte is used to select the DCP devices an Instruction Byte is used to determine which DCP is being addressed The Instruction Byte Figure 8 is valid only when the Device Type Identifier and the Internal Device Address bits of the Slave Address are set to 1010111 In this case the two Least Significant Bit s I1 10 of the Instruction Byte are used to select the particular DCP 0 2 In the case of a Write to any of the DCPs i e the LSB of the Slave Address is 0 the Most Significant Bit of the Instruction Byte I7 deter mines the Write Type WT performed If WT is 1 then a Nonvolatile Write to the DCP occurs In this case the wiper position of the DCP is changed by simultaneously writing new data to the associated WCR and NVM Therefore the new wiper position set ting is recalled into the WCR after Vcc of the X9521 has been powered down then powered back up 6 intersil FN8207 1 January 3 2006 X9521 I7 l6 I5 l4 I3 I2 nh 10 WT 0 0 0 0 0 P1 PO C a WRITE TYPE DCP SELECT wit Description 0 Select a Volatile Write operation to be performed on the DCP pointed to by bits P1 and PO 1 Select a Nonvolatile Write opera
34. the first rising edge of the clock signal after the LSB of the Data Byte DO has been issued on SDA See Figure 25 The Data Byte determines the wiper position which FET switch of the DCP resistive array is switched ON of the DCP The maximum value for the Data Byte depends upon which DCP is being addressed see Table below P1 PO DCPx Taps Max Data Byte 0 0 Reserved 0 1 1 100 Refer to Appendix 1 1 0 x 2 256 FFh 1 1 Reserved Using a Data Byte larger than the values specified above results in the wiper terminal being set to the highest tap position The wiper position does NOT roll over to the lowest tap position the Data Byte ngaps one to one to A ovd ed femina There I5 rresponds to set ting the wiper terminal to tap position 15 Similarly the Data Byte 00011100 2840 corresponds to setting the wiper terminal to tap position 28 The mapping of the Data Byte to wiper position data for DCP1 100 Tap is shown in APPENDIX 1 An example of a simple C lan guage function which translates between the tap posi tion decimal and the Data Byte binary for DCP1 is given in APPENDIX 2 It should be noted that all writes to any DCP of the X9521 are random in nature Therefore the Data Byte of con secutive write operations to any DCP can differ by an arbitrary number of bits Also setting the bits P1 O 0 0 P1 Po A D7 D6 D5 D4 D3 D2 D1 DO
35. tion to be per formed on the DCP pointed to by bits P1 and PO t This bit has no effect when a Read operation is being performed Figure8 Instruction Byte Format If WT is 0 then a DCP Volatile Write is performed This operation changes the DCP wiper position by writing new data to the associated WCR only The contents of the associated NVM register remains unchanged There fore when Vcc to the device is powered down then back up the wiper position reverts to that last written to the DCP using a nonvolatile write operation DCP Write Operation A write to DCP three byte DOM n In order to perform a write operation on a particular DCP the Write Enable Latch WEL bit of the CONSTAT Reg ister must first be set See BL1 BLO Block Lock protec tion bits Nonvolatile on page 12 The Slave Address Byte 10101110 specifies that a Write to a DCP is to be conducted An ACKNOWLEDGE is returned by the X9521 after the Slave Address if it has been received correctly Next an Instruction Byte is issued on SDA Bits P1 and PO of the Instruction Byte determine which WCR is to be written while the WT bit determines if the Write is to be Vy BERE COEPI volatile or nonvolatile If the Instruction Byte format is valid another ACKNOWLEDGE is then returned by the X9521 Following the Instruction Byte a Data Byte is issued to the X9521 over SDA The Data Byte contents is latched into the WCR of the DCP on
36. ut 9 SDA Serial Data SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the de vice The SDA pin input buffer is always active not gated This pin requires an external pull up resistor 10 Vss Ground 11 Ruy Connection to other end of resistor for the 100 Tap DCP 1 12 Rw1 Connection to terminal equivalent to the Wiper of a mechanical potentiometer for DCP 1 13 RH Connection to end of resistor array for the 100 Tap DCP 1 20 Vcc Supply Voltage 4 5 6 ie i NC No connect 18 19 i H FN8207 1 2 intersil January 3 2006 X9521 SCL SDA Start Figure 2 I SCL SDA Data Stable Figure 1 PRINCIPLES OF OPERATION SERIAL INTERFACE The device supp ion P e ri nt d The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver The device controlling the transfer is called the master and the device being controlled is called the slave The master always initiates data transfers and provides the clock for both transmit and receive opera tions Therefore the X9521 operates as a slave in all applications Serial Clock and Data Data states on the SDA line can change only while SCL is LOW SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions See Figure 1 On power up of the X9521 the SDA pin is in the input mode Serial Start Condition All commands are preceded by the
Download Pdf Manuals
Related Search
intersil X9521 Manual