intersil ISL90841 handbook
Contents
1. 9 intersil FN8094 1 February 8 2006 ISL90841 START DATA DATA DATA STOP STABLE CHANGE STABLE FIGURE 15 VALID DATA CHANGES START AND STOP CONDITIONS SCL FROM PN SIN NTS SDA OUTPUT FROM 9 HIGH IMPEDANCE SDA OUTPUT FROM HIGH IMPEDANCE RECEIVER START ACK FIGURE 16 ACKNOWLEDGE RESPONSE FROM RECEIVER eom I ntersi l WANN FROM THE MASTER 5 IDENTIFICATION ADDRESS DATA T 1 BYTE BYTE BYTE E A f X f X 4 SIGNAL AT SDA Ne 0 1 0A1A00 000000 SIGNALS FROM A A A THE ISL90841 K K K FIGURE 17 BYTE WRITE SEQUENCE S S SIGNALS T T S FROM THE A IDENTIFICATION A IDENTIFICATION A e T MASTER R BYTE WITH ADDRESS R BYTE WITH T R W 0 BYTE T RIW 1 K E P f ss Ne 4 SIGNAL SDA o 1 0 1 04140 0 000000 Nooa oaran A V SIGNALS FROM _ FIRST READ LAST READ THE SLAVE K K DATA BYTE DATA BYTE FIGURE 18 READ SEQUENCE H e FN8094 1 10 Intersil February 8 2006 ISL90841 Write Operation A Write operation requires a START condition followed by a valid Identification Byte a valid Address Byte a Data Byte and a STOP condition After2. 0075 19 JL 0118 30 6 1 ww BDTI ntersi d Plane o o 7 0 8 i Seating Plane 019 50 a 029 75 Detail A 20X gees 031 80 041 1 05 See Detail I NOTE ALL DIMENSIONS IN INCHES IN PARENTHESES IN MILLIMETERS All Intersil U S products are manufactured assembled and tested utilizing 1509000 quality systems Intersil Corporation s quality certifications can be viewed at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 12 intersil FN8094 1 c February 8 2006
3. 85 14 Ld TSSOP Pb Free ISL90841WIV1427Z Notes 1 amp 2 90841WI27Z 10K 40 to 85 14 Ld TSSOP Pb Free NOTES 1 Intersil Pb free plus anneal products employ special Pb free material sets molding compounds die attach materials and 100 matte tin plate termination finish which are RoHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 2 Add TK to suffix for Tape and Reel 1 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 1 888 468 3774 Intersil and design is a registered trademark of Intersil Americas Inc XDCP is a trademark of Intersil Americas Inc Copyright Intersil Americas Inc 2005 2006 All Rights Reserved All other trademarks mentioned are the property of their respective owners ISL90841 Functional Diagram Block Diagram 2 INTERFACE a GND Rwo Rw2 CINTERFACE POWER UP Rw2 INTERFACE CONTROL AND STATUS GND Pin Descriptions TSSOP PIN SYMBOL DESCRIPTION 1 RH3 High terminal of DCP3 2 RW3 Wiper terminal of DCP3 3 SCL 2 interface clock 4 SDA Serial data I O for the I2C interface 5 GND Device ground pin 6 RW2 Wiper terminal of DCP2 7 RH2 Hig
4. 2 MI Note 9 RmatcH DCP to DCP matching Any two DCPs at the same tap position with 2 2 MI Note 13 the same terminal voltages Note 9 TCR Resistance temperature coefficient DOP register set between 20 hex and FF hex 45 ppm C Note 14 FN8094 1 February 8 2006 ISL90841 Operating Specifications Over the recommended operating conditions unless otherwise specified TYP SYMBOL PARAMETER TEST CONDITIONS MIN NOTE 1 MAX UNIT Vcc supply current volatile fsc 400kHz SDA Open for 2 active 1 mA write read read and write states Isp Vcc current standby Voc 5 5V 12C interface in standby state 5 Voc 3 6V 12C interface in standby state 2 ILkgDig Leakage current at pins AO A1 SDA Voltage at pin from GND to Vcc 10 10 SCL DCP wiper response time SCL falling edge of last bit of DCP data byte 1 us Note 15 to wiper change SERIAL INTERFACE SPECS ViL A1 A0 SDA and SCL input buffer 0 3 0 3 Vcc V LOW voltage 1 AO SDA SCL input buffer 0 7 0 3 V HIGH voltage Hysteresis SDA and SCL input buffer hysteresis 0 05 V Note 15 Vcc VoL SDA output buffer LOW voltage 0 0 4 V Note 15 sinking 4mA Cpin A1 AO SDA and SCL pin 10 pF Note 15 capacitance fscL SCL frequency 400 kHz tin Pulse width suppression time ny pulse narrower than
5. each of the three bytes the ISL90841 responds with an ACK At this time the device enters its standby state See Figure 17 Read Operation A Read operation consist of a three byte instruction followed by one or more Data Bytes See Figure 18 The master initiates the operation issuing the following sequence a START the Identification byte with the R W bit set to 0 an Address Byte a second START and a second Identification byte with the R W bit set to 1 After each of the three bytes the ISL90841 responds with an ACK Then the ISL90841 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte The master terminates the read operation issuing a STOP condition following the last bit of the last Data Byte See Figure 18 The Data Bytes are from the registers indicated by an internal pointer This pointer initial value is determined by the Address Byte in the Read operation instruction and increments by one during transmission of each Data Byte After reaching the memory location O3h the pointer rolls over to 00h and the device continues to output data for vow BDTI com ntersi 11 intersil FN8094 1 February 8 2006 ISL90841 Packaging Information 14 Lead Plastic TSSOP Package Code V14 025 65 BSC 252 6 4 BSC
6. i i LSB V Ry for i 1 to 255 VMATCH IV RyX V Ryy iJ LSB for i 0 to 255 x 0 to 3 and y 0 to 3 Max V RW Min V RW j 106 x for i 16 to 240 decimal T 40 C to 85 C Max is the maximum value of the wiper V They RW AL MIn VIRAN 7 8 o Max V RW Min V RW 2 125 C voltage and Min is the minimum value of the wiper voltage over the temperature range MI R255 Ro 255 R255 and Rg are the measured resistances for the DCP register set to FF hex and 00 hex respectively Roffset Ro MI when measuring between Ry and GND Roffset R255 MI when measuring between Rw and Ry Rj Rj 4 MI for i 32 to 255 RINL Rj MI i RoJ MI for i 32 to 255 RMATCH Rix Ri y MI for i to 255 x 0 to 3 and y 0 to 3 F 6 TC MaxiRD MIn RD 10 for 32 to 255 T 40 C to 85 Max is the maximum value of the resistance and Min is the Max Ri Min Ri 2 125 C minimum value of the resistance over the temperature range This parameter is not 100 tested Typical Performance Curves 160 1 8 Vcc72 7 85 140 S 420 ul 2 100 2 gt a 4 60 z ne a2 40 20 Ve 5 5 T 40 C 5 5 T 85 C 4 0 2 5 5 T 25 C 0 0 0 50 100 150 200 250 27 3 2 3 7 4 2 4 7 5 2 T
7. 022 T2425 Vec 5 5 25 0 3 5 5 T 40 C o 5 5 T 85 C E 01 Comet o a Vcc22 7 T 85 C a 2 0 1 0 1 5 5 85 eae 0 3 0 2 Vcc 2 7 40 Vcc727 85 cc 2 7 5 5 T 40 C 5 5 25 T 40 C 0 3 0 5 1 1 32 82 132 182 232 32 82 132 182 232 TAP POSITION DECIMAL TAP POSITION DECIMAL FIGURE 7 DNL vs TAP POSITION IN RHEOSTAT MODE FOR FIGURE 8 INL vs TAP POSITION IN RHEOSTAT MODE FOR 50kQ U 50kQ U 7 FN8094 1 intersil February 8 2006 ISL90841 Typical Performance Curves continued END TO END RrorAL CHANGE 1 5 0 5 2 7V o 5 5V 1 5 40 20 0 20 40 60 80 TEMPERATURE C FIGURE 9 END TO END CHANGE vs TC ppm C TEMPERATURE FOR 10kQ W 32 82 132 182 232 TAP POSITION DECIMAL FIGURE 11 TC FOR RHEOSTAT MODE IN ppm SIGNAL AT WIPER WIPER UNLOADED N WIPER MOVEMENT MID POINT FROM 80h TO 7fh 50 0mV amp 50005 Ch2 X 17 FIGURE 13 MIDSCALE GLITCH CODE 80h to 7Fh WIPER 0 20 10 ppm C o 32 82 132 182 232 TAP POSITION DECIMAL FIGURE 10 TC FOR VOLTAGE DIVIDER MODE IN ppm L at ersi TOTAL 9 1 00 2 500 200ns Chi X 2 00 V FIGURE 12 F
8. AP POSITION DECIMAL Vcc V FIGURE 1 WIPER RESISTANCE vs TAP POSITION FIGURE 2 STANDBY Icc vs Vcc Voc RrorAL FOR 50 U 6 H FN8094 1 intersil February 8 2006 ISL90841 Typical Performance Curves continued 0 2 1 0 3 5 5 40 2 7 T 40 C 2 7 T 40 C 0 15 Vc c22 7 25 5 5 T 85 C 0 1 0 05 0 gt gt Voc 2 7 T 25 C A 0 05 TA ji 2 7 85 5 5 25 i 5 5 T 25 C Da 0 15 2 7 T 85 C 5 5 85 id 0 2 0 3 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION DECIMAL TAP POSITION DECIMAL FIGURE 3 DNL vs TAP POSITION IN VOLTAGE DIVIDER FIGURE 4 INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kQ W MODE FOR 10kQ W 0 4 0 0 35 0 2 Vec 5 5V a a o 0 3 8 2212 T 2 7V 9 9 8 025 8 6 Vec 2 7V N e C confi 0 15 1 40 20 0 20 40 60 80 40 20 0 20 40 60 80 TEMPERATURE C TEMPERATURE C FIGURE 5 ZSerror vs TEMPERATURE FOR 50kQ U FIGURE 6 FSerror vs TEMPERATURE FOR 50kQ U 0 3 0 5 2 7 T 25 C Vcc22 7 25 _
9. REQUENCY RESPONSE 2 2MHz SIGNAL AT WIPER WIPER UPLOADED MOVEMENT FROM ffh TO 00h TI 5 00 Ch2 1 00 amp M 20085 Ch2 X 1 28V FIGURE 14 LARGE SIGNAL SETTLING TIME 8 intersil FN8094 1 February 8 2006 ISL90841 Principles of Operation The ISL90841 is an integrated circuit incorporating four DCPs with their associated registers and an 2 serial interface providing direct communication between a host and the potentiometers DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer Ry and GND The Rw pin of each DCP is connected to intermediate nodes and is equivalent to the wiper terminal of a mechanical potentiometer The position of the wiper terminal within the DCP is controlled by an 8 bit volatile Wiper Register WR Each DCP has its own WR When the WR of a DCP contains all zeroes WR lt 7 0 gt 00h its wiper terminal Ry is closest to its Low terminal GND When the WR of a DCP contains all ones WR lt 7 0 gt FFh its wiper terminal is closest to its High terminal Ry As the value of the WR increases from all zeroes 00h to all ones 255 decimal the wiper moves monotonically from the position closest to GND to the closest to Ry At the same time the resistance between Ry and GND increases monotonically while th
10. T condition and does not respond to any command until this condition is met See Figure 15 A START condition is ignored during the power up of the device All 12C interface operations must be terminated by a STOP condition which is a LOW to HIGH transition of SDA while SCL is HIGH See Figure 15 A STOP condition at the end of a read operation or at the end of a write operation places the device in its standby mode An ACK Acknowledge is a software convention used to indicate a successful data transfer The transmitting device either master or slave releases the SDA bus after transmitting eight bits During the ninth clock cycle the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data See Figure 16 The ISL90841 responds with an ACK after recognition of a START condition followed by a valid Identification Byte and once again after successful receipt of an Address Byte The ISL90841 also responds with an ACK after receiving a Data Byte of a write operation The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 01010 as the five MSBs and th fdllowin bits matching fhe Idgic values present andad h is deje rite bit Its value is ead operation and 0 Tor a Write operation See Table 1 TABLE 1 IDENTIFICATION BYTE FORMAT Logic values at pins A1 and 0 respectively m 0 1 0 1 0 A1 AO R W MSB LSB
11. e resistance between Ry and Ryy decreases monotonically While the ISL90841 is being powered up all four WRs are reset to 80h 128 decimal which ghly a amp the center between The WRs can be read or written directly using the 2 serial interface as described in the following sections The 2 interface Address Byte has to be set to 00h 01h 02h and 03h to access the WR of DCPO DCP1 DCP2 and DCP3 respectively Serial Interface The ISL90841 supports a bidirectional bus oriented protocol The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver The device controlling the transfer is a master and the device being controlled is the slave The master always initiates data transfers and provides the clock for both transmit and receive operations Therefore the ISL90841 operates as a slave device in all applications All communication over the 12C interface is conducted by sending the MSB of each byte of data first Protocol Conventions Data states on the SDA line must change only during SCL LOW periods SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions See Figure 15 On power up of the ISL90841 the SDA pin is in the input mode All 12 interface operations must begin with a START condition which is a HIGH to LOW transition of SDA while SCL is HIGH 15190841 continuously monitors the SDA and SCL lines for the STAR
12. e stated 3 intersil TYP SYMBOL PARAMETER TEST CONDITIONS MIN NOTE 1 MAX UNIT RToTAL Ry to GND resistance W option 10 U option 50 kQ Ry to GND resistance tolerance 20 20 Rw Wiper resistance Vcc 3 3V 25 C wiper current 70 200 Q Vcc RTOTAL CH C_ Cw Potentiometer capacitance Note 15 10 10 25 pF ILkgocp Leakage on DCP pins Note 15 Voltage at pin from GND to Vcc 0 1 1 VOLTAGE DIVIDER MODE Vcc measured at Ryi unloaded i 0 1 2 or 3 INL Integral non linearity 1 LSB Note 6 r S Note 2 DNL Differential non linearity Monotonic over all tap positi ns 0 5 0 5 LSB Note 5 Note 2 ZSerror Zero scale error W option 0 1 7 LSB Note 3 Note 2 U option 0 0 5 2 FSerror Full scale error W option 7 1 0 LSB Note 4 Note 2 U option 2 1 0 VMATCH _ DCP to DCP matching Any two DCPs at same tap position same 2 2 LSB Note 7 voltage at all Ry terminals Note 2 TCy Ratiometric temperature coefficient DCP register set to 80 hex 4 ppm C Note 8 RESISTOR MODE Measurements between and i 0 1 2 or 3 RINL Integral non linearity DCP register set between 20 hex and FF 1 1 MI Note 12 hex monotonic over all tap positions Note 9 RDNL Differential non linearity 0 5 0 5 MI Note 11 Note 9 Roffset Offset W option 0 1 7 MI Note 10 Note 9 U option 0 0 5
13. h terminal of DCP2 8 RW1 Wiper terminal of DCP1 9 RH1 High terminal of DCP1 10 A0 Device address for the 2 interface 11 A1 Device address for the 12C interface 12 VCC Power supply pin 13 RHO High terminal of DCPO 14 RWO Wiper terminal of DCPO 2 intersil FN8094 1 February 8 2006 ISL90841 Absolute Maximum Ratings Storage temperature 65 C to 150 C Voltage at any digital interface pin with respect to 0 3V to 0 3 IUS REDIT mem 0 3V to 6V Voltage at any DCP pin with respect to 0 3V to Vcc Lead temperature soldering 105 300 C luy 10S i cate obese diete em hate bentes docena b es 6mA ed pote Class 11 Level B at 85 C gt 2kV Human Body Model Recommended Operating Conditions industrial eto X eee sa 40 C to 85 C Mecca E 2 7V to 5 5V Power rating of each 5mW Wiper current of each 3 0 CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Analog Specifications Over recommended operating conditions unless otherwis
14. intersil Data Sheet Low Noise Low Power 12 Bus 256 Taps The ISL90841 integrates four digitally controlled potentiometers XDCP on a monolithic CMOS integrated circuit The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches The position of the wipers are controlled by the user through the 2 bus interface Each potentiometer has an associated Wiper Register WR that can be directly written to and read by the user The contents of the WR controls the position of the wiper All four potentiometers have one terminal tied to GND The DCPs can be used as a resistor divider or as two terminal variable resistors in a wide variety of applications including control parameter adjustments and signal processing waw BDTI C com ntg Ordering Information ISL90841 Quad Digitally Controlled Potentiometers February 8 2006 FN8094 1 Features Four potentiometers in one package 256 resistor taps 0 4 resolution 12 serial interface Wiper resistance 700 typical 3 3V Standby current lt 5 max Power supply 2 7V to 5 5V 50kQ total resistance 14 Lead TSSOP Pb free plus anneal available ROHS compliant Pinout ISL90841 14 LEAD TSSOP TOP VIEW w2 RESISTANCE OPTION TEMP RANGE PART NUMBER PART MARKING Q C PACKAGE ISL90841UIV1427Z Notes 1 amp 2 9084101272 50K 40 to
15. intersil February 8 2006 ISL90841 Operating Specifications Over the recommended operating conditions unless otherwise specified Continued TYP SYMBOL PARAMETER TEST CONDITIONS MIN NOTE 1 MAX UNIT tF SDA and SCL fall time From 70 to 30 of Vcc 20 250 ns Note 15 0 1 Cb Cb Capacitive loading of SDA or SCL Total on chip and off chip 10 400 pF Note 15 Rpu SDA SCL bus pull up resistor off Maximum is determined by and 1 kQ Note 15 chip For Cb 400pF max is about 2 2 5kQ For Cb 40pF max is about 15 20kQ tSU A A1 and AO setup time Before START condition 600 ns tHD A A1 and hold time After STOP condition 600 ns SDA vs SCL Timing INPUT TIMING SCL tsu DAT tsu STA SDA SDA OUTPUT TIMING BDTI C com I ntersi START SCL CLK 1 tg tHD DAT STOP tHp A tsu sTo 5 intersil FN8094 1 February 8 2006 ISL90841 NOTES o 15 Typical values are for Ta 25 C and 3 3V supply voltage LSB V Rw 255 V Rw 9 255 V Rw 255 and V Rw o are V Ryy for the DCP register set to FF hex and 00 hex respectively LSB is the incremental voltage when changing from one tap to an adjacent tap ZS error V Ry o LSB FS error V Rw 255 Vcc LSB DNL V Rw i V Rw i 1 LSB 1 for i 1 to 255 i is the DCP register setting INL V Ry
16. the max spec is e 50 ns Note 15 and i upiffessed tAA SCL 19850 t CL Tel A nil er S 900 ns Note 15 valid SDA exits the 30 to 70 of Vcc window tBUF Time the bus must be free before the SDA crossing 70 of Vcc during a STOP 1300 ns Note 15 start of a new transmission condition to SDA crossing 70 of Vcc during the following START condition ti ow Clock LOW time Measured at the 30 of Vcc crossing 1300 ns tHIGH Clock HIGH time Measured at the 70 of Vcc crossing 600 ns tsu sta START condition setup time SCL rising edge to SDA falling edge both 600 ns crossing 70 of Vcc tup staA START condition hold time From SDA falling edge crossing 30 of Vcc 600 ns to SCL falling edge crossing 70 of Vcc tsu pAr Input data setup time From SDA exiting the 30 to 70 of Vcc 100 ns window to SCL rising edge crossing 30 of Vcc tHD DAT __ Input data hold time From SCL rising edge crossing 70 of Vcc 0 ns to SDA entering the 30 to 70 of Vcc window tsu sto STOP condition setup time From SCL rising edge crossing 70 of Vcc 600 ns to SDA rising edge crossing 30 of Vcc tup sto STOP condition hold time for read or From SDA rising edge to SCL falling edge 600 ns volatile only write both crossing 70 of Vcc Output data hold time From SCL falling edge crossing 30 of Vcc 0 ns Note 15 until SDA enters the 30 to 70 of Vcc window tg SDA and SCL rise time From 30 to 70 of Voc 20 250 ns Note 15 0 1 Cb FN8094 1 4
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intersil ISL90841 handbook