intersil ISL96017 Manual
Contents
1. aoe 6 On power up the SDA pin is in the input mode All as the four MSBs The following three bits are the MSBs of IFC interface operations must begin with a START condition the memory address to be accessed The LSB of the which is a HIGH to LOW transition of SDA while SCL is Identification Byte is the Read Write bit Its value is 1 for a HIGH The device continuously monitors the SDA and SCL Read operation and 0 for a Write operation See Table 2 lines for the START condition and does not respond to any The complete memory address location to be accessed is a command until this condition is met See Figure 6 ASTART 11 bit word since the memory has 2048 bytes The eight condition is ignored during the power up sequence and LSBs are in the Address Byte during internal non volatile write cycles All I2C interface operations must be terminated by a STOP condition which TABLE 2 IDENTIFICATION BYTE FORMAT is a LOW to HIGH transition of SDA while SCL is HIGH See Figure 6 ASTOP condition at the end of a Read operation 0 A10 A8 R Wb oer aw ISF FE conf nt ersi l during a Write operation to a non volatile byte initiates an ZJ A i DATA STABLE DATA CHANGE DATA STABLE i FIGURE 6 VALID DATA CHANGES START AND STOP CONDITIONS 8 intersil FN8243 1 April 17 2006 ISL96017 SCL FROM MASTER TA J i 1 SDA OUTPUT FROM i TRANSMITTER SDA OUTPUT FROM HIGH IMPEDANCE2. LAVE READ s FROM THE A SLAVE A ADDRESS A A aT MASTER R ADDRESS WITH ADDRESS R WITH c c C o T RIWb 0 BYTE T RIWb 1 K K K P AR SIGNAL AT SDA 1010 0 1 R gt SIGNALS FROM Y OS a THE SLAVE FIRST READ e ST READ www BDTI C com ritersi t FIGURE 9 READ SEQUENCE Applications Information The typical application diagram is shown on Figure 10 For proper operation adding 0 1uF decoupling ceramic capacitor to Vdd is recommended The capacitor value may vary based on expected noise frequency of the design Vdd 3 3V Vdd 3 3V Vdd 3 3V 0 1uF Rpu n WP _Vec 0 1uF scL lt Vout SDA NV NM M R2 ISL96017 R1 FIGURE 10 TYPICAL APPLICATION DIAGRAM FOR IMPLEMENTING ADJUSTABLE VOLTAGE REFERANCE 10 intersil FN8243 1 April 17 2006 ISL96017 Thin Dual Flat No Lead Plastic Package TDFN L8 3x3A A 8 LEAD THIN DUAL FLAT NO LEAD PLASTIC PACKAGE MILLIMETERS 0 15 C B SYMBOL MIN NOMINAL MAX NOTES A 0 70 0 75 0 80 z Al 0 02 0 05 A3 0 20 REF p b 0 25 0 30 0 35 5 8 D 3 00 BSC TOP VIEW 5 D2 2 20 2 30 2 40 7 8 9 E 3 00 BSC I ooie E2 1 40 1 50 1 60 7 8 9 y e 0 65 BSC y 0 08 C k 0 25 K _ K C SIDE VIEW a 0 20 0 30 0 40 8 LANE N 8 2 Nd 4 3 Rev 3 11 04 DATUM B NOTES 1 Dimensioning and toleranc
3. OR 10kQ W 0 2 T 25 C 0 15 ie Vpp 3 6V m 0 05 a 77 I o Z 0 05 0 1 0 15 F VDD 3 0V 0 2 1 0 20 40 60 80 100 120 140 TAP POSITION DECIMAL TAP POSITION DECIMAL FIGURE 3 INL vs TAP POSITION FOR 10k2 W FIGURE 4 RDNL vs TAP POSITION FOR 10kQ W 0 4 T 25 C 0 3 Vpp 3 0V la 0 2 T N 0 1 Z 0 a 0 1 0 2 VDD 3 6V 0 3 0 20 40 60 80 100 120 140 TAP POSITION DECIMAL FIGURE 5 RINL vs TAP POSITION FOR 10kQ W 6 intersil FN8243 1 a April 17 2006 ISL96017 Principles of Operation This device combines a DCP 16kbit non volatile memory and an IC serial interface providing direct communication between a host and the DCP and memory DCP Description The DCP has 10kQ or 50kQ nominal total resistance and 128 taps It is implemented with a combination of resistor elements and CMOS switches The physical ends of the DCP the RH and RL pins are equivalent to the fixed terminals of a mechanical potentiometer The RW pin is connected to intermediate nodes and it is equivalent to the wiper terminal of a mechanical potentiometer The position of the wiper terminal within the DCP is controlled by a 7 bit volatile DCP Register When the DCP Register contains all zeroes 00 hex or Ro its wiper terminal RW is closest to its RL terminal When the DCP Register contains all ones 7F hex or R127 its wiper terminal is closest to its RH terminal As the value of the DCP Register
4. PKG PART NUMBER PART MARKING RTotaL KO RANGE C PACKAGE DWG ISL96017WIRT8Z Note 96017WIZ 10 40 to 85 8 Ld 3x3 TDFN Pb free L8 3x3A ISL96017UIRT8Z Note 96017UIZ 50 40 to 85 8 Ld 3x3 TDFN Pb free L8 3x3A Add TK suffix for 1000 units tape and reel NOTE Intersil Pb free plus anneal products employ special Pb free material sets molding compounds die attach materials and 100 matte tin plate termination finish which are ROHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 1 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 1 888 468 3774 Intersil and design is a registered trademark of Intersil Americas Inc Copyright Intersil Americas Inc 2005 All Rights Reserved All other trademarks mentioned are the property of their respective owners ISL96017 Block Diagram Pin Descriptions SDA SCL POWER UP INTERFACE 16kbit EEPROM PIN SYMBOL DESCRIPTION 1 RH High terminal of the DCP 2 nal gy the conterst 4 VDD Power supply 5 GND Ground 6 SDA Open drain serial interface data input output 7 SCL Open drain serial interface clock input 8 WP Hardware write protection pin Active low Prevents any Wr
5. RECEIVER 1 HIGH IMPEDANCE I ACK FIGURE 7 ACKNOWLEDGE RESPONSE FROM RECEIVER Write Operation A Write operation requires a START condition followed by a valid Identification Byte a valid Address Byte one or more Data Bytes and a STOP condition See Figure 8 After each of the bytes this device responds with an ACK At this time if the operation is only writing to volatile registers then the device enters its standby state If one or more Data Bytes are to be written to non volatile memory the device begins its internal write cycle to non volatile memory During this cycle the device ignores transitions at the SDA and SCL pins and the SDA output is at a high impedance state When the internal non volatile write cycle is completed the device enters its standb The memory is or a 8p 16 bytes eden This allows writing 16 bytes on a single 12C interface operation followed by a single internal non volatile write cycle The addresses of bytes within a page share the same eight MSBs and differ on the four LSBs For example the first page is located at addresses 0 hex through F hex the second page is located at addresses 10 hex through 1F hex etc A Write operation with more than one Data Byte sends the first Data Byte to the memory address indicated by the three address bits of the Identification Byte plus the eight bits of the Address Byte the second Data Byte to the following address etc A single Write op
6. VDD V HIGH Voltage VDD 0 3 Hysteresis SDA and SCL Input 0 05 o V WAN BDI C c Lntersi VoL AAA 0 4 V Sinking pj Cpin WP SDA and SCL Pin Capacitance 10 pF scL SCL Frequency 400 kHz tin Pulse Width Suppression Time at Any pulse narrower than the max spec is 50 ns SDA and SCL Inputs suppressed taa SCL Falling Edge to SDA Output SCL falling edge crossing 30 of VDD until 900 ns Data Valid SDA exits the 30 to 70 of VDD window tBUF Time the Bus Must be Free Before SDA crossing 70 of VCC during a STOP 1300 ns the Start of a New Transmission condition to SDA crossing 70 of VDD during the following START condition tLow Clock LOW Time Measured at the 30 of VDD crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70 of VDD crossing 600 ns tsu STA START Condition Setup Time SCL rising edge to SDA falling edge Both 600 ns crossing 70 of VDD tuD STA START Condition Hold Time From SDA falling edge crossing 30 of VDD to 600 ns SCL falling edge crossing 70 of VDD tSU DAT Input Data Setup Time From SDA exiting the 30 to 70 of VDD 100 ns window to SCL rising edge crossing 30 of VDD tHD DAT Input Data Hold Time From SCL rising edge crossing 70 of VDD to 0 ns SDA entering the 30 to 70 of VDD window tsu sTo STOP Condition Setup Time From SCL rising edge crossing 70 of VCC to 600 ns SDA rising edge crossing 30 of VDD FN8243 1 4 intersil April 17 2006 ISL96017 Electrical Specifications Over recommended operating condition
7. bility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com 11 intersil FN8243 1 April 17 2006
8. d 7F hex respectively 10 RDNL R R 1 MI 1 fori from 1 to 111 i is the DCP Register setting 11 RINL R MI i R127 MI for i from 1 to 111 A s R 6 12 Tc Max Ri Min Ri 1x10 fori 1 to 111 and T 40 C to 85 C R Max Ri Min Ri 2 125 C 13 twc is the minimum cycle time to be allowed for any non volatile Write by the user unless Acknowledge Polling is used It is the time from a valid STOP condition at the end of a Write sequence of a 12C serial interface Write operation to the end of the self timed internal non volatile write cycle 14 Parameter is not 100 tested Pc Timing Diagram tr tHIGH tLow tR SCL tsu sTA tsu sTo AR tHD STA SDA INPUT TIMING tBUF SDA OUTPUT TIMING 5 intersil FN8243 1 April 17 2006 ISL96017 Typical Performance Curves 140 T 25 C _ 120 A Vpp 3 6V w 100 9 lt 80 m 5 7 3 n F w 60 z E Vpp 3 0V a m a 40 20 0 0 25 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 TAP POSITION DECIMAL TAP POSITION DECIMAL FIGURE 1 WIPER RESISTANCE vs TAP POSITION FIGURE 2 DNL vs TAP POSITION FOR 10k2 W F
9. e 2 3 W option 5 1 0 LSB ZSerror Zero Scale Error U option 0 1 2 LSB Note 2 4 W option 0 1 5 LSB TCy Ratiometric Temperature DCP Register between 10 hex and 6F hex 4 ppm C Note 7 13 Coefficient DNL Note 2 5 Differential Non Linearity Monotonic over all tap positions 0 75 0 75 LSB INL Note 2 6 Integral Non Linearity 1 1 LSB FN8243 1 April 17 2006 ISL96017 Electrical Specifications Over recommended operating conditions unless otherwise stated All voltages with respect to GND Continued TYP SYMBOL PARAMETER TEST CONDITIONS MIN Note 1 MAX UNIT DCP IN RESISTOR MODE Measurements between RH and RW with RL not connected R127 Note 8 Resistance Offset U version DCP Register set to 7F hex 0 0 5 2 MI Measured between Ry and Rwy pins W version DCP Register set to 7F hex 1 5 MI Measured between Ry and Rw pins TCR Resistance Temperature Coefficient 100 ppm C Note 11 13 RDNL Resistance Differential Non 0 75 0 75 MI Note 8 9 Linearity Note 1 RINL Resistance Integral Non Linearity 1 1 MI Note 8 10 Note 1 EEPROM SPECS EEPROM Endurance 1 000 000 Cycles EEPROM Retention At 55 C 50 Years twc Note 12 Non Volatile Write Cycle Time 6 12 ms SERIAL INTERFACE SPECS VIL WP SDA and SCL Input Buffer 0 3 0 3 V LOW Voltage VDD Vin WP SDA and SCL Input Buffer 0 7
10. en directly using the 12C serial interface with Address Byte 07FF hex The MSB of the byte at address 7FE hex is called OnlyVolatile and controls the access to the DCP Register and IVR This bit is volatile and it s reset to O at power up The Data Byte read from memory address 7FF hex is from the DCP register when the OnlyVolatile bit is 1 and from the IVR when this bit is O The Data Byte of a Write operation to memory address 7FF hex is written only to the DCP Register when the OnlyVolatile bit is 1 and it s written to both the DCP Register and the IVR when this bit is O When writing to the OnlyVolatile bit at address 7FE hex the seven LSBs of the Data Byte must be all zeros Writing to address 7FE hex and 7FF hex can be done in two Write Tn ters Write operation il two Data See next sections for er Sl description TABLE 1 1SL96017 MEMORY MAP Address Data Bits Function e Address Data Bits Function Pe ae __ 7rEn ov o o o o o o o Access conri Fi Reserved Reserved 7FChI 7een 0 Ds bs 0 D Dz D Da General Purpose Memory Note OV Only Volatile All other bits in register 7FEh must be 0 7 intersil FN8243 1 April 17 2006 ISL96017 PC Serial Interface internal non volatile write cycle The device enters its This device supports a bidirectional bus oriented protocol standby state
11. eration has to stay within a page If the Address Byte corresponds to the lowest address of a page then the Write operation can have anywhere from 1 to 16 Data Bytes If the Address Byte corresponds to the highest address of a page then only one byte can be written with that Write operation See Access to DCP Register and IVR for additional information Data Protection The WP pin has to be at logic HIGH to perform any Write Operation to the device When WP is active LOW the device ignores Data Bytes of a Write operation does not respond to them with ACK and instead goes to its standby state waiting for anew START condition A valid Identification Byte Address Byte and total number of SCL pulses act as a protection of both volatile and non volatile registers During a Write sequence Data Bytes are loaded into an internal shift register as they are received If the address bits in the Identification Byte plus the bits in the Address Byte are all ones the Data Byte is transferred to the DCP Register at the falling edge of the SCL pulse that loads the last bit LSB of the Data Byte e C O of co HR g tionlof non volatile e Ronso i vi cle are started by STOP conditions Read Operation A Read operation consist of a three byte instruction followed by one or more Data Bytes See Figure 9 The master initiates the operation issuing the following sequence a START the Identification Byte with the R W bit set
12. increases from all zeroes to all ones the wiper moves monotonically from the position closest to RL to the closest to RH Therefore the resistance between RH and RW decreases monotonically from Rg to R127 while the resistance between RW and RL increases monotonically from R127 to Ro While the device is being powered up the DCP Register is reset to 40 hex 64 decimal Soon after the power supply voltage becomes large enough for ge D hla latil EFK C Ads it Memory Description memory reading j ds ne pep non volatile Initial Wal ister I This device contains 2048 non volatile bytes organized in DCP Register 128 pages of 16 bytes each This allows writing 16 bytes on a single 12C interface operation followed by a single internal non volatile write cycle The memory is accessed by 12C interface operations with addresses 000 hex through 7FF hex Bytes at addresses 000 hex through 7FB hex are available to the user as general purpose memory The byte at address 7FF hex IVR contains the initial value loaded at power up into the volatile DCP Register The byte at address 7FE hex controls the access to the DCP byte See Access to DCP Register and IVR Bytes at addresses 7FC hex and 7FD hex are reserved which means that they should not be written and their value should be ignored if they are read See Table 1 Access to DCP Register and IVR The volatile DCP Register and the non volatile IVR can be read or writt
13. ing conform to ASME Y14 5 1994 Nis the number of terminals 2 INDEX 3 Nd refers to the number of terminals on D 4 AREA apa ate in millimeters Angles in degrees enbion Wallies etKli ef terminal and is measured edn 0 15 n he t minal tip 6 The configuration of the pin 1 identifier is optional but must be located within the zone indicated The pin 1 identifier may be either a mold or mark feature 7 Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance DATUM A M r 4 0 10 fn c a s 8 Nominal dimensions are provided to assist with PCB Land Pattern Design efforts see Intersil Technical Brief TB389 9 Compliant to JEDEC MO WEEC 2 except for the L min dimension BOTTOM VIEW SECTION C C TERMINAL TIP FOR EVEN TERMINAL SIDE All Intersil U S products are manufactured assembled and tested utilizing ISO9000 quality systems Intersil Corporation s quality certifications can be viewed at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsi
14. intersil ISL96017 Data Sheet April 17 2006 FN8243 1 128 Tap DCP 16kbit EEPROM and Pc Features Serial Interface Integrated Digitally Controlled Potentiometer This device integrates a 128 tap digitally controlled 128 Tap Positions potentiometer 16kbit of EEPROM and a 2 wire 12C serial 10kQ 50kQ Total Resistance interface The device is powered by a single 3 3V supply Monotonic Over Temperature The potentiometer is available with total resistance of either Non Volatile Wiper Position Storage 10kQ or 50kQ Oto VDD Terminal Voltage The memory is organized in 128 pages of 16 bytes each to reduce total programming time All programming signals are generated on chip e 16kbit EEPROM 50 Years Retention lt 55 C 1 000 000 Cycles Endurance 12C Serial Interface The potentiometer is implemented with a combination of CMOS switches and resistor elements The position of the wiper can be stored in non volatile memory and then be Single 3 3 0 3V Supply recalled upon a subsequent power up The three terminals 3mm x 3mm Thin DFN Package 0 8mm Max Thickness of the potentiometer are available for use as either a variable 0 65mm Pitch resistor or a resistor divider Pb Free Plus Anneal Available ROHS Compliant Pinout ISL96017 8 LD TDFN TOP VIEW BDTI C com I ntersi ee SCL 6 SDA VDD 45 5 GND Ordering Information TEMP
15. ite operation to the device 2 intersil FN8243 1 April 17 2006 ISL96017 Absolute Maximum Ratings Thermal Information Storage Temperature 2 0 0 65 C to 150 C Thermal Resistance Typical Note 1 OJA Note All Voltages with Respect to GND 8 Ld TDFN Package 00 90 C W Voltage at SCL SDA WP 2 eee slan 0 3V to 4V Moisture Sensitivity see Technical Brief TB363 Level 2 Voltage at RH RW RL 1 eee eee GND to VDD Maximum Junction Temperature Plastic Package 150 C VOD RE a ar 0 3V to 4V Lead Temperature Soldering 10s 300 C Recommended Operating Conditions WDE CON wales i agna a a ahe rakd Z6MA Ambient Temperature eee eee 40 C to 85 C ESD MIL STD 882B M thod 3014 twat as ate as ni gt 2000V VDD Voltage for DCP Operation 3 0V to 3 6V a gt T90V Wiper Current 1 1 212122kak kakak aaa 3mA to 3mA Power Rating e caigan eta deve ae gia eee Alaa 5mWw CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 1 Oja is measu
16. red in free air with the component mounted on a high effective thermal conductivity test board with direct attach features See Tech Brief TB379 for details Electrical Specifications Over recommended operating conditions unless otherwise stated All voltages with respect to GND 3 intersil TYP SYMBOL PARAMETER TEST CONDITIONS MIN Note 1 MAX UNIT IccdSby Standby Current at VDD Serial interface in standby 10 pA IccdRd Read Current at VDD Reading with 400kHz at SCL 1 mA IccdWr Write Current at VDD Writing to EEPROM 5 mA ILkgDig Leakage Current at Pins SDA SCL Pin voltage from GND to VDD 10 10 HA and WP Q Manor ANAL recom ter S1 VDDRamp V V ms tpcp DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to 1 5 us Note 13 wiper change tp Power Up Delay VDD above 2 6V to DCP Initial Value Register 3 ms recall completed and 12C Interface in standby state CH CW CL RH RW RL Pin Capacitance 10 pF Note 13 RTotal Total Resistance W and U versions respectively Ta 25 C 10 50 kQ Measured between Ry and R pins Rtota Tolerance Ta 25 C Measured between Ry and R pins 20 20 Rwiper Wiper Resistance Vpp 3 3V 25 C Wiper current Vpp R Total 100 300 Q DCP Resolution 7 Bits DCP IN VOLTAGE DIVIDER MODE OV at RL VCC at RH measured at RW unloaded FSerror Full Scale Error U option 2 1 0 LSB Not
17. s unless otherwise stated All voltages with respect to GND Continued TYP SYMBOL PARAMETER TEST CONDITIONS MIN Note 1 MAX UNIT HD STO STOP Condition Hold Time From SDA rising edge to SCL falling edge Both 600 ns crossing 70 of VDD tDH Output Data Hold Time From SCL falling edge crossing 30 of VDD 0 ns until SDA enters the 30 to 70 of VDD window tr SDA and SCL Rise Time From 30 to 70 of VDD 20 250 ns 0 1 Cb te SDA and SCL Fall Time From 70 to 30 of VDD 20 250 ns 0 1 Cb Cb Capacitive Loading of SDA or SCL Total on chip and off chip 10 400 pF Rpu SDA and SCL Bus Pull Up Resistor Maximum is determined by tr and tf 1 kQ Off Chip For Cb 400pF max is about 2 2 5kQ For Cb 40pF max is about 15 20kQ tsu WP WP Setup Time Before START condition 600 ns tup we WP Hold Time After STOP condition 600 ns NOTES 2 Typical values are for TA 25 C and Vpp 3 3V 3 LSB V RW 127 V RW 9 127 V RW 127 and V RW are the voltage at pin RW for the DCP Register set to 7F hex and 00 hex respectively 4 FSerror V RW 127 VDD LSB 5 ZSerror V RW o LSB 6 DNL V RW V RW i 1 LSB 1 for i from 1 to 127 i is the DCP Register setting 7 INL V RW i LSB V RW o 127 P 6 LE C Gondlatersi 25 C 9 MI R R127 127 MI is minimum increment Rg and R1727 are the resistances between RH and RW with the DCP Register set to 00 hex an
18. to 0 an Address Byte which contains the LSBs of the memory address a second START and a second Identification Byte with the same address bits but with the R W bit set to 1 After each of the three bytes this device responds with an ACK Then this device transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte The master terminates the Read operation issuing a STOP condition following the last bit of the last Data Byte The Data Bytes are from the memory location indicated by an internal pointer This pointer initial value is determined by the address bits in the Identification Byte plus the bits in the Address Byte in the Read operation instruction and increments by one during transmission of each Data Byte 9 intersil FN8243 1 April 17 2006 ISL96017 WRITE s SIGNALS FROM T s THE MASTER lt I R SLAVE ADDRESS FIRST DATA BYTE LAST DATA BYTE T ADDRESS BYTE TO WRITE TO WRITE P gt Jk AK Y f SIGNAL AT SDA 1010 0 SIGNALS FROM A A gt A A THE SLAVE lt c c c c K K K K FIGURE 8 WRITE SEQUENCE s s SIGNALS T T S
19. when the internal non volatile write cycle is The protocol defines any device that sends data onto the completed bus as a transmitter and the receiving device as the receiver An ACK Acknowledge is a software convention used to The device controlling the transfer is a master and the indicate a successful data transfer The transmitting device device being controlled is the slave The master always either master or slave releases the SDA bus after initiates data transfers and provides the clock for both transmitting eight bits During the ninth clock cycle the transmit and receive operations Therefore this device receiver pulls the SDA line LOW to acknowledge the operates as a slave device in all applications All reception of the eight bits of data See Figure 7 This device communication over the IC interface is conducted by responds with an ACK after recognition of a START sending the MSB of each byte of data first condition followed by a valid Identification Byte and once again after successful receipt of the Address Byte This device also responds with an ACK after receiving each Data Byte of a Write operation The master must respond with an Protocol Conventions Data states on the SDA line can change only during SCL LOW periods SDA state changes during SCL HIGH are ACK after receiving each Data Byte of a read operation reserved for indicating START and STOP conditions See except the last one A valid Identification Byte contains 1010
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intersil ISL96017 Manual