ATMEL AT88SC3216C handbook
Contents
1. 0 022 0 045 0 060 0 070 0 030 0 039 0 045 0 008 0 010 0 014 0 355 0 365 0 400 eve 0 005 0 300 0 310 0 325 0 240 0 250 0 280 Side View 0 100 BSC 0 300 BSC 0 115 0 130 t bh This drawing is for general information only refer to JEDEC Drawing MS 001 Variation BA for additional information Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS 3 D D1 and E1 dimensions do not include mold Flash or protrusions Mold Flash or protrusions shall not exceed 0 010 inch E and eA measured with the leads constrained to be perpendicular to datum Pointed or rounded lead tips are preferred to ease insertion b2 and b3 maximum dimensions do not include Dambar protrusions Dambar protrusions shall not exceed 0 010 0 25 mm 01 09 02 TITLE DRAWING NO REV MEL 2325 Orchard Parkway 8P3 8 lead 0 300 Wide Body Plastic Dual AIMEL San Jose CA 95131 In line Package PDIP ore B 16 AT88SC3216C 5014JS SMEM 02 09 ees 1 88S C32 16C Revision History Doc Rev Date Comments 5014JS 02 09 Features Section add Green compliant exceeds RoHS to end of Standard 8 lead Plastic Packages bullet added Note to DC Characteristics table and applied to Vcc and all 3 instances of Vinh symbols in table Ordering Information page A2. by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life 2009 Atmel Corporation All rights reserved Atmel Atmel logo and combin
3. 0 15 V loH SDA IO Output High Current Vou 20 uA Notes 1 VIL min and VIH max are reference only and are not tested 2 To prevent Latch Up Conditions from occurring during Power Up of the AT88SCxxxxC Vcc must be turned on before apply ing Vih For Powering Down Vih must be removed before turning vcc off 5014JS SMEM 02 09 AMEL 3 AMEL Table 3 AC Characteristics Applicable over recommended operating range from Vec 2 7 to 5 5V Tac 40 C to 85 C CL 30pF unless otherwise noted Symbol Parameter Min Max Units fok Async Clock Frequency Vec Range 4 5 5 5V 1 5 MHz foLk Async Clock Frequency Vcc Range 2 7 3 3V 1 4 MHz foik Synch Clock Frequency 0 1 MHz Clock Duty cycle 40 60 tR Rise Time I O RST 1 uS te Fall Time I O RST 1 uS tR Rise Time CLK 9 x period uS te Fall Time CLK 9 x period uS taa Clock Low to Data Out Valid 35 nS tuosta Start Hold Time 200 ns tsysta Start Set up Time 200 ns tup par Data In Hold Time 10 nS tsupar Data In Set up Time 100 nS tsu sro Stop Set up Time 200 nS toy Data Out Hold Time 20 ns twr Write Cycle Time at 25 C 5 mS twr Write Cycle Time 40 to 85 C 7 mS Device CLOCK and DATA TRANSITIONS The SDA pin is normally pulled high with an external device Operation For Data on the SDA pin may change only during SCL low time periods see Figure 5 on page 5 Data changes during SCL
4. 13 Password and Authentication Operations Device Card Host Reader AUTHENTICATION Card Number gt COMPUTE Challenge A VerifyA lt Challenge A COMPUTE Challenge B l Challenge B gt VERIFY B READ ACCESS VERIFY RPW Read Password RPW DATA gt Checksum CS gt VERIFY CS WRITE ACCESS VERIFY WPW lt Write Password WPW lt DATA VERIFY CS CS Write DATA AMEL n Checksum Encryption Supervisor Mode Modify Forbidden Program Only Initial Device Programming AMEL The AT88SC3216C implements a data validity check function in the form of a checksum which may function in standard authentication or encryption modes In the standard mode the checksum is implemented as a Modification Detection Code MDC in which the host may read a MDC from the device in order to verify that the data sent was received correctly In the authentication and encryption modes the checksum becomes more powerful since it pro vides a bidirectional data integrity check and data origin authentication capability in the form of a Message Authentication Code MAC Only the host device that carried out a valid authentica tion is capable of computing a valid MAC While operating in the authentication or encryption modes the use of a MAC is required For an ongoing command if the device calculates a MAC different from the MAC transmitted by the host not only is the command abando
5. CLK input is used to provide the device with a car rier frequency f The nominal length of one bit emitted on I O is defined as an elementary time unit ETU and is equal to 372 f When the synchronous protocol is used the SCL CLK input is used to positive edge clock data into the device and negative edge clock data out of the device 5014JS SMEM 02 09 ees T 8S C32 16C Reset RST Serial Data SDA IO The AT88SC3216C provides an ISO 7816 3 compliant asynchronous answer to reset sequence When the reset sequence is activated the device will output the data programmed into the 64 bit answer to reset register An internal pull up on the RST input pad allows the device to be used in synchronous mode without bonding RST The AT88SC3216C does not support the synchronous answer to reset sequence The SDA pin is bidirectional for serial data transfer This pin is open drain driven and may be wired with any number of other open drain or open collector devices An external pull up resistor should be connected between SDA and Vec The value of this resistor and the system capaci tance loading the SDA bus will determine the rise time of SDA This rise time will determine the maximum frequency during read operations Low value pull up resistors will allow higher fre quency operations while drawing higher average power SDA IO information applies to both asynchronous and synchronous protocols When the synchronous protocol is used the SCL
6. from a valid stop condition of a write sequence to the end of DATA CHANGE ALLOWED AMEL Figure 6 Start and Stop Definitions Figure 7 Output Acknowledge oan XX DATA OUT B f START ACKNOWLEDGE Device Architecture User Zones The EEPROM user memory is divided into 16 zones of 2 048 bits each Multiple zones allow for different types of data or files to be stored in different zones Access to the user zones is allowed only after security requirements have been met These security requirements are defined by the user during the personalization of the device in the configuration memory If the same security requirements are selected for multiple zones then these zones may effectively be accessed as one larger zone 5014JS SMEM 02 09 ees 18 8S C32 16C Figure 8 User Zone User 14 User 15 Control Logic Access to the user zones occurs only through the control logic built into the device This logic is configurable through access registers key registers and keys programmed into the configuration memory during device personalization Also implemented in the control logic is a cryptographic engine for performing the various higher level security functions of the device Configuration The configuration memory consists of 2048 bits of EEPROM memory used for storing pass Memory words keys and codes and defining security levels to be used for each user
7. to the configuration memory the secure code must first be successfully presented For the AT88SC3216C device the secure code is CB 28 50 After writing and veri fying data in the configuration memory the security fuses must be blown to lock this information in the device For additional information on personalizing CryptoMemory please see the appli cation notes Programming CryptoMemory for Embedded Applications and Initializing CryptoMemory for Smart Card Applications at www Atmel com 12 AT88SC321 6 C memme 5014JS SMEM 02 09 ees T 8S C32 16C Ordering Information Ordering Code Package Voltage Range Temperature Range AT88SC3216C MJ M2 J Module 2 7V 5 5V Commercial 0 C 70 C AT88SC3216C PU 8P3 2 7V 5 5V Green compliant exceeds AT88SC3216C SU 8S1 RoHS Industrial 40 C 85 C AT88SC3216C WI 7 mil wafer 2 7V 5 5V Industrial 40 C 85 C Package Type Description M2 J Module M2 ISO 7816 Smart Card Module 8P3 8 lead 0 300 Wide Plastic Dual Inline Package PDIP 8S1 8 lead 0 150 Wide Plastic Gull Wing Small Outline Package JEDEC SOIC Note 1 Formal drawings may be obtained from an Atmel sales office 5014JS SMEM 02 09 AMEL 13 Packaging Information Ordering Code MJ a a Module Size M2 Dimension 12 6 x 11 4 mm Glob Top Round O 8 5 mm Thickness 0 58 mm A Pitch 14 25 mm
8. CLK input is used to positive edge clock data into the device and negative edge clock data out of the device Table 2 DC Characteristics Applicable over recommended operating range from Vec 2 7 to 5 5V Tac 40 C to 85 C unless otherwise noted Symbol Parameter Test Condition Min Typ Max Units Voce Supply Voltage 2 7 5 5 vV lcc Supply Current Vec 5 5V Async READ at 3 57MHz 5 mA loc Supply Current Voc 5 5V Async WRITE at 3 57MHz 5 mA loc Supply Current Vec 5 5V Synch READ at 1MHz 5 mA loc Supply Current Vec 5 5V Synch WRITE at 1MHz 5 mA Isp Standby Current Vec 5 5V Vin Voc or GND 1 mA vy SDA IO Input Low Threshold 0 Voc X 0 2 V Vi SCL CLK Input Low Threshold 0 Voc x 0 2 V vy RST Input Low Threshold 0 Voc X 0 2 V VOA SDA IO Input High Threshold Voc X 0 7 Voc V Vy SCL CLK Input High Threshold Voc X 0 7 Vec V VOA RST Input High Threshold Vcc X 0 7 Vcc V lit SDA IO Input Low Current 0 lt V lt Vec x 0 15 15 uA lit SCL CLK Input Low Current 0 lt V lt Vec X 0 15 15 uA li RST Input Low Current O lt V lt Vec x 0 15 50 uA lH SDA IO Input High Current Voc X 0 7 lt Vin lt Vec 20 uA lH SCL CLK Input High Current Vec X 0 7 lt Vin lt Vec 100 uA liq RST Input High Current Vec X 0 7 lt Vin lt Veo 150 uA Vou SDA IO Output High Voltage 20K ohm external pull up Voc X 0 7 Voc V VoL SDA IO Output Low Voltage lo 1MA 0 Voc X
9. Features e One of a Family of 9 Devices with User Memories from 1 Kbit to 256 Kbit e 32 Kbit 4 Kbyte EEPROM User Memory Sixteen 256 byte 2 Kbit Zones Self timed Write Cycle Single Byte or 128 byte Page Write Mode Programmable Access Rights for Each Zone e 2 Kbit Configuration Zone 37 byte OTP Area for User defined Codes 160 byte Area for User defined Keys and Passwords e High Security Features 64 bit Mutual Authentication Protocol Under License of ELVA Encrypted Checksum Stream Encryption Four Key Sets for Authentication and Encryption Eight Sets of Two 24 bit Passwords Anti tearing Function Voltage and Frequency Monitor Smart Card Features ISO 7816 Class A 5V or Class B 3V Operation ISO 7816 3 Asynchronous T 0 Protocol Gemplus Patent Supports Protocol and Parameters Selection for Faster Operation Multiple Zones Key Sets and Passwords for Multi application Use Synchronous 2 wire Serial Interface for Faster Device Initialization Programmable 8 byte Answer to reset Register ISO 7816 2 Compliant Modules Embedded Application Features Low Voltage Operation 2 7V to 5 5V Secure Nonvolatile Storage for Sensitive System or User Information 2 wire Serial Interface 1 0 MHz Compatibility for Fast Operation Standard 8 lead Plastic Packages Green Compliant exceeds RoHS Same Pinout as 2 wire Serial EEPROM
10. Note The module dimensions listed refer to the dimensions of the exposed metal contact area The actual dimensions of the module after excise or punching from the carrier tape are generally 0 4 mm greater in both directions i e a punched M2 module will yield 13 0 x 11 8 mm 14 AT88SC321 6 C memme 5014JS SMEM 02 09 AT88SC3216C Ordering Code SU 8 lead SOIC TOP VIEW END VIEW COMMON DIMENSIONS Unit of Measure mm MIN NOM MAX NOTE 1 35 1 75 a eae Tlos _ b 0 31 0 51 0 25 D 5 05 3 99 6 20 SIDE VIEW Note These drawings are for general information only Refer to JEDEC Drawing MS 012 Variation AA for proper dimensions tolerances datums etc 3 17 05 MEL E Ch Min Biva 891 84 d Wide Body Plastic Gull W eee joe 1150 E Cheyenne Min Blvd 8 lead 0 150 Wide Body Plastic Gull Wing AIMEE colorado Springs CO 80906 Small Outline JEDEC SOIC 8S1 C AMEL 1s 5014JS SMEM 02 09 AMEL Ordering Code PU 8 lead PDIP Z he Re H N Top View eg fe End View COMMON DIMENSIONS Unit of Measure inches SYMBOL MIN NOM MAX 0 210 0 115 0 130 0 195 0 014 0 018
11. ations thereof CryptoMemory and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of others 5014JS SMEM 02 09
12. c and symmetric mutual authentication between the device and host as well as perform ing stream encryption for all data and passwords exchanged between the device and host Up to four unique key sets may be used for these operations The AT88SC3216C offers the ability to communicate with virtually any smart card reader using the asynchronous T 0 protocol Gem plus Patent defined in ISO 7816 3 Communication speeds up to 153 600 baud are supported by utilizing ISO 7816 3 Protocol and Parameter Selection Through dynamic and symmetric mutual authentication data encryption and the use of encrypted checksums the AT88SC3216C provides a secure place for storage of sensitive infor mation within a system With its tamper detection circuits this information remains safe even under attack A 2 wire serial interface running at 1 0 MHz is used for fast and efficient communi cations with up to 15 devices that may be individually addressed The AT88SC3216C is available in industry standard 8 lead packages with the same familiar pinout as 2 wire serial EEPROMs Figure 2 Block Diagram Authentication Encryption and Certification Unit Random Generator VCC Power GND Management Data Transfer SCL CLK Asynchronous Password SDA IO 4 ISO interface ope RST Reset Block Answer to Reset Supply Voltage Vcc The Vec input is a 2 7V to 5 5V positive voltage supplied by the host Clock SCL CLK In the asynchronous T 0 protocol the SCL
13. dd Green compliant exceeds RoHS to middle row of Temperature Range Replace Lead free Halogen free Keep industrial Updated to 2009 Copyright 50141S 1 2009 Removed P module offering 5014HS 11 2008 Updated timing diagrams 5014GS 4 2007 Final release version 5014GS 1 26 07 Replaced User Zone Configuration Memory and Write Lock Example tables with new information 5014GS 1 2007 Implemented revision history Removed Industrial package offerings Removed 8Y4 package offering AMEL 17 5014JS SMEM 02 09 AIMEL T O Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Product Contact Web Site www atmel com Atmel Europe Le Krebs 8 Rue Jean Pierre Timbaud BP 309 78054 Saint Quentin en Yvelines Cedex France Tel 33 1 30 60 70 00 Fax 33 1 30 60 71 11 Technical Support securemem atmel com Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Sales Contact www atmel com contacts Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied
14. e default after powering up Vcc due to an internal pull up on RST For embedded applications using CryptoMemory in standard plastic packages this is the only communication protocol e Power up Voc RST goes high also e After stable Voc CLK SCL and I O SDA may be driven AMEL o AMEL Figure 11 Synchronous 2 wire Protocol O SDA _ i RST _1 CLK SCL __ tL fel fal j4__fs L J LJ Note Five clock pulses must be sent before the first command is issued Communication Communications between the device and host operate in three basic modes Standard mode is Security Modes the default mode for the device after power up Authentication mode is activated by a successful authentication sequence Encryption mode is activated by a successful encryption activation fol lowing a successful authentication Table 4 Communication Security Modes Configuration Data User Data Passwords Data Integrity Check Standard Clear Clear Authentication Clear Encrypted Encryption Encrypted Encrypted Note 1 Configuration data include viewable areas of the Configuration Zone except the passwords MDC Modification Detection Code MAC Message Authentication Code Security Options Anti tearing In the event of a power loss during a write cycle the integrity of the device s stored data may be recovered This function is optiona
15. high periods will indicate a start or stop condition as defined below Synchronous T START CONDITION A high to low transition of SDA with SCL high is a start condition which Protocols must precede any other command see Figure 6 on page 6 STOP CONDITION A low to high transition of SDA with SCL high is a stop condition After a read sequence the stop command will place the EEPROM in a standby power mode see Fig ure 6 on page 6 ACKNOWLEDGE All addresses and data words are serially transmitted to and from the EEPROM in 8 bit words The EEPROM sends a zero to acknowledge that it has received each word This happens during the ninth clock cycle MEMORY RESET After an interruption in protocol power loss or system reset any 2 wire part can be reset by following these steps 1 Clock up to 9 cycles 2 Look for SDA high in each cycle while SCL is high 3 Create a start condition 4 AT88S C321 6 C memm Figure 3 Bus Timing for 2 wire communications SCL Serial Clock SDA Serial Data I O SCL SDA IN SDA OUT tup sta Figure 4 Write Cycle Timing SCL Serial Clock SDA Serial Data I O 8th BIT ACK Figure 5 Data Validity 5014JS SMEM 02 09 WORDn Note tup pat lt _ t STOP CONDITION WR the internal clear write cycle tsu pat tou O y START CONDITION SDA AT88SC3216C tsu sto taur The write cycle time twp is the time
16. ications The asynchronous T 0 protocol defined by ISO 7816 3 is used for compatibility with the industry s standard smart card readers e Embedded Applications A 2 wire serial interface is used for fast and efficient communication with logic or controllers The power up sequence determines which of the two communication protocols will be used This power up sequence complies with ISO 7816 3 for a cold reset in smart card applications e Voc goes high RST I O SDA and CLK SCL are low e Set I O SDA in receive mode e Provide a clock signal to CLK SCL e RST goes high after 400 clock cycles The device will respond with a 64 bit ATR code including historical bytes to indicate the memory density within the CryptoMemory family Once the asynchronous mode has been selected it is not possible to switch to the synchronous mode without powering off the device Figure 10 Asynchronous T 0 Protocol Gemplus Patent Voc 1 O SDA ATR RST cu scl EET After a successful ATR the Protocol and Parameter Selection PPS protocol as defined by ISO 7816 3 may be used to negotiate the communications speed with CryptoMemory devices 32 Kbits and larger CryptoMemory supports D values of 1 2 4 8 12 and 16 for an F value of 372 Also supported are D values of 8 and 16 for F 512 This allows selection of 8 communications speeds ranging from 9600 baud to 153 600 baud The synchronous mode is th
17. l the host may choose to activate the anti tearing function depending on application requirements When anti tearing is active write commands take longer to execute since more write cycles are required to complete them and data are limited to eight bytes Data are written first to a buffer zone in EEPROM instead of the intended destination address but with the same access conditions The data are then written in the required location If this second write cycle is interrupted due to a power loss the device will automatically recover the data from the system buffer zone at the next power up In 2 wire mode the host is required to perform ACK polling for up to 8 ms after write commands when anti tearing is active At power up the host is required to perform ACK polling in some cases for up to 2 ms in the event that the device needs to carry out the data recovery process Write Lock If a user zone is configured in the write lock mode the lowest address byte of an 8 byte page constitutes a write access byte for the bytes of that page Example The write lock byte at 080 controls the bytes from 080 to 087 10 AT88SC321 6 C memme AT88SC3216C Figure 12 Write Lock Example Address so ste XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 080 11011001 Password Verification Authentication Protocol 5014JS SMEM 02 09 locked locked locked The write lock byte may also be locked by w
18. ned but the mode is also reset A new authentication and or encryption activation will be required to reacti vate the MAC The data exchanged between the device and the host during read write and verify password commands may be encrypted to ensure data confidentiality The issuer may choose to require encryption for a user zone by settings made in the configura tion memory Any one of four keys may be selected for use with a user zone In this case activation of the encryption mode is required in order to read write data in the zone and only encrypted data will be transmitted Even if not required the host may elect to activate encryption provided the proper keys are known Enabling this feature allows the holder of one specific password to gain full access to all eight password sets including the ability to change passwords No write access is allowed in a user zone protected with this feature at any time The user zone must be written during device personalization prior to blowing the security fuses For a user zone protected by this feature data within the zone may be changed from a 1 toa 0 but never from a 0 to a 1 To enable the security features of CryptoMemory the device must first be personalized to set up several registers and load in the appropriate passwords and keys This is accomplished through programming the configuration memory of CryptoMemory using simple write and read com mands To gain access
19. riting its least significant rightmost bit to O More over when write lock mode is activated the write lock byte can only be programmed that is bits written to O cannot return to 1 In the write lock configuration only one byte can be written at a time Even if several bytes are received only the first byte will be taken into account by the device Passwords may be used to protect read and or write access of any user zone When a valid password is presented it is memorized and active until power is turned off unless a new pass word is presented or RST becomes active There are eight password sets that may be used to protect any user zone Only one password is active at a time but write passwords give read access also The access to a user zone may be protected by an authentication protocol Any one of four keys may be selected to use with a user zone The authentication success is memorized and active as long as the chip is powered unless a new authentication is initialized or RST becomes active If the new authentication request is not validated the card loses its previous authentication and it should be presented again Only the last request is memorized Note Password and authentication may be presented at any time and in any order If the trials limit has been reached after four consecutive incorrect attempts the password verification or authentica tion process will not be taken into account Figure
20. s e High Reliability Endurance 100 000 Cycles Data Retention 10 years ESD Protection 4 000V min Table 1 Pin Configuration Pad Description ISO Module Contact Standard Package Pin VCC Supply Voltage C1 8 GND Ground C5 4 SCL CLK Serial Clock Input C3 6 SDA IO Serial Data Input Output C7 5 RST Reset Input C2 NC Figure 1 Package Options Smart Card Module 8 lead SOIC PDIP VCC C1 C5 GND NC i 8 VOC RST C2 C6 NC G 5 7 ne SCL CLK C3 C7 SDA IO NC C4 C8 NC 3 6 ISGL GND _ 4 5 ISDA AMEL T O CryptoMemory 32 Kbit AT88SC3216C Summary Rev 5014JS SMEM 02 09 Note This is a summary document A complete document is available under NDA For more information please contact your local Atmel sales office Description Smart Card Applications Embedded Applications Pin Descriptions AMEL The AT88SC3216C member of the CryptoMemory family is a high performance secure mem ory providing 32 Kbits of user memory with advanced security and cryptographic features built in The user memory is divided into 16 256 byte zones each of which may be individually set with different security access rights or effectively combined together to provide space for 1 to 16 data files The AT88SC3216C provides high security low cost and ease of implementation without the need for a microprocessor operating system The embedded cryptographic engine provides for dynami
21. zone Access rights to the configuration memory are defined in the control logic and may not be altered by the user AMEL 7 5014JS SMEM 02 09 Figure 9 Configuration Memory AMEL EEEa Answer To Reset 00 08 Fab Code MTZ Lot History Code Card Manufacturer Code Identification Number Nc PRI AR2 PR2 AR3 PR5 AR6 PR6 AR7 PR AR10 PR10 AR11 PR13 AR14 PR14 AR15 Write 0 Issuer Code For Authentication and Encryption use For Authentication and Encryption use Write 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write 7 Reserved Identification Read Only Access Control Cryptography Password Forbidden 8 AT88SC321 6 C cms 5014JS SMEM 02 09 ees T 8S C32 16C Security Fuses Protocol Selection Asynchronous T 0 Protocol Synchronous 2 wire Serial Interface 5014JS SMEM 02 09 There are three fuses on the device that must be blown during the device personalization pro cess Each fuse locks certain portions of the configuration memory as OTP memory Fuses are designed for the module manufacturer card manufacturer and card issuer and should be blown in sequence although all programming of the device and blowing of the fuses may be performed at one final step The AT88SC3216C supports two different communication protocols e Smart Card Appl
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ATMEL AT88SC3216C handbook