ATMEL AT24C64A handbook
Contents
1. MSB LSB Figure 8 Byte Write S w T R S A T R DEVICE T FIRST SECOND O T ADDRESS E VVORD ADDRESS WORD ADDRESS DATA P SDA LINE xox M LRA M A LA A S s c S G Sc c B BW K B K BK Figure 9 Page Write S Ww T R S A l T R DEVICE T FIRST SECOND o T ADDRESS E WORD ADDRESS n WORD ADDRESS n DATA n N DATA n x P T SDA LINE 5 Wa M LRA A A ANAL A S S C C C C C B BW K K K K Notes 1 DON T CARE bits 2 t DON T CARE bits for the 32K Figure 10 Current Address Read S T R S A E T R DEVICE A T ADDRESS D P SDA LINE M LRA DATA N S s c O B BW K A C K AMEL n 5120D SEEPR 6 08 AMEL Figure 11 Random Read s 4 ist 2nd WORD R S i R A l ADDRESS n A DEVICE E T R DEVICE T R ADDRESS A o T ADDRESS E N T D P T SDA LINE 75 Z M LRA A A DATA n N S s c C C O B BW K K K A C DUMMY WRITE K Note 1 DON CARE bits Figure 12 Sequential Read R S E A A A T DEVICE A C C C o A2. DATA IN DATA OUT START ACKNOWLEDGE mms AT24C32A 64A Device Addressing Write Operations 5120D SEEPR 6 08 The 32K 64K EEPROM requires an 8 bit device address word following a start condition to enable the chip for a read or write operation see Figure 7 on page 11 The device address word consists of a mandatory one zero sequence for the first four most significant bits as shown This is common to all 2 wire EEPROM devices The 32K 64K uses the three device address bits A2 A1 AO to allow as many as eight devices on the same bus These bits must compare to their corresponding hardwired input pins The A2 A1 and AO pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float The eighth bit of the device address is the read write operation select bit A read operation is ini tiated if this bit is high and a write operation is initiated if this bit is low Upon a compare of the device address the EEPROM will output a zero If a compare is not made the device will return to standby state NOISE PROTECTION Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from activating the device DATA SECURITY The AT24C32A 64A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at Voc BYTE WRITE A write operation requires two 8 bit data word addresses following the device addre
3. SOIC 7 fe o END VIEW TOP VIEW COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN MAX 1 35 1 75 D SIDE VIEVV 1 27 BSC Note These drawings are for general information only Refer to JEDEC Drawing MS 012 Variation AA for proper dimensions tolerances datums etc 3 17 05 IMEL E Ch Mtn Blvd 8S1 8 1 d 0 150 Wide Body PI Gull W l eee 1150 E Cheyenne Mtn Blvd 8 lead 0 150 Wide Body Plastic Gull Wing AIMEL Colorado Springs CO 80906 Small Outline UEDEC SOIC 881 C 5120D SEEPR 6 08 AMEL 8A2 TSSOP Pin 1 indicator this corner N Top View End View COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX D 2 90 3 00 3 10 6 40 BSC 4 40 4 50 1 20 1 00 1 05 0 30 0 65 BSC Side Vievv L 0 60 0 75 1 00 REF This drawing is for general information only Refer to JEDEC Drawing MO 153 Variation AA for proper dimensions tolerances datums etc Dimension D does not include mold Flash protrusions or gate burrs Mold Flash protrusions and gate burrs
4. 20D SEEPR 6 08 SERIAL CLOCK SCL The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device SERIAL DATA SDA The SDA pin is bidirectional for serial data transfer This pin is open drain driven and may be vvire ORed vvith any number of other open drain or open collector devices DEVICE ADDRESSES A2 A1 A0 The A2 A1 and AO pins are device address inputs that are hardwired or left not connected for hardware compatibility with other AT24Cxx devices When the pins are hardwired as many as eight 32K 64K devices may be addressed on a single bus system device addressing is discussed in detail under the Device Addressing section If the pins are left floating the A2 A1 and AO pins will be internally pulled down to GND if the capaci tive coupling to the circuit board Vec plane is lt 3 pF If coupling is gt 3 pF Atmel recommends connecting the address pins to GND WRITE PROTECT WP The write protect input when connected to GND allows normal write operations When WP is connected high to Voo all write operations to the memory are inhibited If the pin is left floating the WP pin will be internally pulled down to GND if the capacitive cou pling to the circuit board Voc plane is lt 3 pF If coupling is gt 3 pF Atmel recommends connecting the pin to GND Switching WP to Vec prior to a write operation creates a software write protect function AT24C32A 64A 32K 64K SERIAL
5. BDTIC www BDTIC com ATMEL e eel Features Standard Voltage Operation 2 7 Vcc 2 7V to 5 5V Internally Organized 4096 x 8 32K 8192 x 8 64K Automotive Temperature Range 40 C to 125 C Two wire Serial Interface Schmitt Trigger Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 400 kHz Clock Rate Write Protect Pin for Hardware Data Protection 32 byte Page Write Mode Partial Page Writes Allowed Self timed Write Cycle 5 ms Max High Reliability Endurance 1 Million Write Cycles Data Retention 100 Years e Lead free Halogen free Devices Available 8 lead JEDEC SOIC and 8 lead TSSOP Packages Description The AT24C32A 64A provides 32 768 65 536 bits of serial electrically erasable and programmable read only memory EEPROM organized as 4096 8192 words of 8 bits AT24C32A each The device s cascadable feature allows up to 8 devices to share a common two wire bus The device is optimized for use in many automotive applications where low AT24C64A power and low voltage operation are essential The AT24C32A 64A is available in space saving 8 lead JEDEC SOIC and 8 lead TSSOP packages and is accessed via a 2 wire serial interface and is available in a 2 7V 2 7V to 5 5V version u O Two wire Automotive Serial EEPROM 32K 4096 x 8 64K 8192 x 8 Table 1 Pin Configuration 8 lead SOIC Pin Name Function AO A2 Address In
6. DDRESS D K K K P mi mi T T T SDA LINE E L l RA DATA n DATA n 1 DATA n 2 DATA n 3 N z o WK A C K 5120D SEEPR 6 08 mms AT24C32A 64A AT24C32A Ordering Information Ordering Code Operation Range AT24C32AN 108Q 2 70 881 Lead free Halogen free Automotive 40 C to 125 C Notes 1 For 2 7V devices used in the 4 5V to 5 5V range please refer to performance values in the AC and DC Characteristics tables 2 Q designates Green package and RoHS Compliant AT24C32A 10TQ 2 7 8A2 Package Type 8S1 8 lead 0 150 Wide Plastic Gull Wing Small Outline UEDEC SOIC 8A2 8 lead 4 4 mm Body Plastic Thin Shrink Small Outline Package TSSOP Options 2 7 Lovv Voltage 2 7V to 5 5V AMEL 1 5120D SEEPR 6 08 AMEL AT24C64A Ordering Information Ordering Code Operation Range Lead free Halogen free Automotive 40 C to 125 C AT24C64AN 10SQ 2 7 8S1 AT24C64A 10TQ 2 7 8A2 Notes 1 For 2 7V devices used in the 4 5V to 5 5V range please refer to performance values in the AC and DC Characteristics tables 2 Q designates Green package and RoHS Compliant Package Type 8S1 8 lead 0 150 Wide Plastic Gull Wing Small Outline UEDEC SOIC 8A2 8 lead 4 4mm Body Plastic Thin Shrink Small Outline Package TSSOP Options 2 7 Lovv Voltage 2 7V to 5 5V 5120D SEEPR 6 08 AT24C32A 64A Package Drawings 8S1 JEDEC
7. EEPROM The 32K 64K is internally organized as 128 256 pages of 32 bytes each Random word addressing requires a 12 13 bit data word address AMEL s Table 2 Pin Capacitance AMEL Applicable over recommended operating range from TA 25 C f 1 0 MHz Vec 2 7V to 5 5V Test Condition Input Output Capacitance SDA Conditions h Input Capacitance Ay A4 As SCL pF Vin OV is parameter is Characterized and is not 100 tested Table 3 DC Characteristics Applicable over recommended operating range from TA 40 C to 125 C Vog 2 7V to 5 5V unless otherwise noted Symbol Parameter Test Condition Min Typ Max Units Voces Supply Voltage 2 7 5 5 V lcc1 Supply Current Voc 5 0V READ at 400 kHz 0 4 1 0 mA cc Supply Current Voc 5 0V WRITE at 400 kHz 2 0 3 0 mA Voc 2 7V 1 0 3 0 Isp Standby Current Vin Voc Or Vss HA Voc 5 0V 3 0 5 0 lu ff Vin Vec r Vss 0 10 3 0 uA lo 7 Vout Vec Or Vss 0 05 3 0 uA Vi Input Low Level 0 6 Vcc x 0 3 V Vi Input High Level Voc x 0 7 Voc 0 5 V Vor Output Low Level Vec 3 0V Io 2 1 MA 0 4 V Vou Output Low Level Vcc 1 8V Io 0 15 mA 0 2 V Note 1 Vi min and V4 max are reference only and are not tested 4 AT24C324A 64A mmm 5120D SEEPR 6 08 mms AT24C32A 64A Table 4 AC Characteristics Applicable over recommended operating range from
8. OM the data word address will roll over and previous data will be overwritten ACKNOWLEDGE POLLING Once the internally timed write cycle has started and the EEPROM inputs are disabled acknowledge polling can be initiated This involves sending a start condition followed by the device address word The read write bit is representative of the operation desired Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue AMEL o Read Operations AMEL Read operations are initiated the same way as write operations with the exception that the read write select bit in the device address word is set to one There are three read operations current address read random address read and sequential read CURRENT ADDRESS READ The internal data word address counter maintains the last address accessed during the last read or write operation incremented by one This address stays valid between operations as long as the chip power is maintained The address roll over during read is from the last byte of the last memory page to the first byte of the first page The address roll over during write is from the last byte of the current page to the first byte of the same page Once the device address with the read write select bit set to one is clocked in and acknowledged by the EEPROM the current address data word is serially clocked out The microcontroller does
9. TA 40 C to 125 C Vec 2 7V to 5 5V CL 1 TTL Gate and 100 pF unless otherwise noted AT24C32A AT24C64A 2 7V 5 5V Symbol Parameter Min Max Units fscL Clock Frequency SCL 400 kHz tLow Clock Pulse Width Low 1 2 Hs tuiGH Clock Pulse Width High 0 6 us t Noise Suppression Time 50 ns AA Clock Low to Data Out Valid 0 1 0 9 Hs Time the bus must be free Bur before a nevv transmission 1 2 Hs can start HD STA Start Hold Time 0 6 Hs sU STA Start Set up Time 0 6 Hs tup pat Data In Hold Time 0 Hs tsu pat Data In Set up Time 100 ns tR Inputs Rise Time 0 3 us te Inputs Fall Time 300 ns tsy sto Stop Set up Time 0 6 us tou Data Out Hold Time 50 ns twr Write Cycle Time 5 ms Endurance 5 0V 25 C Page Mode 1M Write Cycles Notes 1 This parameter is ensured by characterization only AMEL 5 5120D SEEPR 6 08 Device Operation AMEL CLOCK and DATA TRANSITIONS The SDA pin is normally pulled high with an external device Data on the SDA pin may change only during SCL low time periods refer to Data Valid ity timing diagram Data changes during SCL high periods will indicate a start or stop condition as defined below START CONDITION A high to low transition of SDA with SCL high is a start condition which must precede any other command see Figure 5 on page 8 STOP CONDITION A low to high transition of SDA with SCL high is a st
10. not respond with an input zero but does generate a following stop condition see Figure 10 on page 11 RANDOM READ A random read requires a dummy byte write sequence to load in the data word address Once the device address word and data word address are clocked in and acknowledged by the EEPROM the microcontroller must generate another start condition The microcontroller now initiates a current address read by sending a device address with the read write select bit high The EEPROM acknowledges the device address and serially clocks out the data word The microcontroller does not respond with a zero but does generate a follow ing stop condition see Figure 11 on page 12 SEQUENTIAL READ Sequential reads are initiated by either a current address read or a ran dom address read After the microcontroller receives a data word it responds with an acknowledge As long as the EEPROM receives an acknowledge it will continue to increment the data word address and serially clock out sequential data words When the memory address limit is reached the data word address will roll over and the sequential read will continue The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition see Figure 12 on page 12 5120D SEEPR 6 08 mms AT24C32A 64A Figure 7 Device Address 1 0 1 0 A A A R W
11. op condition After a read sequence the stop command will place the EEPROM in a standby power mode see Fig ure 5 on page 8 ACKNOWLEDGE All addresses and data words are serially transmitted to and from the EEPROM in 8 bit words The EEPROM sends a zero during the ninth clock cycle to acknowl edge that it has received each word STANDBY MODE The AT24C32A 64A features a low power standby mode which is enabled a upon power up and b after the receipt of the stop bit and the completion of any internal operations MEMORY RESET After an interruption in protocol power loss or system reset any two wire part can be reset by following these steps a Clock up to 9 cycles b look for SDA high in each cycle while SCL is high and then c create a start condition as SDA is high 5120D SEEPR 6 08 AT24C32A 64A Figure 2 Bus Timing SCL Serial Clock SDA Serial Data I O tHIGH SCL tup pat SDA IN SDA OUT Figure 3 Write Cycle Timing SCL Serial Clock SDA Serial Data I O SCL SDA 8th BIT ACK il VVORDn M STOP START CONDITION CONDITION Note 1 The write cycle time twp is the time from a valid stop condition of a write sequence to the end of the internal clear write cycle Figure 4 Data Validity SDA SCL DATA STABLE DATA STABLE DATA CHANGE AMEL 7 5120D SEEPR 6 08 Figure 5 Start and Stop Definition SCL START STOP Figure 6 Output Acknowledge SCL 1 8
12. puts 25177 ATL 2 7 wP SDA Serial Data A2 C3 6 SCL GND C 4 51 1 SDA SCL Serial Clock Input WP Write Protect 8 lead TSSOP AOL 1 8 j vcc ATL 7 Evvp A2L 3 6 SCL GNDL 4 5 O SDA AMEL 5120D SEEPR 6 08 AMEL Absolute Maximum Ratings Operating Temperature 55 C to 125 C NOTICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam Storage Temperature 65 C to 150 C age to the device This is a stress rating only and functional operation of the device at these or any Voltage on Any Pin other conditions beyond those indicated in the with Respect to Ground eeeeeeeeeeeeeeeeeees 1 0V to 7 0V operational sections of this specification is not implied Exposure to absolute maximum rating Maximum Operating Voltage 6 25V conditions for extended periods may affect device reliability DC Output Current ecececeeeeeseeeneeeeeeeeeeeneeeeaeeeneeeaas 5 0 mA Figure 1 Block Diagram spa SERIAL EN CONTROL EN H V PUMP T IMING 9 LOGIC LOAD DEVICE COMP DATA RECOVERY ADDRESS COMPARATOR A A DATA VVORD FEBRONI Ay ADDR COUNTER SERIAL MUX Din o Dour a 5120D SEEPR 6 08 mms AT24C32A 64A Pin Description Memory Organization 51
13. shall not exceed 0 15 mm 0 006 in per side Dimension E1 does not include inter lead Flash or protrusions Inter lead Flash and protrusions shall not exceed 0 25 mm 0 010 in per side Dimension b does not include Dambar protrusion Allowable Dambar protrusion shall be 0 08 mm total in excess of the b dimension at maximum material condition Dambar cannot be located on the lower radius of the foot Minimum space between protrusion and adjacent lead is 0 07 mm Dimension D and E1 to be determined at Datum Plane H 5 30 02 TITLE DRAWING NO REV 2325 Orchard Parkway 8A2 8 lead 4 4 mm Body Plastic 8A2 B o San Jose CA 95131 Thin Shrink Small Outline Package TSSOP 16 AT24C324A 64A 5120D SEEPR 6 08 AT24C32A 64A Revision History Revision History 5120D 6 2008 Implemented revision history AMEL v 5120D SEEPR 6 08
14. ss word and acknowledgment Upon receipt of this address the EEPROM will again respond with a zero and then clock in the first 8 bit data word Following receipt of the 8 bit data word the EEPROM will output a zero and the addressing device such as a microcontroller must terminate the write sequence with a stop condition At this time the EEPROM enters an internally timed write cycle twp to the nonvolatile memory All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete see Figure 8 on page 11 PAGE WRITE The 32K 64K EEPROM is capable of 32 byte page writes A page write is initiated the same way as a byte write but the microcontroller does not send a stop condition after the first data word is clocked in Instead after the EEPROM acknowledges receipt of the first data word the microcontroller can transmit up to 31 more data words The EEPROM will respond with a zero after each data word received The microcontroller must ter minate the page write sequence with a stop condition See Figure 9 on page 11 The data word address lower five bits are internally incremented following the receipt of each data word The higher data word address bits are not incremented retaining the memory page row location When the word address internally generated reaches the page boundary the fol lowing byte is placed at the beginning of the same page If more than 32 data words are transmitted to the EEPR
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ATMEL AT24C64A handbook