ATMEL AT25010A/AT25020A/AT25040A Manual(1)
Contents
1. CS 4 tep ten SCK tHo HOLD tun Le 4 so ltz AMEL 5087D SEEPR 3 07 AT25010A 020A 040A 11 AMEL AT25010A Ordering Information Ordering Code Operation Range Lead free Halogen free ea eee i Automotive Temperature AT25010A 10TQ 2 7 8A2 40 C to 125 C Package Type 8S1 8 lead 0 150 Wide Plastic Gull Wing Small Outline JEDEC SOIC 8A2 8 lead 0 170 Wide Thin Shrink Small Outline Package TSSOP Options 2 7 Low Voltage 2 7V to 5 5V 5087D SEEPR 3 07 AT25020A Ordering Information Ordering Code Operation Range Lead free Halogen free AT 25020AN1080 2 7 el Automotive Temperature AT25020A 10TQ 2 7 8A2 40 C to 125 C Package Type 8S1 8 lead 0 150 Wide Plastic Gull Wing Small Outline JEDEC SOIC 8A2 8 lead 0 170 Wide Thin Shrink Small Outline Package TSSOP Options 2 7 Low Voltage 2 7V to 5 5V ATMEL 1 5087D SEEPR 3 07 AMEL AT25040A Ordering Information Ordering Code Operation Range Lead free Halogen free Sa IW GES 7 o Automotive Temperature AT25040A 10TQ 2 7 8 40 C to 125 C Package Type 8S1 8 lead 0 150 Wide Plastic Gull Wing Small Outline JEDEC SOIC 8A2 8 lead 0 170 Wide Thin Shrink Small Outline Package TSSOP Options 2 7 Low Voltage 2 7V to 5 5V 5087D SEEPR 3 07 P2. 6 25V conditions for extended periods may affect device reliability DC Output Current ss 5 0 mA Figure 1 Block Diagram VCC GND STATUS MEMORY ARRAY REGISTER 128 256 ADDRESS DECODER 512x8 DATA REGISTER OUTPUT BUFFER SI SCK 2 AT25010A 020A 040A mm 5087D SEEPR 3 07 Table 2 Pin Capacitance Applicable over recommended operating range from T 25 C f 1 0 MHz Vec 5 0V unless otherwise noted Symbol Test Conditions Max Units Conditions Cour Output Capacitance SO 8 pF Vout OV Cn Input Capacitance CS SCK SI WP HOLD 6 pF Vin OV Note 1 This parameter is characterized and is not 100 tested Table 3 DC Characteristics Applicable over recommended operating range from Ty 40 C to 125 C Voc 2 7V to 5 5V Symbol Parameter Test Condition Min Max Units Voct Supply Voltage 2 7 5 5 V loci Supply Current Voc 5 0V at 1 MHz SO Open Read 3 0 mA Voc 5 0V at 2 MHz SO Open loce Supply Current Read Write 6 0 mA Voc 5 0V at 5 MHz SO Open lcca Supply Current Read Write 6 0 mA lsg Standby Current Vec 2 7V CS Vec 3 0 HA Igpo Standby Current Voc 5 0V CS Vec 5 0 HA LL Input Leakage Vin OV to Vec 0 6 3 0 HA lo Output Leakage Vin OV to Voc 0 6 3 0 pA Ve Input Low Voltage 0 6 Voc x 0 3 V Vin Input High Voltage Voc X 0 7 Voc 0 5 V V O
3. WAA IL sy to pe tois Von TRE so HI Z AM X N N HI Z Q VAN NA Vo N Wi A AA YE EL L N N L Figure 4 WREN Timing as sd ror E SI WREN OP CODE so HI Z Figure 5 WRDI Timing cs SCK LILI LULL Ll SI WRDI OP CODE 66 HI Z AMEL 5087D SEEPR 3 07 AMEL Figure 6 RDSR Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK INSTRUCTION SI DATA OUT eee RT VE Ea BK 2X1 OD MSB Figure 7 WRSR Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK INSTRUCTION DATA IN i S NE eee 0 S REX2X HIGH IMPEDANCE SO 10 AT25010A 020A 040A memm Figure 8 READ Timing cf 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK INSTRUCTION BYTE ADDRESS XXX 8 ea AX XX AK 9TH BIT OF ADDRESS HIGH IMPEDANCE oe SO zX6X5X4X8X2X1X0 MSB Figure 9 WRITE Timing cs 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK U INSTRUCTION BYTE ADDRESS DATA IN si XXX Z 2099037020000010 9TH BIT OF ADDRESS HIGH IMPEDANCE SO Figure 10 HOLD Timing
4. 040A Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 A011 Read Data from Memory Array WRITE 0000 A010 Write Data to Memory Array Note A represents MSB address bit A8 WRITE ENABLE WREN The device will power up in the write disable state when Voc is applied All programming instructions must therefore be preceded by a Write Enable instruction The WP pin must be held high during a WREN instruction WRITE DISABLE WRDI To protect the device against inadvertent writes the Write Disable instruction disables all programming modes The WRDI instruction is indepen dent of the status of the WP pin READ STATUS REGISTER RDSR The Read Status Register instruction provides access to the status register The READY BUSY and Write Enable status of the device can be determined by the RDSR instruction Similarly the block write protection bits indicate the extent of protection employed These bits are set by using the WRSR instruction Table 6 Status Register Format Bit7 Bits Bits Bitd Bts Bit2 Biti Bito X X X BP1 BPO WEN RDY X Table 7 Read Status Register Bit Definition Bit Definition Bit 0 RDY Bit O 0 RDY indicates the device is ready Bit O 1 indicates the write cycle is in progress B
5. 040A es 5087D SEEPR 3 07 Serial Interface Description 5087D SEEPR 3 07 MASTER The device that generates the serial clock SLAVE Because the serial clock pin SCK is always an input the AT25010A 020A 040A always operates as a slave TRANSMITTER RECEIVER The AT25010A 020A 040A has separate pins designated for data transmission SO and reception SI MSB The Most Significant Bit MSB is the first bit transmitted and received SERIAL OP CODE After the device is selected with CS going low the first byte will be received This byte contains the op code that defines the operations to be performed The op code also contains address bit A8 in both the Read and Write instructions INVALID OP CODE If an invalid op code is received no data will be shifted into the AT25010A 020A 040A and the serial output pin SO will remain in a high impedance state until the falling edge of CS is detected again This will reinitialize the serial communication CHIP SELECT The AT25010A 020A 040A is selected when the CS pin is low When the device is not selected data will not be accepted via the SI pin and the serial output pin SO will remain in a high impedance state HOLD The HOLD pin is used in conjunction with the CS pin to select the AT25010A 020A 040A When the device is selected and a serial sequence is underway HOLD can be used to pause the serial communication with the master device without resetting the serial sequence To
6. BDTIC www bdtic com ATMEL Features Serial Peripheral Interface SPI Compatible Supports SPI Modes 0 0 0 and 3 1 1 Data Sheet Describes Mode 0 Operation Medium voltage and Standard voltage Operation 2 7 Vcc 2 7V to 5 5V Extended Temperature Range 40 C to 125 C 5 0 MHz Clock Rate 8 byte Page Mode Block Write Protection Protect 1 4 1 2 or Entire Array Write Protect WP Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self timed Write Cycle 10 ms max High Reliability Endurance One Million Write Cycles Data Retention 100 Years 8 lead JEDEC SOIC and 8 lead TSSOP Packages Description The AT25010A 020A 040A provides 1024 2048 4096 bits of serial electrically eras able programmable read only memory EEPROM organized as 128 256 512 words of 8 bits each The device is optimized for use in many automotive applications where low power and low voltage operation are essential The AT25010A 020A 040A is available in space saving 8 lead JEDEC SOIC and 8 lead TSSOP packages The AT25010A 020A 040A is enabled through the Chip Select pin CS and accessed via a three wire interface consisting of Serial Data Input SI Serial Data Output SO and Serial Clock SCK All programming cycles are completely self timed and no separate erase cycle is required before write Block write protection is enabled by programming the status register with one of four blocks of write protec
7. ackaging Information 851 JEDEC SOIC gr Top View End View COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX A 1 35 1 75 A1 0 10 0 25 0 31 0 51 0 17 0 25 4 80 5 00 3 81 3 99 Side View 127 BSC Note These drawings are for general information only Refer to JEDEC Drawing MS 012 Variation AA for proper dimensions tolerances datums etc 10 7 03 TITLE DRAWING NO REV MEL 1150 E Cheyenne Min Blvd 8S1 8 lead 0 150 Wide Body Plastic Gull Win A MEL Colorado Springs CO 80906 Smal Outline JEDEC SOIC d j 381 B AMEL i 5087D SEEPR 3 07 AMEL 8A2 TSSOP Pin 1 indicator this corner N Top View End View COMMON DIMENSIONS Unit of Measure mm SYMBOL 3 00 6 40 BSC 4 40 p 1 00 i E 0 65 BSC Side View 0 60 1 00 REF This drawing is for general information only Refer to JEDEC Drawing MO 153 Variation AA for proper dimensions tolerances datums etc Dimension D does not include mold Flash protrusions or gate burrs Mold Flash protrusion
8. e read A7 A0 Upon completion any data on the SI line will be ignored The data D7 D0 at the specified address is then shifted out onto the SO line If only one byte is to be read the CS line should be driven high after the data comes out The read seguence can be continued since the byte address is automatically incremented and data will continue to be shifted out When the highest address is reached the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle WRITE SEGUENCE WRITE In order to program the AT25010A 020A 040A the Write Protect WP pin must be held high and two separate instructions must be executed First the device must be write enabled via the WREN instruction Then a write WRITE instruction may be executed Also the address of the memory location s to be pro grammed must be outside the protected address field location selected by the block write protection level During an internal write cycle all commands will be ignored except the RDSR instruction A write instruction reguires the following seguence After the CS line is pulled low to select the device the WRITE op code including A8 is transmitted via the SI line fol lowed by the byte address A7 AO and the data D7 DO to be programmed Programming will start after the CS pin is brought high The low to high transition of the CS pin must occur during the SCK low time immediately after clocking
9. in the DO LSB data bit The READY BUSY status of the device can be determined by initiating a read status register RDSR instruction If Bit O 1 the write cycle is still in progress If Bit O 0 the write cycle has ended Only the RDSR instruction is enabled during the write pro gramming cycle The AT25010A 020A 040A is capable of an 8 byte page write operation After each byte of data is received the three low order address bits are internally incremented by one the six high order bits of the address will remain constant If more than eight bytes of data are transmitted the address counter will roll over and the previously written data will be overwritten The AT25010A 020A 040A is automatically returned to the write dis able state at the completion of a write cycle NOTE If the WP pin is brought low or if the device is not write enabled WREN the device will ignore the Write instruction and will return to the standby state when CS is brought high A new CS falling edge is required to reinitiate the serial communication 8 AT25010A 020A 040A memm Timing Diagrams Figure 3 Synchronous Data Timing for Mode 0 e tes Vin cs N 7 NN Vi toss i lt gt tesh a o SCK lt kg gt Vi tsu ty Va TT ON ANT A TATA NA VA AA A ANY VARA AA NW MAN AAA SI WAWAAAAAAAA VALID IN AAA HA ANA A y AN
10. it 1 WEN Bit 1 O indicates the device is not write enabled Bit 1 1 indicates the device is write enabled Bit 2 BPO See Table 8 on page 8 Bit 3 BP1 See Table 8 on page 8 Bits 4 6 are O s when device is not in an internal write cycle Bits O 7 are 1 s during an internal write cycle WRITE STATUS REGISTER WRSR The WRSR instruction allows the user to select one of four levels of protection The AT25010A 020A 040A is divided into four array seg ments One guarter one half or all of the memory segments can be protected Any of AMEL 7 AMEL the data within any selected segment will therefore be read only The block write protec tion levels and corresponding status register control bits are shown in Table 8 Bits BPO and BP1 are nonvolatile cells that have the same properties and functions as the regular memory cells e g WREN two RDSR Table 8 Block Write Protect Bits Status Register Bits Array Addresses Protected Level BP1 BPO AT25010A AT25020A AT25040A 0 0 0 None None None 1 1 4 0 1 60 7F CO FF 180 1FF 2 1 2 1 0 40 7F 80 FF 100 1FF 3 All 1 1 00 7F 00 FF 000 1FF READ SEQUENCE READ Reading the AT25010A 020A 040A via the serial output SO pin requires the following sequence After the CS line is pulled low to select a device the read op code including A8 is transmitted via the SI line followed by the byte address to b
11. pause the HOLD pin must be brought low while the SCK pin is low To resume serial communication the HOLD pin is brought high while the SCK pin is low SCK may still toggle during HOLD Inputs to the SI pin will be ignored while the SO pin is in the high impedance state WRITE PROTECT The write protect pin WP will allow normal read write operations when held high When the WP pin is brought low all write operations are inhibited WP going low while CS is still low will interrupt a write to the AT25010A 020A 040A If the internal write cycle has already been initiated WP going low will have no effect on any write operation AMEL s 6 AMEL Figure 2 SPI Serial Interface MASTER MICROCONTROLLER DATA OUT MOSI DATA IN MISO SERIAL CLOCK SPI CK SSO SS1 SS2 SS3 SLAVE AT25010A 020A 040A o gt Sl SO AT25010A 0204A 040A memme 5087D SEEPR 3 07 Functional Description 5087D SEEPR 3 07 The AT25010A 020A 040A is designed to interface directly with the synchronous serial peripheral interface SPI of the 6805 and 68HC11 series of microcontrollers The AT25010A 020A 040A utilizes an 8 bit instruction register The list of instructions and their operation codes are contained in Table 5 All instructions addresses and data are transferred with the MSB first and start with a high to low CS transition Table 5 Instruction Set for the AT25010A 020A
12. s and gate burrs shall not exceed 0 15 mm 0 006 in per side Dimension E1 does not include inter lead Flash or protrusions Inter lead Flash and protrusions shall not exceed 0 25 mm 0 010 in per side Dimension b does not include Dambar protrusion Allowable Dambar protrusion shall be 0 08 mm total in excess of the b dimension at maximum material condition Dambar cannot be located on the lower radius of the foot Minimum space between protrusion and adjacent lead is 0 07 mm Dimension D and E1 to be determined at Datum Plane H 5 30 02 TITLE DRAWING NO REV 2325 Orchard Parkway 8A2 8 lead 4 4 mm Body Plastic San Jose CA 95131 Thin Shrink Small Outline Package TSSOP E 16 AT25010A 020A 040A 5087D SEEPR 3 07 Revision History Doc Rev Date Commenis 5087D 3 2007 Corrected package codes on pages 12 and 13 5087C 2 2007 Implemented revision history Removed PDIP package offering Removed PB d parts AMEL 7 5087D SEEPR 3 07
13. tion Separate program enable and program disable instructions are provided for additional data protection Hardware data protection is provided via the WP pin to protect against inadvertent write attempts The HOLD pin may be used to suspend any serial communication without resetting the serial sequence Table 1 Pin Configurations Pin Name Function 8 lead SOIC cs Chip Select o csc 8 II vec SCK Serial Data Clock sor je 7 HOLD SI Serial Data Input WP 3 6 SCK GND O4 5 SI SO Serial Data Output GND Ground 8 lead TSSOP VCC Power Suppl e RR csc 8 EI vcc WP Write Protect soL 2 7 HOLD HOLD Suspends Serial Input nr SI SER GND 4 5 si d OO SPI Automotive Temperature Serial EEPROMs 1K 128 x 8 2K 256 x 8 4K 512 x 8 AT25010A AT25020A AT25040A 5087D SEEPR 3 07 AMEL Absolute Maximum Ratings Operating Temperature 55 C to 125 C NOTICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam Storage Temperature 65 C to 150 C age to the device This is a stress rating only and functional operation of the device at these or any Voltage on Any Pin other conditions beyond those indicated in the with Respect to Ground 1 0V to 7 0V operational sections of this specification is not implied Exposure to absolute maximum rating Maximum Operating Voltage
14. utput Low Voltage Io 2 0 mA 0 4 V on 3 6V lt Veo lt 5 5V Vout Output High Voltage lou 1 0 mA Vcc 0 8 V V Output Low Voltage lou 0 15 mA 0 2 V VE 2 7V lt Voc lt 3 6V Von Output High Voltage lou 100 HA Voc 0 2 V Note 1 Worst case measured at 125 C 2 Vr min and Vj max are reference only and are not tested 5087D SEEPR 3 07 AMEL Table 4 AC Characteristics Applicable over recommended operating range from Ty 409C to 125 C Vcc As Specified CL 1 TTL Gate and 100 pF unless otherwise noted AMEL Symbol Parameter Voltage Min Max Units fsck SCK Clock Frequency 2 7 5 5 0 5 0 MHz ta Input Rise Time 2 7 5 5 2 us te Input Fall Time 2 7 5 5 2 us tu SCK High Time 2 7 5 5 40 ns tw SCK Low Time 2 7 5 5 40 ns tes CS High Time 2 7 5 5 80 ns tess CS Setup Time 2 7 5 5 80 ns tesi CS Hold Time 2 7 5 5 80 ns tsu Data In Setup Time 2 7 5 5 5 ns ty Data In Hold Time 2 7 5 5 20 ns tuo Hold Setup Time 2 7 5 5 40 too Hold Hold Time 2 7 5 5 40 ns ty Output Valid 2 7 5 5 0 40 ns tho Output Hold Time 2 7 5 5 0 ns tz Hold to Output Low Z 2 7 5 5 0 40 ns tuz Hold to Output High Z 2 7 5 5 80 ns tois Output Disable Time 2 7 5 5 80 ns two Write Cycle Time 2 7 5 5 5 ms Endurance 5 0V 25 C Page Mode 1M Write Cycles Note 1 This parameter is characterized and is not 100 tested 4 AT25010A 020A
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ATMEL AT25010A/AT25020A/AT25040A Manual(1)