ATMEL AT25128A/AT25256A Manual
Contents
1. s ViH UN 4 2 Vi N x 3 css s csH Vibe 1 SCK k L ViL su H b H ViH VXXX A N AMARMMN VA V N VUVAXN 277 V AXXX XXA X XZ VAAN s VAAK AN VALID IN 5 MAN 55 VA m V V V Vi VA iv A i i V Voy Lo iy lo bis Vo XOS X VR VA N so HI Z 257 177 V KKVAZ Z N HI Z NN VX i 5 0 A XA V 5 A TL 4 V X ma Z OL Figure 4 VVREN Timing cs SCK M uepanayanea SI VVREN OP CODE so HI Z Figure 5 VVRDI Timing cs SCK L LTL T zi SI VVRDI OP CODE HI Z SO 5088F SEEPR 2 07 Figure 6 RDSR Timing 10 11 12 13 14 15 SCK SI Z A A A DATA OUT HIGH IMPEDANGE So K7 6 5 X4X3X2X1202 MSB Figure 7 VVRSR Timing 11 12 13 14 SCK DATA IN SI INSTRUCT ION 6 5 4 10 HIGH IMPEDANCE SO Almer 5088F SEEPR 2 07 11 AlmEr Figure 8 READ Timing 01 25 34 5 6 7 8 91011 20 21 22 23 24 25 26 27 28 29 30 91 SCK BYTE ADDRESS s XA INSTRUCT ON c 6 X m 0 0 010119171001110101X1 DATA OUT HIGH IMPEDANCE SO Figure 9 VVRITE Timing es 01238 4 5 6 7 8 9 10 11 20 2122 23 24 25 26 27 28 29 90 91 SCK LiL TTT1liu LML LLu u u uu Lul BYTE ADDRESS DATA IN si YOQA NSTRUCT ON N eXteX X XiXoXosXsX X 2 xo HIGH IM2. Pin Name Function cs Chip Select 8 lead SOIC SCK Serial Data Clock S E11 sE vcc SO 2 7 HOLD SI Serial Data Input V P 3 s SeK SO Serial Data Output ep sE5I GND Ground 8 lead TSSOP VCC Povver Supply VVP VVrite Protect cs 1 8 VCC SO 2 7 HOLD HOLD Suspends Serial nput VP 3 6 SCK NC No Connect GNDT 14 5 s DC Don t Connect Almer NN c SPI Automotive Temperature Serial EEPROMs 128K 16 384 x 8 256K 32 768 x 8 AT25128A AT25256A 5088F SEEPR 2 07 AlmEr Block vvrite protection is enabled by programming the status register vvith top one forth top one half or entire array of vvrite protection Separate program enable and program disable instructions are provided for additional data protection Hardvvare data protec tion is provided via the VVP pin to protect against inadvertent vvrite attempts to the status register The HOLD pin may be used to suspend any serial communication vvithout resetting the serial sequence Absolute Maximum Ratings Operating Temperature 409C to 125 C Storage Temperature 659C to 41509C Voltage on Any Pin vvith Respect to Ground 1 0V to 7 0V Maximum Operating Voltage 6 25V DC Output CurrentL s 88 8888222388 8282 3888 5 0 mA Figure 1 Block Dia
3. Array Addresses Protected Level BP1 BP0 AT25128A AT25256A 0 0 0 None None 1 1 4 0 1 3000 3FFF 6000 7FFF 2 1 2 1 0 2000 3FFF 4000 7FFF 3 Al 1 1 0000 3FFF 0000 7FFF The VVRSR instruction also allovvs the user to enable or disable the vvrite protect VVP pin through the use of the vvrite protect enable VVPEN bit Hardvvare vvrite protection is enabled vvhen the VVP pin is lovv and the VVPEN bit is 1 Hardvvare vvrite protection is disabled vvhen eifher the VVP pin is high or the VVPEN bit is 0 VVhen the device is hard vvare vvrite protected vvrites to the status register including the block protect bits and the VVPEN bit and the block protected sections in the memory array are disabled VVrites are only allovved to sections of the memory that are not block protected NOTE VVhen the VVPEN bit is hardvvare vvrite protected it cannot be changed back to O as long as the VVP pin is held lovv Table 9 VVPEN Operation Protected Unprotected Status VVPEN VVP VVEN Blocks Blocks Register 0 X 0 Protected Protected Protected 0 X 1 Protected VVriteable VVriteable 1 Lovv 0 Protected Protected Protected 1 Lovv 1 Protected VVriteable Protected High 0 Protected Protected Protected X High 1 Protected VVriteable VVriteable READ SEQUENCE READ Reading the AT25128A 256A via the SO pin requires the follovving sequence After the CS line is pulled lovv to
4. SEEPR 2 07 Functional Description 5088F SEEPR 2 07 The AT25128A 256A is designed to interface directly vvith the synchronous serial peripheral interface SPI of the 6800 type series of microcontrollers The AT25128A 256A utilizes an 8 bit instruction register The list of instructions and their operation codes are contained in Table 5 AlI instructions addresses and data are transferred vvith the MSB first and start vvith a high to lovv CS transition Table 5 Instruction Set for the AT25128A 256A nstruction Name nstruction Format Operation VVREN 0000 X110 Set VVrite Enable Latch VVRDI 0000 X100 Reset VVrite Enable Latch RDSR 0000 X101 Read Status Register VVRSR 0000 X001 VVrite Status Register READ 0000 X011 Read Data from Memory Array VVR TE 0000 X010 VVrite Data to Memory Array VVR TE ENABLE VVREN The device vvill povver up in the vvrite disable state vvhen Vcc is applied All programming instructions must therefore be preceded by a VVrite Enable instruction VVRITE DISABLE VVRD To protect the device against inadvertent vvrites the VVrite Disable instruction disables all programming modes The VVRDI instruction is indepen dent of the status of the VVP pin READ STATUS REGISTER RDSR The Read Status Register instruction provides access to the status register The Ready Busy and VVrite Enable status of the device can be determined by the RDSR instruction Similarly the block v
5. be determined at Datum Plane H 5 30 02 TITLE DRAVVING NO REV 2325 Orchard Parkvvay 8A2 8 lead 4 4 mm Bo y Plastic 8A2 B o San dose CA 95131 Thin Shrink Small Outline Package TSSOP 16 AT25128A 256A 5088F SEEPR 2 07 AT25128A 256A Revision History Dek Dm mm 5088F 2 2007 Revision history implemented Removed PD P package offering Removed Pb d parts Almer v 5088F SEEPR 2 07
6. 5 5 0 40 ns z Hold to Output High Z 2 7 5 5 80 ns pis Output Disable Time 2 7 5 5 80 ns yyc VVrite Cycle Time 2 7 5 5 5 ms Endurance 5 0V 25 C Page Mode 1M VVrite Cycles Note 1 This parameter is ensured by characterization only 5088F SEEPR 2 07 Serial interface Description 5088F SEEPR 2 07 MASTER The device that generates the serial clock SLAVE Because the serial clock pin SCK is alvvays an input the AT25128A 256A alvvays operates as a slave TRANSMITTER RECEIVER The AT25128A 256A has separate pins designated for data transmission SO and reception SI MSB The Most Significant Bit MSB is the first bit transmitted and received SERIAL OP CODE After the device is selected vvith CS going lovv the first byte vvill be received This byte contains the op code that defines the operations to be performed INVALID OP CODE f an invalid op code is received no data vvill be shifted into the AT25128A 256A and the serial output pin SO vvill remain in a high impedance state until the falling edge of CS is detected again This vvill reinitialize the serial commuhnication CHIP SELECT The AT25128A 256A is selected vvhen the CS pin is lovv VVhen the device is not selected data vvill not be accepted via the SI pin and the SO pin vill remain in a high impedance state HOLD The HOLD pin is used in coniunction vvith the cs pin to select the AT25128A 256A VVhen the device is selected and a serial sequenc
7. BDTIC vvvvvv bdtic com ATMEL HE 0v0 N n Features Serial Peripheral Interface SPI Compatible Supports SPI Modes 0 0 0 and 3 1 1 Data Sheet Describes Mode 0 Operation Standard voltage Operation 2 7 Vcc 2 7V to 5 5V Automotive Temperature Range 40 C to 4125 C 5 MHz Clock Rate 64 byte Page Mode and Byte VVrite Operation Block VVrite Protection Protect 1 4 1 2 or Entire Array VVrite Protect VVP Pin and VVrite Disable Instructions for both Hardvvare and Softvvare Data Protection Self timed VVrite Cycle 5 ms max High Reliability Endurance 1 Million VVrite Cycles Data Retention 5100 Years 8 lead EDEC SOIC and 8 lead TSSOP Packages Description The AT25128A 256A provides 131 072 262 144 bits of serial electrically erasable pro grammable read onily memory EEPROM organized as 16 384 32 768 vvords of 8 bits each The device is optimized for use in many industrial and automotive applications vvhere lovv povver and lovv voltage operation are essential The devices are available in space saving 8 lead EDEC SOIC and 8 lead TSSOP packages The AT25128A 256A is enabled through the Chip Select pin CS and accessed via a three vvire interface consisting of Serial Data nput SI Serial Data Output SO and Serial Clock SCK All programming eycles are completely self timed and no sepa rate erase eycle is required before vvrite Table 1 Pin Configurations
8. PEDANCE SO Figure 10 HOLD Timing 12 AT25128A 256A sans 5088F SEEPR 2 07 AT25128A Ordering nformation Ordering Code Operation Range Lead free Halogen free 7 Automotive Temperature i 409C to 1259C Package Type 8581 8 lead 0 150 VVide Plastic Gull VVing Small Outline Package UEDEC SOIC 8A2 8 lead 0 170 VVide Thin Shrink Small Outline Package TSSOP Options 2 7 Lovv voltage 2 7V to 5 5V Almer C 5088F SEEPR 2 07 AlmEr AT25256A Ordering nformation Ordering Code Operation Range Lead free Halogen free AT25256AN 1050 2 7 881 Automefile Temperature u AT25256A 10T0 2 7 8A2 5 c409C to 125 C Package Type 881 8 lead 0 150 VVide Plastic Gull VVing Small Outline Package UEDEC SOIC 8A2 8 lead 0 170 VVide Thin Shrink Small Outline Package TSSOP Options 2 7 Lovv voltage 2 7V to 5 5V 5088F SEEPR 2 07 Packaging nformation 881 EDEC SOIC g LL Top Vievv End Vievv COMMON DIMENSIONS Unit of Measure mm SYMBOL I MIN NOM MAX A 1 35 1 75 A1 0 10 0 25 0 31 0 51 0 17 0 25 4 80 5 00 3 81 3 99 Side Vievv L 7 BSC Note These dravvings are for general information only Refe
9. e is undervvay HOLD can be used to pause the serial communication vvith the master device vvithout resetting the serial sequence To pause the HOLD pin must be brought lovv vvhile the SCK pin is lovv To resume serial communication the HOLD pin is brought high vvhile the SCK pin is lovv SCK may still toggle during HOLD Inputs to the SI pin vvill be ignored vvhile the SO pin is in the high impedance state VVR TE PROTECT The vrrite protect pin VVP vvill allovv normal read vrite operations vvhen held high VVhen the VVP pin is brought lovv and VVPEN bit is 1 all vvrite opera tions to the status register are inhibited VVP going lovv vvhile CS is still lovv vvill interrupta vvrite to the status register If the internal vvrite eycle has already been initiated VVP going lovv vvill have no effect on any vvrite operation to the status register The VVP pin function is blocked vvhen the VVPEN bit in the status register is 0 This vvill allovv the user to install the AT25128A 256A in a system vvith the VVP pin tied to ground and still be able to vvrite to the status register AlI VVP pin functions are enabled vvhen the VVPEN bit is set to 1 Almer 6 AlmEr Figure 2 SPI Serial Interface MASTER MICROCONTROLLER DATA OUT MOSI DATA IN MISO SERIAL CLOCK SPI CK SS0 SS1 SS2 SS3 SLAVE AT25128A 256A 9 bi SI SO AT25128A 256A saa 5088F
10. gh The lovv to high transition of the CS pin must occur dur ing the SCK lovv time immediately after clocking in the DO LSB data bit The Ready Busy status of the device can be determined by initiating a Read Status Register RDSR instruction If Bit 0 1 the vvrite eycle is still in progress f Bit 0 0 the vvrite eycle has ended Only the RDSR instruction is enabled during the vvrite pro gramming eycle The AT25128A 256A is capable of a 64 byte page vvrite operation After each byte of data is received the six lovv order address bits are internally incremented by one the high order bits of the address viill remain constant If more than 64 bytes of data are transmitted the address counter vvill roll over and the previously vvritten data vvill be overvvritten The AT25128A 256A is automatically returned to the vvrite disable state at the completion of a vvrite eycle NOTE f the device is not vvrite enabled VVREN the device vvill ignore the VVrite instruction and vvill return to the standby state vvhen CS is brought high A nevv CS falling edge is requlred to reinitiate the serial communication Table 10 Address Key Address AT25128A AT25256A Ax Al A Al4 A Dor t Care Bits A A A 5 Almer 5088F SEEPR 2 07 AlmEr Timing Diagrams for SPI Mode 0 f00 01 Figure 3 Synchronous Data Timing
11. gram STATUS REGISTER NOTICE Stresses beyond those listed under Absolute Maxi mum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Vvcc GND ADDRESS DECODER MEMORY ARRAY 16384 32768 x8 DATA REGISTER 5088F SEEPR 2 07 Table 2 Pin Capacitance Applicable over recommended operating range from TA 25 C f 1 0 MHz V 5 0V unless othervvise noted Symbol Test Conditions Max Units Conditions Cour Output Capacitance SO 8 pF Vour 0V Cin Input Capacitance CS SCK SI VVP HOLD 6 pF Vi 0V Note 1 This parameter is characterized and is not 10096 tested Table 3 DC Characteristics Applicable over recommended operating range from TA 40 C to 125 C V e 32 7V to 45 5V Symbol Parameter Test Condition Min Typ Max Units Veci Supply Voltage 2 7 5 5 V Voc Supply Voltage 4 5 5 5 V ce Suppiy Current Ve 5 0V at 1 MHz SO Open Read 2 0 3 0 mA cc Supply Current 7 3 0 5 0 mA i Supply Current 7 0977 3 5 6 0 mA s Standby Current V ee27v c Ve 0 5 12 00 HA z Standby Cu
12. r to UEDEC Dravving MS 012 Variation AA for proper dimensions tolerances datums etc 10 7 03 TITLE DRAVVING NO REV Alne 59 F Cheyemne Min Bivd ast 8 lead 0 150 Vide Body Plastic Gull VVing sen 6 a Colvrado Springs CO 80906 small Outline UEDEC SOIC 5088F SEEPR 2 07 AlmEr 8A2 TSSOP Pin 1 indicator this corner End Vievv COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX D 3 00 3 10 6 40 BSC 4 40 4 50 TTT T 1 20 lel 1 00 1 05 0 30 0 65 BSC Side Vievv 0 60 0 75 L1 1 00 REF D This dravving is for general information only Refer to UEDEC Dravving MO 153 Variation AA for proper dimensions tolerances datums etc Dimension D does not include mold Flash protrusions or gate burrs Mold Flash protrusions and gate burrs shall not exceed 0 15 mm 0 006 in per side Dimension E1 does not include inter lead Flash or protrusions nter lead Flash and protrusions shall not exceed 0 25mm 0 010 in per side Dimension b does not include Dambar protrusion Allovvable Dambar protrusion shall be 0 08 mm total in excess of the b dimension at maximum material condition Dambar cannot be located on the lovver radius of the foot Minimum space betvveen protrusion and adiacent lead is 0 07 mm Dimension D and E1 to
13. rrent Vaeez B V CS Vac 2 0 15 00 HA L nput Leakage Vi S OV to Vcc 0 3 0 HA oL Output Leakage Viy V to Vcc 3 0 3 0 HA VL Input Lovv voltage 1 0 Vec x 0 3 V V Input High voltage Vec x 0 7 Vec 7 0 5 V Vo Output Lovv voltage 3 6 x Vee s 5 5V lo 7 3 0mA 0 4 V Voxz Output Lovv voltage 2 7s Vee s 3 6V lo 0 15mA 0 2 V Vo Output High voltage 3 6 x Ve s 5 5V on 1 6 mA Vec 0 8 V VoHz Output High voltage 2 7s Vec s 3 6V on 7 100 HA Vec 0 2 V Note 1 Maximum value at 125 C 2 Vi and Vu max are reference only and are not tested Almer 5088F SEEPR 2 07 Table 4 AC Characteristics Applicable over recommended operating range from TA 409C to 4125 C V c As Specified CL z 1TTL Gate and 100 pF unless othervvise noted AlmEr Symbol Parameter Voltage Min Max Units sck SCK Clock Frequency 2 7 5 5 0 5 0 MHz k nput Rise Time 2 7 5 5 2 Hs F nput Fall Time 2 7 5 5 2 HS yyH SCK High Time 2 7 5 5 40 ns yyL SCK Lovv Time 2 7 5 5 40 ns z CS High Time 2 7 5 5 80 ns 1 CS Setup Time 2 7 5 5 80 ns si CS Hold Time 2 7 5 5 80 ns su Data In Setup Time 2 7 5 5 5 ns H Data In Hold Time 2 7 5 5 20 ns p Hold Setup Time 2 7 5 5 40 ns n Hold Hold Time 2 7 5 5 40 ns V Output Valid 2 7 5 5 0 40 ns ko Output Hold Time 2 7 5 5 0 ns z Hold to Output Lovv Z 2 7
14. select a device the read op code is transmitted via the SI line follovved by the byte address to be read see Table 10 Upon completion any data on the Sl line vvill be ignored The data D7 DO at the spec ified address is then shifted out onto the SO line f only one byte is to be read the CS line should be driven high after the data comes out The read sequence can be contin ued since the byte address is automatically incremented and data vvill continue to be shifted out VVhen the highest address is reached the address counter vvill roll over to the lovvest address allovving the entire memory to be read in one continuous read ecycle VVRITE SEQUENCE VVRITE In order to program the AT25128A 256A tvvo separate instructions must be executed First the device must be vvrite enabled via the VVREN instruction Then a VVrite instruction may be executed Also the address of the memory location s to be programmed must be outside the protected address field location AT25128A 256A mann 5088F SEEPR 2 07 selected by the block vvrite protection level During an internal vvrite eycle all commands vvill be ignored except the RDSR instruction A Vvrite instruction requires the follovving sequence After the CS line is pulled lovv to select the device the VVR TE op code is transmitted via the SI line follovved by the byte address and the data D7 D to be programmed see Table 10 Programming vill start after the CS pin is brought hi
15. vrite protection bits indicate the extent of protection employed These bits are set by using the VVRSR instruction Table 6 Status Register Format Bit 7 Bit 0 Bit Bit Bit4 Bit3 Bit2 Bitt X X X BP1 BP0 VVEN RDY VVPEN RDY Table 7 Read Status Register Bit Definition Bit Definition Bit 0 RDY Bit 0 0 RDY indicates the device is ready Bit 0 1 indicates the vvrite eycle is in progress Bit 1 VVEN Bit 1 O indicates the device is not VVRITE ENABLED Bit 1 z 1 indicates the device is vvrite enabled Bit 2 BPO See Table 8 Bit 3 BP1 See Table 8 Bits 4 6 are O s vvhen device is not in an internal vvrite eycle Bit 7 VVPEN See Table 9 Bits 0 7 are 1 s during an internal vvrite eycle VVR TE STATUS REGI STER VVRSR The VVRSR instruction allovvs the user to select one of four levels of protection The AT25128A 256A is divided into four array segments Almer AlmEr Top quarter top half or all of the memory segments can be protected Any of the data vvithin any selected segment vvill therefore be read only The block vvrite protection levels and corresponding status register control bits are shovvn in Table 8 Bits BPO BP1 and VVPEN are nonvolatile cells that have the same properties and func tions as the regular memory cells e g VVREN tc RDSR Table 8 Block VVrite Protect Bits Status Register Bits
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ATMEL AT25128A/AT25256A Manual