ATMEL AT24HC02B Manual
Contents
1. AMEL 12 Revision History Doc Rev Date Comments 5134E 3 2008 Added part marking scheme Updated to new template Removed reference to Waffle Pack on page 1 5134D 4 2007 Added lings i Ordering Code table Shrink Pin Diagram Change to Table 5 Added Two Wire Software Reset Removed LSB from figures 5134C 3 2007 Pg 12 Change to new catalog part number scheme 5134B 9 2006 Revision history implemented Added Preliminary status to datasheet 5134E SEEPR 3 082. n x P 7 M RA A A A A S LC C C C C B W K K K K K The data word address lower three 2K bits are internally incremented following the receipt of each data word The higher data word address bits are not incremented retaining the memory page row location When the word address internally generated reaches the page boundary the following byte is placed at the beginning of the same page If more than eight 2K data words are transmitted to the EEPROM the data word address will roll over and previous data will be overwritten ACKNOWLEDGE POLLING Once the internally timed write cycle has started and the EEPROM inputs are disabled acknowledge polling can be initiated This involves sending a start condition followed by the device address word The read write bit is representative of the operation desired Only if the internal write cycle has completed will the EEPROM respond with a 0 allowing the read or write sequence to continue AMEL o AMEL 8 Read Operations 10 Read operations are initiated the same way as write operations with the exception that the read write select bit in the device address word is set to 1 There are three read operations current address read random address read and sequential read CURRENT ADDRESS READ The internal data word address counter maintains the last address accessed during the last read or write operation incremented by one This address stays valid between operat
3. unless otherwise noted 1 8 2 5 2 7 5 0 volt Symbol Parameter Min Max Min Max Units fscL Clock Frequency SCL 400 1000 kHz tLow Clock Pulse Width Low 1 2 0 4 us tuIGH Clock Pulse Width High 0 6 0 4 us ti Noise Suppression Time 50 40 ns taa Clock Low to Data Out Valid 0 1 0 9 0 05 0 55 us ale Time the bus must be free before a new 12 05 us transmission can start tupsta Start Hold Time 0 6 0 25 us tsu sTA Start Setup Time 0 6 0 25 us tup pat Data In Hold Time 0 0 us tsu DAT Data In Setup Time 100 100 ns ta Inputs Rise Time 0 3 0 3 us tr Inputs Fall Time 300 100 ns tsu sto Stop Setup Time 0 6 25 us ton Data Out Hold Time 50 50 ns twr Write Cycle Time 5 5 ms Endurance 5 0V 25 C Byte Mode 1 Million Write Cycles Note 1 This parameter is ensured by characterization only AIMEL i 5134E SEEPR 3 08 T AMEL 5 Device Operation CLOCK and DATA TRANSITIONS The SDA pin is normally pulled high with an external device Data on the SDA pin may change only during SCL low time periods see Figure 5 1 Data changes during SCL high periods will indicate a start or stop condition as defined below Figure 5 1 Data Validity SDA SCL C DATA STABLE DATA STABLE DATA CHANGE START CONDITION A high to low transition of SDA with SCL high is a start condition that must precede any other command see Figure 5 2 Figure 5 2 S
4. 11 04 Week 4 Sa 8 2008 2 2012 A T M L H Y W W 9 2009 se 2013 lt Si 50 Week 50 H 2 B 1 52 Week 52 Lot Number Lot Number to Use ALL Characters in Marking BOTTOM MARK Pin 1 Indicator Dot No Bottom Mark AIMEL 13 5134E SEEPR 3 08 T AMEL 10 3 8 TSSOP TOP MARK Pin 1 Indicator Dot Y SEAL YEAR WW SEAL WEEK 6 2006 0 2010 02 Week 2 e Ga a 7 2007 1 2011 04 Week 4 H Y W W 8 2008 2 2012 9 2009 32 2013 H 2 B el 50 Week 50 5 4 52 Week 52 BOTTOM MARK ee se ceo P H a S54 eos a r A A A A A A A S S lt Pin 1 Indicator 5134E SEEPR 3 08 11 Packaging Information 11 1 8P3 PDIP ll Top View c a eA End View COMMON DIMENSIONS Unit of Measure inches SYMBOL NOM MAX 0 210 0 130 0 195 0 018 0 022 0 060 0 070 0 039 0 010 0 365 b2 _ a 0 310 j b 0 250 0 100 BSC 0 300 BSC 0 115 0 130 Side View This drawing is for general information only refer to JEDEC Drawing MS 001 Variation BA for additional information Dimensions A and L are m
5. 2B 3 Pin Description 5134E SEEPR 3 08 SERIAL CLOCK SCL The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device SERIAL DATA SDA The SDA pin is bidirectional for serial data transfer This pin is open drain driven and may be wire ORed with any number of other open drain or open collector devices DEVICE PAGE ADDRESSES A2 A1 AO The A2 A1 and AO pins are device address inputs that must be hardwired for the AT24HC02B As many as eight 2K devices may be addressed on a single bus system Device addressing is discussed in detail under Device Addressing page 8 WRITE PROTECT WP The AT24HC02B has a WP pin that provides hardware data protec tion The WP pin allows normal read write operations when connected to ground GND When the WP pin is connected to Voc the write protection feature is enabled and operates as shown Table 3 1 Write Protect Part of the Array Protected WP Pin Status 24HC02B At Voc Upper Half 1K Array At GND Normal Read Write Operations AMEL AMEL 4 Memory Organization AT24HC02B 2K SERIAL EEPROM The 2K is internally organized with 32 pages of 8 bytes each Random word addressing requires an 8 bit data word address Table 4 1 Pin Capacitance Applicable over recommended operating range from Ta 25 C f 1 0 MHz Vec 1 8V Symbol Test Condition Max Units Conditions Gio Input Output Ca
6. 7 R DEVICE E WORD R ADDRESS A O ADDRESS ADDRESS n D P T T i ok de i TT Cok hae LO a SDA LINE ji l po pep AE EE es A e le A M RAM A M A DATA n N S CS Cc Ss C O B WKB K B K A C K DUMMY WRITE 5134E SEEPR 3 08 mes AV 24HC02B SEQUENTIAL READ Sequential reads are initiated by either a current address read or a ran dom address read After the microcontroller receives a data word it responds with an acknowledge As long as the EEPROM receives an acknowledge it will continue to increment the data word address and serially clock out sequential data words When the memory address limit is reached the data word address will roll over and the sequential read will continue The sequential read operation is terminated when the microcontroller does not respond with a 0 but does generate a following stop condition see Figure 8 3 Figure 8 3 Sequential Read R S E A A A T DEVICE A C C C O ADDRESS D K K K P i T SDA LINE E L R A DATA n DATA n 1 DATA n 2 DATA n x N G O WK A C K AMEL n 5134E SEEPR 3 08 AMEL 9 AT24HC02B Ordering Information Ordering Code Voltage Package Operation Range AT24HC02B PU Bulk form only 1 8 8P3 AT24HCO02BN SH B NiPdAu Lead Finish 1 8 8S1 Lead free Halogen free Industrial Temperature SH T70 Ni ini AT24HC02BN
7. BDTIC www BDTIC com ATMEL 1 Features e Write Protect Pin for Hardware Data Protection Utilizes Different Array Protection Compared to the AT24C02B Low voltage and Standard voltage Operation 1 8 Vec 1 8V to 5 5V e Internally Organized 256 x 8 2K e Two wire Serial Interface Schmitt Trigger Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol e 1 MHz 5V and 400 kHz 1 8V 2 5V 2 7V Clock Rate e 8 byte Page Partial Page Writes Allowed Self timed Write Cycle 5 ms Max e High Reliability Endurance One Million Write Cycles Data Retention 100 Years 8 lead PDIP 8 lead JEDEC SOIC and 8 lead TSSOP Packages Die Sales Wafer Form Tape and Reel and Bumped Wafers 2 Description The AT24HC02B provides 2048 bits of serial electrically erasable and programmable read only memory EEPROM organized as 256 words of 8 bits each The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential The AT24HC02B is available in space saving 8 lead PDIP 8 lead JEDEC SOIC and 8 lead TSSOP packages and is accessed via a two wire serial interface In addition the entire family is available in 1 8V 1 8V to 5 5V version Table 2 1 Pin Configuration Pin Name Function 8 lead TSSOP A0 A2 Address Inputs y A0 1 8h VCC SDA Serial Data A102 70 we SCL Serial Clock Input A2 03 6 O SCL GND 4 5 0O SDA
8. DITION CONDITION Notes 1 The write cycle time twp is the time from a valid stop condition of a write sequence to the end of the internal clear write cycle AMEL 7 5134E SEEPR 3 08 Figure 5 6 DATA OUT Output Acknowledge DAS VAL DATA IN x X START ACKNOWLEDGE 6 Device Addressing The 2K EEPROM device requires an 8 bit device address word following a start condition to enable the chip for a read or write operation as shown in Figure 6 1 Figure 6 1 Device Address ax 1 o Jo Ad Ai Ao MSB SB The device address word consists of a mandatory 1 O sequence for the first four most signif icant bits as shown This is common to all the EEPROM devices The next three bits are the A2 A1 and AO device address bits for the 2K EEPROM These three bits must compare to their corresponding hardwired input pins The eighth bit of the device address is the read write operation select bit A read operation is ini tiated if this bit is high and a write operation is initiated if this bit is low Upon a compare of the device address the EEPROM will output a O If a compare is not made the chip will return to a standby state 5134E SEEPR 3 08 mes AV 24HC02B 7 Write Operations Figure 7 2 Page Write SDA LINE 5134E SEEPR 3 08 BYTE WRITE A write operation requires an 8 bit data word address following the device address word and acknowledgement Upon receipt of t
9. SH T NiPdAu Lead Finish 1 8 8S1 40 C to 85 C AT24HC02B TH B NiPdAu Lead Finish 1 8 8A2 AT24HC02B TH T NiPdAu Lead Finish 1 8 8A2 Industrial T t AT24HC02B W 11 1 8 Die Sale oa dea 40 C to 85 C Notes 1 B denotes bulk 2 T denotes tape and reel SOIC 4K per reel TSSOP 5K per reel 3 Available in tape and reel and wafer form order as SL788 for inkless wafer form Bumped die available upon request Please contact Serial Interface Marketing Package Type 8P3 8 lead 0 300 Wide Plastic Dual Inline Package PDIP 8S1 8 lead 0 150 Wide Plastic Gull Wing Small Outline JEDEC SOIC 8A2 8 lead 4 4 mm Body Plastic Thin Shrink Small Outline Package TSSOP Options 1 8 Low Voltage 1 8V to 5 5V 5134E SEEPR 3 08 mes AV 24HC02B 10 Part marking scheme 10 1 8 PDIP TOP MARK Seal Year Y SEAL YEAR WW SEAL WEEK Seal Week 6 2006 0 2010 02 Week 2 7 2007 1 2011 04 Week 4 sas 8 2008 2 2012 A T M L H Y W W 9 2009 35 2013 E 50 Week 50 H 2 B I 52 Week 52 ll Lot Number Lot Number to Use ALL Characters in Marking BOTTOM MARK Pin 1 Indicator Dot No Bottom Mark 10 2 8 SOIC TOP MARK Seal Year Y SEAL YEAR WW SEAL WEEK Seal Week 6 2006 O 2010 02 Week 2 7 2007 1 20
10. WP Write Protect 8 lead PDIP J AOL 1 8 O VCC A192 7 O WP A2 03 6 O SCL GND O 4 5 0O SDA 8 lead SOIC AO 1 8 VCC A1 2 7 WP A2 3 6 SCL GND 4 5 SDA AMEL T Two wire Serial EEPROM 2K 256 x 8 AT24HC02B Rev 5134E SEEPR 3 08 AMEL Absolute Maximum Ratings Operating Temperature cccccscesscssseesssseesssees 55 C to 125 C NOTICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam Storage Temperature ce eeeeeececeeeeeteeteteeeeees 65 C to 150 C age to the device This is a stress rating only and functional operation of the device at these or any Voltage on Any Pin other conditions beyond those indicated in the with Respect to Ground ooccoccncccococicicoconccncncnononos 1 0V to 7 0V operational sections of this specification is not implied Exposure to absolute maximum rating Maximum Operating Voltage cceeceeeeeseeseteeeeeeenees 6 25V conditions for extended periods may affect device reliability DC Output Current ecececeeeeeeeeeneeeeeeeeeeeneeeeaeeeneetaas 5 0 mA Figure 2 1 Block Diagram VCC GND WP SDA SERIAL CONTROL H V PUMP TIMING LOGIC LOAD DEVICE COMP DATA RECOVERY ADDRESS 7 COMPARATOR A A A DATA WORD m EEPROM A ADDR COUNTER gt SERIAL MUX Dn 0 Pp Dour 5134E SEEPR 3 08 mes AV 24HC0
11. easured with the package seated in JEDEC seating plane Gauge GS 3 D D1 and E1 dimensions do not include mold Flash or protrusions Mold Flash or protrusions shall not exceed 0 010 inch E and eA measured with the leads constrained to be perpendicular to datum Pointed or rounded lead tips are preferred to ease insertion b2 and b3 maximum dimensions do not include Dambar protrusions Dambar protrusions shall not exceed 0 010 0 25 mm 01 09 02 TITLE DRAWING NO REV MEL 2325 Orchard Parkway 8P3 8 lead 0 300 Wide Body Plastic Dual AIMEL San Jose CA 95131 In line Package PDIP oe B AIMEL 5134E SEEPR 3 08 T O AT24HC02B 15 AMEL 11 2 8S1 JEDEC SOIC g L Top View End View B COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX A 1 35 1 75 Al 0 10 0 25 b 0 31 0 51 0 17 0 25 4 80 5 00 3 81 3 99 5 79 6 20 Side View 127 BSC 0 40 0 D Note These drawings are for general information only Refer to JEDEC Drawing MS 012 Variation AA for proper dimensions tolerances datums etc 10 7 03 TITLE DRAWING NO REV AMMEL 1190 E Cheyenne Min Blvd 8S1 8 lead 0 150 Wide Body Plastic Gull Wing pel 5 a Colorado Spring
12. his address the EEPROM will again respond with a 0 and then clock in the first 8 bit data word Following receipt of the 8 bit data word the EEPROM will output a 0 and the addressing device such as a microcontroller must terminate the write sequence with a stop condition At this time the EEPROM enters an inter nally timed write cycle twp to the nonvolatile memory All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete see Figure 7 1 on page 9 Figure 7 1 Byte Write 7 A i T R DEVICE L Q ADDRESS WORD ADDRESS DATA SDA LINE M RA A A S iC C C B W K K K PAGE WRITE The 2K EEPROM is capable of an 8 byte page write A page write is initiated the same as a byte write but the microcontroller does not send a stop condition after the first data word is clocked in Instead after the EEPROM acknowledges receipt of the first data word the microcontroller can transmit up to seven 2K more data words The EEPROM will respond with a 0 after each data word received The microcontroller must terminate the page write sequence with a stop condition see Figure 7 2 i Y A l S R DEVICE E O ADDRESS WORD ADDRESS n DATA n DATA n 1 WN DATA
13. ions as long as the chip power is maintained The address roll over during read is from the last byte of the last memory page to the first byte of the first page The address roll over during write is from the last byte of the current page to the first byte of the same page Once the device address with the read write select bit set to 1 is clocked in and acknowledged by the EEPROM the current address data word is serially clocked out The microcontroller does not respond with an input 0 but does generate a following stop condition see Figure 8 1 Figure 8 1 Current Address Read S R S A E T T DEVICE A 9 ADDRESS SDA LINE M RA DATA N S LE O B W K A C K RANDOM READ A random read requires a dummy byte write sequence to load in the data word address Once the device address word and data word address are clocked in and acknowledged by the EEPROM the microcontroller must generate another start condition The microcontroller now initiates a current address read by sending a device address with the read write select bit high The EEPROM acknowledges the device address and serially clocks out the data word The microcontroller does not respond with a 0 but does generate a following stop condition see Figure 8 2 Figure 8 2 Random Read S w S T R T R s A A DEVICE E
14. pacitance SDA 8 pF Vo OV CiN Input Capacitance Ao Ay A gt SCL 6 pF Vin OV Note 1 This parameter is characterized and is not 100 tested Table 4 2 DC Characteristics Applicable over recommended operating range from Ta 40 C to 85 C Vec 1 8V to 5 5V unless otherwise noted Symbol Parameter Test Condition Min Typ Max Units Voct Supply Voltage 1 8 5 5 V Veco Supply Voltage 25 5 5 V Vecs Supply Voltage 2 7 5 5 V Voca Supply Voltage 45 5 5 V lcc Supply Current Vec 5 0V READ at 100 kHz 0 4 1 0 mA loc Supply Current Vec 5 0V WRITE at 100 kHz 2 0 3 0 mA logs Standby Current Voc 1 8V Vin Vcc Or Vss 0 6 3 0 pA logo Standby Current Veg 2 5V Vin Voc OF Vss 1 4 4 0 pA lsB3 Standby Current Vec 2 7V Vin Voc OF Vss 1 6 4 0 pA Ispa Standby Current Vec 5 0V Vin Voc OF Vss 8 0 18 0 yA lo Input Leakage Current Vin Voc Or Vss 0 10 3 0 pA llo Output Leakage Current Vout Voc Or Vss 0 05 3 0 pA Vi Input Low Level 0 6 Voc X 0 3 V Vin Input High Level Voc X 0 7 Voc 0 5 V VoLo Output Low Level Vec 3 0V lo 2 1 mA 0 4 V Vout Output Low Level Vcc 1 8V lo 0 15 mA 0 2 V Note 1 Vi min and Vj max are reference only and are not tested mes AV 24HC02B Table 4 3 AC Characteristics Applicable over recommended operating range from Ta 40 C to 85 C Voc 1 8V to 5 5V CL 1 TTL Gate and 100 pF
15. s CO 80906 Small Outline JEDEC SOIC 16 AT24HC02B 5134E SEEPR 3 08 AT24HC02B 11 3 8A2 TSSOP Pin 1 indicator this corner N Top View End View COMMON DIMENSIONS Unit of Measure mm SYMBOL 6 40 BSC Hao _ of __le A2 1 00 D 0 30 0 65 BSC Side View 0 60 0 75 L1 1 00 REF al This drawing is for general information only Refer to JEDEC Drawing MO 153 Variation AA for proper dimensions tolerances datums etc Dimension D does not include mold Flash protrusions or gate burrs Mold Flash protrusions and gate burrs shall not exceed 0 15 mm 0 006 in per side Dimension E1 does not include inter lead Flash or protrusions Inter lead Flash and protrusions shall not exceed 0 25 mm 0 010 in per side Dimension b does not include Dambar protrusion Allowable Dambar protrusion shall be 0 08 mm total in excess of the b dimension at maximum material condition Dambar cannot be located on the lower radius of the foot Minimum space between protrusion and adjacent lead is 0 07 mm Dimension D and E1 to be determined at Datum Plane H 5 30 02 TITLE DRAWING NO REV 2325 Orchard Parkway 8A2 8 lead 4 4 mm Body Plastic r San Jose CA 95131 Thin Shrink Small Outline Package TSSOP SA2 2 AIMEL 17 5134E SEEPR 3 08 T O
16. tart and Stop Definition SDA SCL START STOP STOP CONDITION A low to high transition of SDA with SCL high is a stop condition After a read sequence the stop command will place the EEPROM in a standby power mode see Fig ure 5 2 ACKNOWLEDGE All addresses and data words are serially transmitted to and from the EEPROM in 8 bit words The EEPROM sends a 0 to acknowledge that it has received each word This happens during the ninth clock cycle STANDBY MODE The AT24HC02B features a low power standby mode that is enabled a upon power up and b after the receipt of the Stop bit and the completion of any internal operations AT24HC02B 2 WIRE SOFTWARE RESET After an interruption in protocol power loss or system reset any two wire part can be reset by following these steps a Clock up to 9 cycles b Look for SDA high in each cycle while SCL is high c Create a start condition as SDA is high The device is ready for next communication after above steps have been completed Figure 5 3 Software Reset Start bit Dummy Clock Cycles Start bit Stop bit gt lt gt lt Sor SDA Figure 5 4 Bus Timing HIGH k ta t t LOW LOW SCL AN NS a et e Losa tho DAT Tuns toy STO SDA IN 7 toy SDA OUT Figure 5 5 Write Cycle Timing SDA 8th BIT ACK WORDn t 1 gt wr STOP START CON
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ATMEL AT24HC02B Manual