ATMEL AT27LV010A handbook
Contents
1. MIN NOM 4 191 2 286 0 508 17 399 16 510 17 399 Notes 1 This package conforms to JEDEC reference MS 018 Variation AC 2 Dimensions D1 and E1 do not include mold protrusion 16 510 Allowable protrusion is 010 0 254 mm per side Dimension D1 14 986 and E1 include mold mismatch and are measured at the extreme 0 660 material condition at the upper or lower parting line 3 Lead coplanarity is 0 004 0 102 mm maximum 0 330 1 270 TYP 10 04 01 DRAWING NO REV 44J B TITLE AMEL S peas a 443 44 lead Plastic J leaded Chip Carrier PLCC AMEL n 03111 EPROM 12 07 AMEL 20 2 40P6 PDIP SEATING PLANE 7 e t COMMON DIMENSIONS SS 0 15 REF Unit of Measure mm ios meal SYMBOL MIN NOM eB Al 0 381 52 070 15 240 13 462 0 356 1 041 Notes 1 This package conforms to JEDEC reference MS 011 Variation AC 2 Dimensions D and E1 do not include mold Flash or Protrusion 3 048 Mold Flash or Protrusion shall not exceed 0 25 mm 0 010 0 203 E 15 494 2 540 TYP 09 28 01 TITLE DRAWING NO REV2. Temperature Under BiaS oooinnininininnnc 55 C to 125 C NOTICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam Storage Temperature ceeeceeeeeeeteeeeeeetees 65 C to 150 C age to the device This is a stress rating only and functional operation of the device at these or any Voltage on Any Pin with other conditions beyond those indicated in the Respect to Ground eeecceeeceeseseeeeeneeeneetens 2 0V to 7 0V operational sections of this specification is not implied Exposure to absolute maximum rating Voltage on A9 with conditions for extended periods may affect device Respect to Ground c cococccconocinoncnnonicnnnnnnronos 2 0V to 14 0V reliability Vpp Supply Voltage with Respect to Ground moocococococononcinineneninnnnnnnonaso 2 0V to 14 0V Note 1 Maximum voltage is 0 6V DC which may undershoot to 2 0V for pulses of less than 20 ns Maximum output pin voltage is Vec 0 75V DC which may overshoot to 7 0V for pulses of less than 20 ns AMEL 03111 EPROM 12 07 6 Operating Modes Mode Pin CE OE Ai Ver Outputs Read Vi Vi Ai x Dour Output Disable X Vin X X High Z Standby Vin X X xo High Z Rapid Program Vi Vin Ai Vpp Dn PGM Verify Vin Vit Ai Vpp Dour PGM Inhibit Vin Vin X Vpp High Z A9 V Product Identification Vi Vi AO VH or Vi Voc Identification Code A1 A17 V Notes 1 X can
3. 27 02 013 15 26 03 04 A5 LEIAN AAANA 012716 251304 POOOOOOOOOO 011 17 24105 SNA53aUuo2I232z 010 18 23 06 OOOO z lt x lt o9 cC 19 221507 08 20 21 GND 2 2 40 lead PDIP Top View VPP C1 VCC CE Q2 A17 01503 A16 01404 A15 01305 A14 01206 A13 01107 A12 o1008 A11 o9 09 A10 08 7 10 A9 GND 11 GND 07 12 A8 o6 13 A7 05014 A6 040 15 A5 03016 A4 02017 A3 01018 A2 007 19 Al OE 20 AO 2 AT27C4096 NN 0311I EPROM 12 07 a AT 2 70 4096 3 System Considerations Switching between active and standby conditions via the Chip Enable pin may produce tran sient voltage excursions Unless accommodated by the system design these transients may exceed datasheet limits resulting in device non conformance At a minimum a 0 1 F high frequency low inherent inductance ceramic capacitor should be utilized for each device This capacitor should be connected between the V and Ground terminals of the device as close to the device as possible Additionally to stabilize the supply voltage level on printed circuit boards with large EPROM arrays a 4 7 uF bulk electrolytic capacitor should be utilized again connected between the V and Ground terminals This capacitor should be positioned as close as possible to the point where the power supply is connected to the array 4 Block Diagram VCC gt DATA OUTPUTS GND 00 015 VPP OE OUTPUT EE BUFFERS AO A17 ADDRESS INPUTS 5 Absolute Maximum Ratings
4. be V or Vij 2 Refer to the Programming characteristics 3 Vp 12 0 0 5V 4 Two identifier words may be selected All Ai inputs are held low V1 except A9 which is set to Vy and AO which is toggled low Vj to select the Manufacturer s Identification word and high Vj to select the Device Code word Standby V current lsg is specified with Vpp Voc Voc gt Vpp will cause a slight increase in Isg 7 DCand AC Operating Conditions for Read Operation AT27C4096 55 90 Industrial Operating Temperature Case 40 C 85 C 40 C 85 C Voc Power Supply 5V 10 5V 10 8 DC and Operating Characteristics for Read Operation 4 Symbol Parameter Condition Min Max Units lo Input Load Current Vin OV to Vec 1 yA lo Output Leakage Current Vout OV to Vec 5 yA lpp Vpp Read Standby Current Vpp Voc 10 uA CMOS lss 100 pA CE Vec 0 3V Isp Vcc Standby Current lso TTL ni loc Voc Active Current f 5 MHz lour 0 mA CE V 40 mA Vi Input Low Voltage 0 6 0 8 V Vin Input High Voltage 2 0 Voc 0 5 V VoL Output Low Voltage lo 2 1 mA 0 4 V Vou Output High Voltage lop 400 yA 2 4 V Notes 1 V must be applied simultaneously or before Vpp and removed simultaneously or after Vpp 2 Vpp may be connected directly to Voc except during programming The supply current would then be the sum of l and lpp a AT 2
5. pulse width is used to program The address is set to the first location Voc is raised to 6 5V and Vpp is raised to 13 0V Each address is first programmed with one 50 us CE pulse without verification Then a verification reprogramming loop is executed for each address In the event a word fails to pass verification up to 10 successive 50 us pulses are applied with a verification after each pulse If the word fails to verify after 10 pulses have been applied the part is considered failed After the word verifies properly the next address is selected until all have been checked Vpp is then lowered to 5 0V and Vec to 5 0V All words are read again and compared with the original data to determine if the device passes or fails ADDR FIRST LOCATION Y Vos 6 5V Vop 13 0V Y PROGRAM ONE 50 uS PULSE INCREMENT NO LAST ADDRESS ADDR YES ADDR FIRST LOCATION INCREMENT X 0 ADDRESS FAIL VEBIEY INCREMENT X WORD NO PROGRAM ONE 50 uS PULSE YES SS Veo 5 0V Vpp 5 0V COMPARE ALL WORDS TO ORIGINAL DATA DEVICE PASSED AMEL 19 Ordering Information 19 1 Standard Package AIMEL EA O Icc mA tacc ns Active Standby Ordering Code Package Operation Range 55 40 0 1 AT27C4096 55Jl 44J Industrial AT27C
6. 4096 55PI 40P6 40 C to 85 C AT27C4096 55VI 40v 90 40 0 1 AT27C4096 90Jl 44J Industrial AT27C4096 90PI 40P6 40 C to 85 C AT27C4096 90VI 40v Note Not recommended for new designs Use Green package option 19 2 Green Package Pb Halide free lcc mA tacc ns Active Standby Ordering Code Package Operation Range 55 40 0 1 AT27C4096 55JU 44J Industrial AT27C4096 55PU 40P6 40 C to 85 C 90 40 0 1 AT27C4096 90JU 44J Industrial AT27C4096 90PU 40P6 40 C to 85 C Note 1 The 40 lead VSOP package is not recommended for new designs Package Type 44 lead Plastic J Leaded Chip Carrier PLCC 40P6 40 lead 0 600 Wide Plastic Dual Inline Package PDIP 40V 40 lead Plastic Thin Small Outline Package VSOP 0311I EPROM 12 07 a AT 2 704096 20 Packaging Information 20 1 44J PLCC 1 14 0 045 X 45 PIN NO 1 1 14 0 045 X 45 0 318 0 0125 t DEMTEER 0 191 0 0075 i l 0 51 0 020 MAX 45 MAX 3X J COMMON DIMENSIONS Unit of Measure mm
7. 70 4096 9 AC Characteristics for Read Operation AT27C4096 55 90 Symbol Parameter Condition Min Max Min Max Units tace Address to Output Delay CE 0E V 55 90 ns toe CE to Output Delay OE V 55 90 ns toe OE to Output Delay CE V 20 35 ns OE or CE High to Output Float Whichever 1 tor Occurred First a ns a Output Hold from Address CE or OE Whichever gt 0 be OH Occurred First Note 1 See the AC Waveforms for Read Operation diagram 10 AC Waveforms for Read Operation ADDRESS S ADDRESS VALID X CE Y ICE o toe OE DF taco OH OUTPUT wae OUTPUT VALID Notes 0311I EPROM 12 07 AMEL Timing measurement references are 0 8V and 2 0V Input AC drive levels are 0 45V and 2 4V unless otherwise specified OE may be delayed up to tog tog after the falling edge of CE without impact on tce OE may be delayed up to tace tog after the address is valid without impact on tacc This parameter is only sampled and is not 100 tested Output float is defined as the point when data is no longer driven AMEL 11 Input Test Waveforms and Measurement Levels For 55 devices only 3 0V ACO Ny AC DRIVING lt EOS MEASUREMENT LEVELS S SS LEVEL 0 0V d S tr tt lt 5 ns 10 to 90 For 90 devices 2 4V JZ ac A FP A DRIVING lt X MEASUREMENT LEVELS N 08 LEVEL 0 45V i E tr te lt 20 n
8. BDTIC www BDTIC com ATMEL Features e Fast Read Access Time 55 ns e Low Power CMOS Operation 100 pA Maximum Standby 40 mA Maximum Active at 5 MHz e JEDEC Standard Packages 40 lead PDIP 44 lead PLCC 40 lead VSOP Direct Upgrade from 512 Kbit 1 Mbit and 2 Mbit AT27C516 AT27C1024 and AT27C2048 EPROMs e 5V 10 Power Supply High Reliability CMOS Technology 2 000V ESD Protection 200 mA Latchup Immunity e Rapid Programming Algorithm 50 us Word Typical e CMOS and TTL Compatible Inputs and Outputs Integrated Product Identification Code Industrial Temperature Range Green Pb Halide free Packaging Option 1 Description The AT27C4096 is a low power high performance 4 194 304 bit one time program mable read only memory OTP EPROM organized 256K by 16 bits It requires a single 5V power supply in normal read mode operation Any word can be accessed in less than 55 ns eliminating the need for speed reducing WAIT states The x16 organi zation makes this part ideal for high performance 16 and 32 bit microprocessor systems In read mode the AT27C4096 typically consumes 15 mA Standby mode supply cur rent is typically less than 10 yA The AT27C4096 is available in industry standard JEDEC approved one time pro grammable OTP plastic PDIP PLCC and VSOP packages The device features two line control CE OE to eliminate bus contention in high speed systems With high density 256K word stor
9. MEL 2325 Orchard Parkway 40P6 40 lead 0 600 15 24 mm Wide Plastic Dual AIMEL San Jose CA 95131 Inline Package PDIP 12 AT27C4096 0311I EPROM 12 07 AT27C4096 20 3 40V VSOP PIN 1 LIM AMANDO anos ol Pin 1 Identifier JOVI YUU vodo UUTUTUUUUUT __GAGE PLANE COMMON DIMENSIONS Unit of Measure mm SYMBOL NOM MAX 1 20 0 15 1 00 1 05 Notes 1 This package conforms to JEDEC reference MO 142 Variation CA 14 00 14 20 2 Dimensions D1 and E do not include mold protrusion Allowable protrusion on E is 0 15 mm per side and on D1 is 0 25 mm per side 12 40 12 50 3 Lead coplanarity is 0 10 mm maximum 10 00 10 10 0 60 0 70 0 25 BASIC 0 22 0 27 0 21 0 50 BASIC 10 18 01 TITLE DRAWING NO REV 2325 Orchard Parkway P i AMEL 40V 40 lead 10 x 14 mm Package Plastic Thin Small Outline 40V See San Jose CA 95131 Package Type VSOP 0 B AMEL 1 0311I EPROM 12 07
10. age capability the AT27C4096 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media Atmel s AT27C4096 has additional features that ensure high quality and efficient pro duction use The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming Programming time is typically only 50 us word The Integrated Product Identification Code electronically identifies the device and manufacturer This feature is used by industry standard programming equipment to select the proper programming algorithms and voltages AIMEL O T E 4 Megabit 256K x 16 OTP EPROM AT27C4096 0311I EPROM 12 07 AMEL 2 Pin Configurations Pin Name Function AO A17 Addresses 00 015 Outputs CE Chip Enable OE Output Enable NC No Connect Note Both GND pins must be connected 2 1 44 lead PLCC Top View 2 3 40 lead VSOP Type 1 Top View o 10 a Qrnowd SOobS SLES a9 c1 40 GND nono Aio 2 39 7 A8 oO O We y O Ae O A11 3 38 A7 012 O A13 a12 c4 371 A6 O11 A12 A13 5 36 JA5 010 A11 A14 6 3517 A4 o9 A10 A15 C7 341 A3 A16 8 33 A2 oe A9 A17 9 32 Al GND GND VCC 10 31 AO NC NC VPP O 11 30 OE 07 A8 CE 12 29 o0 06 A7 015 C 13 28 01 O5 AG 014 14
11. s 10 to 90 12 Output Test Load 1 3V L 1N914 3 3K OUTPUT PN L V Note CL 100 pF including jig capacitance 13 Pin Capacitance f 1 MHz T 25 C Symbol Typ Max Units Conditions Cin 4 10 pF Vin OV Cour 8 12 pF Vout OV Note 1 Typical values for nominal supply voltage This parameter is only sampled and is not 100 tested 0311I EPROM 12 07 14 Programming Waveforms AT27C4096 READ PROGRAM VERIFY VIH ADDRESS VIL gt ADDRESS STABLE taS toe aa taH MH TN DATA OUT DATA VIL DAAN VALID tps H DH __ a DFP 13 0V Vpp TAK tvPS 6 5V Vec 5 0V tes VIH CE NO VIL tpw tOES a VIH OE VIL Notes 1 The Input Timing Reference is 0 8V for Vi and 2 0V for Vj 2 tog and tprp are characteristics of the device but must be accommodated by the programmer 3 When programming the AT27C4096 a 0 1 uF capacitor is required across Vpp and ground to suppress spurious voltage transients AMEL 03111 EPROM 12 07 AMEL 15 DC Programming Characteristics T 25 45 C Vec 6 5 0 25V Vpp 13 0 0 25V Limits Symbol Parameter Test Conditions Min Max Units lo Input Load Current Vin Viv Vin HO pA Vit Input Low Level 0 6 0 8 V Vin Input High Level 2 0 Vcc 0 7 VoL Output Lo
12. w Voltage lo 2 1 mA 0 4 V VoH Output High Voltage lon 400 pA 2 4 V loco Voc Supply Current Program and Verify 50 mA Ippo Vpp Supply Current CE V 30 mA Vip A9 Product Identification Voltage 11 5 12 5 V 16 AC Programming Characteristics Ta 25 5 Vog 6 5 0 25V Vpp 13 0 0 25V Limits Symbol Parameter Test Conditions Min Max Units tas Address Setup Time 2 us toes OE Setup Time 2 us Input Rise and Fall Times tos Data Setup Time 10 to 90 20 ns 2 us tan Address Hold Time 0 us a Data Hold Time Input Pulse Levels 2 us ha OE High to Output Float Delay eevee 0 130 ns tvps Vpp Setup Time Input Timing Reference Level 2 us tvcs Voc Setup Time 0 8V to 2 0V 2 us pw ede dll Output Timing Reference Level pl 2 ai toe Data Valid from OE 0 8V to 2 0V 150 ns ls oe Time During 50 a Notes 1 V must be applied simultaneously or before Vpp and removed simultaneously or after Vpp 2 This parameter is only sampled and is not 100 tested Output Float is defined as the point where data is no longer driven see timing diagram 3 Program Pulse width tolerance is 50 usec 5 17 Atmel s AT27C4096 Intergrated Product Identification Code Pins Codes AO 015 08 07 06 O5 04 03 02 01 00 Hex Data Manufacturer 0 0 0 0 0 1 1 1 1 0 001E Device Type 1 0 1 1 1 1 0 1 0 0 00F4 0311I EPROM 12 07 a AT 2 70 4096 18 Rapid Programming Algorithm 0311I EPROM 12 07 A 50 us CE
Download Pdf Manuals
Related Search
ATMEL AT27LV010A handbook