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ATMEL AT91SAM7A3 handbook (1)

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1. e A MEL 355 6042E ATARM 14 Dec 06 AMEL e TXSYN Tx Sync Interrupt Mask 0 The Tx Sync Interrupt is disabled 1 The Tx Sync Interrupt is enabled RXSYN Rx Sync Interrupt Mask 0 The Rx Sync Interrupt is disabled 1 The Rx Sync Interrupt is enabled 36 91 7 Preliminary memm 6042E ATARM 14 Dec 06 X 7915 7 Preliminary 31 Timer Counter TC 31 1 Overview 6042E ATARM 14 Dec 06 The Timer Counter TC includes three identical 16 bit Timer Counter channels Each channel can be independently programmed to perform a wide range of functions includ ing frequency measurement event counting interval measurement pulse generation delay timing and pulse width modulation Each channel has three external clock inputs five internal clock inputs and two multi purpose input output signals which can be configured by the user Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts The Timer Counter block has two global registers which act upon all three TC channels The Block Control Register allows the three channels to be started simultaneously with the same instruction The Block Mode Register defines the external clock inputs for each channel allowing them to be chained Table 31 1 gives the assignment of the device Timer Counter clock
2. Active Signal Name Function Type Level Comments SPI SPIO MISO SPI MISO Master In Slave Out SPIO_MOSI SPI1_MOSI Master Out Slave In SPIO SPCK SPI1 SPCK SPI Serial Clock SPIO NPCSO SPI NPCSO SPI Peripheral Chip Select 0 y o Low SPIO_NPCS1 SPIO NPCS3 SPI1_NPCS1 SPI1_NPCS3 SPI Peripheral Chip Select Output Low Two wire Interface TWD Two wire Serial Data y o TWCK Two wire Serial Clock y o Analog to Digital Converter ADCO ADO ADCO AD7 E ADC1 ADO ADC1 AD7 Analog Inputs Analog Digital pulled up inputs at reset ADVREFP Analog Positive Reference Analog ADCO ADTRG ADC1 ADTRG ADC Trigger Input CAN Controller CANRXO CANRX1 CAN Inputs Input CANTXO CANTX1 CAN Outputs Output ATMEL 6042E ATARM 14 Dec 06 AMEL 4 Package 4 1 100 lead LQFP Package Outline Figure 4 1 shows the orientation of the 100 lead LQFP package A detailed mechanical description is given in the Mechanical Characteristics section of the full datasheet Figure 4 1 100 LQFP Outline Top View 75 51 100 8 915 Preliminary memm 6042E ATARM 14 Dec 06 2 7915 7 Preliminary 4 2 Pinout Table 4 1 Pinout in 100 lead LQFP Package 1 GND 26 VDDBU 51 PA20 76 PLLRC 2 NRST 27 FWKUP 52 PA21 77 VDDANA 3 TST 28 WKUPO 53 PA22 78 ADVREFP 4 PB13 29 WKUP1 54 PA23 79 GND 5 PB12 30 SHDW 55 PA24 80 PB14 ADCO_
3. re a eges 12 7 Processor and Architecture 13 7 11 ARMTTDMI Processor nennen nnne nennen nnne 13 7 2 Debug and Test Features 13 7 3 Memory Controler 13 7 4 Peripheral DMA Controller 2224 4 1 1 11 0000 nennen nnne nennen 14 9 Dog Q 15 8 1 Embedded Memories 15 8 2 Memory Mapping eret ko Ix E HE ER EE CHER EE ERE EL ERES RE REESE 17 83 Embedded Flash amen cenae enia eedem dec ba 17 9 System Controller usarse DIARI EE XAR rs 19 91 System Controller Mapping sesseseseeeeeeeeeeen nennen nennen 20 AMEL 6042E ATARM 14 Dec 06 AMEL 9 2 Reset Controller ot rtr n eate e Pan e ces cr E PEDE Edo EENE 21 9 3 Clock Generator nnne nennen enne 21 9 4 Power Management Controller essen 21 9 5 Advanced Interrupt Controller 22 9 6 Debug Unit didtnr 23 9 7 Period Interval 23 9 8 Watchdog Timer errare aede dem ed 23 9 9 Real time Timor OA Na EN 23 9 10 Shutdown Controller
4. TCOXCOS TCOXCOS External Clock Signal 0 Selection TCOXCOS Signal Connected to XCO 0 0 TCLKO 0 1 none 1 0 TIOA1 1 1 TIOA2 TC1XC1S External Clock Signal 1 Selection TC1XC1S Signal Connected to XC1 0 0 TCLK1 0 1 none 1 0 TIOAO 1 1 TIOA2 TC2XC2S External Clock Signal 2 Selection TC2XC2S Signal Connected to XC2 0 0 TCLK2 0 1 none 1 0 TIOAO 1 1 TIOA1 A MEL 375 6042E ATARM 14 Dec 06 AMEL 31 6 5 TC Channel Control Register Register Name TC_CCR Access Type Write only 7 6 5 4 3 2 1 0 sr Counter Clock Enable Command 0 No effect 1 Enables the clock if CLKDIS is not 1 CLKDIS Counter Clock Disable Command 0 No effect 1 Disables the clock SWTRG Software Trigger Command 0 No effect 1 software trigger is performed the counter is reset and the clock is started 36 AT9ISAM7A3 Preliminary mm 6042E ATARM 14 Dec 06 7915 7 Preliminary 31 6 6 TC Channel Mode Register Capture Mode Register Name TC Access Type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 1 1 15 14 13 12 11 10 9 8 wave 0 EtrRGEDG 7 6 5 4 3 2 1 0 TCCLKS Clock Selection TCCLKS Clock Selected 0 0 0 TIMER CLO
5. X 7915 7 Preliminary 26 5 I O Lines Programming Example The programing example as shown in Table 26 1 below is used to define the following configuration 4 bit output port on I O lines 0 to 3 should be written in a single write operation open drain with pull up resistor Four output signals on I O lines 4 to 7 to drive LEDs for example driven high and low no pull up resistor Four input signals on I O lines 8 to 11 to read push button states for example with pull up resistors glitch filters and input change interrupts e Four input signals on I O line 12 to 15 to read an external device status polled thus no input change interrupt no pull up resistor no glitch filter I O lines 16 to 19 assigned to peripheral A functions with pull up resistor O lines 20 to 23 assigned to peripheral B functions no pull up resistor I O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull up resistor Table 26 1 Programming Example Register Value to be Written PIO PER 0x0000 FFFF PIO PDR OxOFFF 0000 PIO OER 0x0000 OOFF ODR OxOFFF FFOO PIO IFER 0x0000 0 00 PIO IFDR OxOFFF FOFF PIO SODR 0x0000 0000 PIO CODR OxOFFF FFFF PIO IER OxOFO00 PIO IDR FOFF PIO MDER 0x0000 000F MDDR OxOFFF FFFO PIO PUDR 0 00 0 PIO PUER OxOFOF FFOF PIO ASR OxOFOF 0000 PIO BSR 0 00 0 0000 OWER 0x000
6. DLYBCS DLYBCS e gt PCS A PCS A gt B DLYBCS DLYBCS I gt PCS B PCS B 27 6 3 8 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCSO NSS signal NPCSO MOSI MISO and SPCK must be con figured in open drain through the PIO controller so that external pull up resistors are needed to guarantee high level When a mode fault is detected the bit in the SPI SR is set until the SPI SR is read and the SPI is automatically disabled until re enabled by writing the SPIEN bit in the SPI CR Con trol Register at 1 By default the Mode Fault detection circuitry is enabled The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register SPI 22 915 Preliminary EEE 6042E ATARM 14 Dec 06 7915 7 Preliminary 27 6 4 SPI Slave Mode 6042E ATARM 14 Dec 06 When operating in Slave Mode the SPI processes data bits on the clock provided on the SPI clock pin SPCK The SPI waits for NSS to go active before receiving the serial clock from an external master When NSS falls the clock is validated on the serializer which processes the number of bits defined by the BITS field of the Chip Select Register 0 SPI CSRO These bits are processed following a phase and a polarity defined
7. Preliminary mem 6042E ATARM 14 Dec 06 X 7915 7 Preliminary 6042E ATARM 14 Dec 06 after the read of SHDW SR When using the RTT alarm to wake up the system the user must ensure that the RTT alarm status flag is cleared before shutting down the system Otherwise no rising edge of the status flag may be detected and the wake up fails The pin FWKUP is treated differently and a low level on this pin forces a de assertion of the SHDW pin regardless of the presence of the Slow Clock The bit FWKUP in the status register reports a Forced Wakeup Event after internal resynchronization of the event with the Slow Clock ATMEL s AMEL 18 6 Shutdown Controller SHDWC User Interface 18 6 1 Register Mapping Table 18 2 Shutdown Controller SHDWC Registers Offset Register Name Access Reset Value 0x00 Shutdown Control Register SHDW_CR Write only 0x04 Shutdown Mode Register SHDW_MR Read Write 0x0000_0303 0x18 Shutdown Status Register SHDW_SR Read only 0x0000_0000 18 6 2 Shutdown Control Register Register Name SHDW_CR Access Type Write only 3 2 1 30 29 28 27 26 25 24 KEY 3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Po SW SHDW Shut Down Command 0 No effect 1 If KEY is correct asserts the SHDW pin KEY Password Should be written at value OxA5 Writing any other value in this field aborts the write operation 86 915
8. Preliminary mem 6042E ATARM 14 Dec 06 2 7915 7 Preliminary 18 6 3 Shutdown Mode Register Register Name SHDW MR Access Type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ea 15 14 13 12 11 10 9 8 3 2 1 7 6 5 4 0 CPTWKO WKMODEO Wake up Mode 0 WKMODE1 Wake up Mode 1 WKMODE 1 0 Wake up Input Transition Selection 0 0 None No detection is performed on the wake up input 0 1 Low to high level 1 0 High to low level 1 1 Both levels change CPTWKO Counter on Wake up 0 CPTWK1 Counter on Wake up 1 Defines the number of 16 Slow Clock cycles the level detection on the corresponding input pin shall last before the wake up event occurs Because of the internal synchronization of WKUPO and WKUP1 the SHDW is released CPTWK x 16 1 Slow Clock cycles after the event on WKUP RTTWKEN Real time Timer Wake up Enable 0 The RTT Alarm signal has no effect on the Shutdown Controller 1 The RTT Alarm signal forces the de assertion of the SHDW pin AMEL 6042E ATARM 14 Dec 06 AMEL 18 6 4 Shutdown Status Register Register Name SHDW SR Access Type Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pepe mono ee Ee 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REP WAKEUPO WAKEUPO Wake up 0 Status WAKEUP1 Wake up 1 Status 0 No wake up event occurred on the corresponding wake
9. 23 9 11 Controllers 23 10 Peripherals 25 10 1 Peripheral Mapping 2 ee Ernte ete taire roo nno eter rr 25 10 2 Peripheral Multiplexing on PIO Lines 4 00000 26 10 3 Controller A Multiplexing seseseeeneeenneenneennnnennnnns 27 10 4 Controller B Multiplexing seseseeneeennneennennnnnnnnne 28 11 Peripheral Identifiers 29 11 1 Serial Peripheral Interface 4 0000000 30 11 2 Two wire Interface 044 enne nnne N nnns 30 11 3 USART 30 11 4 Serial Synchronous Controller 2 04 00 0 31 11 5 Timer COUDlGr 31 11 6 PWM Controller ici veaa n ra ee ERR Ra 31 11 7 USB Device iieri eerte res red cero tie d ed eee 32 11 8 Multimedia Card Interface sse nennen 32 11 9 CAN Controllet 1 e ett titre Xx baked 32 11 10 Analog to Digital Converter ssssssssseseeeeeeeeneneeneen nnns 33 12 AHM TDMI Processor id t eror bd vai 35 DAMES TIU ECT M 35 12 2 ARMTTDMI
10. MCK Baud Rate Generator SPI Clock SPCK SPI RDR PCS NPCS3 ES Current NPCS2 Peripheral NPCS1 50 0 23 AT91SAM7AGS Preliminary EEE 6042E ATARM 14 Dec 06 27 6 3 2 6042E ATARM 14 Dec 06 Master Mode Flow Diagram Figure 27 6 Master Mode Flow Diagram SPI Enable 0 5 Variable 1 peripheral NPCS SPI TDR PCS Fixed peripheral NPCS SPI MR PCS NPCS defines the current Chip Select CSAAT DLYBS DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select When NPCS is OxF CSAAT is 0 915 Preliminary Variable 1 peripheral SPI_TDR PCS NPCS no NPCS OxF Delay DLYBCS NPCS SPI_TDR PCS Fixed peripheral SPI MR PCS NPCS no NPCS OxF Delay DLYBCS 1 Delay DLYBS Serializer SPI TDR TD TDRE 1 Data Transfer SPI_RDR RD Serializer RDRF 1 Delay DLYBCT E pp NPCS OxF Delay DLYBCS AIMEL T 239 AMEL 27 6 3 3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock MCK by a value between 1 and 255 This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255 Programming the SCBR field at 0 is forbidden Triggering
11. available only in transfer command The MCI contains the argument field of the command To send a command the user must perform the following steps e Fill the argument register MCI with the command argument e Set the command register MCI CMDR see Table 34 5 The command is sent immediately after writing the command register The status bit CMDRDY in the status register MCI SR is asserted when the command is completed If the command requires a response it can be read in the MCI response register MCI RSPR The response size can be from 48 bits up to 136 bits depending on the command The MCI embeds an error detection to prevent any corrupted data during the transfer The following flowchart shows how to send a command to the card and read the response if needed In this example the status register bits are polled but setting the appropriate bits in the interrupt enable register MCI IER allows using an interrupt method ATMEL 6042E ATARM 14 Dec 06 453 7915 7 Preliminary Figure 34 7 Command Response Functional Flow Diagram Set the command argument MCI ARGR Argument Set the command MCI CMDR Command lt Read MCI_SR Wait for command ready status flag Check error bits in the status register 1 Status error flags Read response if required RETURN OK Y RETURN ERROR Note 1 If the command is SEND OP COND
12. 2 2 0 00 557 37 7 Analog to Digital Converter Characteristics 559 37 8 Characteristics 0 242224 001 0000 nnne nnne nns 560 38 AT91SAM7AS Mechanical Characteristics 566 38 1 Thermal Considerations ssssssssssseseseeeeeeneen nennen 566 38 2 Package Drawing isses centeno tabe ke ea Eta o aacra ce co doa 567 38 3 Soldering Profile 569 39 915 Ordering Information 2222 570 6042E ATARM 14 Dec 06 A MEL vii viii 40 12 17 TETTE 571 40 1 Marking d eee Addn Ene oa 571 40 2 915 Errata Rev A Parts eese rennen nenne 572 i Table of COmMLCIUS fies ccaiecsscavccavadedaivecteddaveverideusussdesededavsdessdededan sovveetwcdsdesseese i PROVISION FIST ONY AT ix 915 Preliminary mem 6042E ATARM 14 Dec 06 7915 7 Preliminary Revision History Change Request Version Comments Ref 6042A 23 Dec 2004 First issue 6042B 30 Sep 2005 In Features corrected number of battery backup registers in Features 05 221 Updated details o
13. 30 AT91SAM7AS3 Preliminary EEE 6042E ATARM 14 Dec 06 7915 7 Preliminary ACPC RC Compare Effect on TIOA ACPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle AEEVT External Event Effect on TIOA AEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle ASWTRG Software Trigger Effect on TIOA ASWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BCPB RB Compare Effect on TIOB BCPB Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BCPC RC Compare Effect on TIOB BCPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle A MEL 381 6042E ATARM 14 Dec 06 AMEL BEEVT External Event Effect on TIOB BEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BSWTRG Software Trigger Effect on TIOB BSWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle 32 AT9ISAM7A3 Preliminary mm 6042E ATARM 14 Dec 06 7915 7 Preliminary 31 6 8 TC Counter Value Register Register Name TC CV Access Type Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 CV Counter Value CV contains the counter value in real time A MEL 383 6042E ATARM 14 Dec 06 AMEL 31 6 9 TC Register A Register Name TC
14. PIO PUSR Pull up Status Register Reading a 1 in PUSR means the pull up is dis abled and reading a 0 means the pull up is enabled Control of the pull up resistor is possible regardless of the configuration of the I O line After reset all of the pull ups are enabled i e PUSR resets at the value 0x0 26 4 2 I O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions the selection is controlled with the registers PIO PER PIO Enable Register and PIO PDR PIO Disable Register The regis ter PSR PIO Status Register is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller A value of 0 indicates that the pin is controlled by the corresponding on chip peripheral selected in the PIO ABSR AB Select Status Register A value of 1 indicates the pin is controlled by the PIO controller If a pin is used as a general purpose I O line not multiplexed with an on chip peripheral PIO PER and PIO PDR have no effect and PIO PSR returns 1 for the corresponding bit After reset most generally the I O lines are controlled by the PIO controller i e PIO PSR resets at 1 However in some events it is important that PIO lines are controlled by the periph eral as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for b
15. PWMO Period Channel Clock em Clock Generator APB Interface Interrupt Generator A MEL 391 AMEL 32 3 I O Lines Description Each channel outputs one waveform on one external I O line Table 32 1 1 0 Line Description Deserpton PWMx PWM Waveform Output for channel x Output 32 4 Product Dependencies 32 4 1 Lines The pins used for interfacing the PWM may be multiplexed with PIO lines The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral func tion If I O lines of the PWM not used by the application they can be used for other purposes by the PIO controller All of the PWM outputs may or may not be enabled If an application requires only four chan nels then only four PIO lines will be assigned to PWM outputs 32 4 2 Power Management The PWM is not continuously clocked The programmer must first enable the PWM clock in the Power Management Controller PMC before using the PWM However if the application does not require PWM operations the PWM clock can be stopped when not needed and be restarted later In this case the PWM will resume its operations where it left off Configuring the PWM does not require the PWM clock to be enabled 32 4 3 Interrupt Sources The PWM interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller Using the PWM interrupt req
16. Start Rising Edge RF RD Input e STTDLY lt lt STTDLY RD STTDLY 4 32 915 Preliminary meem 6042E ATARM 14 Dec 06 7915 7 Preliminary 30 6 5 Frame Sync The Transmitter and Receiver Frame Sync pins TF and RF can be programmed to generate different kinds of frame synchronization signals The Frame Sync Output Selection FSOS field in the Receive Frame Mode Register SSC_RFMR and in the Transmit Frame Mode Register SSC_TFMR are used to select the required waveform Programmable low or high levels during data transfer are supported Programmable high levels before the start of data transfers or toggling are also supported If a pulse waveform is selected the Frame Sync Length FSLEN field in SSC_RFMR and SSC TFMR programs the length of the pulse from 1 bit time up to 16 bit time The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection PERIOD field SSC RCMR and SSC_TCMR 30 6 5 1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal During the Frame Sync signal the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Regis ter in the Shifter Register The data length to be sampled shifted out during the Fram
17. Wait for the MCKRDY bit to be set in the PMC_SR register If a new value for CSS field corresponds to Main Clock or Slow Clock Program the CSS field in the PMC_MCKR register Wait for the MCKRDY bit to be set in the PMC_SR register Program the PRES field in the PMC_MCKR register Wait for the MCKRDY bit to be set in the PMC_SR register If at some stage one of the following parameters CSS or PRES is modified the MCKRDY bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks Note IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR PLLR the MCKRDY flag will go low while PLL is unlocked Once PLL is locked again LOCK goes high and MCKRDY is set While PLL is unlocked the Master Clock selection is automatically changed to Main Clock For fur ther information see Section 24 8 2 Clock Switching Waveforms on page 161 Code Example write register PMC MCKR 0x00000001 wait MCKRDY 1 write register PMC MCKR 0x00000011 wait MCKRDY 1 The Master Clock is main clock divided by 16 The Processor Clock is the Master Clock 5 Selection of Programmable clocks Programmable clocks are controlled via registers PMC SCER PMC_SCDR and PMC SCSR Programmable clocks can be enabled and or disabled via the PMC_SCER and PMC_SCDR registers
18. 1 CAN_MSRx i Time Window 1 1 1 1 4 MEL 520 6042E ATARM 14 Dec 06 X 7915 7 Preliminary 36 8 Controller Area Network CAN User Interface Table 36 4 Memory Map Offset Register Name Access Reset State 0x0000 Mode Register CAN MR Read Write 0x0 0x0004 Interrupt Enable Register CAN_IER Write only 0x0008 Interrupt Disable Register CAN_IDR Write only 0x000C Interrupt Mask Register CAN_IMR Read only 0x0 0x0010 Status Register CAN_SR Read only 0 0014 Baudrate Register CAN BR Read Write 0 0 0x0018 Timer Register CAN TIM Read only 0x0 0x001C Timestamp Register CAN_TIMESTP Read only 0x0 0x0020 Error Counter Register CAN_ECR Read only 0x0 0x0024 Transfer Command Register CAN_TCR Write only 0x0028 Abort Command Register CAN_ACR Write only 0x0100 OxO1FC Reserved 0 0200 Mailbox 0 Mode Register CAN MMRO Read Write 0x0 0x0204 Mailbox O Acceptance Mask Register CAN MAMO Read Write 0x0 0x0208 Mailbox 0 ID Register CAN MIDO Read Write 0 0 0 020 Mailbox 0 Family ID Register CAN MFIDO Read only 0x0 0x0210 Mailbox 0 Status Register CAN MSRO Read only 0 0214 Mailbox 0 Data Low Register CAN MDLO Read Write 0 0 0 0218 Mailbox 0 Data High Register CAN MDHO Read Write 0 0 0x021C Mailbox 0 Control Register CAN_MCRO Write only 0x0220 Mailbox 1 Mode Regist
19. 2222 0 00 128 22 8 Advanced Interrupt Controller AIC User Interface 140 22 Clock Generator sicubi Ds 151 23 1 E 151 23 2 Slow Clock RC Oscillator sese 151 23 3 Main Oscillator sesesessseseseeeeeeenneenennmeeen nennen neret 151 23 4 Divider and PLL Block nennen 153 24 Power Management Controller PMC ooo 155 24 1 Desorption ER 155 24 2 Master Clock Controller 2224 0 155 24 3 Processor Clock Controller 0001 1 156 24 4 USB Clock Controller 22 24 0000 nnne 156 24 5 Peripheral Clock Controller 2 2 esses 156 24 6 Programmable Clock Output Controller 157 24 7 Programming Sequence 2 nennen nennt nennen 157 24 8 Clock Switching Details sssssssseeeeeeeeeenneneen nennen 161 24 9 Power Management Controller PMC User Interface 164 25 Debug Unit DBGU ausis 181 25 4 OVOIVIOW
20. 40 2 6 3 SPI LASTXFER Last Transfer Behavior In FIXED Mode with CSAAT bit set and in PDC mode the Chip Select can rise depending on the data written in the SPI when the TX EMPTY flag is set If for example the PDC writes a 1 in the bit 24 LASTXFER bit of the the chip select will rise as soon as the TXEMPTY flag is set Problem Fix Workaround Use the CS in PIO mode when PDC mode is required and CS has to be maintained between transfers 40 2 6 4 SPI SPCK Behavior in Master Mode SPCK pin can toggle out before the first transfer in Master Mode Problem Fix Workaround In Master Mode MSTR bit must be set in SPI MR register before configuring SPI CSRx registers 40 2 6 5 SPI Chip Select and Fixed Mode In fixed Mode if a transfer is performed through a PDC on a Chip select different from the Chip select 0 the output spi size sampled by the PDC will depend on the field BITS Bits per Trans fer of SPI CSRO register whatever the selected Chip select is For example if SPI CSRO is configured for a 10 bit transfer whereas SPI CSR1 is configured for an 8 bit transfer when a transfer is performed in Fixed mode through the PDC on Chip select 1 the transfer will be con sidered as a HalfWord transfer Problem Fix Workaround If a PDC transfer has to be performed in 8 bits on a Chip select y y as different from O the BITS field of the CSRO must be configured in 8 bits in the same
21. 42 915 Preliminary meem 6042E ATARM 14 Dec 06 AA 7915 7 Preliminary 0 Resets the ISOERROR flag clears the interrupt 1 No effect TXPKTRDY Transmit Packet Ready This flag is cleared by the USB device This flag is set by the USB device firmware Read 0 Can be set to one to send the FIFO data 1 The data is waiting to be sent upon reception of token IN Write 0 No effect 1 new data payload is has been written in the FIFO by the firmware and is ready to be sent This flag is used to generate a Data IN transaction device to host Device firmware checks that it can write a data payload in the FIFO checking that TXPKTRDY is cleared Transfer to the FIFO is done by writing in the UDP_ FDRx register Once the data payload has been transferred to the FIFO the firmware notifies the USB device setting TXPKTRDY to one USB bus transactions can start TXCOMP is set once the data payload has been received by the host FORCESTALL Force Stall used by Control Bulk and Isochronous Endpoints Read 0 Normal state 1 Stall state Write 0 Return to normal state 1 2 Send STALL to the host Refer to chapters 8 4 5 and 9 4 5 of the Universal Serial Bus Specification Rev 2 0 for more information on the STALL handshake Control endpoints During the data stage and status stage this bit indicates that the microcontroller cannot complete the request Bulk and inte
22. 7 6 5 4 3 2 1 0 Lo 1 MCKRY MOSCS MOSCS Main Oscillator Status Interrupt Disable LOCK PLL Lock Interrupt Disable MCKRDY Master Clock Ready Interrupt Disable PCKRDYx Programmable Clock Ready x Interrupt Disable 0 No effect 1 Disables the corresponding interrupt A MEL 177 6042E ATARM 14 Dec 06 AMEL 24 9 14 PMC Status Register Register Name PMC_SR Access Type Read only 10 T OO 7 6 5 4 3 2 1 0 j 1 MOSCS MOSCS Flag Status 0 Main oscillator is not stabilized 1 Main oscillator is stabilized LOCK PLL Lock Status 0 PLL is not locked 1 PLL is locked MCKRDY Master Clock Status 0 Master Clock is not ready 1 Master Clock is ready PCKRDYx Programmable Clock Ready Status 0 Programmable Clock x is not ready 1 Programmable Clock x is ready 18 915 7 Preliminary meem 6042E ATARM 14 Dec 06 7915 7 Preliminary 24 9 15 PMC Interrupt Mask Register Register Name PMC_IMR Access Type Read only 10 OO 7 6 5 4 3 2 1 0 MCKRY MOSCS MOSCS Main Oscillator Status Interrupt Mask LOCK PLL Lock Interrupt Mask MCKRDY Master Clock Ready Interrupt Mask PCKRDYx Programmable Clock Ready x Interrupt Mask 0 The corresponding interrupt is enabled 1 The corresponding interrupt is disabled
23. ADC Interrupt ADTRG L VDDANA LH ADVREF O Dedicated Analog Inputs Peripheral Bridge Successive Approximation Register User Interface Analog to Digital Analog Inputs Converter Multiplexed 4 with I O lines A MEL 475 AMEL 35 3 Signal Description Table 35 1 ADC Pin Description Pin Name Description VDDANA Analog power supply ADVREF Reference voltage ADO AD7 Analog input channels ADTRG External trigger 35 4 Product Dependencies 35 4 1 35 4 2 35 4 3 35 4 4 35 4 5 35 4 6 476 Power Management The ADC is automatically clocked after the first conversion in Normal Mode In Sleep Mode the ADC clock is automatically stopped after each conversion As the logic is small and the ADC cell can be put into Sleep Mode the Power Management Controller has no effect on the ADC behavior Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller Using the ADC interrupt requires the AIC to be programmed first Analog Inputs The analog input pins can be multiplexed with PIO lines In this case the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER By default after reset the PIO line is configured as input with its pull up enabled and the ADC input is connected to the GND Lines The pin AD
24. AMEL 21 4 3 PDC Transmit Pointer Register Register Name PERIPH_TPR Access Type Read Write 31 30 29 28 27 26 25 24 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 7 6 5 4 3 2 1 0 TXPTR Transmit Pointer Address Address of the transmit buffer 21 4 4 PDC Transmit Counter Register Register Name PERIPH TCR Access Type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXCTR Transmit Counter Value TXCTR is the size of the transmit transfer to be performed At zero the peripheral data transfer is stopped 122 AT91SAM7AS3 Preliminary memm 6042E ATARM 14 Dec 06 7915 7 Preliminary 21 4 5 PDC Receive Next Pointer Register Register Name PERIPH RNPR Access Type Read Write 31 30 29 28 27 26 25 24 RXNPTR 23 22 21 20 19 18 17 16 RXNPTR 15 14 13 12 11 10 9 8 RXNPTR Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when the current buffer is full 21 4 6 PDC Receive Next Counter Register Register Name PERIPH RNCR Access Type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXNCR Receive Next Counter Value RXNCR is the size of the next buffer to receive ATMEL 6042E ATARM 14 Dec 06 AMEL 21 4 7 PDC Transmit Next Pointer Register Register Name PERIPH_TNPR Access Type Read Write 31 30 29 28 27 26 25 24 TXNPTR 23 2
25. MDL 31 24 CAN MDH 7 0 MDH 15 8 CAN MDH 23 16 CAN MDH 31 24 ATMEL 6042E ATARM 14 Dec 06 A1915AM7A3 Preliminary 36 8 18 CAN Message Data High Register Name CAN MDHx Access Type Read Write 31 30 29 28 27 26 25 24 MDH 23 22 21 20 19 18 17 16 MDH 15 14 13 12 11 10 9 8 A wo A MDH Message Data High Value When MRDY field is set in the MSRx register the upper 32 bits of a received message are read or written by the soft ware application Otherwise the MDH value is locked by the CAN controller to send receive a new message In Receive with overwrite the CAN controller may modify MDH value while the software application reads MDH and MDL registers To check that MDH and MDL do not belong to different messages the application has to check the MMI field in the MSRx register In this mode the software application must re read and CAN MDL while the MMI bit in the CAN MSRx register is set Bytes are received sent on the bus in the following order CAN MDL 7 0 CAN MDL 15 8 MDL 23 16 MDL 31 24 CAN MDH 7 0 MDH 15 8 CAN MDH 23 16 CAN MDH 31 24 ATMEL 6042E ATARM 14 Dec 06 7915 7 Preliminary 36 8 19 CAN Message Control Register Name CAN MCRx Access Type Write only 31 30 29 28 27 26
26. Preliminary 26 6 49 Multi driver Disable Register Name PIO MDDR Access Type Write only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Pe Pt Pt Pt Po PB 7 6 5 4 3 2 1 0 P5 P4 Ps e _ j Po j e PO P31 Multi Drive Disable 0 No effect 1 Disables Multi Drive on the I O line 26 6 20 PIO Multi driver Status Register Name PIO MDSR Access Type Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Ps Pi Pme Pt Po Po P 7 6 5 4 3 2 1 0 e m m I w I e PO P31 Multi Drive Status 0 The Multi Drive is disabled on the I O line The is driven at high and low level 1 The Multi Drive is enabled on the I O line The pin is driven at low level only AMEL 2 6042E ATARM 14 Dec 06 AMEL 26 6 21 PIO Pull Up Disable Register Name PIO PUDR Access Type Write only 31 30 29 28 27 26 25 24 P24 15 14 13 12 11 10 9 8 pn Po Po P8 7 6 5 4 3 2 1 0 PO P31 Pull Up Disable 0 No effect 1 Disables the pull up resistor on the I O line 26 6 22 PIO Pull Up Enable Register Name PIO_PUER Access Type Write only 31 30 29 28 27 26 25 24 P24 23 22 21 20 19 18 17 16 P23 P22 21 20 15 14 13 12 11 10 9 8 Pii Po P8 7 6 5 4 3 2 1 0 PO P31 Pull Up Enable 0 No effect 1 Enables the pull up resistor on the I O line 22
27. Preliminary 30 8 16 SSC Interrupt Mask Register Name SSC IMR Access Type Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 11 10 9 8 13 12 e qd p BOW USE 7 6 5 4 3 2 1 0 TXRDY Transmit Ready Interrupt Mask The Transmit Ready Interrupt is disabled The Transmit Ready Interrupt is enabled TXEMPTY Transmit Empty Interrupt Mask The Transmit Empty Interrupt is disabled The Transmit Empty Interrupt is enabled ENDTX End of Transmission Interrupt Mask The End of Transmission Interrupt is disabled The End of Transmission Interrupt is enabled TXBUFE Transmit Buffer Empty Interrupt Mask The Transmit Buffer Empty Interrupt is disabled The Transmit Buffer Empty Interrupt is enabled RXRDY Receive Ready Interrupt Mask The Receive Ready Interrupt is disabled The Receive Ready Interrupt is enabled OVRUN Receive Overrun Interrupt Mask The Receive Overrun Interrupt is disabled The Receive Overrun Interrupt is enabled ENDRX End of Reception Interrupt Mask The End of Reception Interrupt is disabled The End of Reception Interrupt is enabled RXBUFF Receive Buffer Full Interrupt Mask The Receive Buffer Full Interrupt is disabled The Receive Buffer Full Interrupt is enabled Compare 0 Interrupt Mask The Compare 0 Interrupt is disabled The Compare 0 Interrupt is enabled CP1 Compare 1 Interrupt Mask The Compare 1 Interrupt is disabled The Compare 1 Interrupt is enabled
28. SR register FERR Form Error No form error occurred during a previous transfer 1 A form error occurred during a previous transfer A form error results from violations on one or more of the fixed form of the following bit fields CRC delimiter ACK delimiter End of frame Error delimiter Overload delimiter This flag is automatically cleared by reading CAN_SR register A MEL 530 6042E ATARM 14 Dec 06 2 7915 7 Preliminary BERR Bit Error No bit error occurred during a previous transfer 1 A bit error occurred during a previous transfer A bit error is set when the bit value monitored on the line is different from the bit value sent This flag is automatically cleared by reading CAN SR register RBSY Receiver busy 0 CAN receiver is not receiving a frame 1 CAN receiver is receiving a frame Receiver busy This status bit is set by hardware while CAN receiver is acquiring or monitoring a frame remote data over load or error frame It is automatically reset when CAN is not receiving TBSY Transmitter busy 0 CAN transmitter is not transmitting a frame 1 CAN transmitter is transmitting a frame Transmitter busy This status bit is set by hardware while CAN transmitter is generating a frame remote data overload or error frame It is automatically reset when CAN is not transmitting OVLSY Overload busy 0 CAN transmitter is not transmitting a
29. Setup transaction gt Status IN transaction Interrupt IN Transfer Data IN transaction Data IN transaction device toward host Interrupt OUT Transfer Data OUT transaction Data OUT transaction host toward device Isochronous IN Transfer Data IN transaction Data IN transaction device toward host Isochronous OUT Transfer 2 Data OUT transaction Data OUT transaction host toward device Bulk IN Transfer Data IN transaction Data IN transaction device toward host Bulk OUT Transfer Data OUT transaction Data OUT transaction host toward device Notes 1 Control transfer must use endpoints with no ping pong attributes 2 transfers must use endpoints with ping pong attributes 3 Control transfers can be aborted using a stall handshake A status transaction is a special type of host to device transaction used only in a control transfer The control transfer must be performed using endpoints with no ping pong attributes According to the control sequence read or write the USB device sends or receives a status transaction 46 915 Preliminary EEE 6042E ATARM 14 Dec 06 915 Preliminary Figure 33 4 Control Read and Write Sequences Setup Stage Data Stage Status Stage Data OUT TX Data OUT TX m Status IN TX Control Read Setup TX d Setup Stage Data Stage Status Stage Data IN TX Dat
30. X 7915 7 Preliminary 27 Serial Peripheral Interface SPI 27 1 Overview 6042E ATARM 14 Dec 06 The Serial Peripheral Interface SPI circuit is a synchronous serial data link that provides com munication with external devices in Master or Slave Mode It also enables communication between processors if an external processor is connected to the system The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPls During a data transfer one SPI system acts as the master which controls the data flow while the other devices act as slaves which have data shifted into and out by the master Different CPUs can take turn being masters Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves and one master may simultaneously shift data into multiple slaves However only one slave may drive its output to write data back to the master at any given time A slave device is selected when the master asserts its NSS signal If multiple slave devices exist the master generates a separate slave select signal for each slave NPCS The SPI system consists of two data lines and two control lines Master Out Slave In MOSI This data line supplies the output data from the master shifted into the input s of the slave s Master In Slave Out MISO This data line supplies the output data from a sl
31. i reca E e ORENSE EE basa Yu 181 iv AT91SAM7A3 Preliminary memm 6042E ATARM 14 Dec 06 7915 7 Preliminary 25 2 182 25 3 Product Dependencies 2 183 25 4 UART Operations nein 183 25 5 Debug Unit User Interface eene 190 26 Parallel Input Output Controller PIO 205 oUONMEOU TSCIUR 205 26 2 Block Diagram 206 26 3 Product Dependencies 207 26 4 Functional Description 208 26 5 I O Lines Programming Example sese 213 26 6 User Interface nennen nenne nnne rennen 214 27 Serial Peripheral Interface SPI 231 27 1 231 27 2 Block Diagram acie be ER Ro Re agua 232 27 3 Application Block Diagrar oie Dent ee eu eas 233 27 4 Signal Description ssssssssssseseseseeeeeeneen eren 234 27 5 Product Dependencies nennen nnn 234 27 6 Functional Descripti
32. 36 6 4 1 CAN Bit Timing Configuration All controllers on a CAN bus must have the same bit rate and bit length At different clock fre quencies of the individual controllers the bit rate has to be adjusted by the time segments The CAN protocol specification partitions the nominal bit time into four different segments Figure 36 4 Partition of the CAN Bit Time NOMINAL BIT TIME SYNC SEG Sample Point TIME QUANTUM The TIME QUANTUM TQ is a fixed unit of time derived from the MCK period The total num ber of TIME QUANTA in a bit time is programmable from 8 to 25 SYNC SEG SYNChronization Segment This part of the bit time is used to synchronize the various nodes on the bus An edge is expected to lie within this segment It is 1 TQ long PROP SEG PROPagation Segment This part of the bit time is used to compensate for the physical delay times within the network It is twice the sum of the signal s propagation time on the bus line the input comparator delay and the output driver delay It is programmable to be 1 2 8 TQ long This parameter is defined in the PROPAG field of the CAN Baudrate Register PHASE SEG1 PHASE SEG2 PHASE Segment 1 and 2 The Phase Buffer Segments are used to compensate for edge phase errors These segments can be lengthened PHASE SEG1 or shortened PHASE SEG2 by resynchronization Phase Segment 1 is programmable to be 1 2 8 TQ long Phase Segment 2 length has to be
33. 6042E ATARM 14 Dec 06 A1915AM7AG Preliminary 17 4 2 Watchdog Timer Mode Register Register Name WDT MR Access Type Read Write Once 81 30 29 28 27 26 25 24 WDDBGRIT WDD 23 22 21 20 19 18 17 16 WDD 15 13 12 11 10 9 8 WDDIS WDRPROC WDRSTEN WDFIEN WDV 7 6 5 4 3 2 1 0 WDV WDV Watchdog Counter Value Defines the value loaded in the 12 bit Watchdog Counter WDFIEN Watchdog Fault Interrupt Enable 0 A Watchdog fault underflow or error has no effect on interrupt A Watchdog fault underflow or error asserts interrupt WDRSTEN Watchdog Reset Enable A Watchdog fault underflow or error has no effect on the resets A Watchdog fault underflow or error triggers a Watchdog reset WDRPROC Watchdog Reset Processor If WDRSTEN is 1 a Watchdog fault underflow or error activates all resets IFWDRSTEN is 1 a Watchdog fault u