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ATMEL AT91SAM7A3 handbook (1)(1)

1. eene 235 27 7 Serial Peripheral Interface SPI User Interface 244 28 Two wire Interface TWI 257 28 1 Overview nenne nennen anite seitens entres ennt nennt renes 257 28 2 Block Diagram PEE EU up 257 28 3 Application Block Diagram 257 28 4 Product 258 28 5 Functional Description 2 22 4 000 nennen nnn 259 28 6 Two wire Interface TWI User Interface 264 29 Universal Synchronous Asynchronous Receiver Transceiver ale erie ee AA LE EE 273 294 Block NEREA 274 29 2 Application Block Diagram 275 29 3 Lines Description n Reo duree 275 29 4 Product Dependencies 276 29 5 Functional Description t Eee PR Red dd 277 29 6 USART User Interface ssssssssssseesseseeeeeeenneeen nennen nennen ens 300 30 Synchronous Serial Controller SSC 317 6042E ATARM 14 Dec 06 AMEL 30 1 SOVERVIOW 317 30 2 Block 318
2. 86 Memory Controller MC sssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 89 191 aunties 89 19 2 Block DIAG FAN 89 19 3 Functional Description 90 19 4 Memory Controller MC User Interface 2 94 Embedded Flash Controller EFC e ooo 101 A MEL iii 20 1 OVERVIOW 101 20 2 Functional Description 02 4204 40 00 101 20 8 Embedded Flash Controller EFC User Interface 109 21 Peripheral DMA Controller PDC 0 00 0 00001000001 eene annu unu 115 AREE UIT 115 21 2 Block nri te 115 21 3 Functional Description 22 2 24 116 21 4 Peripheral DMA Controller PDC User Interface 118 22 Advanced Interrupt Controller AIC ooo 125 PNEU SI 125 22 2 Block Diagram 125 22 3 Application Block Diagram seen ene 126 22 4 Detailed Block Diagram ssssseseseeneenneeennenenneen nennen 126 22 5 VO Line D
3. Table 29 2 Baud Rate Example OVER 0 Continued Expected Baud Source Clock Rate Calculation Result CD Actual Baud Rate Error 14 318 180 38 400 23 30 23 38 908 10 1 31 14 745 600 38 400 24 00 24 38 400 00 0 00 18 432 000 38 400 30 00 30 38 400 00 0 00 24 000 000 38 400 39 06 39 38 461 54 0 16 24 576 000 38 400 40 00 40 38 400 00 0 00 25 000 000 38 400 40 69 40 38 109 76 0 76 32 000 000 38 400 52 08 52 38 461 54 0 16 32 768 000 38 400 53 33 53 38 641 51 0 63 33 000 000 38 400 53 71 54 38 194 44 0 54 40 000 000 38 400 65 10 65 38 461 54 0 16 50 000 000 38 400 81 38 81 38 580 25 0 47 The baud rate is calculated with the following formula BaudRate MCK CD x 16 The baud rate error is calculated with the following formula It is not recommended to work with an error higher than 5 Error 1 ie ater 29 5 1 3 Baud Rate in Synchronous Mode 6042E ATARM 14 Dec 06 If the USART is programmed to operate in synchronous mode the selected clock is simply divided by the field CD in US BRGR SelectedClock CD BaudRate In synchronous mode if the external clock is selected USCLKS 3 the clock is provided directly by the signal on the USART SCK pin No division is active The value written in US BRGRH has no effect The external clock frequency must be at least 4 5 times lower than the system clock When either the external clock SCK or the internal clock divided MCK DIV is selected the va
4. 65 154 MC 65 15 2 Block Diagrams iieri dote bera e 65 15 3 Functional Description 2 65 15 4 Real time Timer RTT User Interface 2 22424 00 0 67 Periodic Interval Timer PIT 71 16 1 Overview 0244144 20 00 00000 00101011 nnn ar Aaa aaa ennt seen rese nnns entere nnne 71 162 Block Diagrams iiit Ee tu te D e Peer Regen 71 16 3 Functional Description mener nnn 71 16 4 Periodic Interval Timer PIT User Interface 73 Watchdog Timer WDT 2 2 77 171 Overview Enp 77 17 27 Block Diagram do tee e eis cbe ea Rie ore ne iets 77 17 3 Functional Description roninai ar mener 78 17 4 Watchdog Timer WDT User Interface 80 Shutdown Controller SHDWO 83 181 Overview 83 18 2 Block Diag ramet iio D a Pe ar Rao 83 18 3 I O Lines Description aE E 84 18 4 Product Dependencies eer eene e epa eg 84 18 5 Functional Description 84 18 6 Shutdown Controller GHDWC User Interface
5. Active Signal Name Function Type Level Comments SPI SPIO_MISO SPI1_MISO Master In Slave Out SPIO_MOSI SPI1_MOSI Master Out Slave In SPIO_SPCK SPI1_SPCK SPI Serial Clock SPIO_NPCSO SPI1_NPCSO SPI Peripheral Chip Select 0 Low SPIO_NPCS1 SPIO_NPCS3 SPI1_NPCS1 SPI1_NPCS3 SPI Peripheral Chip Select Output Low Two wire Interface TWD Two wire Serial Data y o TWCK Two wire Serial Clock y o Analog to Digital Converter ADCO ADO ADCO AD7 E ADC1 ADO ADC1 AD7 Analog Inputs Analog Digital pulled up inputs at reset ADVREFP Analog Positive Reference Analog ADCO ADTRG ADC1 ADTRG ADC Trigger Input CAN Controller CANRXO CANRX1 CAN Inputs Input CANTXO CANTX1 CAN Outputs Output ATMEL 6042E ATARM 14 Dec 06 AMEL 4 Package 41 100 lead LQFP Package Outline Figure 4 1 shows the orientation of the 100 lead LQFP package A detailed mechanical description is given in the Mechanical Characteristics section of the full datasheet Figure 4 1 100 LQFP Outline Top View 75 51 100 8 915 Preliminary memm 6042E ATARM 14 Dec 06 mes 91 SAM7A3 Preliminary 4 2 Pinout Table 4 1 Pinout in 100 lead LQFP Package 1 GND 26 VDDBU 51 PA20 76 PLLRC 2 NRST 27 FWKUP 52 PA21 77 VDDANA 3 TST 28 WKUPO 53 PA22 78 ADVREFP 4 PB13 29 WKUP1 54 PA23 79 GND 5 PB12 30 SHDW 55 PA24 80 PB14 ADCO_ADO 6 PB11 31 GN
6. AMEL a 6042E ATARM 14 Dec 06 AMEL Table 13 2 915 7 JTAG Boundary Scan Register Continued Associated BSR Bit Number Pin Name Pin Type Cells 101 INPUT 100 PA14 IN OUT OUTPUT 99 CONTROL 98 INPUT 97 PA15 IN OUT OUTPUT 96 CONTROL 95 INPUT 94 PA16 IN OUT OUTPUT 93 CONTROL 92 INPUT 91 PA17 IN OUT OUTPUT 90 CONTROL 89 INPUT 88 PA18 IN OUT OUTPUT 87 CONTROL 86 INPUT 85 PA19 IN OUT OUTPUT 84 CONTROL 83 INPUT 82 PA20 IN OUT OUTPUT 81 CONTROL 80 INPUT 79 PA21 IN OUT OUTPUT 78 CONTROL 77 INPUT 76 PA22 IN OUT OUTPUT 75 CONTROL 74 INPUT 73 PA23 IN OUT OUTPUT 72 CONTROL 71 INPUT 70 PA24 IN OUT OUTPUT 69 CONTROL 48 915 Preliminary memm 6042E ATARM 14 Dec 06 91 SAM7A3 Preliminary Table 13 2 915 JTAG Boundary Scan Register Continued Associated BSR Bit Number Pin Name Pin Type Cells 68 INPUT 67 PA25 IN OUT OUTPUT 66 CONTROL 65 INPUT 64 PA26 IN OUT OUTPUT 63 CONTROL 62 INPUT 61 PA27 IN OUT OUTPUT 60 CONTROL 59 INPUT 58 PA28 IN OUT OUTPUT 57 CONTROL 56 INPUT 55 PA29 IN OUT OUTPUT 54 CONTROL 53 INPUT
7. en t 476 35 4 Product Dependencies nennen nennen 476 35 5 Functional Description erret tied ee ku ced d Le ed dae 477 35 6 Analog to digital Converter ADC User Interface 482 36 Controller Area Network 493 36 1 MOVEIVIOW t UR eadera ied De oen RERO 493 36 2 Block Diagram recie e oe ao a e 494 36 3 Application Block 494 36 4 WO Lines Description ssssseseseeeneeenennmeeenenenn nennen nnnm nnns 495 36 5 Product Dependencies 495 36 6 Controller Features ssssssesessssseseeeeeeenenenn neret 496 36 7 Functional Description sssrin asas aei aa in een n i exu du 508 36 8 Controller Area Network CAN User Interface 521 37 915 Electrical Characteristics uuss 549 37 1 Absolute Maximum 549 37 2 DG Characteristic ie cedi secti erre ni di 549 37 9 Power Consumption iicet rte det eee p Er ed cce enu c 551 37 4 Crystal Oscillator Characteristics 553 37 5 Characteristics Dt endete breed ne r
8. 26 4 4 Output Control When the 1 0 line is assigned to a peripheral function i e the corresponding bit in PIO PSR is at 0 the drive of the I O line is controlled by the peripheral Peripheral A or B depending on the value in PIO ABSR determines whether the pin is driven or not A MEL 209 6042E ATARM 14 Dec 06 26 4 5 26 4 6 26 4 7 210 AMEL When the I O line is controlled by the PIO controller the pin can be configured to be driven This is done by writing PIO_OER Output Enable Register and PIO ODR Output Disable Register The results of these write operations are detected in PIO_OSR Output Status Register When a bit in this register is at 0 the corresponding I O line is used as an input only When the bit is at 1 the corresponding I O line is driven by the PIO controller The level driven on I O line can be determined by writing in PIO SODR Set Output Data Register and PIO_CODR Clear Output Data Register These write operations respectively set and clear PIO ODSR Output Data Status Register which represents the data driven on the I O lines Writing in PIO OER and manages PIO OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function This enables configura tion of the I O line prior to setting it to be managed by the PIO Controller Similarly writing in PIO SODR and PIO CODR effects PIO ODSR This is important as it
9. 1 4 Tcsc gt SJW Tsjw Tcsc 1 3 Finally BR 0x00053255 A MEL 502 6042E ATARM 14 Dec 06 mes 91 SAM7A3 Preliminary CAN Bus Synchronization Autobaud Mode 6042E ATARM 14 Dec 06 Two types of synchronization are distinguished hard synchronization at the start of a frame and resynchronization inside a frame After a hard synchronization the bit time is restarted with the end of the SYNC SEG segment regardless of the phase error Resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge The effect of resynchronization is the same as that of hard synchronization when the magni tude of the phase error of the edge causing the resynchronization is less than or equal to the programmed value of the resynchronization jump width ts jw When the magnitude of the phase error is larger than the resynchronization jump width and the phase error is positive then PHASE SEG is lengthened by an amount equal to the resynchronization jump width the phase error is negative then PHASE SEG2 is shortened by an amount equal to the resynchronization jump width Figure 36 6 CAN Resynchronization THE PHASE ERROR IS POSITIVE the transmitter is slower than the receiver Nominal Sample point Sample point after resynchronization Received data bit 1 5 1 Nominal bit time SYNC PROP
10. EtrRGEDG 7 6 5 4 3 2 1 0 TCCLKS Clock Selection TCCLKS Clock Selected 0 0 0 TIMER CLOCK1 0 0 1 TIMER 2 0 1 0 TIMER CLOCKS 0 1 1 TIMER CLOCKA4 1 0 0 TIMER CLOCK5 1 0 1 XCO 1 1 0 XC1 1 1 1 XC2 CLKI Clock Invert 0 Counter is incremented on rising edge of the clock 1 Counter is incremented on falling edge of the clock BURST Burst Signal Selection BURST 0 0 The clock is not gated by an external signal 0 1 XCO is ANDed with the selected clock 1 0 XC1 is ANDed with the selected clock 1 1 XC2 is ANDed with the selected clock LDBSTOP Counter Clock Stopped with RB Loading Counter clock is not stopped when RB loading occurs 1 Counter clock is stopped when RB loading occurs LDBDIS Counter Clock Disable with RB Loading 0 Counter clock is not disabled when RB loading occurs 1 Counter clock is disabled when RB loading occurs AIMEL 37 6042E ATARM 14 Dec 06 AMEL ETRGEDG External Trigger Edge Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ABETRG or TIOB External Trigger Selection 0 TIOB is used as an external trigger 1 TIOA is used as an external trigger CPCTRG RC Compare Trigger Enable 0 RC Compare has no effect on the counter and its clock 1 RC Compare resets the counter and starts the counter clock
11. A MEL 353 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary TXSYN Tx Sync Interrupt Enable 0 No effect 1 Disables the Tx Sync Interrupt RXSYN Rx Sync Interrupt Enable No effect Disables the Rx Sync Interrupt AIMEL 354 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary 30 8 16 SSC Interrupt Mask Register Name SSC_IMR Access Type Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 11 10 9 8 13 12 Le USE 7 6 5 4 3 2 1 0 TXRDY Transmit Ready Interrupt Mask The Transmit Ready Interrupt is disabled The Transmit Ready Interrupt is enabled TXEMPTY Transmit Empty Interrupt Mask The Transmit Empty Interrupt is disabled The Transmit Empty Interrupt is enabled ENDTX End of Transmission Interrupt Mask The End of Transmission Interrupt is disabled The End of Transmission Interrupt is enabled TXBUFE Transmit Buffer Empty Interrupt Mask The Transmit Buffer Empty Interrupt is disabled The Transmit Buffer Empty Interrupt is enabled RXRDY Receive Ready Interrupt Mask The Receive Ready Interrupt is disabled The Receive Ready Interrupt is enabled OVRUN Receive Overrun Interrupt Mask The Receive Overrun Interrupt is disabled The Receive Overrun Interrupt is enabled ENDRX End of Reception Interrupt Mask The End of Reception Interrupt is disabled The End of Reception Interrupt is enabled RXBUFF Receive Buffer Full Interrupt Mask The
12. DLYBCS DLYBCS e gt PCS A PCS A gt B DLYBCS DLYBCS lt e PCS B PCS B 27 6 3 8 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCSO NSS signal NPCSO MOSI MISO and SPCK must be con figured in open drain through the PIO controller so that external pull up resistors are needed to guarantee high level When a mode fault is detected the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re enabled by writing the SPIEN bit in the SPI_CR Con trol Register at 1 By default the Mode Fault detection circuitry is enabled The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register SPI_MR 22 915 Preliminary EEE 6042E ATARM 14 Dec 06 7915 7 Preliminary 27 6 4 SPI Slave Mode 6042E ATARM 14 Dec 06 When operating in Slave Mode the SPI processes data bits on the clock provided on the SPI clock pin SPCK The SPI waits for NSS to go active before receiving the serial clock from an external master When NSS falls the clock is validated on the serializer which processes the number of bits defined by the BITS field of the Chip Select Register 0 SPI CSRO These bits are processed following a phase and a polarity defined respectively by the NCPHA
13. 222 1 0 1 namen nat eene redeam deba EN 23 9 10 Shutdown Controller 23 9 11 Controllers A and 23 10 25 10 1 Peripheral Mapping Ernte ete taire roo nno eter rr un race 25 10 2 Peripheral Multiplexing on PIO Lines 4 00000 26 10 3 Controller A Multiplexing seseseeeneeenneenneennnnennnnns 27 10 4 Controller B Multiplexing seseseeneeennneennennnnnnnnne 28 11 Peripheral Identifiers 29 11 1 Serial Peripheral Interface 30 11 2 Two wire Interface 044 nennen enne nnne N nnns 30 11 3 USART 30 11 4 Serial Synchronous Controller 2 04 00 0 31 11 5 Timer COUDlGr 31 11 6 PWM Controller ici ella e e HERE EE ELS ERE ERR Ra 31 11 7 USB Device iieri eerte res red cero tie d ed eee 32 11 8 Multimedia Card Interface sse nennen 32 11 9 CAN Controllet 1 e ett titre Xx baked 32 11 10 Analog to Digital Converter ssssssssseseeeeeeeeneneenee
14. Preliminary mem 6042E ATARM 14 Dec 06 91 SAM7A3 Preliminary If the ADC_CDR is not read before further incoming data is converted the corresponding Overrun Error OVRE flag is set in the Status Register ADC_SR In the same way new data converted when DRDY is high sets the bit GOVRE General Over run Error in ADC_SR The OVRE and GOVRE flags are automatically cleared when ADC_SR is read Figure 35 3 GOVRE and OVREx Flag Behavior Read ADC_SR ADTRG 1 CHO 1 1 1 1 1 ADC_CHSR i 1 CH1 ADC_CHSR i 1 1 I 1 1 1 1 ADC_CDRO Undefiied Data XK Kata 1 ADC_CDR1 Undefined Daia Data B ADC S lt gt 1 Conversion gt Read ADC_CDRO B 14 1 aed onesie Read DDR1 ADC SR i 1 1 Lu 42 21 11 _ ADC_SR DRDY 177727 77 ADC_SR 1 1 1 OVREO ADC_SR Warning If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable A MEL 479 6042E ATARM 14 Dec 06 35 5 5 35 5 6 480 AMEL Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger The software trigger is provided by writing the Control
15. o 4 3 5 A 0 The Receiver Time out is disabled 1 65535 The Receiver Time out is enabled and the Time out delay is TO x Bit Period 29 6 11 USART Transmitter Timeguard Register Name US_TTGR Access Type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 N O A 4 TG Timeguard Value 0 The Transmitter Timeguard is disabled 1 255 The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period A ATMEL s 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary 29 6 12 USART FI DI RATIO Register Name US FIDI Access Type Read Write Reset Value 0x174 31 30 29 28 27 26 25 24 N N o E 2 wo _ FI DI RATIO N O A DI RATIO Over DI Ratio Value 0 If 15807816 mode is selected the Baud Rate Generator generates no signal 1 2047 If 1507816 mode is selected the Baud Rate is the clock provided SCK divided by DI RATIO 29 6 13 USART Number of Errors Register Name US NER Access Type Read only 31 30 29 28 27 26 25 24 N N E A A 6 k a4
16. CV then increments See Figure 31 12 A MEL 369 6042E ATARM 14 Dec 06 AMEL RC Compare cannot be programmed to generate a trigger in this configuration At the same time RC Compare can stop the counter clock CPCSTOP 1 and or disable the counter clock CPCDIS 1 Figure 31 11 WAVSEL 01 Without Trigger Counter Value Counter decremented by compare match with OxFFFF OxFFFF 1 Waveform Examples Time Jil P 1 TIOA Figure 31 12 WAVSEL 01 With Trigger Counter Value Counter decremented by compare match with OxFFFF OxFFFF Counter decremented by trigger Counter incremented by trigger TIOA 31 5 3 5 WAVSEL 11 When WAVSEL 11 the value of TC_CV is incremented from 0 to RC Once RC is reached the value of TC_CV is decremented to 0 then re incremented to RC and so on See Figure 31 13 30 AT9ISAM7A3 Preliminary memm 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary A trigger such as an external event or a software trigger can modify CV at any time If a trigger occurs while CV is incrementing TC CV then decrements If a trigger is received while CV is decrementing CV then increments See Figure 31 14 RC Compare can stop the counter clock CPCSTOP 1 and or disable the counter clock CPCDIS 1 Figure 31 13 WAVSEL 11 Without Trigger Counter Value OxFF
17. EOP End of Programming Status 0 The programming sequence page programming or erase all Flash triggered by the last write in FCR is not yet completed or FMC_FSR has been read 1 The programming sequence page programming or erase all Flash triggered by the last write in FCR is completed and MC FSR has not been read yet EOL End of Lock Status The lock or unlock sequence triggered by the last write in MC FCR is not yet completed FSR has been read The lock or unlock sequence triggered by the last write in FCR is completed and FSR has not been read yet LOCKE Lock Error Status No programming of at least one locked lock region has happened since the last read of MC FSR Programming of at least one locked lock region has happened since the last read of MC FSR PROGE Programming Error Status No invalid commands and no bad key words were written the Flash Command Register MC FCR An invalid command and or bad key word was were written the Flash Command Register MC FCR LOCKSx Lock Region x Lock Status The corresponding lock region is not locked The corresponding lock region is locked e a O a 0 _ o 14 915 7 Preliminary memm 6042E ATARM 14 Dec 06 X 7915 7 Preliminary 21 Peripheral DMA Controller PDC 21 1 Overview 21 2 Block Diagram 6042E ATARM 14 Dec 06 The Peripheral DMA Controller PDC
18. a4 A Co E o CHDIV CLDIV e g 42 E lt o 09 2 o o F 5 a 2 o 2 o A 99 Tow CLDIV x 2 3 x Tuck CHDIV Clock High Divider The SCL high period is defined as follows Thigh x 20 3 x CKDIV Clock Divider The CKDIV is used to increase both SCL high and low periods J AIMEL 26 6042 14 06 AMEL 28 6 5 TWI Status Register Register Name TWI_SR Access Type Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 E ee _ 7 6 5 4 3 2 1 0 TXCOMP Transmission Completed 0 In master during the length of the current frame In slave from START received to STOP received 1 When both holding and shift registers are empty and STOP condition has been sent in Master or when MSEN is set enable TWI RXRDY Receive Holding Register Ready No character has been received since the last TWI read operation 1 A byte has been received in the TWI_RHR since the last read TXRDY Transmit Holding Register Ready 0 The transmit holding register has not been transferred into shift register Set to 0 when writing into TWI_THR register 1 As soon as data byte is transferred from TWI_THR to internal shifter or if
19. s 5 os osfos osfor P Jam SOS RXRDY PARE Wrong Parity Bit RSTSTA 25 4 2 6 Receiver Framing Error 25 4 3 Transmitter When a start bit is detected it generates a character reception when all the data bits have been sampled The stop bit is also sampled and when it is detected at 0 the FRAME Framing Error bit in DBGU_SR is set at the same time the RXRDY bit is set The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1 Figure 25 9 Receiver Framing Error omo s oo oi ez os vs vs os sep RXRDY FRAME Stop Bit RSTSTA Detected at 0 25 4 3 1 Transmitter Reset Enable and Disable After device reset the Debug Unit transmitter is disabled and it must be enabled before being used The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1 From this command the transmitter waits for a character to be written in the Transmit Hold ing Register before actually starting the transmission The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1 If the transmitter is not operating it is immediately stopped However if a character is being pro cessed into the Shift Register and or a character has been written in the Transmit Holding Register the characters are completed before the transmitter is actually stopped The programmer can also put the transmitter in its reset state by writing the
20. 2 The application writes the first packet of data to be sent in the endpoint s FIFO writing zero or more byte values in the endpoints UDP_ FDRx register 3 The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoints UDP CSRx register 4 The application is notified that the endpoint s FIFO has been released by the USB device when TXCOMP in the endpoint s UDP_ CSRx register has been set Then an interrupt for the corresponding endpoint is pending while TXCOMP is set 5 The microcontroller writes the second packet of data to be sent in the endpoint s FIFO writing zero more byte values in the endpoint s UDP_ FDRx register 6 The microcontroller notifies the USB peripheral it has finished by setting the TXPK TRDY in the endpoint s UDP_ CSRx register 7 The application clears the in the endpoints UDP_ CSRx After the last packet has been sent the application must clear TXCOMP once this has been set TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet An interrupt is pending while TXCOMP is set Warning TX COMP must be cleared after TX PKTRDY has been set Note Refer to Chapter 8 of the Universal Serial Bus Specification Rev 2 0 for more information on the Data IN protocol layer AT9ISAM7A3 Preliminary memm 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary Figure 33 6 Data Transfer for Non Ping pong
21. FSOS Receive Frame Sync Output Selection FSOS Selected Receive Frame Sync Signal RF Pin 0x0 None Input only 0 1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6 0x7 Reserved Undefined FSEDGE Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register FSEDGE Frame Sync Edge Detection 0x0 Positive Edge Detection 0x1 Negative Edge Detection A MEL 340 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary 30 8 5 SSC Transmit Clock Mode Register Name SSC_TCMR Access Type Read Write 31 30 29 28 27 26 25 24 PERIOD 23 22 21 20 19 18 17 16 STTDLY 15 14 13 12 11 10 9 8 ee START 7 6 5 4 3 2 1 0 CKG CKS CKS Transmit Clock Selection CKS Selected Transmit Clock 0 0 Divided Clock 0x1 RK Clock signal 0x2 TK Pin 0x3 Reserved CKO Transmit Clock Output Mode Selection CKO Transmit Clock Output Mode TK pin 0x0 None Input only 0x1 Continuous Transmit Clock Output 0x2 Transmit Clock only during data transfers Output 0x3 0x7 Reserved CKI Transmit Clock Inversion 0 The data outputs Data and Frame Sync signals are shifted out on Transmit Clock falling edge The Frame sync
22. PRIOR Priority Level Programs the priority level for all sources except FIQ source source 0 The priority level can be between 0 lowest and 7 highest The priority level is not used for the FIQ the related SMR register AIC SMRx SRCTYPE Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources SRCTYPE Internal Interrupt Sources External Interrupt Sources 0 0 High level Sensitive Low level Sensitive 0 1 Positive edge triggered Negative edge triggered 1 0 High level Sensitive High level Sensitive 1 1 Positive edge triggered Positive edge triggered A MEL 141 6042E ATARM 14 Dec 06 AMEL 22 8 4 AIC Source Vector Register Register Name AIC_SVRO AIC_SVR31 Access Type Read Write Reset Value 0x0 31 30 29 28 27 26 25 24 N N o A N A ar en A E en A I A A 22 8 5 AIC Interrupt Vector Register Register Name AIC_IVR Access Type Read only Reset Value 0x0 31 30 29 28 27 26 25 24 A N o E N E E A A 99 A A i zx Si A 99 A The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read When there is no current interrupt the Interrupt Vector Register reads the
23. A MEL 383 6042E ATARM 14 Dec 06 AMEL 31 6 9 TC Register A Register Name TC_RA Access Type Read only if WAVE 0 Read Write if WAVE 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 gt 7 6 5 4 3 2 1 0 A RA RA Register A RA contains the Register A value in real time AT91SAM7AS3 Preliminary mm 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary Register Name TC_RB Access Type Read only if WAVE 0 Read Write if WAVE 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A RB Register RB contains the Register value real time 31 6 11 TC Register C Register Name TC_RC Access Type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E A A A En zx c si A m Oo A O RC Register RC contains the Register C value in real time ATMEL s 6042E ATARM 14 Dec 06 AMEL 31 6 12 TC Status Register Register Name TC_SR Access Type Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E MTIOA CLKSTA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS Counter Overflow Status 0 No counter overflow has occurred since the last read of the Status Register 1 counter overflow has occurred since the last read
24. MR 78 915 Preliminary mem 6042E ATARM 14 Dec 06 7915 7 Preliminary Figure 17 2 Watchdog Behavior Watchdog Error FFF Watchdog Underflow if WDRSTEN is 1 Normal behavior WDV if WDRSTEN is 0 Forbidden Window WDD Permitted Window Watcha WDT_CR WDRSTT atchdog Fault ATMEL 6042E ATARM 14 Dec 06 79 AMEL 17 4 Watchdog Timer WDT User Interface Table 17 1 Watchdog Timer WDT Register Mapping Offset Register Name Access Reset Value 0x00 Control Register WDT_CR Write only 0x04 Mode Register WDT_MR Read Write Once Ox3FFF 2FFF 0x08 Status Register WDT SR Read only 0 0000 0000 17 4 1 Watchdog Timer Control Register Register Name WDT CR Access Type Write only 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDRSTT WDRSTT Watchdog Restart 0 No effect 1 Restarts the Watchdog KEY Password Should be written at value OxA5 Writing any other value in this field aborts the write operation 80 915 Preliminary memm 6042E ATARM 14 Dec 06 A1915AM7AG Preliminary 17 4 2 Watchdog Timer Mode Register Register Name WDT MR Access Type Read Write Once 81 30 29 28 27 26 25 24 WDDBGRIT WDD 23 22 21 20 19 18 17 16 WDD 15 13 12 11 10 9 8 WDDIS WDRPROC WDRSTEN WDFIEN WDV 7 6 5 4 3 2
25. Name PIO_IDR Access Type Write only 31 30 29 28 27 26 25 24 P24 23 22 21 20 19 18 17 16 P23 P22 21 20 15 14 13 12 11 10 9 8 Pii Po P9 a 7 6 5 4 3 2 1 0 PO P31 Input Change Interrupt Disable 0 No effect 1 Disables the Input Change Interrupt on the I O line 26 6 16 PIO Controller Interrupt Mask Register Name PIO_IMR Access Type Read only 31 30 29 28 27 26 25 24 P24 23 22 21 20 19 18 17 16 P23 P22 21 20 15 14 13 12 11 10 9 8 Pii Po P8 7 6 5 4 3 2 1 0 PO P31 Input Change Interrupt Mask 0 Input Change Interrupt is disabled on the I O line 1 Input Change Interrupt is enabled on the I O line ATMEL 2 6042E ATARM 14 Dec 06 AMEL 26 6 17 PIO Controller Interrupt Status Register Name PIO_ISR Access Type Read only 31 30 29 28 27 26 25 24 P24 15 14 13 12 11 10 9 8 pn Po Po P8 7 6 5 4 3 2 1 0 e PO P31 Input Change Interrupt Status 0 No Input Change has been detected on the I O line since PIO_ISR was last read or since reset 1 At least one Input Change has been detected on the I O line since PIO_ISR was last read or since reset 26 6 18 PIO Multi driver Enable Register Name PIO_MDER Access Type Write only 31 30 29 28 27 26 25 24 P24 23 22 21 20 19 18 17 16 P23 P22 21 20 15 14 13 12 11 10 9 8 Pii Po P8 7 6 5 4 3 2 1 0 PO P31 Multi Drive Enable 0 No effect 1 Enables Multi Drive on the I O line
26. XW XA XIADRBSTE AC IADRTEB XA XC TADATTON XA X BATA Two bytes internal address v0 XS S XC XC X ORTA XA KE One byte internal address vo XS XK NT Figure 28 6 Master Write with One Byte Internal Address and Multiple Data Bytes TXCOMP SX AOR XW XA KX AK DATA Write THR TXRDY 7 Write THR Write THR Write THR Figure 28 7 Master Read with One Two or Three Bytes Internal Address and One Data Byte Three bytes internal address Two XS X DADR OX WX A XQADRGST6 X AX IADRUSS X A X XA XS X DAR X R X A Two bytes internal address XN KE Two XS XK PADR DX WX AX IADR TS 8 XC IADRTO XA X S X DX RX A DX DX NOX PD One byte internal address XS X Din KX WK AK TABAT KX AK S O DATA XX FD 260 915 Preliminary mem 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary Figure 28 8 Master Read with One Byte Internal Address and Multiple Data Bytes TXCOMP Write START Bit Write STOP Bit RXRDY AA Read RHR Read RHR S Start e P Stop W Write R Read A Acknowledge N Not Acknowledge DADR Device Address IADR Internal Address Figure 28 9 below shows a byte write to an Atmel AT24LC512 EEPROM This demonstrates the use of internal addresses to access the device Figure 28 9 Internal Addre
27. losc Current Consumption After Startup Time 2 5 37 4 2 Main Oscillator Characteristics Table 37 8 Main Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit 1 topmain Crystal Oscillator Frequency 3 16 20 MHz Integrated Load Capacitance Cio Internal Load Capacitance C C XIN XOUT 34 40 46 pF Integrated Load Capacitance E lent L t 17 20 23 F C quivalent Load Capacitance XIN and XOUT in series p Duty Cycle 30 50 70 VppPLL 1 2 to 2V 3 pF 1 topmain 3 MHz 14 5 t tartup m Cs 7 pF 1 16 MHz 1 4 ii Cs 7 pF 1 topmain 20 MHz 1 Ippsr Standby Current Consumption Standby mode 1 pA Q3 MHz 15 Q8 MHz 30 i Ww Pon Drive level 16 MHz 50 u 20 MHz 50 Q3 MHz 150 250 Current dissipation SAMHET pn A DD ON 16 MHz 300 450 20 MHz 9 400 550 Maximum external capacitor Cer on XIN and XOUT s pr Notes 1 Cgisthe shunt capacitance 2 Rg 100 200 Cspunr 2 0 2 5 pF Cy 2 1 5 fF typ worst case using 1 ohm serial resistor on xout 3 Rg 50 100 Cspunrt 2 0 2 5 pF Cy 4 3 fF typ worst case 4 Rg 25 50 Cspunrt 2 5 3 0 pF Cy 7 5 fF typ worst case 5 Rg 20 50 Cspunrt 3 2 4 0 pF Cy 10 8 fF typ worst case 553 6042E ATARM 14 Dec 06 AMEL AMEL 37 4 3 Crystal Characteristics Table 37 9 Crystal Characteristics Symbol Parameter Conditions Min Typ Max Un
28. sur SE 7 6 5 4 3 2 1 0 0 aR ET EN ON RXEN Receive Enable No effect Enables Receive if RXDIS is not set RXDIS Receive Disable No effect Disables Receive If a character is currently being received disables at end of current character reception TXEN Transmit Enable No effect Enables Transmit if TXDIS is not set TXDIS Transmit Disable No effect Disables Transmit If a character is currently being transmitted disables at end of current character transmission SWRST Software Reset No effect Performs a software reset Has priority on any other bit in SSC_CR e A MEL 335 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary 30 8 2 SSC Clock Mode Register Name SSC_CMR Access Type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 cee ee DIV 7 6 5 4 3 2 1 0 DIV DIV Clock Divider 0 The Clock Divider is not active Any Other Value The Divided Clock equals the Master Clock divided by 2 times DIV The maximum bit rate is MCK 2 The minimum bit rate is MCK 2 x 4095 MCK 8190 A MEL 336 6042E ATARM 14 Dec 06 mes 91 SAM7A3 Preliminary 30 8 3 SSC Receive Clock Mode Register Name SSC_RCMR Access Type Read Write 31 30 29 28 27 26 25 24 PERIOD 23 22 21 20 19 18 17 16 STDDLY 15 13 12 11 10 9 8 STOP START 7 6 5 4 3 2 1 0 CKG CKS
29. 15 14 13 12 10 7 6 5 4 2 1 Corresponding interrupt is pending 22 8 9 AIC Interrupt Mask Register Register Name AIC IMR Access Type Read only Reset Value 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PD Pie PID4 PID3 PID2 FIQ SYS PID2 PID31 Interrupt Mask 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled 144 915 7 Preliminary meem 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary 22 8 10 AIC Core Interrupt Status Register Register Name AIC_CISR Access Type Read only Reset Value 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 NFIQ NFIQ Status nFIQ line is deactivated 1 nFIQ line is active NIRQ NIRQ Status nIRQ line is deactivated 1 2 nIRQ line is active 22 8 11 AIC Interrupt Enable Command Register Register Name AIC IECR Access Type Write only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 pioz Pie PID5 PID4 PID3 PID2 FIQ SYS PID2 PID3 Interrupt Enable 0 No effect 1 Enables corresponding interrupt AMEL
30. 15 14 13 12 11 10 9 8 Ca Cea sm c DIA 7 6 5 4 3 2 1 0 DATA DATA Converted Data The analog to digital conversion data is placed into this register at the end of a conversion and remains until a new conver sion is completed The Convert Data Register CDR is only loaded if the corresponding analog channel is enabled A MEL 492 6042E ATARM 14 Dec 06 mes 7915 7 Preliminary 36 Controller Area Network CAN 36 1 Overview 6042E ATARM 14 Dec 06 The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH the CAN specification as referred to by ISO 11898A 2 0 Part A and 2 0 Part B for high speeds and ISO 11519 2 for low speeds The CAN Controller is able to handle all types of frames Data Remote Error and Overload and achieves a bitrate of 1 Mbit sec CAN controller accesses are made through configuration registers 16 independent message objects mailboxes are implemented Any mailbox can be programmed as a reception buffer block even non consecutive buffers For the reception of defined messages one or several message objects can be masked with out participating in the buffer feature An interrupt is generated when the buffer is full According to the mailbox configuration the first message received can be locked in the CAN controller registers until the application acknowledges it or this message can be discarded
31. 164 25 Debug Unit DBGU ausis 181 25 4 OVOIVIOW i reca E e ORENSE EE basa Yu 181 iv AT91SAM7A3 Preliminary memm 6042E ATARM 14 Dec 06 91 SAM7A3 Preliminary 25 2 Block rite te ne esee eere pn e dde 182 25 3 Product Dependencies 2 183 25 4 UART Operations nein eaten FE ERES 183 25 5 Debug Unit User Interface eene 190 26 Parallel Input Output Controller PIO 205 oUONMEOU TSCIUR 205 26 2 Block 206 26 3 Product Dependencies 207 26 4 Functional Description 208 26 5 I O Lines Programming Example sese 213 26 6 User Interface 214 27 Serial Peripheral Interface SPI 231 27 1 231 27 2 Block Diagram acie be ER Ro Re 232 27 3 Application Block Diagrar oie Dent ee eu eas 233 27 4 Signal Description ssssssssssseseseseeeeeeneen eren 234 27 5 Product Dependencies 00 nnn 234 27 6 Functional Description
32. 3 3 Wait State Cycles 3 Wait State Cycles 3 Wait State Cycles 3 Wait State Cycles 1 1 1 1 1 o e 1 1 Master Clock ARM Request 16 bit Code Fetch GByte 0 G2 Q4 G6 10 12 Fl sh Access Bytes 0 3 Bytes 4 7 Bytes 8 11 Bytes 12 15 erezni XXXXXXXXX e X ear Data To ARM KAKs X KT KX Nas Note When FWS is equal to 2 or 3 in case of sequential reads the first access takes FWS cycles the second access one cycle the third access FWS cycles the fourth access one cycle etc 20 2 3 Write Operations The internal memory area reserved for the Embedded Flash can also be written through a write only latch buffer Write operations take into account only the 8 lowest address bits and thus wrap around within the internal memory area address space and appear to be repeated 1024 times within it Write operations might be prevented by programming the Memory Protection Unit of the product Writing of 8 bit and 16 bit data is not allowed and may lead to unpredictable data corruption Write operations are performed in the number of wait states equal to the number of wait states for read operations 1 except for FWS 3 see MC Flash Mode Register on page 110 20 2 4 Flash Commands The Embedded Flash Controller offers a command set to manage programming the memory flash locking and unlocking lock regio
33. 34 9 4 MCI SDCard Register Name MCI_SDCR Access Type Read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 sccus SDCSEL SDCard Slot SDCSEL SDCard Slot 0 Slot A is selected 1 1 0 1 1 e SDCBUS SDCard Bus Width 1 bit data bus 1 4 bit data bus A MEL 464 6042E ATARM 14 Dec 06 X 7915 7 Preliminary 34 9 5 MCI Argument Register Name MCI_ARGR Access Type Read write 31 30 29 28 27 26 25 24 ARG 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARG ARG Command Argument ATMEL 6042E ATARM 14 Dec 06 mes 91 SAM7A3 Preliminary 34 9 6 MCI Command Register Name MCI_CMDR Access Type Write only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C gt l s TRTYP TRDIR TRCMD 15 14 13 12 11 10 9 8 D e ma OPDCMD SPCMD 7 6 5 4 3 2 1 0 RSPTYP CMDNB This register is write protected while CMDRDY is 0 in MCI_SR If an Interrupt command is sent this register is only write able by an interrupt response field SPC

ATMEL AT91SAM7A3 handbook (1)(1)

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