ATMEL AT91SAM9260 handbook
Contents
1. AT91SAM9260 F 4833 Power Management Controller Block Diagram on page 30 Corrected package reference to PQFP in Figure 11 2 208 lead PQFP Package 4740 Drawing on page 42 Updated BGA ordering code in Section 43 AT91SAM9260 Ordering Information on 4768 page 780 6221FS All new information in Section 7 2 1 Matrix Masters Table 7 1 List of Bus Matrix A Masters on page 18 and Section 7 2 3 Master to Slave Access Table 7 3 4457 AT91SAM9260 Masters to Slaves Access on page 18 In Figure 2 1 AT91SAM9260 Block Diagram on page 4 updated EBI signals NRD 4431 NWRO NWR1 NWRS3 Added details on Timer Counter blocks in Section 10 4 5 Timer Counter on page 38 4369 Updated Chip ID in Section 9 12 Chip Identification on page 32 4582 Updated information on programmable pull up resistor in Section 6 4 PIO Controllers on page 16 3972 Updated Section 6 7 Slow Clock Selection on page 16 6221ES In Table 10 1 AT91SAM9260 Peripheral Identifiers on page 32 added Note 3504 and 3543 on clocking and corrected Peripheral Name for PID12 PID13 and PID14 Placed comment on RDY BUSY with PC13 in Table 10 4 Multiplexing on PIO 3406 Controller C on page 36 AIMEL ee 6221HS ATARM 31 Jan 08 ay AMEL Table 13 1 Revision History current version appears first Change Request Revision Comments Ref Removed references to2. Six 32 bit layer Matrix Boot Mode Select Option Remap Command Fully featured System Controller including Reset Controller Shutdown Controller Four 32 bit Battery Backup Registers for a Total of 16 Bytes Clock Generator and Power Management Controller Advanced Interrupt Controller and Debug Unit Periodic Interval Timer Watchdog Timer and Real time Timer Reset Controller RSTC Based on a Power on Reset Cell Reset Source Identification and Reset Output Control e Clock Generator CKGR Selectable 32 768 Hz Low power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply Providing a Permanent Slow Clock 3 to 20 MHz On chip Oscillator One up to 240 MHz PLL and One up to 130 MHz PLL Power Management Controller PMC Very Slow Clock Operating Mode Software Programmable Power Optimization Capabilities Two Programmable External Clock Signals e Advanced Interrupt Controller AIC Individually Maskable Eight level Priority Vectored Interrupt Sources Three External Interrupt Sources and One Fast Interrupt Source Spurious Interrupt Protect errupt Protected 6221HS ATARM 31 Jan 08 AIMEL EEE C AMEL Debug Unit DBGU 2 wire UART and Support for Debug Communication Channel Programmable ICE Access Prevention Periodic Interval Timer PIT 20 bit Interval Timer plus 12 bit Interval Counter Watchdog Timer WDT Key protected Progra
3. A25 Address Bus Output 0 at reset NWAIT External Wait Signal Input Low Static Memory Controller SMC NCS0 NCS7 Chip Select Lines Output Low NWRO NWR3 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0 NBS3 Byte Mask Signal Output Low CompactFlash Support CFCE1 CFCE2 CompactFlash Chip Enable Output Low CFOE CompactFlash Output Enable Output Low CFWE CompactFlash Write Enable Output Low CFIOR CompactFlash IO Read Output Low CFIOW CompactFlash IO Write Output Low CFRNW CompactFlash Read Not Write Output CFCSO CFCS1 CompactFlash Chip Select Lines Output Low 6 AT91SAM926O ws m 6221HS ATARM 31 Jan 08 mm rr TO 1 SAM9260 Table 3 1 Signal Description List Continued Active Signal Name Function Type Level Comments NAND Flash Support NANDCS NAND Flash Chip Select Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDALE NAND Flash Address Latch Enable Output Low NANDCLE NAND Flash Command Latch Enable Output Low SDRAM Controller SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output High SDCS SDRAM Controller Chip Select Output Low BAO BA1 Bank Select Output SDWE SDRAM Write Enable Output Low RAS CAS Row and Column Signal Output Low SDA10 SDRAM Address 10 Line Output Multimedia Card Interface MCI MCCK Multimedi
4. 10 3 2 PIO Controller B Multiplexing Table 10 3 Multiplexing on PIO Controller B PIO Controller B Application Usage O Line Peripheral A Peripheral B Comments Reset State Power Supply Function Comments PBO SPI1_MISO TIOAS 1 0 VDDIOP0 PB1 SPI1_MOSI TIOB3 I O VDDIOPO PB2 SPI1_SPCK TIOA4 I O VDDIOPO PB3 SPI1_NPCSO TIOA5 1 0 VDDIOPO PB4 TXDO 1 0 VDDIOPO PB5 RXDO I O VDDIOPO PB6 TXD1 TCLK1 1 0 VDDIOPO PB7 RXD1 TCLK2 1 0 VDDIOPO PB8 TXD2 1 0 VDDIOPO PB9 RXD2 I O VDDIOPO PB10 TXD3 ISI_D8 1 0 VDDIOP1 PB11 RXD3 ISI_D9 I O VDDIOP1 PB12 TXD5 ISI_D10 O VDDIOP1 PB13 RXD5 ISI_D11 O VDDIOP1 PB14 DRXD 1 0 VDDIOPO PB15 DTXD 1 0 VDDIOP0 PB16 TKO TCLK3 1 0 VDDIOPO PB17 TF0 TCLK4 1 0 VDDIOP0 PB18 TD0 TIOB4 1 0 VDDIOPO PB19 RDO TIOB5 1 0 VDDIOP0 PB20 RK0 ISI_DO 1 0 VDDIOP1 PB21 RFO ISI_D1 I O VDDIOP1 PB22 DSRO ISI_D2 1 0 VDDIOP1 PB23 DCD0 ISI_D3 1 0 VDDIOP1 PB24 DTRO ISI_D4 1 0 VDDIOP1 PB25 RIO ISI_D5 I O VDDIOP1 PB26 RTSO ISI_D6 1 0 VDDIOP1 PB27 CTS0 ISI_D7 1 0 VDDIOP1 PB28 RTS1 ISI_PCK 1 0 VDDIOP1 PB29 CTS1 ISI_VSYNC 1 0 VDDIOP1 PB30 PCK0 ISILHSYNC 1 0 VDDIOP1 PB31 PCK1 ISI_MCK 1 0 VDDIOP1 Note 1 Not available in the 208 lead PQFP package AMEL s 6221HS ATARM 31 Jan 08 AMEL 1
5. 15 Reserved 16 Reserved 17 TCO Timer Counter 0 18 TC1 Timer Counter 1 19 TC2 Timer Counter 2 20 UHP USB Host Port 21 EMAC Ethernet MAC 22 ISI Image Sensor Interface 23 US3 USART 3 24 US4 USART 4 25 US5 USART 5 26 TC3 Timer Counter 3 27 TC4 Timer Counter 4 28 TC5 Timer Counter 5 6221HS ATARM 31 Jan 08 mm nrn TO SAM9260 Table 10 1 AT91SAM9260 Peripheral Identifiers Continued Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt 29 AIC Advanced Interrupt Controller IRQ0 30 AIC Advanced Interrupt Controller IRQ1 31 AIC Advanced Interrupt Controller IRQ2 Note Setting AIC SYSC UHP ADC and IRQ0 2 bits in the clock set clear registers of the PMC has no effect The ADC clock is auto matically started for the first conversion In Sleep Mode the ADC clock is automatically stopped after each conversion 10 2 1 Peripheral Interrupts and Clock Control 10 2 1 1 System Interrupt The System Interrupt in Source 1 is the wired OR of the interrupt signals coming from e the SDRAM Controller e the Debug Unit e the Periodic Interval Timer e the Real time Timer e the Watchdog Timer e the Reset Controller e the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller 10 2 1 2 External Interrupts All external interrupt signals i e the Fast Interrupt signal FIQ or
6. 3V nominal and power supply pins can accept either 1 8V or 3 3V Obviously the device cannot reach its maximum speed if the voltage supplied to the pins is 1 8V only The user must program the EBI voltage range before getting the device out of its Slow Clock Mode I O Line Considerations JTAG Port Pins Test Pin Reset Pins 6221HS ATARM 31 Jan 08 TMS TDI and TCK are Schmitt trigger inputs and have no pull up resistors TDO and RTCK are outputs driven at up to VDDIOPO and have no pull up resistors The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level tied to VDDBU It integrates a permanent pull down resistor of about 15 kO to GNDBU so that it can be left unconnected for normal operations The NTRST signal is described in Section 6 3 All the JTAG signals are supplied with VDDIOPO The TST pin is used for manufacturing test purposes when asserted high It integrates a perma nent pull down resistor of about 15 kQ to GNDBU so that it can be left unconnected for normal operations Driving this line at a high level leads to unpredictable results This pin is supplied with VDDBU NRST is a bidirectional with an open drain output integrating a non programmable pull up resis tor It can be driven with voltage at up to VDDIOPO NTRST is an input which allows reset of the JTAG Test Access port It has no action on the processor As the product integrates power on reset cells which manages the
7. 69 CFOE NRD 121 D10 173 GND 18 PB7 70 CFWE NWE NWR0 122 D11 174 VDDCORE 19 PB8 71 NANDOE 123 D12 175 PB28 20 PB9 72 NANDWE 124 D13 176 PB29 21 PB14 73 A22 125 D14 177 PB30 22 PB15 74 A21 126 D15 178 PB31 23 PB16 75 A20 127 PC15 179 PA0 24 VDDIOPO 76 A19 128 PC16 180 PA1 25 GND 77 VDDCORE 129 PC17 181 PA2 26 PB17 78 GND 130 PC18 182 PAS 27 PB18 79 A18 131 PC19 183 PA4 28 PB19 80 BA1 A17 132 VDDIOM 184 PA5 29 TDO 81 BAO A16 133 GND 185 PA6 30 TDI 82 A15 134 PC20 186 PA7 31 TMS 83 A14 135 PC21 187 VDDIOPO 32 VDDIOPO 84 A13 136 PC22 188 GND 33 GND 85 A12 137 PC23 189 PA8 34 TCK 86 A11 138 PC24 190 PA9 35 NTRST 87 A10 139 PC25 191 PA10 36 NRST 88 A9 140 PC26 192 PA11 37 RTCK 89 A8 141 PC27 193 PA12 38 VDDCORE 90 VDDIOM 142 PC28 194 PA13 39 GND 91 GND 143 PC29 195 PA14 40 BMS 92 A7 144 PC30 196 PA15 41 OSCSEL 93 A6 145 PC31 197 PA16 42 TST 94 A5 146 GND 198 PA17 43 JTAGSEL 95 A4 147 VDDCORE 199 VDDIOPO 44 GNDBU 96 A3 148 VDDPLL 200 GND 45 XOUT32 97 A2 149 XIN 201 PA18 46 XIN32 98 NWR2 NBS2 A1 150 XOUT 202 PA19 47 VDDBU 99 NBS0 A0 151 GNDPLL 203 VDDCORE 48 WKUP 100 SDA10 152 NC 204 GND AIMEL i 6221HS ATARM 31 Jan 08 ey AMEL Table 4 1 Pinout for 208 pin PQFP Package Continued Pin Signal Name Pin T Signal Name FPin Signal Name Pin Signal Name 44 SHDN 10 CFIOWNBS3NWR3 153 GNDPLL 205 PA20 50 HDMA 102 CFIOR NBS1 NWR1 154 PLLRCA 206 PA21 51 HDPA 103 SDCS N
8. COMMRX and COMMTX signals from the ARM Processor s ICE Interface 9 12 Chip Identification e Chip ID 0x019803A2 e JTAG ID 0x05B1303F e ARM926 TAP ID 0x0792603F AMEL i 6221HS ATARM 31 Jan 08 AMEL 10 Peripherals 10 1 User Interface The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF Each User Peripheral is allocated 16 Kbytes of address space A complete memory map is presented in Figure 8 1 on page 21 10 2 Identifiers Table 10 1 defines the Peripheral Identifiers of the AT91SAM9260 A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller Table 10 1 AT91SAM9260 Peripheral Identifiers Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt 0 AIC Advanced Interrupt Controller FIQ 1 SYSC System Controller Interrupt 2 PIOA Parallel I O Controller A 3 PIOB Parallel I O Controller B 4 PIOC Parallel I O Controller C 5 ADC Analog to Digital Converter 6 USO USART 0 7 US1 USART 1 8 US2 USART 2 9 MCI Multimedia Card Interface 10 UDP USB Device Port 11 TWI Two wire Interface 12 SPI0 Serial Peripheral Interface 0 13 SPI1 Serial Peripheral Interface 1 14 SSC Synchronous Serial Controller
9. Master and Slave interfaces with additional features Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCSO to EBI_NCS7 Bank 0 is reserved for the addressing of the internal memories and a second level of decoding provides 1 Mbyte of internal memory area Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus APB Other areas are unused and performing an access within them provides an abort to the master requesting such an access Each Master has its own bus and its own decoder thus allowing a different memory mapping per Master However in order to simplify the mappings all the masters have a similar address decoding Regarding Master 0 and Master 1 ARM926 Instruction and Data three different Slaves are assigned to the memory space decoded at address 0x0 one for internal boot one for external boot one after remap Refer to Table 8 1 Internal Memory Mapping on page 22 for details A complete memory map is presented in Figure 8 1 on page 21 8 1 Embedded Memories e 32 KB ROM Single Cycle Access at full matrix speed Two 4 KB Fast SRAM Single Cycle Access at full matrix speed 8 1 1 Boot Strategies Table 8 1 summarizes the Internal Memory Mapping for each Master depending on the Remap status and the BMS state at reset Table 8 1 Internal Memo
10. VDDOSC in Features in Table 3 1 Signal Description List and in Section 5 1 Power Supplies on page 14 Corrected VDDPLLA and VDDPLLB with VDDPLL and GNDPLLA and GNDPLLB with GNDPLL in Table 4 1 3183 Pinout for 208 pin PQFP Package on page 11 and in Table 4 2 Pinout for 217 ball LFBGA Package on page 13 In Figure 2 1 on page 4 corrected range for SCKx pins label change on matrix 3235 3071 6221DS block In Figure 2 1 on page 4 and Section 7 3 Peripheral DMA Controller on page 3066 19 removed TWI PDC channels In Section 6 3 Reset Pins on page 15 added NRST as bidirectional 3236 In Figure 9 3 on page 30 added UHPCK as USB Clock Controller output 3237 In Section 10 4 3 USART on page 37 added information on modem signals 3245 For VDDIOP1 added supported voltage levels in Table 3 1 Signal Description List on page 5 and corrected supported voltage levels in Section 5 2 Power 2874 Consumption on page 14 Removed package marking and updated package outline information in Section 4 Package and Pinout on page 10 man Change to signal name for pin 147 in Section 4 1 Pinout for 208 pin PQFP 2907 Package on page 11 6221CS En Inserted new voltage information for JTAGSEL signal in Table 3 1 Signal 2047 Description List and in Section 6 1 JTAG Port Pins on page 15 In Table 3 1 Signal Descripti
11. processor and the JTAG reset the NRST and NTRST pins can be left unconnected The NRST and NTRST pins both integrate a permanent pull up resistor to VDDIOPO Its value can be found in the table DC Characteristics in the section AT91SAM9260 Electrical Charac teristics in the product datasheet The NRST signal is inserted in the Boundary Scan AMEL is AMEL 6 4 PIO Controllers All the I O lines managed by the PIO Controllers integrate a programmable pull up resistor Refer to the section on DC Characteristics in AT91SAM9260 Electrical Characteristics for more information Programming of this pull up resistor is performed independently for each I O line through the PIO Controllers After reset all the I O lines default as inputs with pull up resistors enabled except those which are multiplexed with the External Bus Interface signals and that must be enabled as Peripheral at reset This is explicitly indicated in the column Reset State of the PIO Controller multiplexing tables 6 5 I O Line Drive Levels The PIO lines are high drive current capable Each of these I O lines can drive up to 16 mA per manently except PC4 to PC31 that are VDDIOM powered 6 6 Shutdown Logic Pins The SHDN pin is an output only which is driven by the Shutdown Controller The pin WKUP is an input only It can accept voltages only between OV and VDDBU 6 7 Slow Clock Selection The AT91SAM9260 slow clock can be generated either by
12. the user to power the device differently for interfacing with memories and for interfacing with peripherals Ground pins GND are common to VDDCORE VDDIOM VDDIOPO and VDDIOP1 pins power supplies Separated ground pins are provided for VDDBU VDDPLL and VDDANA These ground pins are respectively GNDBU GNDPLL and GNDANA Power Consumption The AT91SAM9260 consumes about 500 pA of static current on VDDCORE at 25 C This static current rises up to 5 mA if the temperature increases to 85 C On VDDBU the current does not exceed 10 pA in worst case conditions For dynamic power consumption the AT91SAM9260 consumes a maximum of 100 mA on VDDCORE at maximum conditions 1 8V 25 C processor running full performance algorithm out of high speed memories AT91SAM9260 m n 6221HS ATARM 31 Jan 08 mman A T 9 1 SAM9260 5 3 6 6 1 6 2 6 3 Programmable I O Lines Power Supplies The power supplies pins VDDIOM accept two voltage ranges This allows the device to reach its maximum speed either out of 1 8V or 3 3V external memories The target maximum speed is 100 MHz on the pin SDCK SDRAM Clock loaded with 30 pF for power supply at 1 8V and 50 pF for power supply at 3 3V The other signals control address and data signals do not exceed 50 MHz The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface At reset the selected voltage defaults to 3
13. 0 3 3 PIO Controller C Multiplexing Table 10 4 Multiplexing on PIO Controller C PIO Controller C Application Usage 1 0 Line Peripheral A Peripheral B Comments Reset State Power Supply Function Comments PCO SCK3 AD0 I O VDDANA PC1 PCK0 AD1 I O VDDANA pal PCK1 AD2 Vo VDDANA poat SPI1_NPCS3 AD3 Vo VDDANA PC4 A23 SPI1_NPCS2 A23 VDDIOM PC5 A24 SPI1_NPCS1 A24 VDDIOM PC6 TIOB2 CFCE1 I O VDDIOM PC7 TIOB1 CFCE2 I O VDDIOM PC8 NCS4 CFCS0 RTS3 I O VDDIOM PC9 NCS5 CFCS1 TIOBO I O VDDIOM PC10 A25 CFRNW CTS3 A25 VDDIOM PC11 NCS2 SPI0_NPCS1 I O VDDIOM PC12 IRQ0 NCS7 O VDDIOM PC13 FIQ NCS6 I O VDDIOM PC14 NCS3 NANDCS IRQ2 I O VDDIOM PC15 NWAIT IRQ1 I O VDDIOM PC16 D16 SPIO_NPCS2 I O VDDIOM PC17 D17 SPI0_NPCS3 I O VDDIOM PC18 D18 SPI1_NPCS1 I O VDDIOM PC19 D19 SPI1_NPCS2 I O VDDIOM PC20 D20 SPI1_NPCS3 I O VDDIOM PC21 D21 EF100 I O VDDIOM PC22 D22 TCLK5 I O VDDIOM PC23 D23 I O VDDIOM PC24 D24 I O VDDIOM PC25 D25 I O VDDIOM PC26 D26 I O VDDIOM PC27 D27 I O VDDIOM PC28 D28 I O VDDIOM PC29 D29 I O VDDIOM PC30 D30 I O VDDIOM PC31 D31 I O VDDIOM Note 1 Not available in the 208 lead PQFP package 36 AT91SAM9260 mmm 6221HS ATARM 31 Jan 08 mm rrrrc n rr n A T 9 1 SAM9260 10 4 Embedded Peripherals 10 4 1 Serial Peripheral Interface e Supports communication with serial external devices Four chip selects with external decoder support allow communication with up to 15 peripherals Serial memories such as DataFlash
14. 17 XIN32 K15 PB17 R12 PA5 A14 NCS0 E1 D10 K16 GND R13 PA10 A15 PC5 E2 D5 K17 PB15 R14 PA21 A16 PC6 E3 D3 L1 GND R15 PA23 A17 PC4 E4 D4 L2 PC26 R16 PA24 B1 SDCK E14 HDPA L3 PC25 R17 PA29 B2 CFIOR NBS1 NWR1 E15 HDMA L4 VDDIOP0 T1 PLLRCA B3 SDCS NCS1 E16 GNDBU L14 PA28 T2 GNDPLL B4 SDA10 E17 XOUT32 L15 PB9 T3 PC0 B5 A3 F1 D13 L16 PB8 T4 PC1 B6 A7 F2 SDWE L17 PB14 T5 PB10 B7 A12 F3 D6 M1 VDDCORE T6 PB22 B8 A15 F4 GND M2 PC31 T7 GND B9 A20 F14 OSCSEL M3 GND T8 PB29 B10 NANDWE F15 BMS M4 PC22 T9 PA2 B11 PC7 F16 JTAGSEL M14 PB1 T10 PA6 B12 PC10 F17 TST M15 PB2 T11 PA8 B13 PC13 G1 PC15 M16 PB3 T12 PA11 B14 PC11 G2 D7 M17 PB7 T13 VDDCORE B15 PC14 G3 SDCKE N1 XIN T14 PA20 B16 PC8 G4 VDDIOM N2 VDDPLL T15 GND B17 WKUP G14 GND N3 PC23 T16 PA22 C1 D8 G15 NRST N4 PC27 T17 PA27 C2 D1 G16 RTCK N14 PA31 U1 GNDPLL C3 CAS G17 TMS N15 PA30 U2 ADVREF C4 A2 H1 PC18 N16 PBO U3 PC2 C5 A4 H2 D14 N17 PB6 U4 PC3 C6 A9 H3 D12 P1 XOUT U5 PB20 C7 A14 H4 D11 P2 VDDPLL U6 PB21 C8 BA1 A17 H8 GND P3 PC30 U7 PB25 cg A19 H9 GND P4 PC28 U8 PB27 C10 NANDOE H10 GND P5 PB11 U9 PA12 C11 PC9 H14 VDDCORE P6 PB13 U10 PA13 C12 PC12 H15 TCK P7 PB24 U11 PA14 C13 DDP H16 NTRST P8 VDDIOP1 U12 PA15 C14 HDMB H17 PB18 P9 PB30 U13 PA19 C15 NC J1 PC19 P10 PB31 U14 PA17 AIMEL 13 6221HS ATARM 31 Jan 08 Eoo AMEL Table 4 2 Pinout for 217 ball LFBGA Package Continued Pin Signal Name Pin SignalName Pin Signal Name Pin Sig
15. BDTIC www bdtic com ATMEL Features Incorporates the ARM926EJ S ARM Thumb Processor DSP Instruction Extensions ARM Jazelle Technology for Java Acceleration 8 KByte Data Cache 8 KByte Instruction Cache Write Buffer 200 MIPS at 180 MHz Memory Management Unit EmbeddedICE Debug Communication Channel Support Additional Embedded Memories One 32 KByte Internal ROM Single cycle Access At Maximum Matrix Speed G Two 4 KByte Internal SRAM Single cycle Access At Maximum Matrix Speed AT91 ARM External Bus Interface EBI Supports SDRAM Static Memory ECC enabled NAND Flash and CompactFlash Th u mb e USB 2 0 Full Speed 12 Mbits per second Device Port M icrocontrol lers On chip Transceiver 2 432 byte Configurable Integrated DPRAM USB 2 0 Full Speed 12 Mbits per second Host Single Port in the 208 lead PQFP Package and Double Port in 217 ball LFBGA Package Single or Dual On chip Transceivers AT91 SAM9260 Integrated FIFOs and Dedicated DMA Channels Ethernet MAC 10 100 Base T Media Independent Interface or Reduced Media Independent Interface 28 byte FIFOs and Dedicated DMA Channels for Receive and Transmit Image Sensor Interface ITU R BT 601 656 External Interface Programmable Frame Capture Rate Su mmary 12 bit Data Interface for Support of High Sensibility Sensors SAV and EAV Synchronization Preview Path with Scaler YCbCr Format Bus Matrix
16. CS1 155 VDDPLL 207 PA22 52 VDDIOPO 104 CAS 156 GNDANA 208 PA23 43 217 ball LFBGA Package Outline Figure 4 2 shows the orientation of the 217 ball LFBGA package A detailed mechanical description is given in the section AT91SAM9260 Mechanical Character istics of the product datasheet Figure 4 2 217 ball LFBGA Package Top View 17 ooooooooooooooooo 16 ooooooooooooooooo 15 OOOOOOO OOOOOOOO 14 ooooooo OOOOOOOO 13 oooo 12 oooo 11 0000 10 0000 9 0000 8 oooo 7 oooo0 6 oooo0 5 oo oo 4 OOOOOOOOOOOOOOOOO 3 OOOOOOOOOOOOOOOOO 2 OOOOOOOOOOOOOOOOO 1 OOOOOOOOOOOOOOOOO if ABCDEFGHJKLMNPRTU Ball A1 12 AT91SAM9260 cmp mman A T 9 1 SAM9260 4 4 217 ball LFBGA Pinout Table 4 2 Pinout for 217 ball LFBGA Package Pin J Signali Name Pin SignalName Pin SignalName Pin SignalName AT CFIOW NBS3 NWR3 D5 AS ji TTDO Pi7 PB5 A2 NBS0 A0 D6 GND J15 PB19 R1 NC A3 NWR2 NBS2 A1 D7 A10 J16 TDI R2 GNDANA A4 A6 D8 GND J17 PB16 R3 PC29 A5 A8 D9 VDDCORE K1 PC24 R4 VDDANA A6 A11 D10 GND K2 PC20 R5 PB12 A7 A13 D11 VDDIOM K3 D15 R6 PB23 A8 BAO A16 D12 GND K4 PC21 R7 GND AQ A18 D13 DDM K8 GND R8 PB26 A10 A21 D14 HDPB K9 GND R9 PB28 A11 A22 D15 NC K10 GND R10 PA0 A12 CFWE NWE NWR0 D16 VDDBU K14 PB4 R11 PA4 A13 CFOE NRD D
17. DFlash e Full 32 bit External Data Bus e Up to 26 bit Address Bus up to 64MBytes linear Up to 8 chip selects Configurable Assignment Static Memory Controller on NCSO SDRAM Controller or Static Memory Controller on NCS1 Static Memory Controller on NCS2 Static Memory Controller on NCS3 Optional NAND Flash support Static Memory Controller on NCS4 NCS5 Optional CompactFlash support Static Memory Controller on NCS6 NCS7 8 2 2 Static Memory Controller 8 16 or 32 bit Data Bus e Multiple Access Modes supported Byte Write or Byte Select Lines Asynchronous read in Page Mode supported 4 up to 32 byte page size e Multiple device adaptability Compliant with LCD Module Control signals programmable setup pulse and hold time for each Memory Bank e Multiple Wait State Management Programmable Wait State Generation External Wait Request Programmable Data Float Time e Slow Clock mode supported 8 2 3 SDRAM Controller e Supported devices Standard and Low power SDRAM Mobile SDRAM e Numerous configurations supported 2K 4K 8K Row Address Memory Parts SDRAM with two or four Internal Banks SDRAM with 16 or 32 bit Datapath e Programming facilities Word half word byte access Automatic page break when Memory Boundary has been reached Multibank Ping pong Access Timing parameters specified by software Automatic refresh operation refresh rate is progra
18. F However all the registers of System Controller are mapped on the top of the address space All the registers of the System Controller can be addressed from a single pointer by using the stan dard ARM instruction set as the Load Store instruction has an indexing mode of 4 Kbytes Figure 9 1 on page 27 shows the System Controller block diagram Figure 8 1 on page 21 shows the mapping of the User Interfaces of the System Controller peripherals AT91SAM9260 man 6221HS ATARM 31 Jan 08 9 1 Figure 9 1 Block Diagram AT91SAM9260 System Controller Block Diagram System Controller VDDCORE Powered irq0 irq2 AT91SAM9260 nirq Advanced nfiq fiq periph_irq 2 24 Interrupt Controller pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq int MCK A ua ss Ropa dbgu_irq dbgu_rxd dbgu_txd Nast kR VDDBU SHDN WKUP MCK Periodic ae debug Interval pit_irq periph_nreset Timer amp oth Watchd lebug atchdog i idle Timer wdt_irq proc_nreset wdt_fault WDRPROC rstc_irq por_ntrst VDDCORE i Pe VDDBU POR periph_nreset Reset proc_nreset Controller backup_nreset VDDBU Powered rtt_irq rtt_alarm backup_nreset SLCK XIN32 XOUT32 osc seL E XIN XOUT PLLRCA Shutdown Controller Backup Registers periph_clk 2 27 pck 0 1 PCK Y i UDPCK anagemen PLLA PLLAC
19. K Controller UHPCK MCK PLLB PLLBCK periph_nreset pmc_irq idle periph_nreset periph_irq 2 4 PA0 PA31 Lk PBO PB31 Lk por_ntrst ntrst ARM926EJ S proc_nreset PCK debug jtag_nreset Boundary Scan TAP Controller MCK Bus Matrix periph_nreset UHPCK periph_clk 20 USB Host periph_nreset Port periph_irq 20 UDPCK periph_clk 10 USB Device eriph_nreset penpn Port periph_irq 10 periph_clk 6 24 periph_nreset Embedded PC0 PC31 Lk 6221HS ATARM 31 Jan 08 periph_clk 2 4 irq0 irq2 Peripherals dbgu_rxd PIO fiq periph_irq 6 24 Controllers dbgu_txd in gt out enable ATNEL K T O AMEL 9 2 Reset Controller Based on two Power on reset cells One on VDDBU and one on VDDCORE e Status of the last reset Either general reset VDDBU rising wake up reset VDDCORE rising software reset user reset or watchdog reset e Controls the internal resets and the NRST pin output Allows shaping a reset signal for the external devices 9 3 Shutdown Controller e Shutdown and Wake up logic Software programmable assertion of the SHDN pin Deassertion Programmable on a WKUP pin level change or on alarm 94 Clock Generator e Embeds a Low power 32 768 Hz Slow Clock Oscillator and a Low power RC oscillator selectable with OSCSEL signal Provides the permanent Slow Clock SLCK to the system e Embeds the Main Oscillator Oscill
20. REF 3 4 5 6 7 8 BP 10 11121314 15 16 17 171615 1413121110 9 8 7 6 5 4 4 2 1 F x Fy O OOOOOOQDOOOOQOOOO A O O O O O O O O Q O O O O O O O O B OPTION PIN A1 IDENTIFIER OOQOOOOOOQQOQOOOOQOQOQOQO C 91 00 0 10 INK PR LASER MARKING oooooooodoooooooo D W OOGO oooo E 8 OOOO OOOO F T oooo oooo G u oooo ooo oooo H SS F 3 R 7 ee G 0e TT OOO ogo oooo K O00 oooo L 5 OOO O OOOO M S oooo oooo N oooooooodoooooooo P ooooooooprpoooooooo0 R ooooooooddoooooooo T Wee me U 1 8 En v 2 15 00 i o fo Gls aTe 2N S S Boll Pitch Substrote Thickness i q 0 80 0 36 1 I C SEATING PLANE Ball Diameter Mold Thickness 4 0 40 0 53 2 wo N 0 36 0 04 1 40 MAX Table 11 1 Soldering Informations Ball Land 0 43 mm 0 05 Soldering Mask Opening 0 30 mm 0 05 Table 11 2 Device and 217 ball LFBGA Package Maximum Weight 450 mg Table 11 3 217 ball LFBGA Package Characteristics Moisture Sensitivity Level 3 Table 11 4 Package Reference JEDEC Drawing Reference MO 205 JESD97 Classification el 6221HS ATARM 31 Jan 08 ay AMEL Figure 11 2 208 lead PQFP Package Drawing LD 4 A DT AZ A1 COTROL DIMENSIONS ARE IN MILLIMETERS MILLIMETER NCH SYMBOL OM MAX A 0 161 Al 0 25 0 010 A2 3 20 3 32 13 60
21. Selects Synchronous Communications Two Three channel 16 bit Timer Counters TC Three External Clock Inputs Two Multi purpose I O Pins per Channel Double PWM Generation Capture Waveform Mode Up Down Capability High Drive Capability on Outputs TIOAO TIOA1 TIOA2 One Two wire Interface TWI Master Multi master and Slave Mode Operation General Call Supported in Slave Mode IEEE 1149 1 JTAG Boundary Scan on All Digital Pins Required Power Supplies 1 65V to 1 95V for VDDBU VDDCORE and VDDPLL 1 65V to 3 6V for VDDIOP1 Peripheral I Os 3 0V to 3 6V for VDDIOPO and VDDANA Analog to digital Converter Programmable 1 65V to 1 95V or 3 0V to 3 6V for VDDIOM Memory I Os Available in a 208 lead PQFP Green and a 217 ball LFBGA Green Package mm rTr rr nr A T 9 1 SAM9260 1 Description The AT91SAM9260 is based on the integration of an ARM926EJ S processor with fast ROM and RAM memories and a wide range of peripherals The AT91SAM9260 embeds an Ethernet MAC one USB Device Port and a USB Host control ler It also integrates several standard peripherals such as the USART SPI TWI Timer Counters Synchronous Serial Controller ADC and MultiMedia Card Interface The AT91SAM9260 is architectured on a 6 layer matrix allowing a maximum internal bandwidth of six 32 bit buses It also features an External Bus Interface capable of interfacing with a wide range of memory devices 2 A
22. T91SAM9260 Block Diagram 6221HS ATARM 31 Jan 08 The block diagram shows all the features for the 217 LFBGA package Some functions are not accessible in the 208 pin PQFP package and the unavailable pins are highlighted in Multiplex ing on PIO Controller A on page 34 Multiplexing on PIO Controller B on page 35 Multiplexing on PIO Controller C on page 36 The USB Host Port B is not available in the 208 pin package Table 2 1 on page 3 defines all the multiplexed and not multiplexed pins not avail able in the 208 PQFP package Table 2 1 Unavailable Signals in 208 lead PQFP Package PIO Peripheral A Peripheral B HDPB HDMB PA30 SCK2 RXD4 PA31 SCKO TXD4 PB12 TXD5 ISI_D10 PB13 RXD5 ISI_D11 PC2 AD2 PCK1 PC3 AD3 SPI1_NPCS3 PC12 IRQO NCS7 AMEL AIMEL See AT91SAM9260 Block Diagram Figure 2 1 SOGNVN ESON SON ASIN SON z3949 13949 MNH49 SeV LSO409 SSON 0S949 7SIN vev ecV LIVMN Leq 9L A ATIONYN eeV 3 1VQNVN LcV AMONYN 3OGqNVN olvas IMAS SV9 SVH AMOS Mods MOIA9 ESAN EHMN HOI49 ESAN LHMN AMA49 AMN OUMN 3049 AYN SOdS LSON OSON LVa L lv 0v8g 9lv Oev 8Lv SLV 2V SHANN cS8N LV 0S8N 0V Sta 0a 1 lonuoo Mowe ones 1J llonuoo WvHaS ysei4 ONYN laa A aT Va IDHO asn osuely osue 1 lonuoo 904 usejgjoedwog J M OSULIL eoIned asn egeHoUI JOSUeS SQV 1q 0L jauueyo p d
23. a Card Clock Output MCCDA Multimedia Card Slot A Command 1 0 MCDAO MCDA3 Multimedia Card Slot A Data 1 0 MCCDB Multimedia Card Slot B Command 1 0 MCDB0 MCDB3 Multimedia Card Slot B Data 0 Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx USARTx Serial Clock I O TXDx USARTx Transmit Data I O RXDx USARTx Receive Data Input RTSx USARTx Request To Send Output CTSx USARTx Clear To Send Input DTR0 USARTO Data Terminal Ready Output DSRO USARTO Data Set Ready Input DCDO USARTO Data Carrier Detect Input RIO USARTO Ring Indicator Input Synchronous Serial Controller SSC TD SSC Transmit Data Output RD SSC Receive Data Input TK SSC Transmit Clock 1 0 RK SSC Receive Clock 1 0 TF SSC Transmit Frame Sync I O RF SSC Receive Frame Sync I O AMEL 7 6221HS ATARM 31 Jan 08 AMEL Table 3 1 Signal Description List Continued Active Signal Name Function Type Level Comments Timer Counter TCx TCLKx TC Channel x External Clock Input Input TIOAx TC Channel x I O Line A I O TIOBx TC Channel x I O Line B 1 0 Serial Peripheral Interface SPIx_ SPIx_MISO Master In Slave Out 1 0 SPIx_MOSI Master Out Slave In 1 0 SPIx_SPCK SPI Serial Clock I O SPIx_NPCSO SPI Peripheral Chip Select 0 I O Low SPIx_NPCS1 SPIx_NPCS3 SPI Peripheral Chip Select Output Low Two Wire Interface TWD Two wire Seria
24. an external 32 768 Hz crystal or the on chip RC oscillator Table 6 1 defines the states for OSCSEL signal Table 6 1 Slow Clock Selection OSCSEL Slow Clock Startup Time 0 Internal RC 240 us 1 External 32768 Hz 1200 ms The startup counter delay for the slow clock oscillator depends on the OSCSEL signal The 32 768 Hz startup delay is 1200 ms whereas it is 240 us for the internal RC oscillator refer to Table 6 1 The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the device 7 Processor and Architecture 7 1 ARM926EJ S Processor e RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration Two Instruction Sets ARM High performance 32 bit Instruction Set Thumb High Code Density 16 bit Instruction Set e DSP Instruction Extensions e 5 Stage Pipeline Architecture Instruction Fetch F 16 AT91SAM9260 mw 6221HS ATARM 31 Jan 08 mm nrn TO SAM9260 Instruction Decode D Execute E Data Memory M Register Write W e 8 Kbyte Data Cache 8 Kbyte Instruction Cache Virtually addressed 4 way Associative Cache Eight words per line Write through and Write back Operation Pseudo random or Round robin Replacement e Write Buffer Main Write Buffer with 16 word Data Buffer and 4 address Buffer DCache Write back Buffer with 8 word Entries and a Single Address Entry Software Control Drain e St
25. and 3 wire EEPROMs Serial peripherals such as ADCs DACs LCD Controllers CAN Controllers and Sensors External co processors e Master or slave serial peripheral bus interface 8 to 16 bit programmable data length per chip select Programmable phase and polarity per chip select Programmable transfer delays between consecutive transfers and between clock and data per chip select Programmable delay between consecutive transfers Selectable mode fault detection Very fast transfers supported Transfers with baud rates up to MCK The chip select line may be left active to speed up transfers on the same device 10 4 2 Two wire Interface e Master MultiMaster and Slave modes supported e General Call supported in Slave mode 10 4 3 USART e Programmable Baud Rate Generator e 5 to 9 bit full duplex synchronous or asynchronous serial communications 1 1 5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode Parity generation and error detection Framing error detection overrun error detection MSB or LSB first Optional break generation and detection By 8 or by 16 over sampling receiver frequency Hardware handshaking RTS CTS Optional modem signal management DTR DSR DCD RI Receiver time out and transmitter timeguard Optional Multi drop Mode with address generation and detection e RS485 with driver control signal e ISO7816 T 0 or T 1 Proto
26. andard ARM v4 and v5 Memory Management Unit MMU Access Permission for Sections Access Permission for large pages and small pages can be specified separately for each quarter of the page 16 embedded domains e Bus Interface Unit BIU Arbitrates and Schedules AHB Requests Separate Masters for both instruction and data access providing complete Matrix system flexibility Separate Address and Data Buses for both the 32 bit instruction interface and the 32 bit data interface On Address and Data Buses data can be 8 bit Bytes 16 bit Half words or 32 bit Words 7 2 Bus Matrix e 6 layer Matrix handling requests from 6 masters e Programmable Arbitration strategy Fixed priority Arbitration Round Robin Arbitration either with no default master last accessed default master or fixed default master e Burst Management Breaking with Slot Cycle Limit Support Undefined Burst Length Support e One Address Decoder provided per Master Three different slaves may be assigned to each decoded memory area one for internal boot one for external boot one after remap e Boot Mode Select Non volatile Boot Memory can be internal or external Selection is made by BMS pin sampled at reset AMEL 7 6221HS ATARM 31 Jan 08 AMEL e Remap Command Allows Remapping of an Internal SRAM in Place of the Boot Non Volatile Memory Allows Handling of Dynamic Exception Vectors 7 2 1 Matri
27. ator bypass feature Supports 3 to 20 MHz crystals e Embeds 2 PLLs PLLA outputs 80 to 240 MHz clock PLLB outputs 70 to 130 MHz clock Both integrate an input divider to increase output accuracy PLLB embeds its own filter 28 AT91SAM9260 mmm AT91SAM9260 Figure 9 2 Clock Generator Block Diagram OSC_SEL l Clock Generator On Chip RC OSC Slow Clock Oscillator Main Oscillator PLL and Divider A Slow Clock SLCK XIN32 XOUT32 XIN xouT PLLRCA l Main Clock MAINCK PLLA Clock PLLACK PLL and Divider B PLLB Clock PLLBCK Status 1 Control Power Management Controller 9 5 Power Management Controller e Provides the Processor Clock PCK the Master Clock MCK in particular to the Matrix and the memory interfaces the USB Device Clock UDPCK independent peripheral clocks typically at the frequency of MCK 2 programmable clock outputs PCK0 PCK1 Five flexible operating modes Normal Mode processor and peripherals running at a programmable frequency Idle Mode processor stopped waiting for an interrupt Slow Clock Mode processor and peripherals running at low frequency Standby Mode mix of Idle and Backup Mode peripheral running at low frequency processor stopped waiting for an interrupt Backup Mode Main Power Supplies off VDDBU powered by a battery AMEL 2 6221HS ATARM 31 Jan 08 AMEL Fi
28. ck Oscillator Output Output OSCSEL Slow Clock Oscillator Selection Input bn between OV and PLLRCA PLL A Filter Input PCKO PCK1 Programmable Clock Output Output Shutdown Wakeup Logic SHDN Shutdown Control Output a DO not tie WKUP Wake up Input Input eae DeIWESN OW and ICE and JTAG NTRST Test Reset Signal Input Low Pull up resistor TCK Test Clock Input No pull up resistor TDI Test Data In Input No pull up resistor TDO Test Data Out Output TMS Test Mode Select Input No pull up resistor JTAGSEL JTAG Selection Input a eS RTCK Return Test Clock Output AIMEL 6221HS ATARM 31 Jan 08 Ee AMEL Table 3 1 Signal Description List Continued Active Signal Name Function Type Level Comments Reset Test NRST Microcontroller Reset 1 0 Low Pull up resistor TST Test Mode Select Input ue sare ag BMS Boot Mode Select Input Debug Unit DBGU DRXD Debug Receive Data Input DTXD Debug Transmit Data Output Advanced Interrupt Controller AIC IRQO IRQ2 External Interrupt Inputs Input FIQ Fast Interrupt Input Input PIO Controller PIOA PIOB PIOC PAO PA31 Parallel IO Controller A O Pulled up input at reset PBO PB31 Parallel IO Controller B O Pulled up input at reset PCO PC31 Parallel IO Controller C I O Pulled up input at reset External Bus Interface EBI D0 D31 Data Bus I O Pulled up input at reset A0
29. cols for interfacing with smart cards NACK handling error counter with repetition and iteration limit e IrDA modulation and demodulation AMEL x 6221HS ATARM 31 Jan 08 AMEL Communication at up to 115 2 Kbps e Test Modes Remote Loopback Local Loopback Automatic Echo The USART contains features allowing management of the Modem Signals DTR DSR DCD and RI In the AT91SAM9260 only the USARTO implements these signals named DTRO DSRO DCDO and RIO The USART1 and USART2 do not implement all the modem signals Only RTS and CTS RTS1 and CTS1 RTS2 and CTS2 respectively are implemented in these USARTSs for other features Thus programming the USART1 USART2 or the USART3 in Modem Mode may lead to unpre dictable results In these USARTs the commands relating to the Modem Mode have no effect and the status bits relating the status of the modem signals are never activated 10 4 4 Serial Synchronous Controller e Provides serial synchronous communication links used in audio and telecom applications with CODECs in Master or Slave Modes IS TDM Buses Magnetic Card Reader etc e Contains an independent receiver and transmitter and a common clock divider e Offers a configurable frame sync and data length e Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal e Receiver and transmitter include a data signal a clock signal and a frame synch
30. d vwa feseydued jauueyo zz ebpug reseydued xue Jekel 9 2 NO POD PSN LP HIH So QM y WV S 1se4 sofa p WY HS 1se4 ayed AOSS9901d S PAIE6NHVY Jorejnw3 N30 ueos Arepunog pue uono S OVE SLYVSN vLHYSN eLHVSN lt LHVSN LLHYSN OLYVSN Ad LSHN 2HOIAAA naaaA dM NOHS gELNOX ENIX TASOSO LNOX NIX VOUT Id LA9d 04 9d axa axa OtI 0Oti Did 1 lonuoo ui ls s isl SAV 1S o HLS AT91SAM9260 mmm 6221HS ATARM 31 Jan 08 mm r v A T 9 1 SAM9260 3 Signal Description Table 3 1 Signal Description List Active Signal Name Function Type Level Comments Power Supplies VDDIOM EBI I O Lines Power Supply Power 1 65V to 1 95V or 3 0V to3 6V VDDIOPO Peripherals I O Lines Power Supply Power 3 0V to 3 6V VDDIOP1 Peripherals I O Lines Power Supply Power 1 65V to 3 6V VDDBU Backup I O Lines Power Supply Power 1 65V to 1 95V VDDANA Analog Power Supply Power 3 0V to 3 6V VDDPLL PLL Power Supply Power 1 65V to 1 95V VDDCORE Core Chip Power Supply Power 1 65V to 1 95V GND Ground Ground GNDPLL PLL and Oscillator Ground Ground GNDANA Analog Ground Ground GNDBU Backup Ground Ground Clocks Oscillators and PLLs XIN Main Oscillator Input Input XOUT Main Oscillator Output Output XIN32 Slow Clock Oscillator Input Input XOUT32 Slow Clo
31. eive Channel SSC Receive Channel AMEL i 6221HS ATARM 31 Jan 08 MCI Transmit Receive Channel 7 4 Debug and Test Features e ARM926 Real time In circuit Emulator Two real time Watchpoint Units Two Independent Registers Debug Control Register and Debug Status Register Test Access Port Accessible through JTAG Protocol Debug Communications Channel e Debug Unit Two pin UART Debug Communication Channel Interrupt Handling Chip ID Register e IEEE1149 1 JTAG Boundary scan on All Digital Pins 20 AT91SAM9260 mmm AT91SAM9260 8 Memories Figure 8 1 AT91SAM9260 Memory Mapping Address Memory Space Internal Memory Mapping Notes 1 Can be ROM EBI_NCSO or SRAM 00000 0000 depending on BMS and REMAP 0x0000 0000 Boot Memory 1 Internal Memories 256M Bytes 0x10 0000 ROM 0x1000 0000 0x10 8000 Reserved 0x20 0000 SRAMO 4K Bytes 0x20 1000 0x30 0000 SRAM1 4K Bytes 0x30 1000 0x50 0000 EBI UHP 16K Bytes Chip Select 2 256M Bytes 0x50 4000 e y 0x4000 0000 X EBI Reserved Chip Select 3 256M Bytes OxOFFF FFFF EBI Chip Select 0 256M Bytes 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 256M Bytes SDRAMC 0x2FFF FFFF 0x3000 0000 NANDFlash 0x4FFF FFFF 0x5000 0000 EBI Chip Select 4 Compact Flash 256M Bytes OxSFFF FFFF Sioro 0x6000 0000 EBI Peripheral Mapping Chip Select 5 256M Bytes Compact Flash 0xF000 0000 0x6FFF FFFF Slot 1 0x7000 0000 Sys
32. grammable Edge triggered or Level sensitive Internal Sources Programmable Positive Negative Edge triggered or High Low Level sensitive e Three External Sources plus the Fast Interrupt signal e 8 level Priority Controller Drives the Normal Interrupt of the processor Handles priority of the interrupt sources 1 to 31 Higher priority interrupts can be served during service of lower priority interrupt e Vectoring Optimizes Interrupt Service Routine Branch and Execution One 32 bit Vector Register per interrupt source Interrupt Vector Register reads the corresponding current Interrupt Vector e Protect Mode Easy debugging by preventing automatic operations when protect models are enabled e Fast Forcing Permits redirecting any normal interrupt source on the Fast Interrupt of the processor 9 11 Debug Unit e Composed of two functions Two pin UART Debug Communication Channel DCC support e Two pin UART Implemented features are 100 compatible with the standard Atmel USART Independent receiver and transmitter with a common programmable Baud Rate Generator Even Odd Mark or Space Parity Generation Parity Framing and Overrun Error Detection Automatic Echo Local Loopback and Remote Loopback Channel Modes Support for two PDC channels with connection to receiver and transmitter e Debug Communication Channel Support Offers visibility of and interrupt trigger from
33. gure 9 3 AT91SAM9260 Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller Idle Mode Prescaler 1 2 4 64 gt MCK Peripherals Clock Controller periph_clk ON OFF Programmable Clock Controller ON OFF Prescaler gt pck 1 2 4 64 USB Clock Controller ON OFF Divider gt UDPCK Pepa gt UHPCK 9 6 Periodic Interval Timer e Includes a 20 bit Periodic Counter with less than 1 us accuracy e Includes a 12 bit Interval Overlay Counter Real Time OS or Linux Windows CE compliant tick generator 9 7 Watchdog Timer e 16 bit key protected only once Programmable Counter e Windowed prevents the processor being in a dead lock on the watchdog access 9 8 Real time Timer Real time Timer 32 bit free running back up Counter Integrates a 16 bit programmable prescaler running on slow clock Alarm Register capable of generating a wake up of the system through the Shutdown Controller 9 9 General purpose Back up Registers e Four 32 bit backup general purpose registers 9 10 Advanced Interrupt Controller e Controls the interrupt lines nIRQ and nFIQ of the ARM Processor e Thirty two individually maskable and vectored interrupt sources Source 0 is reserved for the Fast Interrupt Input FIQ Source 1 is reserved for system peripherals PIT RTT PMC DBGU etc 30 AT91SAM9260 memmm mmn rn A T 9 1 SAM9260 Pro
34. igger Input AIMEL i 6221HS ATARM 31 Jan 08 T AMEL 4 Package and Pinout The AT91SAM9260 is available in two packages e 208 pin PQFP Green package 0 5mm pitch Figure 4 1 e 217 ball LFBGA Green package 0 8 mm ball pitch Figure 4 2 41 208 pin PQFP Package Outline Figure 4 1 shows the orientation of the 208 pin PQFP package A detailed mechanical description is given in the section AT91SAM9260 Mechanical Character istics of the product datasheet Figure 4 1 208 pin PQFP Package 156 105 157 104 208 10 AT91SAM9260 mu Tu 6221HS ATARM 31 Jan 08 mnr TO SAM9260 4 2 208 pin PQFP Pinout Table 4 1 Pinout for 208 pin PQFP Package Pin ignal Name Pin ignal Name Pin ignal Name Pin ignal Name 1 PA24 5 GND Hos TRAS 157 TT ADVREF O 2 PA25 54 DDM 106 D0 158 PC0 3 PA26 55 DDP 107 D1 159 PC1 4 PA27 56 PC13 108 D2 160 VDDANA 5 VDDIOPO 57 PC11 109 D3 161 PB10 6 GND 58 PC10 110 D4 162 PB11 7 PA28 59 PC14 111 D5 163 PB20 8 PA29 60 PC9 112 D6 164 PB21 9 PBO 61 PC8 113 GND 165 PB22 10 PB1 62 PC4 114 VDDIOM 166 PB23 11 PB2 63 PC6 115 SDCK 167 PB24 12 PB3 64 PC7 116 SDWE 168 PB25 13 VDDIOPO 65 VDDIOM 117 SDCKE 169 VDDIOP1 14 GND 66 GND 118 D7 170 GND 15 PB4 67 PC5 119 D8 171 PB26 16 PB5 68 NCS0 120 D9 172 PB27 17 PB6
35. ion e Compliance with USB V2 0 Full speed and Low speed Specification e Supports both Low Speed 1 5 Mbps and Full speed 12 Mbps devices e Root hub integrated with two downstream USB ports in the 217 LFBGA package e Two embedded USB transceivers e Supports power management e Operates as a master on the Matrix 10 4 8 USB Device Port e USB V2 0 full speed compliant 12 MBits per second e Embedded USB V2 0 full speed transceiver e Embedded 2 432 byte dual port RAM for endpoints e Suspend Resume logic e Ping pong mode two memory banks for isochronous and bulk endpoints e Six general purpose endpoints Endpoint 0 and 3 64 bytes no ping pong mode Endpoint 1 and 2 64 bytes ping pong mode Endpoint 4 and 5 512 bytes ping pong mode e Embedded pad pull up 10 4 9 Ethernet 10 100 MAC e Compatibility with IEEE Standard 802 3 e 10 and 100 MBits per second data throughput capability e Full and half duplex operations MII or RMII interface to the physical layer e Register Interface to address data status and control registers e DMA Interface operating as a master on the Memory Controller e Interrupt generation to signal receive and transmit completion e 28 byte transmit and 28 byte receive FIFOs e Automatic pad and CRC generation on transmitted frames e Address checking logic to recognize four 48 bit addresses e Support promiscuous mode where all valid frames are copied to memory AMEL 39 6221HS ATARM 31 Jan 08 AMEL e S
36. l Data 1 0 TWCK Two wire Serial Clock 1 0 USB Host Port HDPA USB Host Port A Data Analog HDMA USB Host Port A Data Analog HDPB USB Host Port B Data Analog HDMB USB Host Port B Data Analog USB Device Port DDM USB Device Port Data Analog DDP USB Device Port Data Analog Ethernet 10 100 ETXCK Transmit Clock or Reference Clock Input MII only REFCK in RMII ERXCK Receive Clock Input MII only ETXEN Transmit Enable Output ETX0 ETX3 Transmit Data Output ETXO ETX1 only in RMII ETXER Transmit Coding Error Output MII only ERXDV Receive Data Valid Input RXDV in MII CRSDV in RMII ERX0 ERX3 Receive Data Input ERXO ERX1 only in RMII ERXER Receive Error Input ECRS Carrier Sense and Data Valid Input MII only ECOL Collision Detect Input MII only EMDC Management Data Clock Output EMDIO Management Data Input Output I O EF100 Force 100Mbit sec Output High 8 AT91SAM9260 mw 6221HS ATARM 31 Jan 08 mm rr TO 1 SAM9260 Table 3 1 Signal Description List Continued Active Signal Name Function Type Level Comments Image Sensor Interface ISI_DO ISI_D11 Image Sensor Data Input ISI_LMCK Image Sensor Reference Clock Output ISILHSYNC Image Sensor Horizontal Synchro Input ISI_VSYNC Image Sensor Vertical Synchro Input ISI_PCK Image Sensor Data clock Input Analog to Digital Converter Digital pulled up inputs at ADO AD3 Analog Inputs Analog reset ADVREF Analog Positive Reference Analog ADTRG ADC Tr
37. mmable e Energy saving capabilities Self refresh power down and deep power down modes supported 24 AT91SAM9260 mar mm nrn TO SAM9260 e Error detection Refresh Error Interrupt e SDRAM Power up Initialization by software e CAS Latency of 1 2 and 3 supported e Auto Precharge Command not used 8 2 4 Error Corrected Code Controller e Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select e Single bit error correction and 2 bit Random detection e Automatic Hamming Code Calculation while writing ECC value available in a register e Automatic Hamming Code Calculation while reading Error Report including error flag correctable error flag and word address being detected erroneous Support 8 or 16 bit NAND Flash devices with 512 1024 2048 or 4096 bytes pages AMEL 25 6221HS ATARM 31 Jan 08 AMEL 9 System Controller 26 The System Controller is a set of peripherals that allows handling of key elements of the system such as power resets clocks time interrupts watchdog etc The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration The chip configuration registers configure EBI chip select assignment and voltage range for external memories The System Controllers peripherals are all mapped within the highest 16 Kbytes of address space between addresses OxFFFF E800 and 0xFFFF FFF
38. mmable Only Once Windowed 16 bit Counter Running at Slow Clock Real time Timer RTT 32 bit Free running Backup Counter Running at Slow Clock with 16 bit Prescaler One 4 channel 10 bit Analog to Digital Converter Three 32 bit Parallel Input Output Controllers PIOA PIOB PIOC 96 Programmable I O Lines Multiplexed with up to Two Peripheral I Os Input Change Interrupt Capability on Each I O Line Individually Programmable Open drain Pull up Resistor and Synchronous Output High current Drive I O Lines Up to 16 mA Each Peripheral DMA Controller Channels PDC One Two slot MultiMedia Card Interface MCI SDCard SDIO and MultiMediaCard Compliant Automatic Protocol Control and Fast Automatic Data Transfers with PDC One Synchronous Serial Controller SSC Independent Clock and Frame Sync Signals for Each Receiver and Transmitter PS Analog Interface Support Time Division Multiplex Support High speed Continuous Data Stream Capabilities with 32 bit Data Transfer Four Universal Synchronous Asynchronous Receiver Transmitters USART Individual Baud Rate Generator IrDA Infrared Modulation Demodulation Manchester Encoding Decoding Support for ISO7816 TO T1 Smart Card Hardware Handshaking RS485 Support Full Modem Signal Control on USARTO Two 2 wire UARTs Two Master Slave Serial Peripheral Interfaces SPI 8 to 16 bit Programmable Data Length Four External Peripheral Chip
39. nal Name C16 VDDIOPO J2 PC17 P11 PA1 U15 PA16 C17 SHDN J3 VDDIOM P12 PAS U16 PA18 D1 D9 J4 PC16 P13 PA7 U17 VDDIOPO D2 D2 J8 GND P14 PAQ D3 RAS J9 GND P15 PA26 D4 D0 J10 GND P16 PA25 5 Power Considerations 5 1 5 2 14 Power Supplies The AT91SAM9260 has several types of power supply pins e VDDCORE pins Power the core including the processor the embedded memories and the peripherals voltage ranges from 1 65V and 1 95V 1 8V nominal e VDDIOM pins Power the External Bus Interface I O lines voltage ranges between 1 65V and 1 95V 1 8V typical or between 3 0V and 3 6V 3 3V nominal The expected voltage range is selectable by software e VDDIOPO pins Power the Peripheral I O lines and the USB transceivers voltage ranges from 3 0V and 3 6V 3V or 3 3V nominal e VDDIOP1 pins Power the Peripherals I O lines involving the Image Sensor Interface voltage ranges from 1 65V and 3 6V 1 8V 2 5V 3V or 3 3V nominal e VDDBU pin Powers the Slow Clock oscillator and a part of the System Controller voltage ranges from 1 65V to 1 95V 1 8V nominal e VDDPLL pin Powers the Main Oscillator and PLL cells voltage ranges from 1 65V and 1 95V 1 8V nominal e VDDANA pin Powers the Analog to Digital Converter voltage ranges from 3 0V and 3 6V 3 3V nominal The power supplies VDDIOM VDDIOPO and VDDIOP1 are identified in the pinout table and the multiplexing tables These supplies enable
40. nal SRAM 4 KBytes X X X X 6221HS ATARM 31 Jan 08 mm nrn TO SAM9260 Table 7 3 AT91SAM9260 Masters to Slaves Access Internal ROM X X X 2 UHP User Interface X 3 External Bus Interface X X X X X 4 Internal Peripherals X 7 3 Peripheral DMA Controller e Acting as one Matrix Master e Allows data transfers from to peripheral to from any memory space without any intervention of the processor e Next Pointer Support forbids strong real time constraints on buffer management e Twenty two channels Two for each USART Two for the Debug Unit Two for each Serial Synchronous Controller Two for each Serial Peripheral Interface One for Multimedia Card Interface One for Analog to Digital Converter The Peripheral DMA Controller handles transfer requests from the channel according to the fol lowing priorities Low to High priorities DBGU Transmit Channel USART5 Transmit Channel USART4 Transmit Channel USART3 Transmit Channel USART2 Transmit Channel USART1 Transmit Channel USARTO Transmit Channel SPI1 Transmit Channel SPIO Transmit Channel SSC Transmit Channel DBGU Receive Channel USART5 Receive Channel USART4 Receive Channel USARTS Receive Channel USART2 Receive Channel USART1 Receive Channel USARTO Receive Channel ADC Receive Channel SPI1 Receive Channel SPIO Rec
41. nds on embedded SRAM size e Automatic detection of valid application e Bootloader on a non volatile memory SPI DataFlash connected on NPCSO and NPCS1 of the SPIO 8 bit and or 16 bit NANDFlash e SAM BA Boot in case no valid program is detected in external NVM supporting Serial communication on a DBGU USB Device Port 8 1 1 2 BMS 0 Boot on External Memory Boot on slow clock On chip RC or 32 768 Hz e Boot with the default configuration for the Static Memory Controller byte select mode 16 bit data bus Read Write controlled by Chip Select allows boot on 16 bit non volatile memory The customer programmed software must perform a complete configuration To speed up the boot sequence when booting at 32 kHz EBI CSO BMS 0 the user must take the following steps 1 Program the PMC main oscillator enable or bypass mode 2 Program and start the PLL 3 Reprogram the SMC setup cycle hold mode timings registers for CSO to adapt them to the new clock 4 Switch the main clock to the new value 8 2 External Memories The external memories are accessed through the External Bus Interface Each Chip Select line has a 256 Mbyte memory area assigned Refer to the memory map in Figure 8 1 on page 21 8 2 1 External Bus Interface e Integrates three External Memory Controllers Static Memory Controller SDRAM Controller AMEL 23 6221HS ATARM 31 Jan 08 ECC Controller e Additional logic for NAN
42. o 126 D 31 20 BASIC 1 228 BASIC Di 28 00 BASIC 1 102 BASIC E 3 20 sasie 1 228 BASIC E1 28 00 BASIC 1 102 BASIC oa o oo5 o o12 8 REF B REF Qs REF 8 REF c 0 11 0 15 l 0 73 0 88 1 03 0 23 0 004 0 006 0 009 0 035 0 041 SEATING PLANE 1 60 REF 063 REF 1 004 TOLERANCES OF FORM AND POSITION aaa 0 25 0 010 0 20 0 008 i nan ej 4 x Sa SAGE PLANE J Table 11 5 Device and 208 lead PQFP Package Maximum Weight 5 5 g Table 11 6 208 lead PQFP Package Characteristics Moisture Sensitivity Level 3 Table 11 7 Package Reference JEDEC Drawing Reference MS 022 JESD97 Classification e3 6221HS ATARM 31 Jan 08 mman A T 9 1 SAM9260 11 2 Soldering Profile Table 11 8 gives the recommended soldering profile from J STD 20 Table 11 8 Soldering Profile BGA217 Green Profile Feature PQFP208 Green Package Package Average Ramp up Rate 217 C to Peak 3 C sec max 3 C sec max Preheat Temperature 175 C 25 C 180 sec max 180 sec max Temperature Maintained Above 217 C 60 sec to 150 sec 60 sec to 150 sec Time within 5 C of Actual Peak Temperature 20 sec to 40 sec 20 sec to 40 sec Peak Temperature Range 260 0 C 260 0 C Ramp down Rate 6 C sec max 6 C sec max Time 25 C to Peak Temperature 8 min max 8 min max Note Itis recommended to apply a solde
43. on List on page 5 added new voltage information for 2979 OSCSEL and TST pins In Section 6 3 Reset Pins on page 15 new information on NRST and NRTST pins 3003 Corrected ADC features in Section 10 4 11 Analog to Digital Converter on 2023 page 40 Power consumption figures updated with current values in Section 5 2 Power Consumption on page 14 221B 2843 gt Change to signal name for pin 47 in Section 4 1 Pinout for 208 pin PQFP Package on page 11 6221AS First issue 6221HS ATARM 31 Jan 08
44. quire the pin to be driven as soon as the reset is released Note that the pull up resistor is also enabled in this case AMEL 33 6221HS ATARM 31 Jan 08 AMEL 10 3 1 PIO Controller A Multiplexing Table 10 2 Multiplexing on PIO Controller A PIO Controller A Application Usage O Line Peripheral A Peripheral B Comments Reset State Power Supply Function Comments PAO SPIO_MISO MCDBO O VDDIOPO PA1 SPIO_MOSI MCCDB 1 0 VDDIOPO PA2 SPIO_SPCK 1 0 VDDIOPO PA3 SPIO_NPCSO MCDB3 1 0 VDDIOPO PA4 RTS2 MCDB2 1 0 VDDIOPO PA5 CTS2 MCDB1 1 0 VDDIOPO PA6 MCDA0 1 0 VDDIOPO PA7 MCCDA O VDDIOPO PA8 MCCK 1 0 VDDIOPO PAQ MCDA1 1 0 VDDIOPO PA10 MCDA2 ETX2 1 0 VDDIOPO PA11 MCDA3 ETX3 1 0 VDDIOPO PA12 ETXO 1 0 VDDIOPO PA13 ETX1 1 0 VDDIOPO PA14 ERX0 1 0 VDDIOPO PA15 ERX1 1 0 VDDIOPO PA16 ETXEN 1 0 VDDIOPO PA17 ERXDV 1 0 VDDIOPO PA18 ERXER 1 0 VDDIOPO PA19 ETXCK 1 0 VDDIOPO PA20 EMDC 1 0 VDDIOPO PA21 EMDIO 1 0 VDDIOPO PA22 ADTRG ETXER 1 0 VDDIOPO PA23 TWD ETX2 1 0 VDDIOPO PA24 TWCK ETX3 1 0 VDDIOPO PA25 TCLKO ERX2 1 0 VDDIOPO PA26 TIOAO ERX3 1 0 VDDIOPO PA27 TIOA1 ERXCK O VDDIOPO PA28 TIOA2 ECRS 1 0 VDDIOPO PA29 SCK1 ECOL 1 0 VDDIOPO PA3O SCK2 RXD4 V 0 VDDIOPO PA31 SCKO TXD4 O VDDIOPO Note 1 Not available in the 208 lead PQFP package 34 AT91SAM9260 mmm 6221HS ATARM 31 Jan 08 mm ssnrrss A T 9 1 SAM9260
45. ring temperature higher than 250 C A maximum of three reflow passes is allowed per component AIMEL 6221HS ATARM 31 Jan 08 ey AMEL 12 AT91SAM9260 Ordering Information Table 12 1 AT91SAM9260 Ordering Information Ordering Code Package Package Type AT91SAM9260 QU PQFP208 Green AT91SAM9260 CU BGA217 Green Temperature Operating Range Industrial 40 C to 85 C 44 AT91SAM9260 mus 6221HS ATARM 31 Jan 08 mnr TO SAM9260 13 Revision History Table 13 1 Revision History current version appears first Change Request Revision Comments Ref 6221HS Power Considerations in Section 5 1 Power Supplies VDDCORE and 5229 VDDBU startup voltage restraints removed 6221GS Updated all references to 217 ball LFBGA to Green package Review In Section 5 1 Power Supplies on page 14 VDDCORE and VDDBU added information on supply voltage during startup Review In Section 6 5 I O Line Drive Levels on page 16 added information on PC4 to PC31 Review In Section 6 7 Slow Clock Selection on page 16 corrected startup delay for internal RC oscillator Review In Section 10 4 6 Multimedia Card Interface on page 38 corrected specification 4944 version compatibility In Section 8 1 1 Boot Strategies on page 22 removed sentence When REMAP 1 ae j 5026 BMS is ignored Changed divider value for Master Clock Controller in Figure 9 3
46. ronization signal 10 4 5 Timer Counter Two blocks of three 16 bit Timer Counter channels e Each channel can be individually programmed to perfom a wide range of functions including Frequency Measurement Event Counting Interval Measurement Pulse Generation Delay Timing Pulse Width Modulation Up down Capabilities e Each channel is user configurable and contains Three external clock inputs Five internal clock inputs Two multi purpose input output signals e Each block contains two global registers that act on all three TC Channels Note TC Block 0 TCO TC1 TC2 and TC Block 1 TC3 TC4 TC5 have identical user interfaces See Figure 8 1 AT91SAM9260 Memory Mapping on page 21 for TC Block 0 and TC Block 1 base addresses 10 4 6 Multimedia Card Interface e One double channel MultiMedia Card Interface e Compatibility with MultiMedia Card Specification Version 3 11 38 AT91SAM9260 w mr n nn A T 9 1 SAM9260 e Compatibility with SD Memory Card Specification Version 1 1 e Compatibility with SDIO Specification Version V1 0 e Card clock rate up to Master Clock divided by 2 e Embedded power management to slow down clock rate when not used e MCI has two slots each supporting One slot for one MultiMediaCard bus up to 30 cards or One SD Memory Card e Support for stream block and multi block data read and write 10 4 7 USB Host Port e Compliance with Open HCI Rev 1 0 Specificat
47. ry Mapping REMAP 0 REMAP 1 Address BMS 1 BMS 0 0x0000 0000 ROM EBI_NCS0 SRAMO 4K The system always boots at address 0x0 To ensure a maximum number of possibilities for boot the memory layout can be configured with two parameters REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development This is done by software once the system has booted Refer to the Bus Matrix Section for more details When REMAP 0 BMS allows the user to lay out to 0x0 at his convenience the ROM or an external memory This is done via hardware at reset Note Memory blocks not affected by these parameters can always be seen at their specified base addresses See the complete memory map presented in Figure 8 1 on page 21 22 AT91SAM9260 mmm mm rrr A T 9 1 SAM9260 The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose If BMS is detected at 1 the boot memory is the embedded ROM If BMS is detected at 0 the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface 8 1 1 1 BMS 1 Boot on Embedded ROM The system boots using the Boot Program Boot on slow clock On chip RC or 32 768 Hz e Auto baudrate detection e Downloads and runs an application from external storage media into internal SRAM e Downloaded code size depe
48. tem Controller Mapping Reserved OxFFFA 0000 0xFFFF C000 EBI TCO TC1 TC2 16K Bytes Chip Select 6 256M Bytes OxFFFA 4000 Reserved 0x8000 0000 OxFFFA 8000 ECC 512 Bytes Fae 256M Bytes 16K Bytes OxFFFF EA00 Chip Select 7 OxFFFA C000 5 9000 0000 one Sa 0x9000 0000 XEEEB 6000 OxFFFF EC00 USARTO 16K Bytes SMC 512 Bytes USART 16KB Mam 0xFFFB 8000 vies OxFFFF EF10 512 Bytes oxFFFF poon cere USART2 16K Bytes i OxFFFB C000 AIC 512 Bytes a HEE F200 OxFFFC 0000 512 Byt ae on OxFFFC 4000 OxFFFF F400 EMAC 16K Bytes 512 Bytes OxFFFC 8000 OxFFFF F600 Undefined 1 518M Bytes SPIO 16K B so i PIOB ne OxFFFC C000 OxFFFF F800 SPH 16K Bytes PIOC 512 bytes OxFFFD 0000 OxFFFF FA00 USART3 16K Bytes 0xFFFD 4000 neee 16K Bytes OxFFFF FCOO USART4 256 Bytes 16K Bytes OxFFFF FD00 USARTS RSTC 16 Bytes OxFFFD C000 OxFFFF FD10 16 Bytes TC3 TC4 TCS 16K Bytes OXFEFE FD20 SHDWC RTTC 16 Bytes OxFFRE 0000 OxFFFF FD30 ADC 16K Bytes PITC 16 Bytes OxEFFF FFFF OxFFFF FD40 0xF000 0000 OxFFFE 4000 WDTC 16 Bytes Reserved OxFFFF FD50 GPBR 16 Bytes Internal Peripherals 256M Bytes OxFFFF C000 aa ge OxFFFF FD60 SYSC 16K Bytes Reserved OxFFFF FFFF OXFFFF FFFF es OxFFFFFFFF Abort ue O OxFFFD 8000 AIMEL 6221HS ATARM 31 Jan 08 ay AMEL A first level of address decoding is performed by the Bus Matrix i e the implementation of the Advanced High Performance Bus AHB for its
49. the Interrupt signals IRQO to IRQ2 use a dedicated Peripheral ID However there is no clock control associated with these peripheral IDs 10 3 Peripheral Signal Multiplexing on I O Lines The AT91SAM9260 features 3 PIO controllers PIOA PIOB PIOC that multiplex the I O lines of the peripheral set Each PIO Controller controls up to 32 lines Each line can be assigned to one of two peripheral functions A or B Table 10 2 on page 34 Table 10 3 on page 35 and Table 10 4 on page 36 define how the I O lines of the peripherals A and B are multiplexed on the PIO Controllers The two columns Function and Comments have been inserted in this table for the user s own comments they may be used to track how pins are defined in an application Note that some peripheral functions which are output only might be duplicated within both tables The column Reset State indicates whether the PIO Line resets in I O mode or in peripheral mode If I O appears the PIO Line resets in input with the pull up enabled so that the device is maintained in a static state as soon as the reset is released As a result the bit corresponding to the PIO Line in the register PIO_PSR Peripheral Status Register resets low If a signal name appears in the Reset State column the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high This is the case of pins controlling memories in particular the address lines which re
50. upport physical layer management through MDIO interface 10 4 10 Image Sensor Interface e ITU R BT 601 656 8 bit mode external interface support Support for ITU R BT 656 4 SAV and EAV synchronization e Vertical and horizontal resolutions up to 2048 x 2048 e Preview Path up to 640 480 e Support for packed data formatting for YCbCr 4 2 2 formats e Preview scaler to generate smaller size image Programmable frame capture rate 10 4 11 Analog to Digital Converter e 4 channel ADC e 10 bit 312K samples sec Successive Approximation Register ADC e 2 2 LSB Integral Non Linearity 1 1 LSB Differential Non Linearity e Individual enable and disable of each channel e External voltage reference for better accuracy on low voltage inputs e Multiple trigger source Hardware or software trigger External trigger pin Timer Counter 0 to 2 outputs TIOAO to TIOA2 trigger e Sleep Mode and conversion sequencer Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels e Four analog inputs shared with digital signals 40 AT91SAM9260 mmm AT91SAM9260 11 AT91SAM9260 Mechanical Characteristics 11 1 Package Drawings Figure 11 1 217 ball LFBGA Package Drawing BOTTOM VIEW TOP VIEW 20 15 lclals on corner PIN 1 CORNER 00 35 0 45 217X 5 50
51. x Masters The Bus Matrix of the AT91SAM9260 manages six Masters which means that each master can perform an access concurrently with others according the slave it accesses is available Each Master has its own decoder that can be defined specifically for each master In order to simplify the addressing all the masters have the same decodings Table 7 1 List of Bus Matrix Masters Master 0 ARM926 Instruction Master 1 ARM926 Data Master 2 PDC Master 3 USB Host DMA Master 4 ISI Controller Master 5 Ethernet MAC 7 2 2 Matrix Slaves Each Slave has its own arbiter thus allowing a different arbitration per Slave to be programmed Table 7 2 List of Bus Matrix Slaves Slave 0 Internal SRAMO 4 KBytes Slave 1 Internal SRAM1 4 KBytes Internal ROM Slave 2 USB Host User Interface Slave 3 External Bus Interface Slave 4 Internal Peripherals 7 2 3 Master to Slave Access All the Masters can normally access all the Slaves However some paths do not make sense such as allowing access from the Ethernet MAC to the Internal Peripherals Thus these paths are forbidden or simply not wired and shown in the following table Table 7 3 AT91SAM9260 Masters to Slaves Access Master 0 amp 1 2 3 4 5 ARM926 Peripheral Slave Instruction amp DMA USB Host ISI Ethernet Controller Controller MAC Data Controller Internal SRAM 4 KBytes X X X x Inter
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ATMEL AT91SAM9260 handbook