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ATMEL Atmel AVR micro controller ATxmega64A1 English handbook

1. 8067 05 08 Symbol Parameter Condition Min Typ Max Units Voc 3 3V 0 5 0 3 Vit Input Low Voltage 2 7V 0 5 0 3 V Voc 1 8 0 5 0 3 Voc 3 3 0 7 0 5 Input High Voltage 2 7 0 7 0 5 V 1 8 0 7 0 5 Voc 0 2 20 Output Sink Current Voc 2 7V 0 2 17 mA Vec 1 8 Vg 0 2 10 mA Voc 0 8 10 mA lou Output Source Current Voc 2 7V 0 8Voc 7 mA Voc 1 8V 0 8 3 mA 52 Curent Rest Reset Pull up Resistor 20 Pin Pull up Resistor 20 AMEL 40 C to 85 C Vec 1 6V to 3 6V unless otherwise noted Symbol Parameter Condition Min Typ Max Units 1 MHz Voc 1 8V 350 Ext Clock Voc 2 7V 650 PRR set 2 MHz Internal RC 720 Active All PRR Set Ext Clock 670 32 MHz Internal RC TBD Voc 2 7 32 2 Internal RC TBD Voc 3 3 Power Supply Current 1 MHz Voc 1 8V 130 Ext Clock Voc 2 7V 220 All PRR set 2 2 Internal RC 310 32 MHz Internal RC TBD Voc 2 7 32 Voc 3 3V Functions Disabled 1 8V 0 1 Powe
2. 34 18 1 Em 34 192 34 19 TWI Two Wire Interface 35 19 1 Features 35 2 35 20 SPI Serial Peripheral Interface 36 20 1 BIER IEEE IT 36 202 SII RENS 36 21 USART sse 37 21 1 37 212 200440040000000 sides dass 37 22 IRCOM Communication Module 38 22 1 Feature S 38 222 38 23 Engine aare ERR 39 23 1 39 232 39 24 ADC 12 bit Analog to Digital Converter 40 24 1 BINE NET T E ETT 40 242 rc tn 40 25 DAC 12 bit Digital to Analog Converter 42 25 1
3. 22 12 3 Reset Sources 22 124 WDT Watchdog Timer 23 Programmable Multi level Interrupt Controller 24 13 1 TEES 24 IK ZEB ODOREM 24 13 3 IntetT pt VOCO rete ees Exin 24 26 14 1 RDUM 26 14 02 26 14 3 WVO CONTIQUIATION cis ente tpe den ere br ec 26 144 Input Sensilig 29 14 5 Port Interrupt ei edie 29 14 6 Alternate Port FUunGllOns 29 16 bit 30 15 1 a 30 152 040000000 00000 30 AWEX Advanced Waveform Extension 32 16 1 RICE DENT 32 16 2 32 Hi Res High Resolution Extension 33 17 1 Features TERRE ED 33 UESTRE ERE 33 RTC 16 bit Real Time Counter
4. SDA PE1 36 SYNC OCOB SCL PE2 37 SYNC ASYNC OCOC OCOB RXDO 38 SYNC OCOD OCOB TXDO 4 39 5 OCOC OC1A 55 5 40 SYNC OCOC XCK1 MOSI PE6 41 SYNC OCOD RXD1 MISO 42 SYNC OCOD TXD1 SCK CLKOUT EVOUT 51 8067 05 0 8 AMEL Table 29 6 Port F Alternate functions PORT F PIN INTERRUPT TCFO TCF1 USARTFO USARTF1 SPIF TWIF GND 43 vcc 44 PFO 45 SYNC SDA PF1 46 SYNC OCOB SCL PF2 47 SYNC ASYNC OCOC RXDO 48 SYNC OCOD TXDO 4 49 SYNC OC1A SS PF5 50 SYNC XCK1 MOSI PF6 51 SYNC RXD1 MISO PF7 52 SYNC TXD1 SCK Table 29 7 Port H Alternate functions PORTH PIN INTERRUPT SDRAM 3P SRAM ALE1 SRAM ALE12 LPC3 ALE1 LPC2 ALE1 LPC2 ALE12 GND 53 vcc 54 PHO 55 SYNC WE WE WE WE PH1 56 SYNC CAS RE RE RE RE RE PH2 57 SYNC ASYNC RAS ALET ALET ALET ALET ALET PH3 58 SYNC DOM ALE2 ALE2 4 59 SYNC BAO 50 16 50 50 16 50 50 16 5 60 SYNC BA1 CS1 A17 CS1 CS1 A17 CS1 CS1 A17 PH6 61 SYNC CKE CS2 A18 CS2 CS2 A18 CS2 CS2 A18 62 5 CS3 A19 CS3 CS3 A19 53 CS3 A19 Table 29 8 Port J Alternate functions PORT J PIN INTERRUPT SDRAM 3P SRAM ALE1 SRAM ALE12 LPC3 ALE1 LPC2 ALE1 LPC2 ALE12 GND 63 vcc 64 PJO 65 SYNC DO DO DO D0 AO D0 AO D0 A0 A8 PJ1 66 S
5. 9 7 3 In System Programmable Flash Program Memory 9 7 4 Data MENON cd 10 7 5 Signature ROWS tei eee a 13 7 6 Flash and EEPROM Page 14 8 DMAC Direct Memory Access Controller 15 8 1 gu qc 15 8 2 eu M case 15 9 Event 16 91 16 9 2 u u 16 10 System Clock and Clock options 18 10 1 5 18 10 2 OWVGIVIBW iei nebat eui 18 8067 05 08 11 12 13 14 15 16 17 18 8067 05 08 10 3 5 19 Power Management Sleep Modes 21 11 1 TE 21 11 2 Overview 2 21 11 3 Sleep Modes cec 21 System Control and Reset 22 12 1 Features 22 12 2 AVR
6. 56 gt 8067 05 08 Mnemonics Operands Description Operation Flags Clocks CALL k call Subroutine lt None 3 40 RET Subroutine Return lt STACK None 4150 Interrupt Return PC lt STACK 4150 5 Compare Skip if Equal lt 20 3 1 2 8 CP Rd Rr Compare Rd Rr Z C N V S H 1 CPC Rd Rr Compare with Carry Rd Rr C Z C N V S H 1 Compare with Immediate Rd K Z C N V S H 1 SBRC Rr b Skip if Bit in Register Cleared if 0 lt 2 1 2 3 SBRS Rr b Skip if Bit in Register Set if 1 lt 2 1 2 3 SBIC b Skip if Bit in Register Cleared if O Ab 0 lt PC 2or3 None 2 3 4 SBIS b Skip if Bit in Register Set If VO A b 1 lt PC 2or3 None 2 3 4 BRBS Branch if Status Set if SREG s 1 thenPC lt 1 None 1 2 BRBC Branch if Status Cleared if SREG s 0 thenPC lt PC k 1 None 1 2 BREQ k Branch if Equal if Z 1 thenPC lt PC k 1 None 1 2 BRNE k Branch if Not Equal if Z 0 thenPC lt PC k 1 None 1 2 BRCS k Branch if Carry Set if C 1 thenPC lt PC k 1 None 172 Branch if Carry Cleared if C 0 then PC 1 1 2 BRSH k Branch if Same or Higher if
7. PB4 9 Bower TEMP RTC 2 5 0 Control FLASH eL 6 1 AVR v 7 2 CPU RAM GND 3 2 GND 4 pus E PROM 7 5 is PCI 6 Interrupt Controlle r 5 5 Watchdog d 2 7 Event System ctrl 8 4 5 rus PC5 EVENT ROUTING NETWORK PC6 MEC GND 5 GND VCC PF7 PDO PF6 Note For full details on pinout and pin functions refer to Pinout and Pin Functions on page 48 AMEL 2 8067 05 08 1 Figure 2 2 CBGA pinout Top view Bottom view 1234 5 6 7 10 10987654321 OO D E H J Table 2 1 CBGA pinout 1 2 3 4 5 6 7 8 9 10 A PKO VCC GND PJ3 GND VCC PH1 GND VCC PF7 B PK3 2 4 2 PF6 PF5 VCC PK5 PK4 PJ5 5 2 VCC D GND PK6 PK7 PJ6 PJ1 PH6 PFO PF1 PF4 GND 22 2 7 PJ2 4 Qm i ps 2 2 1 VCC G GND PA1 PA4 PB3 PB4 PC1 PC6 PD7 PD6 GND H AVCC PA2 PA5 PB2 PB5 PCO PC5 PD5 PD4 PD3 J PAO PA3 PBO PB1 PB6 PC3 PC4 PC7 PD2 PD1 K PA6 PA7 GND AVCC PB7 VCC GND VCC GND PDO AMEL 8067 05 08 3 8067 05 08 XMEGA A1 is
8. 8 90 9 00 9 10 7 10 7 20 7 30 7 10 7 20 7 30 0 35 0 40 0 45 0 80 TYP 2225 Orchard Parkway 10 100 ball 9 x 9 x 1 2 mm Pitch 0 80 mm ATE PITE ARE San Jose CA 95131 8067 05 08 Chip Array BGA Package AMEL 5 25 06 DRAWING NO 61 33 Electrical Characteristics 33 1 Absolute Maximum Ratings Storage Temperature 65 to 150 Voltage on any Pin with respect to Ground 0 5V to 0 5 Operating 55 C to 125 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Maximum Operating Voltage 3 6V DC Current per Pin 20 0 mA DC Current GND 200 0 mA 33 2 DC Characteristics 40 C to 85 C Vec 1 6V to 3 6V unless otherwise noted
9. 0 004 TWIF INT base Two Wire Interface on Port F INT base 0x0D8 Timer Counter 0 on F Interrupt base 0 0 4 TCF1 INT base Timer Counter 1 on port F Interrupt base OxOEC SPIF INT vector SPI ion port F Interrupt base OxOEE USARTFO INT base USART 0 on port Interrupt base OxOF4 USARTF1 INT base USART 1 on port F Interrupt base 8067 05 08 AMEL 25 14 14 4 Features Selectable input and output configuration for each pin individually Flexible pin configuration through dedicated Pin Configuration Register Synchronous and or asynchronous input sensing with port interrupts and events Sense both edges Sense rising edges Sense falling edges Sense low level Asynchronous wake up from all input sensing configurations Two port interrupts with flexible pin masking Highly configurable output driver and pull settings Totem pole Pull up down Wired AND Wired OR Bus keeper inverted I O Optional Slew rate control Configuration of multiple pins in a single operation Read Modify Write RMW support Toggle clear set registers for Output and Direction registers Clock output on port pin Event Channel 7 output on port pin Mapping of port registers virtual ports into bit accessible memory space 14 2 Overview The A1 devices have flexible General Purpose Ports A port consists of up to 8 pins ranging from pin O t
10. ASR Rd Arithmetic Shift Right lt 1 0 6 Z C N V 1 SWAP Rd Swap Nibbles 3 0 Rdq 7 4 None 1 BSET 5 Flag Set SREG s 1 SREG s 1 BCLR 5 SREG s lt 0 SREG s 1 58 Set Bit in Register VO A b 1 1 Clear Bit in I O Register O A b lt 0 None 1 BST Rr b Bit Store from Register to T lt Rr b T 1 BLD b Bit load from T to Register Rd b T None 1 SEC Set Carry C lt 1 1 CLC Clear Carry e 0 1 Set Negative Flag N e 1 N 1 CLN Clear Negative Flag N e 0 N 1 SEZ Set Zero Flag Z 1 Z 1 CLZ Clear Zero Flag 2 lt 0 2 1 Global Interrupt Enable e 1 1 Global Interrupt Disable 1 5 5 Set Signed Test 5 1 S 1 CLS Clear Signed Test Flag 5 e 0 5 1 Set Two s Complement Overflow V e 1 V 1 CLV Clear Two s Complement Overflow e 0 V 1 SET Set T in SREG T 1 1 CLT Clear T in SREG T 0 1 Set Carry SREG H lt 1 1 Clear Half Carry in SREG H lt 0 1 Control Instructions BREAK Break See specific descr for BREAK None 1 NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep None 1 WDR Watchdog Reset see specific descr for WDR None 1 8067 05 08 Notes 1 for accesses the external RAM interface 2 One extra cycle must be added when accessing Internal SRAM AMEL Cycle times for Data memory accesses
11. 4 2K 4K 32 1 6 3 6V PR ATxmega384A1 AU 384K 4 32K 32 1 6 3 6V ATxmega256A1 CU 256K 4 16 32 1 6 3 6 ATxmega192A1 CU 192K 8K 2K 16K 32 1 6 3 6V 100C1 ATxmega128A1 CU 128 8K 2K 8K 32 1 6 3 6V ATxmega64A1 CU 64K 4 2K 4K 32 1 6 3 6V Notes 1 This device can also be supplied in wafer form Please contact your local Atmel sales office for detailed ordering information 2 Pb free packaging complies to the European Directive for Restriction of Hazardous Substances RoHS directive Also Halide free and fully Green 3 For packaging information see Packaging information on page 60 Package Type 100A 100 lead 14 x 14 x 1 0 mm 0 5 mm Lead Pitch Thin Profile Plastic Quad Flat Package TQFP 100C1 100 ball 9 x 9 x 1 2 mm Body Ball Pitch 0 88 mm Chip Ball Grid Array CBGA 2 Pinout Block Diagram Figure 2 1 Block diagram and TQFP pinout 355550858092 SNR 6 1 7 2 GND 3 GND AVCC 4 DATABU 5 pJ7 PBO 5 PJ6 PB1 6 OSC CLK 5 2 7 4 8
12. 42 252 60 42 26 AC Analog Comparator 43 26 1 Features MEIST eee 43 262 JOVerVIeW gt tre deed 43 26 9 Input Selection 45 26 4 Window Function 45 27 DeDUg aad d D GRADO 46 27 1 Features NER EN TERT 46 MEER MISERUNT 46 28 Program and Debug Interfaces 47 28 1 MINIME 47 28 2 47 283 JTAG interface 28 47 AMEL iii 8067 05 08 29 30 31 32 33 34 35 36 8067 05 08 28 4 PDI Program and Debug Interface 47 Pinout and Pin Functions 48 29 1 Alternate Pin Function Description 48 29 2 Alternate Pin Functions 50 Peripheral Module Address Map 54 Instruction Set Summary NK ev Ux d R
13. 8067 05 08 14 3 5 8067 05 08 Figure 14 4 configuration Totem pole with bus keeper 4 a OUTn lt Others Figure 14 5 Output configuration Wired OR with optional pull down OUTn gt Figure 14 6 configuration Wired AND with optional pull up AMEL XMEGA A1 28 14 4 Input sensing Sense both edges Sense rising edges Sense falling edges Sense low level Input sensing is synchronous or asynchronous depending on the enabled clock for the ports and the configuration is shown in Figure 14 7 on page 29 Figure 14 7 Input sensing system overview When pin is configured with inverted the pin value is inverted before the input sensing 14 5 Port Interrupt Each ports have two interrupts with seperate priority and interrupt vector All pins on the port can be individually selected as source for each of the interrupts The interrupts are then triggered according to the input sense configuration for each pin configured as source for the interrupt 14 6 Alternate Port Functions In addition to the input output functions on all port pins most pins have alternate functions This means that other modules or peripherals connected to the port can use the port pins for their functions such as communication or pulse width modulation Pinout and Pin Functions on page 48
14. Time Counter 18 1 Features 16 bit Timer Flexible Tick resolution ranging from 1 Hz to 32 768 kHz One Compare register One Period register Clear timer on Overflow or Compare Match Overflow or Compare Match event and interrupt generation 18 2 Overview The XMEGA includes a 16 bit Real time Counter RTC The can be clocked from accurate 32 768 kHz Crystal Oscillator the 32 768 kHz Calibrated Internal Oscillator or from the 32 kHz Ultra Low Power Internal Oscillator The RTC includes both a Period and a Compare register For details see Figure 18 1 A wide range of Resolution and Time out periods can be configured using the RTC With a max imum resolution of 30 5 us time out periods range up to 2000 seconds With a resolution of 1 second the maximum time out period is over 18 hours 65536 seconds Overflow Figure 18 1 Real Time Counter overview 32 kHz 10 bit orescaler AMEL 8067 05 08 19 TWI Two Wire Interface 19 1 Features 19 2 Overview 8067 05 08 Four Identical TWI peripherals Simple yet Powerful and Flexible Communication Interface Both Master and Slave Operation Supported Device can Operate as Transmitter or Receiver 7 bit Address Space Allows up to 128 Different Slave Addresses Multi master Arbitration Support Up to 400 kHz Data Transfer Speed Slew rate Limited Output Drivers Noise Suppression Circuitry Rejects Spikes on Bus L
15. also be used as an address pointer for look up tables in Flash program memory 64 ALU Arithmetic Logic Unit 6 5 Program Flow 8067 05 08 The high performance Arithmetic Logic Unit ALU supports arithmetic and logic operations between registers or between a constant and a register Single register operations can also be executed Within a single clock cycle arithmetic operations between general purpose registers or between a register and an immediate are executed After an arithmetic or logic operation the Status Register is updated to reflect information about the result of the operation The ALU operations are divided into three main categories arithmetic logical and bit func tions Both 8 and 16 bit arithmetic is supported and the instruction set allows for efficient implementation of 32 bit aritmetic The ALU also provides a powerful multiplier supporting both signed and unsigned multiplication and fractional format When the device is powered on the CPU starts to execute instructions from the lowest address in the Flash Program Memory 0 The Program Counter PC addresses the next instruction to be fetched After a reset the PC is set to location 0 Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly Most AVR instructions use a 16 bit word format while a limited number uses a 32 bit format During interrupts an
16. by a configurable base address and address size for each chip celect For SDRAM both 4 bit SDRAM is supported and SDRAM configurations such as CAS Latency and Refresh rate is configurable in software The EBI is clocked from the Peripheral 2x Clock running up to two times faster than the CPU and supporting speeds of up to 64 MHz AMEL 7 5 Signature Rows The Non Volatile Memory has two sections that are not affected by chip erase Each section is one flash page in size and is used for parameter storage One section is for factory programmed device ID serial number and calibration data for func tions such as the oscillators The device ID for the available XMEGA 1 devices is shown Table 7 1 on page 13 Some of the calibration values will be automatically loaded to the corre sponding module or peripheral unit during reset This section can not be erased and it can be read from application software and external programming Table 7 1 Device ID bytes for 1 devices Device Device ID bytes Byte 2 Byte 1 Byte 0 ATxmega64A1 4E 96 1E 128 1 4 97 192 1 4 97 1 ATxmega256A1 46 98 1E ATxmega384A1 TBD TBD TBD The other section is fully accessible read and write from application software and external interface programming This is meant to be used to store data that should not be erased during chip erase or on chip debug sessions This sect
17. interrupt can be generated The AES Crypto Module also has DMA support with transfer triggers when encryption decryp tion is done and optional auto start of encryption decryption when the state memory is fully loaded AMEL 24 ADC 12 bit Analog to Digital Converter 24 1 Features 24 2 Overview 8067 05 08 Two ADCs with 12 bit resolution 2 Msps sample rate for each ADC Signed and Unsigned conversions 4 result registers with individual input channel control for each ADC 8 single ended inputs for each ADC 8x4 differential inputs for each ADC Software selectable gain of 2 4 8 16 32 or 64 Selectable accuracy of 8 or 12 bit Internal or External Reference selection Event triggered conversion for accurate timing DMA transfer of conversion results Interrupt Event on compare result devices have two Analog to Digital Converters ADC see Figure 24 1 on page 41 The two ADC modules can be operated simultaneously individually or synchronized The ADC converts analog voltages to digital values The ADC has 12 bit resolution and is capa ble of converting up to 2 million samples per second The input selection is flexible and both single ended and differential measurements can be performed The ADC can provide both signed and unsigned results and an optional gain stage is available to increase the dynamic range of the ADC It is a Successive Approximation Result ADC A SAR ADC measures o
18. kHz ULP WDT BOD Internal Oscillator Clkerc Calibrated Internal Oscillator PERIPHERALS 2 MHz Run Time Calibrated Internal Oscillator CLOCK CONTROL 32 MHz UNIT Run time Calibrated Internal Oscillator with PLL and Prescaler DMA 32 768 KHz INTERRUPT Crystal Oscillator EVSYS 0 4 16 MHz RAM Crystal Oscillator NVM MEMORY FLASH External Clock Input EEPROM Each clock source is briefly described in the following sub sections 10 3 Clock Options 10 3 1 32 kHz Ultra Low Power Internal Oscillator The 32 kHz Ultra Low Power ULP Internal Oscillator is a very low power consumption clock source It is used for the Watchdog Timer Brown Out Detection and as an asynchronous clock source for the Real Time Counter This oscillator cannot be used as the system clock source and it cannot be directly controlled from software 10 3 2 32 768 kHz Calibrated Internal Oscillator The 32 768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used as the system clock source or as an asynchronous clock source for the Real Time Counter It is calibrated during protection to provide a default frequency which is close to its nominal frequency AMEL 8067 05 08 10 3 3 10 3 4 10 3 5 10 3 6 10 3 7 10 3 8 8067 05 08 32 768 kHz Crystal Oscillator The 32 768 kHz Crystal Oscillator is a low power driver for an external watch crysta
19. of Timer and Compare registers are double buffered to ensure glitch free operation Single slope PWM dual slope PWM and frequency generation waveforms can be generated using the Com pare Channels Through the Event System any input pin or event in the microcontroller can be used to trigger input capture hence no dedicated pins is required for this The input capture has a noise cancel ler to avoid incorrect capture of the T C and can be used to do frequency and pulse width measurements A wide range of interrupt or event sources are available including T C Overflow Compare match and Capture for each Compare Capture channel in the T C PORTD PORTE and PORTF each has one Timer Counter 0 and one Timer Counter1 Notation of these Timer Counters are TCCO Time Counter CO TCC1 TCDO TCD1 TCEO TCE1 and TCF1 respectively AMEL 8067 05 08 1 Figure 15 1 Overview of a Timer Counter and closely related peripherals Timer Counter Base Counter Prescaler clkper Control Logic Pattern Capture Dead Time Fault Waveform The Hi Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits 4x This is available for all Timer Counters See Hi Res High Resolution Extension on page 33 for more details The Advanced Waveform Extension can be enabled to provide extra and more advanced fea tures for the Timer Counter This
20. the JTAG and PDI physical inter faces The PDI physical uses one dedicated pin together with the Reset pin and no general purpose pins are used JTAG uses four general purpose pins on PORTB 28 3 JTAG interface The JTAG physical layer handles the basic low level serial communication over four I O lines named TMS TCK TDI and TDO It complies to the IEEE Std 1149 1 for test access port and boundary scan 28 4 PDI Program and Debug Interface The is Atmel proprietary protocol for communication between the microcontroller and Atmel s development tools AMEL a 8067 05 08 29 Pinout and Pin Functions The pinout of is shown in Pinout Block Diagram on page 2 In addition to general functionality each pin may have several functions This will depend on which peripheral is enabled and connected to the actual pin Only one of the alternate pin functions can be used at time 29 1 Alternate Pin Function Description The tables below shows the notation for all pin functions available and describes its function 29 1 1 Operation Power Supply VCC GND 29 1 2 Port Interrupt functions SYNC ASYNC 29 1 3 Analog functions 29 1 4 functions 8067 05 08 Digital supply voltage Analog supply voltage Ground Port pin with full synchronous and limited asynchronous interrupt function Port pin with full sync
21. 0 on 0 0 40 1 Timer Counter 1 on 0 0 90 HIRESF High Resolution Extension on port F USART 0 on port OxOBBO USARTF1 USART 1 on port F SPIF Serial Peripheral Interface on port F 8067 05 08 AMEL 55 31 Instruction Set Summary 8067 05 08 Mnemonics Operands Description Operation Flags Clocks Arithmetic and Logic Instructions ADD Rd Rr Add without Carry Rd lt Rd Rr Z C N V S H 1 ADC Rd Rr Add with Carry lt Rd Rr C Z C N V S H 1 ADIW Rd K Add Immediate to Word Rd lt Rd 1 Rd K Z C N V S 2 SUB Rr Subtract without Carry Rd lt Rd Rr Z C N V S H 1 SUBI Rd K Subtract Immediate lt Rd K Z C N V S H 1 SBC Rd Rr Subtract with Carry Rd lt Rd Rr C Z C N V S H 1 Subtract Immediate with Carry Rd lt Rd K C Z C N V S H 1 SBIW Rd K Subtract Immediate from Word 1 lt Rd 1 Rd K Z C N V S 2 AND Rd Rr Logical AND Rd lt RdeRr 2 5 1 Logical AND with Immediate Rd lt 2 5 1 Logical OR Rd lt RdvRr 2 5 1 ORI Rd K Logical OR with Immediate Rd Z N V S 1 EOR Rd Rr Exclusive OR Rd Rd e Rr ZN VS 1 COM Rd One s Complement Rd lt FF Rd Z C N VS 1 NEG Rd Two s Complement Rd lt
22. 00 Rd Z C N V S H 1 SBR Set Bit s in Register Rd lt RdvK ZN V S 1 CBR Clear Bit s in Register Rd lt Rde FFh K ZN VS 1 INC Rd Increment Rd lt 1 2 6 1 DEC Rd Decrement Rd lt 4 1 2 6 1 TST Rd Test for Zero or Minus Rd lt RdeRd 2 5 1 Clear Register Rd lt Rd Rd 2 6 1 SER Rd Set Register Rd lt FF None 1 MUL Rd Rr Multiply Unsigned R1 RO lt RdxRr UU 2 2 MULS Multiply Signed R1 RO lt RdxRr SS 2 6 2 MULSU Rd Rr Multiply Signed with Unsigned 1 0 lt Rd x Rr SU 2 6 2 FMUL Fractional Multiply Unsigned 1 0 lt lt lt 1 UU 2 2 FMULS Fractional Multiply Signed 1 0 lt RdxRr lt lt 1 SS Z C 2 FMULSU Rd Rr Fractional Multiply Signed with Unsigned R1 RO lt RdxRr lt lt 1 SU Z C 2 DES K Data Encryption if H 0 then R15 RO lt Encrypt R15 RO 1 2 else if H 1 then R15 RO Decrypt R15 RO Branch Instructions RJMP k Relative Jump lt PC k 1 None 2 10 2 15 0 7 2 21 16 lt 0 EIJMP Extended Indirect Jump to Z 15 0 lt 2 None 2 21 16 lt EIND lt None 3 RCALL k Relative Call Subroutine lt PC k 1 None 2 30 ICALL Indirect Call to Z 15 0 lt 7 2 30 PC 21 16 lt 0 EICALL Extended Indirect Call to Z 15 0 lt 7 30 21 16 lt EIND
23. 1 TOSC1 L a a T T XTAL2 5 2 E gt Oscillator Watchdog 4 Oscillator 72 tc 9 9 Generation 1 Watchdog Counter Timer DATA BUS Power gt 4 1 gt Supervision Event System Oscillator PORIBOD amp PA O 7 Y gt 8 1 Controller Control RESET i GND g ACA Fr 1 1 DMA Sleep Controller Controller la RESET gt gt PDI gt DATA Prog Debug gt AREFA Controller Controller JTAG gt Internal gt gt Interrupt 8 0 7 apes Controller 8 PK 0 7 Port J 8 gt gt 0 7 Controller PB O 7V lt gt PORTB 8 2 gt PORT 8 gt 0 7 DACB gt la IRCOM DATA BUS EVENT ROUTING NETWORK gt MEN b b a 5181019 5 8 S uu 8 8 8 5 5 5 8185 Fs Fils 5 3 5 5 vv 8 PORT D 8 PORT E 8 PORT F 8 PC 0 7 PD O 7 PE O 7 0 7 5 4 Resources A comprehensive set of development tools application notes and datasheets are available for download on http www atmel com avr 41 Recommended reading XMEGA A Manual XMEGA A Application Note
24. 44A1 device in Features page 1 updated Ordering Information on page 2 and Memories on page 9 Replaced the Figure 3 1 on page 5 by a new XMEGA 1 detailed block diagram Inserted Errata 128 1 rev on page 70 AMEL 72 36 3 8067 02 08 1 Initial revision AMEL r 8067 05 08 Table of Contents FOALS I 1 lt Didi ERA IER ute 2E 1 1 Ordering Information m C 2 2 Pinout Block Diagram 2 3 4 3 1 Block aim 5 5 58 6 4 1 Recommended reading 6 D jDISCIaHHBeE rd 6 m 7 6 1 Druso De td paves ext 7 6 2 OVeIVIQW og te Ep 7 6 3 a de 8 6 4 ALU Arithmetic Logic 8 6 5 Program FOW EE 8 7 9 7 1 du qc 9 7 2
25. 52 2721 9778 Fax 852 2722 1369 Atmel Europe Le Krebs 8 Rue Jean Pierre Timbaud BP 309 78054 Saint Quentin en Yvelines Cedex France Tel 33 1 30 60 70 00 Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Fax 83 1 30 60 71 11 Product Contact Sales Contact www atmel com contacts Web Site Technical Support www atmel com avr atmel com Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no repres
26. 5V 67 7 AREF Int 1 0V 57 1 Signal to Noise Ratio SNR Ext 1 7V 59 3 2 5V 60 8 Int 1 0V 48 2 AREF Ext 1 7V 50 5 AREF Ext 2 5V 52 2 AREF Int 1 0V 39 3 ct AREF Ext 1 7V 41 6 AREF Ext 2 5V 43 2 AREF Int 1 0V 30 2 22 AREF Ext 1 7V 324 AREF Ext 2 5V 34 3 AMEL 66 NENNEN 8067 05 08 Table 33 2 ADC Gain Stage Characteristics Continued Symbol Parameter Condition Min Typ Max Units Signal Range TBD V DC Supply Current TBD mA Start up time TBD clk cycles 33 5 DAC Characteristics TBD Table 33 3 DAC Characteristics Symbol Parameter Condition Min Typ Max Units Resolution 12 12 LSB Integral Non Linearity INL TBD LSB Differential Non Linearity DNL TBD LSB Gain Error TBD LSB Offset Error TBD LSB Calibrated Gain Offset Error TBD LSB Output Range TBD V Output Settling Time TBD us Output Capacitance TBD nF Output Resistance TBD Reference Input Voltage TBD V Reference Input Capacitance TBD pF Reference Input Resistance TBD Current Consumption TBD mA Start up time TBD us 33 6 Analog Comparator Characteristics TBD Table 33 4 Analog Comparator Characteristics Symbol Parameter Condition Min Typ Max Units Offset 0 5 mV No High Speed mode 0 No Low Power mo
27. A Controller Two Signature Row Flash Memories Factory programmed data Oscillator calibration bytes Serial number Device ID for each device type User programmable memory One flash page in size Data is kept after normal chip erase 7 2 Overview The AVR architecture has two main memory spaces the Program Memory and the Data Mem In addition the XMEGA A1 features an EEPROM Memory for non volatile data storage three memory spaces are linear and require no paging The available memory size configura tions are shown in Ordering Information on page 2 In addition each device has a Flash memory signature row for calibration data device identification serial number etc Non volatile memory spaces can be locked for further write or read write operations This pre vents unrestricted access to the application software 73 In System Programmable Flash Program Memory The XMEGA 1 devices contains On chip In System Programmable Flash memory for program storage see Figure 7 1 on page 10 Since all AVR instructions are 16 or 32 bits wide each Flash address location is 16 bits AMEL 8067 05 08 The Program Flash memory space is divided into Application and Boot sections Both sections have dedicated Lock Bits for setting restrictions on write or read write operations The Store Pro gram Memory SPM instruction must reside in the Boot Section when used to write to the Flash memory A third section ins
28. C20 thenPC lt 1 1 2 BRLO k Branch if Lower if C 1 thenPC lt PC k 1 None 1 2 BRMI k Branch if Minus if N 1 thenPC lt PC k 1 None 1 2 BRPL k Branch if Plus if N 0 thenPC lt PC k 1 None 1 2 BRGE k Branch if Greater or Equal Signed if V 0 thenPC lt PC k 1 1 2 Branch if Less Than Signed N V 1 thenPC lt PC k 1 None 1 2 BRHS k Branch if Half Carry Flag Set if H 1 thenPC lt 1 None 1 2 BRHC k Branch if Half Carry Flag Cleared if H 0 thenPC lt PC k 1 None 1 2 BRTS k Branch if T Flag Set if T 1 thenPC lt PC k 1 None 1 2 Branch if T Cleared if T 0 thenPC lt 1 None 1 2 BRVS k Branch if Overflow Flag is Set 1 lt PC k 1 1 2 Branch if Overflow Flag is Cleared if V 0 then PC 1 None 1 2 BRIE k Branch if Interrupt Enabled if l21 thenPC lt 1 None 1 2 BRID k Branch if Interrupt Disabled if l20 thenPC lt 1 None 1 2 Data Transfer Instructions MOV Rd Rr Copy Register Rd lt Rr None 1 MOVW Rd Rr Copy Register Pair Rd 1 Rd Rr 1 Rr None 1 LDI Rd K Load Immediate lt 1 105 Load Direct from data space Rd lt 202 LD Rd X Load Indirect Rd lt X None 1000 Load Indirect and Post Increment lt X None 100 X lt 1 LD Rd X Load Indirect and Pre Decrement Xc X 1 lt 1 None 2000 lt lt X LD
29. DDR m n is used for addressing The most significant bits the address E2PAGE gives the page number and the least significant address bits 2 gives the byte in the page Table 7 3 Number of Bytes and Pages in the EEPROM Devices EEPROM Page Size E2BYTE E2PAGE No of Pages Size Bytes Bytes ATxmega64A1 2K 32 ADDR 4 0 ADDR 10 5 64 ATxmega128A1 2K 32 ADDR 4 0 ADDR 10 5 64 ATxmega192A1 2K 32 ADDR 4 0 ADDR 10 5 64 ATxmega256A1 4K 32 ADDR 4 0 ADDR 1 1 5 128 ATxmega384A1 4K 32 ADDR 4 0 ADDR 1 1 5 128 14 8067 05 08 O 8 DMAC Direct Memory Access Controller 8 1 Features 8 2 Overview 8067 05 08 Allows High speed data transfer From memory to peripheral From memory to memory From peripheral to memory From peripheral to peripheral 4 Channels From 1 byte and up to 16M bytes transfers in a single transaction Multiple addressing modes for source and destination address Increment Decrement Static 1 2 4 or 8 byte Burst Transfers Programmable priority between channels The XMEGA A1 has a Direct Memory Access DMA Controller to move data between memories and peripherals in the data space The DMA controller uses the same data bus as the CPU to transfer data It has 4 channels that can be configured independently Each DMA channel can perform data transfers in blocks of configurable size from 1 to 64K bytes A repeat counter can be use
30. DR O0 bit value the Slave Address Register Problem fix Workaround Use software to check the R W bit on general call address match TWI the minimum SCL low time could be violated in Master Read mode When the TWI is in Master Read mode and issuing a Repeated Start on the bus this will immediately release the SCL line even if one complete SCL low period has not passed This means that the minimum SCL low time in the specification could be violated Problem fix Workaround If this causes a potential problem in the application software must ensure that the Repeated Start is never issued before one SCL low time has passed Setting HIRES PR bit makes PWM output unavailable Setting the HIRES Power Reduction PR bit for PORTx will make any Frequency or PWM output for the corresponding Timer Counters and 1 unavailable on the pin Problem fix Workaround Do not write the HIRES PR bit on PORTx when frequency PWM output from TCx0 1 is used EEPROM erase and write does not work with all System Clock sources When doing EEPROM erase or Write operations with other clock sources than the 2 MHz RCOSC Flash will be read wrongly for one or two clock cycles at the end of the EEPROM operation Problem fix Workaround Alt 1 Use the internal 2 MHz RCOSC when doing erase or write operations on EEPROM Alt 2 Ensure to be in sleep mode while completing erase or write on EEPROM After starting erase or write operations o
31. F PB1 6 SYNC ADC1 ADC1 ADC1 AC1 AC1 PB2 7 SYNC ASYNC ADC2 ADC2 ADC2 AC2 DACO PB3 8 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1 PB4 9 SYNC 4 ADC4 ADC4 AC4 TMS PB5 10 SYNC ADC5 ADC5 ADC5 AC5 AC5 TDI PB6 11 SYNC ADC6 ADC6 ADC6 AC6 TCK PB7 12 SYNC ADC7 ADC7 ADC7 AC7 AMEL so 8067 05 08 Table 29 3 Port C Alternate functions PORTC PIN INTERRUPT TCCO AWEXC TCC1 USARTCO USARTC1 SPIC TWIC CLOCKOUT EVENTOUT GND 13 14 15 SYNC SDA PC1 16 SYNC OCOB SCL PC2 17 SYNCIASY ococ 18 SYNC OCOD OCOB TXDO 4 19 5 OCOC OC1A 55 5 20 SYNC OCOC XCK1 MOSI PC6 21 SYNC OCOD RXD1 MISO PC7 22 SYNC OCOD TXD1 SCK CLKOUT EVOUT Table 29 4 Port D Alternate functions PORTD PIN INTERRUPT TCDO TCD1 USARTDO USARTD1 SPID TWID CLOCKOUT EVENTOUT GND 23 vcc 24 PDO 25 SYNC PD1 26 SYNC OCOB SCL PD2 27 SYNC ASYNC OCOC RXDO PD3 28 SYNC OCOD TXDO PDA 29 SYNC OC1A 55 5 30 SYNC OC1B XCK1 MOSI PD6 31 SYNC RXD1 MISO PD7 32 SYNC TXD1 SCK CLKOUT EVOUT Table 29 5 Port E Alternate functions PORTE PIN INTERRUPT TCEO AWEXE TCE1 USARTEO USARTE1 SPIE TWIE CLOCKOUT EVENTOUT GND 33 vcc 34 PEO 35 SYNC
32. Features High performance Low power 8 16 bit AVR XMEGA Microcontroller Non Volatile Program and Data Memories 64K 384K Bytes of In System Self Programmable Flash 4K 8K Bytes Boot Section with Independent Lock Bits 2K Bytes EEPROM BDTIC www bdtic com ATMEL 4K 32K Bytes Internal SRAM External Bus Interface for up to 16M bytes SRAM External Bus Interface for up to 128M bit SDRAM Peripheral Features Four channel DMA Controller with support for external requests Eight channel Event System Eight 16 bit Timer Counters Four Timer Counters with 4 Output Compare or Input Capture channels EE 8 16 bit AMR XMEGA A1 Microcontroller Four Timer Counters with 2 Output Compare or Input Capture channels High Resolution Extension on all Timer Counters Advanced Waveform Extension on two Timer Counters Eight USARTs IrDA modulation demodulation for one USART Four Two Wire Interfaces with dual address match and SMBus compatible Four SPI Serial Peripheral Interface peripherals AES and DES Crypto Engine 16 bit Real Time Counter with separate Oscillator Two Eight channel 12 bit 2 Msps Analog to Digital Converters Two Two channel 12 bit 1 Msps Digital to Analog Converters ATxmega384A1 ATxmega256A1 192 1 128 1 ATxmega64A1 Four Analog Comparators with Window compare function External Interrupts on all General Purp
33. R 56 Packaging information 60 32 1 ji a 60 32 2 100 1 61 Electrical Characteristics 62 33 1 X Absolute Maximum enne ene 62 33 2 Characteristics Fred ned enano an eene Rn aae 62 33 3 pM IT 64 334 ADC Characteristics 0 65 335 Characteristics 67 33 6 Analog Comparator Characteristics TBD 67 Typical Characteristics TBD mi n nata Pun kk nk ra Kk 69 2 M 70 95 1 JATxme gal28A Q aententia 70 Datasheet Revision History 72 36 1 80672 05 08 EE 72 36 2 80678 05 08 72 36 3 8067 02 08 73 Table of Content c c i AMEL AIMEL Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 8
34. Rd Y Load Indirect lt lt Y None 1000 LD Rd Y Load Indirect and Post Increment Rd lt Y None 1000 lt 1 57 gt 8067 05 08 Mnemonics Operands Description Operation Flags Clocks LD Rd Y Load Indirect and Pre Decrement e Y i None 2000 Rd e LDD Rd Y q Load Indirect with Displacement Rd e None 20100 LD Rd Z Load Indirect Rd lt 2 None 100 LD Rd Z Load Indirect and Post Increment lt 2 None 100 2 lt 7 LD Rd Z Load Indirect and Pre Decrement 2 lt 7 1 2000 Rd lt 2 LDD Rd Z q Load Indirect with Displacement lt Z q None 20100 STS k Rr Store Direct to Data Space k lt Rd None 20 Store Indirec lt Rr None 10 ST Rr Store Indirect and Post Increment lt Rr None 10 X lt X 1 ST Rr Store Indirect and Pre Decrement X lt X i None 20 X e Rr ST Rr Store Indirec Y lt Rr None 10 ST Rr Store Indirect and Post Increment Y lt Rr None 10 lt Y 1 Y Rr Store Indirect and Pre Decrement lt Y i None 20 Y e Rr STD Rr Store Indirect with Displacement lt Rr None 20 7 Store Indirec 2 lt Rr None 10 ST Z Rr Store Indirect and Post Increment 2 lt Rr None 10 2 lt 241 2 Store Indirect and Pre Decremen
35. SRAM 3FFF 8K 4000 External Memory AMEL Byte Address 2000 2FFF 3000 FFFFFF ATxmega64A1 Registers 4KB EEPROM 2K RESERVED Internal SRAM 4K External Memory 0 to 16 MB 10 7 4 1 7 4 2 7 4 3 8067 05 08 5 ATxmega384A1 Byte Address ATxmega256A1 0 Registers 0 Registers FFF 4KB FFF 4KB 1000 1000 EEPROM EEPROM 4K 1FFF 2000 Internal SRAM 2000 Internal SRAM 9FFF 32K 5FFF 16K 10000 External Memory 6000 External Memory FFFFFF 0 to 16 MB FFFFFF 0 to 16 MB Memory All peripherals and modules are addressable through I O memory locations in the data memory space All memory locations can be accessed by the Load LD LDS LDD and Store ST STS STD instructions transferring data between the 32 general purpose registers in the CPU and the Memory The IN and OUT instructions can address memory locations in the range 0x00 Ox3F directly registers within the address range 0x00 Ox1F are directly bit accessible using the SBI and CBI instructions The value of single bits can be checked by using the SBIS and SBIC instruc tions on these registers The memory address for all peripherals and modules in A1 is shown in the eral Module Address Map on page 54 SRAM Data Memory The XMEGA 1 dev
36. YNC D1 D1 D1 D1 A1 D1 A1 D1 A1 A9 PJ2 67 SYNC ASYNC D2 D2 D2 D2 A2 D2 A2 D2 A2 A10 PJ3 68 SYNC 03 03 03 D3 A3 D3 A3 A11 PJ4 69 SYNC 8 04 04 4 4 4 4 D4 A4 A12 PJ5 70 SYNC A9 D5 D5 D5 A5 D5 A5 D5 A5 A13 PJ6 71 SYNC A10 D6 D6 D6 A6 D6 A6 D6 A6 A14 PJ7 72 SYNC A11 D7 D7 D7 A7 D7 A7 D7 A7 A15 8067 05 08 AMEL 52 Table 29 9 Port K Alternate functions PORT K PIN INTERRUPT SDRAM 3P SRAM ALE1 SRAM ALE2 LPC3 ALE1 GND 73 vcc 74 PKO 75 SYNC AO 8 A0 A8 A16 A8 76 SYNC A1 A1 A9 A1 A9 A17 A9 PK2 77 2 2 10 2 10 18 10 78 SYNC A3 11 11 19 11 4 79 5 4 4 12 4 12 20 12 5 80 SYNC A5 A5 A13 A5 A13 A21 A13 PK6 81 SYNC A6 6 14 6 14 22 14 82 SYNC A7 7 15 A7 A15 A23 A15 Table 29 10 Port Q Alternate functions PORT PIN INTERRUPT TOSC vcc 83 GND 84 85 SYNC TOSC1 PQ1 86 SYNC TOSC2 PQ2 87 SYNC ASYNC PQ3 88 SYNC Table 29 11 Port R Alternate functions PORTR PIN INTERRUPT PDI XTAL PDI 89 PDI DATA RESET 90 PDI CLOCK PRO 91 SYNC XTAL2 PR1 92 SYNC XTAL1 8067 05 08 AMEL 53 30 Peripheral Module Address 8067 05 08 The address maps show the base address for each p
37. and the asynchronous Real Time Counter RTC clock source are stopped This allows operation of asynchronous modules only The only inter rupts that can wake up the MCU are the Two Wire Interface address match interrupts and asynchronous port interrupts e g pin change Power save Mode Standby Mode Power save mode is identical to Power down with one exception If the RTC is enabled it will keep running during sleep and the device can also wake up from interrupts Standby mode is identical to Power down with the exception that all enabled system clock sources are kept running while the CPU Peripheral and RTC clocks are stopped This reduces the wake up time when external crystals or resonators are used Extended Standby Mode 8067 05 08 Extended Standby mode is identical to Power save mode with the exception all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped This reduces the wake up time when external crystals or resonators are used AMEL n 12 System Control and Reset 12 1 Features Multiple reset sources for safe operation and device reset Power On Reset External Reset Watchdog Reset The Watchdog Timer runs from separate dedicated oscillator Brown Out Reset Accurate programmable Brown Out levels JTAG Reset PDI reset Software reset Asynchronous reset Norunning clock in the device is required for reset Reset st
38. ansmis sion without any delay between frames There are separate interrupt vectors for receive and transmit complete enabling fully interrupt driven communication Frame error and buffer over flow are detected in hardware and indicated with separate status flags Even or odd parity generation and parity check can also be enabled One USART can use the IRCOM module to support IrDA 1 4 physical compliant pulse modula tion and demodulation for baud rates up to 115 2 kbps PORTC PORTD PORTE and PORTF each has two USARTSs Notation of these peripherals are USARTCO USARTC1 USARTDO USARTD1 USARTEO USARTE1 USARTFO USARTF1 respectively AMEL s 22 IRCOM IR Communication Module 22 1 Features 22 2 Overview 8067 05 08 Pulse modulation demodulation for infrared communication Compatible to IrDA 1 4 physical for baud rates up to 115 2 kbps Selectable pulse modulation scheme 3 16 of baud rate period Fixed pulse period 8 bit programmable Pulse modulation disabled Built in filtering Can be connected to and used by one USART at the time XMEGA contains an Infrared Communication Module IRCOM for IrDA communication with baud rates up to 115 2 kbps This supports three modulation schemes 3 16 of baud rate period fixed programmable pulse time based on the Peripheral Clock speed or pulse modulation dis abled There is one IRCOM available which can be connected to any USART to enable infrared pulse c
39. are only available for Timer Counter 0 See AWEX Advanced Waveform Extension on page 32 for more details AMEL 16 AWEX Advanced Waveform Extension 16 1 Features 16 2 Overview 8067 05 08 Output with complementary output from each Capture channel Four Dead Time Insertion DTI Units one for each Capture channel 8 bit DTI Resolution Separate High and Low Side Dead Time Setting Double Buffered Dead Time Event Controlled Fault Protection Single Channel Multiple Output Operation for BLDC motor control Double Buffered Pattern Generation The Advanced Waveform Extension AWEX provides extra features to the Timer Counter in Waveform Generation WG modes The AWEX enables easy and safe implementation of for example advanced motor control AC BLDC SR and Stepper and power control applications Any WG output from a Timer Counter 0 is split into a complimentary pair of outputs when any AWEX feature is enabled These output pairs go through a Dead Time Insertion DTI unit that enables generation of the non inverted Low Side LS and inverted High Side HS of the WG output with dead time insertion between LS and HS switching The DTI output will override the normal port value according to the port override setting Optionally the final output can be inverted by using the invert setting for the port pin The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is con
40. assume internal memory accesses and are not valid 59 32 Packaging information 32 1 100A Notes 1 This package conforms to JEDEC reference MS 026 Variation AED 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 0 25 mm per side Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch 3 Lead coplanarity is 0 08 mm maximum TITLE SYMBOL COMMON DIMENSIONS Unit of Measure mm MAX 1 20 0 15 1 05 16 25 14 10 16 25 14 10 0 27 0 20 0 75 0 50 TYP DRAWING NO REV AMEL p 100A 100 lead 14 x 14 mm Body Size 1 0 mm Body Thickness 0 5 mm Lead Pitch Thin Profile Plastic Quad Flat Package TQFP AMEL 8067 05 08 10 5 2001 60 32 2 100 1 Marked 1 Identifier TOP VIEW 0 90 000000000 6 0000000000 09000000000 0000000000 909000000000 000000000 0 1 Corner SYMBOL A SIDE VIEW COMMON DIMENSIONS Unit of Measure mm MIN 1 10 NOM MAX 1 20 1 0 30 0 35 0 40 8 90 9 00 9 10 TITLE
41. ation on Rising edge Falling edge Toggle Window function interrupt and event generation on Signal above window Signal inside window Signal below window features four Analog Comparators AC An Analog Comparator compares two volt ages and the output indicates which input is largest The Analog Comparator may be configured to give interrupt requests and or events upon several different combinations of input change Both hysteresis and propagation delays may be adjusted in order to find the optimal operation for each application A wide range of input selection is available both external pins and several internal signals can be used The Analog Comparators are always grouped in pairs ACO and AC1 on each analog port They have identical behavior but separate control registers Optionally the state of the comparator is directly available on a pin PORTA and PORTB each has one AC pair Notations are ACA and ACB respectively AMEL 1 Figure 26 1 Analog comparator overview Pin inputs Internal inputs Pin O output Pin inputs Internal inputs VCC scaled Interrupt Interrupts sensitivity control Events Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled AMEL T 8067 05 08 26 3 Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be u
42. atus register 12 2 Resetting the AVR During reset all registers are set to their initial values The SRAM content is not reset Appli cation execution starts from the Reset Vector The instruction placed at the Reset Vector should be an Absolute Jump JMP instruction to the reset handling routine By default the Reset Vector address is the lowest Flash program memory address 0 but it is possible to move the Reset Vector to the first address in the Boot Section The I O ports of the AVR are immediately tri stated when a reset source goes active The reset functionality is asynchronous so no running clock is required to reset the device After the device is reset the reset source can be determined by the application by reading the Reset Status Register 12 3 Reset Sources 12 3 1 12 3 2 12 3 3 12 3 4 8067 05 08 MCU is reset when the supply voltage VCC is below Power on Reset threshold voltage External Reset The MCU is reset when a low level is present on the RESET pin Watchdog Reset The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled The Watchdog Timer runs from a dedicated oscillator independent of the System Clock For more details see Watchdog Timer on page 23 Brown Out Reset The MCU is reset when the supply voltage VCC is below the Brown Out Reset threshold voltage and the Brown out Detector is e
43. cteristics Symbol Parameter Condition Min Typ Max Units Input Capacitance TBD pF 1X Gain AREF Int 1 0V 5 VCC 3 3V AREF 2 5V 3 2 Gain Int 1 0V 5 VCC 3 3V AREF Ext 2 5V 3 4X Gain AREF Int 1 0V 5 VCC 3 3V AREF Ext 2 5V 2 5 Offset Error E LSB VCC 3 3V AREF Ext 2 5V 2 16X Gain AREF Int 1 0V 4 VCC 3 3V AREF Ext 2 5V 1 5 32X Gain AREF Int 1 0V 3 VCC 3 3V AREF Ext 2 5V 0 64X Gain AREF Int 1 0V 3 VCC 3 3V AREF Ext 2 5V 5 65 8067 05 08 Table 33 2 ADC Gain Stage Characteristics Continued Symbol Parameter Condition Min Typ Max Units 1X Gain AREF Int 1 0V TBD 3 3V Ext 2 5V TBD 2X Gain AREF Int 1 0V TBD VCC 3 3V AREF Ext 2 5V TBD 4X Gain AREF Int 1 0V TBD VCC 3 3V AREF Ext 2 5V TBD 8X Gain AREF Int 1 0V TBD VCC 3 3V Ext 2 5V TBD 16X Gain AREF Int 1 0V TBD VCC 3 3V AREF Ext 2 5V TBD 32X Gain AREF Int 1 0V TBD VCC 3 3V AREF Ext 2 5V TBD 64 Gain AREF Int 1 0V TBD VCC 3 3V AREF Ext 2 5V TBD AREF Int 1 0V 76 3 a gy AREF Ext 17V 75 7 AREF Ext 2 5V 74 6 AREF Int 1 0V 71 2 AREF Ext 17V 72 2 AREF Ext 2 5V 71 6 AREF Int 1 0V 64 8 2 AREF Ext 1 7V 66 8 AREF Ext 2
44. d enabling disabling or change of WDT settings For maximum safety the WDT also has an Always on mode This mode is enabled by program ming a fuse In Always on mode application software can not disable the WDT AMEL 23 8067 05 08 13 Programmable Multi level Interrupt Controller 13 1 Features Separate interrupt vector for each interrupt Short predictable interrupt response time Programmable Multi level Interrupt Controller 3 programmable interrupt levels Selectable priority scheme within low level interrupts round robin or fixed Non Maskable Interrupts NMI nterrupt vectors can be moved to the start of the Boot Section 13 2 Overview A1 has a Programmable Multi level Interrupt Controller PMIC peripherals can define three different priority levels for interrupts high medium or low Medium level interrupts may interrupt low level interrupt service routines High level interrupts may interrupt both low and medium level interrupt service routines Low level interrupts have an optional round robin scheme to make sure all interrupts are serviced within a certain amount of time The built in oscillator failure detection mechanism can issue a Non Maskable Interrupt NMI 13 3 Interrupt vectors When an interrupt is serviced the program counter will jump to the interrupt vector address The interrupt vector is the sum of the peripheral s base interrupt address a
45. d subroutine calls the return address PC is stored on the Stack The Stack is effectively allocated in the general data SRAM and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM After reset the Stack Pointer SP points to the highest address in the internal SRAM The SP is read write accessible in the memory space enabling easy implementation of multiple stacks or stack areas The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU AMEL 7 7 1 Features Flash Program Memory One linear address space In System Programmable Self Programming and Bootloader support Application Section for application code Application Table Section for application code or data storage Boot Section for application code or bootloader code Separate lock bits and protection for all sections Data Memory One linear address space Single cycle access from CPU SRAM EEPROM Byte or page accessible Optional memory mapping for direct load and store Memory Configuration and Status registers for all peripherals and modules 16 bit accessible General Purpose Register for global variables or flags External Memory support Bus arbitration Safe and deterministic handling of CPU and DMA Controller priority Separate buses for SRAM EEPROM Memory and External Memory access Simultaneous bus access for CPU and DM
46. d to repeat each block transfer for single transactions up to 16M bytes Each DMA channel can be configured to access the source and destination memory address with incrementing decrement ing or static addressing The addressing is independent for source and destination address When the transaction is complete the original source and destination address can automatically be reloaded to be ready for the next transaction DMAC can access all the peripherals through their memory registers and the may be used for automatic transfer of data to from communication modules as well as automatic data retrieval from ADC conversions data transfer to DAC conversions or data transfer to or from port pins A wide range of transfer triggers is available from the peripherals Event System and software Each DMA channel has different transfer triggers To allow for continuous transfers two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa The DMA controller can read from memory mapped EEPROM but it cannot write to the EEPROM or access the Flash AMEL 9 Event System 9 1 Features 9 2 Overview 8067 05 08 Inter peripheral communication and signalling with minimum latency CPU and DMA independent operation 8 Event Channels allows for up to 8 signals to be routed at the same time Events can be generated by Timer Counters Real Time Count
47. de 0 mV Small High Speed mode 3 mV Hysteresis Small Low Power mode 3 mV Large High Speed mode 25 mV Large Low Power mode 30 mV High Speed mode 50 Propagation Delay ns Low power mode 130 AMEL 8067 05 08 Table 33 4 Analog Comparator Characteristics Symbol Parameter Condition Min Typ Max Units High Speed mode TBD Current Consumption Low power mode TBD Start up time TBD us AIMEL 68 NENNEN 8067 05 08 34 Typical Characteristics AMEL 8067 05 08 35 Errata 35 1 128 1 8067 05 08 1 Bootloader Section Flash is non functional The Bootloader Section is non functional and bootloader or application code cannot reside in this part of the Flash Problem fix Workaround None do not use the Bootloader Section Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator AC and then selected deselected as input for the another AC the first comparator will be affected for up to 1 us and could potentially give a wrong comparison result Problem fix Workaround If the Bandgap is required for both ACs simultaneously configure the input selection for both ACs before enabling any of them DAC is nonlinear and inaccurate when reference is above 2 4V Using the DAC with a refer
48. e used for simple routing of signals pin func tions or for sequencing of events The maximum latency is two CPU clock cycles from when an event is generated in one periph eral until the actions are triggered in one or more other peripherals The Event System is functional in both Active and Idle modes AMEL 1 Figure 9 1 Event system block diagram ADCx RTC Network DACx IRCOM DMAC T Cxn The Event Routing Network can directly connect together ADCs DACs Analog Comparators ports the Real time Counter RTC Timer Counters and the IR Com munication Module IRCOM Events can also be generated from software CPU ACx events from all peripherals are always routed into the Event Routing Network This consist of eight multiplexers where each can be configured in software to select which event to be routed into that event channel eight event channels are connected to the peripherals that can use events and each of these peripherals can be configured to use events from one or more event channels to automatically trigger a software selectable action AMEL 8067 05 08 10 System Clock and Clock options 10 1 Features Fast start up time Safe run time clock switching Internal Oscillators 32 MHz run time calibrated RC oscillator 2 MHz run time calibrated RC oscillator 32 kHz calibrated RC oscillator 32 kHz Ultra Low P
49. ence voltage above 2 4V give inaccurate output when converting codes that give below 0 75V output 20 LSB for continuous mode 200 LSB for Sample and Hold mode Problem fix Workaround None avoid using a voltage reference above 2 4V ADC gain stage output range is limited to 2 6 V The amplified output of the ADC gain stage will never go above 2 6V hence the differential input will only give correct output when below 2 6V gain For the available gain settings this gives a differential input range of 1X gain 2 6V 2X gain 1 3V 4X gain 0 65V 8X gain 325 mV 16X gain 163 mV 32X gain 82 mV 64X gain 41 mV Problem fix Workaround Keep the amplified voltage output from the ADC gain stage below 2 6V in order to get a cor rect result or keep ADC voltage reference is below2 6V AMEL 8067 05 08 ADC has up to 2 LSB inaccuracy The ADC will have up to 2 LSB inaccuracy visible as saw tooth pattern on the input volt age output value transfer function of the ADC The inaccuracy increases with increasing voltage reference reaching 2 LSB with reference Problem fix Workaround None the actual ADC resolution will be reduced with up to 2 LSB TWI a general address call will match independent of the R W bit value When the TWI is in Slave mode and a general address call is issued on the bus the TWI Slave will get an address match regardless of the R W bit AD
50. entations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life 2008 Atmel Corporation All rights reserved Atmel logo and combinations thereof AVR and others are registered trademarks XMEGA M and others aretrademarks of Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of others 8067 05 08
51. er RTC Analog to Digital Converters ADCx Analog Comparators ACx Ports PORTx System Clock Software CPU Events can be used by Timer Counters TCxn Analog to Digital Converters ADCx Digital to Analog Converters DACx Ports PORTx DMA Controller DMAC IR Communication Module IRCOM The same event can be used by multiple peripherals for synchronized timing Advanced Features Manual Event Generation from software CPU Quadrature Decoding Digital Filtering Functions in Active and Idle mode The Event System is a set of features for inter peripheral communication It enables the possibil ity for a change of state in one peripheral to automatically trigger actions in one or more peripherals What changes in a peripheral that will trigger actions in other peripherals are config urable by software It is a simple but powerful system as it allows for autonomous control of peripherals without any use of interrupts CPU or DMA resources The indication of a change in a peripheral is referred to as an event and is usually the same as the interrupt conditions for that peripheral Events are passed between peripherals using a dedi cated routing network called the Event Routing Network Figure 9 1 on page 17 shows a basic block diagram of the Event System with the Event Routing Network and the peripherals to which it is connected This highly flexible system can b
52. erence selection Channel A Register 9 A UUU Channel A DAC HARI Channel B Register Event Trigger Each DAC has one continuous output with high drive capabilities for both resistive and capaci tive loads It is also possible to split the continuous time channel into two Sample and Hold S H channels each with separate data conversion registers A DAC conversion may be started from the application software by writing the data conversion registers The DAC can also be configured to do conversions triggered by the Event System to have regular timing independent of the application software DMA may be used for transferring data from memory locations to DAC data registers The DAC has a built in calibration system to reduce offset and gain error when loading with a calibration value from software PORTA and PORTB each has one DAC Notation of these peripherals are DACA and DACB respectively AMEL 2 26 Analog Comparator 26 1 Features 26 2 Overview 8067 05 08 Four Analog Comparators Selectable Power vs Speed Selectable hysteresis 0 20 mV 50 mV Analog Comparator output available on pin Flexible Input Selection pins on the port Output from the DAC Bandgap reference voltage Voltage scaler that can perform a 64 level scaling of the internal VCC voltage Interrupt and event gener
53. eripheral and module For complete register description and summary for each peripheral module refer to the XMEGA A Manual Base Address Name Description 0x0000 GPIO General Purpose IO Registers 0x0010 VPORTO Virtual Port 0 0x0014 VPORT1 Virtual Port 1 0x0018 VPORT2 Virtual Port 2 0x001C VPORT3 Virtual Port 2 0x0030 CPU CPU 0x0040 CLK Clock Control 0x0048 SLEEP Sleep Controller 0x0050 OSC Oscillator Control 0x0060 DFLLRC32M DFLL for the 32 MHz Internal RC Oscillator 0x0068 DFLLRC2M DFLL for the 2 MHz RC Oscillator 0x0070 PR Power Reduction 0x0078 RST Reset Controller 0x0080 WDT Watch Dog Timer 0x0090 MCU MCU Control 0x00A0 PMIC Programmable Multilevel Interrupt Controller 0 00 0 Configuration 0 00 0 5 5 0 0100 Controller 0 0180 EVSYS Event System 0 01 0 NVM Non Volatile Memory NVM Controller 0x0200 ADCA Analog to Digital Converter on port A 0x0240 ADCB Analog to Digital Converter on port B 0x0300 DACA Digital to Analog Converter on port A 0x0320 DACB Digital to Analog Converter on port B 0x0380 ACA Analog Comparator pair on port A 0x0390 ACB Analog Comparator pair on port B 0x0400 RTC Real Time Counter 0x0440 External Bus Interface 0x0480 TWIC Two Wire Interface on port C 0x0490 TWID Tw
54. family of low power high performance and peripheral rich CMOS 8 16 bit microcontrollers based on the AVR enhanced RISC architecture By executing powerful instructions in a single clock cycle the XMEGA A1 achieves throughputs approaching 1 Million Instructions Per Second MIPS per MHz allowing the system designer to optimize power con sumption versus processing speed The AVR CPU combines rich instruction set with 32 general purpose working registers All the 32 registers are directly connected to the Arithmetic Logic Unit ALU allowing two independent registers to be accessed in one single instruction executed in one clock cycle The resulting architecture is more code efficient while achieving throughputs many times faster than conven tional single accumulator or CISC based microcontrollers The XMEGA A1 devices provides the following features In System Programmable Flash with Read While Write capabilities Internal EEPROM and SRAM four channel DMA Controller eight channel Event System Programmable Multi level Interrupt Controller 78 general purpose lines 16 bit Real Time Counter RTC eight flexible 16 bit Timer Counters with compare modes and PWM eight USARTS four Two Wire Serial Interfaces TWIs four Serial Peripheral Interfaces SPIs AES and DES crypto engine two 8 channel 12 bit ADCs with optional differ ential input with programmable gain two 2 channel 12 bit DACs four analog comparators with window mode program
55. for SPI Serial Clock for SPI Timer Oscillator pin n Input Output for inverting Oscillator pin n Peripheral Clock Output Event Channel 0 Output Reset pin Program and Debug Interface Clock pin Program and Debug Interface Data pin JTAG Test Clock JTAG Test Data In JTAG Test Data Out JTAG Test Mode Select AMEL 29 2 Alternate Pin Functions The tables below show the primary default function for each pin on a port in the first column the pin number in the second column and then all alternate pin functions in the remaining columns The head row shows what peripheral that enable and use the alternate pin functions Table 29 1 Port A Alternate functions PORTA PIN INTERRUPT ADCA ADCA ADCA ADCA ACA ACA ACA DACA REFA POS NEG GAINPOS GAINNEG POS NEG OUT GND 93 94 95 SYNC ADCO ADCO ADCO ACO ACO AREF PA1 96 SYNC ADC1 ADC1 ADC1 AC1 AC1 PA2 97 SYNC ASYNC ADC2 ADC2 ADC2 AC2 DACO 98 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1 PA4 99 SYNC ADC4 ADC4 ADC4 AC4 5 100 SYNC ADC5 ADC5 ADC5 AC5 AC5 PA6 1 SYNC ADC6 ADC6 ADC6 AC6 PA7 2 SYNC ADC7 ADC7 ADC7 Table 29 2 Port B Alternate functions PORT PIN INTERRUPT ADCB ADCB ADCB ADCB ACB ACB ACB DACB REFB JTAG POS NEG GAINPOS GAINNEG POS NEG OUT GND 3 4 5 SYNC ADCO ADCO ADCO ACO ACO ARE
56. hronous and full asynchronous interrupt function Analog Comparator input pin n Analog Comparator 0 Output Analog to Digital Converter input pin n Digital to Analog Converter output pin n Analog Reference input pin Address line n Data line n Chip Select n Address Latch Enable pin n SRAM Read Enable SRAM External Data Memory Write SRAM SDRAM Bank Address SDRAM Column Access Strobe SDRAM SDRAM Clock Enable SDRAM SDRAM Clock SDRAM Data Mask Signal Output Enable SDRAM Row Access Strobe SDRAM AMEL a 29 1 5 Timer Counter AWEX functions 29 1 6 Communication functions SCL SDA SCLIN SCLOUT SDAIN SDAOUT XCKn RXDn TXDn 55 MOSI MISO SCK 29 1 7 Oscillators Clock and Event TOSCn XTALn CLKOUT EVOUT 29 1 8 Debug System functions RESET PDI_CLK PDI_DATA TCK TDI TDO TMS 8067 05 08 Output Compare Channel x Timer Counter Inverted Output Compare Channel x for Timer Counter n Serial Clock for TWI Serial Data for TWI Serial Clock In for TWI when external driver interface is enabled Serial Clock Out for TWI when external driver interface is enabled Serial Data In for when external driver interface is enabled Serial Data Out for TWI when external driver interface is enabled Transfer Clock for USART n Receiver Data for USART n Transmitter Data for USART n Slave Select for SPI Master Out Slave In for SPI Master In Slave Out
57. ices has internal SRAM memory for data storage EEPROM Data Memory The XMEGA 1 devices has internal EEPROM memory for non volatile data storage It is addressable either in a separate data space or it can be memory mapped into the normal data memory space The EEPROM memory supports both byte and page access AMEL 7 4 4 EBI External Bus Interface 8067 05 08 Supports SRAM up to 512K Bytes using 2 port EBI 16M Bytes using 3 port EBI Supports SDRAM up to 128M bit using 3 port EBI Four software configurable Chip Selects Software configurable Wait State insertion Clocked from the Peripheral 2x Clock at up to two times the CPU clock speed The External Bus Interface EBI is the interface for connecting external peripheral and memory to the data memory space The 1 has 3 ports that can be used for the EBI It can inter face external SRAM SDRAM and or peripherals such as LCD displays and other memory mapped devices The address space and the number of pins used for the external memory is selectable from 256 bytes 8 bit and up to 16M bytes 24 bit Various multiplexing modes for address and data lines can be selected for optimal use of pins when more or less pins is available for the EBI Each of the four chip selects has seperate configuration and can be configured for SRAM SRAM Low Pin Count LPC or SDRAM The data memory address space associated for each chip select is decided
58. ide the Application section is referred to as the Application Table section which has separate Lock bits for storage of write or read write protection The Application Table sec tion can be used for storing non volatile data or application software Figure 7 1 2EFFF 2F000 2FFFF 30000 30FFF Word Address 1EFFF 16FFF EFFF 12000 17000 000 1FFFF 17FFF FFFF 20000 18000 10000 20FFF 18 10FFF 77 7800 8000 87FF Flash Program Memory Hexadecimal address Application Section 384K 256K 192K 128K 64K Application Table Section 8 8 8 8 4 Boot Section 8K 8K 8K 8K AK The Application Table Section and Boot Section can also be used for general application software 74 Data Memory Figure 7 2 Byte Address 2000 5FFF 6000 FFFFFF 8067 05 08 The Data Memory consist of the Memory SRAM memories within lin ear address space see Figure 7 2 on page 10 To simplify development the memory map for all devices in the family is identical and with empty reserved memory space for smaller devices ATxmega192A1 Registers 4 2K RESERVED Internal SRAM 16K External Memory 0 to 16 MB Data Memory Map Hexadecimal address Byte Address ATxmega128A1 0 Registers FFF 4KB 1000 EEPROM 17FF a9 RESERVED 2000 Internal
59. ines Fully Programmable Slave Address with General Call Support Address Recognition Causes Wake up when in Sleep Mode and System Management Bus SMBus compatible The Two Wire Interface TWI is a bi directional wired AND bus with only two lines the clock SCL line and the data SDA line The protocol makes it possible to interconnect up to 128 indi vidually addressable devices Since it is a multi master bus one or more devices capable of taking control of the bus can be connected The only external hardware needed to implement the bus is a single pull up resistor for each of the TWI bus lines Mechanisms for resolving bus contention are inherent in the TWI protocol PORTC PORTD PORTE and PORTF each has one TWI Notation of these peripherals are TWIC TWID TWIE and TWIF respectively AMEL 35 20 SPI Serial Peripheral Interface 20 1 Features 20 2 Overview 8067 05 08 Four Identical SPI peripherals Full duplex Three wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake up from Idle Mode Double Speed CK 2 Master SPI Mode The Serial Peripheral Interface SPI allows high speed full duplex synchronous data transfer between different devices Devices can communicate using a master slave scheme and data is transferred both to and from the devices simu
60. ion can only be erased using a dedicated erase command 8067 05 08 AMEL 13 7 66 Flash and EEPROM Page Size The Flash Program Memory and EEPROM data memory is organized in pages The pages are word accessible for the Flash and byte accessible for the EEPROM Table 7 2 on page 14 shows the Flash Program Memory organization Flash write and erase operations are performed on one page at the time while reading the Flash is done one byte at the time For Flash access the Z pointer Z m n is used for addressing The most significant bits in the address FPAGE gives the page number and the least significant address bits FWORD gives the word in the page Table 7 2 Number of words and Pages in the Flash Devices Flash Page Size FWORD FPAGE Application Boot Size Bytes words Size No of Pages Size No of Pages ATxmega64A1 64K 4 128 2171 Z 16 8 64K 256 4K 16 ATxmega128A1 128K 8K 256 Z 8 1 2117 9 128 256 8K 16 ATxmega192A1 192K 8K 256 28 11 2118 9 192 384 8K 16 ATxmega256A1 256K 8K 256 Z 8 1 2118 9 256 512 8K 16 ATxmega384A1 384K 8K 256 218 1 z 19 9 384K 768 8K 16 Table 7 3 on page 14 shows EEPROM memory organization for the XMEGA 1 devices EEPROM write and erase operations can be performed one page or one byte at the time while reading the EEPROM is done one byte at the time For EEPROM access the NVM Address Register A
61. l It can be used as system clock source or as asynchronous clock source for the Real Time Counter 0 4 16 MHz Crystal Oscillator The 0 4 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and crystals ranging from 400 kHz to 16 MHz 2 MHz Run time Calibrated Internal Oscillator The 2 MHz Run time Calibrated Internal Oscillator is a high frequency oscillator It is calibrated during protection to provide a default frequency which is close to its nominal frequency The oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a source for calibrating the frequency run time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator 32 MHz Run time Calibrated Internal Oscillator The 32 MHz Run time Calibrated Internal Oscillator is a high frequency oscillator It is calibrated during protection to provide a default frequency which is close to its nominal frequency The oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a source for calibrating the frequency run time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator External Clock input The external clock input gives the possibility to connect a clock from an external source PLL with Multiplication factor 2 31x The PLL provides the possibility of multiplying a frequency by any number fr
62. ltaneously PORTC PORTD PORTE and PORTF each has one SPI Notation of these peripherals SPIC SPID SPIE and SPIF respectively AMEL 21 USART 21 1 Features 21 2 Overview 8067 05 08 Eight Identical USART peripherals Full Duplex Operation Independent Serial Receive and Transmit Registers Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High resolution Arithmetic Baud Rate Generator Supports Serial Frames with 5 6 7 8 or 9 Data Bits and 1 or 2 Stop Bits Odd or Even Parity Generation and Parity Check Supported by Hardware Data OverRun Detection Framing Error Detection Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete TX Data Register Empty and RX Complete Multi processor Communication Mode Double Speed Asynchronous Communication Mode Master SPI mode for SPI communication IrDA support through the IRCOM module The Universal Synchronous and Asynchronous serial Receiver and Transmitter USART is a highly flexible serial communication module The USART supports full duplex communication and both asynchronous and clocked synchronous operation The USART can also be set in Master SPI mode to be used for SPI communication Communication is frame based and the frame format can be customized to support a wide range of standards The USART is buffered in both direction enabling continued data tr
63. mable Watchdog Timer with seperate Internal Oscillator accurate inter nal oscillators with PLL and prescaler and programmable Brown Out Detection The Program and Debug Interface PDI a fast 2 pin interface for programming and debugging is available The devices also have an IEEE std 1149 1 compliant JTAG test interface and this can also be used for On chip Debug and programming The XMEGA A1 devices have five software selectable power saving modes The Idle mode stops the CPU while allowing the SRAM DMA Controller Event System Interrupt Controller and all peripherals to continue functioning The Power down mode saves the SRAM and register contents but stops the oscillators disabling all other functions until the next TWI or pin change interrupt or Reset In Power save mode the asynchronous Real Time Counter continues to run allowing the application to maintain a timer base while the rest of the device is sleeping In Standby mode the Crystal Resonator Oscillator is kept running while the rest of the device is sleeping This allows very fast start up from external crystal combined with low power consump tion In Extended Standby mode both the main Oscillator and the Asynchronous Timer continue to run To further reduce power consumption the peripheral clock to each individual peripheral can optionally be stopped in Active mode and Idle sleep mode The device is manufactured using Atmel s high density nonvolatile memory technology The p
64. n EEPROM other interrupts should be disabled and the device put to sleep AMEL 36 Datasheet Revision History 36 1 8067C 05 08 36 2 8067 05 08 8067 05 08 amp o o 17 18 Updated the Front page and Features on page 1 Updated the DC Characteristics on page 62 Updated Figure 3 1 on page 5 Added Flash and EEPROM Page Size on page 14 Updated Table 33 2 on page 65 with new data Gain Error Offset Error and Signal to Noise Ratio SNR Updated Errata 128 1 rev on page 70 Updated Pinout Block Diagram on page 2 and Pinout and Pin Functions on page 48 Added XMEGA A1 Block Diagram Figure 3 1 on page 5 Updated Overview on page 4 included the XMEGA A1 explanation text on page 6 Updated AVR CPU Features on page 7 Updated Event System block diagram Figure 9 1 on page 17 Updated Updated Updated Updated Updated Updated Updated PMIC Programmable Multi level Interrupt Controller on page 24 AC Analog Comparator on page 43 Alternate Pin Function Description on page 48 Alternate Pin Functions on page 50 Typical Characteristics TBD on page 69 Ordering Information on page 2 Overview on page 4 Updated Figure 6 1 on page 7 Inserted a new Figure 15 1 on page 31 Updated Speed grades in Speed on page 64 Added a new ATxmega38
65. nabled The Brown out threshold voltage is programmable AMEL 2 12 3 5 JTAG reset The is reset as long as there is a logic one in Reset Register of the scan chains of the JTAG system Refer to IEEE 1149 1 JTAG Boundary scan for details 12 3 6 PDI reset The MCU can be reset through the Program and Debug Interface PDI 12 3 7 Software reset The MCU can be reset by the CPU writing to a special I O register through a timed sequence 12 4 WDT Watchdog Timer 12 4 1 Features 11 selectable timeout periods from 8 ms to 8s Two operation modes Standard mode Window mode Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator Configuration lock to prevent unwanted changes 12 4 2 Overview The XMEGA A1 has a Watchdog Timer WDT The WDT will run continuously when turned on and if the Watchdog Timer is not reset within a software configurable time out period the micro controller will be reset The Watchdog Reset WDR instruction must be run by software to reset the WDT and prevent microcontroller reset The WDT has a Window mode In this mode the WDR instruction must be run within a specified period called a window Application software can set the minimum and maximum limits for this window If the WDR instruction is not executed inside the window limits the microcontroller will be reset A protection mechanism using a timed write sequence is implemented in order to prevent unwante
66. nd the offset address for specific interrupts in each peripheral The base addresses for the XMEGA A1 devices are shown in Table 13 1 Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA A manual For peripherals or modules that have only one inter rupt the interrupt vector is shown in Table 13 1 The program address is the word address Table 13 1 gt Reset and Interrupt Vectors 8067 05 08 Program Address Base Address Source Interrupt Description 0x000 RESET 0x002 OSCF INT vect Crystal Oscillator Failure Interrupt vector NMI 0x004 INT base Port C Interrupt base 0x008 PORTR INT base Port R Interrupt base 0x00C DMA_INT_base DMA Controller Interrupt base 0x014 RTC_INT_base Real Time Counter Interrupt base 0x018 TWIC_INT_base Two Wire Interface on Port C Interrupt base 0x01C TCCO INT base Timer Counter 0 on port C Interrupt base 0x028 TCC1 INT base Timer Counter 1 on port C Interrupt base 0x030 SPIC INT vect SPI on port C Interrupt vector 0x032 USARTCO INT base USART 0 on port C Interrupt base 0x038 USARTC1 INT base USART 1 on port C Interrupt base OxO3E AES INT vect AES Interrupt vector AMEL Table 13 1 Reset and Interrupt Vectors Continued Program Address Base Address Source Interrupt Description 0
67. ne bit of the con version result at a time The ADC has a pipeline architecture This means that a new analog voltage can be sampled and a new ADC measurement started on each ADC clock cycle Each sample will be converted in the pipeline where the total sample and conversion time is seven ADC clock cycles for 12 bit result and 5 ADC clock cycles for 8 bit result ADC measurements can be started by application software or an incoming event from another peripheral in the device Four different result registers with individual channel selection MUX registers are provided to make it easier for the application to keep track of the data It is also possible to use DMA to move ADC results directly to memory or peripherals Both internal and external analog reference voltages can be used A very accurate internal 1 0V reference is available AMEL 1 Figure 24 1 ADC overview Channel A MUX selection Channel B MUX selection Channel C MUX selection Channel D MUX selection Configuration Channel A Reference selection Register Internal inputs Channel B Register Channel C Register Pin inputs Channel D Register Event Trigger Pin inputs Each ADC has four MUX selection registers with a corresponding result register This means that four channels can be sampled within 1 5 without any intervention b
68. nected to In addition the waveform generator output from Compare Channel A can be dis tributed to and override all port pins When the Pattern Generator unit is enabled the DTI unit is bypassed The Fault Protection unit is connected to the Event System This enables any event to trigger a fault condition that will disable the AWEX output Several event channels can be used to trigger fault on several different conditions The AWEX is available for TCCO and TCEO The notation of these peripherals are AWEXC and AWEXE AMEL s 17 Hi Res Resolution Extension 17 1 Features 17 2 Overview 8067 05 08 Increases Waveform Generator resolution by 2 bits 4 Supports Frequency single and dual slope PWM operation Supports the AWEX when this is enabled and used for the same Timer Counter The Hi Resolution Hi Res Extension is able to increase the resolution of the waveform genera tion output by a factor of 4 When enabled for a Timer Counter the Fast Peripheral clock running at four times the CPU clock speed will be as input to the Timer Counter The High Resolution Extension can also be used when an AWEX is enabled and used with a Timer Counter A1 devices have four Hi Res Extensions that each can be enabled for each Timer Counters pair on PORTC PORTD PORTE and PORTF The notation of these peripher als are HIRESC HIRESD HIRESE and HIRESF respectively AMEL 18 16 bit Real
69. o Wire Interface on port D 0x04A0 TWIE Two Wire Interface on port E 0 04 0 Two Wire Interface 0 0600 0 0620 0 0640 0 0660 Port D 0x0680 PORTE Port E 0x06A0 PORTF Port F 0 06 0 0 0700 PORTJ Port J 0x0720 PORTK Port K 0 07 0 0x07E0 PORTR R 0x0800 TCCO Timer Counter 0 on port C 0x0840 TCC1 Timer Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTCO USART 0 on port C 0 08 0 USARTC1 USART 1 on port C 0 08 0 SPIC Serial Peripheral Interface on port C Infrared Communication Module 0x0900 TCDO Timer Counter 0 on port D 0x0940 TCD1 Timer Counter 1 on port D 0x0990 HIRESD High Resolution Extension on port D 0x09A0 USARTDO USART 0 on port D 0x09B0 USARTD1 USART 1 on port D 0 09 0 SPID Serial Peripheral Interface on port D 0 0 00 Timer Counter 0 on E AMEL 54 Base Address Name Description 0 0 40 1 Timer Counter 1 on E 0x0A80 AWEXE Advanced Waveform Extension on port E 0x0A90 HIRESE High Resolution Extension on port E USARTEO USART 0 on port E USARTE1 USART 1 on port E SPIE Serial Peripheral Interface on port E 0 0 00 Timer Counter
70. o pin 7 The ports implement several functions including synchronous asyn chronous input sensing pin change interrupts and configurable output settings All functions are individual per pin but several pins may be configured in a single operation 14 3 configuration port pins Pn have programmable output configuration In addition all port pins have inverted I O function For an input this means inverting the signal between the port pin and the pin register For an output this means inverting the output signal between the port register and the port pin The inverted I O function can be used also when the pin is used for alternate func tions The port pins also have configurable slew rate limitation to reduce electromagnetic emission AMEL 29 8067 05 08 1 1431 Push pull Figure 14 1 configuration Totem pole DIRn OUTn gt Pn INn 14 3 2 Pull down Figure 14 2 configuration Totem pole with pull down on input DIRn OUTn X Pn INn lt lt 14 3 3 Pull up Figure 14 3 configuration Totem pole with pull up on input DIRn OUTn lt lt bus keeper s weak output produces the same logical level the last output level It acts as a pull up if the last level was 1 and pull down if the last level was 0 Pn 14 3 4 Bus keeper AMEL
71. oding decoding for that USART AMEL 23 23 1 Features 23 2 Overview 8067 05 08 Data Encryption Standard DES CPU instruction Advanced Encryption Standard AES Crypto module DES Instruction Encryption and Decryption Single cycle DES instruction Encryption Decryption in 16 clock cycles per 8 byte block AES Crypto Module Encryption and Decryption Support 128 bit keys Support XOR data load mode to the State memory for Cipher Block Chaining Encryption Decryption in 375 clock cycles per 16 byte block The Advanced Encryption Standard AES and Data Encryption Standard DES are two com monly used encryption standards These are supported through an AES peripheral module and a DES CPU instruction All communication interfaces and the CPU can optionally use AES and DES encrypted communication and data storage DES is supported by a DES instruction in the AVR XMEGA CPU The 8 byte key and 8 byte data blocks must be loaded into the Register file and then DES must be executed 16 times to encrypt decrypt the data block The AES Crypto Module encrypts and decrypts 128 bit data blocks with the use of a 128 bit key The key and data must be loaded into the key and state memory in the module before encryp tion decryption is started It takes 375 peripheral clock cycles before the encryption decryption is done and decrypted encrypted data can be read out and an optional
72. om 2 to 31 In com bination with the prescalers this gives a wide range of output frequencies from all clock sources AMEL 20 11 Power Management and Sleep Modes 11 1 Features 11 2 Overview 11 3 Sleep Modes 11 3 1 11 3 2 11 3 3 11 3 4 11 3 5 Idle Mode 5 sleep modes Idle Power down Power save Standby Extended standby Power Reduction registers to disable clocks to unused peripherals The 1 provides various sleep modes tailored to reduce power consumption to a mini mum All sleep modes are available and can be entered from Active mode In Active mode the CPU is executing application code The application code decides when and what sleep mode to enter Interrupts from enabled peripherals and all enabled reset sources can restore the micro controller from sleep to Active mode In addition Power Reduction registers provide a method to stop the clock to individual peripher als from software When this is done the current state of the peripheral is frozen and there is no power consumption from that peripheral This reduces the power consumption in Active mode and Idle sleep mode In Idle mode the CPU and Non Volatile Memory are stopped but all peripherals including the Interrupt Controller Event System and DMA Controller are kept running Interrupt requests from all enabled interrupts will wake the device Power down Mode In Power down mode all system clock sources
73. ose pins 2 Programmable Watchdog Timer with Separate Ultra Low Power Oscillator Preli minary Special Microcontroller Features Power on Reset and Programmable Brown out Detection Internal and External Clock Options with PLL and Prescaler Programmable Multi level Interrupt Controller Sleep Modes Idle Power down Standby Power save Extended Standby Advanced Programming Test and Debugging Interfaces JTAG IEEE 1149 1 Compliant Interface for programming test and debugging PDI Program and Debug Interface for programming and debugging and Packages 78 Programmable I O Lines 100 lead TQFP 100 ball CBGA Operating Voltage 1 6 3 6V Speed performance 0 12 MHz Q 1 6 3 6V 0 32 MHz 2 7 3 6V Typical Applications Industrial control Factory automation Building control Board control White Goods Climate control ZigBee Motor control Networking Optical Hand held battery applications Power tools HVAC Metering Medical Applications 8067 05 08 AMEL 1 Ordering Information Ordering Code Flash B E B SRAM B Speed MHz Power Supply Package 9 Temp ATxmega384A1 AU 384K 4K 32K 32 1 6 3 6V ATxmega256A1 AU 256K 4 8K 4K 16K 32 1 6 3 6V 192 1 192 8 2K 16K 32 1 6 3 6V 100A ATxmega128A1 AU 128 8K 2K 8K 32 1 6 3 6V ATxmega64A1 AU 64K
74. ower ULP oscillator External clock options 0 4 16 MHz Crystal Oscillator 32 kHz Crystal Oscillator External clock PLL with internal and external clock options with 2 to 31x multiplication Clock Prescalers with 2 to 2048x division Fast peripheral clock running at 2 and 4 times the CPU clock speed Automatic Run Time Calibration of internal oscillators Crystal Oscillator failure detection 10 2 Overview XMEGA 1 has an advanced clock system supporting a large number of clock sources It incor porates both integrated oscillators external crystal oscillators and resonators A high frequency Phase Locked Loop PLL and clock prescalers can be controlled from software to generate a wide range of clock frequencies from the clock source input It is possible to switch between clock sources from software during run time After reset the device will always start up running from the 2 Mhz internal oscillator A calibration feature is available and can be used for automatic run time calibration of the inter nal 2 MHz and 32 MHz oscillators This reduce frequency drift over voltage and temperature A Crystal Oscillator Failure Monitor can be enabled to issue a Non Maskable Interrupt and switch to internal oscillator if the external oscillator fails Figure 10 1 on page 19 shows the prin cipal clock system in XMEGA 1 AMEL 8067 05 08 18 1 Figure 10 1 Clock system overview Clkuip 32
75. r down mode ULP WDT Sampled BOD 1 8 1 1 Enabled Voc 3 3V 1 5 ULP RTC WDT BOD 1 8V 1 1 Enabled 3 3V 1 5 OUO Enabled Voc 1 8V 650 1 kHz from Low Power nA TOSC32 3 3V 650 Note 1 Max means the highest value where the pin is guaranteed to be read as low 2 Min means the lowest value where the pin is guaranteed to be read as high AIMEL 63 NENNEN 8067 05 08 33 3 Speed The maximum frequency of the XMEGA 1 devices is depending on As shown in Figure 33 1 on page 64 the Frequency vs curve is linear between 1 8V lt lt 2 7V Figure 33 1 Maximum Frequency vs Vcc MHz 32 Safe Operating Area AMEL 8067 05 08 33 4 Characteristics Table 33 1 Characteristics Symbol Parameter Condition Min Typ Max Units Resolution 8 12 12 LSB Integral Non Linearity INL TBD LSB Differential Non Linearity DNL TBD LSB Gain Error TBD LSB Offset Error TBD LSB Conversion Time a ET 12 bit Result 3 5 us ADC Clock Frequency 100 2000 kHz AVCC DC Supply Voltage 1 6 3 6 Source Impedance 2 Msps sample rate 3 Start up time TBD us Vec 0 3 Voc 0 3 Table 33 2 ADC Gain Stage Chara
76. ro gram Flash memory can be reprogrammed in system through the PDI or JTAG A Bootloader running in the device can use any interface to download the application program to the Flash memory The Bootloader software in the Boot Flash section will continue to run while the Appli cation Flash section is updated providing true Read While Write operation By combining an 8 16 bit RISC CPU with In System Self Programmable Flash the Atmel XMEGA A1 is a power ful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications The 1 devices is supported with a full suite of program and system development tools including C compilers macro assemblers program debugger simulators programmers and evaluation kits AMEL s 1 31 Block Diagram Figure 3 1 Block Diagram PR O 1 PQ O 3 XTAL
77. s This device data sheet only contains part specific information and a short description of each peripheral and module The XMEGA A Manual describes the modules and peripherals in depth The XMEGA A application notes contain example code and show applied use of the modules and peripherals The XMEGA A Manual and Application Notes are available from http www atmel com avr 5 Disclaimer For devices that are not available yet typical values contained in this datasheet are based on simulations and characterization of other AVR XMEGA microcontrollers manufactured on the same process technology Min and Max values will be available after the device is characterized AMEL 8067 05 08 6 AVR CPU 6 1 Features 6 2 Overview 8067 05 08 8 16 bit high performance AVR RISC Architecture 138 instructions Hardware multiplier 32x8 bit registers directly connected to the ALU Stack in SRAM Stack Pointer accessible memory space Direct addressing of up to 16M Bytes of program and data memory True 16 24 bit access to 16 24 bit I O registers Support for 8 16 and 32 bit Arithmetic Configuration Change Protection of system critical features The XMEGA 1 uses the 8 16 bit AVR CPU The main function of the CPU is program execu tion The CPU must therefore be able to access memories perform calculations and control peripherals Interrupt handling is described in a separate section Figure 6 1 on page 7
78. sed to realize a window function One pair of analog comparators is shown in Figure 26 1 on page 44 Input selection from Pin 0 1 2 3 4 5 6 selectable to positive input of analog comparator Pin 0 1 3 5 7 selectable to negative input of analog comparator Internal signals available on positive analog comparator inputs Output from 12 bit DAC Internal signals available on negative analog comparator inputs 64 level scaler of the VCC available on negative analog comparator input Bandgap voltage reference Output from 12 bit DAC 26 4 Window Function The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 26 2 Figure 26 2 Analog comparator window function Upper limit of windo Interrupt Interrupts sensitivity control Input signal Events Lower limit of window AMEL a 8067 05 08 27 OCD On chip Debug 27 1 Features Complete Program Flow Control Go Stop Reset Step into Step over Step out Run to Cursor Debugging and high level language source code level Debugging on Assembler and disassembler level 1 dedicated program address or source level breakpoint for AVR Studio debugger 4 Hardware Breakpoints Unlimited Number of User Program Breakpoints Unlimited Number of User Data Breakpoints with break on Data location read write or both read and write Data loca
79. shows the CPU block diagram Figure 6 1 block diagram lt DATA BUS Flash Program Program 32 x 8 General Purpose Instruction Registers OCD Register STATUS Instruction CONTROL gt Decode Y Y Y Multiplier ALU DES DATA BUS gt Peripheral Peripheral Module 1 Module 2 SRAM EEPROM PMIC The AVR uses a Harvard architecture with separate memories and buses for program and data Instructions in the program memory are executed with a single level pipeline While one instruction is being executed the next instruction is pre fetched from the program memory This AMEL 7 6 3 Register File concept enables instructions to be executed in every clock cycle The program memory is In System Self Programmable Flash memory The fast access Register File contains 32 x 8 bit general purpose working registers with single clock cycle access time This allows single cycle Arithmetic Logic Unit ALU operation In a typ ical ALU cycle the operation is performed on two Register File operands and the result is stored back in the Register File Six of the 32 registers can be used as three 16 bit address register pointers for data space addressing enabling efficient address calculations One of these address pointers can
80. shows which modules on peripherals that enables alternate functions on a pin and what alternate functions that is available on a pin AMEL 2 8067 05 08 15 16 bit Timer Counter 15 1 Features 15 2 Overview 8067 05 08 Eight 16 bit Timer Counters Four Timer Counters of type 0 Four Timer Counters of type 1 Four Compare or Capture CC Channels Timer Counter 0 Two Compare or Capture CC Channels in Timer Counter 1 Double Buffered Timer Period Setting Double Buffered Compare or Capture Channels Waveform Generation Single Slope Pulse Width Modulation Dual Slope Pulse Width Modulation Frequency Generation Input Capture Input Capture with Noise Cancelling Frequency capture Pulse width capture 32 bit input capture Event Counter with Direction Control Timer Overflow and Timer Error Interrupts and Events One Compare Match or Capture Interrupt and Event per CC Channel Supports DMA Operation Hi Resolution Extension Hi Res Advanced Waveform Extension AWEX XMEGA 1 has eight Timer Counters four Timer Counter 0 and four Timer Counter 1 The dif ference between them is that Timer Counter 0 has four Compare Capture channels while Timer Counter 1 has two Compare Capture channels The Timer Counters T C are 16 bit and can count any clock event or external input in the microcontroller A programmable prescaler is available to get a useful T C resolution Updates
81. t 7 lt 7 1 20 Z q Rr Store Indirect with Displacement Z q lt Rr None 20 Load Program Memory RO Z None 3 LPM Rd Z Load Program Memory Rd lt Z 3 LPM Rd 2 Load Program Memory and Post Increment Rd lt Z 3 2 lt 2 1 ELPM Extended Load Program Memory RO lt RAMPZZ 3 ELPM Rd Z Extended Load Program Memory Rd lt RAMPZZ None 3 ELPM Rd 2 Extended Load Program Memory and Post Rd lt 2 2 None 3 Increment 2 lt 241 Store Program Memory RAMPZZ lt R1 RO None SPM 2 Store Program Memory and Post Increment RAMPZZ lt Rt RO None by 2 Z lt 7 2 In From Location Rd O A None 1 OUT A Rr Out To Location lt Rr None 1 PUSH Rr Push Register on Stack STACK e Rr None 10 Pop Register Stack Rd lt STACK None 20 Bit and Bit test Instructions LSL Rd Logical Shift Left 1 lt Z C N V H 1 lt 0 C lt 4 LSR Rd Logical Shift Right Rd n 1 Z C N V 1 Rd7 lt 0 Rd 0 AMEL 58 E lt Mnemonics Operands Description Operation Flags Clocks ROL Rd Rotate Left Through Carry lt Z C N V H 1 Rd n 1 lt C lt 7 Rotate Right Through Carry lt 2 1 lt C lt Rd 0
82. tion content equal or not equal to a value Data location content is greater or less than a value Data location content is within or outside a range Bits of a data location are equal or not equal to a value Non Intrusive Operation No hardware or software resources in the device are used High Speed Operation No limitation on debug programming clock frequency versus system clock frequency 27 2 Overview The XMEGA A1 has a powerful On Chip Debug OCD system that in combination with Atmel s development tools provides all the necessary functions to debug an application It has support for program and data breakpoints and can debug an application from C and high level language source code level as well as assembler and disassembler level It has full Non Intrusive Opera tion and no hardware or software resources in the device are used The ODC system is accessed through an external debugging tool which connects to the JTAG or PDI physical inter faces Refer to Program and Debug Interfaces on page 47 AMEL a 8067 05 08 28 Program and Debug Interfaces 28 1 Features PDI Program and Debug Interface Atmel proprietary 2 pin interface JTAG Interface IEEE std 1149 1 compliant Boundary scan capabilities according to the IEEE Std 1149 1 JTAG Access to the OCD system Programming of Flash EEPROM Fuses and Lock Bits 28 2 Overview The programming and debug facilities are accessed through
83. x040 NVM_INT_base Non Volatile Memory Interrupt base 0x044 PORTB_INT_base Port B Interrupt base 0x048 ACB_INT_base Analog Comparator on Port B Interrupt base 0 04 ADCB INT base Analog to Digital Converter on Port B Interrupt base 0x056 PORTE INT base Port E Interrupt base 0x05A TWIE INT base Two Wire Interface on Port E Interrupt base 0 05 Timer Counter 0 on Interrupt base 0x06A TCE1 INT base Timer Counter 1 on port E Interrupt base 0x072 SPIE INT vect SPI on port E Interrupt vector 0x074 USARTEO INT base USART 0 on port E Interrupt base 0x07A USARTE1 INT base USART 1 on port E Interrupt base 0x080 PORTD INT base Port D Interrupt base 0x084 PORTA INT base Port A Interrupt base 0x088 ACA INT base Analog Comparator on Port A Interrupt base ADCA INT base Analog to Digital Converter on Port A Interrupt base 0x096 TWID INT base Two Wire Interface on Port D Interrupt base 0x09A TCDO INT base Timer Counter 0 on port D Interrupt base 0x0A6 TCD1 INT base Timer Counter 1 on port D Interrupt base OxOAE SPID INT vector SPI on port D Interrupt vector 0 0 0 USARTDO INT base USART 0 on port D Interrupt base 0x0B6 USARTD1 INT base USART 1 on port D Interrupt base OxOBC PORTO INT Port Q INT base 0 0 4 PORTJ INT Port J INT base 0 0 PORTK INT base Port K INT base
84. y the application other than starting the conversion The results will be available in the result registers The ADC may be configured for 8 or 12 bit resolution reducing the minimum conversion time propagation delay from 3 5 us for 12 bit to 2 5 us for 8 bit resolution ADC conversion results are provided left or right adjusted with optional 1 or 0 padding This eases calculation when the result is represented as a signed integer signed 16 bit number PORTA and PORTB each has one ADC Notation of these peripherals are ADCA and ADCB respectively AMEL a 8067 05 08 25 DAC 12 bit Digital to Analog Converter 25 1 Features 25 2 Overview 8067 05 08 Two DACs with 12 bit resolution Up to 1 Msps conversion rate for each DAC Flexible conversion range Multiple trigger sources 1 continuous output or 2 Sample and Hold S H outputs for each DAC Built in offset and gain calibration High drive capabilities Low Power Mode The 1 devices features two 12 bit 1 DACs with built in offset and gain calibra tion see Figure 25 1 on page 42 A DAC converts a digital value into an analog signal The DAC may use an internal 1 1 voltage as the upper limit for conversion but it is also possible to use the supply voltage or any applied voltage in between The external reference input is shared with the ADC reference input Figure 25 1 DAC overview Configuration Ref

ATMEL Atmel AVR micro controller ATxmega64A1 English handbook

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