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ATMEL Atmel AVR micro controller ATtiny28L handbook

1. Mnemonic Operands Description Operation Flags 4 Clocks DATA TRANSFER INSTRUCTIONS LD Rd Z Load Register Indirect Rd Z None 2 ST Z Rr Store Register Indirect Z lt Rr None 2 MOV Rd Rr Move between Registers Rd Rr None 1 LDI Rd K Load Immediate Rd K None 1 IN Rd P In Port Rd P None 1 OUT P Rr Out Port P lt Rr None 1 LPM Load Program Memory RO Z None 3 BIT AND BIT TEST INSTRUCTIONS SBI P b Set Bit in I O Register O P b None 2 CBI P b Clear Bit in I O Register O P b 0 None 2 LSL Rd Logical Shift Left Rd n 1 Rd n Rd 0 0 Z C N V 1 LSR Rd Logical Shift Right Rd n Rd n 1 Rd 7 0 Z C N V 1 ROL Rd Rotate Left through Carry Rd 0 C Rd n 1 Rd n C Rd 7 ZC NV 1 ROR Rd Rotate Right through Carry Rd 7 C Rd n Rd n 1 C Rd 0 Z C N V 1 ASR Rd Arithmetic Shift Right Rd n Rd n 1 n 0 6 Z C N V 1 SWAP Rd Swap Nibbles Rd 3 0 Rd 7 4 Rd 7 4 Rd 3 0 None 1 BSET s Flag Set SREG s 1 SREG s 1 BCLR s Flag Clear SREG s 0 SREG s 1 BST Rr b Bit Store from Register to T TE Rr b T 1 BLD Rd b Bit Load from T to Register Rd b T None 1 SEC Set Carry Cei C 1 CLC Clear Carry C 0 C 1 SEN Set Negative Flag Nei N 1 CLN Clear Negative Flag N O N 1 SEZ Set Zero Flag Z lt 1 Z 1 CLZ Clear Zero Flag Z lt 0 Z 1 SEI Global Interrupt Enable le 1 l 1 CLI Global Interrupt Disable 1 lt 0 l 1 SES
2. 120 Ta 25 C IL 100 EE Ta 85C 80 T i 60 o 40 20 0 0 0 5 1 1 5 2 25 3 3 5 4 45 5 Vop V Figure 58 Pull up Resistor Current vs Input Voltage Voc 2 7V 30 Ta 25 C ep JL Ta 85C 20 lop HA AMEL 1062F AVR 07 06 AMEL Figure 59 UO Pin Sink Current vs Output Voltage All pins except PA2 Voc 5V 70 Ta 25 C 60 Ta 8s o 50 a V o 30 mA B o 0 0 5 1 1 5 2 2 5 3 Vol V Figure 60 O Pin Source Current vs Output voltage Vee 5V lon mA 66 ATtiny28L V mem 1062F AVR 07 06 ATtiny28L V Figure 61 I O Pin Sink Current vs Output Voltage All Pins Except PA2 Vec 2 7V 20 P sal Ta 85 C 15 lt E 2 10 5 0 0 0 5 1 1 5 2 Vor V 6 TA 25 C TA 85C lou mA AMEL e 1062F AVR 07 06 AMEL Figure 63 PA2 I O Pin Sink Current vs Output Voltage High Current Pin PA2 T 25 C Voc 3 6V lou mA Vol V Figure 64 I O Pin Input Threshold Voltage vs Vcc Ta 25 C 2 5 2 1 5 S Z E 1 9 E 0 5 0 2 7 4 0
3. COMMON DIMENSIONS Unit of Measure mm SYMBOL NOM MAX A 4 5724 A1 34 798 8 255 7 493 0 533 1 397 Note 1 Dimensions D and E1 do not include mold Flash or Protrusion Mold Flash or Protrusion shall not exceed 0 25 mm 0 010 1 143 3 429 0 356 10 160 2 540 TYP 09 28 01 TITLE DRAWING NO REV 2325 Orchard Parkway v 28P3 28 lead 0 300 7 62 mm Wide Plastic Dual AMEL San Jose CA 95131 Inline Package PDIP AMEL 7 1062F AVR 07 06 AMEL 32M1 A TOP VIEW BOTTOM VIEW Note JEDEC Standard MO 220 Fig 2 Anvil Singulation VHHD 2 TITLE COMMON DIMENSIONS Unit of Measure mm NOM 0 90 MAX 1 00 0 02 0 05 0 65 1 00 0 20 REF 0 23 0 30 5 00 4 75 5 10 4 80 3 10 3 25 5 00 5 10 4 75 4 80 3 10 0 50 BSC 0 40 5 25 06 DRAWING NO REV AMEL cla jud 32M1 A 32 pad 5 x 5 x 1 0 mm Body Lead Pitch 0 50 mm eno 9513 3 10 mm Exposed Pad Micro Lead Frame Package MLF ATtiny28L V 1062F AVR 07 06 Errata All revisions No known errata AMEL 7 1062F AVR 07 06 Datasheet Revision History AMEL Please note that the referring page numbers in this section are referred to this docu ment The referring revision in th
4. Crystal Resonator Carrier Error in ONTIM MCONF Frequency Frequency Frequency Duty cycle Value Value 2 MHz 455 kHz 9 9 50 1 001 2 4576 MHz 455 kHz 10 0 33 1 010 2 4576 MHz 455 kHz 10 0 50 2 001 3 2768 MHz 455 kHz 10 0 25 1 011 3 2768 MHz 455 kHz 10 0 50 3 001 3 64 MHz 455 kHz 0 0 25 1 011 3 64 MHz 455 kHz 0 0 50 3 001 4 MHz 455 kHz 9 9 25 1 011 4 MHz 455 kHz 9 9 50 3 001 ATtiny28L V mem 1062F AVR 07 06 Register Description Modulation Control Register MODCR Bit Read Write Initial Value e Bits 7 3 ONTIM4 0 Modulation On time 6 0 0 5 4 0 0 3 2 0 0 1 0 7 RW R W R W R W R W R W R W R W 0 0 This 5 bit value 1 determines the number of clock cycles the output pin PA2 is active low e Bits 2 0 MCONF2 0 Modulation Configuration Bits 2 1 and 0 These three bits determine the relationship between the on and off times of the modu lator and thereby the duty cycle The various settings are shown in Table 18 The minimum and maximum modulation period is also shown in the table The minimum modulation period is obtained by setting ONTIM to zero while the maximum period is obtained by setting ONTIM to 31 The configuration values for some common oscillator and carrier frequencies are listed in Table 17 The relationship between oscillator fre quency and carrier frequency is fcarrier fosc On time Off time If the MCONF register
5. Ta 25 0 18 16 Voc 6 0V LH 14 Vec 5 5V L J LN 12 Vec 5 0V 10 E py D es Vcc 4 5V o 8 Pag Vee 4 0V 7a GC ES E ees agi Voc 3 6V Lee LL Noo 3 3V AA IL CU Tl Naa j er ee sue pe eee Vec 27V eg Vcc 2 4V o LEE Veo 2 1V Voc 1 8V 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Frequency MHz AMEL s 58 AMEL Figure 43 Active Supply Current vs Voc Icc mA ACTIVE SUPPLY CURRENT vs Vcc FREQUENCY 4 MHz Ta 25 C Ta 85 C 1 5 2 5 3 3 5 4 4 5 5 5 5 6 Figure 44 Active Supply Current vs Vcc Device Clocked by Internal Oscillator mA ACTIVE SUPPLY CURRENT vs Vec DEVICE CLOCKED BY 1 2MHz INTERNAL RC OSCILLATOR 15 T 25 C TJ 85 C 2 5 3 3 5 4 45 5 5 5 6 ATtiny28L V mem 1062F AVR 07 06 Figure 45 Active Supply Current vs Vcc Device Clocked by External 32 kHz Crystal ACTIVE SUPPLY CURRENT vs Vcc DEVICE CLOCKED BY 32 kHz CRYSTAL 3 5 Ta 25 C 3 Ta 85 C 2 5 T E 2 8 1 5 j 0 5 sila 0 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 Voc V Figure 46 Idle Supply Current vs Frequency IDLE SUPPLY CURRENT vs FREQUENCY Ta 25 C 45 Vee 6 0V de Vee 5 5V p Vee 5 0V
6. TOVO FOVO ATtiny28L V 1062F AVR 07 06 Port B Port B as General Digital Input Alternate Functions of Port B 1062F AVR 07 06 Port B is an 8 bit input port One I O address location is allocated for the Port B Input Pins PINB 516 The Port B Input Pins address is read only All port pins have pull ups that can be switched on for all Port B pins simultaneously If any of the Port B special functions is enabled the corresponding pull up s is disabled When pins PBO to PB7 are externally pulled low they will source current l if the inter nal pull up resistors are activated The Port B pins with alternate functions are shown in Table 11 Table 11 Port B Pin Alternate Functions Port Pin Alternate Functions PBO AINO Analog Comparator Positive Input PB1 AIN1 Analog Comparator Negative Input PB2 TO Timer Counter 0 External Counter Input PB3 INTO External Interrupt O Input PB4 INT1 External Interrupt 1 Input All eight pins in Port B have equal functionality when used as digital input pins PBn general input pin To switch the pull up resistors on the PLUPB bit in the MCUCS register must be set one This bit controls the pull up on all Port B pins To turn the pull ups off this bit has to be cleared zero Note that if any Port B pins are used for alternate functions the pull up on the corresponding pins are disabled The port pins are tri stated wh
7. 2 are popped one level in the stack If more than three subsequent subroutine calls or interrupts are executed the first val ues written to the stack are overwritten Figure 4 shows the structure of the 32 general purpose registers in the CPU Figure 4 AVR CPU General purpose Working Registers 7 0 General Purpose E Working R28 Registers R29 R30 Z Register low byte R31 Z Register high byte All the register operating instructions in the instruction set have direct and single cycle access to all registers The only exception are the five constant arithmetic and logic instructions SBCI SUBI CPI ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data These instructions apply to the second half of the registers in the register file R16 R31 The general SBC SUB CP AND OR and all other operations between two registers or on a single register apply to the entire register file Registers 30 and 31 form a 16 bit pointer the Z pointer which is used for indirect Flash memory and register file access When the register file is accessed the contents of R31 are discarded by the CPU AMEL s Status Register Status Register SREG AMEL The AVR status register SREG at I O space location 3F is defined as Bit T 6 5 4 3 2 1 0 sar TT Vv sss Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bit7 l Global
8. DATA 10 ADDR HIGH X ADDR LOW DATA LOW X XA1 ER j XAO CC RDY BSY RESET 12V OE AMEL s AMEL Figure 39 Programming the Flash Waveforms Continued DATA X DATA HIGH A XA1 XAO EE EN BS NL RDY BSY N y RESET 12V OE 52 ATtiny28L V mem 1062F AVR 07 06 ATtiny28L V Parallel Programming Figure 40 Parallel Programming Timing Characteristics txLwL XTAL1 Data amp Contol DATA XA0 1 BS E m Ss Write tRHBx pi lwLRH m BE NN o 3 Kor zz loupz E OLDV DATA Symbol Parameter Min Typ Max Unit Vpp Programming Enable Voltage 11 5 12 5 V Ipp Programming Enable Current 250 0 HA tovxH Data amp Control Valid before XTAL1 High 67 0 ns TXHXL XTAL1 Pulse Width High 67 0 ns txLDX Data amp Control Hold after XTAL1 Low 67 0 ns Kiwi XTAL1 Low to WR Low 67 0 ns Lou BS Valid to WR Low 67 0 ns tRHBX BS Hold after RDY BSY High 67 0 ns twiwH WR Pulse Width Low 67 0 ns twi pL WR Low to RDY BSY Low 0 0 2 5 us bau pu WD Low to RDY BSY High 0 5 0 7 0 9 ms Kol XTAL1 Low to OE Low 67 0 ns La OE Low to DATA Valid 20 0 ns toupz OE High to DATA Tri stated 20 0 ns AMEL 5 1062F AVR 07 06 AMEL Electrical Characteristics Absolute Maximum Ratings Operating Temperature 40 C to 85 105 C NOTICE Stresses beyond those ratings listed
9. Power on oh aa HI 100 500K ee Pte Watchdog Timer uiis uid On chip RC Oscillator Delay Counters si INTERNAL RESET COUNTER RESET CK Table 4 Reset Characteristics Parameter vila Power on Reset Threshold Voltage rising 1 0 1 4 1 8 V a Power on Reset Threshold Voltage falling 0 4 0 6 0 8 V Vast RESET Pin Threshold Voltage 0 6 Vcc V Note 1 The Power on Reset will not work unless the supply voltage has been below Vpor falling AMEL 1062F AVR 07 06 Power on Reset AMEL Table 5 ATtiny28 Clock Options and Start up Time CKSEL3 0 Clock Source Start up Time at 2 7V 1111 External Crystal Ceramic Resonator 1K CK 1110 External Crystal Ceramic Resonator 4 2 ms 1K CK 1101 External Crystal Ceramic Resonator 67 ms 1K CK 1100 External Crystal Ceramic Resonator 16K CK 1011 External Crystal Ceramic Resonator 4 2 ms 16K CK 1010 External Crystal Ceramic Resonator 67 ms 16K CK 1001 External Low frequency Crystal 67 ms 1K CK 1000 External Low frequency Crystal 67 ms 32K CK 0111 External RC Oscillator 6 CK 0110 External RC Oscillator 4 2ms 6CK 0101 External RC Oscillator 67 ms 6 CK 0100 Internal RC Oscillator 6 CK 0011 Internal RC Oscillator 4 2ms 6CK 0010 Internal RC Oscillator 67 ms 6 CK 0001 External Clock 6 CK 0000 External Clock 4 2ms 6CK Note 1 Due to limited n
10. For timing insensitive applications the external RC configuration shown in Figure 7 can External RC Oscillator be used For details on how to choose R and C see Table 25 on page 56 Figure 7 External RC Configuration Vcc A R NC XTAL2 e XTAL1 C e GND 8 ATtiny28L V mns Register Description Oscillator Calibration Register OSCCAL Bit 7 6 5 4 3 2 1 0 00 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CALO OSCCAL Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bits 7 0 CAL7 CALO Oscillator Calibration Value Writing the calibration byte to this address will trim the internal oscillator to remove pro cess variation from the oscillator frequency When OSCCAL is zero the lowest available frequency is chosen Writing non zero values to the register will increase the frequency to the internal oscillator Writing SFF to the register gives the highest available fre quency Table 2 shows the range for OSCCAL Note that the oscillator is intended for calibration to 1 2 MHz thus tuning to other values is not guaranteed At 3V and 25 C the pre programmed calibration byte gives a frequency within 1 of the nominal frequency Table 2 Internal RC Oscillator Range OSCCAL Value Min Frequency Max Frequency Ox00 0 6 MHZ 1 2 MHz Ox7F 0 8 MHz 1 7 MHz OxFF 1 2 MHz 2 5 MHz 1062F AVR 07 06 AMEL AMEL Me
11. The period of the Watchdog oscillator is 2 7 us nominal at 3 0V and 25 C The frequency of the watchdog oscillator is voltage dependent as shown in the section Typical Characteristics on page 57 When waking up from the Power down mode there is a delay from the wake up condi tion until the wake up becomes effective This allows the clock to restart and become stable after having been stopped 14 ATtiny28L V mem 1062F AVR 07 06 System Control and Reset Reset Sources The ATtiny28 provides three sources of reset e Power on Reset The MCU is reset when the supply voltage is below the Power on Reset threshold Vpo e External Reset The MCU is reset when a low level is present on the RESET pin for more than 50 ns e Watchdog Reset The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled During reset all I O registers are then set to their initial values and the program starts execution from address 000 The instruction placed in address 000 must be an RJMP relative jump instruction to the reset handling routine If the program never enables an interrupt source the interrupt vectors are not used and regular program code can be placed at these locations The circuit diagram in Figure 16 shows the reset logic Table 4 defines the timing and electrical parameters of the reset circuitry Figure 16 Reset Logic DATA BUS MCU Control and Status Register MCUCS o LD Q
12. j2 PA1 PD1 3 PAZ PD2 4 PA2 IR PD3 15 PB7 PD4 16 PB6 NG ls vec 7 GND vec 4 GND 8 NC GND LJ 5 XTAL1 VCC 6 XTA 7 XTAL2 PB5 oi PD5 PB4 INT1 PDE PB3 INT0 sas rsssse 55565864 AINO PBO PB1 AIN1 COOP ROD Sr Sr zzEEE JI Z2 PB7 PB6 NC GND NC NC VCC PB5 MAA 5 8 bit AVR Microcontroller with 2K Bytes of Flash ATtiny28L ATtiny28V Rev 1062F AVR 07 06 Description Block Diagram AMEL The ATtiny28 is a low power CMOS 8 bit microcontroller based on the AVR RISC archi tecture By executing powerful instructions in a single clock cycle the ATtiny28 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed The AVR core combines a rich instruction set with 32 general purpose working registers All the 32 registers are directly con nected to the Arithmetic Logic Unit ALU allowing two independent registers to be accessed in one single instruction executed in one clock cycle The resulting architec ture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers Figure 1 The ATtiny28 Block Diagram pum ERES F1 vcc and le 8 BIT DATA BUS E b m INTERNAL OSCILLATOR OSCILLA
13. resistors if configured as input Port A is a 4 bit I O port PA3 PA1 and PAO are bi directional while PA2 is output only Before entering Power down see Sleep Modes on page 14 PORTA2 bit in PORTA register should be set Three 1 0 memory address locations are allocated for Port A one each for the Data Register PORTA 1B Port A Control Register PACR 1A and the Port A Input Pins PINA 19 The Port A Input Pins address is read only while the Data Register and the Control Register are read write Compared to other output ports the Port A output is delayed one extra clock cycle Port pins PAO PA1 and PAS have individually selectable pull up resistors When pins PAO PAT or PAS are used as inputs and are externally pulled low they will source cur rent if the internal pull up resistors are activated PA2 is output only The PA2 output buffer can sink 25 mA and thus drive a high current LED directly This output can also be modulated see Hardware Modulator on page 39 for details PA3 PA1 and PAO are general I O pins The DDAn n 3 1 0 bits in PACR select the direction of these pins If DDAn is set one PAn is configured as an output pin If DDAn is cleared zero PAn is configured as an input pin If PORTAn is set one when the pin is configured as an input pin the MOS pull up resistor is activated To switch the pull up resistor off the PORTAn bit has to be cleared zero or the pin has to be configured as an outp
14. to the destination register Figure 15 Single Cycle ALU Operation T1 T2 T3 T4 Result Write Back A SV l 1 Flash Program Memory The ATtiny28 contains 2K bytes of on chip Flash memory for program storage Since all instructions are single 16 bit words the Flash is organized as 1K x 16 words The Flash memory has an endurance of at least 1 000 write erase cycles The ATtiny28 program counter is 10 bits wide thus addressing the 1K word Flash pro gram memory See Programming the Flash on page 47 for a detailed description of Flash data downloading AMEL 1 1062F AVR 07 06 Sleep Modes Idle Mode Power down Mode AMEL To enter the sleep modes the SE bit in MCUCS must be set one and a SLEEP instruc tion must be executed The SM bit in the MCUCS register selects which sleep mode Idle or Power down will be activated by the SLEEP instruction If an enabled interrupt occurs while the MCU is in a sleep mode the MCU awakes The CPU is then halted for four cycles It executes the interrupt routine and resumes execution from the instruction following SLEEP The contents of the register file and I O memory are unaltered If a reset occurs during sleep mode the MCU wakes up and executes from the Reset vector When the SM bit is cleared zero the SLEEP instruction forces the MCU into the Idle Mode stopping the CPU but allowing Timer Counters Watchdog and the interrupt sys tem to continue oper
15. 06 rupt on low level input feature enables the ATtiny28 to be highly responsive to external events still featuring the lowest power consumption while in the power down modes The device is manufactured using Atmel s high density nonvolatile memory technology By combining an enhanced RISC 8 bit CPU with Flash on a monolithic chip the Atmel ATtiny28 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications The ATtiny28 AVR is supported with a full suite of program and system development tools including macro assemblers pro gram debugger simulators in circuit emulators and evaluation kits Supply voltage pin Ground pin Port A is a 4 bit I O port PA2 is output only and can be used as a high current LED driver At Vcc 2 0V the PA2 output buffer can sink 25 mA PAS PA1 and PAO are bi directional I O pins with internal pull ups selected for each bit The port pins are tri stated when a reset condition becomes active even if the clock is not running Port B is an 8 bit input port with internal pull ups selected for all Port B pins Port B pins that are externally pulled low will source current if the pull ups are activated Port B also serves the functions of various special features of the ATtiny28 as listed on page 27 If any of the special features are enabled the pull up s on the corresponding pin s is automatically disabled The port pins are tri stated
16. 3V 2 3 V LL Input Leakage Current I O Pin Vec 5 5V pin low 8 0 HA absolute value LL Input Leakage Current I O Pin Voc 5 5V pin high 8 0 HA absolute value Ryo UO Pin Pull up 35 0 122 0 kQ Active Mode Vcc 3V 3 0 mA 4 MHz Idle Mode Ve 3V 1 0 1 2 mA e 4 MHz l Power Supply Current ka Power down90 Vog 3V 9 0 15 0 JA WDT enabled Power down9 Vee 3V 1 0 2 0 UA WDT disabled 54 ATti ny28 L V OLLLOLULL ZSbALLLAILODA O LO U OOe 1062F AVR 07 06 DC Characteristics Continued Ta 40 C to 85 C Voc 1 8V to 5 5V unless otherwise noted Symbol Parameter Condition Min Typ Max Units Vacio Analog Comparator Input Voc DM 40 0 mv Offset Voltage Vin Vec 2 lACLK Analog Comparator Input Voc 5V 50 0 50 0 nA Leakage Current Vin Voc 2 Tacpo Analog Comparator Vee 2 7V 750 0 ns Propagation Delay Voc 4 0V 500 0 Notes 1 Max means the highest value where the pin is guaranteed to be read as low 2 Min means the lowest value where the pin is guaranteed to be read as high 3 Although each I O port can sink more than the test conditions 20 mA at Vcc 5V 10 MA at Vec 3V under steady state conditions non transient the following must be observed 1 The sum of all lo for all ports should not exceed 300 MA 2 The sum of all lo for port DO D7 and XTAL2 should not exceed 100 mA If lo exceeds the test condition Vo may exceed the related specif
17. 5 0 Voc 1062F AVR 07 06 Figure 65 UO Pin Input Hysteresis vs Vee Ta 25 C Input Hysteresis V 2 7 4 0 5 0 AMEL d 1062F AVR 07 06 AMEL Register Summary 3F SREG l T H s V N Z C page 6 3E Reserved nas Reserved 20 Reserved 1F Reserved 1E Reserved 1D Reserved 1C Reserved 1B PORTA PORTA3 PORTA2 PORTA1 PORTAO page 32 SIA PACR DDA3 PA2HC DDA1 DDAO page 32 19 PINA PINA3 PINA1 PINAO page 32 S18 Reserved S17 Reserved 16 PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINBO page 32 15 Reserved 14 Reserved 13 Reserved 12 PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTDO page 33 11 DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDDO page 33 10 PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PINDO page 33 0F Reserved 0E Reserved 0D Reserved 0C Reserved 0B Reserved 0A Reserved 09 Reserved 08 ACSR ACD ACO ACI ACIE ACIS1 ACISO page 44 07 MCUCS PLUPB SE SM WDRF EXTRF PORF page 19 06 ICR INT1 INTO LLIE TOIEO ISC11 ISC10 ISCO1 ISCO0 page 22 05 IFR INTF1 INTFO TOVO page 23 04 TCCRO FOVO OOMO1 OOMOO CS02 CS01 CS00 page 35 03 TCNTO Timer Counter0 8 bit page 36 02 MODCR ONTIM4 ONTIM3 ONTIM2 ONTIMI ONTIMO MCONF2 MCONF1 MCONFO p
18. 78 Table OF CONTENT na ein dites i ATtiny28 L V mns 1062F AVR 07 06 AMEL AN Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH 1705 Fribourg Atmel Operations Memory 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 Microcontrollers 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 La Chantrerie RF Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn Germany Tel 49 71 31 67 0 Fax 49 71 31 67 2340 1150 East Cheyenne Min Blvd Colorado Springs CO 80906 USA Tel 1 719 576 3300 Fax 1 719 540 1759 Biometrics Imaging Hi Rel MPU Switzerland Tel 41 26 426 5555 BP 70602 High Speed Converters RF Datacom Fax 41 26 426 5500 44306 Nantes Cedex 3 France Avenue de Rochepleine Tel 33 2 40 18 18 18 BP 123 Asia Fax 33 2 40 18 19 60 38521 Saint Egreve Cedex France Room 1219 Tel 33 4 76 58 30 00 Chinachem Golden Plaza ASICIASSPISmart Cards Fax 33 4 76 58 34 80 77 Mody Road Tsimshatsui Zone Industrielle East Kowloon 13106 Rousset Cedex France Hong Kong Tel 33 4 42 53 60 00 Tel 852 2721 0778 Fax 33 4 42 53 60 01 Fax 852 2722 1369 1150 East Cheyenne Min Blvd Colorado Springs CO 80906 USA Tel 1 719 576 3300 Fax 1 719 540 1759
19. Interrupt Enable The global interrupt enable bit must be set one for the interrupts to be enabled The individual interrupt enable control is then performed in separate control registers If the global interrupt enable register is cleared zero none of the interrupts are enabled inde pendent of the individual interrupt enable settings The I bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts e Bit 6 T Bit Copy Storage The bit copy instructions BLD Bit LoaD and BST Bit STore use the T bit as source and destination for the operated bit A bit from a register in the register file can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the register file by the BLD instruction Bit5 H Half carry Flag The half carry flag H indicates a half carry in some arithmetic operations See the Instruction Set description for detailed information e Bit4 S Sign Bit S NOV The S bit is always an exclusive or between the negative flag N and the two s comple ment overflow flag V See the Instruction Set description for detailed information e Bit 3 V Two s Complement Overflow Flag The two s complement overflow flag V supports two s complement arithmetic See the Instruction Set description for detailed information e Bit 2 N Negative Flag The negative flag N indicates a negative result from an arithmetical or
20. is activated on rising or falling edge on pin change or low level of the INTO pin The corresponding interrupt of External Interrupt Request 0 is executed from program memory address 001 See also External Interrupt e Bit 5 LLIE Low level Input Interrupt Enable When the LLIE is set one and the I bit in the status register SREG is set one the interrupt on low level input is activated Any of the Port B pins pulled low will then cause an interrupt However if any Port B pins are used for other special features these pins will not trigger the interrupt The corresponding interrupt of Low level Input Interrupt Request is executed from program memory address 003 See also Low level Input Interrupt e Bit 4 TOIEO Timer CounterO Overflow Interrupt Enable When the TOIEO bit is set one and the I bit in the Status Register is set one the Timer Counter0 Overflow Interrupt is enabled The corresponding interrupt at vector 004 is executed if an overflow in Timer Counter0 occurs i e when the TOVO bit is set in the Interrupt Flag Register IFR e Bits 3 2 ISC11 ISC10 Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I flag and the corresponding interrupt enable are set The level and edges on the external INT1 pin that activate the interrupt are defined in Table 8 22 ATtiny28L V mns 1062F AVR 07 06 Interrupt Flag Register IFR 10
21. logical operation See the Instruction Set description for detailed information e Bit 1 Z Zero Flag The zero flag Z indicates a zero result from an arithmetical or logical operation See the Instruction Set description for detailed information e Bit 0 C Carry Flag The carry flag C indicates a carry in an arithmetical or logical operation See the Instruc tion Set description for detailed information Note that the status register is not automatically stored when entering an interrupt rou tine and restored when returning from an interrupt routine This must be handled by software 6 ATtiny28L V mns 1062F AVR 07 06 System Clock and Clock Options Internal RC Oscillator Calibrated Internal RC Oscillator Crystal Oscillator External Clock 1062F AVR 07 06 The device has the following clock source options selectable by Flash Fuse bits as shown in Table 1 Table 1 Device Clocking Option Select Clock Option CKSEL3 0 External Crystal Ceramic Resonator 1111 1010 External Low frequency Crystal 1001 1000 External RC Oscillator 0111 0101 Internal RC Oscillator 0100 0010 External Clock 0001 0000 Note 1 means unprogrammed O means programmed The various choices for each clocking option give different start up times as shown in Table 5 on page 16 The internal RC oscillator option is an on chip calibrated oscillator running at a nominal frequency of 1 2 MHZ If sel
22. n O programs the Lock bit Bit 2 Lock Bit2 Bit 1 Lock Bit1 Bits 7 3 0 1 These bits are reserved and should be left unprogrammed 1 E Write Data Low Byte The Lock bits can only be cleared by executing Chip Erase 50 ATtiny28L V mem 1062F AVR 07 06 Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte 1062F AVR 07 06 The algorithm for reading the Fuse and Lock bits is as follows refer to Programming the Flash for details on command loading A Load Command 0000 0100 1 Set OE to 0 and BS to 0 The status of the Fuse bits can now be read at DATA 0 means programmed Bit 4 INTCAP Fuse Bit 3 CKSEL3 Fuse Bit 2 CKSEL2 Fuse Bit 1 CKSEL1 Fuse Bit 0 CKSELO Fuse 2 Set BS to 1 The status of the Lock bits can now be read at DATA DO means programmed Bit 2 Lock Bit2 Bit 1 Lock Bit1 3 Set OE to 1 The algorithm for reading the signature bytes and the calibration byte is as follows refer to Programming the Flash for details on command and address loading A Load Command 0000 1000 C Load Address Low Byte 00 02 1 Set OE to 0 and BS to 0 The selected signature byte can now be read at DATA C Load Address Low Byte 00 1 Set OE to 0 and BS to 1 The calibration byte can now be read at DATA 2 Set OE to 1 Figure 38 Programming the Flash Waveforms
23. refer to Sleep Modes below Bit3 WDRF Watchdog Reset Flag This bit is set if a Watchdog reset occurs The bit is cleared by a Power on Reset or by writing a logical O to the flag e Bit 2 Res Reserved Bit This bit is a reserved bit in the ATtiny28 and always reads as zero e Bit 1 EXTRF External Reset Flag This bit is set if an external reset occurs The bit is cleared by a Power on Reset or by writing a logical O to the flag e Bit 0 PORF Power on Reset Flag This bit is set if a Power on Reset occurs The bit is cleared by writing a logical O to the flag To make use of the reset flags to identify a reset condition the user should read and then clear the flag bits in MCUCS as early as possible in the program If the register is cleared before another reset occurs the source of the reset can be found by examining the reset flags ATMEL Interrupts Reset and Interrupt Interrupt Handling AMEL The ATtiny28 provides five different interrupt sources These interrupts and the reset vector each have a separate program vector in the program memory space All the inter rupts are assigned to individual enable bits In order to enable the interrupt both the individual enable bit and the l bit in the status register SREG must be set to one The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors The complete list of vectors is show
24. space with an additional global interrupt enable bit in the status register All the different interrupts have a sepa 4 ATtiny28L V mem 1062F AVR 07 06 ALU Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack General purpose Register File 1062F AVR 07 06 rate interrupt vector in the interrupt vector table at the beginning of the program memory The different interrupts have priority in accordance with their interrupt vector position The lower the interrupt vector address the higher the priority The high performance AVR ALU operates in direct connection with all the 32 general purpose working registers Within a single clock cycle ALU operations between regis ters in the register file are executed The ALU operations are divided into three main categories arithmetic logic and bit functions Some microcontrollers in the AVR prod uct family feature a hardware multiplier in the arithmetic part of the ALU The ATtiny28 uses a 3 level deep hardware stack for subroutines and interrupts The hardware stack is 10 bits wide and stores the program counter PC return address while subroutines and interrupts are executed RCALL instructions and interrupts push the PC return address onto stack level 0 and the data in the other stack levels 1 2 are pushed one level deeper in the stack When a RET or RETI instruction is executed the returning PC is fetched from stack level O and the data in the other stack levels 1
25. tive pulse The coding is shown in Table 23 When pulsing WR or OE the command loaded determines the action executed The command is a byte where the different bits are assigned functions as shown in Table 24 Figure 37 Parallel Programming ATtiny28 45V O RDY BSY VCC OE PB7 PBO DATA AMEL a Enter Programming Mode 48 AMEL Table 22 Pin Name Mapping Signal Name in Programming Mode Pin Name I O Function RDY BSY PD1 o 0 Device is busy programming 1 Device is ready for new command OE PD2 Output Enable active low WR PD3 Write Pulse active low BS PD4 Byte Select 0 selects low byte 1 selects high byte XAO PD5 l XTAL1 Action Bit 0 XA1 PD6 l XTAL1 Action Bit 1 DATA PB7 PBO I O Bi directional Data Bus output when OE is low Table 23 XA1 and XAO Coding XA1 0 0 XAO Action when XTAL1 is Pulsed Load Flash Signature byte Address High or low address byte for Flash determined by BS 0 1 Load Data High or low data byte for Flash determined by BS 1 0 Load Command 1 1 No Action Idle Table 24 Command Byte Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse Bits 0010 0000 Write Lock Bits 0001 0000 Write Flash 0000 1000 Read Signature Bytes and Calibration Byte 0000 0100 Read Fuse and Lock Bits 0000 0010 Read Flash The
26. 000 in the signature address space During memory programming the external programmer must read this location and program it into a selected location in the the normal Flash program memory At start up the user soft ware must read this Flash location and write the value to the OSCCAL register 46 ATtiny28L V mns 1062F AVR 07 06 Programming the Flash Parallel Programming Signal Names 1062F AVR 07 06 Atmel s ATtiny28 offers 2K bytes of Flash program memory The ATtiny28 is shipped with the on chip Flash program memory array in the erased state i e contents FF and ready to be programmed This device supports a high voltage 12V parallel programming mode Only minor currents 1mA are drawn from the 12V pin during programming The program memory array in the ATtiny28 is programmed byte by byte During pro gramming the supply voltage must be in accordance with Table 21 Table 21 Supply Voltage during Programming Part Serial Programming Parallel Programming ATtiny28 Not applicable 4 5 5 5V This section describes how to parallel program and verify Flash program memory Lock bits and Fuse bits in the ATtiny28 In this section some pins of the ATtiny28 are referenced by signal names describing their function during parallel programming See Figure 37 and Table 22 Pins not described in Table 22 are referenced by pin name The XA1 XA0 pins determine the action executed when the XTAL1 pin is given a posi
27. 1 ORI Rd K Logical OR Register and Constant Rd RdvK Z N V 1 EOR Rd Rr Exclusive OR Registers Rd Rd Rr Z N V 1 COM Rd One s Complement Rd FF Rd Z C N V 1 NEG Rd Two s Complement Rd S00 Rd Z C N V H 1 SBR Rd K Set Bit s in Register Rd Rdv K Z N V 1 CBR Rd K Clear Bit s in Register Rd Rd e FFh K Z N V 1 INC Rd Increment Rd Rd 1 Z N V 1 DEC Rd Decrement Rd Rd 1 Z N V 1 TST Rd Test for Zero or Minus Rd Rd e Rd Z N V 1 CLR Rd Clear Register Rd Rd 9 Rd Z N V 1 SER Rd Set Register Rd FF None i BRANCH INSTRUCTIONS RJMP k Relative Jump PC PC k 1 None 2 RCALL k Relative Subroutine Call PC lt PC k 1 None 3 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK l 4 CPSE Rd Rr Compare Skip if Equal if Rd Rr PC lt PC 20r3 None 1 2 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K ZN V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC e PC 20r3 None 1 2 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 20r3 None 1 2 SBIC P b Skip if Bit in I O Register Cleared if P b 0 PC PC 2 or 3 None 1 2 SBIS P b Skip if Bit in I O Register is Set if P b 1 PC PC 2 0r3 None 1 2 BRBS s k Branch if Status Flag Set if SREG s 1 then PC PC k 1 None 1 2 BRBC s k Branch if Status Flag Cleared if SREG s 0 then PC PC k 1 None 1 2 BREQ k
28. 62F AVR 07 06 Table 8 Interrupt 1 Sense Control ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request 0 1 Any change on INT1 generates an interrupt request 1 0 The falling edge of INT1 generates an interrupt request 1 1 The rising edge of INT1 generates an interrupt request Note When changing the ISC11 ISC10 bits INT1 must be disabled by clearing its Interrupt Enable bit Otherwise an interrupt can occur when the bits are changed e Bits 1 0 ISCO1 ISCOO Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt O is activated by the external pin INTO if the SREG I flag and the corresponding interrupt enable are set The level and edges on the external INTO pin that activate the interrupt are defined in Table 9 Table 9 Interrupt O Sense Control ISCO1 ISCOO Description 0 0 The low level of INTO generates an interrupt request 0 1 Any change on INTO generates an interrupt request 1 0 The falling edge of INTO generates an interrupt request 1 1 The rising edge of INTO generates an interrupt request Note When changing the ISC01 ISCOO bits INTO must be disabled by clearing its Interrupt Enable bit Otherwise an interrupt can occur when the bits are changed The value on the INT pins are sampled before detecting edges If edge interrupt is selected pulses that last longer than one CPU clock period will generate an interrupt Shorter pul
29. Analog Comparator Interrupt Enable When the ACIE bit is set one and the I bit in the Status Register is set one the ana log comparator interrupt is activated When cleared zero the interrupt is disabled e Bit 2 RES Reserved Bit This bit is a reserved bit in the ATtiny28 and will always read as zero e Bits 1 0 ACIS1 ACISO Analog Comparator Interrupt Mode Select These bits determine which comparator events trigger the Analog Comparator Interrupt The different settings are shown in Table 19 Table 19 ACIS1 ACISO Settings ACIS1 ACISO Interrupt Mode 0 0 Comparator Interrupt on Output Toggle 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge Note When changing the ACIS1 ACISO bits the Analog Comparator Interrupt must be dis abled by clearing its Interrupt Enable bit in the ACSR register Otherwise an interrupt can occur when the bits are changed Caution Using the SBI or CBI instruction on bits other than ACI in this register will write a one back into ACI if it is read as set thus clearing the flag AMEL i Memory Programming Program Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte AMEL The ATtiny28 MCU provides two Lock bits that can be left unprogrammed 1 or can be programmed 0 to obtain the additional features listed in Table 20 The Lock bits can only be erased with the Chip Eras
30. BDTIC www bdtic com ATMEL Features Utilizes the AVR RISC Architecture AVR High performance and Low power RISC Architecture 90 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General purpose Working Registers Up to 4 MIPS Throughput at 4 MHz Nonvolatile Program Memory 2K Bytes of Flash Program Memory Endurance 1 000 Write Erase Cycles Programming Lock for Flash Program Data Security Peripheral Features Interrupt and Wake up on Low level Input One 8 bit Timer Counter with Separate Prescaler On chip Analog Comparator Programmable Watchdog Timer with On chip Oscillator Built in High current LED Driver with Programmable Modulation Special Microcontroller Features Low power Idle and Power down Modes External and Internal Interrupt Sources Power on Reset Circuit with Programmable Start up Time Internal Calibrated RC Oscillator Power Consumption at 1 MHz 2V 25 C Active 3 0 mA Idle Mode 1 2 mA Power down Mode 1 HA HO and Packages 11 Programmable I O Lines 8 Input Lines and a High current LED Driver 28 lead PDIP 32 lead TQFP and 32 pad MLF Operating Voltages Voc 1 8V 5 5V for the ATtiny28V Vec 2 7V 5 5V for the ATtiny28L Speed Grades 0 1 2 MHz for the ATtiny28V 0 4 MHz For the ATtiny28L Pin Configurations PDIP TQFP QFN MLF T LL RESET Cl 1 PAO 8 SS S gt 22 oO n OC o oon PDO
31. Branch if Equal if Z 1 then PC PC K 1 None 1 2 BRNE k Branch if Not Equal if Z 0 then PC PC K 1 None 1 2 BRCS k Branch if Carry Set if C 1 then PC PC k 1 None 1 2 BRCC k Branch if Carry Cleared if C 0 then PC PC K 1 None 1 2 BRSH k Branch if Same or Higher if C 0 then PC PC k 1 None 1 2 BRLO k Branch if Lower if C 1 then PC PC K 1 None 1 2 BRMI k Branch if Minus if N 1 then PC PC K 1 None 1 2 BRPL k Branch if Plus if N 0 then PC PC K 1 None 1 2 BRGE k Branch if Greater or Equal Signed if N V 0 then PC lt PC K 1 None 1 2 BRLT k Branch if Less than Zero Signed if N V 1 then PC PC k 1 None 1 2 BRHS k Branch if Half carry Flag Set if H 1 then PC PC k 1 None 1 2 BRHC k Branch if Half carry Flag Cleared if H 0 then PC PC k 1 None 1 2 BRTS k Branch if T flag Set if T2 1 then PC PC k 1 None 1 2 BRTC k Branch if T flag Cleared if T 0 then PC PC k 1 None 1 2 BRVS k Branch if Overflow Flag is Set if V 1 then PC PC k 1 None 1 2 BRVC k Branch if Overflow Flag is Cleared if V 0 then PC PC k 1 None 1 2 BRIE k Branch if Interrupt Enabled if I 1 then PC PC K 1 None 1 2 BRID k Branch if Interrupt Disabled if I 0 then PC PC k 1 None 1 2 AIMEL H 1062F AVR 07 06 TOJ 5 AIMEL TMO O Instruction Set Summary Continued
32. Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Scottish Enterprise Technology Park Tel 81 3 3523 3551 Maxwell Building Fax 81 3 3523 7581 East Kilbride G75 OQR Scotland Tel 44 1355 803 000 Fax 44 1355 242 743 Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMELS WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without not
33. Latch is read and when reading PIND the logical values present on the pins are read AIMEL Timer CounterO Timer Counter Prescaler x ATtiny28L V AMEL The ATtiny28 provides one general purpose 8 bit Timer Counter Timer CounterO Timer Counter0 has prescaling selection from the 10 bit prescaling timer The Timer Counter0 can either be used as a timer with an internal clock time base or as a counter with an external pin connection that triggers the counting Figure 28 shows the Timer Counter prescaler Figure 28 Timer Counter0 Prescaler D 10 BIT T C PRESCALER st CK CK 6 COUNT ENABLE FROM MODULATOR TO o E 0 CS00 CS01 CS02 TIMER COUNTERO CLOCK SOURCE TCKO The four different prescaled selections are the hardware modulator period CK 64 CK 256 and CK 1028 where CK is the oscillator clock CK external source and stop can also be selected as clock sources Figure 29 shows the block diagram for Timer Counter0 Figure 29 Timer CounterO Block Diagram T CO OVER FLOW IRQ m INTERRUPT CONTROL INTERRUPT FLAG T CO CONTROL REGISTER TCCRO REGISTER ICR REGISTER IFR 8 BIT DATA BUS TIMER COUNTERO 4 T C CLK SOURCE TCNTO T0 1062F AVR 07 06 Register Description Timer Counter0 Control Register TCCRO 1062F AVR 07 06 The 8 bit Timer CounterO can select clock source from CK prescaled CK or an external pi
34. Set Signed Test Flag Sc 1 S 1 CLS Clear Signed Test Flag Sc 0 S 1 SEV Set Two s Complement Overflow Vel V CLV Clear Two s Complement Overflow Vc 0 V 1 SET Set T in SREG Te1 T 1 CLT Clear T in SREG TEO T 1 SEH Set Half carry Flag in SREG H lt 1 H 1 CLH Clear Half carry Flag in SREG H 0 H 1 NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep function None 1 WDR Watchdog Reset see specific descr for WDR timer None 1 D 72 AT In y2 8 L V paa E HG 7 F FEC C F CCCEC CEECCE EFEF CCCEEE E EEE E E E Uen SENI 1062F AVR 07 06 Ordering Information Speed MHz Power Supply Volts Ordering Code Package Operation Range See APC os Commercial ATtiny28L 4MC 32M1 A 0 C to 70 C ATtiny28L 4Al 32A 4 2 7 5 5 ATtiny28L 4AU 32A ATtiny28L 4PI 28P3 Industrial ATtiny28L 4PU 28P3 40 C to 85 C ATtiny28L 4MI 32M1 A ATtiny28L 4MU 32M1 A ATtiny28V 1A 2A vo PE See CARRE ATtiny28V 1MC 32M1 A 0 C to 70 C ATtiny28V 1Al 32A 1 2 1 8 5 5 ATtiny28V 1 AU 32A ATtiny28V 1 PI 28P3 industria ATtiny28V 1 PU 28P3 40 C to 85 C ATtiny28V 1MI 32M1 A ATtiny28V 1MU 32M1 A Notes 1 This device can also be supplied in wafer form Please contact your local Atmel sales office for detailed ordering information and minimum quantities 2 Pb free packaging alternative complies to the European Directive for Restriction of Hazardous Substances RoHS direc tive A
35. Stop condition provides a Timer Enable Disable function The CK down divided modes are scaled directly from the CK oscillator clock If the external pin modes are used for Timer CounterO transitions on PB2 TO will clock the counter even if the pin is configured as an output This feature can give the user software control of the counting Bit 7 6 5 4 3 2 1 0 sos me BY Teno Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Timer Countero is realized as an up counter with read and write access If the Timer CounterO is written and a clock source is present the Timer Counter0 continues counting in the timer clock cycle following the write operation 36 ATtiny28L V mns 1062F AVR 07 06 Watchdog Timer Register Description Watchdog Timer Control Register WDTCR 1062F AVR 07 06 The Watchdog Timer is clocked from a separate on chip oscillator By controlling the Watchdog Timer prescaler the Watchdog reset interval can be adjusted as shown in Table 15 See characterization data for typical values at other Vcc levels The WDR Watchdog Reset instruction resets the Watchdog Timer Eight different clock cycle periods can be selected to determine the reset period If the reset period expires without another Watchdog reset the ATtiny28 resets and executes from the reset vector For timing details on the Watchdog reset refer to page 18 To prevent unintentional disabling of the Watchdog a special turn off
36. T 25 Voc 4 5V7 E LH avec 8 2 7 Ee Vcc 4 0V I 36v 19 EE Tes 233V TL E oj 30V Eva 2v Vee 2 4V 7 8 9 10 11 12 13 14 15 Frequency MHz AMEL 1062F AVR 07 06 59 AMEL Figure 47 Idle Supply Current vs Voc IDLE SUPPLY CURRENT vs Vcc FREQUENCY 4 MHz 1 4 Ta 85 C Ta 25 C lec mA Figure 48 Idle Supply Current vs Voc Device Clocked by Internal Oscillator IDLE SUPPLY CURRENT vs Vec DEVICE CLOCKED BY 1 2MHz INTERNAL RC OSCILLATOR 0 7 0 6 q225C 0 5 T 85 C T E 0 3 0 2 e 7 0 1 0 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 VIVI 1062F AVR 07 06 Figure 49 Idle Supply Current vs Vcc Device Clocked by External 32 kHz Crystal IDLE SUPPLY CURRENT vs Vcc DEVICE CLOCKED BY 32 kHz CRYSTAL 30 25 Ta 85 C 20 Ta 25 C x 15 Q D a 10 up 5 0 15 2 2 5 3 3 5 4 4 5 5 55 6 Voc V Figure 50 Power down Supply Current vs Voc POWER DOWN SUPPLY CURRENT vs Vcc WATCHDOG TIMER DISABLED 3 Ta 85 C 2 5 2 Ei 15 Ta 70 C Q 9 1 9 E oue NT Ta 45 C Ta 25 L _ TA C 0 L 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 AMEL s 1062F AVR 07 06 AMEL Figure 51 Power down Supply Current vs Vec POWER DOWN SUPPLY CURRENT vs Vcc
37. T L mm ann DEN Note Clock frequency 455 kHz modulation frequency 38 kHz duty cycle 50 40 ATtiny28L V mns 1062F AVR 07 06 Figure 34 Modulation with ONTIM 1 MCONF 011 Note Clock frequency 3 64 MHz modulation frequency 455 kHz duty cycle 25 Figure 35 Modulation with ONTIM 3 MCONF 001 ek J LJ L LT L L L L L LT L LT L L LT L L I mm as Note Clock frequency 3 64 MHz modulation frequency 455 kHz duty cycle 50 Table 17 Some Common Modulator Configurations Crystal Resonator Carrier Error in ONTIM MCONF Frequency Frequency Frequency Duty cycle Value Value 455 kHz 38 kHz 0 2 2590 2 011 455 kHz 38 kHz 0 2 33 3 010 455 kHz 38 kHz 0 2 50 5 001 455 kHz 38 kHz 0 2 67 3 100 455 kHz 38 kHz 0 2 75 2 101 1 MHz 38 kHz 1 2 50 12 001 1 8432 MHz 38 kHz 1 1 25 11 011 1 8432 MHZ 38 kHz 1 1 33 15 010 1 8432 MHz 38 kHz 1 1 50 23 001 2 MHz 38 kHz 1 2 25 12 011 2 MHz 38 kHz 1 2 50 25 001 2 4576 MHz 38 kHz 1 1 50 31 001 3 2768 MHz 38 kHz 2 0 25 21 011 4 MHz 38 kHz 1 2 2590 25 011 455 kHz 455 kHz 0 0 approx 50 X 111 1 MHz 455 kHz 9 9 50 0 001 1 82 MHz 455 kHz 0 0 25 0 011 1 82 MHZ 455 kHz 0 0 50 1 001 1 8432 MHz 455 kHz 1 3 25 0 011 1 8432 MHz 455 kHz 1 3 50 1 001 2 MHz 455 kHz 9 9 25 0 011 AMEL a 1062F AVR 07 06 42 Table 17 Some Common Modulator Configurations Continued AMEL
38. TOR OSCILLATOR GND v Y gr PROGRAM Le STACK WATCHDOG TIMING AND RESET COUNTER POINTER TIMER CONTROL i i Y l i LJ PROGRAM L HARDWARE MCU CONTROL STACK REGISTER 1 1 INSTRUCTION TIMER l REGISTER gt GENERAL COUNTER i Lal PURPOSE REGISTERS INSTRUCTION INTERRUPT i DECODER UNIT i 1 CONTROL LINES y STATUS REGISTER i LAT HARDWARE gt gt MODULATOR fe i Al i tI LOGIC LN DATA REGISTER PORTB DATA REGISTER PORTD DATA DIR REG PORTD ANALOG COMPARATOR The ATtiny28 provides the following features 2K bytes of Flash 11 general purpose I O lines 8 input lines a high current LED driver 32 general purpose working registers an 8 bit timer counter internal and external interrupts programmable Watchdog Timer with internal oscillator and 2 software selectable power saving modes The Idle Mode stops the CPU while allowing the timer counter and interrupt system to continue functioning The Power down mode saves the register contents but freezes the oscillator disabling all other chip functions until the next interrupt or hardware reset The wake up or inter 2 ATtiny28L V mns 1062F AVR 07 06 Pin Descriptions VCC GND Port A PA3 PAO Port B PB7 PBO Port D PD7 PDO 1062F AVR 07
39. The hardware modulator generates a configurable pulse train The on time of a pulse can be set to a number of chip clock cycles This is done by configuring the Modu lation Control Register MODCR PA2 is the built in high current LED driver and it is always an output pin The output buffer can sink 25 mA at Voc 2 0V When MCONF is zero modulation is switched off and the pin acts as a normal high current output pin The following truth table shows the effect of various PORTA2 and MCONF settings Table 16 PA2 Output PORTA2 MCONF PA2 Output 0 0 0 0 1 7 Modulated 1 X 1 The modulation period is available as a prescale to Timer CounterO and thus this timer should be used to time the length of each burst If the number of pulses to be sent is N the number 255 N should be loaded to the timer When an overflow occurs the trans mission is complete The OOMO1 and OOMOO bits in TCCRO can be configured to automatically change the value on PA2 when a Timer CounterO overflow occurs See Timer CounterO on page 34 for details on how to configure the OOMO1 and OOMOO bits The modulation period is available as a prescale even when PORTA is high and mod ulation is stopped Thus this prescale can also be used to time the intervals between bursts To get a glitch free output the user should first configure the MODCR register to enable modulation There are two ways to start the modulation 1 Clear the PORTA bit in P
40. Ttiny28L V mns 1062F AVR 07 06 Typical Characteristics 1062F AVR 07 06 The following charts show typical behavior These figures are not tested during manu facturing All current consumption measurements are performed with all I O pins configured as inputs and with internal pull ups enabled A sine wave generator with rail to rail output is used as clock source The power consumption in Power down mode is independent of clock selection The current consumption is a function of several factors such as operating voltage operating frequency loading of I O pins switching rate of I O pins code executed and ambient temperature The dominating factors are operating voltage and frequency The current drawn from capacitive loaded pins may be estimated for one pin as C Vee f where C Load Capacitance Voc Operating Voltage and f Average Switching Fre quency of I O pin The parts are characterized at frequencies and voltages higher than test limits Parts are not guaranteed to function properly at frequencies and voltages higher than the ordering code indicates The difference between current consumption in Power down mode with Watchdog Timer enabled and Power down mode with Watchdog Timer disabled represents the dif ferential current drawn by the Watchdog Timer Figure 42 Active Supply Current vs Frequency ACTIVE SUPPLY CURRENT vs FREQUENCY
41. UP PORT B UP DATA BUS TO LOW LEVEL DETECTOR RP READ PORT B PIN n 5 7 Port D is an 8 bit bi directional I O port with internal pull up resistors Three 1 0 memory address locations are allocated for Port D one each for the Data Register PORTD 12 Data Direction Register DDRD 11 and the Port D Input Pins PIND 10 The Port D Input Pins address is read only while the Data Register and the Data Direction Register are read write The Port D output buffers can sink 10 mA As inputs Port D pins that are externally pulled low will source current if the pull up resistors are activated All eight pins in Port D have equal functionality when used as digital I O pins PDn general I O pin The DDDn bit in the DDRD register selects the direction of this pin If DDDn is set one PDn is configured as an output pin If DDDn is cleared zero PDn is configured as an input pin If PDn is set one when configured as an input pin the MOS pull up resistor is activated To switch the pull up resistor off the PDn has to be cleared zero or the pin has to be configured as an output pin The port pins are tri stated when a reset condition becomes active even if the clock is not running Table 12 DDDn Bits on Port D Pins DDDn PORTDn yo Pull up Comment 0 0 Input No Tri state high Z 0 1 Input Yes PDn will source current if ext pulled low 1 0 Output No Push pull Zero Output 1 1 Output NO Push pull On
42. WATCHDOG TIMER ENABLED 70 60 lec HA Analog comparator offset voltage is measured as absolute offset Figure 52 Analog Comparator Offset Voltage vs Common Mode Voltage Vec 5V 18 E 16 E Ta 85 C o g 10 5 A 5 8 E alas 5 ses lo a UL 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 Common Mode Voltage V 62 ATtiny28L V mns Figure 53 Analog Comparator Offset Voltage vs Common Mode Voltage Vec 2 7V Offset Voltage mV RB o gt Il oo o O 0 0 5 1 1 5 2 2 5 3 Common Mode Voltage V Figure 54 Analog Comparator Input Leakage Current Vcc 6V T4 25 C 60 lacuk nA 10 10 AMEL 1062F AVR 07 06 AMEL Figure 55 Calibrated Internal RC Oscillator Frequency vs Voc CALIBRATED RC OSCILLATOR FREQUENCY vs OPERATING VOLTAGE Figure 56 Watchdog Oscillator Frequency vs Voc Ta 25 C Ta 85 C 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 64 ATtiny28L V mns 1062F AVR 07 06 Sink and source capabilities of I O ports are measured on one pin at a time Figure 57 Pull up Resistor Current vs Input Voltage Ver 5V
43. again without any delay when the Vec decreases below detection level See Figure 17 If the built in start up delay is sufficient RESET can be connected to VCC directly or via an external pull up resistor By holding the RESET pin low for a period after Ve has been applied the Power on Reset period can be extended Refer to Figure 18 for a tim ing example of this Figure 17 MCU Start up RESET Tied to VCC n a vec POT i eos ME RESET ke sel i TIME OUT a trout INTERNAL RESET Figure 18 MCU Start up RESET Controlled Externally I VCC Yr Veo l i i E I I L HY RESET p BST i l I I I TIME OUT trout I I I INTERNAL RESET An external reset is generated by a low level on the RESET pin Reset pulses longer than 50 ns will generate a reset even if the clock is not running Shorter pulses are not guaranteed to generate a reset When the applied voltage reaches the Reset Threshold Voltage Vasr on its positive edge the delay timer starts the MCU after the Time out period trour has expired AMEL 7 AMEL Figure 19 External Reset during Operation VCC RESET INTERNAL RESET Watchdog Reset When the Watchdog times out it will generate a short reset pulse of 1 XTAL cycle dura tion On the falling edge of this pulse the delay timer starts counting the Time out period trour Refer to page 37 for details on operation of the Watchdog Figure 20 Watchdog Reset dur
44. age 43 01 WDTCR WDTOE WDE WDP2 WDP1 WDPO page 37 00 OSCCAL Oscillator Calibration Register page 9 Notes 1 For compatibility with future devices reserved bits should be written to zero if accessed Reserved 1 0 memory addresses should never be written 2 Some of the status flags are cleared by writing a logical 1 to them Note that the CBI and SBI instructions will operate on all bits in the I O register writing a one back into any flag read as set thus clearing the flag The CBI and SBI instructions work with registers 00 to 1F only 70 ATtiny28L V memm Instruction Set Summary Mnemonic Operands Description Operation Flags Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd Rr Add Two Registers Rd lt Rd Rr Z C N V H 1 ADC Rd Rr Add with Carry Two Registers Rd Rd Rr C Z C N V H sl SUB Rd Rr Subtract Two Registers Rd Rd Br Z C N V H 1 SUBI Rd K Subtract Constant from Register Rd Rd K Z C N V H 1 SBC Rd Rr Subtract with Carry Two Registers Rd Rd Rr C Z C N V H 1 SBCI Rd K Subtract with Carry Constant from Reg Rd Rd K C Z C N V H 1 AND Rd Rr Logical AND Registers Rd Rd e Rr Z N V ll ANDI Rd K Logical AND Register and Constant Rd Rd e K ZN V 1 OR Rd Rr Logical OR Registers Rd Rd v Rr Z N V
45. and its surrounding logic is shown in Figure 36 Figure 36 Analog Comparator Block Diagram vcc ANALOG INTERRUPT COMPARATOR SELECT IRQ ACI ACIS1 ACISO Register Description Analog Comparator Control and Status Register ACSR Bit 7 6 5 4 3 2 1 0 sos EE eem Read Write R W R R R W R W R R W R W Initial Value 1 0 x 0 0 0 0 0 e Bit 7 ACD Analog Comparator Disable When this bit is set one the power to the analog comparator is switched off This bit can be set at any time to turn off the analog comparator When changing the ACD bit the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR Otherwise an interrupt can occur when the bit is changed To use the analog compara tor the user must clear this bit e Bit 6 Res Reserved Bit This bit is a reserved bit in the ATtiny28 and will always read as zero e Bit 5 ACO Analog Comparator Output ACO is directly connected to the comparator output e Bit 4 ACI Analog Comparator Interrupt Flag This bit is set one when a comparator output event triggers the interrupt mode defined by ACI1 and ACIO The Analog Comparator Interrupt routine is executed if the ACIE bit is set one and the I bit in SREG is set one ACI is cleared by hardware when execut 44 ATtiny28L V mns 1062F AVR 07 06 ing the corresponding interrupt handling vector Alternatively ACI is cleared by writing a logical 1 to the flag e Bit 3 ACIE
46. ating This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and Watchdog reset If wake up from the Analog Comparator Interrupt is not required the analog comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Sta tus register ACSR This will reduce power consumption in Idle Mode Note that the ACD bit is set by default When the SM bit is set one the SLEEP instruction forces the MCU into the Power down mode In this mode the external oscillator is stopped while the external interrupts and the Watchdog if enabled continue operating Only an external reset a Watchdog reset if enabled or an external level interrupt can wake up the MCU Note that if a level triggered interrupt is used for wake up from Power down mode the changed level must be held for some time to wake up the MCU This makes the MCU less sensitive to noise The wake up period is equal to the clock counting part of the reset period see Table 5 The MCU will wake up from power down if the input has the required level for two Watchdog oscillator cycles If the wake up period is shorter than two Watchdog oscillator cycles the MCU will wake up if the input has the required level for the duration of the wake up period If the wake up condition disappears before the wake up period has expired the MCU will wake up from power down without executing the corresponding interrupt
47. e the interrupt handling routine hardware clears the corresponding flag that generated the interrupt Some of the interrupt flags can also be cleared by writing a logical 1 to the flag bit position s to be cleared 20 ATtiny28L V mem 1062F AVR 07 06 Interrupt Response Time External Interrupt Low level Input Interrupt 1062F AVR 07 06 If an interrupt condition occurs when the corresponding interrupt enable bit is cleared zero the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software If one or more interrupt conditions occur when the global interrupt enable bit is cleared zero the corresponding interrupt flag s will be set and remembered until the global interrupt enable bit is set one and will be executed by order of priority Note that external level interrupt does not have a flag and will only be remembered for as long as the interrupt condition is active Note that the status register is not automatically stored when entering an interrupt rou tine and restored when returning from an interrupt routine This must be handled by software The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum After four clock cycles the program vector address for the actual interrupt handling routine is executed During this 4 clock cycle period the program counter 10 bits is pushed onto the stack The vector is normally a relati
48. e Output Note n 7 6 0 pin number 30 ATtiny28L V mem 1062F AVR 07 06 ATtiny28L V Figure 27 Port D Schematic Diagram Pins PD7 PDO t MOS PULL UP RESET oj D m S RESET T PDn a Pp PORTDn C N WP pU RL L RP WP WRITE PORTD WD WRITE DDRD RL READ PORTD LATCH RP READ PORTD PIN RD READ DDRD n 0 7 AMEL s 1062F AVR 07 06 Register Description Port A Data Register PORTA Port A Control Register PACR Port A Input Pins Address PINA Port B Input Pins Address PINB AMEL Bit 7 6 5 4 3 2 1 0 s E EE Pomo PORTAT EST PORTA Read Write R R R R R W R W R W R W Initial Value 0 0 0 0 0 1 0 0 Bit 7 6 5 4 3 2 1 0 sa D pomo ekono obi DDAO Pacer Read Write R R R R R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bits 7 4 Res Reserved Bits These bits are reserved bits in the ATtiny28 and always read as zero e Bit 3 DDA3 Data Direction PA3 When DDA3 is set one the corresponding pin is an output pin Otherwise it is an input pin e Bit 2 PA2HC PORTA2 High Current Enable When the PA2HC bit is set one an additional driver at the output pin PA2 is enabled This makes it possible to sink 25 mA at Voc 1 8V Vo 0 8V When the PA2HC bit is cleared zero PA2 can sink 15 mA at Voc 1 8V Vo 0 8V e Bits 1 0 DDA1 DDAO Data Direction PA1 and PAO When DDAn is set one the corre
49. e command Table 20 Lock Bit Protection Modes Memory Lock Bits Mode LB1 LB2 Protection Type 1 1 1 No memory lock features enabled 2 0 1 Further programming of the Flash is disabled 3 0 0 Same as mode 2 and verify is also disabled Note 1 Further programming of the Fuse bits is also disabled Program the Fuse bits before programming the Lock bits The ATtiny28 has five Fuse bits INTCAP and CKSEL3 0 e When the INTCAP Fuse is programmed 0 internal load capacitors are connected between XTAL1 XTAL2 and GND similar to C1 and C2 in Figure 5 See Crystal Oscillator on page 7 Default value is unprogrammed 1 e CKSEL3 0 Fuses See Table 1 Device Clocking Option Select on page 7 and Table 5 ATtiny28 Clock Options and Start up Time on page 16 for which combination of CKSEL3 0 to use Default value is 0010 internal RC oscillator with long start up time The status of the Fuse bits is not affected by Chip Erase All Atmel microcontrollers have a 3 byte signature code that identifies the device The three bytes reside in a separate address space For the ATtiny28 they are 1 000 1E indicates manufactured by Atmel 2 001 91 indicates 2 KB Flash memory 3 002 07 indicates ATtiny28 device when signature byte 001 is 91 The ATtiny28 has one byte calibration value for the internal RC oscillator This byte resides in the high byte of address
50. ected the device can operate with no external components The device is shipped with this option selected The calibrated internal oscillator provides a fixed 1 2 MHz nominal clock at 3V and 25 C This clock may be used as the system clock This oscillator can be calibrated by writing the calibration byte to the OSCCAL register When this oscillator is used as the chip clock the Watchdog oscillator will still be used for the Watchdog Timer and for the reset time out For details on how to use the pre programmed calibration value see the section Calibration Byte on page 46 XTAL1 and XTAL2 are input and output respectively of an inverting amplifier which can be configured for use as an on chip oscillator as shown in Figure 5 Either a quartz crystal or a ceramic resonator may be used When the INTCAP fuse is programmed internal load capacitors with typical values 50 pF are connected between XTAL1 XTAL2 and ground Figure 5 Oscillator Connections MAX 1 HC BUFFER m n mi XTAL2 St I XTAL1 GND Note 1 When using the MCU oscillator as a clock for an external device an HC buffer should be connected as indicated in the figure To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 6 AMEL 7 AMEL Figure 6 External Clock Drive Configuration NC XTAL2 EXTERNAL OSCILLATOR XTAL1 SIGNAL GND
51. en a reset condition becomes active even if the clock is not running All Port B pins are connected to a low level detector that can trigger the low level input interrupt See Low level Input Interrupt on page 21 for details In addition Port B has the following alternate functions e INT1 Port B Bit 4 INT1 External Interrupt source 1 The PB4 pin can serve as an external interrupt source to the MCU See the interrupt description for details on how to enable and configure this interrupt If the interrupt is enabled the pull up resistor on PB4 is disabled and PB4 will not give low level interrupts e INTO Port B Bit 3 INTO External Interrupt source 0 The PB3 pin can serve as an external interrupt source to the MCU See the interrupt description for details on how to enable and configure this interrupt If the interrupt is enabled the pull up resistor on PB3 is disabled and PB3 will not give low level interrupts e TO Port B Bit 2 TO Timer Counter0 Counter source See the timer description for further details If TO is used as the counter source the pull up resistor on PB2 is disabled and PB2 will not give low level interrupts AMEL 2 AMEL e AIN1 Port B Bit 1 AIN1 Analog Comparator Negative input When the on chip analog comparator is enabled this pin also serves as the negative input of the comparator If the analog com parator is enabled the pull up resistors on PB1 and PBO are disabled and these pi
52. essing Using Figure 13 Code Memory Constant Addressing the LPM Instruction PROGRAM MEMORY m ATtiny28L V 1062F AVR 07 06 Constant byte address is specified by the Z register contents The 15 MSBs select word address 0 1K and LSB selects low byte if cleared LSB 0 or high byte if set LSB 1 Memory Access and This section describes the general access timing concepts for instruction execution and Instruction Execution internal memory access Timing The AVR CPU is driven by the System Clock directly generated from the external clock crystal for the chip No internal clock division is used Figure 14 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access register file concept This is the basic pipe lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost functions per clocks and functions per power unit Figure 14 The Parallel Instruction Fetches and Instruction Executions Ti T2 T3 T4 i l i i i I l l 1st Instruction Fetch 1st Instruction Execute i gt 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch i i l l 3rd Instruction Execute 4th Instruction Fetch i l 1 l l f r Figure 15 shows the internal timing concept for the register file In a single clock cycle an ALU operation using two register operands is executed and the result is stored back
53. following algorithm puts the device in parallel programming mode 1 Apply 4 5 5 5V between VCC and GND 2 Set RESET and BS pins to O and wait at least 100 ns 3 Apply 11 5 12 5V to RESET Any activity on BS within 100 ns after 12V has been applied to RESET will cause the device to fail entering programming mode ATtiny28L V vs 1062F AVR 07 06 Chip Erase Programming the Flash 1062F AVR 07 06 The Chip Erase command will erase the Flash memory and the Lock bits The Lock bits are not reset until the Flash has been completely erased The Fuse bits are not changed Chip Erase must be performed before the Flash is reprogrammed Load Command Chip Erase Set XA1 XAO to 10 This enables command loading Set BS to 0 Set DATA to 1000 0000 This is the command for Chip Erase Give XTAL1 a positive pulse This loads the command Give WR a negative pulse This starts the Chip Erase RDY BSY goes low Wait until RDY BSY goes high before loading a new command o M D gt A Load Command Write Flash 1 Set XA1 XAO to 10 This enables command loading 2 Set BS to 0 3 Set DATA to 0001 0000 This is the command for Write Flash 4 Give XTAL1 a positive pulse This loads the command B Load Address High Byte 1 Set XA1 XAO to 00 This enables address loading 2 Set BS to 1 This selects high byte 3 Set DATA Address high byte 00 03 4 G
54. ication Pins are not guaranteed to sink current greater than the listed test conditions 4 Although each I O port can source more than the test conditions 3 mA at Voc 5V 1 5 mA at Vgc 3V under steady state conditions non transient the following must be observed 1 The sum of all Lou for all ports should not exceed 300 mA 2 The sum of all lo for port DO D7 and XTAL2 should not exceed 100 mA If loy exceeds the test condition Voy may exceed the related specification Pins are not guaranteed to source current greater than the listed test conditions Minimum Vec for power down is 1 5V When entering Power down PORTA bit in PORTA register should be set 1062F AVR 07 06 AMEL 55 External Clock Drive Waveforms Figure 41 External Clock External Clock Drive AMEL teror Vec 1 8V to 2 7V Vcc 2 7V to 4 0V Vee 4 0V to 5 5V Symbol Parameter Min Max Min Max Min Max Units Voice Oscillator Frequency 0 0 1 2 0 0 4 0 0 0 4 0 MHz tere Clock Period 833 0 250 0 250 0 ns teucx High Time 333 0 100 0 100 0 ns tercx Low Time 333 0 100 0 100 0 ns tcLcH Rise Time 1 6 1 6 0 5 us tene Fall Time 1 6 1 6 0 5 Hs Table 25 External RC Oscillator Typical Frequencies R kO C pF f 100 0 70 0 100 0 kHz 31 5 20 0 1 0 MHz 6 5 20 0 4 0 MHZ 56 Note R should be in the range 3 100 KQ and C should be at least 20 pF A
55. ice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life Atmel Corporation 2006 All rights reserved Atmel logo and combinations thereof Everywhere You Are AVR AVR Studio and oth ers are registered trademarks or trademarks of Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of oth ers Printed on recycled paper 1062F AVR 07 06
56. ing Operation VCC RESET 1 XTAL Cycle WDT TIME OUT 1 RESET et E TIME OUT j INTERNAL RESET 18 ATtiny28L V mns Register Description MCU Control and Status Register MCUCS 1062F AVR 07 06 The MCU Control and Status Register contains control and status bits for general MCU functions Bit 7 6 5 4 3 2 1 0 sor rie se T WORF EXrse PORF movos Read Write R W R R W R W R W R R W R W Initial Value 0 0 0 0 See Bit 0 See Bit Description Desc Bit 7 PLUPB Pull up Enable Port B When the PLUPB bit is set one pull up resistors are enabled on all Port B input pins When PLUPB is cleared the pull ups are disabled If any of the special functions of Port B is enabled the corresponding pull up s is disabled independent of the value of PLUPB e Bit 6 Res Reserved Bit This bit is a reserved bit in the ATtiny28 and always reads as zero e Bit 5 SE Sleep Enable The SE bit must be set one to make the MCU enter the sleep mode when the SLEEP instruction is executed To avoid the MCU entering the sleep mode unless it is the pro grammer s purpose it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction Bit4 SM Sleep Mode This bit selects between the two available sleep modes When SM is cleared zero Idle Mode is selected as sleep mode When SM is set one Power down mode is selected as sleep mode For details
57. is section are referring to the document revision Rev 01 06G 1 Updated chapter layout 2 Updated Ordering Information on page 73 Rev 01 06G 1 Updated description for Port A on page 25 2 Added note 6 in DC Characteristics on page 54 3 Updated Ordering Information on page 73 4 Added Errata on page 77 Rev 03 05F 1 Updated Electrical Characteristics on page 54 2 MLF package alternative changed to Quad Flat No Lead Micro Lead Frame Package QFN MLF 3 Updated Ordering Information on page 73 78 ATti ny28 L V paa E HG 7 F FEC C F CCCEC CEECCE EFEF CCCEEE E EEE E E E CA 1062F AVR 07 06 Table of Contents 1062F AVR 07 06 POAT CS 1 Pin Con Nga ONG T P 1 DOSCHDUON EE 2 Block Diagrairi TE E RA e e OPT MIN EET 2 Pin Descriptions sandrine aR e aE EENAA 3 edes AA aea EEE PN OTOJ 4 Architectural e ET E 6 General purpose Register File 7 ALU Arithmetic Logic R 2 ses susesi an ette nt tee reis 7 Downloadable Flash Program Memory sese e eee 7 Program and Data Addressing Modes 7 Subroutine and Interrupt Hardware Stack eee eee eee eee eee eee 10 Memory Access and Instruction Execution Timing sese eee eee eee eee 10 VO Memory diurne 11 Reset and Interrupt Handling ans 12 Sleep MODES c ees 21 Timer Counter0 AA AA CR APUD I Eri GN Ma AP 24 Timer Counter Presca
58. is set to 111 the carrier frequency will be equal to the oscillator frequency Table 18 MCONF2 0 Effect on Duty cycle and Modulation Period MCONF2 0 On time Off time Duty cycle Min Period Max Period Comment 000 X X 100 X X Unmodulated output 001 ONTIM 1 ONTIM 1 50 2CK 64 CK 010 ONTIM 1 2 x ONTIM 1 33 3 CK 96 CK 011 ONTIM 1 3 x ONTIM 1 25 4CK 128 CK 100 2 x ONTIM 1 ONTIM 1 67 3 CK 96 CK 101 3 x ONTIM 1 ONTIM 1 75 4CK 128 CK 110 Reserved 111 X X Note 1 1 CK 1 CK High frequency output Note In the high frequency mode the output is gated with the clock signal Thus the on and off times will be dependent on the clock input to the MCU Also note that when changing from this mode directly to another modulation mode the output will have a small glitch Thus PA2 should be set to stop the modulated output before changing from this mode 1062F AVR 07 06 AMEL 43 AMEL Analog Com parator The analog comparator compares the input values on the positive input PBO AINO and negative input PB1 AIN1 When the voltage on the positive input PBO AINO is higher than the voltage on the negative input PB1 AIN1 the Analog Comparator Output ACO is set one The comparator can trigger a separate interrupt exclusive to the ana log comparator The user can select interrupt triggering on comparator output rise fall or toggle A block diagram of the comparator
59. ister Registrers Timer Counter Instruction Timer Analog Comparator Control Lines O Lines The ALU supports arithmetic and logic functions between registers or between a con stant and a register Single register operations are also executed in the ALU Figure 3 shows the ATtiny28 AVR RISC microcontroller architecture The AVR uses a Harvard architecture concept with separate memories and buses for program and data memo ries The program memory is accessed with a two stage pipeline While one instruction is being executed the next instruction is pre fetched from the program memory This concept enables instructions to be executed every clock cycle The program memory is reprogrammable Flash memory With the relative jump and relative call instructions the whole 1K address space is directly accessed All AVR instructions have a single 16 bit word format meaning that every program memory address contains a single 16 bit instruction During interrupts and subroutine calls the return address program counter PC is stored on the stack The stack is a 3 level deep hardware stack dedicated for subrou tines and interrupts The I O memory space contains 64 addresses for CPU peripheral functions such as Control Registers Timer Counters and other I O functions The memory spaces in the AVR architecture are all linear and regular memory maps A flexible interrupt module has its control registers in the I O
60. ive XTAL1 a positive pulse This loads the address high byte C Load Address Low Byte 1 Set XA1 XAO to 00 This enables address loading 2 Set BS to O This selects low byte 3 Set DATA Address low byte 00 SFF 4 Give XTAL1 a positive pulse This loads the address low byte D Load Data Low Byte 1 Set XA1 XAO to 01 This enables data loading 2 Set DATA Data low byte S00 SFF 3 Give XTALI a positive pulse This loads the data low byte E Write Data Low Byte 1 Set BS to 0 This selects low data 2 Give WR a negative pulse This starts programming of the data byte RDY BSY goes low 3 Wait until RDY BSY goes high to program the next byte See Figure 38 for signal waveforms F Load Data High Byte Set XA1 XAO to 01 This enables data loading 2 Set DATA Data high byte 00 FF 3 Give XTAL1 a positive pulse This loads the data high byte G Write Data High Byte AMEL i Reading the Flash Programming the Fuse Bits Programming the Lock Bits AMEL 1 Set BS to 1 This selects high data 2 Give WR a negative pulse This starts programming of the data byte RDY BSY goes low 3 Wait until RDY BSY goes high to program the next byte See Figure 39 for signal waveforms The loaded command and address are retained in the device during programming For efficient programming the following should be considered The command needs t
61. ler nnne nennen 24 WaAIChNUOO TUM CF 27 Calibrated Internal RC Oscillator s 29 le E EE EE 30 Analog Comparator 2 sssr nsrsiiiisilisisissrseindissssisnit nninrssii sisiss sers 35 LO POMS aNG AA AA oasis 37 ov To NTN AA LAT aaa 37 Por Binan sects tess ANA AA AA E 40 KP AA AA 43 Memory PIOQFAMIMNINO usi ms AA ak 45 Program Memory Lock Bits A 45 GUJ eege eege S ee eege 45 Signature Bytes uei REI gei a EE Ce ue elder 45 Calibration Byte iii 45 Programming the Flash uicit eh ekvo envi ne te Ra e EE CAR ERR KANA AA ta 45 Parallel Programming aaa aaa eco deett rco e Lo a 46 Parallel Programming Characteristics 52 AMEL AMEL Electrical CHALACICHSUCS sss ot Ia sont kor Koen 53 Absolute Maximum Ratings eene 53 DC Characteristics screen AA AGA ALAN 53 External Clock Drive Waveforms sese 55 External Clock Rn UE 55 Typical Characteristics iiis enisi android a Amahan 56 MEGISTEF SUMMAN ts 69 Instruction Set Summary Lo aec AA 70 Ordering Information ssssssaannnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 72 Packaging Jerta eeeee e dee Eed deed 74 e o Nm 74 Eck RR LE en do ie no di dun 75 SIMA AP es 76 CA MORIETUR AA 77 LTR Te Ta aa 77 Datasheet Revision History rss 78 ANA a ite 78 ni Oe ne me te ae
62. lso Halide free and fully Green Package Type 32A 32 ead Thin 1 0 mm Plastic Quad Flat Package TQFP 28P3 28 lead 0 300 Wide Plastic Dual Inline Package PDIP 32M1 A 32 pad 5x5x1 0 body Lead Pitch 0 50mm Quad Flat No lead Micro Lead Frame Package QFN MLF ATMEL n 1062F AVR 07 06 AMEL Packaging Information 32A NUNA KNK Q PIN 1 IDENTIFIER CUUUUUUUUUU ma Ti 1 D COMMON DIMENSIONS Unit of Measure mm SYMBOL MAX 1 20 0 15 1 05 9 25 7 10 9 25 Notes 1 This package conforms to JEDEC reference MS 026 Variation ABA 2 Dimensions D1 and E1 do not include mold protrusion Allowable 7 10 protrusion is 0 25 mm per side Dimensions D1 and E1 are maximum 0 45 plastic body size dimensions including mold mismatch 3 Lead coplanarity is 0 10 mm maximum 0 20 0 75 0 80 TYP 10 5 2001 TITLE DRAWING NO REV IMEL 2929 Orchard Parkway 324 32 lead 7 x 7 mm Body Size 1 0 mm Body Thickness A A s San Jose CA 99191 0 8 n Lead Pitch Thin Profile Plastic Quad Flat Package TQFP n ATtiny28L V 1062F AVR 07 06 28P3 A 7 SEATING rine t H Pt Ld UE Le B2 4 PLACES
63. mories VO Memory The I O space definition of the ATtiny28 is shown in Table 3 Table 3 ATtiny28 I O Space Address Hex Name Function S3F SREG Status Register 1B PORTA Data Register Port A SIA PACR Port A Control Register 519 PINA Input Pins Port A S16 PINB Input Pins Port B 12 PORTD Data Register Port D 11 DDRD Data Direction Register Port D 10 PIND Input Pins Port D 08 ACSR Analog Comparator Control and Status Register 07 MCUCS MCU Control and Status Register 06 ICR Interrupt Control Register 05 IFR Interrupt Flag Register 04 TCCRO Timer CounterO Control Register 03 TCNTO Timer CounterO 8 bit 02 MODCR Modulation Control Register 01 WDTCR Watchdog Timer Control Register 00 OSCCAL Oscillator Calibration Register Note Reserved and unused locations are not shown in the table All ATtiny28 I O and peripherals are placed in the I O space The I O locations are accessed by the IN and OUT instructions transferring data between the 32 general pur pose working registers and the I O space I O registers within the address range 00 1F are directly bit accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SBIS and SBIC instructions Refer to the Instruction Set section for more details For compatibility with future devices reserved bits should be written to zero if accessed Reserved I O memory addresses should never be written The I O and peripherals control regi
64. n In addition it can be stopped as described in the specification for the Timer Counter0 Control Register TCCRO The overflow status flag is found in the Inter rupt Flag Register IFR Control signals are found in the Timer CounterO Control Register TCCRO The interrupt enable disable setting for Timer CounterO is found in the Interrupt Control Register ICR When Timer CounterO is externally clocked the external signal is synchronized with the oscillator frequency of the CPU To ensure proper sampling of the external clock the minimum time between two external clock transitions must be at least one internal CPU clock period The external clock signal is sampled on the rising edge of the internal CPU clock The 8 bit Timer CounterO features both a high resolution and a high accuracy usage with the lower prescaling opportunities Similarly the high prescaling opportunities make the Timer CounterO useful for lower speed functions or exact timing functions with infre quent actions Bit 7 6 5 4 3 2 1 0 04 FOV O0M01 oomoo CSo2 CS01 Csoo TCCRO Read Write RAW R R RAW RAW R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bit 7 FOVO Force Overflow Writing a logical 1 to this bit forces a change on the overflow output pin PA2 according to the values already set in OOM01 and OOMOO If the OOM01 and OOMOO bits are written in the same cycle as FOVO the new settings will not take effect until the next overflow or forced
65. n in Table 7 The list also determines the priority levels of the different interrupts The lower the address the higher the priority level RESET has the highest priority and next is INTO the External Interrupt Request 0 Table 7 Reset and Interrupt Vectors Vector Program No Address Source Interrupt Definition Hardware Pin Power on Reset and 000 BESET Watchdog Reset 2 001 INTO External Interrupt Request 0 3 002 INT1 External Interrupt Request 1 4 003 Input Pins Low level Input on Port B TIMERO 5 004 OVFO Timer Counter0 Overflow 6 005 ANA COMP Analog Comparator The most typical and general program setup for the Reset and Interrupt vector addresses are Address Labels Code Comments 000 rjmp RESET Reset handler 001 rjmp EXT INTO IRQO handler 002 rjmp EXT INTI IRQ1 handler 003 rjmp OW LEVEL Low level input handler 004 rjmp TIMO OVF Timer0 overflow handle 005 rjmp ANA COMP Analog Comparator handle 006 MAIN instr xxx Main program start The ATtiny28 has one 8 bit Interrupt Control Register ICR When an interrupt occurs the Global Interrupt Enable I bit is cleared zero and all inter rupts are disabled The user software can set one the I bit to enable nested interrupts The I bit is set one when a Return from Interrupt instruction RETI is executed When the program counter is vectored to the actual interrupt vector in order to execut
66. ns will not give low level interrupts e AINO Port B Bit 0 AINO Analog Comparator Positive input When the on chip analog comparator is enabled this pin also serves as the positive input of the comparator If the analog com parator is enabled the pull up resistors on PB1 and PBO are disabled and these pins will not give low level interrupts Port B Schematics Note that all port pins are synchronized The synchronization latches are however not 28 shown in the figures Figure 23 Port B Schematic Diagram Pins PBO and PB1 MOS PULL UP PORT B Ge COMPARATOR DISABLE o Li 3 pu D z T DATA BUS TO LOW LEVEL DETECTOR TO COMPARATOR AINn RP READ PORTB PIN n 0 1 ATtiny28L V mns 1062F AVR 07 06 ATtiny28L V Figure 24 Port B Schematic Diagram Pin PB2 MOS PULL UP PORT B PULL UP DATA BUS RP PB2 e P IS TO LOW LEVEL DETECTOR e TIMERO CLOCK SENSE CONTROL SOURCE MUX CS02 CS01 CS00 RP READ PORTB PIN Figure 25 PORT B Schematic Diagram Pins PB3 and PB4 MOS K PULL UP PORT B PULL b 4 e p INTm ENABLE DATA BUS AJ TO LOW LEVEL DETECTOR gt 4 L SENSE CONTROL INTm ISCm1 ISCmO P READ PORTB PIN RP R n 3 4 m 0 1 ATMEL 2 Port D Port D as General Digital I O AMEL Figure 26 PORT B Schematic Diagram Pins PB7 PB5 MOS PULL Jp lt PULL
67. o be loaded only once when writing or reading multiple memory locations e Address high byte only needs to be loaded before programming a new 256 word page in the Flash e Skip writing the data value SFF that is the contents of the entire Flash after a Chip Erase These considerations also apply to Flash and signature bytes reading The algorithm for reading the Flash memory is as follows refer to Programming the Flash for details on command and address loading A Load Command 0000 0010 B Load Address High Byte 00 03 C Load Address Low Byte 00 FF 1 Set OE to 0 and BS to 0 The Flash word low byte can now be read at DATA 2 Set BS to 1 The Flash word high byte can now be read from DATA 3 Set OE to 1 The algorithm for programming the Fuse bits is as follows refer to Programming the Flash for details on command and data loading A Load Command 0100 0000 D Load Data Low Byte Bit n O programs and bit n 1 erases the Fuse bit Bit 4 INTCAP Fuse Bit 3 CKSEL3 Fuse Bit 2 CKSEL2 Fuse Bit 1 CKSEL1 Fuse Bit O CKSELO Fuse Bits 7 5 1 These bits are reserved and should be left unprogrammed 1 E Write Data Low Byte The algorithm for programming the Lock bits is as follows refer to Programming the Flash for details on command and data loading A Load Command 0010 0000 D Load Data Low Byte Bit
68. ock cycles write a logical O to WDE This disables the Watchdog e Bits 2 0 WDP2 WDP1 WDPO Watchdog Timer Prescaler 2 1 and 0 The WDP2 WDP1 and WDPO bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled The different prescaling values and their corresponding time out periods are shown in Table 15 Table 15 Watchdog Timer Prescale Select Number of WDT Typical Typical Typical Oscillator Time outat Time outat Time out at WDP2 WDP1 WDPO Cycles Vec 2 0V Vec 23 0V Vec BON 0 0 0 16K cycles 0 15s 47 ms 15 ms 0 0 1 32K cycles 0 30 s 94 ms 30 ms 0 1 0 64K cycles 0 60s 0 19 s 60 ms 0 1 1 128K cycles 1 2s 0 38s 0 12 s 1 0 0 256K cycles 24s 0 75s 0 24 s 1 0 1 512K cycles 48s 1 55 0 49 s 1 1 0 1 024K cycles 9 6s 3 0s 0 97 s 1 1 1 2 048K cycles 19s 60s 1 9s Note The frequency of the Watchdog oscillator is voltage dependent as shown in the section Typical Characteristics on page 57 The WDR Watchdog Reset instruction should always be executed before the Watchdog Timer is enabled This ensures that the reset period will be in accordance with the Watchdog Timer prescale settings If the Watchdog Timer is enabled without reset the Watchdog Timer may not start counting from zero ATtiny28L V memm Hardware Modulator 1062F AVR 07 06 ATtiny28 features a built in hardware modulator connected to a high current output pad PA2
69. ort A Data Register PORTA 2 Configure OOMOO and OOMO bits in the Timer CounterO Control Register TCCRO to clear PA2 on the next overflow Either an overflow or a forced over flow can then be used to start modulation The PA2 output will then be set low at the start of the next cycle To stop the modulated output the user should set the PORTA2 bit or configure OOMOO and OOM01 to set PA2 on the next overflow If the MODCR register is changed during modulation the changed value will take effect at the start of the next cycle producing a glitch free output See Figure 31 below and Figure 22 on page 26 AMEL s AMEL Figure 31 The Hardware Modulator RM EE COUNT ENABLE MODULATOR TO TIMER COUNTERO 2 F Z O ZN STATE 3 all 3 MACHINE sl O o z A PIMCONF DISABLE MODUALTOR ENABLE SETTING WM WRITE MODCR PAZ RM READ MODCR E Figure 32 to Figure 35 show examples on output from the Modulator Figure 32 also shows the timing for the enable setting signal and for the count enable signal to Timer CounterO T O X E gt ND D IPORTA2 Figure 32 Modulation with ONTIM 3 MCONF 010 CLK PA2 ENABLE LT LO o SETTING CON la LL Uk T py ENABLE Note 1 Clock frequency 455 kHz modulation frequency 38 kHz duty cycle 33 Figure 33 Modulation with ONTIM 5 MCONF 001 ck LJ L LT L L LT L L LT L LT L L L
70. overflow occurs The Force Overflow bit can be used to change the output pin without waiting for an overflow in the timer The automatic action programmed in OOMO1 and OOMOO happens as if an overflow had occurred but no interrupt is gen erated The FOVO bit will always read as zero and writing a zero to this bit has no effect e Bits 6 5 Res Reserved Bits These bits are reserved bits in the ATtiny28 and always read as zero e Bits 4 3 OOMO1 OOMOO Overflow Output Mode Bits 1 and 0 The OOMO1 and OOMOO control bits determine any output pin action following an over flow or a forced overflow in Timer Counter0 Any output pin actions affect pin PA2 The control configuration is shown in Table 13 Table 13 Overflow Output Mode Select OOMO1 OOMOO Description 0 0 Timer CounterO disconnected from output pin PA2 0 1 Toggle the PA2 output line 1 0 Clear the PA2 output line to zero 1 1 Set the PA2 output line to one AMEL a Timer Counter 0 TCNTO AMEL e Bits 2 1 0 CS02 CS01 CS00 Clock Selecto Bits 2 1 and 0 The Clock SelectO bits 2 1 and O define the prescaling source of Timer Counter0 Table 14 Clock O Prescale Select CS02 CS01 CS00 Description 0 0 0 Stop the Timer Countero is stopped 0 0 1 CK 0 1 0 Modulator Period 0 1 1 CK 64 1 0 0 CK 256 1 0 1 CK 1024 1 1 0 External Pin TO falling edge 1 1 1 External Pin TO rising edge The
71. rved Bit This bit is a reserved bit in the ATtiny28 and always reads as zero e Bit 4 TOVO Timer Counter0 Overflow Flag The bit TOVO is set one when an overflow occurs in Timer Counter0 TOVO is cleared by hardware when executing the corresponding interrupt handling vector TOVO is cleared by writing a logical 1 to the flag When the SREG I bit TOIEO in ICR and TOVO are set one the Timer Counter0 Overflow interrupt is executed e Bit 3 0 Res Reserved Bits These bits are reserved bits in the ATtiny28 and always read as zero Note 1 One should not try to use the SBI Set Bit in I O Register instruction to clear individ ual flags in the Register This will result in clearing all the flags in the register because the register is first read then modified and finally written thus writing ones to all set flags Using the CBI Clear Bit in I O Register instruction on IFR will result in clearing all bits apart from the specified bit ATtiny28L V mns 1062F AVR 07 06 O Ports Port A Port A as General Digital I O Alternate Function of PA2 1062F AVR 07 06 All AVR ports have true read modify write functionality when used as general digital I O ports This means that the direction of one port pin can be changed without unintention ally changing the direction of any other pin with the SBI and CBI instructions The same applies for changing drive value if configured as output or enabling disabling of pull up
72. sequence must be followed when the Watchdog is disabled Refer to the description of the Watchdog Timer Control Register for details Figure 30 Watchdog Timer Oscillator 1 MHz at Voc 5V WATCHDOG 350 kHz at Voc 3V PRESCALER 110 kHz at Voc 2V OSC 32K OSC 256K OSC 512K OSC 1024K OSC 2048K WATCHDOG RESET WDPO WDP1 WDP2 WDE MCU RESET Bit 7 6 5 4 3 2 1 0 01 pose WESGE BE ili WOPE WEE NERO ONCE Read Write R R R RW RW RW RW R W Initial Value 0 0 0 0 0 0 0 0 e Bits 7 5 Res Reserved Bits These bits are reserved bits in the ATtiny28 and will always read as zero e Bit 4 WDTOE Watchdog Turn off Enable This bit must be set one when the WDE bit is cleared Otherwise the Watchdog will not be disabled Once set hardware will clear this bit to zero after four clock cycles Refer to the description of the WDE bit for a Watchdog disable procedure e Bit 3 WDE Watchdog Enable When the WDE is set one the Watchdog Timer is enabled and if the WDE is cleared zero the Watchdog Timer function is disabled WDE can only be cleared if the WDTOE bit is set one To disable an enabled Watchdog Timer the following proce dure must be followed ATMEL s 38 AMEL 1 Inthe same operation write a logical 1 to WDTOE and WDE A logical 1 must be written to WDE even though it is set to one before the disable operation starts 2 Within the next four cl
73. ses are not guaranteed to generate an interrupt If low level interrupt is selected the low level must be held until the completion of the currently executing instruction to generate an interrupt If enabled a level triggered interrupt will generate an interrupt request as long as the pin is held low Bit 7 6 5 4 3 2 1 0 sos mer o vow e Read Write R W R W R R W R R R R Initial Value 0 0 0 0 0 0 0 0 e Bit 7 INTF1 External Interrupt Flag1 When an edge on the INT1 pin triggers an interrupt request the corresponding interrupt flag INTF1 becomes set one If the I bit in SREG and the corresponding interrupt enable bit INT1 in GIMSK is set one the MCU will jump to the interrupt vector The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a logical 1 to it This flag is always cleared when INT1 is configured as level interrupt e Bit 6 INTFO External Interrupt Flago When an edge on the INTO pin triggers an interrupt request the corresponding interrupt flag INTFO becomes set one If the I bit in SREG and the corresponding interrupt AMEL 2 24 AMEL enable bit INTO in GIMSK is set one the MCU will jump to the interrupt vector The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a logical 1 to it This flag is always cleared when INTO is configured as level interrupt e Bit 5 Res Rese
74. sponding pin is an output pin Otherwise itis an input pin Bit 7 6 5 4 3 2 1 0 19 em 2 PINAS PINAT PINAO PINA Read Write R R R R R R R R Initial Value 0 0 0 0 N A 0 N A N A The Port A Input Pins address PINA is not a register this address enables access to the physical value on each Port A pin When reading PORTA the Port A Data Latch is read and when reading PINA the logical values present on the pins are read Bit 7 6 5 4 3 2 1 0 16 PINB7 PINB6 PINB4 PINB3 PINB2 PINB1 PINBO PINB Read Write R R R R R R R R Initial Value N A N A N A N A N A N A N A N A The Port B Input Pins address PINB is not a register this address enables access to the physical value on each Port B pin When reading PINB the logical values present on the pins are read 32 ATtiny28L V mns 1062F AVR 07 06 Port D Data Register PORTD Port D Data Direction Register DDRD Port D Input Pins Address PIND 1062F AVR 07 06 Bit 7 6 5 4 3 2 1 0 Read Write RW R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Read Write RW R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 sto ERC Re FINOS FINDS FINDS PNG PRET NEO PINO Read Write R R R R R R R R Initial Value N A N A N A N A N A N A N A N A The Port D Input Pins Address PIND is not a register this address enables access to the physical value on each Port D pin When reading PORTD the Port D Data
75. sters are explained in the following sections 10 ATtiny28L V mns 1062F AVR 07 06 ATtiny28L V Program and Data The ATtiny28 AVR RISC microcontroller supports powerful and efficient addressing Addressing Modes modes This section describes the different addressing modes supported in the ATtiny28 In the figures OP means the operation code part of the instruction word To simplify not all figures show the exact location of the addressing bits Register Direct Single Figure 8 Direct Single Register Addressing Register Rd REGISTER FILE 0 15 4 0 oe 9 E 3 d 31 The operand is contained in register d Rd Register Indirect Figure 9 Indirect Register Addressing REGISTERFILE Z Register The register accessed is the one pointed to by the Z register R31 R30 Register Direct Two Registers Figure 10 Direct Register Addressing Two Registers Rd and Rr REGISTER FILE ATMEL 1062F AVR 07 06 AIMEL Operands are contained in register r Rr and d Rd The result is stored in register d Rd O Direct Figure 11 O Direct Addressing UO MEMORY Operand address is contained in six bits of the instruction word n is the destination or source register address Relative Program Addressing Figure 12 Relative Program Memory Addressing RJMP and RCALL PROGRAM MEMORY Program execution continues at address PC k 1 The relative address k is 2048 to 2047 Constant Addr
76. these pins will not trigger the interrupt For example if the analog comparator is enabled a low level on PBO or PB1 will not cause an interrupt This is also the case for the special functions TO INTO and INT1 If low level interrupt is selected the low level must be held until the completion of the cur rently executing instruction to generate an interrupt When this interrupt is enabled the interrupt will trigger as long as any of the Port B pins are held low AMEL Register Description Interrupt Control Register ICR AMEL Bit 7 6 5 4 3 2 1 0 06 INT1 INTO LLIE TOIEO ISC11 ISC10 ISCO1 ISCO0 ICR Read Write RW RW RW R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bit 7 INT1 External Interrupt Request 1 Enable When the INT1 bit is set one and I bit in the Status Register SREG is set one the external pin interrupt 1 is enabled The interrupt Sense Control1 bits 1 0 ISC11 and ISC10 define whether the external interrupt is activated on rising or falling edge on pin change or low level of the INT1 pin The corresponding interrupt of External Interrupt Request 1 is executed from program memory address 002 See also External Interrupt e Bit 6 INTO External Interrupt Request 0 Enable When the INTO bit is set one and the I bit in the Status Register SREG is set one the external pin interrupt O is enabled The interrupt Sense ControlO bits 1 0 ISCO1 and ISCO0 define whether the external interrupt
77. umber of clock cycles in the start up period it is recommended that ceramic resonator be used This table shows the start up times from reset From Power down mode only the clock counting part of the start up time is used The Watchdog oscillator is used for timing the real time part of the start up time The number WDT oscillator cycles used for each time out is shown in Table 6 Table 6 Number of Watchdog Oscillator Cycles Time out Number of Cycles 4 2 ms 1K 67 ms 16K The frequency of the Watchdog oscillator is voltage dependent as shown in the section Typical Characteristics on page 57 The device is shipped with CKSEL 0010 A Power on Reset POR pulse is generated by an on chip detection circuit The detec tion level is nominally 1 4V The POR is activated whenever Ve is below the detection level The POR circuit can be used to trigger the start up reset as well as detect a fail ure in supply voltage The Power on Reset POR circuit ensures that the device is reset from power on Reaching the Power on Reset threshold voltage invokes a delay counter which deter mines the delay for which the device is kept in RESET after Vcc rise The time out period of the delay counter can be defined by the user through the CKSEL fuses The different selections for the delay period are presented in Table 5 The RESET signal is 16 ATtiny28L V mns 1062F AVR 07 06 External Reset 1062F AVR 07 06 activated
78. under Absolute Maximum Ratings may cause perma Storage Temperature 65 C to 150 C nent damage to the device This is a stress rating only and functional operation of the device at Voltage on Any Pin except RESET these or other conditions beyond those indicated with Respect to Ground 1 0V to Voc 0 5V in the operational sections of this specification is not implied Exposure to absolute maximum rat Maximum Operating Voltage A 6 0V ing conditions for extended periods may affect device reliability Voltage on RESET with Respect to Ground 1 0V to 13 0V DC Current per I O Pin except PA2 40 0 mA DC Current PAZ 5 eri GA aanak 60 0 mA DC Current VCC and GND Pin 300 0 mA DC Characteristics Ta 40 C to 85 C Vec 1 8V to 5 5V unless otherwise noted Symbol Parameter Condition Min Typ Max Units Vi Input Low Voltage Except XTAL 0 5 0 3 Vee Vu Input Low Voltage XTAL 0 5 0 1 Vee V Viu Input High Voltage Except XTAL RESET 0 6 Voc Voc 0 5 V Vi Input High Voltage XTAL 0 7 Vee Voc 0 5 V Vino Input High Voltage RESET 0 85 Voc Voc 0 5 V Vor Output Low Voltage lou 20 mA Voc 5V 0 6 V VoL Output Low Voltage lou 25 MA Voc 2 0V 10 V Port A2 V Von Output High Voltage lon 3 MA Voc 5V 4 3 V Ports A D loH 1 5 mA Voc
79. ut pin The effects of the DDAn and PORTAn bits on PA3 PA1 and PAO are shown in Table 10 The port pins are tri stated when a reset condition becomes active even if the clock is not running Table 10 DDAn Effects on Port A Pins DDAn PORTAn HO Pull up Comment 0 0 Input No Tri state high Z 0 1 Input Yes PAn will source current if ext pulled low 1 0 Output No Push pull Zero Output 1 1 Output No Push pull One Output Note n 3 1 0 pin number PA2 is the built in high current LED driver and it is always an output pin The output sig nal can be modulated with a software programmable frequency See Hardware Modulator on page 39 for further details AMEL 3 AMEL Port A Schematics Note that all port pins are synchronized The synchronization latches are however not shown in the figures Figure 21 Port A Schematic Diagram Pins PAO PA1 and PA3 DATA BUS gt gt WP WRITE PORTA WD WRITE DDRA RL READ PORTA LATCH RP READ PORTA PIN RD READ DDRA n 0 1 3 Figure 22 Port A Schematic Diagram Pin PA2 o 5 a RESET lt HL lt R a HARDWARE 1 a E PA2 MODULATOR PORTAS 0 C WP ni BISABIE OOM01 OOM00 e ET RESET SET i 1 WP WRITE PORTA RL READ PORTA LATCH Q Note Both the flip flops shown have reset value one set
80. ve jump to the interrupt rou tine and this jump takes two clock cycles If an interrupt occurs during execution of a multi cycle instruction this instruction is completed before the interrupt is served If an interrupt occurs when the MCU is in sleep mode the interrupt execution response time is increased by four clock cycles A return from an interrupt handling routine takes four clock cycles During these four clock cycles the program counter 10 bits is popped back from the stack and the I flag in SREG is set When AVR exits from an interrupt it will always return to the main pro gram and execute one more instruction before any pending interrupt is served The external interrupt is triggered by the INT pins Observe that if enabled the interrupt will trigger even if the INT pin is configured as an output This feature provides a way of generating a software interrupt The external interrupt can be triggered by a falling or ris ing edge a pin change or a low level This is set up as indicated in the specification for the Interrupt Control Register ICR When the external interrupt is enabled and is con figured as level triggered the interrupt will trigger as long as the pin is held low The external interrupt is set up as described in the specification for the Interrupt Control Register ICR The low level interrupt is triggered by setting any of the Port B pins low However if any Port B pins are used for other special features
81. when a reset condition becomes active even if the clock is not running Port D is an 8 bit I O port Port pins can provide internal pull up resistors selected for each bit The port pins are tri stated when a reset condition becomes active even if the clock is not running Input to the inverting oscillator amplifier and input to the internal clock operating circuit Output from the inverting oscillator amplifier Reset input An external reset is generated by a low level on the RESET pin Reset pulses longer than 50 ns will generate a reset even if the clock is not running Shorter pulses are not guaranteed to generate a reset Figure 2 AMEL Architectural Overview AMEL The fast access register file concept contains 32 x 8 bit general purpose working regis ters with a single clock cycle access time This means that during one single clock cycle one ALU Arithmetic Logic Unit operation is executed Two operands are output from the register file the operation is executed and the result is stored back in the register file in one clock cycle Two of the 32 registers can be used as a 16 bit pointer for indirect memory access This pointer is called the Z pointer and can address the register file and the Flash program memory Figure 3 The ATtiny28 AVR RISC Architecture Data Bus 8 bit 1Kx16 Program Status Control Program Counter and Test Registrers Interrupts 32 x8 Unit General Instruction Purpose 8 bit Reg

ATMEL Atmel AVR micro controller ATtiny28L handbook

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