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ATMEL ATtiny85 handbook (1)

1. Ss Mnemonics Operands Description Operation Flags Clocks ROR Rd Rotate Right Through Carry Rd 7 e C Rd n e Rd n 1 C lt Rd 0 Z C N V 1 ASR Rd Arithmetic Shift Right Rd n Rd n 1 n 0 6 Z C N V SWAP Rd Swap Nibbles Rd 3 0 lt Rd 7 4 Rd 7 4 lt Rd 3 0 None 1 BSET S Flag Set SREG s 1 SREG s BCLR s Flag Clear SREG s 0 SREG s BST Rr b Bit Store from Register to T T e Rr b T BLD Rd b Bit load from T to Register Rd b T None SEC Set Carry Cei C CLC Clear Carry Cc 0 C 1 SEN Set Negative Flag Ne1 N 1 CLN Clear Negative Flag Nc 0 N SEZ Set Zero Flag Zei Z CLZ Clear Zero Flag Zc 0 Z 1 SEI Global Interrupt Enable lei l CLI Global Interrupt Disable l0 l SES Set Signed Test Flag Sc 1 S CLS Clear Signed Test Flag Sc 0 S SEV Set Twos Complement Overflow Vel V 1 CLV Clear Twos Complement Overflow Vc 0 V 1 SET Set T in SREG Tei T CLT Clear T in SREG T lt 0 it SEH Set Half Carry Flag in SREG Hc1 H CLH Clear Half Carry Flag in SREG Hc0 H DATA TRANSFER INSTRUCTIONS MOV Rd Rr Move Between Registers Rd Rr None MOVW Rd Rr Copy Register Word Rd 1 Rd lt Rr 1 Rr None LDI Rd K Load Immediate Rd K None LD Rd X Load Indirect Rd lt X None 2 LD Rd X Lo
2. PWM Frequency Clock Selection CS13 CS10 OCR1C RESOLUTION 20 kHz PCK 16 0101 199 7 6 30 kHz PCK 16 0101 132 7 1 40 kHz PCK 8 0100 199 7 6 50 kHz PCK 8 0100 159 7 3 60 kHz PCK 8 0100 132 7 1 70 kHz PCK 4 0011 228 7 8 80 kHz PCK 4 0011 199 7 6 90 kHz PCK 4 0011 177 7 5 100 kHz PCK 4 0011 159 7 3 110 kHz PCK 4 0011 144 7 2 120 kHz PCK 4 0011 132 7 1 130 kHz PCK 2 0010 245 7 9 140 kHz PCK 2 0010 228 7 8 150 kHz PCK 2 0010 212 7 7 160 kHz PCK 2 0010 199 7 6 170 kHz PCK 2 0010 187 7 6 180 kHz PCK 2 0010 177 7 5 190 kHz PCK 2 0010 167 7 4 200 kHz PCK 2 0010 159 7 3 250 kHz PCK 0001 255 8 0 300 kHz PCK 0001 212 7 7 350 kHz PCK 0001 182 7 5 400 kHz PCK 0001 159 7 3 450 kHz PCK 0001 141 7 1 500 kHz PCK 0001 127 7 0 15 Dead Time Generator The Dead Time Generator is provided for the Timer Counter1 PWM output pairs to allow driving external power control switches safely The Dead Time Generator is a separate block that can be connected to Timer Counter1 and it is used to insert dead times non overlapping times for the Timer Counter1 complementary output pairs OC1A OC1A and OC1B OC1B The sharing of tasks is as follows the timer counter generates the PWM output and the Dead Time Genera tor generates the non overlapping PWM output pair from the timer counter PWM signal Two Dead Time Generators are provided one for each PWM output The non overlap time is adjust 90 ATtiny25 45
3. The analog input channel and differential gain are selected by writing to the MUX3 0 bits in ADMUX Any of the four ADC input pins ADC3 0 can be selected as single ended inputs to the 108 ATtiNY25 45 85 uu 7598G AVR 03 08 ADC ADC2 or ADCO can be selected as positive input and ADCO ADC1 ADC2 or ADC3 can be selected as negative input to the differential gain amplifier If differential channels are selected the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor 1x or 20x according to the setting of the MUX3 0 bits in ADMUX This amplified value then becomes the analog input to the ADC If single ended channels are used the gain amplifier is bypassed altogether If ADCO or ADC2 is selected as both the positive and negative input to the differential gain amplifier ADCO ADCO or ADC2 ADC2 the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion This figure can be subtracted from subsequent conversions with the same gain setting to reduce offset error to below 1 LSW The on chip temperature sensor is selected by writing the code 1111 to the MUX3 0 bits in ADMUX register when the ADC4 channel is used as an ADC input The ADC is enabled by setting the ADC Enable bit ADEN in ADCSRA Voltage reference and input channel selections will not go into effect until ADEN
4. Calibration Frequency Vcc Temperature Accuracy Factory 8 0 MHz 3V 25 C 1 Calibration User Calibration 7 3 8 1 MHz 2 7V 5 5V 40 C 125 C 14 23 Typical Characteristics 7598G AVR 03 08 The data contained in this section is extracted from preliminary silicon characterization and will be updated upon final characterization The following charts show typical behavior These figures are not tested during manufacturing All current consumption measurements are performed with all I O pins configured as inputs and with internal pull ups enabled A sine wave generator with railtorail output is used as clock source The power consumption in Power down mode is independent of clock selection The current consumption is a function of several factors such as operating voltage operating frequency loading of I O pins switching rate of I O pins code executed and ambient tempera ture The dominating factors are operating voltage and frequency The current drawn from capacitive loaded pins may be estimated for one pin as CL VCC f where CL load capacitance VCC operating voltage and f average switching frequency of I O pin The parts are characterized at frequencies higher than test limits Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates The difference between current consumption in Power down mode with Watchdog Timer enabled and Power down mo
5. Figure 18 7 ADC Timing Diagram Free Running Conversion One Conversion Next Conversion Cycle Number ADC Clock i t ADSC f f I I ADIF l ADCH x Sign and MSB of Result 7 l ADCL LSB of Result T Conversion E a us DL Sample amp Hold Complete MUX and REFS Update n2 ATtiny25 45 85 7598G AVR 03 08 Table 18 1 ADC Conversion Time Sample amp Hold Cycles Total Conversion Time Condition from Start of Conversion Cycles First conversion 13 5 25 Normal conversions 1 5 13 Auto Triggered conversions 2 13 5 18 5 Changing Channel or Reference Selection The MUX3 0 and REFS2 0 bits in the ADMUX Register are single buffered through a tempo rary register to which the CPU has random access This ensures that the channels and voltage reference selection only takes place at a safe point during the conversion The channel and volt age reference selection is continuously updated until a conversion is started Once the conversion starts the channel and voltage reference selection is locked to ensure a sufficient sampling time for the ADC Continuous updating resumes in the last ADC clock cycle before the conversion completes ADIF in ADCSRA is set Note that the conversion starts on the following rising ADC clock edge after ADSC is written The user is thus advised not to write new channel or voltage reference selection values to ADMUX until one ADC clock cycle after ADSC is
6. ssssssssssssseseseeeeeeeee nennen nennen nennen nene 4 2 9 IN DescripliOlis io e cree rere E Drei ni rx eiie esce NL IEEE DUE 5 3 About Code Examples a oeeiieseseiee seran tror bn ausu Re pepe keel nd ino ndo dora Ex ErKEEE 5 4 AVR CGPUCOTe 5 A Miei ne 5 4 2 Architectural Overview i2 it ttes mao te brennen e tbe gla ceu uri iaaa 6 4 3 ALU Arithmetic Logic Unit aii rct eate itte dente teet 7 4 4 Stat s Register narret re paa etr ain e Renatus 7 4 5 General Purpose Register File essssssseseseeeeeeeenen nennen 9 4 6 Stack Polhlter 2 in eec e asit Ere rd eei te tabe rat ek 10 4 7 Instruction Execution Timing esses enne 10 4 8 Reset and Interrupt Handling sesseeeenn enne 11 5 AVR ATtiny25 45 85 Memories eeeeee esses n nennen nennt 13 5 1 In System Re programmable Flash Program Memory ssseseesee 13 5 2 SRAM Data Memory iioii ara Fete e eae e ena ee ea xke euer ak 14 5 3 EEPROM Data Memory sess enne nennen nennen nne 15 5 4 VO MOM OLY 21 6 System Clock and Clock Options 1cccccccccccccccccsessssesnssssssnsenesereseees 21 6 1 Clock Systems and their Distribution ssssseeeeneen 21 6 2 CIOCK SOURCES itc dire tote tein deu ea ce etna orc ped edes 23 6 3 Default Clock Source ssssssssssssesessseseeeeeeeeneee
7. sts USICR r16 sts USICR r17 sts USICR r16 sts USICR r17 sts USICR r16 sts USICR r17 sts USICR r16 sts USICR r17 sts USICR r16 sts USICR r17 sts USICR r16 sts USICR r17 sts USICR rl16 LSB sts USICR r17 lds r16 USIDR ret 16 2 3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave init ldi r16 1 USIWMO 1 lt lt USICS1 sts USICR r16 SlaveSPITransfer sts USIDR r16 ldi r16 1 USIOIF sts USISR r16 SlaveSPITransfer loop lds r16 USISR sbrs r1l6 USIOIF rjmp SlaveSPITransfer loop lds r16 USIDR ret The code is size optimized using only eight instructions ret The code example assumes that the DO is configured as output and USCK pin is configured as input in the DDR Register The value stored in register r16 prior to the function is called is transferred to the master device and when the transfer is completed the data received from the Master is stored back into the r16 Register Note that the first two instructions is for initialization only and needs only to be executed once These instructions sets Three wire mode and positive edge Shift Register clock The loop is repeated until the USI Counter Overflow Flag is set AMEL s 7598G AVR 03 08 16 2 4 98 AMEL Two wire Mode The USI Two wire mode is compliant to the Inter IC TWI bus protocol but without slew rate lim iting on outputs and input noise filtering Pin names used by th
8. AMEL 161 7598G AVR 03 08 AMEL 23 5 Pin Driver Strength Figure 23 19 I O Pin Source Current vs Output Voltage Vec 1 8V VO PIN SINK CURRENT vs OUTPUT VOLTAGE Veg 1 8V lo mA Figure 23 20 I O Pin Source Current vs Output Voltage Vec 3V VO PIN OUTPUT VOLTAGE vs SINK CURRENT Vcc 3 0V lo V 162 ATtiny25 45 65 sue 7598G AVR 03 08 Figure 23 21 I O Pin Source Current vs Output Voltage Voc 5V VO PIN OUTPUT VOLTAGE vs SINK CURRENT Vcc 5 0V Figure 23 22 I O Pin Sink Current vs Output Voltage Voc 1 8V VO PINSOURCE CURRENT vs OUTPUT VOLTAGE Voc 1 8V AMEL 163 7598G AVR 03 08 AMEL Figure 23 23 O Pin Sink Current vs Output Voltage Vec 3V VO PIN OUTP UT VOLTAGE vs SOURCE CURRENT Vcc 3V lo mA Figure 23 24 I O Pin Sink Current vs Output Voltage Voc 5 0V VO PIN OUTPUT VOLTAGE vs SOURCE CURRENT Vcc 5 0V 40 25 85 125 20 25 lo mA 164 ATtiny25 45 05 memme 7598G AVR 03 08 7598G AVR 03 08 23 6 Pin Thresholds and Hysteresis Figure 23 25 I O Pin Input Threshold Voltage vs Vcc VIH I O Pin Read As 1 VO PIN INPUT THRESHOLD VOLTAGE vs Vc VIH IO PN READ AS 40 C 25 C 85 C 25 125 G Threshold Figure 23 26 O Pin Input Threshold Voltage vs Vec VIL
9. SEATING Al PLANE TITLE Atmel Nantes S A AME La Chantrerie BP 70602 T5 8 Lead 0 208 Body Width 34508 Nantes Cedex sis Francs Plastic Gull Wing Small Outline Package SOIC TS 184 ATtiny25 45 65 su ATtiny25 45 85 27 2 PC EATING PLANE o 10 C 1 00 REF co 15 4x J TOP VIEW 4 DRAWINGS NUT SCALED SIDE VIEW COMMON DIMENSIONS IN MM NOTES he Option A Option B tion SEE OPTION A B C BOTTOM VIEW Pin 1 Chamfer Pin 1 Notch Pin 1 cC 0 30 X0 20 R Triangle Compliant JEDEC Standard MO 220 variation WGGD 5 07 26 07 TITLE DRAWING No REV ATEL Amel Nantes S TOROS PC 20 Lead 4 0x4 0 mm Body 0 50 mm Pitch 44306 Nantes Cedex 3 France Quad Flat No Lead Package QFN PC G AMEL 185 7598G AVR 03 08 AMEL 28 Document Revision History 28 1 28 2 28 3 28 4 28 5 28 6 28 7 186 Rev 7598G 03 08 1 Modified Power Management and Sleep Modes on page 30 Modified MCU Control Register MCUCR on page 31 Modified Active Clock Domains and Wake up Sources in the Different Sleep Modes 33 Added Limitations on page 33 Modified Power Reduction Register on page 33 cO RON Rev 7598F 11 07 1 Correction to ICC Active Table 22 1 on page 147 Rev 7598E 03 07 1 POR updated see Section 8 0 3 on page
10. ATtiny25 45 05 memme 7598G AVR 03 08 12 1 1 Registers 12 1 2 Definitions 7598G AVR 03 08 ATtiny25 45 85 Figure 12 1 8 bit Timer Counter Block Diagram TOVn Int Req Clock Select Edge Detector uo Ls From Prescaler Timer Counter OCnA Int Req Waveform OCnA Generation OCnB Int Req isi Generation p H p DATA BUS TCCRnA TCCRnB The Timer Counter TCNTO and Output Compare Registers OCROA and OCROB are 8 bit registers Interrupt request abbreviated to Int Req in the figure signals are all visible in the Timer Interrupt Flag Register TIFR All interrupts are individually masked with the Timer Inter rupt Mask Register TIMSK TIFR and TIMSK are not shown in the figure The Timer Counter can be clocked internally via the prescaler or by an external clock source on the TO pin The Clock Select logic block controls which clock source and edge the Timer Counter uses to increment or decrement its value The Timer Counter is inactive when no clock source is selected The output from the Clock Select logic is referred to as the timer clock clky9 The double buffered Output Compare Registers OCROA and OCROB is compared with the Timer Counter value at all times The result of the compare can be used by the Waveform Gen erator to generate a PWM or variable frequency output on the Output Compare pins
11. z4 None 3 SPM Store Program Memory z R1 RO None IN Rd P In Port Rd P None 1 OUT P Rr Out Port P lt Rr None 1 PUSH Rr Push Register on Stack STACK lt Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep function None 1 WDR Watchdog Reset see specific descr for WDR Timer None 1 BREAK Break For On chip Debug Only None N A i 5 ATtinY25 45 85 su 26 Ordering Information Power Supply Speed MHz Ordering Code Package Operation Range ATtiny25 45 85 15ST Automotive 40 C to 85 C 2 7 5 5V 8 16 ATtiny25 45 85 15ST1 T5 Automotive 40 C to 105 C ATtiny25 45 85 15SZ Automotive 40 C to 125 C ATtiny25 45 85 15MT Automotive 40 C to 85 C 2 7 5 5V 8 169 ATtiny25 45 85 15MT1 PC Automotive 40 C to 105 C ATtiny25 45 85 15MZ Automotive 40 C to 125 C Notes 1 Green and ROHS packaging 2 Tape and Reel with Dry pack delivery 3 For Speed vs Vcc see Figure 22 2 on page 149 Package Type T5 8 lead 0 208 Body Width T5 Plastic Gull Wing Small Outline Package PC 20 lead 4 0x4 0 mm Body 0 50 mm Pitch PC Quad Flat No Lead Package QFN 7598G AVR 03 08 AMEL 183 AMEL 27 Packaging Information 27 1 T5 Q eg Aw E1 D e A BASE r PLANE
12. ATtiny25 45 05 sue Bit 5 ADATE ADC Auto Trigger Enable When this bit is written to one Auto Triggering of the ADC is enabled The ADC will start a con version on a positive edge of the selected trigger signal The trigger source is selected by setting the ADC Trigger Select bits ADTS in ADCSRB Bit 4 ADIF ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I bit in SREG are set ADIF is cleared by hardware when executing the corresponding interrupt handling vector Alternatively ADIF is cleared by writing a logical one to the flag Beware that if doing a Read Modify Write on ADCSRA a pending interrupt can be disabled This also applies if the SBI and CBI instructions are used Bit 3 ADIE ADC Interrupt Enable When this bit is written to one and the I bit in SREG is set the ADC Conversion Complete Inter rupt is activated Bits 2 0 ADPS2 0 ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC Table 18 5 ADC Prescaler Selections ADPS2 ADPS1 ADPSO Division Factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 18 7 7 The ADC Data Register ADCL and ADCH 18 7 7 1 ADLAR 0 18 7 7 2 ADLAR 1 7598G AVR 03 08 Bit 15 14 13 12 11 10 9
13. C 0 then PC PC k 1 None 1 2 BRSH k Branch if Same or Higher if C 0 then PC PC k 1 None 1 2 BRLO k Branch if Lower if C 1 then PC PC k 1 None 1 2 BRMI k Branch if Minus if N 1 then PC PC k 1 None 1 2 BRPL k Branch if Plus if N 0 then PC PC k 1 None 1 2 BRGE k Branch if Greater or Equal Signed if N V 0 then PC e PC k 1 None 12 BRLT k Branch if Less Than Zero Signed if N V 1 then PC PC k 1 None 1 2 BRHS k Branch if Half Carry Flag Set if H 1 then PC PC k 1 None 1 2 BRHC k Branch if Half Carry Flag Cleared if H 0 then PC PC k 1 None 1 2 BRTS k Branch if T Flag Set if T 1 then PC PC k 1 None 1 2 BRTC k Branch if T Flag Cleared if T 0 then PC PC k 1 None 1 2 BRVS k Branch if Overflow Flag is Set if V 1 then PC PC k 1 None 1 2 BRVC k Branch if Overflow Flag is Cleared if V 0 then PC PC k 1 None 1 2 BRIE k Branch if Interrupt Enabled if l 1 then PC PC k 1 None 1 2 BRID k Branch if Interrupt Disabled if 1 2 0 then PC PC k 1 None 1 2 BIT AND BIT TEST INSTRUCTIONS SBI P b Set Bit in I O Register VO P b 1 None 2 CBI P b Clear Bit in I O Register VO P b 0 None 2 LSL Rd Logical Shift Left Rd n 1 Rd n Rd 0 0 Z C N V 1 LSR Rd Logical Shift Right Rd n Rd n 1 Rd 7 0 Z C N V 1 ROL Rd Rotate Left Through Carr Rd 0 lt C Rd n 1 lt Rd n C lt Rd 7 Z C N V 1 ANMEL 181 AIMEL
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15. DEAD TIME GENERATOR DEAD TIME GENERATOR TIMER INT MASK REGISTER TIMSK T C CONTROL REGISTER 1 TCCR1 GLOBAL T C CONTROL REGISTER GTCCR lt 5 o e TIMER COUNTER1 TIMER COUNTER1 T C CLEAR T C1 CONTROL lt TCNT1 ae LOGIC q 8 BIT E T C1 OUTPUT COMPARE REGISTER OCR1B COM1BO a FOCIE 8 BIT COMPARATOR T C1 OUTPUT COMPARE REGISTER OCR1A 8 BIT COMPARATOR T C1 OUTPUT COMPARE REGISTER OCR1C 8 BIT DATABUS Three status flags overflow and compare matches are found in the Timer Counter Interrupt Flag Register TIFR Control signals are found in the Timer Counter Control Registers TCCR1 and GTCCR The interrupt enable disable settings are found in the Timer Counter Interrupt Mask Register TIMSK The Timer Counter1 contains three Output Compare Registers OCR1A OCR1B and OCR1C as the data source to be compared with the Timer Counter1 contents In normal mode the Out put Compare functions are operational with all three output compare registers OCR1A determines action on the OC1A pin PB1 and it can generate Timer1 OC1A interrupt in normal mode and in PWM mode Likewise OCR1B determines action on the OC1B pin PB3 and it can generate Timer1 OC1B interrupt in normal mode and in PWM mode OCRIC holds the Timer Counter maximum value i e the clear on compare match value In the normal mode an overflow interrupt TOV1
16. EEPROM in the address given by the EEAR Register For the EEPROM read operation the EEDR contains the data read out from the EEPROM at the address given by EEAR 5 3 5 EEPROM Control Register EECR Bit 7 6 5 4 3 2 1 0 LLL LEewrTeewe EERIE EEMPE EEPE EERE EECR Read Write R R R W R W R W R W R W R W Initial Value 0 0 X X 0 0 X 0 Bit 7 Res Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny25 45 85 For compatibility with future AVR devices always write this bit to zero After reading mask out this bit Bit 6 Res Reserved Bit This bit is reserved in the ATtiny25 45 85 and will always read as zero Bits 5 4 EEPM1 and EEPMO EEPROM Programming Mode Bits The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE It is possible to program data in one atomic operation erase the old value and program the new value or to split the Erase and Write operations in two different 16 ATtiny25 45 05 memme operations The Programming times for the different modes are shown in Table 5 1 While EEPE is set any write to EEPMn will be ignored During reset the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming Table 5 1 EEPROM Mode Bits Programming EEPM1 EEPMO Time Operation 0 0 3 4 ms Erase and Write in one operation Atomic Operation 0 1 1 8 ms Erase Only 1 0 1 8 ms Write Only 1 1 Reser
17. If the ADC is enabled a conversion starts automatically when this mode is entered ADC Noise Reduction Mode When the SM1 0 bits are written to 01 the SLEEP instruction makes the MCU enter ADC Noise Reduction mode stopping the CPU but allowing the ADC the external interrupts and the Watchdog to continue operating if enabled This sleep mode halts clkyo clkgpy and clke Asi while allowing the other clocks to run This improves the noise environment for the ADC enabling higher resolution measurements If the ADC is enabled a conversion starts automatically when this mode is entered Apart form the ADC Conversion Complete interrupt only an External Reset a Watchdog Reset a Brown out Reset an SPM EEPROM ready interrupt an external level interrupt on INTO or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode Power down Mode When the SM1 0 bits are written to 10 the SLEEP instruction makes the MCU enter Power down mode In this mode the Oscillator is stopped while the external interrupts and the Watch dog continue operating if enabled Only an External Reset a Watchdog Reset a Brown out Reset an external level interrupt on INTO or a pin change interrupt can wake up the MCU This sleep mode halts all generated clocks allowing operation of asynchronous modules only ATtiny25 45 05 memm 7598G AVR 03 08 Note that if a level triggered interrupt is used for wake up from Power down mode the chang
18. T2 and T1 2 T2 before the new clock frequency is active In this interval 2 active clock edges are produced Here T1 is the previous clock period and T2 is the period corresponding to the new prescaler setting 7 Power Management and Sleep Modes 30 The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications Sleep modes enable the application to shut down unused modules in the MCU thereby saving power The AVR provides various sleep modes allowing the user to tailor the power consump tion to the application s requirements ATtiny25 45 05 H 7598G AVR 03 08 To enter any of the three sleep modes the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed The SM1 0 bits in the MCUCR Register select which sleep mode Idle ADC Noise Reduction or Power down will be activated by the SLEEP instruc tion See Table 7 1 for a summary If an enabled interrupt occurs while the MCU is in a sleep mode the MCU wakes up The MCU is then halted for four cycles in addition to the start up time executes the interrupt routine and resumes execution from the instruction following SLEEP The contents of the Register File and SRAM are unaltered when the device wakes up from sleep If a reset occurs during sleep mode the MCU wakes up and executes from the Reset Vector Figure 6 1 on page 21 presents the different clock systems in t
19. respectively of an inverting amplifier which can be con figured for use as an On chip Oscillator as shown in Figure 6 3 Either a quartz crystal or a ceramic resonator may be used C1 and C2 should always be equal for both crystals and resonators The optimal value of the capacitors depends on the crystal or resonator in use the amount of stray capacitance and the electromagnetic noise of the environment Some initial guidelines for choosing capacitors for use with crystals are given in Table 6 3 For ceramic resonators the capacitor values given by the manufacturer should be used Figure 6 3 Crystal Oscillator Connections 2 c NN XTAL2 eS T XTAL1 e GND The Oscillator can operate in three different modes each optimized for a specific frequency range The operating mode is selected by the fuses CKSEL3 1 as shown in Table 6 3 Table 6 3 Crystal Oscillator Operating Modes Recommended Range for Capacitors C1 and CKSEL3 1 Frequency Range MHz C2 for Use with Crystals pF 100 0 4 0 9 101 0 9 3 0 12 22 110 3 0 8 0 12 22 111 8 0 12 22 Notes 1 This option should not be used with crystals only with ceramic resonators The CKSELO Fuse together with the SUT1 0 Fuses select the start up times as shown in Table 6 4 n ATtiNY25 45 85 memme Table 6 4 Start up Times for the Crystal Oscillator Clock Selection Start up Time f
20. 0 PRELIMINARY Symbol Parameter Condition Min Typ Max Units Resolution Single Ended Conversion 10 Bits Single Ended Conversion Vner 4V Vec 4V 2 LSB ADC clock 200 kHz Single Ended Conversion VREF 4V Vec 4V 3 LSB ADC clock 1 MHz Absolute accuracy Including INL DNL quantization error UE yes nud ain and offset error REF TNs oo FON ADC clock 200 kHz de Se Noise Reduction Mode Single Ended Conversion VREF 4V Vec 4V ADC clock 1 MHz 29 LSB Noise Reduction Mode Single Ended Conversion Integral Non linearity INL Vrer 4V Voc 4V 1 LSB ADC clock 200 kHz Single Ended Conversion Differential Non linearity DNL Vper 4V Vec 4V 0 5 LSB ADC clock 200 kHz Single Ended Conversion Gain Error Vrer 4V Voc 4V 2 5 LSB ADC clock 200 kHz Single Ended Conversion Offset Error Vrer 4V Voc 4V 1 5 LSB ADC clock 200 kHz Conversion Time Free Running Conversion 13 260 us Clock Frequency 50 1000 kHz AVCC Analog Supply Voltage Voc 0 32 Voc 0 389 V Vin Input Voltage GND Vgage 50mV V Input Bandwidth 38 5 kHz Vint Internal Voltage Reference 1 0 1 1 1 2 V Rain Analog Input Resistance 100 MO Note 1 All DC Characteristics contained in this data sheet result from actual silicon characterization 2 Minimum for AVCC is 2 7V 3 Maximum for AVCC is 5 5V so ATtiny25 45 65 memm 22 5 Calibrated RC Oscillator Accuracy Table 22 4 Calibration Accuracy of Internal RC Oscillator
21. 0 1 1 1 1 0 1 1 1 1 Note 1 If selected one of the valid settings below 0b1010 will be used AMEL 43 AMEL The following code example shows one assembly and one C function for turning off the WDT The example assumes that interrupts are controlled e g by disabling interrupts globally so that no interrupts will occur during execution of these functions Assembly Code Example WDT off WDR Clear WDRF in MCUSR ldi r16 0 lt lt WDRF out MCUSR r16 Write logical one to WDCE and WDE Keep old prescaler setting to prevent unintentional Watchdog Reset in r16 WDTCR ori r16 1 lt lt WDCE 1 lt lt WDE out WDTCR r16 Turn off WDT ldi r16 0 WDE out WDTCR r16 ret C Code Example void WDT off void _WDR Clear WDRF in MCUSR MCUSR 0x00 Write logical one to WDCE and WDE WDTCR 1 lt lt WDCE 1 WDE Turn off WDT WDTCR 0x00 Note 1 The example code assumes that the part specific header file is included 8 3 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels Separate procedures are described for each level 8 3 1 Safety Level 1 In this mode the Watchdog Timer is initially disabled but can be enabled by writing the WDE bit to one without any restriction A timed sequence is needed when disabling an enabled Wat
22. 0 X Output No Output Low Sink 1 1 X Output No Output High Source 10 2 4 Reading the Pin Value 7598G AVR 03 08 Independent of the setting of Data Direction bit DDxn the port pin can be read through the PINxn Register bit As shown in Figure 10 2 the PINxn Register bit and the preceding latch con stitute a synchronizer This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock but it also introduces a delay Figure 10 3 shows a timing dia gram of the synchronization when reading an externally applied pin value The maximum and minimum propagation delays are denoted t max and tog min respectively Figure 10 3 Synchronization when Reading an Externally Applied Pin value systemclkK ff INSTRUCTIONS Xx XXX X 7 PINK SYNC LATCH i ZZ PINxn r17 i 0x00 OxFF AMEL s AMEL Consider the clock period starting shortly after the first falling edge of the system clock The latch is closed when the clock is low and goes transparent when the clock is high as indicated by the shaded region of the SYNC LATCH signal The signal value is latched when the system clock goes low It is clocked into the PINxn Register at the succeeding positive clock edge As indi cated by the two arrows tpd max and tpd min a single signal transition on the pin will be delayed between 1 2 and 11 2 system clock period depending upon the time of assertion When reading back a
23. 1A OCF1A is cleared by hardware when executing the corresponding interrupt handling vector Alternatively OCF1A is cleared after synchroniza tion clock cycle by writing a logic one to the flag When the I bit in SREG OCIE1A and OCF1A are set one the Timer Counter1 A compare match interrupt is executed Bit 5 OCF1B Output Compare Flag 1B The OCF1B bit is set one when compare match occurs between Timer Counter1 and the data value in OCR1B Output Compare Register 1A OCF1B is cleared by hardware when executing the corresponding interrupt handling vector Alternatively OCF1B is cleared after synchroniza tion clock cycle by writing a logic one to the flag When the I bit in SREG OCIE1B and OCF1B are set one the Timer Counter1 B compare match interrupt is executed Bit2 TOV1 Timer Counter1 Overflow Flag In normal mode PWM1A 0 and PWM1B 0 the bit TOV1 is set one when an overflow occurs in Timer Counter1 The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vector Alternatively TOV1 is cleared after synchronization clock cycle by writing a logical one to the flag 86 ATtiny25 45 05 memme 14 1 9 In PWM mode either PWM1A 1 or PWM1B 1 the bit TOV1 is set one when compare match occurs between Timer Counter1 and data value in OCR1C Output Compare Register 1C Clearing the Timer Counter1 with the bit CTC1 does not generate an overflow When the SREG I bit and TOIE1 Timer Co
24. 1V 2 56V ADC Voltage Reference Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Cancele Unipolar Bibilar Input Mode Input Polarity Reversal Mode The ATtiny25 45 85 features a 10 bit successive approximation ADC The ADC is connected to a 4 channel Analog Multiplexer which allows one differential voltage input and four single ended voltage inputs constructed from the pins of Port B The differential input PB3 PB4 or PB2 PB5 is equipped with a programmable gain stage providing amplification step of 26 dB 20x on the differential input voltage before the A D conversion The single ended voltage inputs refer to OV GND The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion A block diagram of the ADC is shown in Figure 18 1 AMEL 107 18 2 Operation AMEL Internal voltage references of nominally 1 1V or 2 56V are provided On chip and these voltage references can optionally be externally decoupled at the AREF PBO pin by a capacitor for bet ter noise performance Alternatively Vcc can be used as voltage reference for single ended channels There is also an option to use an external voltage reference and turn off the internal voltage reference These options are selected using the REFS2 0 bits of the ADMUX control register Figure 18 1 A
25. 256 From prescaler 1 0 1 Clkyo 1024 From prescaler 1 1 0 External clock source on TO pin Clock on falling edge 1 1 1 External clock source on TO pin Clock on rising edge If external pin modes are used for the Timer Counter0 transitions on the TO pin will clock the counter even if the pin is configured as an output This feature allows software control of the counting 12 8 3 Timer Counter Register TCNTO Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Timer Counter Register gives direct access both for read and write operations to the Timer Counter unit 8 bit counter Writing to the TCNTO Register blocks removes the Compare Match on the following timer clock Modifying the counter TCNTO while the counter is running introduces a risk of missing a Compare Match between TCNTO and the OCROx Registers 12 8 4 Output Compare Register A OCROA Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 AMEL rs 7598G AVR 03 08 AMEL The Output Compare Register A contains an 8 bit value that is continuously compared with the counter value TCNTO A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OCOA pin 12 8 5 Output Compare Register B OCROB Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Output Comp
26. 36 Rev 7598D 02 07 1 Clarification of Power On Reset Specifications table Table 8 1 on page 37 2 Errata list updated 3 Added QFN packages Rev 7598C 09 06 1 Correction of package codification and drawings Rev 7598B 08 06 1 Clarification of several TBD values 2 Addition of the Power On Reset specification 3 DCcharacteristics Limits completed after corner run characterization 4 Typical Characteristic curves produced Changes from Rev 2535A 09 01 to Rev 7598A 04 06 1 Automotive grade created Features Change voltage and temperature range 2 7V 5 5V 40 C 125 C Adapt Stand by current to automotive temperature range Packages PDIP removed Ordering info limited to Automotive versions green only dry pack DC amp AC parameters Only PRELIMINARY values are produced ATtiny25 45 05 memme 29 Errata The revision letter in this section refers to the revision of the ATtiny25 45 85 device 29 1 ATtiny25 Rev E 1 No known errata Flash security improvements 29 2 ATtiny45 Rev G 1 No known errata Flash security improvements 29 3 ATtiny85 Rev C 1 No known errata Flash security improvements AMEL 187 7598G AVR 03 08 gl M 1 1 Pin Configurations ger 2 OVW E AEE E EA E E EE AT 2 2 1 Block DIagrarm uei edi itte ANET dett cdi cea TRA EATEN uda eda 3 2 2 Automotive Quality Grade
27. 5 LSB 18 7 ADC Conversion Result After the conversion is complete ADIF is high the conversion result can be found in the ADC Result Registers ADCL ADCH The form of the conversion result depends on the type of the conversio as there are three types of conversions single ended conversion unipolar differential conversion and bipolar differential conversion 18 7 1 Single Ended Conversion For single ended conversion the result is Vy 1024 AD Rl cs REF where Vy is the voltage on the selected input pin and Vpger the selected voltage reference see Table 18 3 on page 119 and Table 18 4 on page 120 0x000 represents analog ground and Ox3FF represents the selected voltage reference minus one LSB The result is presented in one sided form from Ox3FF to 0x000 18 7 2 Unipolar Differential Conversion If differential channels and an unipolar input mode are used the result is _ Vpos Vygg 1024 VREF ADC GAIN where Vros is the voltage on the positive input pin VNec the voltage on the negative input pin and Vref the selected voltage reference see Table 18 3 on page 119 and Table 18 4 on page AMEL 117 7598G AVR 03 08 AMEL 120 The voltage on the positive pin must always be larger than the voltage on the negative pin or otherwise the voltage difference is saturated to zero The result is presented in one sided form from 0x000 0d to 0x3FF 1023d The GAIN is either 1x or 20x 18 7 3 Bipolar Different
28. 8 IL LL LLL Le usen Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 When accessing the USI Data Register USIDR the Serial Register can be accessed directly If a serial clock occurs at the same cycle the register is written the register will contain the value written and no shift is performed A left shift operation is performed depending of the USICS1 0 bits setting The shift operation can be controlled by an external clock edge by a Timer CounterO Compare Match or directly by software using the USICLK strobe bit Note that even when no wire mode is selected USIWM1 0 0 both the external data input DI SDA and the external clock input USCK SCL can still be used by the Shift Register The output pin in use DO or SDA depending on the wire mode is connected via the output latch to the most significant bit bit 7 of the Data Register The output latch is open transparent dur ing the first half of a serial clock cycle when an external clock source is selected USICS1 1 and constantly open when an internal clock source is used USICS1 0 The output will be ATtiny25 45 8 5 memme changed immediately when a new MSB written as long as the latch is open The latch ensures that data input is sampled and data output is changed on opposite clock edges Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the Shift Register 16 4 2 USI Buffe
29. 8 CK 8 82 ATtiny25 45 85 Ex M 7598G AVR 03 08 Table 14 2 Timer Counter1 Prescale Select Continued Asynchronous Synchronous CS13 CS12 CS11 CS10 Clocking Mode Clocking Mode 0 1 0 1 PCK 16 CK 16 0 1 1 0 PCK 32 CK 32 0 1 1 1 PCK 64 CK 64 1 0 0 0 PCK 128 CK 128 1 0 0 1 PCK 256 CK 256 1 0 1 0 PCK 512 CK 512 1 0 1 1 PCK 1024 CK 1024 1 1 0 0 PCK 2048 CK 2048 1 1 0 1 PCK 4096 CK 4096 1 1 1 0 PCK 8192 CK 8192 1 1 1 1 PCK 16384 CK 16384 The Stop condition provides a Timer Enable Disable function 14 1 2 General Timer Counter1 Control Register GTCCR Bit 7 6 5 4 3 2 1 0 2C 4C TSM PWMIB COM1B1 COM1BO FOC1B FOC1A PSR1 PSRO GTCCR Read Write R W R W R W R W W Ww R W R W Initial value 0 0 0 0 0 0 0 0 Bit 6 PWM1B Pulse Width Modulator B Enable When set one this bit enables PWM mode based on comparator OCR1B in Timer Counter1 and the counter value is reset to 00 in the CPU clock cycle after a compare match with OCR1C register value Bits 5 4 COM1B1 COM1BO Comparator B Output Mode Bits 1 and 0 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer Counter1 Output pin actions affect pin PB3 OC1B Since this is an alternative function to an I O port the corresponding direction control bit must be set one in order to control an out
30. DEAD TIME PRESCALER CLOCK CONTROL ee ee The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register and selecting then the dead time value in I O register DT1x The DT1x register consists of two 4 bit fields DT1xH and DT1xL that control the dead time periods of the PWM output and its complementary output separately Thus the rising edge of OC1x and OC1x can have different dead time periods The dead time is adjusted as the number of prescaled dead time generator clock cycles AMEL o 7598G AVR 03 08 AMEL Figure 15 3 The Complementary Output Pair 1 i 1 I 1 PWM1x i L l l 1 L I l OC1x i ji i 4 i i A i i l I l 1 x AorB 1 lt lt t non overlap rising edge t non overlap falling edge 15 0 1 Timer Counter1 Dead Time Prescaler register 1 DTPS1 Bit 7 6 5 4 3 2 1 0 565 D O_o bres Read Write R R R R R R R W R W Initial value 0 0 0 0 0 0 0 0 The dead time prescaler register DTPS1 is a 2 bit read write register Bits 1 0 DTPS1 Timer Counter1 Dead Time Prescaler register 1 The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer Counter1 clock PCK or Ck by 1 2 4 or 8 providing a large range of dead times that can be generated The Dead Time prescaler is controlled by two bits DTPS11 10 from the Dead Time Prescaler register These bits def
31. Frequency Range Min Frequency in Percentage of Max Frequency in Percentage of OSCCAL Value Nominal Frequency Nominal Frequency 0x00 5096 10096 Ox3F 75 150 Ox7F 10096 20096 External Clock To drive the device from an external clock source CLKI should be driven as shown in Figure 6 4 To run the device on an external clock the CKSEL Fuses must be programmed to 00 Figure 6 4 External Clock Drive Configuration EXTERNAL CLOCK CLKI SIGNAL GND When this clock source is selected start up times are determined by the SUT Fuses as shown in Table 6 9 Table 6 9 Start up Times for the External Clock Selection Start up Time from Power Additional Delay from SUT1 0 down and Power save Reset Recommended Usage 00 6 CK 14CK BOD enabled 01 6 CK 14CK 4 ms Fast rising power 10 6 CK 14CK 4 64 ms Slowly rising power 11 Reserved Note that the System Clock Prescaler can be used to implement run time changes of the internal clock frequency while still ensuring stable operation Refer to System Clock Prescaler on page 29 for details AMEL 27 6 7 1 6 8 6 9 28 AMEL High Frequency PLL Clock PLLo There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer Counter1 and for the system clock source When selected as a system clock source by programming the CKSEL fuses to 0001 it is divided by
32. Fuse Low High bits and Lock bits are shown in Table 21 16 Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in Table 21 16 Power off sequence Set SCI to 0 Set RESET to 1 Turn Voc power off ATtiny25 45 85 memm Table 21 16 High voltage Serial Programming Instruction Set for ATtiny25 45 85 Instruction Format Instruction Instr 1 5 Instr 2 6 Instr 3 Instr 4 Operation Remarks SD 0 1000 0000 00 0 0000 0000 00 0 0000 0000 00 Wait after Instr 3 until SDO goes Chip Erase SII O0 0100 1100 00 O0 0110 0100 00 O0 0110 1100 00 high for the Chip Erase cycle to SD X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX finish O SD Load Write 0 0001 0000 00 Flash SII O0 0100 1100 00 Enter Flash Programming code Command SD X XXXX XXXX XX O SD Q bbbb bbbb Repeat after Instr 1 5 until the l 00 0_eeee_eeee_00 0_dddd_dddd_00 0_0000_0000_00 ies nace buffer alice or unti sll 0_0000_1100_00 9000101100209 ee ee all data within the page is filled SD X 000 3000 XX X XXXX XXXX XX X XXXX XXXX XX X XXXX XXXX XX See Note 1 Load Flash O Page Buffer SD l 0_0000_0000_00 SII 0_0111_1100_00 Instr 5 SD X_XXXX_XXXX_XX O SD Wait after Instr 3 until SDO goes Load Flash 0 0000 000a 00 0 0000 0000 00 0 0000 0000 00 high Repeat Instr 2 3 for each ac eae SII 0 0
33. I O Pin Read As 0 VO PIN INPUT THRESHOLD VOLTAGE vs Vcc VL IO PN READ AS 0 125 C 25 85 C 25 C 40 C 2 3 15 4 o D ZI FE 0 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 AMEL 165 AMEL Figure 23 27 O Pin Input Hysteresis vs Vec VO PIN INPUT HYSTERESIS 0 8 I I TI T 1T T 0 7 0 6 g 05 o K o 0 4 25 C ah bM 2st i 125 C 0 1 il 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Figure 23 28 Reset Input Threshold Voltage vs Voc VIH Reset Pin Read As 1 RESET INPUT THRESHOLD VOLTAGE vs Vcc VH O PN READ AS 1 125 C 2 5 85 C 25 C 40 C 2 3 15 A o D E LE 0 5 0 1 5 2 2 5 3 3 5 4 45 5 5 5 1 6 ATtiny25 45 05 mememe 7598G AVR 03 08 ATtiny25 45 85 Figure 23 29 Reset Input Threshold Voltage vs Vec VIL Reset Pin Read As 0 RESET INPUT THRESHOLD VOLTAGE vs oc VL O PN READ AS 0 125 C 2 5 85 C 25 C 40 C EN a Threshold 0 5 Voc V Figure 23 30 Reset Input Pin Hysteresis vs Vec RESET INPUT THRESHOLD VOLTAGE vs o VH O PN READ AS 1 0 251 0 2 4 e E c Thres hold e ab 0 05 AMEL 167 7598G AVR 03 08 AMEL 23 7 BOD Thresholds and Analog Comparator Offset Figure 23 31 BOD Thresholds vs Temperature BODLEVEL Is 4 3V BOD THRESHOLDS vs
34. I O Port Control Registers DDR and PORT that are affected by the COMOx1 0 bits are shown When referring to the OCOx state the reference is for the internal OCOx Register not the OCOx pin If a system reset occur the OCOx Register is reset to 0 ATtiny25 45 05 7598G AVR 03 08 ATtiny25 45 85 Figure 12 4 Compare Match Output Unit Schematic COMnx1 COMnxo Waveform FOCn Generator OCn OCnx Pin PORT DATA BUS Clk o The general I O port function is overridden by the Output Compare OCOx from the Waveform Generator if either of the COMOx1 0 bits are set However the OCOx pin direction input or out put is still controlled by the Data Direction Register DDR for the port pin The Data Direction Register bit for the OCOx pin DDR OCOx must be set as output before the OCOx value is visi ble on the pin The port override function is independent of the Waveform Generation mode The design of the Output Compare pin logic allows initialization of the OCOx state before the out put is enabled Note that some COMOXx1 0 bit settings are reserved for certain modes of operation 8 bit Timer Counter Register Description on page 71 12 5 1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMOXx1 0 bits differently in Normal CTC and PWM modes For all modes setting the COMOx1 0 0 tells the Waveform Generator that no action on the OCOx Register is to
35. It is also erased after a system reset Note that it is not possible to write more than one time to each address without erasing the temporary buffer If the EEPROM is written in the middle of an SPM Page Load operation all data loaded will be lost 20 0 3 Performing a Page Write To execute Page Write set up the address in the Z pointer write 00000101 to SPMCSR and execute SPM within four clock cycles after writing SPMCSR The data in R1 and RO is ignored The page address must be written to PCPAGE Other bits in the Z pointer must be written to zero during this operation The CPU is halted during the Page Write operation 20 1 Addressing the Flash During Self Programming The Z pointer is used to address the SPM commands Bit 15 14 13 12 11 10 9 8 zen as za ms me CDS T T zm 7 2 IL 7 6 5 4 3 2 1 0 Since the Flash is organized in pages see Table 21 6 on page 132 the Program Counter can be treated as having two different sections One section consisting of the least significant bits is addressing the words within a page while the most significant bits are addressing the pages This is shown in Figure 20 1 Note that the Page Erase and Page Write operations are addressed independently Therefore it is of major importance that the software addresses the same page in both the Page Erase and Page Write operation The LPM instruction uses the Z pointer to store the address Since this instruction addresses t
36. PLLCSR register enables the asynchronous mode The frequency of the fast peripheral clock is 64 MHz or 32 MHz in Low Speed Mode 14 4 Timer Counter1 The Timer Counter1 general operation is described in the asynchronous mode and the opera tion in the synchronous mode is mentioned only if there are differences between these two modes Figure 14 2 shows Timer Counter 1 synchronization register block diagram and syn chronization delays in between registers Note that all clock gating details are not shown in the AMEL 7 7598G AVR 03 08 ATMEL figure The Timer Counter1 register values go through the internal synchronization registers which cause the input synchronization delay before affecting the counter operation The regis ters TCCR1 GTCCR OCR1A OCR1B and OCRIC can be read back right after writing the register The read back values are delayed for the Timer Counter1 TCNT1 register and flags OCF1A OCF1B and TOV1 because of the input and output synchronization The Timer Counter1 features a high resolution and a high accuracy usage with the lower pres caling opportunities It can also support two accurate high speed 8 bit Pulse Width Modulators using clock speeds up to 64 MHz or 32 MHz in Low Speed Mode In this mode Timer Counter1 and the output compare registers serve as dual stand alone PWMs with non overlapping non inverted and inverted outputs Refer to page 87 for a detailed description on this function Simila
37. RESET gt 1 1 CK Cycle WDT TIME OUT i l t RESET tro a TIME OUT i L INTERNAL RESET 8 0 7 MCU Status Register MCUSR 7598G AVR 03 08 The MCU Status Register provides information on which reset source caused an MCU Reset Bit 7 6 5 4 3 2 1 0 Read Write R R R R R W R W R W R W Initial Value 0 0 0 0 See Bit Description Bits 7 4 Res Reserved Bits AMEL s 8 1 8 1 1 40 AMEL These bits are reserved bits in the ATtiny25 45 85 and will always read as zero Bit 3 WDRF Watchdog Reset Flag This bit is set if a Watchdog Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 2 BORF Brown out Reset Flag This bit is set if a Brown out Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 1 EXTRF External Reset Flag This bit is set if an External Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 0 PORF Power on Reset Flag This bit is set if a Power on Reset occurs The bit is reset only by writing a logic zero to the flag To make use of the Reset Flags to identify a reset condition the user should read and then reset the MCUSR as early as possible in the program If the register is cleared before another reset occurs the source of the reset can be found by examining the Reset Flags Internal Voltage Reference ATtiny25 45 85 features a
38. Register A TCCR1 as shown in Table 14 4 Timer Counter1 acts as an up counter counting from 00 up to the value specified in the output compare register OCR1C and starting from 00 up again A compare match with OC1C will set an overflow interrupt flag TOV1 after a synchronization delay following the compare event Table 14 4 Compare Mode Select in PWM Mode COM11 COM10 Effect on Output Compare Pins OC1x not connected 9 j OC1x not connected OC1x cleared on compare match Set whenTCNT1 01 OC1x set on compare match Cleared when TCNT1 00 OC1x cleared on compare match Set when TCNT1 01 OC1x not connected OC1x Set on compare match Cleared when TCNT1 01 OC1x not connected Note that in PWM mode writing to the Output Compare Registers OCR1A or OCR1B the data value is first transferred to a temporary location The value is latched into OCR1A or OCR1B when the Timer Counter reaches OCHR1C This prevents the occurrence of odd length PWM pulses glitches in the event of an unsynchronized OCR1A or OCR1B See Figure 14 5 for an example 88 ATtiny25 45 05 J m 7598G AVR 03 08 Figure 14 5 Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value LLL IL IL IL ILU U U pPwmouputocix Compare Value changes Counter Value Compare Value TILES RH Unsynchronized OC1x Latch pa Glitch PWM Output OC1x During the
39. Running Reset 1 1 Running Interrupt Bit 4 WDCE Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero Otherwise the Watchdog will not be disabled Once written to one hardware will clear this bit after four clock cycles Refer to the description of the WDE bit for a Watchdog disable procedure This bit must also be set when changing the prescaler bits Timed Sequences for Changing the Configuration of the Watchdog Timer on page 44 Bit 3 WDE Watchdog Enable When the WDE is written to logic one the Watchdog Timer is enabled and if the WDE is written to logic zero the Watchdog Timer function is disabled WDE can only be cleared if the WDCE bit has logic level one To disable an enabled Watchdog Timer the following procedure must be followed 1 In the same operation write a logic one to WDCE and WDE A logic one must be writ ten to WDE even though it is set to one before the disable operation starts 2 Within the next four clock cycles write a logic O to WDE This disables the Watchdog In safety level 2 it is not possible to disable the Watchdog Timer even with the algorithm described above Timed Sequences for Changing the Configuration of the Watchdog Timer on page 44 In safety level 1 WDE is overridden by WDRF in MCUSR See MCU Status Register MCUSR on page 39 for description of WDRF This means that WDE is always set when WDRF is set To clear WDE WDRF must b
40. SCL i 1 7 8 N 9 N 1 8 9 1 8 9 i J ADDRESS DATA ACK DATA ACK E j Is j Xu RW ACK Referring to the timing diagram Figure 16 5 a bus transfer involves the following steps 1 The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high A SDA can be forced low either by writing a zero to bit 7 of the Shift Register or by setting the corresponding bit in the PORT Register to zero Note that the Data Direction Register bit must be set to one for the output to be enabled The slave device s start detector logic Figure 16 6 detects the start condition and sets the USISIF Flag The flag can generate an interrupt if necessary In addition the start detector will hold the SCL line low after the Master has forced an negative edge on this line B This allows the Slave to wake up from sleep or complete its other tasks before setting up the Shift Register to receive the address This is done by clearing the start condition flag and reset the counter The Master set the first bit to be transferred and releases the SCL line C The Slave samples the data and shift it into the Serial Register at the positive edge of the SCL clock After eight bits are transferred containing slave address and data direction read or write the Slave counter overflows and the SCL line is forced low D If the slave is not the one the Master has addressed it releases the SC
41. TEMP ERATURE BODLEVEL 4 3V Risin Falling Threshold V EN PO 4 __ 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature C Figure 23 32 BOD Thresholds vs Temperature BODLEVEL Is 2 7V BOD THRESHOLDS vs TEMP ERATURE BODLEVEL 2 7V 2 8 4 2 751 2 7 2 65 Threshold V 2 6 4 2 55 2 51 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature C 1 5 ATtiny25 45 05 nue Figure 23 33 BOD Thresholds vs Temperature BODLEVEL Is 1 8V BOD THRESHOLDS vs TEMPERATURE BODLEVEL at 1 8V Threshold V 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature C 23 8 Internal Oscillator Speed Figure 23 34 Watchdog Oscillator Frequency vs Voc WATCHDOC OSCILLATOR FREQUENCY vs Vcc Fao MHz 125 C AMEL 169 7598G AVR 03 08 AMEL Figure 23 35 Watchdog Oscillator Frequency vs Temperature WATCHDOG OSCILLATOR FREQUENCY vs TEMP ERATURE 0 118 L 0 116 0 114 0 112 foot 2 0 108 uw 1 8V 0 106 2 7V 0 104 3 6V 4 0 V 0 102 5 5 V 0 1 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Figure 23 36 Calibrated 8 MHz RC Oscillator Frequency vs Temperature CALIBRATED 8MHz RC OSCILLATOR FR
42. The Watchdog Timer is clocked from an On chip Oscillator which runs at 128 kHz By controlling the Watchdog Timer prescaler the Watchdog Reset interval can be adjusted as shown in Table 8 7 on page 43 The WDR Watchdog Reset instruction resets the Watchdog Timer The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs Ten different clock cycle periods can be selected to determine the reset period If the reset period expires without another Watchdog Reset the ATtiny25 45 85 resets and executes from the Reset Vec tor For timing details on the Watchdog Reset refer to Table 8 7 on page 43 The Wathdog Timer can also be configured to generate an interrupt instead of a reset This can be very helpful when using the Watchdog to wake up from Power down To prevent unintentional disabling of the Watchdog or unintentional change of time out period two different safety levels are selected by the fuse WDTON as shown in Table 8 5 Refer to Timed Sequences for Changing the Configuration of the Watchdog Timer on page 44 for details Table 8 5 WDT Configuration as a Function of the Fuse Settings of WDTON Safety WDT Initial How to Disable the How to Change Time WDTON Level State WDT out Unprogrammed 1 Disabled Timed sequence No limitations Programmed 2 Enabled Always enabled Timed sequence Figure 8 7 Watchdog Timer WATCHDOG 128 kHz p PRESCALER OSCILLATOR OSC 4K OSC 8K O
43. Units lteic Oscillator Frequency ATtiny25 45 85V 0 4 MHz lei cL Oscillator Period ATtiny25 45 85V 250 ns loro a Frequency ATtiny25 45 85L VCC 2 7 0 10 MHz Oscillator Period ATtiny25 45 85L VCC 2 7 teLeL 5 5V 100 ns AMEL 137 7598G AVR 03 08 AMEL Table 21 11 Serial Programming Characteristics T4 40 C to 125 C Voc 2 7 5 5V Unless Otherwise Noted Symbol Parameter Min Typ Max Units iaa E Frequency ATtiny25 45 85 Voc 4 5V 0 20 MHz leic Oscillator Period ATtiny25 45 85 Voc 4 5V 5 5V 50 ns tsus SCK Pulse Width High 2 toc ns tei sH SCK Pulse Width Low 2 terc ns tovsH MOSI Setup to SCK High teLcL ns tsHox MOSI Hold after SCK High 2 tote ns Note 1 2 teicL for fek 12 MHz 3 tote for Tee gt 12 MHz 21 7 High voltage Serial Programming This section describes how to program and verify Flash Program memory EEPROM Data mem ory Lock bits and Fuse bits in the ATtiny25 45 85 Figure 21 4 High voltage Serial Programming SDI PBO SII PB1 SCI PB3 SDO PB2 Table 21 12 Pin Name Mapping Signal Name in High voltage Serial Programming Mode Pin Name lO Function SDI PBO Serial Data Input SII PB1 l Serial Instruction Input SDO PB2 O Serial Data Output SCI PB3 l Serial Clock Input min 220ns period ns ATtinY25 45 85 su Table 21 13 High v
44. W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TPN Pei PINES PINE PINS PNBo Pme Read Write R R R W R W R W R W R W R W Initial Value 0 0 N A N A N A N A N A N A 11 External Interrupts 11 0 1 58 The External Interrupts are triggered by the INTO pin or any of the PCINT5 0 pins Observe that if enabled the interrupts will trigger even if the INTO or PCINTS5 0 pins are configured as out puts This feature provides a way of generating a software interrupt Pin change interrupts PCI will trigger if any enabled PCINT5 0 pin toggles The PCMSK Register control which pins con tribute to the pin change interrupts Pin change interrupts on PCINTS5 0 are detected asynchronously This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode The INTO interrupts can be triggered by a falling or rising edge or a low level This is set up as indicated in the specification for the MCU Control Register MCUCR When the INTO interrupt is enabled and is configured as level triggered the interrupt will trigger as long as the pin is held low Note that recognition of falling or rising edge interrupts on INTO requires the presence of an I O clock described in Clock Systems and their Distribution on page 21 Low level interrupt on INTO is detected asynchronously This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode The I O c
45. W R W R W R W Initial Value 0 0 1 1 1 1 1 1 Bits 7 6 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and will always read as zero Bits 5 0 PCINT5 0 Pin Change Enable Mask 5 0 Each PCINT5 0 bit selects whether pin change interrupt is enabled on the corresponding I O pin If PCINT5 0 is set and the PCIE bit in GIMSK is set pin change interrupt is enabled on the corresponding I O pin If PCINT5 0 is cleared pin change interrupt on the corresponding I O pin is disabled 12 8 bit Timer CounterO with PWM 12 1 60 Overview Timer CounterO is a general purpose 8 bit Timer Counter module with two independent Output Compare Units and with PWM support It allows accurate program execution timing event man agement and wave generation The main features are Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match Auto Reload Glitch Free Phase Correct Pulse Width Modulator PWM Variable PWM Period Frequency Generator Three Independent Interrupt Sources TOVO OCFOA and OCFOB A simplified block diagram of the 8 bit Timer Counter is shown in Figure 12 1 For the actual placement of I O pins refer to Pinout ATtiny25 45 85 on page 2 CPU accessible I O Registers including I O bits and I O pins are shown in bold The device specific I O Register and bit loca tions are listed in the 8 bit Timer Counter Register Description on page 71
46. after Instr 4 until SDO goes Wre Fuse Sil 0_0100_1100_00 0 0010 1100 00 0 0111 0100 00 0_0111_1100_00 high Write F B 0 to program High Bits SD X XXXX XXXX XX X XXXX XXXX XX X XXXX XXXX XX X XXXX XXXX XX the Fuse bit O SD l 0 0010 0000 00 0 0000 0021 00 0 0000 0000 00 0 0000 0000 00 wait after Instr 4 until SDO goes dus Lack SII 0 0100 1100 O0 0 0010 1100 O0 0_0110_0100_00 0_0110_1100_00 high Write 2 1 0 to program SD X XXXX XXXX XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX the Lock Bit O SD l 0_0000_0100_00 0_0000_0000_00 0_0000_0000_00 oe Redd Fuse Sil 0 0100 1100 00 0 0110 1000 O0 0 0110 1100 00 Reading Aes 10 means the Low Bits Fuse bit is programmed SD X_XXXX_XXXX_XX X_XXXX_XXXX_XX A 9876 543x xx O 144 ATtiny25 45 05 memme 7598G AVR 03 08 Table 21 16 High voltage Serial Programming Instruction Set for ATtiny25 45 85 Continued Instruction Format Instruction Instr 1 5 Instr 2 6 Instr 3 Instr 4 Operation Remarks SD l 0_0000_0100_00 0_0000_0000_00 0_0000_0000_00 Pan Mead FUSE SII 0 0100 1100 O0 00111101000 0_0111_1110_00 Reading PB oe adus die High Bits Fuse bit is programmed SD X XXXX XXXX XX X XXXX XXXX XX x xxFE DCBx xx O SD l 0_0000_0100_00 0 0000 0000 00 0 0000 0000 00 M Head Lock SII 0 0100 1100 00 0_0111_1000_00 0 O111 1100 O0 Headings 1 0 means the Bit
47. cleared Timer Counter1 continues counting and is unaffected by a compare match Bit 6 PWM1A Pulse Width Modulator A Enable When set one this bit enables PWM mode based on comparator OCR1A in Timer Counter1 and the counter value is reset to 00 in the CPU clock cycle after a compare match with OCR1C register value Bits 5 4 COM1A1 COM1A0 Comparator A Output Mode Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer Counter1 Output pin actions affect pin PB1 OC1A Since this is an alternative function to an I O port the corresponding direction control bit must be set one in order to control an output pin Note that OC1A is not connected in normal mode Table 14 1 Comparator A Mode Select COM1A1 COM1AO Description 0 0 Timer Counter Comparator A disconnected from output pin OC1A 0 1 Toggle the OC1A output line 1 0 Clear the OC1A output line 1 1 Set the OC1A output line In PWM mode these bits have different functions Refer to Table 14 4 on page 88 for a detailed description Bits 3 0 CS13 CS12 CS11 CS10 Clock Select Bits 3 2 1 and 0 The Clock Select bits 3 2 1 and 0 define the prescaling source of Timer Counter1 Table 14 2 Timer Counter1 Prescale Select Asynchronous Synchronous CS13 CS12 CS11 CS10 Clocking Mode Clocking Mode 0 0 0 0 T C1 stopped T C1 stopped 0 0 0 1 PCK CK 0 0 1 0 PCK 2 CK 2 0 0 1 1 PCK 4 CK 4 0 1 0 0 PCK
48. conditions 8 mA at Voc 5V 5 mA at Vec 3V under steady state conditions non transient the following must be observed 1 The sum of all IOH for all ports should not exceed 60 mA If IOH exceeds the test condition VOH may exceed the related specification Pins are not guaranteed to source current greater than the listed test condition 6 All I O modules are turned off PRR OxFF for all Icc values 7 Brown Out Detection BOD disabled 22 2 External Clock Drive Waveforms Figure 22 1 External Clock Drive Waveforms 148 ATtiny25 45 05 memme 7598G AVR 03 08 22 3 External Clock Drive Figure 22 2 Maximum Frequency vs Vcc Table 22 2 External Clock Drive PRELIMINARY Voc 4 5 Voc 2 7 5 5V 5 5V Symbol Parameter Min Max Min Max Units 1 teLeL Clock Frequency 0 8 0 16 MHz teLcL Clock Period 100 50 ns tcHCX High Time 40 20 ns teLcx Low Time 40 20 ns teLcH Rise Time 1 6 0 5 us tcHCL Fall Time 1 6 0 5 us Change in period from one clock cycle to Aterot the next Notes 1 All DC Characteristics contained in this data sheet result from actual silicon characterization 16 MHz 8 MHz Safe Operating Area 2 7V 4 5V 5 5V 149 7598G AVR 03 08 AMEL AMEL 22 4 ADC Characteristics Preliminary Data Table 22 3 ADC Characteristics Single Ended Channels 40 C 125 C
49. consumed by the input logic when not needed In some cases the input logic is needed for detecting wake up conditions and it will then be enabled Refer to the section Digital Input Enable and Sleep Modes on page 51 for details on which pins are enabled If the input buffer is enabled and the input signal is left floating or has an analog signal level close to V 2 the input buffer will use excessive power For analog input pins the digital input buffer should be disabled at all times An analog signal level close to Voc 2 on an input pin can cause significant current even in active mode Digital input buffers can be disabled by writing to the Digital Input Disable Register DIDRO Refer to Digital Input Disable Register 0 DIDRO on page 107 for details 8 System Control and Reset 8 0 1 Resetting the AVR 8 0 2 Reset Sources 7598G AVR 03 08 During reset all I O Registers are set to their initial values and the program starts execution from the Reset Vector The instruction placed at the Reset Vector must be a RUMP Relative Jump instruction to the reset handling routine If the program never enables an interrupt source the Interrupt Vectors are not used and regular program code can be placed at these locations The circuit diagram in Figure 8 1 shows the reset logic Table 8 1 defines the electrical parameters of the reset circuitry The I O ports of the AVR are immediately reset to their initial state when a res
50. different addressing modes these address registers have functions as fixed displacement automatic increment and automatic decrement see the instruction set reference for details The Stack is mainly used for storing temporary data for storing local variables and for storing return addresses after interrupts and subroutine calls The Stack Pointer Register always points to the top of the Stack Note that the Stack is implemented as growing from higher memory loca tions to lower memory locations This implies that a Stack PUSH command decreases the Stack Pointer The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled The Stack Pointer must be set to point above 0x60 The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI The AVR Stack Pointer is implemented as two 8 bit registers in the I O space The number of bits actually used is implementation dependent Note that the data space in
51. enable 2 SDO pin and the resulting drive contention may increase the power consumption To minimize this drive contention release the Prog enable 2 pin after tyuyast has elapsed 6 Wait at least 50 us before giving any serial instructions on SDI SII Table 21 15 High voltage Reset Characteristics Minimum High voltage Period for Supply Voltage RESET Pin High voltage Threshold Latching Prog enable Voc VuvRsT luvnsT 4 5V 11 5V 100 ns 5 5V 11 5V 100 ns 7598G AVR 03 08 AMEL 139 AMEL 21 8 2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming For efficient programming the following should be considered The command needs only be loaded once when writing or reading multiple memory locations Skip writing the data value OxFF that is the contents of the entire EEPROM unless the EESAVE Fuse is programmed and Flash after a Chip Erase Address High byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM This consideration also applies to Signature bytes reading 21 8 3 Chip Erase The Chip Erase will erase the Flash and EEPROM memories plus Lock bits The Lock bits are not reset until the Program memory has been completely erased The Fuse bits are not changed A Chip Erase must be performed before the Flash and or EEPROM are re programmed Note 1 The EEPROM memory is pres
52. is generated when Timer Counter1 counts from FF to 00 while in the PWM mode the overflow interrupt is generated when Timer Counter1 counts either from FF to 00 or from OCR1C to 00 The inverted PWM outputs OC1A and OC1B are not connected in normal mode In PWM mode OCR1A and OCR1B provide the data values against which the Timer Counter value is compared Upon compare match the PWM outputs OC1A OC1A OC1B OC1B are generated In PWM mode the Timer Counter counts up to the value specified in the output com pare register OCR1C and starts again from 00 This feature allows limiting the counter full value to a specified value lower than FF Together with the many prescaler options flexible PWM frequency selection is provided Table 14 6 lists clock selection and OCR1C values to AMEL a 7598G AVR 03 08 AMEL obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps Higher PWM frequencies can be obtained at the expense of resolution 14 1 1 Timer Counter1 Control Register TCCR1 Bit 7 6 5 4 3 2 1 0 90 50 Tec Read Write R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 Bit 7 CTC1 Clear Timer Counter on Compare Match When the CTC1 control bit is set one Timer Counter1 is reset to 00 in the CPU clock cycle after a compare match with OCRIC register value If the control bit is
53. is set The ADC does not consume power when ADEN is cleared so it is recommended to switch off the ADC before entering power saving sleep modes The ADC generates a 10 bit result which is presented in the ADC Data Registers ADCH and ADCL By default the result is presented right adjusted but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX If the result is left adjusted and no more than 8 bit precision is required it is sufficient to read ADCH Otherwise ADCL must be read first then ADCH to ensure that the content of the data registers belongs to the same conversion Once ADCL is read ADC access to data registers is blocked This means that if ADCL has been read and a conversion completes before ADCH is read neither register is updated and the result from the conversion is lost When ADCH is read ADC access to the ADCH and ADCL Registers is re enabled The ADC has its own interrupt which can be triggered when a conversion completes When ADC access to the data registers is prohibited between reading of ADCH and ADCL the interrupt will trigger even if the result is lost 18 3 Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit ADSC This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed If a different data channel is selected while a conversion is in progress the ADC will finish
54. li Current I O Pin except Ve sent i high 50 nA RESET absolute value Rast Reset Pull up Resistor 30 60 kQ Rou I O Pin Pull up Resistor 20 50 kQ AIMEL a ey AMEL Table 22 1 DC Characteristics T4 40 C to 125 C Vec 2 7V to 5 5V unless otherwise noted Symbol Parameter Condition Min Typ Max Units Active 4MHz Vcc 3V 1 25 3 mA Active 8MHz Voc 5V 5 10 mA Active 16MHz Voc 5V 10 15 mA Power Supply Current Idle 4MHz Voc 3V 0 4 0 5 mA 1 Idle 8MHz Voc 5V 1 2 2 mA i Idle 16MHz Vec 5V 25 5 mA WDT enabled Voc 3V 5 30 uA WDT disabled Voc 3V 2 24 yA Power down mode WDT enabled Voc 5V 9 50 pA WDT disabled Voc 5V 3 36 yA Notes 1 All DC Characteristics contained in this data sheet result from actual silicon characterization 2 Max means the highest value where the pin is guaranteed to be read as low 3 Min means the lowest value where the pin is guaranteed to be read as high 4 Although each I O port can sink more than the test conditions 8 mA at Voc 5V 5 mA at Vec 3V under steady state con ditions non transient the following must be observed 1 The sum of all IOL for all ports should not exceed 60 mA If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test condition 5 Although each I O port can source more than the test
55. methods for Programming the ATtiny25 45 85 memories 21 1 Program And Data Memory Lock Bits The ATtiny25 45 85 provides two Lock bits which can be left unprogrammed 1 or can be pro grammed 0 to obtain the additional security listed in Table 21 2 The Lock bits can only be erased to 1 with the Chip Erase command AMEL 129 7598G AVR 03 08 21 2 Fuse Bytes AMEL Program memory can be read out via the debugWIRE interface when the DWEN fuse is pro grammed even if the Lock Bits are set Thus when Lock Bit security is required should always debugWIRE be disabled by clearing the DWEN fuse Table 21 1 Lock Bit Byte Lock Bit Byte Bit No Description Default Value 1 1 1 1 1 1 LB2 1 Lock bit 1 LB1 0 Lock bit 1 unprogrammed unprogrammed unprogrammed unprogrammed unprogrammed m Co O1 O0O IN unprogrammed unprogrammed unprogrammed Note 1 1 means unprogrammed 0 means programmed Table 21 2 Lock Bit Protection Modes Memory Lock Bits Protection Type LB Mode LB2 LB1 1 1 1 No memory lock features enabled Further programming of the Flash and EEPROM is disabled in High voltage and Serial Programming mode The Fuse bits are 1 P locked in both Serial and High voltage Programming mode debugWire is disabled Further programming and verification of the Flash and 3 0 0 EEPROM is di
56. multiple bytes are to be written to the same page Note that auto erase of EEPROM is not available in High voltage Serial Programming only in SPI Programming 145 AMEL 7598G AVR 03 08 ATMEL 21 9 High voltage Serial Programming Characteristics Figure 21 7 High voltage Serial Programming Timing P I 1 CK Cycle DM trour gt RESET TIME OUT INTERNAL RESET Table 21 17 High voltage Serial Programming Characteristics T 25 C 10 Voc 5 0V 10 Unless otherwise noted Symbol Parameter Min Typ Max Units tsHSL SCI PB3 Pulse Width High 110 ns tei sH SCI PB3 Pulse Width Low 110 ns tive SDI PBO SII PB1 Valid to SCI PB3 High 50 ns taux SDI PBO SII PB1 Hold after SCI PB3 High 50 ns tsuov SCI PB3 High to SDO PB2 Valid 16 ns tWLWH_PFB Wait after Instr 3 for Write Fuse Bits 2 5 ms 146 ATtiny25 45 05 nue 7598G AVR 03 08 22 Electrical Characteristics 22 1 Absolute Maximum Ratings Operating Temperature 40 C to 125 C Storage Temperature sssssss 65 C to 150 C Voltage on any Pin except RESET with respect to Ground sssess 1 0V to Vcc40 5V Voltage on RESET with respect to Ground 1 0V to 13 0V NOTICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam age to
57. software assigned pin value a nop instruction must be inserted as indi cated in Figure 10 4 The out instruction sets the SYNC LATCH signal at the positive edge of the clock In this case the delay tpd through the synchronizer is one system clock period Figure 10 4 Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK Mq pag r16 COE E LLL INSTRUCTIONS CK SYNC LATCH DT PINxn SENE NS uu r17 0x00 OxFF The following code example shows how to set port B pins 0 and 1 high 2 and 3 low and define the port pins from 4 to 5 as input with a pull up assigned to port pin 4 The resulting pin values are read back again but as previously discussed a nop instruction is included to be able to read back the value recently assigned to some of the pins 50 ATtiny25 45 05 memm 10 2 5 7598G AVR 03 08 Assembly Code Example Define pull ups and set outputs high Define directions for port pins ldi r16 1 PB4 1 PB1 1 PBO ldi r17 1 DDB3 1 DDB2 1 DDB1 1 DDBO out PORTB r16 out DDRB r17 Insert nop for synchronization nop Read port pins in r16 PINB C Code Example unsigned char i Define pull ups and set outputs high Define directions for port pins PORTB 1 lt lt PB4 1 lt lt PB1 1 lt lt PBO DDRB 1 lt lt DDB3 1 lt lt DDB2 1 DDB1 1 lt lt DDBO Insert nop for synchronization NOP R
58. stored by loading the Write Program memory Page instruction with the 6 MSB of the address If polling RDY BSY is not used the user must wait at least typ ri Asu before issuing the next page See Table 21 9 Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming A The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction An EEPROM memory location is first automatically erased before new data is written If polling RDY BSY is not used the user must wait at least typ eeprom before issuing the next byte See Table 21 9 In a chip erased device no OxFFs in the data file s need to be programmed B The EEPROM array is programmed one page at a time The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 6 MSB of the address When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered The remaining locations remain unchanged If poll ing RDY BSY is not used the used must wait at least twp eeprom before issuing the next page See Table 21 7 In a chip erased device no OxFF in the data file s need to be programmed Any memory location can be verified by using the Rea
59. the ATtiny25 45 85 data is clocked on the falling edge of SCK See Figure 21 2 and Figure 21 3 for timing details To program and verify the ATtiny25 45 85 in the Serial Programming mode the following sequence is recommended see four byte instruction formats in Table 21 10 1 Power up sequence Apply power between Vcc and GND while RESET and SCK are set to 0 In some sys tems the programmer can not guarantee that SCK is held low during power up In this case RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to 0 Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI The serial programming instructions will not work if the communication is out of syn chronization When in sync the second byte 0x53 will echo back when issuing the third byte of the Programming Enable instruction Whether the echo is correct or not all four bytes of the instruction must be transmitted If the 0x53 did not echo back give RESET a positive pulse and issue a new Programming Enable command The Flash is programmed one page at a time The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction To ensure correct loading of the page the data low byte must be loaded before data high byte is applied for a given address The Program memory Page is
60. the PLL has been enabled earlier Bit 1 PLLE PLL Enable When the PLLE is set the PLL is started and if needed internal RC oscillator is started as a PLL reference clock If PLL is selected as a system clock source the value for this bit is always 1 Bit 0 PLOCK PLL Lock Detector When the PLOCK bit is set the PLL is locked to the reference clock and it is safe to enable PCK for Timer Counter1 After the PLL is enabled it takes about 100 micro seconds for the PLL to lock 14 1 10 Timer Counter1 Initialization for Asynchronous Mode 14 1 11 7598G AVR 03 08 To change Timer Counter1 to the asynchronous mode first enable PLL wait 100 us before poll ing the PLOCK bit until it is set and then set the PCKE bit Timer Counter1 in PWM Mode When the PWM mode is selected Timer Counter1 and the Output Compare Register C OCR10C form a dual 8 bit free running and glitch free PWM generator with outputs on the AMEL sr AMEL PB1 OC1A and PB3 OC1B pins and inverted outputs on pins PBO OC1A and PB2 OC1B As default non overlapping times for complementary output pairs are zero but they can be inserted using a Dead Time Generator see description on page 100 Figure 14 4 The PWM Output Pair thon overlaa 0 tnon overlap 0 x AorB When the counter value match the contents of OCR1A or OCR1B the OC1A and OC1B outputs are set or cleared according to the COM1A1 COM1A0 or COM1B1 COM1B0 bits in the Timer Counter1 Control
61. the device This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 7598G AVR 03 08 Maximum Operating Voltage eeeeeeese 6 0V DC Current per I O Pin sseeeeeeeee 40 0 mA DC Current Veg and GND Pins ss 200 0 mA Table 22 1 DC Characteristics T4 40 C to 125 C Vec 2 7V to 5 5V unless otherwise noted Symbol Parameter Condition Min Typ Max Units Vi Input Low Voltage me PERETANE ATAL 0 5 0 3Voc V Viu 4 Input Low Voltage XTAL pin 0 5 0 1Voc Vio Input Low Voltage RESET pin 0 5 0 1Voc V Mig Input High voltage sina RESET and a gt opi Voc 0 5 V Vig Input High voltage XTAL pin 0 9 Voc Voc 40 5 V Vino Input High voltage RESET pin 0 9 Vc c 9 Voc 0 5 V VoL Output Low Voltage lo 8 mA Voc 5V 0 6 V Port B except PB5 log 5 mA Vec 3V 0 5 V Vou Output High voltage lon 8 MA Vec 5V 4 1 V Port B except PB5 lon 5 mA Vec 3V 2 3 V 4 Vs E Low Voltage lo 1 mA 0 6 V Output High voltage Vp PEE g lop 200pA Voc 5V 3 2 V Input Leakage B lu Current I O Pin except lins B e MW 50 nA RESET absolute value Input Leakage B TR
62. time between the write and the latch operation a read from OCR1A or OCR1B will read the contents of the temporary location This means that the most recently written value always will read out of OCR1A or OCR1B When OCR14A or OCR1B contain 00 or the top value as specified in OCR1C register the out put PB1 OC1A or PBS OC1B is held low or high according to the settings of COM1A1 COM1A0 This is shown in Table 14 5 Table 14 5 PWM Outputs OCR1x 00 or OCR1C x Aor B COM1x1 COM1x0 OCR1x Output OC1x Output OC1x 0 1 00 L H 0 1 OCR1C H L 1 0 00 L Not connected 1 0 OCR1C H Not connected 1 1 00 H Not connected 1 1 OCR1C L Not connected In PWM mode the Timer Overflow Flag TOV1 is set when the TCNT1 counts to the OCR1C value and the TCNT1 is reset to 00 The Timer Overflow Interrupt1 is executed when TOV1 is set provided that Timer Overflow Interrupt and global interrupts are enabled This also applies to the Timer Output Compare flags and interrupts The frequency of the PWM will be Timer Clock 1 Frequency divided by OCR1C value 1 See the following equation foun freki PWM OCR1C 1 AMEL s AMEL Resolution shows how many bit is required to express the value in the OCR1C register It is cal culated by following equation Resolutiongywy ogo OCR1C 1 Table 14 6 Timer Counter1 Clock Prescale Select in the Asynchronous Mode
63. time for the default clock source 7598G AVR 03 08 See Table 6 7 on page 26 for details AMEL 131 AMEL 4 The default setting of CKSEL1 0 results in internal RC Oscillator 8 0 MHz See Table 6 6 on page 26 for details The status of the Fuse bits is not affected by Chip Erase Note that the Fuse bits are locked if Lock bit1 LB1 is programmed Program the Fuse bits before programming the Lock bits 21 2 1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode This does not apply to the EESAVE Fuse which will take effect once it is programmed The fuses are also latched on Power up in Normal mode 21 3 Signature Bytes All Atmel microcontrollers have a three byte signature code which identifies the device This code can be read in both serial and High voltage Programming mode also when the device is locked The three bytes reside in a separate address space 21 3 1 ATtiny25 Signature Bytes 1 0x000 Ox1E indicates manufactured by Atmel 2 0x001 0x91 indicates 2 KB Flash memory 3 0x002 0x08 indicates ATtiny25 device when 0x001 is 0x91 21 3 2 ATtiny45 Signature Bytes 1 0x000 Ox1E indicates manufactured by Atmel 2 0x001 0x92 indicates 4 KB Flash memory 3 0x002 0x06 indicates ATtiny45 device when 0x001 is 0x92 21 3 3 ATtiny85 Signature Bytes 1 0x000 Ox1E indicates manu
64. to Ox1F only 190 ATtiNY25 45 85 su 7598G AVR 03 08 25 Instruction Set Summary 7598G AVR 03 08 EE Mnemonics Operands Description Operation Flags Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd Rr Add two Registers Rd Rd Rr Z C N V H 1 ADC Rd Rr Add with Carry two Registers Rd Rd Rr C Z C N V H 1 ADIW Rdl K Add Immediate to Word Rdh Rdl Rdh Rdl K Z C N V S 2 SUB Rd Rr Subtract two Registers Rd Rd Rr Z C N V H 1 SUBI Rd K Subtract Constant from Register Rd Rd K Z C N V H 1 SBC Rd Rr Subtract with Carry two Registers Rd Rd Rr C Z C N V H 1 SBCI Rd K Subtract with Carry Constant from Reg Rd Rd K C Z C N V H 1 SBIW Rdl K Subtract Immediate from Word Rdh Rdl Rdh Rdl K Z C N V S 2 AND Rd Rr Logical AND Registers Rd Rde Rr Z N V 1 ANDI Rd K Logical AND Register and Constant Rd Rd eK Z N V 1 OR Rd Rr Logical OR Registers Rd RdvRr Z N V 1 ORI Rd K Logical OR Register and Constant Rd Rdv K ZN V 1 EOR Rd Rr Exclusive OR Registers Rd Rd e Rr ZN V 1 COM Rd One s Complemen Rd OxFF Rd Z C N V 1 NEG Rd Two s Complemen Rd lt 0x00 Rd Z C N V H 1 SBR Rd K Set Bit s in Register Rd RdvK Z N V 1 CBR Rd K Clear Bit s in Register Rd Rd
65. when the pin is configured as an output pin the port pin is driven high one If PORTxn is written logic zero when the pin is configured as an output pin the port pin is driven low zero 10 2 2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn independent on the value of DDRxn Note that the SBI instruction can be used to toggle one single bit in a port 48 ATtiny25 45 05 memm 10 2 3 Switching Between Input and Output When switching between tri state DDxn PORTxn 0b00 and output high DDxn PORTxn 0b11 an intermediate state with either pull up enabled DDxn PORTxn 0b01 or output low DDxn PORTxn 0610 must occur Normally the pull up enabled state is fully accept able as a high impedant environment will not notice the difference between a strong high driver and a pull up If this is not the case the PUD bit in the MCUCR Register can be set to disable all pull ups in all ports Switching between input with pull up and output low generates the same problem The user must use either the tri state DDxn PORTxn 0b00 or the output high state DDxn PORTxn 0b10 as an intermediate step Table 10 1 summarizes the control signals for the pin value Table 10 1 Port Pin Configurations DDxn PORTxn in jeuh yo Pull up Comment 0 0 X Input No Tri state Hi Z 0 1 0 Input Yes Pxn will source current if ext pulled low 0 1 1 Input No Tri state Hi Z 1
66. working registers in the CPU Figure 4 2 AVR CPU General Purpose Working Registers T 0 Addr 0x00 0x01 0x02 0x0D General Ox0E Purpose OxOF Working 0x10 Registers 0x11 Ox1A X register Low Byte 0x1B X register High Byte Ox1C Y register Low Byte Ox1D Y register High Byte Ox1E Z register Low Byte Ox1F Z register High Byte Most of the instructions operating on the Register File have direct access to all registers and most of them are single cycle instructions As shown in Figure 4 2 each register is also assigned a Data memory address mapping them directly into the first 32 locations of the user Data Space Although not being physically imple mented as SRAM locations this memory organization provides great flexibility in access of the registers as the X Y and Z pointer registers can be set to index any register in the file 4 5 1 The X register Y register and Z register The registers R26 R31 have some added functions to their general purpose usage These reg isters are 16 bit address pointers for indirect addressing of the data space The three indirect address registers X Y and Z are defined as described in Figure 4 3 Figure 4 3 The X Y and Z registers 15 XH XL 0 Xeregister R27 0x1B R26 0x1A 15 YH YL 0 7598G AVR 03 08 4 6 4 7 10 Stack Pointer Y register R29 0x1D R28 0x1C 15 ZH ZL 0 Z register 7 0 7 0 R31 0x1F R30 0x1E In the
67. 001 1100 O0 0 0110 0100 O0 0 0110 1100 00 ide ufa aut Page SD X XXXX XXXX XX X XXXX XXXX XX X XXXX XXXX XX Repeat Instr 1 for a new 256 o byte page See Note 1 SD Load Read l 0_0000_0010_00 Flash SII 0_0100_1100_00 Enter Flash Read mode Command SD X_XXXX_XXXX_XX O SD l 0_bbbb_bbbb_00 0 0000 000a 00 0 0000 0000 00 0 0000 0000 00 Repeat Instr 1 3 6 for each SII 0 0000 1100 00 0 0001 1100 00 O0 0110 1000 00 O0 0110 1100 00 new address Repeat Instr 2 for SD X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX qd qqqq qqqx xx new 256 byte page Read Flash Oo Low and High Bytes SD l 0_0000_0000_00 0_0000_0000_00 SII 0_0111_1000_00 0_0111_1100_00 Instr 5 6 SD X_XXXX_XXXX_XX P_Pppp_pppx_xx O SD igne L oss ener EPROM Panno mode Command SD X_XXXX_XXXX_XX O 7598G AVR 03 08 AMEL 143 AMEL Table 21 16 High voltage Serial Programming Instruction Set for ATtiny25 45 85 Continued Instruction Format Instruction Instr 1 5 Instr 2 6 Instr 3 Instr 4 Operation Remarks SD ond 0_00bb_bbbb_00 0 eeee eeee 00 0 0000 0000 00 0_0000_0000_00 Repeat instr 1 4 until the entire page buffer is filled or until all EEPROM SII 0 0000 1100 00 O0 0010 1100 00 O0 0110 1101 00 O 0110 1100 00 Pen Yom data within the page is filled See Page Buffer SD X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX
68. 05 memme 7598G AVR 03 08 ATtiny25 45 85 able and the PWM output and it s complementary output are adjusted separately and independently for both PWM outputs Figure 15 1 Timer Counter1 amp Dead Time Generators PCKE gt TIMER COUNTER1 TIM gt TELE hie aces ee tae ette eee dim ok gt PWM GENERATOR i DT1AH _ gt HK amp DT1BH DEAD TIME GENERATOR DEAD TIME GENERATOR OC1A OC1A OC1B OC1B The dead time generation is based on the 4 bit down counters that count the dead time as shown in Figure 46 There is a dedicated prescaler in front of the Dead Time Generator that can divide the Timer Counter1 clock PCK or CK by 1 2 4 or 8 This provides for large range of dead times that can be generated The prescaler is controlled by two control bits DTPS11 10 from the I O register at address 0x23 The block has also a rising and falling edge detector that is used to start the dead time counting period Depending on the edge one of the transitions on the rising edges OC1x or OC1x is delayed until the counter has counted to zero The compara tor is used to compare the counter with zero and stop the dead time insertion when zero has been reached The counter is loaded with a 4 bit DT1xH or DT1xL value from DT1x I O register depending on the edge of the PWM generator output when the dead time insertion is started Figure 15 2 Dead Time Generator T C1 CLOCK DTPS11 10 OC1x
69. 0x000C rjmp WDT n 0x000D rjmp USI START 0x000E rjmp USI OVF O0x000F RESET ldi r16 low RAMEND Main program start 0x0010 ldi r17 high RAMEND Tiny85 has also SPH 0x0011 out SPL r16 Set Stack Pointer to top of RAM 0x0012 out SPH 17 Tiny85 has also SPH 0x0013 sei Enable interrupts 0x0014 instr xxx 10 I O Ports 10 1 Introduction All AVR ports have true Read Modify Write functionality when used as general digital I O ports This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions The same applies when chang ing drive value if configured as output or enabling disabling of pull up resistors if configured as input Each output buffer has symmetrical drive characteristics with both high sink and source capability The pin driver is strong enough to drive LED displays directly All port pins have indi vidually selectable pull up resistors with a supply voltage invariant resistance All I O pins have protection diodes to both Voc and Ground as indicated in Figure 10 1 Refer to Electrical Char acteristics on page 147 for a complete list of parameters a ATtiny25 45 05 cum Figure 10 1 I O Pin Equivalent Schematic Logic See Figure General Digital I O for Details All registers and bit references in this section are written in general form A lower case x repre sents the numbering letter for
70. 1 3 on page 130 for details ATtiny25 45 05 memme 7598G AVR 03 08 Table 21 10 Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation 0101 0000 XXXX 0000 Read Fuse bits 0 0000 0000 XXXX 0000 programmed 1 Read Fuse bits unprogrammed See Table 21 5 on page 131 for details 0101 0000 XXXX 0000 Read Fuse High bits 0 1000 1000 XXXX oooo pro grammed 1 unprogrammed See Table 21 4 on page 131 for details Read Fuse High bits 0101 0000 XXXX 0000 Read Extended Fuse bits 0 Read Extended Fuse 0000 1000 XXXX 0000 pro grammed 1 Bits unprogrammed See Table 21 3 on page 130 for details 0011 000x 0000 oooo i Read Calibration Byte AG cos DOO oboo Read Calibration Byte 1111 0000 XXXX XXXX If o 1 a programming 0000 0000 XXXX XXXO operation is still busy Wait Poll RDY BSY until this bit returns to 0 before applying another command Note a address high bits b address low bits H 0 Low byte 1 High Byte o data out i data in x don t care 21 6 2 Serial Programming Characteristics Figure 21 3 Serial Programming Timing MOSI K tovsH tsHox IstsH SCK ISHsL MISO suiv Table 21 11 Serial Programming Characteristics T4 40 C to 125 C Vgc 2 7 5 5V Unless Otherwise Noted Symbol Parameter Min Typ Max
71. 11 GPIORO General Purpose l O Register 0 0x10 USIBR USI Buffer Register page 101 OxOF USIDR USI Data Register page 100 Ox0E USISR USICIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNTO page 101 0x0D USICR USISIE USIOIE USIWM1 USIWMO USICS1 USICSO USICLK USITC page 102 0x0C Reserved im 0x0B Reserved Ox0A Reserved 0x09 Reserved 0x08 ACSR ACD ACBG ACO ACI ACIE ACIS1 ACISO page 105 0x07 ADMUX REFS1 REFSO ADLAR REFS2 MUX3 MUX2 MUX1 MUXO page 119 0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPSO page 120 0x05 ADCH ADC Data Register High Byte page 121 0x04 ADCL ADC Data Register Low Byte page 121 0x03 ADCSRB BIN ACME IPR ADTS2 ADTS1 ADTSO page 105 page 122 0x02 Reserved 0x01 Reserved 0x00 Reserved Ex E 7598G AVR 03 08 179 AMEL 0 AMEL Note 1 For compatibility with future devices reserved bits should be written to zero if accessed Reserved I O memory addresses should never be written 2 I O Registers within the address range 0x00 Ox1F are directly bit accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SBIS and SBIC instructions 3 Some of the Status Flags are cleared by writing a logical one to them Note that unlike most other AVRs the CBI and SBI instructions will only operation the specified bit and can therefore be used on registers containing such Status Flags The CBI and SBI instructions work with registers 0x00
72. 2 23 24 25 T N N 3 k Cycle Number ADC Clock ADEN con ee m S b k 8 ARN EE ADSC ADIF ADCH IL TITTI 77 Jg i TUIT TTT IK Sign and MSB of Result ADCL TIILI 7 f AMI 7 P BM P TTX LSB of Result IM MUX and REFS TC Conversion Na Mes MUX and REFS Update Sample amp Hold Update Complete AMEL 111 AMEL Figure 18 5 ADC Timing Diagram Single Conversion One Conversion Next Conversion E gt lt 4 Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 ADC Clock ally LILI LILI L4 L4 xc fff VI ADIF I I 1 J li I 1 AH Z PK Sign and MSB of Result Ac Z7 X TSB of Result T I T TO XS Sample amp Hold Conversion E 3a TS MUX and REFS MUX and REFS Complete Update Update Figure 18 6 ADC Timing Diagram Auto Triggered Conversion P One Conversion Next Conversion ke if I Cycle Number 13 1 2 3 4 5 e 7 8 9 to at 12 13 1311 2 ADC Clock TI t AT Trigger i i Source VID ADATE pog l ADIF l AH Z i PX Sign and MSB of Result l T ADCL ZII 1 X LSB of Result It l I Pag N LINE Sample amp Conversion S So Prescaler Prescaler Hold Complete Reset Reset MUX and REFS Update
73. 2 56V Voltage Reference with external bypass capacitor at PBO AREF pin 1 The device requires a supply voltage of 3V in order to generate 2 56V reference voltage e Bit5 ADLAR ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register Write one to ADLAR to left adjust the result Otherwise the result is right adjusted Changing the ADLAR bit will affect the ADC Data Register immediately regardless of any ongoing conver sions For a comple te description of this bit see The ADC Data Register ADCL and ADCH on page 121 Bits 3 0 MUX3 0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC In case of differential input ADCO ADC1 or ADC2 ADC3 gain selection is also made with these bits Selecting ADC2 or ADCO as both inputs to the differential gain stage enables offset mea AMEL 119 7598G AVR 03 08 AMEL surements Selecting the single ended channel ADC4 enables the temperature sensor Refer to Table 18 4 for details If these bits are changed during a conversion the change will not go into effect until this conversion is complete ADIF in ADCSRA is set Table 18 4 Input Channel Selections Single Ended Positive Negative MUX3 0 Input Differential Input Differential Input Gain 0000 A
74. 6 debugWIRE Related Register in I O Memory The following section describes the registers used with the debugWire 19 6 1 debugWire Data Register DWDR 20 7598G AVR 03 08 Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The DWDR Register provides a communication channel from the running program in the MCU to the debugger This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations Self Programming the Flash The device provides a Self Programming mechanism for downloading and uploading program code by the MCU itself The Self Programming can use any available data interface and associ ated protocol to read code and write program that code into the Program memory The Program memory is updated in a page by page fashion Before programming a page with the data stored in the temporary page buffer the page must be erased The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation Alternative 1 fill the buffer before a Page Erase Fill temporary page buffer Perform a Page Erase Perform a Page Write Alternative 2 fill the buffer after Page Erase Perform a Page Erase Fill temporary page buffer Perform a Page Write If only a part of the page needs to be changed the rest o
75. 8 TT ADCS asc ADCL 7 6 5 4 3 2 1 0 Read Write R R R R R R R R R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADCT ADCH AMEL 121 AMEL mn mN a 7 6 5 4 3 2 1 0 Read Write R R R R R R R R R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When an ADC conversion is complete the result is found in these two registers When ADCL is read the ADC Data Register is not updated until ADCH is read Consequently if the result is left adjusted and no more than 8 bit precision is required it is sufficient to read ADCH Otherwise ADCL must be read first then ADCH The ADLAR bit in ADMUX and the MUXn bits in ADMUX affect the way the result is read from the registers If ADLAR is set the result is left adjusted If ADLAR is cleared default the result is right adjusted ADC9 0 ADC Conversion Result These bits represent the result from the conversion as detailed in ADC Conversion Result on page 117 18 7 8 ADC Control and Status Register B ADCSRB Bit 7 6 5 4 3 2 1 0 BIN ACME IPR ADTS2 ADTS1 ADTSO ADCSRB Read Write R W R W R W R R R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 BIN Bipolar Input Mode The gain stage is working in the unipolar mode as default but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register In the unipolar mode only one sided conversions are supported and the voltage on the positive i
76. A 102 uA PRADC 13uA 84 uA 351 uA Table 23 2 Additional Current Consumption percentage in Active and Idle mode Additional Current consumption compared to Active with external Additional Current consumption clock compared to Idle with external clock PRR bit see Figure 23 1 and Figure 23 2 see Figure 23 6 and Figure 23 7 PRTIM1 17 3 68 4 PRTIMO 1 8 7 3 96 PRUSI 16 6 4 96 PRADC 5 4 96 21 4 96 It is possible to calculate the typical current consumption based on the numbers from Table 2 for other Voc and frequency settings than listed in Table 1 Calculate the expected current consumption in idle mode with USI TIMERO and ADC enabled at Vcc 2 0V and F 1MHz From Table 23 2 third column we see that we need to add 6 4 for the USI 7 396 for the TIMERO module and 21 496 for the ADC module Reading from Figure 23 9 we find that the idle current consumption is 0 25mA at Voc 3 0V and F 1MHz The total current consumption in idle mode with USI TIMERO and ADC enabled gives ICCtotal 0 25 mA 1 0 064 0 073 0 214 0 337 mA AMEL 157 AMEL 23 3 Power Down Supply Current Figure 23 11 Power Down Supply Current vs Vcc Watchdog Timer Disabled POWER DOWN SUPPLY CURRENT vs Voc WATCHDOG TIVER DISABLED 125 C bc UA 85 C 40 C 25 C Figure 23 12 Power Down Supply Current vs Voc Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs Vc
77. A is set this will start a conversion Switching to Free Running mode ADTS 2 0 0 will not cause a trigger event even if the ADC Interrupt Flag is set Table 18 6 ADC Auto Trigger Source Selections ADTS2 ADTS1 ADTSO Trigger Source 0 0 0 Free Running mode 0 0 1 Analog Comparator 0 1 0 External Interrupt Request 0 0 1 1 Timer Counter Compare Match A 1 0 0 Timer Counter Overflow 1 0 1 Timer Counter Compare Match B 1 1 0 Pin Change Interrupt Request 18 7 9 Digital Input Disable Register 0 DIDRO Bit 7 6 5 4 3 2 1 0 ncaa Aoczo Abc3b GG Read Write R R R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 5 2 ADC3D ADCOD ADC3 0 Digital Input Disable When this bit is written logic one the digital input buffer on the corresponding ADC pin is dis abled The corresponding PIN register bit will always read as zero when this bit is set When an analog signal is applied to the ADC3 0 pin and the digital input from this pin is not needed this bit should be written logic one to reduce power consumption in the digital input buffer 19 debugWIRE On chip Debug System 19 1 Features 19 2 Overview 7598G AVR 03 08 Complete Program Flow Control Emulates All On chip Functions Both Digital and Analog except RESET Pin Real time Operation Symbolic Debugging Support Both at C and Assembler Source Level or for Other HLLs Unlimited Number of Program Break Points Using Sof
78. As for the Normal mode of operation the TOVO Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00 12 6 3 Fast PWM Mode 7598G AVR 03 08 The fast Pulse Width Modulation or fast PWM mode WGM02 0 3 or 7 provides a high fre quency PWM waveform generation option The fast PWM differs from the other PWM option by its single slope operation The counter counts from BOTTOM to TOP then restarts from BOT TOM TOP is defined as OXFF when WGM2 0 3 and OCROA when WGM2 0 7 In non inverting Compare Output mode the Output Compare OCOx is cleared on the Compare Match between TCNTO and OCROx and set at BOTTOM In inverting Compare Output mode the out put is set on Compare Match and cleared at BOTTOM Due to the single slope operation the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual slope operation This high frequency makes the fast PWM mode well suited for power regulation rectification and DAC applications High frequency allows physically small sized external components coils capacitors and therefore reduces total system cost In fast PWM mode the counter is incremented until the counter value matches the TOP value The counter is then cleared at the following timer clock cycle The timing diagram for the fast PWM mode is shown in Figure 12 6 The TONTO value is in the timing diagram shown as a his togram for illustrating the single slope opera
79. BDTIC www bdtic com ATMEL Features High Performance Low Power AVR 8 Bit Microcontroller Advanced RISC Architecture 120 Powerful Instructions Most Single Clock Cycle Execution In E 32 x 8 General Purpose Working Registers Fully Static Operation T O Non volatile Program and Data Memories 2 4 8K Byte of In System Programmable Program Memory Flash ATtiny25 45 85 Endurance 10 000 Write Erase Cycles 128 256 512 Bytes In System Programmable EEPROM ATtiny25 45 85 8 bit AVR e Endurance 100 000 Write Erase Cycles 128 256 512 Bytes Internal SRAM ATtiny25 45 85 M ICr OCO nitro l le r Programming Lock for Self Programming Flash Program and EEPROM Data 1 E with 2 4 8K Peripheral Features l Bytes In System 8 bit Timer Counter with Prescaler and Two PWM Channels 8 bit High Speed Timer Counter with Separate Prescaler Prog ram mable 2 High Frequency PWM Outputs with Separate Output Compare Registers Programmable Dead Time Generator Flash Universal Serial Interface with Start Condition Detector 10 bit ADC 4 Single Ended Channels ATtiny25 2 Differential ADC Channel Pairs with Programmable Gain 1x 20x Programmable Watchdog Timer with Separate On chip Oscillator ATti ny4 5 On chip Analog Comparator Special Microcontroller Features ATtiny85 debugWIRE On chip Debug System In System Programmable via SPI Port External and Internal Interrupt Sources 2
80. C Code Example SEI set Global Interrupt Enable _SLEEP enter sleep waiting for interrupt note will enter sleep before any pending interrupt s 12 ATtiny25 45 05 memme 4 8 1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini mum After four clock cycles the Program Vector address for the actual interrupt handling routine is executed During this four clock cycle period the Program Counter is pushed onto the Stack The vector is normally a jump to the interrupt routine and this jump takes three clock cycles If an interrupt occurs during execution of a multi cycle instruction this instruction is completed before the interrupt is served If an interrupt occurs when the MCU is in sleep mode the interrupt execution response time is increased by four clock cycles This increase comes in addition to the start up time from the selected sleep mode A return from an interrupt handling routine takes four clock cycles During these four clock cycles the Program Counter two bytes is popped back from the Stack the Stack Pointer is incremented by two and the I bit in SREG is set 5 AVR ATtiny25 45 85 Memories 5 1 7598G AVR 03 08 This section describes the different memories in the ATtiny25 45 85 The AVR architecture has two main memory spaces the Data memory and the Program memory space In addition the ATti
81. C Timer Counter1 Output Compare Register C page 85 page 96 0x2C GTCCR TSM PWM1B COM1B1 COM1BO FOC1B FOC1A PSR1 PSRO page 78 page 83 page 95 Ox2B OCR1B Timer Counter1 Output Compare Register B page 85 Ox2A TCCROA COMO0A1 COMOAO COMOB1 COMOBO WGM01 WGM00 page 71 0x29 OCROA Timer CounterO Output Compare Register A page 75 0x28 OCROB Timer Counter0 Output Compare Register B page 76 0x27 PLLCSR SM PCKE PLLE PLOCK page 87 page 97 0x26 CLKPR CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPSO page 29 0x25 DT1A DT1AH3 DT1AH2 DT1AH1 DT1AHO DT1AL3 DT1AL2 DT1AL1 DT1ALO page 92 0x24 DT1B DT1BH3 DT1BH2 DT1BH1 DT1BHO DT1BL3 DT1BL2 DT1BL1 DT1BLO page 93 0x23 DTPS1 DTPS11 DTPS10 page 92 0x22 DWDR DWDR 7 0 page 125 0x21 WDTCR WDTIF WDTIE WDP3 WDCE WDE WDP2 WDP1 WDPO page 41 0x20 PRR PRTIM1 PRTIMO PRUSI PRADC page 33 Ox1F EEARH EEAR8 page 15 Ox1E EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEARO page 16 Ox1D EEDR EEPROM Data Register page 16 0x1C EECR EEPM1 EEPMO EERIE EEMWE EEWE EERE page 16 Ox1B Reserved Ez Ox1A Reserved 0x19 Reserved d 0x18 PORTB PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTBO page 58 0x17 DDRB DDB5 DDB4 DDB3 DDB2 DDB1 DDBO page 58 0x16 PINB PINB5 PINB4 PINB3 PINB2 PINB1 PINBO page 58 0x15 PCMSK PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINTO page 60 0x14 DIDRO ADCOD ADC2D ADC3D ADC1D EIN1D AINOD page 107 page 123 0x13 GPIOR2 General Purpose I O Register 2 0x12 GPIOR1 General Purpose I O Register 1 0x
82. C mode using OCROA as TOP The FOCOA bit is always read as zero Bit 6 FOCOB Force Output Compare B The FOCOB bit is only active when the WGM bits specify a non PWM mode However for ensuring compatibility with future devices this bit must be set to zero when TCCROB is written when operating in PWM mode When writing a logical one to the FOCOB bit an immediate Compare Match is forced on the Waveform Generation unit The OCOB output is changed according to its COMOB1 0 bits setting Note that the FOCOB bit is implemented as a ATtiny25 45 05 memme 7598G AVR 03 08 strobe Therefore it is the value present in the COMOB1 0 bits that determines the effect of the forced compare A FOCOB strobe will not generate any interrupt nor will it clear the timer in CTC mode using OCROB as TOP The FOCOB bit is always read as zero Bits 5 4 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and will always read as zero Bit 3 WGM02 Waveform Generation Mode See the description in the Timer Counter Control Register A TCCROA on page 71 Bits 2 0 CS02 0 Clock Select The three Clock Select bits select the clock source to be used by the Timer Counter Table 12 8 Clock Select Bit Description CSs02 CS01 CSO0O0 Description 0 0 0 No clock source Timer Counter stopped 0 0 1 clkyo No prescaling 0 1 0 Clkyo 8 From prescaler 0 1 1 Clkyo 64 From prescaler 1 0 0 clkyo
83. COMnX1 0 The OCROx Registers are double buffered when using any of the Pulse Width Modulation PWM modes For the normal and Clear Timer on Compare CTC modes of operation the dou ble buffering is disabled The double buffering synchronizes the update of the OCROx Compare Registers to either top or bottom of the counting sequence The synchronization prevents the occurrence of odd length non symmetrical PWM pulses thereby making the output glitch free AMEL s 7598G AVR 03 08 12 4 1 12 4 2 12 4 3 AMEL The OCROx Register access may seem complex but this is not case When the double buffering is enabled the CPU has access to the OCROx Buffer Register and if double buffering is dis abled the CPU will access the OCROx directly Force Output Compare In non PWM waveform generation modes the match output of the comparator can be forced by writing a one to the Force Output Compare FOCOx bit Forcing Compare Match will not set the OCFOx Flag or reload clear the timer but the OCOx pin will be updated as if a real Compare Match had occurred the COMOx1 0 bits settings define whether the OCOx pin is set cleared or toggled Compare Match Blocking by TCNTO Write All CPU write operations to the TCNTO Register will block any Compare Match that occur in the next timer clock cycle even when the timer is stopped This feature allows OCROx to be initial ized to the same value as TCNTO without triggering an interrupt when the
84. Compare Match B when configured as an output DDB3 set The OC1B pin is also the inverted output pin for the PWM mode timer function PCINT3 Pin Change Interrupt source 3 Port B Bit 2 SCK ADC1 TO USCK SCL INTO PCINT2 SCK Master Clock output Slave Clock input pin for SPI channel When the SPI is enabled as a Slave this pin is configured as an input regardless of the setting of DDB2 When the SPI is enabled as a Master the data direction of this pin is controlled by DDPB2 When the pin is forced by the SPI to be an input the pull up can still be controlled by the PORTB2 bit ADC1 Analog to Digital Converter Channel 1 T0 Timer CounterO counter source USCK Three wire mode Universal Serial Interface Clock SCL Two wire mode Serial Clock for USI Two wire mode INTO External Interrupt source O PCINT2 Pin Change Interrupt source 2 Port B Bit 1 MISO AIN1 OCOB OC1A DO PCINT1 MISO Master Data input Slave Data output pin for SPI channel When the SPI is enabled as a Master this pin is configured as an input regardless of the setting of DDB1 When the SPI is enabled as a Slave the data direction of this pin is controlled by DDB1 When the pin is forced by the SPI to be an input the pull up can still be controlled by the PORTB1 bit AIN1 Analog Comparator Negative Input Configure the port pin as input with the internal pull up switched off to avoid the digital port function from interfering with the function of th
85. Counter clock pulse is generated Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling The external clock must be guaranteed to have less than half the sys tem clock frequency feci lt fok 0 2 given a 50 50 duty cycle Since the edge detector uses sampling the maximum frequency of an external clock it can detect is half the sampling fre quency Nyquist sampling theorem However due to variation of the system clock frequency and duty cycle caused by Oscillator source crystal resonator and capacitors tolerances it is recommended that maximum frequency of an external clock source is less than f jo 2 5 An external clock source can not be prescaled Figure 13 2 Prescaler for Timer CounterO Clkyo 10 BIT T C PRESCALER PSR10 TO TIMER COUNTERO CLOCK SOURCE Clkr Note 1 The synchronization logic on the input pins TO is shown in Figure 13 1 13 0 3 General Timer Counter Control Register GTCCR Bi 7 6 5 4 3 2 1 0 a E ercen 78 ATtiny25 45 05 memme 7598G AVR 03 08 Read Write R W R R R R R R R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 TSM Timer Counter Synchronization Mode Writing the TSM bit to one activates the Timer Counter Synchronization mode In this mode the value that is written to the PSRO bit is kept hence keeping the Prescaler Reset signal asserted This ensures that the Timer Counter is halted and can be co
86. DCO PB5 0001 ADC1 PB2 N A 0010 ADC2 PB4 0011 ADC3 PB3 0100 ADC2 PB3 ADC2 PB3 1x 0101 ADC2 PB3 ADC2 PB3 20x 0110 ADC2 PB3 ADC3 PB4 1x 0111 T ADC2 PB3 ADC3 PB4 20x 1000 ADCO PB5 ADCO PB5 1x 1001 ADCO PB5 ADCO PB5 20x 1010 ADCO PB5 ADC1 PB2 1x 1011 ADCO PB5 ADC1 PB2 20x 1100 1 1V 2 56V 1101 OV N A 1110 N A 1111 ADC4 1 For offset calibration only Operation on page 108 2 For Temperature Sensor 18 7 6 ADC Control and Status Register A ADCSRA Bit 7 6 5 4 3 2 1 0 anen anso ADATE ADF Apes ApPST ADPSO ApcsmA Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 ADEN ADC Enable Writing this bit to one enables the ADC By writing it to zero the ADC is turned off Turning the ADC off while a conversion is in progress will terminate this conversion Bit 6 ADSC ADC Start Conversion In Single Conversion mode write this bit to one to start each conversion In Free Running mode write this bit to one to start the first conversion The first conversion after ADSC has been written after the ADC has been enabled or if ADSC is written at the same time as the ADC is enabled will take 25 ADC clock cycles instead of the normal 13 This first conversion performs initializa tion of the ADC ADSC will read as one as long as a conversion is in progress When the conversion is complete it returns to zero Writing zero to this bit has no effect 120
87. Data memory cover Direct Indirect with Displace ment Indirect Indirect with Pre decrement and Indirect with Post increment In the Register File registers R26 to R31 feature the indirect addressing pointer registers The direct addressing reaches the entire data space The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y or Z register When using register indirect addressing modes with automatic pre decrement and post incre ment the address registers X Y and Z are decremented or incremented The 32 general purpose working registers 64 I O Registers and the 128 256 512 bytes of inter nal data SRAM in the ATtiny25 45 85 are all accessible through all these addressing modes The Register File is described in General Purpose Register File on page 9 Figure 5 2 Data Memory Map Data Memory 0x0000 0x001F 64 I O Registers 0x0020 0x005F 0x0060 Internal SRAM 128 256 512 x 8 OxODF 0x015F 0x025F Data Memory Access Times This section describes the general access timing concepts for internal memory access The internal data SRAM access is performed in two clkgpy cycles as described in Figure 5 3 ATtiny25 45 8 5 memme 7598G AVR 03 08 Figure 5 3 On chip Data SRAM Access Cycles Ti T T3 Address i Compute Address X Address valid Dua oS WR i lt lt Data Memory Access Instruction Next Instruction 5 3 EEPROM Data Memory The ATtiny25 45 85 con
88. Diagram 1 i i i i i 4 i t i i i i i i 4 i i i i 1 pu 2 4 oo 7 OCnx Interrupt Flag Set ees ee Mars TCNTn OCn Toggle An interrupt can be generated each time the counter value reaches the TOP value by using the OCFOA Flag If the interrupt is enabled the interrupt handler routine can be used for updating the TOP value However changing TOP to a value close to BOTTOM when the counter is run ning with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature If the new value written to OCROA is lower than the current value of TCNTO the counter will miss the Compare Match The counter will then have to count to its maximum value OxFF and wrap around starting at 0x00 before the Compare Match can occur COMnx1 0 1 For generating a waveform output in CTC mode the OCOA output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode COMOA1 0 1 The OCOA value will not be visible on the port pin unless the data direction for ATtiny25 45 05 memme 7598G AVR 03 08 the pin is set to output The waveform generated will have a maximum frequency of foco fa yo 2 when OCROA is set to zero 0x00 The waveform frequency is defined by the following equation f B fok Vo OCnx 2 N 1 OCRnx The N variable represents the prescale factor 1 8 64 256 or 1024
89. EQUENCY vs TEMP ERATURE Fac MHz 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature vo ATtiny25 45 65 ne 7598G AVR 03 08 ATtiny25 45 85 Figure 23 37 Calibrated 8 MHz RC Oscillator Frequency vs Vec CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs OPERATING VOLTAGE 8 4 r NEU 125 C W E ll el ee ee ee a N NNT Taaa 25 Cc P m A 7 8 40 C s d 7 5 1 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Voc V Figure 23 38 Calibrated 8 MHz RC Oscillator Frequency vs Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE Fac MHz 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL X1 AMEL 171 7598G AVR 03 08 AMEL 23 9 Current Consumption of Peripheral Units Figure 23 39 Brownout Detector Current vs Voc BROWNOUT DETECTOR CURRENT vs d 125 C at 85 C 25 C 25 40 C T 20 3 8 10 5 0 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Figure 23 40 Analog Comparator Current vs Voc ANALOG COMP ARATOR CURRENT vs Vc AREF AVcc lcc uA v2 ATtiny25 45 05 memme 23 10 Current Consumption in Reset and Reset Pulse width Figure 23 41 Reset Supply Current vs Voc 0 1 1 0 MHz Excluding Current through the Reset Pull up RESET SUPPLY CURRENT vs dc 0 1 1 0 MHz EXCLUDNG CURRENT TH
90. External Interrupt Request 0 3 0x0002 PCINTO Pin Change Interrupt Request 0 4 0x0003 TIM1_COMPA Timer Counter1 Compare Match A 5 0x0004 TIM1_OVF Timer Counter1 Overflow 6 0x0005 TIMO_OVF Timer CounterO Overflow 7 0x0006 EE RDY EEPROM Ready 8 0x0007 ANA COMP Analog Comparator 9 0x0008 ADC ADC Conversion Complete 10 0x0009 TIM1 COMPB Timer Counter1 Compare Match B 11 0x000A TIMO COMPA Timer CounterO Compare Match A 12 0x000B TIMO COMPB Timer CounterO Compare Match B 13 0x000C WDT Watchdog Time out 14 0x000D USI START USI START 15 0x000E USI OVF USI Overflow If the program never enables an interrupt source the Interrupt Vectors are not used and regular program code can be placed at these locations The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny25 45 85 is Address Labels Code Comments 0x0000 rjmp RESE Reset Handler 0x0001 rjmp EXT INTO IRQO Handler 0x0002 rjmp PCINTO PCINTO Handler AMEL a 7598G AVR 03 08 0x0003 rjmp TIM1_COMPA Timerl CompareA Handler 0x0004 rjmp TIM1_OVF Timerl Overflow Handler 0x0005 rjmp TIMO OVF Timer0 Overflow Handler 0x0006 rjmp EE RDY EEPROM Ready Handler 0x0007 rjmp ANA COMP Analog Comparator Handler 0x0008 rjmp ADC ADC Conversion Handler 0x0009 rjmp TIM1_COMPB Timerl CompareB Handler 0x000A rjmp TIMO COMPA 0x000B rjmp TIMO_COMPB H
91. IRER MASH M NES 179 25 Instruction Set Summary 12 ies ese ses Lene sane ao Sea RSa MIB BR EMRRRR rS ERE RR RARE Rus 181 2b Ordering Information 2 aa enini enin rRk EFE na rax Fs E2ad iaiaeiaeiaa 183 27 Packaging Information 42e eo nain enano eai eee aa nano oo eee Ug ER rae Rasa se HAE R eap us 184 ZMNLIM E E AS 184 AA PG E E E E E E A E A E T 185 28 Document Revision History ssssssssssssnnnsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 186 28 1 Rev 7598G 09 08 1 Leder E E EUER Fo GRE FRE AN aou E 186 28 2 REV 7598F 14 07 iecore rea eec nete ten Res reed tn Les denis ke Re Rd cu Ru eR 186 28 3 REV 7598E 03 07 eenoog arinaa anea aa RR CRM E DUERUE RE dd ev aaeei 186 28 4 Rev 7598D 02 07 iioii aaa a ERE BRRR RR EXE ERIR EUER ERR ERRRE FURENT aaa 186 28 5 REV 75986 09 06 ic iiteas tineis tic cecidi ETE EAEE Dev s REPE TRR A CN aeuo R e NR ER ERA 186 28 6 REV 598B 08 00 4 tdt pie aaae kxe edo OR ERR DR e PERF aea Rau eM 186 28 7 Changes from Rev 2535A 09 01 to Rev 7598A 04 06 sesser 186 29 Errata oiec iien eanna deaan aa a aranana DOG GRE FR EDU RN EDO DR MEE 188 29 1 AT ny25 ROV E e xr ieri uS LE EFE REPE IEEE 188 29 2 ATtiny4b Revi Gi ii b m dedu ofa A ee TOC olde Bere d etd cuni doeet 188 29 8 ATtiny85 Rev Qiii e edet teer apes ee cto leen dereud 188 iv ATtiny25 45 05 memm 7598F AVR 08 07 AIMEL T O Headquarters Atmel Corporation 2325 Orchard Parkway San Jose
92. L line and waits for a new start condition If the Slave is addressed it holds the SDA line low during the acknowledgment cycle before holding the SCL line low again i e the Counter Register must be set to 14 before releasing SCL at D Depending of the R W bit the Master or Slave enables its output If the bit is set a master read operation is in progress i e the slave drives the SDA line The slave can hold the SCL line low after the acknowledge E Multiple bytes can now be transmitted all in same direction until a stop condition is given by the Master F Or a new start condition is given If the Slave is not able to receive more data it does not acknowledge the data byte it has last received When the Master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted Figure 16 6 Start Condition Detector Logic Diagram 1 gt USISIF CLOCK P Q HOLD SCL Write USISIF 16 2 5 Start Condition Detector The start condition detector is shown in Figure 16 6 The SDA line is delayed in the range of 50 to 300 ns to ensure valid sampling of the SCL line The start condition detector is only enabled in Two wire mode 7598G AVR 03 08 AMEL 99 AMEL The start condition detector is working asynchronously and can therefore wake up the processor from the Power down sleep mode However the protocol used might have restrictions on
93. LELUTEUPTU UUUUUUULUUUUUUUUUUUUUU i EE clk clk 8 TCNTn OCRnx 1 OCRnx 1 OCRnx 2 OCRnx OCRnx Value i OCFnx i H Figure 12 11 shows the setting of OCFOA and the clearing of TCNTO in CTC mode and fast PWM mode where OCROA is TOP Figure 12 11 Timer Counter Timing Diagram Clear Timer on Compare Match mode with Pres caler fy 0 8 so MINIM clk clk 8 TCNTn CTC OCRnx i TOP S o o o OCFnx i H H T T 1 12 8 8 bit Timer Counter Register Description 12 8 1 Timer Counter Control Register A TCCROA Bit 7 6 5 4 3 2 1 0 COMOA1 COMOAO COMOBO wamo waGMoo TCCROA Read Write R W R W R W R W R R R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 7 6 COM01A 0 Compare Match Output A Mode These bits control the Output Compare pin OCOA behavior If one or both of the COMOA1 0 bits are set the OCOA output overrides the normal port functionality of the I O pin it is connected to However note that the Data Direction Register DDR bit corresponding to the OCOA pin must be set in order to enable the output driver AMEL n 7598G AVR 03 08 ATMEL When OCOA is connected to the pin the function of the COMOA1 0 bits depends on the WGM02 0 bit setting Table 12 1 shows the COMOAt1 0 bit functionality when the WGM02 0 bits are s
94. Lee unida ces 41 8 3 Timed Sequences for Changing the Configuration of the Watchdog Timer 44 9 8 45 9 1 Interrupt Vectors in ATtiny25 45 85 sesssssssseeenenmeenn 45 gt PIS ENIRO HERODIS TRIN SO REC 46 SEES evirero Senior T 46 10 2 Ports as General Digital l O ssssssssseseseseeeeneneneene nnne 47 10 3 Alterate Port FUNCIONS sie 5 5 fiie iret oen e e c ERR ee DO E teu 52 10 4 Register Description for l O Ports ssesssssssseseeeeeeeneenne enne 57 11 External Interrupts eer 58 12 8 bit Timer Counter0 with PWM ssessssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 60 121 QVORMIOW aieiai ian EAER ARRES AAAA TRARRE 60 12 2 Timer Counter Clock Sources ecccceeeeeeneeeeeneeeeeneeeeeeeeeseaeeeeseaeeeseaeeeseaeeeseneeeeas 62 12 9 Counter Unii 2 eiie dere he A Fue Rx vete pe Y xeu ea ka xe eee ee RR Meere Eee 62 12 4 Output Compare Unit nnne enne nnne nnne 63 12 5 Compare Match Output Unit essssssssssseseeeee eene 64 12 6 Modes of Operation 1 irridet tree tede a aaen aa a eun de veined 65 12 7 Timer Counter Timing Diagrams sss 70 12 8 8 bit Timer Counter Register Description ssseeeeeee 71 13 Timer Counter Prescaler eee eeee esee esses eese n enn a annia ttn n nan nnnnn 77 14 Counter and Compare Uni
95. Low Power Idle ADC Noise Reduction and Power down Modes Automotive Enhanced Power on Reset Circuit Programmable Brown out Detection Circuit Internal Calibrated Oscillator I O and Packages Six Programmable I O Lines 8 pin SOIC 20 pin QFN Operating Voltage 2 7 5 5V for ATtiny25 45 85 Speed Grade ATtiny25 45 85 0 8 MHz 2 7 5 5V 0 16 MHz 4 5 5 5V Automotive Temperature Range 40 C to 125 C Low Power Consumption Active Mode 1 MHz 2 7V 3004A Power down Mode 0 2uA at 2 7V 7598G AVR 03 08 AIMEL AIMEL e O 1 Pin Configurations Figure 1 1 Pinout ATtiny25 45 85 SOIC oy PCINT5 RESET ADCO dW PB5 C 1 8 VCC PCINTS XTAL1 OC1B ADC3 PB3 2 7 L1 PB2 SCK USCK SCL ADC1 TO INTO PCINT2 PCINT4 XTAL2 CLKO OC1B ADC2 PB4 3 6 1 PB1 MISO DO AIN1 OCOB OC1A PCINT1 GND 4 5 0 PBO MOSI DI SDA AINO OCOA OC1 A AREF PCINTO QFN MLF oovo000 2l z zlzc oaaaa PCINTS RESET ADCO dW PBS P PCINTS XTAL1 CLKI OC1B ADC3 PBS DNC DNC voc PB2 SCK USCK SCL ADC1 TO INTO PCINT2 PB1 MISO DO AIN1 OCOB OC 1A PCINT1 Oo 44H 130 DNC 1420 1410 PCINTA XTAL2 CLKO OC1B ADC2 PB4 PBO MOSI DI SDA AINO OCOA OC1 AVAREF PCINTO NOTE Bottom pad should be soldered to ground DNC Do Not Connect 2 Overview 2 The ATtiny25 45 85 is a low power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture By e
96. NESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life 2008 Atmel Corporation All rights reserved Atmel logo and combinations thereof and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of others 7598F AVR 08 07
97. O The ports are bi directional I O ports with optional internal pull ups Figure 10 2 shows a func tional description of one l O port pin here generically called Pxn AMEL ar 7598G AVR 03 08 AMEL Figure 10 2 General Digital 1 0 DATA BUS SYNCHRONIZER clk yo WRITE DDRx PUD PULLUP DISABLE RDx X SLEEP SLEEP CONTROL WRx WRITE PORTx clkyo 1 0 CLOCK RRx READ PORTx REGISTER RPx READ PORTx PIN WPx WRITE PINx REGISTER Note 1 WRx WPx WDx RRx RPx and RDx are common to all pins within the same port clkyo SLEEP and PUD are common to all ports 10 2 1 Configuring the Pin Each port pin consists of three register bits DDxn PORTxn and PINxn As shown in Register Description for l O Ports on page 57 the DDxn bits are accessed at the DDRx I O address the PORTxn bits at the PORTx I O address and the PINxn bits at the PINx I O address The DDxn bit in the DDRx Register selects the direction of this pin If DDxn is written logic one Pxn is configured as an output pin If DDxn is written logic zero Pxn is configured as an input pin If PORTxn is written logic one when the pin is configured as an input pin the pull up resistor is activated To switch the pull up resistor off PORTxn has to be written logic zero or the pin has to be configured as an output pin The port pins are tri stated when reset condition becomes active even if no clocks are running If PORTxn is written logic one
98. OB at TOP Note 1 A special case occurs when OCROB equals TOP and COMOBI is set In this case the Com pare Match is ignored but the set or clear is done at TOP See Fast PWM Mode on page 67 for more details Table 12 3 shows the COMOB 1 0 bit functionality when the WGM02 0 bits are set to phase cor rect PWM mode Table 12 6 Compare Output Mode Phase Correct PWM Mode COMOA1 COMO0AO0 Description 0 0 Normal port operation OCOB disconnected 0 1 Reserved Clear OCOB on Compare Match when up counting Set OCOB on 1 0 Compare Match when down counting 1 1 Set OCOB on Compare Match when up counting Clear OCOB on Compare Match when down counting Note 1 A special case occurs when OCROB equals TOP and COMOBI is set In this case the Com Bits 3 2 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and will always read as zero Bits 1 0 WGMO01 0 Waveform Generation Mode pare Match is ignored but the set or clear is done at TOP See Phase Correct PWM Mode on page 68 for more details Combined with the WGMO bit found in the TCCROB Register these bits control the counting sequence of the counter the source for maximum TOP counter value and what type of wave form generation to be used see Table 12 7 Modes of operation supported by the Timer Counter AMEL 7 7598G AVR 03 08 12 8 2 74 AMEL unit are Normal mode counter Clear Timer on Compare Matc
99. OCOA and OCOB Output Compare Unit on page 63 for details The Compare Match event will also set the Compare Flag OCFOA or OCFOB which can be used to generate an Output Compare inter rupt request Many register and bit references in this section are written in general form A lower case n replaces the Timer Counter number in this case 0 A lower case x replaces the Output Com pare Unit in this case Compare Unit A or Compare Unit B However when using the register or bit defines in a program the precise form must be used i e TCNTO for accessing Timer CounterO counter value and so on AMEL s AMEL The definitions in Table 34 are also used extensively throughout the document BOTTOM The counter reaches the BOTTOM when it becomes 0x00 MAX The counter reaches its MAXimum when it becomes 0xFF decimal 255 TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence The TOP value can be assigned to be the fixed value OxFF MAX or the value stored in the OCROA Register The assignment is dependent on the mode of operation 12 2 Timer Counter Clock Sources The Timer Counter can be clocked by an internal or an external clock source The clock source is selected by the Clock Select logic which is controlled by the Clock Select CS02 0 bits located in the Timer Counter Control Register TCCROB For details on clock sources and pres caler see Timer Counter Prescal
100. ON OVERRIDE VALUE RRx READ PORTx REGISTER PVOExn Pxn PORT VALUE OVERRIDE ENABLE WRx WRITE PORTx PVOVxn Pxn PORT VALUE OVERRIDE VALUE RPx READ PORTx PIN DIEOExn Pxn DIGITAL INPUT ENABLE OVERRIDE ENABLE WPx WRITE PINx DIEOVxn Pxn DIGITAL INPUT ENABLE OVERRIDE VALUE ciko VO CLOCK SLEEP SLEEP CONTROL DIxn DIGITAL INPUT PIN n ON PORTx PTOExn Pxn PORT TOGGLE OVERRIDE ENABLE AlOxn ANALOG INPUT OUTPUT PIN n ON PORTx ATtiny25 45 05 memme 7598G AVR 03 08 Note 1 WRx WPx WDx RRx RPx and RDx are common to all pins within the same port clkyo SLEEP and PUD are common to all ports All other signals are unique for each pin Table 10 2 summarizes the function of the overriding signals The pin and port indexes from Fig ure 10 5 are not shown in the succeeding tables The overriding signals are generated internally in the modules having the alternate function Table 10 2 Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description If this signal is set the pull up enable is controlled by the PUOV ENIEUB Override signal If this signal is cleared the pull up is enabled when PUOE Ld DDxn PORTxn PUD 0b010 Pull up Override If PUOE is set the pull up is enabled disabled when PUOV is PUOV eed set cleared regardless of the setting of the DDxn PORTxn and PUD Register bits Data Direction If this signal is set the Output Driver Enable is controlled by the DDOE DDOV sign
101. Physical Interface cenaren an ceci Aa ttes eese dent e ER a et 124 19 4 Software Break Points ssrin aeinn aaa aa seen nennen nnne 124 19 5 Limitations of debugWIRE seeeeeeen nennen enne 125 19 6 debugWIRE Related Register in I O Memory sssssem 125 20 Self Programming the Flash 2 c cc ceeeeee eene eene nnn nnn 125 20 1 Addressing the Flash During Self Programming esssesesss 126 21 Memory Programming urere rarae rep nan anni nn innu nnm aan nuu EREREFEH RE Ka Raus 129 21 1 Program And Data Memory Lock Bits seeeeeen 129 21 2 Fuse Bytes pere recited REEE EE ER power rua ue 130 21 3 Signature Bytes uiro epa oh aia d Eee in epit 132 21 4 Calibration Byte 2 2 ded eie beh ene dade Ela beet Gala 132 21 5 Page SIZE i oe ex e acte I Rande Eb erdt eder ta bad d nad 132 21 6 Serial Downloading sessssssssssessseseeeeeeeeenene nennen nnne nnne nennt 133 21 7 High voltage Serial Programming sssseeeeeeenneeneene 138 21 8 High voltage Serial Programming Algorithm Sequence sss 139 21 9 High voltage Serial Programming Characteristics eesssesssssss 146 22 Electrical Characteristics 42i inii iiia RM E ERE EARENRR ARE LeKFRa dd dna P ko K kal reEo 147 22 1 Absolute Maximum Ratings sssssssssssseeeeeeneeenee nennen 147 22 2 Ex
102. R core Examples of such modules are the General Purpose Register File the Status Register and the Data memory holding the Stack Pointer Halting the CPU clock inhibits the core from performing general operations and calculations 1 0 Clock clkyo The I O clock is used by the majority of the I O modules like Timer Counter The I O clock is also used by the External Interrupt module but note that some external interrupts are detected by asynchronous logic allowing such interrupts to be detected even if the I O clock is halted The Flash clock controls operation of the Flash interface The Flash clock is usually active simul taneously with the CPU clock ADC Clock clkApc The ADC is provided with a dedicated clock domain This allows halting the CPU and I O clocks in order to reduce noise generated by digital circuitry This gives more accurate ADC conversion results Internal PLL for Fast Peripheral Clock Generation clkpcy The internal PLL in ATtiny25 45 85 generates a clock frequency that is 8x multiplied from a source input The source of the PLL input clock is the output of the internal RC oscillator having a frequency of 8 0 MHz Thus the output of the PLL the fast peripheral clock is 64 MHz The fast peripheral clock or a clock prescaled from that can be selected as the clock source for Timer Counter1 See the Figure 6 2 on page 23 The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will
103. ROUGH THE RES ET PULLUP 0 144 5 5 V 0 12 5 0 V 0 1 4 5 V z 0 08 4 0 V E 0 06 3 3 V 2 7V 0 04 1 8 V 0 02 0 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz Figure 23 42 Reset Supply Current vs Voc 1 24 MHz Excluding Current through the Reset Pull up RESET SUPPLY CURRENT ws Vcc 1 20 Mz EXCLUDING CURRENT THROUGH THE RESET PULLUP 5 5V 5 0 V 4 5 V kc mA Frequency MHz AMEL 173 7598G AVR 03 08 AMEL Figure 23 43 Reset Pulse Width vs Voc MINIMUM RESET PULSE WIDTH vs Voc 2500 2000 1500 1000 Pub ewidth ns 500 23 11 Analog to Digital Converter Figure 23 44 Analog to Digital Converter Differential mode OFFSET vs Vec Analog to Digital Converter OFFSET Differential nputs Vcc 4V Vref 4V 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Diff x20 174 ATtiny25 45 85 memm 7598G AVR 03 08 Figure 23 45 Analog to Digital Converter Single Endded mode OFFSET vs Vec Analog to Digital Converter OFFSET Single Ended Vcc 4V Vref 4V 2 5 LSB 0 5 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Figure 23 46 Analog to Digital Converter Differential mode GAIN vs Voc Analog to Digital Converter GAIN Differential hputs Vcc 5V Vref 4V L
104. Reserved I O memory addresses should never be written Some of the Status Flags are cleared by writing a logical one to them Note that the CBI and SBI instructions will only operate on the specified bit and can therefore be used on registers contain ing such Status Flags The CBI and SBI instructions work with registers 0x00 to Ox1F only The I O and Peripherals Control Registers are explained in later sections 6 System Clock and Clock Options 6 1 Clock Systems and their Distribution 7598G AVR 03 08 Figure 6 1 presents the principal clock systems in the AVR and their distribution All of the clocks need not be active at a given time In order to reduce power consumption the clocks to modules not being used can be halted by using different sleep modes as described in Power Manage ment and Sleep Modes on page 30 The clock systems are detailed below Figure 6 1 Clock Distribution clkpck clkopu ciko AVR Clock Control Unit clk Clkriasn Reset Logic Watchdog Timer Source clock Watchdog clock System Clock Prescaler Clock Watchdog PEL Multiplexer Oscillator Oscillator x 5 me o Crystal Low Frequency Oscillator External Clock Crystal Oscillator Calibrated RC Oscillator AIMEL ey 6 1 1 6 1 5 22 ATMEL CPU Clock clkcpy The CPU clock is routed to parts of the system concerned with operation of the AV
105. SB 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature AMEL 7598G AVR 03 08 Diff x20 Diff x1 175 AMEL Figure 23 47 Analog to Digital Converter Single Endded mode GAIN vs Voc Analog to Digital Converter GAIN Single Ended Vcc 4V Vref 4V LSB 2 5 Temperature Figure 23 48 Analog to Digital Converter Differential mode DNL vs Voc Analog to Digital Converter Differential Non Linearity DNL Differential hputs Vcc 4V Vref 4V Diff x20 Diff x1 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature vc ATtiNY25 45 85 nu ATtiny25 45 85 Figure 23 49 Analog to Digital Converter Single Endded mode DNL vs Vec Analog to Digital Converter Differential Non Linearity DNL Single Ended Vcc 4V Vref 4V 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Figure 23 50 Analog to Digital Converter differential mode INL vs Voc Analog to Digital Converter Integral Non Linearity INL Differential nputs Vcc 4V Vref 4V Diff x20 Diff x1 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature AMEL 177 7598G AVR 03 08 AMEL Figure 23 51 Analog to Digital Converter Single Endded mode INL vs Voc Analog
106. SC 16K OSC 32K OSC 64K OSC 128K WATCHDOG RESET OSC 256K OSC 512K OSC 1024K MCU RESET Watchdog Timer Control Register WDTCR Bit 7 6 5 4 3 2 1 0 wor wore woes woce woe wor2 wort woro worcr Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 X 0 0 0 Bit 7 WDIF Watchdog Timeout Interrupt Flag This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is config ured for interrupt WDIF is cleared by hardware when executing the corresponding interrupt handling vector Alternatively WDIF is cleared by writing a logic one to the flag When the I bit in SREG and WDIE are set the Watchdog Time out Interrupt is executed AMEL a AMEL Bit 6 WDIE Watchdog Timeout Interrupt Enable When this bit is written to one WDE is cleared and the I bit in the Status Register is set the Watchdog Time out Interrupt is enabled In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog Timer occurs If WDE is set WDIE is automatically cleared by hardware when a time out occurs This is useful for keeping the Watchdog Reset security while using the interrupt After the WDIE bit is cleared the next time out will generate a reset To avoid the Watchdog Reset WDIE must be set after each interrupt Table 8 6 Watchdog Timer Configuration WDE WDIE Watchdog Timer State Action on Time out 0 0 Stopped None 0 1 Running Interrupt 1 0
107. SEL 1 0 SUT 1 0 8 0 3 Power on Reset A Power on Reset POR pulse is generated by an On chip detection circuit The detection level is defined in Table 8 1 The POR is activated whenever Vcc is below the detection level The POR circuit can be used to trigger the Start up Reset as well as to detect a failure in supply voltage A Power on Reset POR circuit ensures that the device is reset from Power on Reaching the Power on Reset threshold voltage invokes the delay counter which determines how long the device is kept in RESET after Voc rise The RESET signal is activated again without any delay when Vcc decreases below the detection level 36 ATtiny25 45 05 mem Figure 8 2 MCU Start up RESET Tied to Voc Voc VeonMX VPORMIN INTERNAL RESET Figure 8 3 MCU Start up RESET Extended Externally l L Li 1 lt lt t TIMEOUT ToU INTERNAL RESET Table 8 1 Power On Reset Specifications Symbol Parameter Min Typ Max Units Power on Reset Threshold Voltage rising 1 1 1 4 1 7 V V re Power on Reset Threshold Voltage falling 0 8 1 3 1 6 V VCC Max start voltage to ensure internal Power VPORMAX on Reset signal Os M cuu VCC Min start voltage to ensure internal Power 0 1 V on Reset signal Vccnn VCC Rise Rate to ensure Power on Reset 0 01 V ms Vast RESET Pin Threshold Voltage 0 1 Voc 0 9V6o V Note 1 Before rising the supply has to be between Vpormin a
108. T vs FREQUENCY 1 20MHz 3 5 5 5V 3 5 0 V 1225 4 5V z 2 2 2 1 5 0 5 N 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz Figure 23 8 Idle Supply Current vs Voc Internal RC Oscillator 128 kHz IDLE SUPPLY CURRENT vs Voc NTERNAL RC OSCLLATOR 128 KHz AMEL 155 AMEL Figure 23 9 Idle Supply Current vs Voc Internal RC Oscillator 1 MHz IDLE SUPPLY CURRENT vs Vcc NTERNAL RC OSCLLATOR 1 MHz 0 6 4 0 5 C C C 0 4 C T E o 0 3 kej 0 2 0 1 Figure 23 10 Idle Supply Current vs Voc Internal RC Oscillator 8 MHz IDLE SUPPLY CURRENT vs Voc NTERNAL RC OSCLLATOR 8 MHz 23 2 1 Using the Power Reduction Register The tables and formulas below can be used to calculate the additional current consumption for the different I O modules in Active and Idle mode The enabling or disabling of the I O modules se ATtiNY25 45 85 memme 7598G AVR 03 08 23 2 1 1 Example 1 7598G AVR 03 08 are controlled by the Power Reduction Register See Power Reduction Register on page 33 for details Table 23 1 Additional Current Consumption for the different I O modules absolute values PRR bit Typical numbers Voce 2V F 1MHz Voc 3V F 4MHz Voc 5V F 8MHz PRTIM1 43 uA 270 uA 1090 uA PRTIMO 5 0 uA 28 uA 116 uA PRUSI 4 0 uA 25 u
109. TCNT1 and OCR1A to the same value does not generate a compare match A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow ing the compare event 84 ATtiny25 45 05 memme 14 1 5 Timer Counter1 Output Compare RegisterB OCR1B Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 The output compare register B is an 8 bit read write register The Timer Counter Output Compare Register B contains data to be continuously compared with Timer Counter1 Actions on compare matches are specified in TCCR1 A compare match does only occur if Timer Counter1 counts to the OCR1B value A software write that sets TCNT1 and OCR1B to the same value does not generate a compare match A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow ing the compare event 14 1 6 Timer Counter1 Output Compare RegisterC OCR1C Bit 7 6 5 4 3 2 1 0 see mse crc Read Write R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 The output compare register C is an 8 bit read write register The Timer Counter Output Compare Register C contains data to be continuously compared with Timer Counter1 A compare match does only occur if Timer Counter1 counts to the OCR1C value A software write that sets TCNT1 and OCR1C to the same value does not generate a compare match If the CTC1 bit in TCCR1 is set a compare match will clear TCNT1
110. This bit can be set at any time to turn off the Analog Comparator This will reduce power consumption in Active and Idle mode When changing the ACD bit the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR Otherwise an interrupt can occur when the bit is changed Bit 6 ACBG Analog Comparator Bandgap Select When this bit is set an internal 1 1V 2 56V reference voltage replaces the positive input to the Analog Comparator The selection of the internal voltage reference is done by writing the REFS2 0 bits in ADMUX register When this bit is cleared AINO is applied to the positive input of the Analog Comparator AMEL 7598G AVR 03 08 105 17 1 106 AMEL Bit 5 ACO Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO The synchronization introduces a delay of 1 2 clock cycles Bit4 ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACISO The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I bit in SREG is set ACI is cleared by hardware when executing the corresponding inter rupt handling vector Alternatively ACI is cleared by writing a logic one to the flag Bit 3 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I bit in the Status Register is set t
111. This register has the same function in normal mode and PWM mode 14 1 7 Timer Counter Interrupt Mask Register TIMSK Bit 7 6 5 4 3 2 1 0 39 59 OCIE1A OCIE1B OCIEOA OCIEOB TOIE1 TOIEO TIMSK Read Write R R W R W R W R W R W R W R Initial value 0 0 0 0 0 0 0 0 Bit 7 Res Reserved Bit This bit is a reserved bit in the ATtiny25 45 85 and always reads as zero Bit 6 OCIE1A Timer Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set one and the I bit in the Status Register is set one the Timer Counter1 Compare MatchA interrupt is enabled The corresponding interrupt at vector 003 is executed if a compare matchA occurs The Compare Flag in Timer Counter1 is set one in the Timer Counter Interrupt Flag Register Bit 5 OCIE1B Timer Counter1 Output Compare Interrupt Enable When the OCIE1B bit is set one and the I bit in the Status Register is set one the Timer Counter1 Compare MatchB interrupt is enabled The corresponding interrupt at vector 009 is executed if a compare matchB occurs The Compare Flag in Timer Counter1 is set one in the Timer Counter Interrupt Flag Register AMEL s 7598G AVR 03 08 AMEL Bit 4 OCIEOA Timer Counter Output Compare Match A Interrupt Enable When the OCIEOA bit is written to one and the I bit in the Status Register is set the Timer Counter Compare Match A interrupt is enabled The corresponding interrupt is executed if a Compare Match i
112. Timer Counter clock is enabled Using the Output Compare Unit Since writing TCNTO in any mode of operation will block all Compare Matches for one timer clock cycle there are risks involved when changing TCNTO when using the Output Compare Unit independently of whether the Timer Counter is running or not If the value written to TCNTO equals the OCROx value the Compare Match will be missed resulting in incorrect waveform generation Similarly do not write the TCNTO value equal to BOTTOM when the counter is down counting The setup of the OCOx should be performed before setting the Data Direction Register for the port pin to output The easiest way of setting the OCOx value is to use the Force Output Com pare FOCOx strobe bits in Normal mode The OCOx Registers keep their values even when changing between Waveform Generation modes Be aware that the COMOx1 0 bits are not double buffered together with the compare value Changing the COMOx1 0 bits will take effect immediately 12 5 Compare Match Output Unit 64 The Compare Output mode COMOx1 0 bits have two functions The Waveform Generator uses the COMOx1 0 bits for defining the Output Compare OCOx state at the next Compare Match Also the COMOx1 0 bits control the OCOx pin output source Figure 12 4 shows a simplified schematic of the logic affected by the COMOXx1 0 bit setting The I O Registers I O bits and I O pins in the figure are shown in bold Only the parts of the general
113. U is halted for two clock cycles before the next instruction is executed 5 3 2 EEPROM Address Register High EEARH Bit 7 6 5 4 3 2 1 0 Read Write R R R R R R R R W Initial Value X X X X X X X Xx AMEL 7598G AVR 03 08 AMEL Bit 7 1 Res6 0 Reserved Bits These bits are reserved for future use and will always read as 0 in ATtiny25 45 85 Bits 0 EEAR8 EEPROM Address The EEPROM Address Register EEARH specifies the high EEPROM address in the 128 256 512 bytes EEPROM space The EEPROM data bytes are addressed linearly between 0 and 127 255 511 The initial value of EEAR is undefined A proper value must be written before the EEPROM may be accessed 5 3 3 EEPROM Address Register EEARL Bit v 6 5 4 3 2 1 0 FEAR EEARS FEARS EEAR FEAR EARS EEARL Read Write R R R W R W R W R W R W R W Initial Value X X X X X X X X Bits 7 0 EEAR7 0 EEPROM Address The EEPROM Address Register EEARL specifies the low EEPROM address in the 128 256 512 bytes EEPROM space The EEPROM data bytes are addressed linearly between 0 and 127 255 511 The initial value of EEAR is undefined A proper value must be written before the EEPROM may be accessed 5 3 4 EEPROM Data Register EEDR Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value X X X X X X X X Bits 7 0 EEDR7 0 EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the
114. _XXXX_XX Note 2 O SD Wait after Instr 2 until SDO goes Program l 0_0000_0000_00 0_0000_0000_00 high Repeat Instr 1 2 for each EEPROM SII O 0110 0100 00 O 0110 1100 00 loaded EEPROM page until the Page SD X XXXX XXXX XX X XXXX XXXX XX entire EEPROM or all data is Oo a Fe programmed SD 0 00bb bbbb 00 O eeee eeee 00 0 0000 0000 00 O 0000 0000 00 Repeat Instr 1 5 for each new SII 0 0000 1100 00 O0 0010 1100 00 O0 0110 1101 00 O0 0110 0100 00 address Wait after Instr 5 until SD X XXXX XXXX XX X XXXX XXXX XX X XXXX XXXX XX X XXXX XXXX XX SDO goes high See Note 3 Write Oo EEPROM Byte SD l 0_0000_0000_00 SII 0_0110_1100_00 Instr 5 SD X_XXXX_XXXX_XX O SD Load Read l 0_0000_0011_00 EEPROM SII 0_0100_1100_00 Enter EEPROM Read mode Command SD X_XXXX_XXXX_XX O SD Read l 0 bbbb bbbb 00 O aaaa aaaa 00 0 0000 0000 00 O 0000 0000 00 Repeat Instr 1 3 4 for each EEPROM SII 0 0000 1100 00 0 0001 1100 00 0 0110 1000 00 O0 0110 1100 00 new address Repeat Instr 2 for Byte SD X XXXX XXXX XX X XXXX XXXX XX X_XXXX_XXXX_XX q qqqq qqq0 00 anew 256 byte page O SD 0 0100 0100 00 0_A987_6543_00 0_0000_0000_00 0 0000 0000 00 wait after Instr 4 until SDO goes scien SII O0 0100 1100 00 0 0010 1100 00 O0 0110 0100 00 O0 0110 1100 00 high Write A 3 0 to program SD X XXXX XXXX XX X XXXX XXXX XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX the Fuse bit O SD 0 0100 0000 00 0_000F_EDCB_00 0_0000_0000_00 0 0000 0000 00 wait
115. abled for the SDA pin the output driver will force the line SDA low if the output of the Shift Register or the corresponding bit in 1 0 the PORT Register is zero Otherwise the SDA line will not be driven i e it is released When the SCL pin output driver is enabled the SCL line will be forced low if the corresponding bit in the PORT Register is zero or by the start detector Otherwise the SCL line will not be driven The SCL line is held low when a start detector detects a start condition and the output is enabled Clearing the Start Condition Flag USISIF releases the line The SDA and SCL pin inputs is not affected by enabling this mode Pull ups on the SDA and SCL port pin are disabled in Two wire mode 0 0 Two wire mode Uses SDA and SCL pins 1 1 Same operation as for the Two wire mode described above except that the SCL line is also held low when a counter overflow occurs and is held low until the Counter Overflow Flag USIOIF is cleared Note 1 The DI and USCK pins are renamed to Serial Data SDA and Serial Clock SCL respectively to avoid confusion between the modes of operation Bit 3 2 USICS1 0 Clock Source Select These bits set the clock source for the Shift Register and counter The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input DI SDA when using external clock source USCK SCL When software strobe or Timer CounterO Compar
116. ad Indirect and Post Inc Rd X Xec X 1 None 2 LD Rd X Load Indirect and Pre Dec X lt X 1 Rd lt X None 2 LD Rd Y Load Indirect Rd Y None 2 LD Rd Y Load Indirect and Post Inc Rd Y Y Y 1 None 2 LD Rd Y Load Indirect and Pre Dec Y lt Y 1 Rd lt Y None 2 LDD Rd Y q Load Indirect with Displacement Rd Y q None 2 LD Rd Z Load Indirect Rd Z None 2 LD Rd Z Load Indirect and Post Inc Rd Z Z Z None 2 LD Rd Z Load Indirect and Pre Dec Ze Z 1 Rd Z None 2 LDD Rd Z q Load Indirect with Displacement Rd Z q None 2 LDS Rd k Load Direct from SRAM Rd lt k None 2 ST X Rr Store Indirec X Rr None 2 ST X Rr Store Indirect and Post Inc X Rr Xe X41 None 2 ST X Rr Store Indirect and Pre Dec X lt X 1 X Rr None 2 ST Y Rr Store Indirec Y Rr None 2 ST Y Rr Store Indirect and Post Inc Y Rr YH Y 1 None 2 ST Y Rr Store Indirect and Pre Dec Y lt Y 1 Y lt Rr None 2 STD Y q Rr Store Indirect with Displacemen Y q Rr None 2 ST Z Rr Store Indirec Z lt Rr None 2 ST Z Rr Store Indirect and Post Inc Z Rr Z Z 1 None 2 ST Z Rr Store Indirect and Pre Dec Z lt Z 1 Z lt Rr None 2 STD Z q Rr Store Indirect with Displacemen Z q lt Rr None 2 STS k Rr Store Direct to SRAM k Rr None 2 LPM Load Program Memory RO Z None 3 LPM Rd Z Load Program Memory Rd Z None 3 LPM Rd Z Load Program Memory and Post Inc Rd Z Z
117. adjust the fast peripheral clock at the same time However even if the RC oscillator is taken to a higher frequency than 8 MHz the fast peripheral clock frequency saturates at 85 MHz worst case and remains oscillating at the maximum frequency It should be noted that the PLL in this case is not locked any longer with the RC oscillator clock Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 8 MHz in order to keep the PLL in the correct operating range The internal PLL is enabled only when the PLLE bit in PLLCSR is set or the PLLCK fuse is programmed 0 The bit PLOCK from PLLCSR is set when PLL is locked Both internal RC oscillator and PLL are switched off in power down and stand by sleep modes ATtiny25 45 05 memme ATtiny25 45 85 Figure 6 2 PCK Clocking System OSCCAL PLLE PLLCK amp CKSEL FUSES CLKPS3 0 Lock Detector PLOCK RC OSCILLATOR PCK 8 0 MHz 64 25 6 MHz DIVIDE BY 4 SYSTEM System CLOCK gt Clock gt Prescaler XTAL1 XTAL2 OSCILLATORS 6 2 Clock Sources The device has the following clock source options selectable by Flash Fuse bits as shown below The clock from the selected source is input to the AVR clock generator and routed to the appropriate modules Table 6 1 Device Clocking Options Select Device Clocking Option CKSEL3 0 External Clock 0000 PLL Clock 0001 Calibrated Inter
118. al If this signal is cleared the Output driver is Override Enable enabled by the DDxn Register bit ee If DDOE is set the Output Driver is enabled disabled when Data Direction DDOV DDOV is set cleared regardless of the setting of the DDxn Override Value i Register bit If this signal is set and the Output Driver is enabled the port PVOE Port Value value is controlled by the PVOV signal If PVOE is cleared and Override Enable the Output Driver is enabled the port Value is controlled by the PORTxn Register bit PVOV Port Value If PVOE is set the port value is set to PVOV regardless of the Override Value setting of the PORTxn Register bit PTOE Port Toggle If PTOE is set the PORTxn Register bit is inverted Override Enable Digital Input If this bit is set the Digital Input Enable is controlled by the DIEOE Enable Override DIEOV signal If this signal is cleared the Digital Input Enable Enable is determined by MCU state Normal mode sleep mode Digital Input If DIEOE is set the Digital Input is enabled disabled when DIEOV Enable Override DIEOV is set cleared regardless of the MCU state Normal Value mode sleep mode This is the Digital Input to alternate functions In the figure the signal is connected to the output of the schmitt trigger but DI Digital Input before the synchronizer Unless the Digital Input is used as a clock source the module with the alternate function will use its own synchr
119. an easily be avoided by following this design recommendation Keep the AVR RESET active low during periods of insufficient power supply voltage This can be done by enabling the internal Brown out Detector BOD If the detection level of the internal BOD does not match the needed detection level an external low Voc reset protection circuit can be used If a reset occurs while a write operation is in progress the write operation will be com pleted provided that the power supply voltage is sufficient ATtiny25 45 05 memme 7598G AVR 03 08 5 4 O Memory The I O space definition of the ATtiny25 45 85 is shown in Register Summary on page 179 All ATtiny25 45 85 I Os and peripherals are placed in the I O space All I O locations may be accessed by the LD LDS LDD and ST STS STD instructions transferring data between the 32 general purpose working registers and the I O space I O Registers within the address range 0x00 Ox1F are directly bit accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SBIS and SBIC instructions Refer to the instruction set section for more details When using the I O specific commands IN and OUT the I O addresses 0x00 Ox3F must be used When addressing I O Registers as data space using LD and ST instructions 0x20 must be added to these addresses For compatibility with future devices reserved bits should be written to zero if accessed
120. and Tos is the temperature sensor offset value determined and stored into EEPROM as a part of produc tion test 18 7 5 ADC Multiplexer Selection Register ADMUX Bit 7 6 5 4 3 2 1 0 LRErsr REFSO ADLAR REFS2 MUX MUX2 moxt MUXO ADMUX Read Write R R W R W R R R R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 4 REFS2 REFSO Voltage Reference Selection Bits These bits select the voltage reference Vpep for the ADC as shown in Table 18 3 If these bits are changed during a conversion the change will not go in effect until this conversion is complete ADIF in ADCSR is set Whenever these bits are changed the next conversion will take 25 ADC clock cycles If active channels are used using Vcc or an external AREF higher than Vcc 1V as a voltage reference is not recommended as this will affect the ADC accuracy Table 18 3 Voltage Reference Selections for ADC REFS2 REFS1 REFSO Voltage Reference Vp_ Selection 0 0 0 Voc used as Voltage Reference disconnected from PBO AREF External Voltage Reference at PBO AREF pin Internal Voltage 0 0 1 Reference turned off 0 1 0 Internal 1 1V Voltage Reference without external bypass capacitor disconnected from PBO AREF 0 1 1 Internal 1 1V Voltage Reference with external bypass capacitor at PBO AREF pin 1 1 0 Internal 2 56V Voltage Reference without external bypass capacitor disconnected from PBO AREF 1 1 1 Internal
121. are Register B contains an 8 bit value that is continuously compared with the counter value TCNTO A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OCOB pin 12 8 6 Timer Counter Interrupt Mask Register TIMSK Bit 7 6 5 4 3 2 1 0 OCIE1A OCIE1B OCIEOA OCIEOB TOIE1 TOIEO TIMSK Read Write R R R R R W R W R W R Initial Value 0 0 0 0 0 0 0 0 Bits 7 4 0 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and will always read as zero Bit 3 OCIEOB Timer Counter Output Compare Match B Interrupt Enable When the OCIEOB bit is written to one and the I bit in the Status Register is set the Timer Counter Compare Match B interrupt is enabled The corresponding interrupt is executed if a Compare Match in Timer Counter occurs i e when the OCFOB bit is set in the Timer Counter Interrupt Flag Register TIFRO Bit 2 OCIEOA Timer Counter0 Output Compare Match A Interrupt Enable When the OCIEOA bit is written to one and the I bit in the Status Register is set the Timer CounterO Compare Match A interrupt is enabled The corresponding interrupt is executed if a Compare Match in Timer CounterO occurs i e when the OCFOA bit is set in the Timer Counter 0 Interrupt Flag Register TIFRO Bit 1 TOIEO Timer CounterO Overflow Interrupt Enable When the TOIEO bit is written to one and the I bit in the Status Register is set the Timer Count
122. be performed on the next Compare Match For compare output actions in the non PWM modes refer to Table 12 1 on page 72 For fast PWM mode refer to Table 12 2 on page 72 and for phase correct PWM refer to Table 12 3 on page 72 A change of the COMOx1 0 bits state will have effect at the first Compare Match after the bits are written For non PWM modes the action can be forced to have immediate effect by using the FOCOx strobe bits 12 6 Modes of Operation The mode of operation i e the behavior of the Timer Counter and the Output Compare pins is defined by the combination of the Waveform Generation mode WGMO02 0 and Compare Output mode COMOx1 0 bits The Compare Output mode bits do not affect the counting sequence while the Waveform Generation mode bits do The COMOx1 0 bits control whether the PWM out put generated should be inverted or not inverted or non inverted PWM For non PWM modes the COMOx1 0 bits control whether the output should be set cleared or toggled at a Compare Match Compare Match Output Unit on page 64 For detailed timing information refer to Figure 12 8 Figure 12 9 Figure 12 10 and Figure 12 11 in Timer Counter Timing Diagrams on page 70 AMEL s 7598G AVR 03 08 12 6 1 12 6 2 66 Normal Mode ATMEL The simplest mode of operation is the Normal mode WGM02 0 0 In this mode the counting direction is always up incrementing and no counter clear is performed The counter sim
123. bit Program Status Counter and Control 32x8 Instruction General Register Purpose Interrupt Registrers Unit E E PA PA 1 0 Module1 I O Module 2 I O Module n Instruction Decoder Control Lines Direct Addressing Indirect Addressing I O Lines EEPROM In order to maximize performance and parallelism the AVR uses a Harvard architecture with separate memories and buses for program and data Instructions in the Program memory are executed with a single level pipelining While one instruction is being executed the next instruc tion is pre fetched from the Program memory This concept enables instructions to be executed in every clock cycle The Program memory is In System Reprogrammable Flash memory The fast access Register File contains 32 x 8 bit general purpose working registers with a single clock cycle access time This allows single cycle Arithmetic Logic Unit ALU operation In a typ ical ALU operation two operands are output from the Register File the operation is executed and the result is stored back in the Register File in one clock cycle Six of the 32 registers can be used as three 16 bit indirect address register pointers for Data Space addressing enabling efficient address calculations One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory These added function registers are the 16 bit X Y and Z register describ
124. bit to enable nested interrupts All enabled interrupts can then interrupt the current interrupt routine The I bit is automatically set when a Return from Interrupt instruction RETI is executed There are basically two types of interrupts The first type is triggered by an event that sets the Interrupt Flag For these interrupts the Program Counter is vectored to the actual Interrupt Vec tor in order to execute the interrupt handling routine and hardware clears the corresponding Interrupt Flag Interrupt Flags can also be cleared by writing a logic one to the flag bit position s to be cleared If an interrupt condition occurs while the corresponding interrupt enable bit is AMEL n 7598G AVR 03 08 AMEL cleared the Interrupt Flag will be set and remembered until the interrupt is enabled or the flag is cleared by software Similarly if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared the corresponding Interrupt Flag s will be set and remembered until the Global Interrupt Enable bit is set and will then be executed by order of priority The second type of interrupts will trigger as long as the interrupt condition is present These interrupts do not necessarily have Interrupt Flags If the interrupt condition disappears before the interrupt is enabled the interrupt will not be triggered When the AVR exits from an interrupt it will always return to the main program and execute one mo
125. bits regardless of the CKDIV8 Fuse setting The Application software must ensure that a sufficient division factor is chosen if the selcted clock source has a higher frequency than the maximum frequency of the AMEL 2 7598G AVR 03 08 6 10 2 AMEL device at the present operating conditions The device is shipped with the CKDIV8 Fuse programmed Table 6 13 Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPSO Clock Division Factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Switching Time When switching between prescaler settings the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting nor the clock frequency corresponding to the new setting The ripple counter that implements the prescaler runs at the frequency of the undivided clock which may be faster than the CPU s clock frequency Hence it is not possible to determine the state of the prescaler even if it were readable and the exact time it takes to switch from one clock division to another cannot be exactly predicted From the time the CLKPS values are written it takes between T1
126. ble of the device s functions are operating All functions not needed should be disabled In particular the following modules may need special consideration when trying to achieve the lowest possible power consumption 7 6 1 Analog to Digital Converter If enabled the ADC will be enabled in all sleep modes To save power the ADC should be dis abled before entering any sleep mode When the ADC is turned off and on again the next conversion will be an extended conversion Refer to Analog to Digital Converter on page 107 for details on ADC operation 7 6 2 Analog Comparator When entering Idle mode the Analog Comparator should be disabled if not used When entering ADC Noise Reduction mode the Analog Comparator should be disabled In the other sleep modes the Analog Comparator is automatically disabled However if the Analog Comparator is set up to use the Internal Voltage Reference as input the Analog Comparator should be dis abled in all sleep modes Otherwise the Internal Voltage Reference will be enabled independent of sleep mode Refer to Analog Comparator on page 104 for details on how to configure the Analog Comparator 7 6 3 Brown out Detector If the Brown out Detector is not needed in the application this module should be turned off If the Brown out Detector is enabled by the BODLEVEL Fuses it will be enabled in all sleep modes and hence always consume power In the deeper sleep modes this will contribute significantly t
127. c WATCHDOG TIVER ENABLED lsc uA ss ATtiny25 45 05 sue 7598G AVR 03 08 ATtiny25 45 85 23 4 Pin Pull up Figure 23 13 I O Pin Pull Up Resistor Current vs Input Voltage Voc 1 8V VO PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 1 8V 0000 Figure 23 14 I O Pin Pull Up Resistor Current vs Input Voltage Vec 2 7V VO PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 2 7V 10 125 c 85 C 0 25 C 0 0 5 1 15 2 25 3 40 C AMEL 159 7598G AVR 03 08 AMEL Figure 23 15 I O Pin Pull Up Resistor Current vs Input Voltage Voc 5 0V VO PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 5 0V lop UA 125 C 85 C 25 C 40 C Figure 23 16 Reset Pull Up Resistor Current vs Reset Pin Voltage Vec 1 8V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Veo 1 8V t0 ATtiny25 45 05 nu 7598G AVR 03 08 Figure 23 17 Reset Pull Up Resistor Current vs Reset Pin Voltage Voc 2 7V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Vcc 2 7V keser UA Figure 23 18 Reset Pull Up Resistor Current vs Reset Pin Voltage Voc 5 0V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Vcc 5 0V 140 120 100 3 80 a E amp 60 40 20 125 C 0 85 C 0 1 2 3 4 5 6 bs e Vaeser V
128. c action pro grammed in COM1A1 and COM1A0 takes place as if a compare match had occurred but no interrupt is generated The FOC1A bit always reads as zero FOC1A is not in use if PWM1A bit is set Bit 1 PSR1 Prescaler Reset Timer Counter1 When this bit is set one the Timer Counter prescaler TCNT1 is unaffected will be reset The bit will be cleared by hardware after the operation is performed Writing a zero to this bit will have no effect This bit will always read as zero 14 1 3 Timer Counter1 TCNT1 Bit 7 6 5 4 3 2 1 0 sre D LLLE re Read Write R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 This 8 bit register contains the value of Timer Counter1 Timer Counter1 is realized as an up counter with read and write access Due to synchronization of the CPU Timer Counter1 data written into Timer Counter1 is delayed by one and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asynchronous mode 14 1 4 Timer Counter1 Output Compare RegisterA OCR1A Bit 7 6 5 4 3 2 1 0 see D SS oma Read Write R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 The output compare register A is an 8 bit read write register The Timer Counter Output Compare Register A contains data to be continuously compared with Timer Counter1 Actions on compare matches are specified in TCCR1 A compare match does only occur if Timer Counter1 counts to the OCR1A value A software write that sets
129. ccess takes one instruction and the requested data is available immediately When the EEPROM is read the CPU is halted for four cycles before the next instruction is executed The user should poll the EEPE bit before starting the read opera tion If a write operation is in progress it is neither possible to read the EEPROM nor to change the EEAR Register 5 3 6 Atomic Byte Programming Using Atomic Byte Programming is the simplest mode When writing a byte to the EEPROM the user must write the address into the EEAR Register and data into EEDR Register If the EEPMn bits are zero writing EEPE within four cycles after EEMPE is written will trigger the erase write operation Both the erase and write cycle are done in one operation and the total programming time is given in Table 20 1 The EEPE bit remains set until the erase and write operations are completed While the device is busy with programming it is not possible to do any other EEPROM operations AMEL M EE 7598G AVR 03 08 5 3 7 5 3 8 5 3 9 18 AMEL Split Byte Programming Erase Write It is possible to split the erase and write cycle in two different operations This may be useful if the system requires short access time for some limited period of time typically if the power sup ply voltage falls In order to take advantage of this method it is required that the locations to be written have been erased before the write operation But since the erase and w
130. ch dog Timer To disable an enabled Watchdog Timer the following procedure must be followed 1 Inthe same operation write a logic one to WDCE and WDE A logic one must be writ ten to WDE regardless of the previous value of the WDE bit 2 Within the next four clock cycles in the same operation write the WDE and WDP bits as desired but with the WDCE bit cleared 4 ATtiny25 45 05 ee 7598G AVR 03 08 8 3 2 Safety Level 2 In this mode the Watchdog Timer is always enabled and the WDE bit will always read as one A timed sequence is needed when changing the Watchdog Time out period To change the Watchdog Time out the following procedure must be followed 1 Inthe same operation write a logical one to WDCE and WDE Even though the WDE always is set the WDE must be written to one to start the timed sequence 2 Within the next four clock cycles in the same operation write the WDP bits as desired but with the WDCE bit cleared The value written to the WDE bit is irrelevant 9 Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny25 45 85 For a general explanation of the AVR interrupt handling refer to Reset and Interrupt Handling on page 11 9 1 Interrupt Vectors in ATtiny25 45 85 Table 9 1 Reset and Interrupt Vectors Vector Program No Address Source Interrupt Definition 1 0x0000 RESET TA Reset Brown out Reset 2 0x0001 INTO
131. components higher than the Nyquist frequency fapc 2 should not be present to avoid distortion from unpredictable signal convolution The user is advised to remove high frequency components with a low pass filter before applying the signals as inputs to the ADC ATtiny25 45 05 memme 7598G AVR 03 08 Figure 18 8 Analog Input Circuitry ADCn rt 1 100 kohm Coy 14 pF li Vcc 2 18 6 2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements If conversion accuracy is critical the noise level can be reduced by applying the following techniques a Keep analog signal paths as short as possible Make sure analog tracks run over the analog ground plane and keep them well away from high speed switching digi tal tracks b Use the ADC noise canceler function to reduce induced noise from the CPU c If any port pins are used as digital outputs it is essential that these do not switch while a conversion is in progress 18 6 3 ADC Accuracy Definitions An n bit single ended ADC converts a voltage linearly between GND and Vgge in 2 steps LSBs The lowest code is read as 0 and the highest code is read as 2 1 Several parameters describe the deviation from the ideal behavior Offset The deviation of the first transition 0x000 to 0x001 compared to the ideal transition at 0 5 LSB Ideal value 0 LSB Figure 18 9 Offset Error Output Cod
132. d instruction which returns the content at the selected address at serial output MISO At the end of the programming session RESET can be set high to commence normal operation 1334 ATtiny25 45 05 nu 7598G AVR 03 08 8 Power off sequence if needed Set RESET to 1 Turn Voc power off Table 21 9 Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay lwp FLASH 4 5 ms lwp EEPROM 4 0 ms lwp ERASE 4 0 ms lwp FUsE 4 5 ms Figure 21 2 Serial Programming Waveforms SERIAL DATA INPUT MOSI SERIAL DATA OUTPUT MISO SERIAL CLOCK INPUT SCK SAMPLE 7598G AVR 03 08 JEn PM Jr pep ET rt ee dt oo AMEL 135 136 AMEL Table 21 10 Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable 1010 0101 XXXX XXXX Enable Serial Programming 9 9 1100 0011 XXXX XXXX after RESET goes low Chip Erase 1010 100x XXXX XXXX Chip Erase EEPROM and p 1100 XXXX XXXX XXXX Flash Read Program 0010 0000 bbbb 0000 Read H high or low data o Membr 9 H000 000a bbbb 0000 from Program memory at y word address a b 0100 000x xxxb iiii Write H high or low data i to H000 XXXX bbbb iiii Program memory page at Load Program word address b Data low Memory Page byte must be load
133. d when entering an interrupt routine and restored when returning from an interrupt This must be handled by software The AVR Status Register SREG is defined as Bit 7 6 5 4 3 2 1 0 ET Tz se Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 I Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled The individual inter rupt enable control is then performed in separate control registers If the Global Interrupt Enable AMEL 7 8 AMEL Register is cleared none of the interrupts are enabled independent of the individual interrupt enable settings The l bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts The l bit can also be set and cleared by the application with the SEI and CLI instructions as described in the instruction set reference Bit 6 T Bit Copy Storage The Bit Copy instructions BLD Bit LoaD and BST Bit STore use the T bit as source or desti nation for the operated bit A bit from a register in the Register File can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction Bit 5 H Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations Half Carry is useful in BCD arithmetic See the Instruction Set Description for detailed informat
134. de with Watchdog Timer disabled represents the differential cur rent drawn by the Watchdog Timer AMEL 151 AMEL 23 1 Active Supply Current 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz Figure 23 2 Active Supply Current vs Frequency 1 20 MHz ACTIVE SUPPLY CURRENT vs FREQUENCY 1 20MHz Frequency MHz 152 ATtiny25 45 65 su ATtiny25 45 85 Figure 23 3 Active Supply Current vs Voc Internal RC Oscillator 128 kHz ACTIVE SUPPLY CURRENT vs Voc NTERNAL RC OSCLLATOR 128 KHz 0 25 0 2 0 15 lcc mA 0 1 0 05 Figure 23 4 Active Supply Current vs Voc Internal RC Oscillator 1 MHz ACTNE SUPPLY CURRENT vs Vcc NTERNAL RC OSCLLATOR 1 MHz AMEL 153 7598G AVR 03 08 AMEL Figure 23 5 Active Supply Current vs Voc Internal RC Oscillator 8 MHz ACTIVE SUPPLY CURRENT vs Vc NTERNAL RC OSCILLATOR 8 MHz 23 2 Idle Supply Current Figure 23 6 Idle Supply Current vs Frequency 0 1 1 0 MHz IDLE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 0 25 0 2 5 0V Idle mA ho CO N w lt lt 0 05 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz 154 ATtiny25 45 65 su 7598G AVR 03 08 7598G AVR 03 08 Figure 23 7 Idle Supply Current vs Frequency 1 20 MHz IDLE SUPPLY CURREN
135. e Ideal ADC Actual ADC Vrer Input Voltage AMEL 115 7598G AVR 03 08 AMEL Gain Error After adjusting for offset the Gain Error is found as the deviation of the last transition OXSFE to OX3FF compared to the ideal transition at 1 5 LSB below maximum Ideal value 0 LSB Figure 18 10 Gain Error Output Code Ideal ADC Actual ADC Vrer Input Voltage Integral Non linearity INL After adjusting for offset and gain error the INL is the maximum deviation of an actual transition compared to an ideal transition for any code Ideal value 0 LSB Figure 18 11 Integral Non linearity INL OutputCode Ideal ADC Actual ADC Veer dnput Voltage Differential Non linearity DNL The maximum deviation of the actual code width the interval between two adjacent transitions from the ideal code width 1 LSB Ideal value 0 LSB nes ATtiny25 45 65 sue Figure 18 12 Differential Non linearity DNL OuputCode 0 o e s Ox3FF Veer Input Voltage Quantization Error Due to the quantization of the input voltage into a finite number of codes a range of input voltages 1 LSB wide will code to the same value Always 0 5 LSB Absolute Accuracy The maximum deviation of an actual unadjusted transition compared to an ideal transition for any code This is the compound effect of offset gain error differential error non linearity and quantization error Ideal value 0
136. e Match clock option is selected the output latch is transparent and therefore the output is changed immediately Clearing the USICS1 0 bits enables software strobe option When using this option writing a one to the USICLK bit clocks both the Shift Register and the counter For external clock source USICS1 1 the USICLK bit is no longer used as a strobe but selects between external clocking and software clocking by the USITC strobe bit AMEL 103 7598G AVR 03 08 AMEL Table 16 2 shows the relationship between the USICS1 0 and USICLK setting and clock source used for the Shift Register and the 4 bit counter Table 16 2 Relations between the USICS1 0 and USICLK Setting USICS1 USICSO USICLK Shift Register Clock Source 4 bit Counter Clock Source 0 0 0 No Clock No Clock 0 0 1 Software clock strobe Software clock strobe USICLK USICLK 0 1 X Timer CounterO Compare Timer CounterO Compare Match Match 1 0 0 External positive edge External both edges 1 1 0 External negative edge External both edges 1 0 1 External positive edge Software clock strobe USITC 1 1 1 External negative edge Software clock strobe USITC Bit 1 USICLK Clock Strobe Writing a one to this bit location strobes the Shift Register to shift one step and the counter to increment by one provided that the USICS1 0 bits are set to zero and by doing so the software clock strobe option is selected The ou
137. e OxFF K ZN V 1 INC Rd Increment Rd Rd 1 ZN V 1 DEC Rd Decrement Rd Rd 1 Z N V 1 TST Rd Test for Zero or Minus Rd Rd e Rd Z N V 1 CLR Rd Clear Register Rd Rd Rd Z N V 1 SER Rd Set Register Rd OxFF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC PC k 1 None 2 IJMP Indirect Jump to Z PC Z None 2 RCALL k Relative Subroutine Call PC PC k 1 None 3 ICALL Indirect Call to Z PC lt Z None 3 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK 4 CPSE Rd Rr Compare Skip if Equal if Rd Rr PC PC 20r3 None 1 2 3 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 20r 3 None 1 2 3 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 20r 3 None 1 2 3 SBIC P b Skip if Bit in I O Register Cleared if P b 0 PC PC 2 0r3 None 1 2 3 SBIS P b Skip if Bit in I O Register is Set if P b 1 PC PC 20r 3 None 1 2 3 BRBS s k Branch if Status Flag Set if SREG s 1 then PC lt PC k 1 None 1 2 BRBC S k Branch if Status Flag Cleared if SREG s 0 then PC lt PC k 1 None 1 2 BREQ k Branch if Equal if Z 1 then PC PC k 1 None 1 2 BRNE k Branch if Not Equal if Z 0 then PC PC k 1 None 1 2 BRCS k Branch if Carry Set if C 1 then PC PC k 1 None 1 2 BRCC k Branch if Carry Cleared if
138. e Analog Comparator AMEL s 7598G AVR 03 08 56 AMEL OCOB Output Compare Match output The PB1 pin can serve as an external output for the Timer CounterO Compare Match B The PB1 pin has to be configured as an output DDB1 set one to serve this function The OCOB pin is also the output pin for the PWM mode timer function OC1A Output Compare Match output The PB1 pin can serve as an external output for the Timer Counter1 Compare Match B when configured as an output DDB1 set The OC1A pin is also the output pin for the PWM mode timer function DO Three wire mode Universal Serial Interface Data output Three wire mode Data output over rides PORTB1 value and it is driven to the port when data direction bit DDB1 is set one PORTB1 still enables the pull up if the direction is input and PORTB1 is set one PCINT1 Pin Change Interrupt source 1 Port B Bit 0 MOSI AINO OCOA OC1A DI SDA AREF PCINTO MOSI SPI Master Data output Slave Data input for SPI channel When the SPI is enabled as a Slave this pin is configured as an input regardless of the setting of DDBO When the SPI is enabled as a Master the data direction of this pin is controlled by DDBO When the pin is forced by the SPI to be an input the pull up can still be controlled by the PORTBO bit AINO Analog Comparator Positive Input Configure the port pin as input with the internal pull up switched off to avoid the digital port function from interfering
139. e Timer Counter Compare Match Interrupt is executed Bit 1 TOVO Timer CounterO Overflow Flag The bit TOVO is set when an overflow occurs in Timer CounterO TOVO is cleared by hardware when executing the corresponding interrupt handling vector Alternatively TOVO is cleared by writing a logic one to the flag When the SREG I bit TOIEO Timer CounterO Overflow Interrupt Enable and TOVO are set the Timer CounterO Overflow interrupt is executed The setting of this flag is dependent of the WGMO2 0 bit setting Refer to Table 12 7 Waveform Generation Mode Bit Description on page 74 13 Timer Counter Prescaler The Timer Counter can be clocked directly by the system clock by setting the CSn2 0 1 This provides the fastest operation with a maximum Timer Counter clock frequency equal to system clock frequency foi yo Alternatively one of four taps from the prescaler can be used as a clock source The prescaled clock has a frequency of either fc 0 8 fork 10 64 fci yo 256 or fork yo 1024 p i 13 0 1 Prescaler Reset The prescaler is free running i e operates independently of the Clock Select logic of the Timer Counter Since the prescaler is not affected by the Timer Counter s clock select the state of the prescaler will have implications for situations where a prescaled clock is used One exam ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler 6 gt CSn2 0 gt 1 The number of syste
140. e calculated by the following equation _ Jak VO focnxPWM N 256 The N variable represents the prescale factor 1 8 64 256 or 1024 The extreme values for the OCROA Register represents special cases when generating a PWM waveform output in the fast PWM mode If the OCROA is set equal to BOTTOM the output will be a narrow spike for each MAX 1 timer clock cycle Setting the OCROA equal to MAX will result in a constantly high or low output depending on the polarity of the output set by the COMOA1 0 bits A frequency with 50 duty cycle waveform output in fast PWM mode can be achieved by set ting OCOx to toggle its logical level on each Compare Match COMOx1 0 1 The waveform generated will have a maximum frequency of foco fek 0 2 when OCROA is set to zero This feature is similar to the OCOA toggle in CTC mode except the double buffer feature of the Out put Compare unit is enabled in the fast PWM mode 12 6 4 Phase Correct PWM Mode The phase correct PWM mode WGMO02 0 1 or 5 provides a high resolution phase correct PWM waveform generation option The phase correct PWM mode is based on a dual slope operation The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT TOM TOP is defined as OXFF when WGM2 0 1 and OCROA when WGM2 0 5 In non inverting Compare Output mode the Output Compare OCOx is cleared on the Compare Match between TCNTO and OCROx while upcounting and set on the Compare Match while d
141. e caused by two situations when the voltage is too low First a regular write sequence to the Flash requires a minimum voltage to operate correctly Secondly the CPU itself can execute instructions incorrectly if the supply voltage for executing instructions is too low Flash corruption can easily be avoided by following these design recommendations one is sufficient 1 Keep the AVR RESET active low during periods of insufficient power supply voltage This can be done by enabling the internal Brown out Detector BOD if the operating voltage matches the detection level If not an external low Vcc reset protection circuit can be used If a reset occurs while a write operation is in progress the write operation will be completed provided that the power supply voltage is sufficient 2 Keep the AVR core in Power down sleep mode during periods of low Vcc This will pre vent the CPU from attempting to decode and execute instructions effectively protecting the SPMCSR Register and thus the Flash from unintentional writes 20 1 5 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses Table 20 1 shows the typical pro gramming time for Flash accesses from the CPU Table 20 1 SPM Programming Time Symbol Min Programming Time Max Programming Time Flash write Page Erase Page Write and write Lock bits by SPM 3 7 ms 4 5 ms 21 Memory Programming This section describes the different
142. e cleared before disabling the Watchdog with the procedure described above This feature ensures multiple resets during conditions causing failure and a safe start up after the failure Note If the watchdog timer is not going to be used in the application it is important to go through a watchdog disable procedure in the initialization of the device If the Watchdog is accidentally enabled for example by a runaway pointer or brown out condition the device will be reset which in turn will lead to a new watchdog reset To avoid this situation the application software should always clear the WDRF flag and the WDE control bit in the initialization routine Bits 5 2 0 WDP3 0 Watchdog Timer Prescaler 3 2 1 and 0 2 ATtiny25 45 05 mememe 7598G AVR 03 08 The WDP3 0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled The different prescaling values and their corresponding Timeout Periods are shown in Table 8 7 Table 8 7 Watchdog Timer Prescale Select Number of WDT Oscillator Typical Time out at WDP3 WDP2 WDP1 WDPO Cycles Vec 5 0V 0 0 0 0 2K cycles 16 ms 0 0 0 1 4K cycles 32 ms 0 0 1 0 8K cycles 64 ms 0 0 1 1 16K cycles 0 125s 0 1 0 0 32K cycles 0 25s 0 1 0 1 64K cycles 0 5s 0 1 1 0 128K cycles 1 0s 0 1 1 1 256K cycles 20s 1 0 0 0 512K cycles 4 0s 1 0 0 1 1024K cycles 8 0 s 1 0 1 0 1 0 1 1 1 1 0 0 Reserved 1 1
143. e of program and system development tools including C Compilers Macro Assemblers Program Debugger Simulators In Circuit Emulators and Evaluation kits Automotive Quality Grade The ATtiny25 45 85 have been developed and manufactured according to the most stringent requirements of the international standard ISO TS 16949 This data sheet contains limit values extracted from the results of extensive characterization Temperature and Voltage The quality and reliability of the ATtiny25 45 85 have been verified during regular product qualification as per AEC Q100 grade 1 As indicated in the ordering information paragraph the products are available in three different temperature grades but with equivalent quality and reliability objectives Different temperature identifiers have been defined as listed in Table 2 1 Table 2 1 Temperature Grade Identification for Automotive Products Temperature Temperature Identifier Comments 40 485 T Similar to Industrial Temperature Grade but with Automotive Quality 40 4105 T1 Reduced Automotive Temperature Range 40 4125 Z Full AutomotiveTemperature Range ATtiny25 45 05 cummm 7598G AVR 03 08 2 3 Pin Descriptions 2 3 1 vcc 2 3 2 GND Supply voltage Ground 2 3 3 Port B PB5 PBO 2 3 4 RESET Port B is a 6 bit bi directional I O port with internal pull up resistors selected for each bit The Port B output buffers have symmetrical drive characteristics wi
144. ead port pins i PINB Note 1 For the assembly program two temporary registers are used to minimize the time from pull ups are set on pins 0 1 and 4 until the direction bits are correctly set defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers Digital Input Enable and Sleep Modes As shown in Figure 10 2 the digital input signal can be clamped to ground at the input of the schmitt trigger The signal denoted SLEEP in the figure is set by the MCU Sleep Controller in Power down mode Power save mode and Standby mode to avoid high power consumption if some input signals are left floating or have an analog signal level close to V 2 SLEEP is overridden for port pins enabled as external interrupt pins If the external interrupt request is not enabled SLEEP is active also for these pins SLEEP is also overridden by various other alternate functions as described in Alternate Port Functions on page 52 If a logic high level one is present on an asynchronous external interrupt pin configured as Interrupt on Rising Edge Falling Edge or Any Logic Change on Pin while the external interrupt is not enabled the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode as the clamping in these sleep mode produces the requested logic change AMEL s 10 2 6 AMEL Unconnected Pins If some pins are unused it is recommended to ensure that th
145. ed level must be held for some time to wake up the MCU Refer to External Interrupts on page 58 for details Table 7 2 Active Clock Domains and Wake up Sources in the Different Sleep Modes Active Clock Domains Oscillators Wake up Sources c 2 9 5 a o x oO oO oO X 8 ui g E 5 Q 3 o9 E o x Og os o gt 8 25 a 4 Qa O c2 oO o e D o E 6 T o a 5 SA y pes Oo o x x x x x So Es ow o Hn als oo Sleep Mode o o o 20 2a Ow C 2 O ES Idle X X X X X X X X X X ADG Noise X X x X x x X Reduction Power down x X X 7 4 Limitations Note 1 For INTO only level interrupt BOD disable functionality has been implemented in the following devices only ATtiny25 revision D and newer ATtiny45 revision D and newer ATtiny85 revision C and newer 7 5 Power Reduction Register 7598G AVR 03 08 The Power Reduction Register PRR provides a method to stop the clock to individualperipher als to reduce power consumption The current state of the peripheral is frozenand the I O registers can not be read or written Resources used by the peripheral when stopping the clock will remain occupied hence the peripheral should in most cases be disabled before stopping the clock Waking up a module which is done by clearing the bit in PRR puts the module in the same state as before shutdown Module shutdown can be used in Idle mode and Active mode to significant
146. ed before Data high byte is applied within the same address Write Program 0100 0000 bbxx XXXX Write Program memory Page Memory Page 100 000a XXXX XXXX at address a b Read EEPROM 1010 000x xxbb oooo Read data o from EEPROM Memory 0000 XXXX bbbb oooo memory at address b Write EEPROM 1100 000x xxbb iiii Write data i to EEPROM Memory 0000 XXXX bbbb iiii memory at address b Load EEPROM 1100 0000 0000 iiii Load data i to EEPROM 0001 0000 00bb iiii memory page buffer After Memory Page page access data is loaded program EEPROM page Memory Page page ooro ioo peoo ou Wille EEPROM page at y age pag mS i address b access 0101 0000 XXXX Xxoo Read Lock bits 0 Read Lock bits 1000 0000 XXXX 0000 programmed 1 unprogrammed See Table 21 1 on page 130 for details 1010 111x XXXX 11ii Write Lock bits Set bits 0 1 1100 XXXX XXXX iiii to program Lock bits See varte CORE DIIS Table 21 1 on page 130 for details 0011 000x XXXX oooo Read Signature Byte o at Read Signature Byte 0000 XXXX xxbb 0000 address b 1010 1010 XXXX iiii Set bits 0 to program 1 Write Fuse bits 1100 0000 XXXX iiii to unprogram See Table 21 5 on page 131 for details 10 1010 XXXX iiii Set bits 0 to program 1 Write Fuse High bits 1100 1000 XXXX iiii to unprogram See Table 21 4 on page 131 for details 1010 1010 XXXX XXXX Set bits 0 to program 1 Extended Fuse 100 0100 XXXX xxxi to unprogram See Table 2
147. ed later in this section 6 ATtiny25 45 05 memme The ALU supports arithmetic and logic operations between registers or between a constant and a register Single register operations can also be executed in the ALU After an arithmetic opera tion the Status Register is updated to reflect information about the result of the operation Program flow is provided by conditional and unconditional jump and call instructions able to directly address the whole address space Most AVR instructions are 16 bits wide There are also 32 bit instructions During interrupts and subroutine calls the return address Program Counter PC is stored on the Stack The Stack is effectively allocated in the general data SRAM and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM All user programs must initialize the SP in the Reset routine before subroutines or interrupts are executed The Stack Pointer SP is read write accessible in the I O space The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture The memory spaces in the AVR architecture are all linear and regular memory maps A flexible interrupt module has its control registers in the I O space with an additional Global Interrupt Enable bit in the Status Register All interrupts have a separate Interrupt Vector in the Interrupt Vector table The interrupts have priority in accordance with their Interru
148. ed so that no interrupts will occur during execution of these functions Assembly Code Example EEPROM_read Wait for completion of previous write sbic EECR EEPE rjmp EEPROM read Set up address r17 in address register out EEARL r17 Start eeprom read by writing EERE sbi EECR EERE Read data from data register in r16 EEDR ret C Code Example unsigned char EEPROM read unsigned char ucAddress Wait for completion of previous write while EECR amp 1 lt lt EEPE Set up address register EEARL ucAddress Start eeprom read by writing EERE EECR 1 lt lt EERE Return data from data register return EEDR Preventing EEPROM Corruption During periods of low Voc the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly These issues are the same as for board level systems using EEPROM and the same design solutions should be applied An EEPROM data corruption can be caused by two situations when the voltage is too low First a regular write sequence to the EEPROM requires a minimum voltage to operate correctly Sec ondly the CPU itself can execute instructions incorrectly if the supply voltage is too low EEPROM data corruption c
149. er on page 77 12 3 Counter Unit The main part of the 8 bit Timer Counter is the programmable bi directional counter unit Figure 12 2 shows a block diagram of the counter and its surroundings Figure 12 2 Counter Unit Block Diagram TOVn DATA BUS In Req Detector From Prescaler bottom top Signal description internal signals count Increment or decrement TCNTO by 1 direction Select between increment and decrement clear Clear TCNTO set all bits to zero clk Timer Counter clock referred to as clk in the following top Signalize that TCNTO has reached maximum value bottom Signalize that TCNTO has reached minimum value zero Depending of the mode of operation used the counter is cleared incremented or decremented at each timer clock clky9 clktg can be generated from an external or internal clock source selected by the Clock Select bits CS02 0 When no clock source is selected CS02 0 0 the timer is stopped However the TCNTO value can be accessed by the CPU regardless of whether clk is present or not A CPU write overrides has priority over all counter clear or count operations The counting sequence is determined by the setting of the WGM01 and WGMOO bits located in the Timer Counter Control Register TCCROA and the WGM02 bit located in the Timer Counter 62 ATtiny25 45 05 cummm Control Register B TCCROB There are close connections between how the counter behaves counts and how waveforms a
150. erO Overflow interrupt is enabled The corresponding interrupt is executed if an overflow in Timer CounterO occurs i e when the TOVO bit is set in the Timer Counter O Inter rupt Flag Register TIFRO 12 8 7 Timer Counter 0 Interrupt Flag Register TIFR Bit 7 6 5 4 3 2 1 0 OCFIA OCFIB OCFOA OCFOB TOV1 TOVO TFR Read Write R R W R W R W R W R W R W R Initial Value 0 0 0 0 0 0 0 0 Bits 7 0 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and will always read as zero Bit 4 OCFOA Output Compare Flag 0 A 76 ATtiny25 45 05 memme The OCFOA bit is set when a Compare Match occurs between the Timer CounterO and the data in OCROA Output Compare Register0 OCFOA is cleared by hardware when executing the cor responding interrupt handling vector Alternatively OCFOA is cleared by writing a logic one to the flag When the I bit in SREG OCIEOA Timer CounterO Compare Match Interrupt Enable and OCFOA are set the Timer CounterO Compare Match Interrupt is executed Bit 3 OCFOB Output Compare Flag 0 B The OCFOB bit is set when a Compare Match occurs between the Timer Counter and the data in OCROB Output Compare RegisterO B OCFOB is cleared by hardware when executing the cor responding interrupt handling vector Alternatively OCFOB is cleared by writing a logic one to the flag When the I bit in SREG OCIEOB Timer Counter Compare B Match Interrupt Enable and OCFOB are set th
151. erflow Interrupt Flag This flag is set one when the 4 bit counter overflows i e at the transition from 15 to 0 An interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global Interrupt Enable Flag are set The flag will only be cleared if a one is written to the USIOIF bit Clearing this bit will release the counter overflow hold of SCL in Two wire mode A counter overflow interrupt will wakeup the processor from Idle sleep mode e Bit 5 USIPF Stop Condition Flag When Two wire mode is selected the USIPF Flag is set one when a stop condition is detected The flag is cleared by writing a one to this bit Note that this is not an Interrupt Flag This signal is useful when implementing Two wire bus master arbitration Bit 4 USIDC Data Output Collision AMEL 101 7598G AVR 03 08 16 4 4 102 AMEL This bit is logical one when bit 7 in the Shift Register differs from the physical pin value The flag is only valid when Two wire mode is used This signal is useful when implementing Two wire bus master arbitration Bits 3 0 USICNT3 0 Counter Value These bits reflect the current 4 bit counter value The 4 bit counter value can directly be read or written by the CPU The 4 bit counter increments by one for each clock generated either by the external clock edge detector by a Timer CounterO Compare Match or by software using USICLK or USITC strobe bits The clock source depends of t
152. erved during Chip Erase if the EESAVE Fuse is programmed 1 Load command Chip Erase see Table 21 16 2 Wait after Instr 3 until SDO goes high for the Chip Erase cycle to finish 3 Load Command No Operation 21 8 4 Programming the Flash The Flash is organized in pages see Table 21 10 on page 136 When programming the Flash the program data is latched into a page buffer This allows one page of program data to be pro grammed simultaneously The following procedure describes how to program the entire Flash memory 1 Load Command Write Flash see Table 21 16 2 Load Flash Page Buffer 3 Load Flash High Address and Program Page Wait after Instr 3 until SDO goes high for the Page Programming cycle to finish 4 Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed 5 End Page Programming by Loading Command No Operation When writing or reading serial data to the ATtiny25 45 85 data is clocked on the rising edge of the serial clock see Figure 21 6 Figure 21 7 and Table 21 17 for details uo ATtiny25 45 05 su Figure 21 5 Addressing the Flash which is Organized in Pages PAGEMSB PROGRAM COUNTER PCPAGE PCWORD PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY ee Bo PAGE PCWORD PAGEMSB 0 PAGE Erud ere INSTRUCTION WORD 00 NN desse Scd MN 01 02 gt eee ened PAGEEND Figu
153. ese pins have a defined level Even though most of the digital inputs are disabled in the deep sleep modes as described above float ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled Reset Active mode and Idle mode The simplest method to ensure a defined level of an unused pin is to enable the internal pull up In this case the pull up will be disabled during reset If low power consumption during reset is important it is recommended to use an external pull up or pulldown Connecting unused pins directly to Vcc or GND is not recommended since this may cause excessive currents if the pin is accidentally configured as an output 10 3 Alternate Port Functions 52 Most port pins have alternate functions in addition to being general digital I Os Figure 10 5 shows how the port pin control signals from the simplified Figure 10 2 can be overridden by alternate functions The overriding signals may not be present in all port pins but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family Figure 10 5 Alternate Port Functions PUOExn PUOVxn I C b DDOExn DDOVxn DATA BUS DIEOExn DIEOVxn clk yo Dixn p AlOxn PUOExn Pxn PULL UP OVERRIDE ENABLE PUD PULLUP DISABLE PUOVxn Pxn PULL UP OVERRIDE VALUE WDx WRITE DDRx DDOExn Pxn DATA DIRECTION OVERRIDE ENABLE RDx READ DDRx DDOVxn Pxn DATA DIRECTI
154. et source goes active This does not require any clock source to be running After all reset sources have gone inactive a delay counter is invoked stretching the internal reset This allows the power to reach a stable level before normal operation starts The time out period of the delay counter is defined by the user through the SUT and CKSEL Fuses The dif ferent selections for the delay period are presented in Clock Sources on page 23 The ATtiny25 45 85 has four sources of reset Power on Reset The MCU is reset when the supply voltage is below the Power on Reset threshold Vpo External Reset The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length Watchdog Reset The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled e Brown out Reset The MCU is reset when the supply voltage Vcc is below the Brown out Reset threshold Vgo7 and the Brown out Detector is enabled AMEL s AMEL Figure 8 1 Reset Logic DATA BUS gt MCU Status Register MCUSR LL WL x oc meal ee vec ower on Rese i Brown out I BODLEVEL 1 0 Reset Circuit EXTRF WDR Wu Pull up Resistor 9 SPIKE RESET 4 Reset Circuit i S Q B Z R th E zZ Watchdog Timer COUNTER RESET Watchdog Oscillator Clock CK Generator lt Delay Counters TIMEOUT CK
155. et to a normal or CTC mode non PWM Table 12 1 Compare Output Mode non PWM Mode COM01 COMOO Description 0 0 Normal port operation OCOA disconnected 0 1 Toggle OCOA on Compare Match 1 0 Clear OCOA on Compare Match 1 1 Set OCOA on Compare Match Table 12 2 shows the COMOA1 0 bit functionality when the WGMO 1 0 bits are set to fast PWM mode Table 12 2 Compare Output Mode Fast PWM Mode COM01 COMOO Description 0 0 Normal port operation OCOA disconnected 0 1 WGMO2 0 Normal Port Operation OCOA Disconnected WGMO2 1 Toggle OCOA on Compare Match 1 0 Clear OCOA on Compare Match set OCOA at TOP 1 1 Set OCOA on Compare Match clear OCOA at TOP Note 1 A special case occurs when OCROA equals TOP and COMOA1 is set In this case the Com pare Match is ignored but the set or clear is done at TOP See Fast PWM Mode on page 67 for more details Table 12 3 shows the COMOA1 0 bit functionality when the WGMO2 0 bits are set to phase cor rect PWM mode Table 12 3 Compare Output Mode Phase Correct PWM Mode COMOA1 COMO0A0 Description 0 0 Normal port operation OCOA disconnected 0 1 WGM02 0 Normal Port Operation OCOA Disconnected WGM02 1 Toggle OCOA on Compare Match Clear OCOA on Compare Match when up counting Set OCOA on 1 0 i Compare Match when down counting 1 1 Set OCOA on Compare Match when up counting Clear OCOA on Compare Match when do
156. f Pin Change Interrupt Request is executed from the PCI Interrupt Vector PCINT5 0 pins are enabled individually by the PCMSKO Register 11 0 3 General Interrupt Flag Register GIFR 7598G AVR 03 08 Bit 7 6 5 4 3 2 1 0 LL OD Read Write R R W R W R R R R R Initial Value 0 0 0 0 0 0 0 0 Bits 7 4 0 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and will always read as zero Bit 6 INTFO External Interrupt Flag 0 AMEL s 11 0 4 AMEL When an edge or logic change on the INTO pin triggers an interrupt request INTFO becomes set one If the l bit in SREG and the INTO bit in GIMSK are set one the MCU will jump to the cor responding Interrupt Vector The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a logical one to it This flag is always cleared when INTO is configured as a level interrupt Bit 5 PCIF Pin Change Interrupt Flag When a logic change on any PCINT5 0 pin triggers an interrupt request PCIF becomes set one If the I bit in SREG and the PCIE bit in GIMSK are set one the MCU will jump to the cor responding Interrupt Vector The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a logical one to it Pin Change Mask Register PCMSK Bit 7 6 5 4 3 2 1 0 PF o j PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINTO PCMSK Read Write R R R W R W R
157. f the page must be stored for example in the temporary page buffer before the erase and then be re written When using alternative 1 the Boot Loader provides an effective Read Modify Write feature which allows the user software to first read the page do the necessary changes and then write back the modified data If alter native 2 is used it is not possible to read the old data while loading since the page is already ATMEL 125 AMEL erased The temporary page buffer can be accessed in a random sequence It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page 20 0 1 Performing Page Erase by SPM To execute Page Erase set up the address in the Z pointer write 00000011 to SPMCSR and execute SPM within four clock cycles after writing SPMCSR The data in R1 and RO is ignored The page address must be written to PCPAGE in the Z register Other bits in the Z pointer will be ignored during this operation The CPU is halted during the Page Erase operation 20 0 2 Filling the Temporary Buffer Page Loading To write an instruction word set up the address in the Z pointer and data in R1 RO write 00000001 to SPMCSR and execute SPM within four clock cycles after writing SPMCSR The content of PCWORD in the Z register is used to address the data in the temporary buffer The temporary buffer will auto erase after a Page Write operation or by writing the CTPB bit in SPMCSR
158. factured by Atmel 2 0x001 0x93 indicates 8 KB Flash memory 3 0x002 OxOB indicates ATtiny85 device when 0x001 is 0x93 21 4 Calibration Byte Signature area of the ATtiny25 45 85 has one byte of calibration data for the internal RC Oscilla tor This byte resides in the high byte of address 0x000 During reset this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator 21 5 Page Size Table 21 6 No of Words in a Page and No of Pages in the Flash Device Flash Size Page Size PCWORD No of Pages PCPAGE PCMSB 1K words i ATtiny25 2K bytes 16 words PC 3 0 64 PC 9 4 9 2K words ATtiny45 4K bytes 32 words PC 4 0 64 PC 10 5 10 4K words f ATtiny85 8K bytes 32 words PC 4 0 128 PC 11 5 11 132 ATtiny25 45 85 E KKK lt iCi____ ee 7598G AVR 03 08 Table 21 7 No of Words in a Page and No of Pages in the EEPROM EEPROM Device Size Page Size PCWORD No of Pages PCPAGE EEAMSB ATtiny25 128 bytes 4 bytes EEA 1 0 32 EEA 6 2 6 ATtiny45 256 bytes 4 bytes EEA 1 0 64 EEA 7 2 7 ATtiny85 512 bytes 4 bytes EEA 1 0 128 EEA 8 2 8 21 6 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND The serial interface consists of pins SCK MOSI input and MISO out put After RESET is set low the Programm
159. four like shown in Table 6 10 When this clock source is selected start up times are determined by the SUT fuses as shown in Table 6 11 See also PCK Clocking System on page 23 Table 6 10 PLLCK Operating Modes CKSEL3 0 Nominal Frequency 0001 16 MHz Table 6 11 Start up Times for the PLLCK Start up Time from Power Additional Delay from SUT1 0 Down and Power Save Reset Vcc 5 0V Recommended usage 00 1K CK 14CK 8ms BOD enabled 01 16K CK 14CK 8ms Fast rising power 10 1K CK 14CK 68 ms Slowly rising power 11 16K CK 14CK 68 ms Slowly rising power 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz The fre quency is nominal at 3V and 25 C This clock may be select as the system clock by programming the CKSEL Fuses to 11 When this clock source is selected start up times are determined by the SUT Fuses as shown in Table 6 12 Table 6 12 Start up Times for the 128 kHz Internal Oscillator Start up Time from Power Additional Delay from SUT1 0 down and Power save Reset Recommended Usage 00 6 CK 14CK BOD enabled 01 6 CK 14CK 4 ms Fast rising power 10 6 CK 14CK 64 ms Slowly rising power 11 Reserved Clock Output Buffer The device can output the system clock on the CLKO pin To enable the output the CKOUT Fuse has to be programmed This mode is suitable when the chip clock is
160. ftware Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction Setting a Break Point in AVR Studio will insert a BREAK instruction in the Program memory The instruc tion replaced by the BREAK instruction will be stored When program execution is continued the stored instruction will be executed before continuing from the Program memory A break can be inserted manually by putting the BREAK instruction in the program The Flash must be re programmed each time a Break Point is changed This is automatically handled by AVR Studio through the debugWIRE interface The use of Break Points will therefore reduce the Falsh Data retention Devices used for debugging purposes should not be shipped to end customers 124 ATtiny25 45 05 memm 19 5 Limitations of debugWIRE The debugWIRE communication pin dW is physically located on the same pin as External Reset RESET An External Reset source is therefore not supported when the debugWIRE is enabled The debugWIRE system accurately emulates all I O functions when running at full speed i e when the program in the CPU is running When the CPU is stopped care must be taken while accessing some of the I O Registers via the debugger AVR Studio A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes This will increase the power consumption while in sleep Thus the DWEN Fuse should be disabled when debugWire is not used 19
161. ges the output at positive edges The USI clock modes corresponds to the SPI data mode 0 and 1 Referring to the timing diagram Figure 16 3 a bus transfer involves the following steps 1 The Slave device and Master device sets up its data output and depending on the pro tocol used enables its output driver mark A and B The output is set up by writing the AMEL s 7598G AVR 03 08 AMEL data to be transmitted to the Serial Data Register Enabling of the output is done by set ting the corresponding bit in the port Data Direction Register Note that point A and B does not have any specific order but both must be at least one half USCK cycle before point C where the data is sampled This must be done to ensure that the data setup requirement is satisfied The 4 bit counter is reset to zero 2 The Master generates a clock pulse by software toggling the USCK line twice C and D The bit value on the slave and master s data input DI pin is sampled by the USI on the first edge C and the data output is changed on the opposite edge D The 4 bit counter will count both edges 3 Step 2 is repeated eight times for a complete register byte transfer 4 After eight clock pulses i e 16 clock edges the counter will overflow and indicate that the transfer is completed The data bytes transferred must now be processed before a new transfer can be initiated The overflow interrupt will wake up the processor if it is set to Id
162. h CTC mode and two types of Pulse Width Modulation PWM modes see Modes of Operation on page 65 Table 12 7 Waveform Generation Mode Bit Description Timer Counter Mode of Update of TOV Fla Mode WGM2 WGM1 WGMO Operation TOP OCRx at Set on 0 0 0 0 Normal OxFF Immediate MAX 1 0 0 1 PWM Phase OxFF TOP BOTTOM Correct 2 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM OxFF TOP MAX 4 1 0 0 Reserved 5 1 0 1 Leese OCRA TOP BOTTOM Correct 6 1 1 0 Reserved 7 1 1 1 Fast PWM OCRA TOP TOP Notes 1 MAX OxFF 2 BOTTOM 0x00 Timer Counter Control Register B TCCROB Bit 7 6 5 4 3 2 1 0 Foco Focas wem cso esn C90 ccm Read Write W Ww R R R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 FOCOA Force Output Compare A The FOCOA bit is only active when the WGM bits specify a non PWM mode However for ensuring compatibility with future devices this bit must be set to zero when TCCROB is written when operating in PWM mode When writing a logical one to the FOCOA bit an immediate Compare Match is forced on the Waveform Generation unit The OCOA output is changed according to its COMOA1 0 bits setting Note that the FOCOA bit is implemented as a strobe Therefore it is the value present in the COMOA1 0 bits that determines the effect of the forced compare A FOCOA strobe will not generate any interrupt nor will it clear the timer in CT
163. he Flash byte by byte also the LSB bit ZO of the Z pointer is used 16 ATtiny25 45 05 nu Figure 20 1 Addressing the Flash During SPM BIT 15 ZPCMSB ZPAGEMSB 1 0 Z REGISTER 0 SHOGR PCMSB PAGEMSB COUNTER PCPAGE PCWORD PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD PAGEMSB 0 FAGE NR INSTRUCTION WORD 00 01 02 PAGEEND Note 1 The different variables used in Figure 20 1 are listed in Table 21 6 on page 132 20 1 1 Store Program Memory Control and Status Register SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to con trol the Program memory operations Bit 7 6 5 4 3 2 1 0 Es errs T wes T Pawar Pcens SPMEN sposa Read Write R R R R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 7 5 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and always read as zero Bit 4 CTPB Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer the temporary page buffer will be cleared and the data will be lost Bit 3 RFLB Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register will read either the Lock bits or the Fuse bits depending on ZO in the Z pointer into the destina tion register See EEPROM Write Prevents Writing to SPMCSR on
164. he ATtiny25 45 85 and their dis tribution The figure is helpful in selecting an appropriate sleep mode 7 0 1 MCU Control Register MCUCR The MCU Control Register contains control bits for power management Bit 7 6 5 4 3 2 1 0 BODS PUD se sm smo BODSE j isem sco wcucn Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 BODS BOD Sleep BOD disable functionality is available in some devices only See Limitations on page 33 In order to disable BOD during sleep see Table 7 2 on page 33 the BODS bit must be written to logic one This is controlled by a timed sequence and the enable bit BODSE in MCUCR First both BODS and BODSE must be set to one Second within four clock cycles BODS must be set to one and BODSE must be set to zero The BODS bit is active three clock cycles after it is set A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode The BODS bit is automatically cleared after three clock cycles In devices where Sleeping BOD has not been implemented this bit is unused and will always read zero Bit5 SE Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed To avoid the MCU entering the sleep mode unless it is the programmer s purpose it is recommended to write the Sleep Enable SE bit to one just before the execution of the SLEEP instructio
165. he Analog Com parator interrupt is activated When written logic zero the interrupt is disabled Bit 2 Res Reserved Bit This bit is a reserved bit in the ATtiny25 45 85 and will always read as zero Bits 1 0 ACIS1 ACISO Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt The different settings are shown in Table 17 1 Table 17 1 ACIS1 ACISO Settings ACIS1 ACISO Interrupt Mode 0 0 Comparator Interrupt on Output Toggle 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge When changing the ACIS1 ACISO bits the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register Otherwise an interrupt can occur when the bits are changed Analog Comparator Multiplexed Input It is possible to select any of the ADC3 0 pins to replace the negative input to the Analog Com parator The ADC multiplexer is used to select this input and consequently the ADC must be switched off to utilize this feature If the Analog Comparator Multiplexer Enable bit ACME in ADCSRB is set and the ADC is switched off ADEN in ADCSRA is zero MUX1 0 in ADMUX select the input pin to replace the negative input to the Analog Comparator as shown in Table 17 2 If ACME is cleared or ADEN is set AIN1 is applied to the negative input to the Analog Compara
166. he Analog Comparator The user can select Interrupt triggering on comparator output rise fall or toggle A block diagram of the comparator and its surrounding logic is shown in Figure 17 1 ATtiny25 45 05 memme 7598G AVR 03 08 Figure 17 1 Analog Comparator Block Diagram ANALOG COMPARATOR IRQ INTERRUPT SELECT ACIS1 ACISO ADC MULTIPLEXER OUTPUT Notes 1 See Table 17 2 on page 106 2 Refer to Figure 1 1 on page 2 and Table 10 5 on page 57 for Analog Comparator pin placement 17 0 1 ADC Control and Status Register B ADCSRB Bit 7 6 5 4 3 2 1 0 ew T cme TPR Abs T Aorsr ADTSO apcsne Read Write R R W R R R R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit6 ACME Analog Comparator Multiplexer Enable ATtiny25 45 85 When this bit is written logic one and the ADC is switched off ADEN in ADCSRA is zero the ADC multiplexer selects the negative input to the Analog Comparator When this bit is written logic zero AIN1 is applied to the negative input of the Analog Comparator For a detailed description of this bit see Analog Comparator Multiplexed Input on page 106 17 0 2 Analog Comparator Control and Status Register ACSR Bit 7 6 5 4 3 2 1 0 ACG Aci Acist ACIS csr Read Write R W R W R R W R W R R W R W Initial Value 0 0 N A 0 0 0 0 0 Bit 7 ACD Analog Comparator Disable When this bit is written logic one the power to the Analog Comparator is switched off
167. he setting of the USICS1 0 bits For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit This feature is enabled by write a one to the USICLK bit while setting an external clock source USICS1 1 Note that even when no wire mode is selected USIWM1 0 0 the external clock input USCK SCL are can still be used by the counter USI Control Register USICR Bit 7 6 5 4 3 2 1 0 USISIE USIOIE USIWM1 USIWMO USICS1 USICSO USICLK USITC USICR Read Write R W R W R W R W R W R W Ww Ww Initial Value 0 0 0 0 0 0 0 0 The Control Register includes interrupt enable control wire mode setting Clock Select setting and clock strobe Bit 7 USISIE Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt If there is a pending inter rupt when the USISIE and the Global Interrupt Enable Flag is set to one this will immediately be executed Refer to the USISIF bit description on page 101 for further details Bit 6 USIOIE Counter Overflow Interrupt Enable Setting this bit to one enables the Counter Overflow interrupt If there is a pending interrupt when the USIOIE and the Global Interrupt Enable Flag is set to one this will immediately be executed Refer to the USIOIF bit description on page 101 for further details Bit 5 4 USIWMf1 0 Wire Mode These bits set the type of wire mode to be used Basicall
168. ial Conversion As default the ADC converter operates in the unipolar input mode but the bipolar input mode can be selected by writting the BIN bit in the ADCSRB to one In the bipolar input mode two sided voltage differences are allowed and thus the voltage on the negative input pin can also be larger than the voltage on the positive input pin If differential channels and a bipolar input mode are used the result is Vpos Vygg 912 ADC VREF GAIN where Vros is the voltage on the positive input pin VNec the voltage on the negative input pin and Vner the selected voltage reference The result is presented in two s complement form from 0x200 512d through 0x000 0d to Ox1FF 511d The GAIN is either 1x or 20x However if the signal is not bipolar by nature 9 bits sign as the 10th bit this scheme loses one bit of the converter dynamic range Then if the user wants to perform the conversion with the maximum dynamic range the user can perform a quick polarity check of the result and use the unipolar differential conversion with selectable differential input pairs see the Input Polarity Reversal mode ie the IPR bit in the ADCSRB register on page 135 When the polarity check is performed it is sufficient to read the MSB of the result ADC9 in ADCH If the bit is one the result is negative and if this bit is zero the result is positive 18 7 4 Temperature Measurement Preliminary description The temperature measureme
169. ine the division factor of the Dead Time prescaler The division factors are given in table 46 Table 15 1 Division factors of the Dead Time prescaler DTPS11 DTPS10 Prescaler divides the T C1 clock by 0 0 1x no division 0 1 2x 1 0 4x 1 1 8x 15 0 2 Timer Counter1 Dead Time A DT1A Bit 7 6 5 4 3 2 1 0 25 45 DT1AH3 DT1AH2 DT1AH1 DT1AHO DT1AL3 DT1AL2 DT1AL1 DT1ALO DT1A Read Write R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 The dead time value register A is an 8 bit read write register The dead time delay of is adjusted by the dead time value register DT1A The register consists of two fields DT1AH3 0 and DT1AL3 0 one for each complementary output Therefore a differ ent dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A Bits 7 4 DT1AH3 DT1AHO Dead Time Value for OC1A Output 92 ATtiny25 45 05 memm 7598G AVR 03 08 The dead time value for the OC1A output The dead time delay is set as a number of the pres caled timer counter clocks The minimum dead time is zero and the maximum dead time is the prescaled time counter clock period multiplied by 15 Bits 3 0 DT1AL3 DT1ALO Dead Time Value for OC1A Output The dead time value for the OC1A output The dead time delay is set as a number of the pres caled timer counter clocks The minimum dead time is zero and the maximum dead time is the prescaled time coun
170. ing Enable instruction needs to be executed first before program erase operations can be executed NOTE in Table 21 8 on page 133 the pin mapping for SPI programming is listed Not all parts use the SPI pins dedicated for the internal SPI interface Figure 21 1 Serial Programming and Verify 44 5 5 5V O MOSI MISO SCK Notes 1 Ifthe device is clocked by the internal Oscillator it is no need to connect a clock source to the CLKI pin Table 21 8 Pin Mapping Serial Programming Symbol Pins y o Description MOSI PBO l Serial Data in MISO PB1 O Serial Data out SCK PB2 l Serial Clock When programming the EEPROM an auto erase cycle is built into the self timed programming operation in the Serial mode ONLY and there is no need to first execute the Chip Erase instruction The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into OxFF Depending on CKSEL Fuses a valid clock must be present The minimum low and high periods for the serial clock SCK input are defined as follows AMEL 133 7598G AVR 03 08 AMEL Low gt 2 CPU clock cycles for fx lt 12 MHz 3 CPU clock cycles for fy gt 12 MHz High gt 2 CPU clock cycles for fy lt 12 MHz 3 CPU clock cycles for fy gt 12 MHz 21 6 1 Serial Programming Algorithm When writing serial data to the ATtiny25 45 85 data is clocked on the rising edge of SCK When reading data from
171. iny25 45 05 memme ATtiny25 45 85 Figure 16 2 Three wire Mode Operation Simplified Diagram om oe es me bom e n md lt H PORTxn Figure 16 2 shows two USI units operating in Three wire mode one as Master and one as Slave The two Shift Registers are interconnected in such way that after eight USCK clocks the data in each register are interchanged The same clock also increments the USI s 4 bit counter The Counter Overflow interrupt Flag or USIOIF can therefore be used to determine when a transfer is completed The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR Figure 16 3 Three wire Mode Timing Diagram CYCLE Reference 1 2 3 4 5 6 7 8 USCK USCK i DO Xs 6 X 8 X 45 X 3 X 2 X 3 OCUS8 X DI 5 4 X 3 X 2 1 X LSB X Ei l The Three wire mode timing is shown in Figure 16 3 At the top of the figure is a USCK cycle ref erence One bit is shifted into the USI Shift Register USIDR for each of these cycles The USCK timing is shown for both external clock modes In External Clock mode 0 USICSO 0 DI is sampled at positive edges and DO is changed Data Register is shifted by one at negative edges External Clock mode 1 USICSO 1 uses the opposite edges versus mode 0 i e sam ples data at negative and chan
172. iod nor clear the CLKPCE bit Bits 6 4 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and will always read as zero Bits 3 0 CLKPS3 0 Clock Prescaler Select Bits 3 0 These bits define the division factor between the selected clock source and the internal system clock These bits can be written run time to vary the clock frequency to suit the application requirements As the divider divides the master clock input to the MCU the speed of all synchro nous peripherals is reduced when a division factor is used The division factors are given in Table 6 13 To avoid unintentional changes of clock frequency a special write procedure must be followed to change the CLKPS bits 1 Write the Clock Prescaler Change Enable CLKPCE bit to one and all other bits in CLKPR to zero 2 Within four cycles write the desired value to CLKPS while writing a zero to CLKPCE Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted The CKDIV8 Fuse determines the initial value of the CLKPS bits If CKDIV8 is unprogrammed the CLKPS bits will be reset to 0000 If CKDIV8 is programmed CLKPS bits are reset to 0011 giving a division factor of eight at start up This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions Note that any value can be written to the CLKPS
173. ion Bit 4 S Sign Bit S N V The S bit is always an exclusive or between the Negative Flag N and the Two s Complement Overflow Flag V See the Instruction Set Description for detailed information Bit 3 V Two s Complement Overflow Flag The Two s Complement Overflow Flag V supports two s complement arithmetics See the Instruction Set Description for detailed information Bit 2 N Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation See the Instruction Set Description for detailed information Bit 1 Z Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation See the Instruction Set Description for detailed information Bit 0 C Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation See the Instruction Set Description for detailed information ATtiny25 45 05 memme 7598G AVR 03 08 4 5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set In order to achieve the required performance and flexibility the following input output schemes are supported by the Register File One 8 bit output operand and one 8 bit result input Two 8 bit output operands and one 8 bit result input Two 8 bit output operands and one 16 bit result input One 16 bit output operand and one 16 bit result input Figure 4 2 shows the structure of the 32 general purpose
174. is is the case the device is tested down to Voc Vgor during the production test This guar antees that a Brown out Reset will occur before Voc drops to a voltage where correct operation of the microcontroller is no longer guaranteed 2 Centered value not tested Table 8 3 Brown out Characteristics Symbol Parameter Min Typ Max Units VnRAM RAM Retention Voltage 50 mV Vuyst Brown out Detector Hysteresis 50 mV top Min Pulse Width on Brown out Reset 2 us Notes 1 This is the limit to which VDD can be lowered without losing RAM data 38 ATtiny25 45 85 A 7598G AVR 03 08 When the BOD is enabled and Vcc decreases to a value below the trigger level Vgor in Figure 8 5 the Brown out Reset is immediately activated When Vec increases above the trigger level Vgor in Figure 8 5 the delay counter starts the MCU after the Time out period trout has expired The BOD circuit will only detect a drop in Voc if the voltage stays below the trigger level for longer than tgop given in Table 8 1 Figure 8 5 Brown out Reset During Operation n I I i 1 TIME OUT trour 7 l l l l 1 1 INTERNAL RESET 8 0 6 Watchdog Reset When the Watchdog times out it will generate a short reset pulse of one CK cycle duration On the falling edge of this pulse the delay timer starts counting the Time out period tour Refer to page 41 for details on operation of the Watchdog Timer Figure 8 6 Watchdog Reset During Operation Voc
175. is mode are SCL and SDA Figure 16 4 Two wire Mode Operation Simplified Diagram wo wire Clock Control Unit Figure 16 4 shows two USI units operating in Two wire mode one as Master and one as Slave It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used The main differences between the Master and Slave operation at this level is the serial clock generation which is always done by the Master and only the Slave uses the clock control unit Clock generation must be implemented in software but the shift operation is done automatically by both devices Note that only clocking on negative edge for shifting data is of practical use in this mode The slave can insert wait states at start or end of transfer by forcing the SCL clock low This means that the Master must always check if the SCL line was actually released after it has generated a positive edge Since the clock also increments the counter a counter overflow can be used to indicate that the transfer is completed The clock is generated by the master by toggling the USCK pin via the PORT Register The data direction is not given by the physical layer A protocol like the one used by the TWI bus must be implemented to control the data flow ATtiny25 45 85 memme 7598G AVR 03 08 Figure 16 5 Two wire Mode Typical Timing Diagram SDA X
176. le mode Depending of the protocol used the slave device can now set its out put to high impedance 16 2 2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master SPITransfer sts USIDR r16 ldi r16 1 lt lt USIOIF sts USISR r16 ldi r16 1 lt lt USIWMO 1 lt lt USICS1 1 lt lt USICLK 1 lt lt USITC SPITransfer loop sts USICR r16 lds ri6 USISR sbrs ri6 USIOIF rjmp SPITransfer loop lds r16 USIDR The code is size optimized using only eight instructions ret The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register The value stored in register r16 prior to the function is called is transferred to the Slave device and when the transfer is com pleted the data received from the Slave is stored back into the r16 Register The second and third instructions clears the USI Counter Overflow Flag and the USI counter value The fourth and fifth instruction set Three wire mode positive edge Shift Register clock count at USITC strobe and toggle USCK The loop is repeated 16 times The following code demonstrates how to use the USI module as a SPI Master with maximum speed fsck fck 4 SPITransfer Fast sts USIDR r16 ldi r16 1 lt lt USIWMO 0 USICSO 1 USITC ldi r17 1 lt lt USIWMO 0 lt lt USICS0 1 lt lt USITC 1 lt lt USICLK sts USICR r16 MSB sts USICR r17 96 ATtiny25 45 05 memme
177. lock cycle an ALU operation using two register operands is executed and the result is stored back to the destina tion register Figure 4 5 Single Cycle ALU Operation T1 T2 T3 T4 dins AA AAA AAA XL CPU 1 I I Total Execution Time 1 9 4 Register Operands Fetch i 3 4 I I I I ALU Operation Execute lt _ gt ras Result Write Back lt D e e I I I 4 8 Reset and Interrupt Handling The AVR provides several different interrupt sources These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors The complete list of vectors is shown in Interrupts on page 45 The list also determines the priority levels of the different interrupts The lower the address the higher is the priority level RESET has the highest priority and next is INTO the External Interrupt Request 0 When an interrupt occurs the Global Interrupt Enable I bit is cleared and all interrupts are dis abled The user software can write logic one to the I
178. lock is halted in all sleep modes except Idle mode Note that if a level triggered interrupt is used for wake up from Power down the required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt If the level disappears before the end of the Start up Time the MCU will still wake up but no inter rupt will be generated The start up time is defined by the SUT and CKSEL Fuses as described in System Clock and Clock Options on page 21 MCU Control Register MCUCR The External Interrupt Control Register A contains control bits for interrupt sense control Bit 7 6 5 4 3 2 1 0 Bops Puo se sm smo BODSE iscor ico mcucr Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 e Bits 1 0 ISC01 ISCOO Interrupt Sense Control 0 Bit 1 and Bit 0 ATtiny25 45 05 memme 7598G AVR 03 08 The External Interrupt 0 is activated by the external pin INTO if the SREG I flag and the corre sponding interrupt mask are set The level and edges on the external INTO pin that activate the interrupt are defined in Table 11 1 The value on the INTO pin is sampled before detecting edges If edge or toggle interrupt is selected pulses that last longer than one clock period will generate an interrupt Shorter pulses are not guaranteed to generate an interrupt If low level interrupt is selected the low level must be held until the completion of the currently executing instruction to ge
179. ls eruere eaim h kann anna ax pax an aan ku 79 14 1 Timer GOUnler 2 nte eee rechnen teet r E ex eee s 79 15 Dead Time Generator uiiiouseieci inva nee pe eor kx kn Se suuo dun Eo Re adnd Nara EEEEEEEE 90 16 Universal Serial Interface USI eere 93 I mE9 73 93 16 2 Functional Descriptioris 2 ubere e e eee eee ph eee dee be aa en 94 7598F AVR 08 07 16 3 Alternative US Usage sssssssssseesesseeseeee nennen enne nennen nennen 100 16 4 USI Register Descriptions sssssssssseseeneeeeeneenneeennenennnenni 100 17 Analog Eeu rin d 104 17 1 Analog Comparator Multiplexed Input ssesssseeen 106 18 Analog to Digital Converter eeeeeeeeee eere eese e eiie n erra nnn 107 18 1 Features L 107 1 59pm 108 18 3 Starting a Conversion ssssssssssssessseseeeeeee eene enne entente 109 18 4 Prescaling and Conversion Timing ssssssseseeeeenenen 110 18 5 Changing Channel or Reference Selection ssssssssseee 113 18 6 ADC Noise Canceler ssssssssssssseseesseee eene enmt terere nnne 114 19 7 ADG Conversion Result 1 re cte eee reti eere tn a edo dS 117 19 debugWIRE On chip Debug System cceeeneeeeee 123 IX Ius c EE 123 19 2 OVGIVIOW ae aere tot et a eiae bc ee Fea cu eds 123 19 3
180. ly reduce the overall power consumption In all other sleep modes the clock is already stopped Bit 7 6 5 4 3 2 1 0 C eam PRTG PRUSI PRADC PRR Read Write R R R R R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 7 6 5 4 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and will always read as zero Bit 3 PRTIM1 Power Reduction Timer Counter1 Writing a logic one to this bit shuts down the Timer Counter1 module When the Timer Counter1 is enabled operation will continue like before the shutdown Bit 2 PRTIMO Power Reduction Timer CounterO AMEL 33 AMEL Writing a logic one to this bit shuts down the Timer CounterO module When the Timer CounterO is enabled operation will continue like before the shutdown Bit 1 PRUSI Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module When waking up the USI again the USI should be re initialized to ensure proper operation Bit 0 PRADC Power Reduction ADC Writing a logic one to this bit shuts down the ADC The ADC must be disabled before shut down The analog comparator cannot use the ADC input MUX when the ADC is shut down 7 6 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system In general sleep modes should be used as much as possible and the sleep mode should be selected so that as few as possi
181. m clock cycles from when the timer is enabled to the first count occurs can be from 1 to N 1 system clock cycles where N equals the prescaler divisor 8 64 256 or 1024 It is possible to use the Prescaler Reset for synchronizing the Timer Counter to program execution 13 0 2 External Clock Source An external clock source applied to the TO pin can be used as Timer Counter clock clky The TO pin is sampled once every system clock cycle by the pin synchronization logic The synchro nized sampled signal is then passed through the edge detector Figure 13 1 shows a functional equivalent block diagram of the TO synchronization and edge detector logic The registers are clocked at the positive edge of the internal system clock clkyo The latch is transparent in the high period of the internal system clock AMEL 77 7598G AVR 03 08 AMEL The edge detector generates one clk pulse for each positive CSn2 0 7 or negative CSn2 0 6 edge it detects Figure 13 1 TO Pin Sampling T D a PS f Be Select Logic vO P Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2 5 to 3 5 system clock cycles from an edge has been applied to the TO pin to the counter is updated Enabling and disabling of the clock input must be done when TO has been stable for at least one system clock cycle otherwise it is a risk that a false Timer
182. n A transparent latch is inserted between the Serial Register Output and output pin which delays the change of data output to the opposite clock edge of the data input sampling The serial input is always sampled from the Data Input DI pin independent of the configuration The 4 bit counter can be both read and written via the data bus and can generate an overflow interrupt Both the Serial Register and the counter are clocked simultaneously by the same clock source This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete Note that when an external clock source is selected the counter counts both clock edges In this case the counter counts the number of edges and not the number of bits The clock can be selected from three different sources The USCK pin Timer CounterO Compare Match or from software The Two wire clock control unit can generate an interrupt when a start condition is detected on the Two wire bus It can also generate wait states by holding the clock pin low after a start con dition is detected or after the counter overflows 16 2 Functional Descriptions 16 2 1 Three wire Mode The USI Three wire mode is compliant to the Serial Peripheral Interface SPI mode 0 and 1 but does not have the slave select SS pin functionality However this feature can be implemented in software if necessary Pin names used by this mode are DI DO and USCK 94 ATt
183. n Complete interrupt routine If another interrupt wakes up the CPU before the ADC conversion is com plete that interrupt will be executed and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes The CPU will remain in active mode until a new sleep command is executed Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode The user is advised to write zero to ADEN before enter ing such sleep modes to avoid excessive power consumption Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 18 8 An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin regard less of whether that channel is selected as input for the ADC When the channel is selected the source must drive the S H capacitor through the series resistance combined resistance in the input path The ADC is optimized for analog signals with an output impedance of approximately 10 kQ or less If such a source is used the sampling time will be negligible If a source with higher imped ance is used the sampling time will depend on how long time the source needs to charge the S H capacitor with can vary widely The user is recommended to only use low impedant sources with slowly varying signals since this minimizes the required charge transfer to the S H capacitor Signal
184. n Timer Counter occurs i e when the OCFOA bit is set in the Timer Counter Interrupt Flag Register TIFRO Bit 3 OCIEOB Timer Counter Output Compare Match B Interrupt Enable When the OCIEOB bit is written to one and the I bit in the Status Register is set the Timer Counter Compare Match B interrupt is enabled The corresponding interrupt is executed if a Compare Match in Timer Counter occurs i e when the OCFOB bit is set in the Timer Counte Interrupt Flag Register TIFRO Bit 2 TOIE1 Timer Counter1 Overflow Interrupt Enable When the TOIE1 bit is set one and the I bit in the Status Register is set one the Timer Counter1 Overflow interrupt is enabled The corresponding interrupt at vector 004 is executed if an overflow in Timer Counter1 occurs The Overflow Flag Timer1 is set one in the Timer Counter Interrupt Flag Register TIFR Bit 0 Res Reserved Bit This bit is a reserved bit in the ATtiny25 45 85 and always reads as zero 14 1 8 Timer Counter Interrupt Flag Register TIFR Bit 7 6 5 4 3 2 1 0 38 58 OCFiA OCFiB OCFOA OCFOB TOVi TOVO TIFR Read Write R R W R W R R R W R W R Initial value 0 0 0 0 0 0 0 0 Bit 7 Res Reserved Bit This bit is a reserved bit in the ATtiny25 45 85 and always reads as zero Bit 6 OCF1A Output Compare Flag 1A The OCF1A bit is set one when compare match occurs between Timer Counter1 and the data value in OCR1A Output Compare Register
185. n and to clear it immediately after waking up e Bits 4 3 SM1 0 Sleep Mode Select Bits 2 0 These bits select between the three available sleep modes as shown in Table 7 1 Table 7 1 Sleep Mode Select SM1 SMO Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power down 1 1 Stand by mode e Bit2 BODSE BOD Sleep Enable BOD disable functionality is available in some devices only See Limitations on page 33 AMEL 7598G AVR 03 08 7 1 7 2 7 3 32 Idle Mode AMEL The BODSE bit enables setting of BODS control bit as explained on BODS bit description BOD disable is controlled by a timed sequence This bit is unused in devices where software BOD disable has not been implemented and will read as zero in those devices When the SM1 0 bits are written to 00 the SLEEP instruction makes the MCU enter Idle mode stopping the CPU but allowing Analog Comparator ADC Timer Counter Watchdog and the interrupt system to continue operating This sleep mode basically halts clkgpy and clk As while allowing the other clocks to run Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow If wake up from the Analog Comparator interrupt is not required the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register ACSR This will reduce power consumption in Idle mode
186. n ennemi nnne nennen nnns 24 6 4 Crystal Oscillator i eren eene Ur ra Ense epa baee ERE be PATRE ERE I NaNe 24 6 5 Low frequency Crystal Oscillator sessssneeeneenenennnnns 25 6 6 Calibrated Internal RC Oscillator sseeeneeneenneennnnns 26 6 7 External CloCK Gu M 27 6 8 128 kHz Internal Oscillator sssssseeeeeeeneneeeneeneeen nennen 28 6 9 Clock Output Butter 1 2 2 iiec aeq decori ote iae Us e E daa e i suc dca 28 6 10 System Clock Prescaler ssesssssssssssseseeeeeeeeee enne nennen enn nenne nnns 29 7 Power Management and Sleep Modes e ceeseeeee 30 reu r 32 7598F AVR 08 07 AMEL 7 2 ADC Noise Reduction Mode sse nnne nnne nnns 32 7 9 Power down Mode reete eite ceret ee rnie dt E pe daB Ee oe iBB Ce dap asap dul 32 T A Limitatlofis i crt tmr DR MR ERES TORRE seat anes Fas ke ERR ee ER NR n ash EERERR AR RR aeaa 33 7 5 Power Reduction Register cceesseccceeeeeeeceeeeeseeeeeeseseaeeeeeseseeeeesenseeneeeneeseneaes 33 7 6 Minimizing Power Consumption sesssssseeeeeeeeeeenenennenen nennen nnns 34 8 System Control and Reset ceeeeee esee essen nena nana nina 35 8 1 Internal Voltage Reference ssssssssssssssseeeeeeeeeenn rennen 40 8 2 Watchdog TIIer s iei e er ere Enea nee
187. n internal bandgap reference This reference is used for Brown out Detection and it can be used as an input to the Analog Comparator or the ADC Voltage Reference Enable Signals and Start up Time The voltage reference has a start up time that may influence the way it should be used The start up time is given in Table 8 4 To save power the reference is not always turned on The reference is on during the following situations 1 When the BOD is enabled by programming the BODLEVEL 2 0 Fuse bits 2 When the bandgap reference is connected to the Analog Comparator by setting the ACBG bit in ACSR 3 When the ADC is enabled Thus when the BOD is not enabled after setting the ACBG bit or enabling the ADC the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used To reduce power consumption in Power down mode the user can avoid the three conditions above to ensure that the reference is turned off before entering Power down mode Table 8 4 Internal Voltage Reference Characteristics Symbol Parameter Condition Min Typ Max Units Vec 1 1V 2 7V VBG Bandgap reference voltage T 25 C 1 0 1 1 1 2 V AT Vec 2 7V tec Bandgap reference start up time T 25 C 40 70 us Bandgap reference current Voc 2 7V 15 A BG consumption Ty 25 C H ATtiny25 45 85 memme 7598G AVR 03 08 8 2 8 2 1 7598G AVR 03 08 Watchdog Timer
188. n out Detector trigger level 1 unprogrammed BODLEVEL1 1 Brown out Detector trigger level 1 unprogrammed BODLEVELO 0 Brown out Detector trigger level 1 unprogrammed Notes 1 See Alternate Functions of Port B on page 54 for description of RSTDISBL and DWEN Fuses oar wo DWEN must be unprogrammed when Lock Bit security is required Program And Data Mem ory Lock Bits on page 129 The SPIEN Fuse is not accessible in SPI Programming mode See Watchdog Timer Control Register WDTCR on page 41 for details See Table 8 2 on page 38 for BODLEVEL Fuse decoding When programming the RSTDISBL Fuse High voltage Serial programming has to be used to change fuses to perform further programming Table 21 5 Fuse Low Byte Fuse Low Byte Bit No Description Default Value CKDIV8 7 Divide clock by 8 0 unprogrammed CKOUT 6 Clock Output Enable 1 unprogrammed SUT1 5 Select start up time 1 unprogrammed SUTO 4 Select start up time 0 programmed CKSEL3 3 Select Clock source 0 programmed CKSEL2 2 Select Clock source 0 programmed CKSEL1 1 Select Clock source 1 unprogrammed CKSELO 0 Select Clock source 0 programmed Notes 1 See System Clock Prescaler on page 29 for details 2 The CKOUT Fuse allows the system clock to be output on PORTBA See Clock Output Buffer on page 30 for details 3 The default value of SUT1 0 results in maximum start up
189. nal RC Oscillator 8 0 MHz 0010 Watchdog Oscillator 128 kHz 0100 External Low frequency Crystal 0110 External Crystal Ceramic Resonator 1000 1111 Reserved 0101 0111 0011 Note 1 For all fuses 1 means unprogrammed while 0 means programmed The various choices for each clocking option is given in the following sections When the CPU wakes up from Power down or Power save the selected clock source is used to time the start up ensuring stable Oscillator operation before instruction execution starts When the CPU starts from reset there is an additional delay allowing the power to reach a stable level before com mencing normal operation The Watchdog Oscillator is used for timing this real time part of the start up time The number of WDT Oscillator cycles used for each time out is shown in Table 6 2 AMEL 23 7598G AVR 03 08 AMEL Table 6 2 Number of Watchdog Oscillator Cycles Typ Time out Number of Cycles 4 ms 512 64 ms 8K 8 192 6 3 Default Clock Source The device is shipped with CKSEL 0010 SUT 10 and CKDIV8 programmed The default clock source setting is therefore the Internal RC Oscillator running at 8 MHz with longest start up time and an initial system clock prescaling of 8 This default setting ensures that all users can make their desired clock source setting using an In System or High voltage Programmer 6 4 Crystal Oscillator XTAL1 and XTAL2 are input and output
190. nalog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS 2 0 8 BIT DATA BUS uj w EE 15 0 ADC CTRL amp STATUS B ADC MULTIPLEXER ADC CTRL amp STATUS A ADC DATA REGISTER REGISTER ADCSRB SELECT ADMUX REGISTER ADCSRA ADCHIADCL al cl ol tm A ui BIN S55 a PR S 3 3 lt TRIGGER SELECT yv y MUX DECODER V I 4 PRESCALER Y CONVERSION LOGIC TEMPERATURE SAMPLE amp HOLD SENSOR COMPARATOR 10 BIT DAC ADC4 ADC3 SINGLE ENDED DIFFERENTIAL SELECTION ADC2 INPUT MUX ADC1 ADO GAIN ADC MULTIPLEXER AMPLIFIER OUTPUT NEG INPUT MUX The ADC converts an analog input voltage to a 10 bit digital value through successive approxi mation The minimum value represents GND and the maximum value represents the voltage on Voc the voltage on the AREF pin or an internal 1 1V 2 56V voltage reference The voltage reference for the ADC may be selected by writing to the REFS2 0 bits in ADMUX The VCC supply the AREF pin or an internal 1 1V 2 56V voltage reference may be selected as the ADC voltage reference Optionally the internal 1 1V 2 56V voltage reference may be decou pled by an external capacitor at the AREF pin to improve noise immunity ADEN ADSC ADATI ADIF ADPS2 ADPS ADPSO ADC 9 0 REFS2 0 INTERNAL 1 1V 2 56V REFERENCE CHANNEL SELECTION GAIN SELECTION
191. nd Veormax to ensure Reset 8 0 4 External Reset An External Reset is generated by a low level on the RESET pin if enabled Reset pulses longer than the minimum pulse width see Table 8 1 will generate a reset even if the clock is not run ning Shorter pulses are not guaranteed to generate a reset When the applied signal reaches the Reset Threshold Voltage Vna on its positive edge the delay counter starts the MCU after the Time out period trout has expired AMEL s 7598G AVR 03 08 ATMEL Figure 8 4 External Reset During Operation Vcc RESET i 7 X Vest f i r trout TIME OUT i i INTERNAL A o nn o RESET 8 0 5 Brown out Detection ATtiny25 45 85 has an On chip Brown out Detection BOD circuit for monitoring the Vgc level during operation by comparing it to a fixed trigger level The trigger level for the BOD can be selected by the BODLEVEL Fuses The trigger level has a hysteresis to ensure spike free Brown out Detection The hysteresis on the detection level should be interpreted as Vao7 Vpot Vuysr 2 and Vgor Vgor Vuysr 2 Table 8 2 BODLEVEL Fuse Coding BODLEVEL 2 0 Fuses Min Vgot Typ Vaor Max Vgot Units 111 BOD Disabled 110 1 7 1 8 2 0 101 2 5 2 7 2 9 100 4 0 4 3 4 6 011 2 300 V 010 2 200 001 1 92 000 2 000 Note 1 Vgo7 may be below nominal minimum operating voltage for some devices For devices where th
192. nerate an interrupt Table 11 1 Interrupt 0 Sense Control ISCO1 ISCOO Description 0 0 The low level of INTO generates an interrupt request 0 1 Any logical change on INTO generates an interrupt request 1 0 The falling edge of INTO generates an interrupt request 1 1 The rising edge of INTO generates an interrupt request 11 0 2 General Interrupt Mask Register GIMSK Bit 7 6 5 4 3 2 1 0 LN TET N ems Read Write R R W R W R R R R R Initial Value 0 0 0 0 0 0 0 0 Bits 7 4 0 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and will always read as zero Bit 6 INTO External Interrupt Request 0 Enable When the INTO bit is set one and the I bit in the Status Register SREG is set one the exter nal pin interrupt is enabled The Interrupt Sense Controlo bits 1 0 ISCO1 and ISCOO in the MCU Control Register MCUCR define whether the external interrupt is activated on rising and or fall ing edge of the INTO pin or level sensed Activity on the pin will cause an interrupt request even if INTO is configured as an output The corresponding interrupt of External Interrupt Request 0 is executed from the INTO Interrupt Vector e Bit 5 PCIE Pin Change Interrupt Enable When the PCIE bit is set one and the I bit in the Status Register SREG is set one pin change interrupt is enabled Any change on any enabled PCINT5 0 pin will cause an interrupt The corresponding interrupt o
193. nfigured without the risk of advanc ing during configuration When the TSM bit is written to zero the PSRO bit is cleared by hardware and the Timer Counter start counting Bit 0 PSRO Prescaler Reset Timer CounterO When this bit is one the Timer CounterO prescaler will be Reset This bit is normally cleared immediately by hardware except if the TSM bit is set 14 Counter and Compare Units Figure 14 1 shows the Timer Counter1 prescaler that supports two clocking modes a synchro nous clocking mode and an asynchronous clocking mode The synchronous clocking mode uses the system clock CK as the clock timebase and asynchronous mode uses the fast peripheral clock PCK as the clock time base The PCKE bit from the PLLCSR register enables the asyn chronous mode when it is set 1 Figure 14 1 Timer Counter1 Prescaler PCKE PSR1 ERE T1CK 14 BIT T C PRESCALER PCK 64 32 MHz T1CK 128 T1CK 1024 T1CK 2048 T1CK 4096 T1CK 8192 T1CK 16384 T1CK 256 T1CK 512 T1CK 16 T1CK 32 T1CK 64 TIMER COUNTER1 COUNT ENABLE In the asynchronous clocking mode the clock selections are from PCK to PCK 16384 and stop and in the synchronous clocking mode the clock selections are from CK to CK 16384 and stop The clock options are described in Table 14 2 on page 82 and the Timer Counter1 Control Reg ister TCCR1 Setting the PSR1 bit in GTCCR register resets the prescaler The PCKE bit in the
194. nificantly higher transfer rates and uses less code space than solutions based on software only Interrupts are included to minimize the processor load The main features of the USI are Two wire Synchronous Data Transfer Master or Slave fscLmax fcx 16 Three wire Synchronous Data Transfer Master or Slave fsckmax fex 4 Data Received Interrupt Wakeup from Idle Mode In Two wire Mode Wake up from All Sleep Modes Including Power down Mode Two wire Start Condition Detector with Interrupt Capability A simplified block diagram of the USI is shown on Figure 16 1 For the actual placement of I O pins refer to Pinout ATtiny25 45 85 on page 2 CPU accessible I O Registers including I O AMEL s AMEL bits and I O pins are shown in bold The device specific I O Register and bit locations are listed in the USI Register Descriptions on page 100 Figure 16 1 Universal Serial Interface Block Diagram Q Output only ry s HLE DI SDA Input Open Drain e TIMO COMP USCK ScL Input Open Drain Two wire Clock Control Unit DATA BUS The 8 bit Shift Register is directly accessible via the data bus and contains the incoming and outgoing data The register has no buffering so the data must be read as quickly as possible to ensure that no data is lost The most significant bit is connected to one of two output pins depending of the wire mode configuratio
195. nput must always be larger than the voltage on the negative input Otherwise the result is saturated to the voltage reference In the bipolar mode two sided conversions are supported and the result is represented in the two s complement form In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits 1 sign bit Bit 5 IPR Input Polarity Mode The Input Polarity mode allows software selectable differential input pairs and full 10 bit ADC resolution in the unipolar input mode assuming a pre determined input polarity If the input polarity is not known it is actually possible to determine the polarity first by using the bipolar input mode with 9 bit resolution 1 sign bit ADC measurement And once determined set or clear the polarity reversal bit as needed for a succeeding 10 bit unipolar measurement e Bits 4 3 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and will always read as zero e Bits 2 0 ADTS2 0 ADC Auto Trigger Source If ADATE in ADCSRA is written to one the value of these bits selects which source will trigger an ADC conversion If ADATE is cleared the ADTS2 0 settings will have no effect A conversion will be triggered by the rising edge of the selected Interrupt Flag Note that switching from a trig ger source that is cleared to a trigger source that is set will generate a positive edge on the 122 ATtiny25 45 85 memme trigger signal If ADEN in ADCSR
196. nt is based on an on chip temperature sensor that is coupled to a single ended ADC4 channel Selecting the ADC4 channel by writing the MUX3 0 bits in ADMUX register to 1111 enables the temperature sensor The internal 1 1V voltage reference must also be selected for the ADC voltage reference source in the temperature sensor measurement When the temperature sensor is enabled the ADC converter can be used in single conversion mode to measure the voltage over the temperature sensor The measured voltage has a linear relationship to the temperature as described in Table 51 The voltage sensitivity is approximately 1 mV C and the accuracy of the temperature measurement is 10 C after bandgap calibration Table 18 2 Temperature vs Sensor Output Voltage Typical Case Voltage mV 242 mV 314 mv 403 mV The values described in Table 51 are typical values However due to the process variation the temperature sensor output voltage varies from one chip to another To be capable of achieving more accurate results the temperature measurement can be calibrated in the application soft ware The software calibration requires that a calibration value is measured and stored in a register or EEPROM for each chip as a part of the production test The sofware calibration can be done utilizing the formula ns ATtiny25 45 65 su Temperature k VrpyptTos where V zyp is the ADC reading of the temperature sensor signal k is a fixed coefficient
197. nversion to complete and then change the channel selection Since the next conversion has already started automatically the next result will reflect the previous channel selection Subsequent conversions will reflect the new channel selection 18 5 2 ADC Voltage Reference The voltage reference for the ADC Vggr indicates the conversion range for the ADC Single ended channels that exceed Vg will result in codes close to Ox3FF Vae can be selected as ATMEL 113 7598G AVR 03 08 AMEL either Vcc or internal 1 1V 2 56V voltage reference or external AREF pin The first ADC con version result after switching voltage reference source may be inaccurate and the user is advised to discard this result 18 6 ADC Noise Canceler 18 6 1 114 The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I O peripherals The noise canceler can be used with ADC Noise Reduction and Idle mode To make use of this feature the following procedure should be used a Make sure that the ADC is enabled and is not busy converting Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled b Enter ADC Noise Reduction mode or Idle mode The ADC will start a conversion once the CPU has been halted c If no other interrupts occur before the ADC conversion completes the ADC inter rupt will wake up the CPU and execute the ADC Conversio
198. ny25 45 85 features an EEPROM Memory for data storage All three memory spaces are lin ear and regular In System Re programmable Flash Program Memory The ATtiny25 45 85 contains 2 4 8K byte On chip In System Reprogrammable Flash memory for program storage Since all AVR instructions are 16 or 32 bits wide the Flash is organized as 1024 2048 4096 x 16 The Flash memory has an endurance of at least 10 000 write erase cycles The ATtiny25 45 85 Program Counter PC is 10 11 12 bits wide thus addressing the 1024 2048 4096 Program memory locations Memory Programming on page 129 contains a detailed description on Flash data serial downloading using the SPI pins Constant tables can be allocated within the entire Program memory address space see the LPM Load Program memory instruction description Timing diagrams for instruction fetch and execution are presented in Instruction Execution Tim ing on page 10 Figure 5 1 Program Memory Map Program Memory 0x0000 Ox03FF 0x07FF AMEL 13 5 2 5 2 1 14 AMEL SRAM Data Memory Figure 5 2 shows how the ATtiny25 45 85 SRAM Memory is organized The lower 224 352 607 Data memory locations address both the Register File the I O memory and the internal data SRAM The first 32 locations address the Register File the next 64 loca tions the standard I O memory and the last 128 256 512 locations address the internal data SRAM The five different addressing modes for the
199. o the total current consumption Refer to Brown out Detection on page 38 for details on how to configure the Brown out Detector 7 6 4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown out Detection the Analog Comparator or the ADC If these modules are disabled as described in the sections above the internal voltage reference will be disabled and it will not be consuming power When turned on again the user must allow the reference to start up before the output is used If the reference is kept on in sleep mode the output can be used immediately Refer to Internal Volt age Reference on page 40 for details on the start up time 13 ATtiny25 45 5 uuu 7 6 5 Watchdog Timer 7 6 6 Port Pins If the Watchdog Timer is not needed in the application this module should be turned off If the Watchdog Timer is enabled it will be enabled in all sleep modes and hence always consume power In the deeper sleep modes this will contribute significantly to the total current consump tion Refer to Watchdog Timer on page 41 for details on how to configure the Watchdog Timer When entering a sleep mode all port pins should be configured to use minimum power The most important thing is then to ensure that no pins drive resistive loads In sleep modes where both the I O clock clkyg and the ADC clock clkapc are stopped the input buffers of the device will be disabled This ensures that no power is
200. oltage Serial Programming Characteristics Ta 25 C 10 Vcc 5 0V 10 Unless otherwise noted Symbol Parameter Min Typ Max Units tSHSL SCI PB3 Pulse Width High 125 ns tSLSH SCI PB3 Pulse Width Low 125 ns tIVSH SDI PBO SII PB1 Valid to SCI PB3 High 50 ns ane Wiis SII PB1 Hold after SCI PB3 En tSHOV SCI PB3 High to SDO PB2 Valid 16 ns tWLWH PFB Wait after Instr 3 for Write Fuse Bits 2 5 ms Table 21 14 Pin Values Used to Enter Programming Mode Pin Symbol Value SDI Prog enable 0 0 SII Prog enable 1 0 SDO Prog enable 2 0 21 8 High voltage Serial Programming Algorithm Sequence To program and verify the ATtiny25 45 85 in the High voltage Serial Programming mode the fol lowing sequence is recommended See instruction formats in Table 21 16 21 8 1 Enter High voltage Serial Programming Mode The following algorithm puts the device in High voltage Serial Programming mode PON gt Apply 4 5 5 5V between Veco and GND Set RESET pin to 0 and toggle SCI at least six times Set the Prog enable pins listed in Table 21 14 to 000 and wait at least 100 ns Apply Vivrast 5 5V to RESET Keep the Prog enable pins unchanged for at least tuvrast after the High voltage has been applied to ensure the Prog enable signature has been latched 5 Shortly after latching the Prog enable signature the device will activly output data on the Prog
201. onizer This is the Analog Input Output to from alternate functions The signal is connected directly to the pad and can be used bi directionally Analog Alo Input Output The following subsections shortly describe the alternate functions for each port and relate the overriding signals to the alternate function Refer to the alternate function description for further details 10 3 1 MCU Control Register MCUCR Bit 6 5 4 3 2 1 0 7 sons T Tub T SE suo sobsE cor isco wcucn AMEL s 7598G AVR 03 08 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 6 PUD Pull up Disable When this bit is written to one the pull ups in the I O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull ups DDxn PORTxn 0b01 See Con figuring the Pin on page 48 for more details about this feature 10 3 2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10 3 Table 10 3 Port B Pins Alternate Functions Port Pin Alternate Function PB5 RESET dW ADCO PCINTS PB4 XTAL2 CLKO ADC2 OC1B PCINT4 PB3 XTAL1 ADC3 OC1B PCINT3 PB2 SCK ADC1 TO USCK SCL INTO PCINT2 PB1 MISO AIN1 OCOB OC1A DO PCINT10 PBO MOSI AINO OCOA OC1A DI SDA AREF PCINTO Notes 1 Reset Pin debugWIRE I O ADC Input Channel or Pin Change Inter
202. own counting In inverting Output Compare mode the operation is inverted The dual slope operation has lower maximum operation frequency than single slope operation However due to the sym metric feature of the dual slope PWM modes these modes are preferred for motor control applications In phase correct PWM mode the counter is incremented until the counter value matches TOP When the counter reaches TOP it changes the count direction The TCNTO value will be equal to TOP for one timer clock cycle The timing diagram for the phase correct PWM mode is shown on Figure 12 7 The TCNTO value is in the timing diagram shown as a histogram for illustrating the dual slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNTO slopes represent Compare Matches between OCROx and TCNTO 68 ATtiny25 45 05 memme ATtiny25 45 85 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set Figure 12 7 Phase Correct PWM Mode Timing Diagram TCNTn OCn COMnx1 0 2 OCn COMnx1 0 3 The Timer Counter Overflow Flag TOVO is set each time the counter reaches BOTTOM The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value In phase correct PWM mode the compare unit allows generation of PWM waveforms on the OCOx pins Setting the COMOx1 0 bits to two will produce a non inverted PWM An inverted PWM output can be gene
203. page 128 for details Bit 2 PGWRT Page Write If this bit is written to one at the same time as SPMEN the next SPM instruction within four clock cycles executes Page Write with the data stored in the temporary buffer The page address is taken from the high part of the Z pointer The data in R1 and RO are ignored The PGWRT bit AMEL 127 7598G AVR 03 08 AMEL will auto clear upon completion of a Page Write or if no SPM instruction is executed within four clock cycles The CPU is halted during the entire Page Write operation Bit 1 PGERS Page Erase If this bit is written to one at the same time as SPMEN the next SPM instruction within four clock cycles executes Page Erase The page address is taken from the high part of the Z pointer The data in R1 and RO are ignored The PGERS bit will auto clear upon completion of a Page Erase or if no SPM instruction is executed within four clock cycles The CPU is halted during the entire Page Write operation Bit 0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles If written to one together with either CTPB RFLB PGWRT or PGERS the following SPM instruction will have a special meaning see description above If only SPMEN is written the following SPM instruction will store the value in R1 RO in the temporary page buffer addressed by the Z pointer The LSB of the Z pointer is ignored The SPMEN bit will auto clear upon com
204. pletion of an SPM instruction or if no SPM instruction is executed within four clock cycles During Page Erase and Page Write the SPMEN bit remains high until the operation is completed Writing any other combination than 10001 01001 00101 00011 or 00001 in the lower five bits will have no effect 20 1 2 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation It is recommended that the user checks the status bit EEWE in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register 20 1 3 Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software To read the Lock bits load the Z pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR When an LPM instruction is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR the value of the Lock bits will be loaded in the destination register The RFLB and SPMEN bits will auto clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles When RFLB and SPMEN are cleared LPM will work as described in the Instruction set Manual Bit 7 6 5 4 3 2 1 0 Rd gt a Tue The algorithm for reading the Fu
205. pling and updating the ADC Data Register The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag ADIF is cleared or not If Auto Triggering is enabled single conversions can be started by writing ADSC in ADCSRA to one ADSC can also be used to determine if a conversion is in progress The ADSC bit will be read as one during a conversion independently of how the conversion was started 18 4 Prescaling and Conversion Timing Figure 18 3 ADC Prescaler ADEN START Reset 7 BIT ADC PRESCALER ADPSO ADPS1 ADPS2 ADC CLOCK SOURCE By default the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution If a lower resolution than 10 bits is needed the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate It is not recommended to use a higher input clock frequency than 1 MHz o ATtiny25 45 05 mememe 7598G AVR 03 08 The ADC module contains a prescaler which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz The prescaling is set by the ADPS bits in ADCSRA The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA The prescaler keeps running for as long as the ADEN bit is set and is continuously reset when ADEN i
206. ply overruns when it passes its maximum 8 bit value TOP OxFF and then restarts from the bot tom 0x00 In normal operation the Timer Counter Overflow Flag TOVO will be set in the same timer clock cycle as the TCNTO becomes zero The TOVO Flag in this case behaves like a ninth bit except that it is only set not cleared However combined with the timer overflow interrupt that automatically clears the TOVO Flag the timer resolution can be increased by software There are no special cases to consider in the Normal mode a new counter value can be written anytime The Output Compare Unit can be used to generate interrupts at some given time Using the Out put Compare to generate waveforms in Normal mode is not recommended since this will occupy too much of the CPU time Clear Timer on Compare Match CTC Mode In Clear Timer on Compare or CTC mode WGMO02 0 2 the OCROA Register is used to manipulate the counter resolution In CTC mode the counter is cleared to zero when the counter value TCNTO matches the OCROA The OCROA defines the top value for the counter hence also its resolution This mode allows greater control of the Compare Match output frequency It also simplifies the operation of counting external events The timing diagram for the CTC mode is shown in Figure 12 5 The counter value TCNTO increases until a Compare Match occurs between TCNTO and OCROA and then counter TCNTO is cleared Figure 12 5 CTC Mode Timing
207. pt Vector posi tion The lower the Interrupt Vector address the higher the priority The I O memory space contains 64 addresses for CPU peripheral functions as Control Regis ters SPI and other I O functions The I O memory can be accessed directly or as the Data Space locations following those of the Register File 0x20 Ox5F 4 3 ALU Arithmetic Logic Unit The high performance AVR ALU operates in direct connection with all the 32 general purpose working registers Within a single clock cycle arithmetic operations between general purpose registers or between a register and an immediate are executed The ALU operations are divided into three main categories arithmetic logical and bit functions Some implementations of the architecture also provide a powerful multiplier supporting both signed unsigned multiplication and fractional format See the Instruction Set section for a detailed description 4 4 Status Register 7598G AVR 03 08 The Status Register contains information about the result of the most recently executed arith metic instruction This information can be used for altering program flow in order to perform conditional operations Note that the Status Register is updated after all ALU operations as specified in the Instruction Set Reference This will in many cases remove the need for using the dedicated compare instructions resulting in faster and more compact code The Status Register is not automatically store
208. put pin Note that OC1B is not connected in normal mode Table 14 3 Comparator B Mode Select COM1B1 COM1BO Description 0 0 Timer Counter Comparator B disconnected from output pin OC1B 0 1 Toggle the OC1B output line 1 0 Clear the OC1B output line 1 1 Set the OC1B output line In PWM mode these bits have different functions Refer to Table 14 4 on page 88 for a detailed description Bit 3 FOC1B Force Output Compare Match 1B AMEL s3 7598G AVR 03 08 AMEL Writing a logical one to this bit forces a change in the compare match output pin PB3 OC1B according to the values already set in COM1B1 and COM1B0 If COM1B1 and COM1B0 written in the same cycle as FOC1B the new settings will be used The Force Output Compare bit can be used to change the output pin value regardless of the timer value The automatic action pro grammed in COM1B1 and COM1B0 takes place as if a compare match had occurred but no interrupt is generated The FOC1B bit always reads as zero FOC1B is not in use if PWM1B bit is set Bit 2 FOC1A Force Output Compare Match 1A Writing a logical one to this bit forces a change in the compare match output pin PB1 OC1A according to the values already set in COM1A1 and COM1A0 If COM1A1 and COM1A0 written in the same cycle as FOC1A the new settings will be used The Force Output Compare bit can be used to change the output pin value regardless of the timer value The automati
209. r Register USIBR Bit 7 6 5 4 3 2 1 0 use CB uses Read Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is com pleted and instead of accessing the USI Data Register the Serial Register the USI Data Buffer can be accessed when the CPU reads the received data This gives the CPU time to handle other program tasks too as the controlling of the USI is not so timing critical The USI flags as set same as when reading the USIDR register 16 4 3 USI Status Register USISR Bit 7 3 2 1 0 6 5 4 R W R W R R W R W R W Read Write R W R W Initial Value 0 0 0 0 0 0 0 0 The Status Register contains Interrupt Flags line Status Flags and the counter value Bit 7 USISIF Start Condition Interrupt Flag When Two wire mode is selected the USISIF Flag is set to one when a start condition is detected When output disable mode or Three wire mode is selected and USICSx 0b11 amp USICLK 0 or USICS 0b10 amp USICLK 0 any edge on the SCK pin sets the flag An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global Interrupt Enable Flag are set The flag will only be cleared by writing a logical one to the USISIF bit Clearing this bit will release the start detection hold of USCL in Two wire mode A start condition interrupt will wakeup the processor from all sleep modes Bit 6 USIOIF Counter Ov
210. ransmit 0 0 PVOE 0 OC1B Enable OC1B Enable PVOV 0 OC1B _OC1B PTOE 0 0 0 DIEOE su RE PCINT4 PCIE ADC2D PCINT3 PCIE ADC3D DIEOV ADCOD ADC2D ADC3D DI PCINTS Input PCINTA Input PCINT3 Input AIO RESET Input ADCO Input ADC2 Input ADC3 Input Note 1when the Fuse is 0 Programmed Table 10 5 Overriding Signals for Alternate Functions in PB3 PBO PBO MOSI DI SDA AINO AR Signal PB2 SCK ADC1 TO PB1 MISO DO AIN1 EF OC1A OCOA Name USCK SCL INTO PCINT2 OC1A OCOB PCINT1 PCINTO PUOE 0 0 0 PUOV 0 0 0 DDOE USI TWO WIRE 0 USI TWO WIRE DDOV SGHTBS gt DDB i 0 SDA PORTBO DDBO OCOB Enable OC1A OCOA Enable OC1A PVOE USI TWO WIRE DDB2 Enable Enable USI TWO WIRE USI THREE WIRE DDBO PVOV 0 OCOB OC1A DO OCOA _OC1A PTOE USITC 0 0 DIEOE dene PCIE ADC1D PCINT1 PCIE AIN1D pete PCIE AINOD DIEOV ADC1D AIN1D AINOD DI BENE aaa PCINT1 Input DI SDA PCINTO Input AIO ADC1 Input Analog Comparator Analog Comparator Positive Negative Input Input 10 4 Register Description for l O Ports 7598G AVR 03 08 AMEL 57 10 4 1 10 4 2 10 4 3 ATMEL Port B Data Register PORTB Bit 7 6 5 4 3 2 1 0 PORTED PORTS Read Write R R R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Port B Data Direction Register DDRB Port B Input Pins Address PINB Bit 7 6 5 4 3 2 1 0 LLL Loos 5084 0083 ooB2 bo8 Do80 pone Read Write R R R W R W R W R W R
211. rated by setting the COMOx1 0 to three Setting the COMOAO bits to one allows the OCOA pin to toggle on Compare Matches if the WGM02 bit is set This option is not available for the OCOB pin See Table 12 3 on page 72 The actual OCOx value will only be visible on the port pin if the data direction for the port pin is set as output The PWM waveform is generated by clearing or setting the OCOx Register at the Compare Match between OCROx and TCNTO when the counter increments and setting or clearing the OCOx Register at Com pare Match between OCROx and TCNTO when the counter decrements The PWM frequency for the output when using phase correct PWM can be calculated by the following equation Joko focnxPCPWM N B10 The N variable represents the prescale factor 1 8 64 256 or 1024 The extreme values for the OCROA Register represent special cases when generating a PWM waveform output in the phase correct PWM mode If the OCROA is set equal to BOTTOM the output will be continuously low and if set equal to MAX the output will be continuously high for non inverted PWM mode For inverted PWM the output will have the opposite logic values At the very start of period 2 in Figure 12 7 OCn has a transition from high to low even though there is no Compare Match The point of this transition is to guaratee symmetry around BOT TOM There are two cases that give a transition without Compare Match OCROA changes its value from MAX like in Fig
212. ration and how to choose appropriate values for C1 and C2 When this oscillator is selected start up times are determined by the SUT fuses as shown in Table 6 5 Table 6 5 Start up Times for the Low Frequency Crystal Oscillator Clock Selection Start up Time from Additional Delay from Power Down and Power Power On Reset SUT1 0 Save Vec 5 0V Recommended usage 00 1K CK Ams Fast rising power or BOD enabled 01 1K CK 64 ms Slowly rising power 10 32K CK 64 ms Stable frequency at start up 11 Reserved Notes 1 These options should only be used if frequency stability at start up is not important for the application AIMEL 25 ay 7598G AVR 03 08 AMEL 6 6 Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides an 8 0 MHz clock The frequency is the nominal value at 3V and 25 C If the frequency exceeds the specification of the device depends on Vgc the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 during start up System Clock Prescaler on page 29 for more details This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6 6 If selected it will operate with no external components During reset hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator At 3V and 25 C this calibration gives a frequency within 1 of the nominal frequenc
213. re 21 6 High voltage Serial Programming Waveforms sol EO EN E SEC COCOS spo ADO C OC OC C OC GEN SCI PB3 21 8 5 Programming the EEPROM The EEPROM is organized in pages see Table 21 11 on page 137 When programming the EEPROM the data is latched into a page buffer This allows one page of data to be pro grammed simultaneously The programming algorithm for the EEPROM Data memory is as follows refer to Table 21 16 1 Load Command Write EEPROM 2 Load EEPROM Page Buffer 3 Program EEPROM Page Wait after Instr 2 until SDO goes high for the Page Pro gramming cycle to finish 4 Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been programmed 5 End Page Programming by Loading Command No Operation 21 8 6 Reading the Flash The algorithm for reading the Flash memory is as follows refer to Table 21 16 AMEL 141 7598G AVR 03 08 21 8 7 21 8 8 21 8 9 21 8 10 142 AMEL 1 Load Command Read Flash 2 Read Flash Low and High Bytes The contents at the selected address are available at serial output SDO Reading the EEPROM The algorithm for reading the EEPROM memory is as follows refer to Table 21 16 1 Load Command Read EEPROM 2 Read EEPROM Byte The contents at the selected address are available at serial out put SDO Programming and Reading the Fuse and Lock Bits The algorithms for programming and reading the
214. re generated on the Output Compare output OCOA For more details about advanced counting sequences and waveform generation see Modes of Opera tion on page 65 The Timer Counter Overflow Flag TOVO is set according to the mode of operation selected by the WGM01 0 bits TOVO can be used for generating a CPU interrupt 12 4 Output Compare Unit The 8 bit comparator continuously compares TCNTO with the Output Compare Registers OCROA and OCROB Whenever TCNTO equals OCROA or OCROB the comparator signals a match A match will set the Output Compare Flag OCFOA or OCFOB at the next timer clock cycle If the corresponding interrupt is enabled the Output Compare Flag generates an Output Compare interrupt The Output Compare Flag is automatically cleared when the interrupt is exe cuted Alternatively the flag can be cleared by software by writing a logical one to its I O bit location The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02 0 bits and Compare Output mode COMOXx1 0 bits The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Modes of Operation on page 65 Figure 12 3 shows a block diagram of the Output Compare unit Figure 12 3 Output Compare Unit Block Diagram DATA BUS 8 bit Comparator OCFnx Int Req top bottom Waveform Generator FOCn WGMn1 0
215. re instruction before any pending interrupt is served Note that the Status Register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt routine This must be handled by software When using the CLI instruction to disable interrupts the interrupts will be immediately disabled No interrupt will be executed after the CLI instruction even if it occurs simultaneously with the CLI instruction The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence Assembly Code Example in r16 SREG store SREG value cli disable interrupts during timed sequence sbiEECR EEMWE start EEPROM write sbi EECR EEWE out SREG r16 restore SREG value I bit C Code Example char cSREG CSREG SREG store SREG value disable interrupts during timed sequence CLI EECR 1 lt lt EEMWE start EEPROM write EECR 1 EEWE SREG cSREG restore SREG value I bit When using the SEI instruction to enable interrupts the instruction following SEI will be exe cuted before any pending interrupts as shown in this example Assembly Code Example sei set Global Interrupt Enable Sleep enter sleep waiting for interrupt note will enter sleep before any pending interrupt s
216. rite operations are split it is possible to do the erase operations when the system allows doing time critical operations typically after Power up To erase a byte the address must be written to EEAR If the EEPMn bits are 0b01 writing the EEPE within four cycles after EEMPE is written will trigger the erase operation only program ming time is given in Table 20 1 The EEPE bit remains set until the erase operation completes While the device is busy programming it is not possible to do any other EEPROM operations To write a location the user must write the address into EEAR and the data into EEDR If the EEPMn bits are 0b10 writing the EEPE within four cycles after EEMPE is written will trigger the write operation only programming time is given in Table 20 1 The EEPE bit remains set until the write operation completes If the location to be written has not been erased before write the data that is stored must be considered as lost While the device is busy with programming it is not possible to do any other EEPROM operations The calibrated Oscillator is used to time the EEPROM accesses Make sure the Oscillator fre quency is within the requirements described in Oscillator Calibration Register OSCCAL on page 26 The following code examples show one assembly and one C function for erase write or atomic write of the EEPROM The examples assume that interrupts are controlled e g by disabling interrupts globally so tha
217. rly the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions Figure 14 2 Timer Counter 1 Synchronization Register Block Diagram 8 BIT DATABUS IO registers Input synchronization Timer Counter1 Output synchronization registers registers mcm omm TCNT1 M ocric OCR1C ocric s SI ocric si gt OCF1A 3 OCF1A SO OCF1B 3 OCF1B SO TOV1 ors E I SYNC 1 2 CK Delay 1 CK Delay 1 CK Delay 1 2 CK Delay MODE SS A 1 l ASYNC 1 2 PCK Delay 1 PCK Delay 1 CK Delay No Delay MODE 1 2 Pokey _ _1 Pox Dey y gt I Timer Counter1 and the prescaler allow running the CPU from any clock source while the pres caler is operating on the fast 64 MHz or 32 MHz in Low Speed Mode PCK clock in the asynchronous mode Note that the system clock frequency must be lower than one third of the PCK frequency The synchronization mechanism of the asynchronous Timer Counter1 needs at least two edges of the PCK when the system clock is high If the frequency of the system clock is too high it is a risk that data or control values are lost 80 ATtiny25 45 05 memme ATtiny25 45 85 The following Figure 14 3 shows the block diagram for Timer Counter1 Figure 14 3 Timer Counter1 Block Diagram T C1 OVER T C1 COMPARE T C1 COMPARE OC1A OC1A OC1B OC1B FLOW IRQ MATCHAIRQ MATCH B IRQ PB1 PBO PB4 PB3 A
218. rom Additional Delay Power down and from Reset CKSELO SUT1 0 Power save Vec 5 0V Recommended Usage 0 00 258 CK 14CK 4 ms ceramic resonator fast rising power 0 01 258 CK dackao4ms Ceramic resonator slowly rising power 0 10 1K CK 14CK Ceramic resonator BOD enabled 0 t 1K CK 14CK 4 ms Ceramic resonator fast rising power 1 00 1K CK2 14CK 64 ms Ceramic resonator slowly rising power 1 01 16K CK 14CK Crystal Oscillator BOD enabled 1 10 16K CK 14CK dia Crystal Oscillator fast rising power 1 11 16K CK 14CK 64 ms Crystal Oscillator slowly rising power Notes 1 These options should only be used when not operating close to the maximum frequency of the device and only if frequency stability at start up is not important for the application These options are not suitable for crystals 2 These options are intended for use with ceramic resonators and will ensure frequency stability at start up They can also be used with crystals when not operating close to the maximum fre quency of the device and if frequency stability at start up is not important for the application 6 5 Low frequency Crystal Oscillator To use a 32 768 kHz watch crystal as the clock source for the device the low frequency crystal oscillator must be selected by setting CKSEL fuses to 0110 The crystal should be connected as shown in Figure 6 3 Refer to the 32 kHz Crystal Oscillator Application Note for details on oscillator ope
219. rupt 2 XOSC Output Divided System Clock Output ADC Input Channel Timer Counter1 Output Compare and PWM Output B or Pin Change Interrupt 3 XOSC Input External Clock Input ADC Input Channel Timer Counter1 Inverted Output Com pare and PWM Output B or Pin Change Interrupt 4 Serial Clock Input ADC Input Channel Timer Counter Clock Input USI Clock three wire mode USI Clock two wire mode External Interrupt or Pin Change Interrupt 5 Serial Data Input Analog Comparator Negative Input Timer CounterO Output Compare and PWM Output B Timer Counter1 Output Compare and PWM Output A USI Data Output three wire mode or Pin Change Interrupt 6 Serial Data Output Analog Comparator Positive Input Timer CounterO Output Compare and PWM Output A Timer Counter1 Inverted Output Compare and PWM Output A USI Data Input three wire mode USI Data two wire mode Voltage Ref or Pin Change Interrupt Port B Bit 5 RESET dW ADCO PCINT5 RESET External Reset input is active low and enabled by unprogramming 1 the RSTDISBL Fuse Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin dW When the debugWIRE Enable DWEN Fuse is programmed and Lock bits are unpro grammed the debugWIRE system within the target device is activated The RESET port pin is configured as a wire AND open drain bi directional I O pin with pull up enabled and becomes the communication gate
220. s Lock bit is programmed SD X XXXX XXXX XX X XXXX XXXX XX X XXXX X2dx xx O SD Read l 0_0000_1000_00 0_0000_00bb_00 0_0000_0000_00 0_0000_0000_00 Signature SII 0 0100 1100 00 0 0000 1100 00 0 0110 1000 00 0 0110 1100 oo Repeats Instr 2 4 for each signature byte address Bytes SD X XXXX XXXX XX X XXXX XXXX XX X XXXX XXXX XX q_qqqq_qqqx_xx O SD Read l 0_0000_1000_00 0 0000 0000 00 0 0000 0000 00 0 0000 0000 00 Calibration SII O0 0100 1100 00 0 0000 1100 00 O0 0111 1000 00 O0 0111 1100 00 Byte SD X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX p pppp pppx xx O SD Load No l 0_0000_0000_00 Operation SII 0_0100_1100_00 Command SD X_XXXX_XXXX_XX O Note a address high bits b address low bits d data in high bits e data in low bits p data out high bits q data out low bits x don t care 7 Lock Bit1 2 Lock Bit2 3 CKSELO Fuse 4 CKSEL1 Fuse 5 SUTO Fuse 6 SUT1 Fuse 7 CKDIV8 Fuse 8 WDTON Fuse 9 EESAVE Fuse A SPIEN Fuse B RSTDISBL Fuse C BODLEVELO Fuse D BODLEVEL1 Fuse E MONEN Fuse F SPMEN Fuse Notes 1 For page sizes less than 256 words parts of the address bbbb bbbb will be parts of the page address 2 For page sizes less than 256 bytes parts of the address bbbb bbbb will be parts of the page address 3 The EEPROM is written page wise But only the bytes that are loaded into the page are actually written to the EEPROM Page wise EEPROM access is more efficient when
221. s low When initiating a single ended conversion by setting the ADSC bit in ADCSRA the conversion starts at the following rising edge of the ADC clock cycle A normal conversion takes 13 ADC clock cycles The first conversion after the ADC is switched on ADEN in ADCSRA is set takes 25 ADC clock cycles in order to initialize the analog circuitry The actual sample and hold takes place 1 5 ADC clock cycles after the start of a normal conver sion and 14 5 ADC clock cycles after the start of an first conversion When a conversion is complete the result is written to the ADC Data Registers and ADIF is set In Single Conversion mode ADSC is cleared simultaneously The software may then set ADSC again and a new conversion will be initiated on the first rising ADC clock edge When Auto Triggering is used the prescaler is reset when the trigger event occurs This assures a fixed delay from the trigger event to the start of conversion In this mode the sample and hold takes place two ADC clock cycles after the rising edge on the trigger source signal Three addi tional CPU clock cycles are used for synchronization logic In Free Running mode a new conversion will be started immediately after the conversion com pletes while ADSC remains high For a summary of conversion times see Table 18 1 Figure 18 4 ADC Timing Diagram First Conversion Single Conversion Mode Next First Conversion Conversion N e 4 15 16 17 18 19 20 21 2
222. sabled in High voltage and Serial Programming mode The Fuse bits are locked in both Serial and High voltage Programming mode debugWire is disabled Notes 1 Program the Fuse bits before programming the LB1 and LB2 2 1 means unprogrammed 0 means programmed The ATtiny25 45 85 has three Fuse bytes Table 21 4 Table 21 5 and Table61 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes Note that the fuses are read as logical zero 0 if they are programmed Table 21 3 Fuse Extended Byte Fuse High Byte Bit No Description Default Value 7 1 unprogrammed 6 1 unprogrammed 5 1 unprogrammed 4 1 unprogrammed 3 z 1 unprogrammed n0 ATtiny25 45 05 memme 7598G AVR 03 08 Table 21 3 Fuse Extended Byte Fuse High Byte Bit No Description Default Value 2 1 unprogrammed 1 1 unprogrammed SELFPRGEN 0 Self Programming Enable 1 unprogrammed Table 21 4 Fuse High Byte Fuse High Byte Bit No Description Default Value RSTDISBL 7 External Reset disable 1 unprogrammed DWEN 6 DebugWIRE Enable 1 unprogrammed SPIEN 5 Enable Serial Program and Data 0 programmed SPI prog Downloading enabled WDTON 4 Watchdog Timer always on 1 unprogrammed EESAVE 3 EEPROM memory is preserved 1 unprogrammed EEPROM through the Chip Erase not preserved BODLEVEL2 2 Brow
223. se Low byte is similar to the one described above for reading the Lock bits To read the Fuse Low byte load the Z pointer with 0x0000 and set the RFLB and SPMEN bits in SPMCSR When an LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR the value of the Fuse Low byte FLB will be loaded in the destination register as shown below Refer to Table 21 5 on page 131 for a detailed description and mapping of the Fuse Low byte Bit 7 6 5 4 3 2 1 0 Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLBO Similarly when reading the Fuse High byte load 0x0003 in the Z pointer When an LPM instruc tion is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR the ns ATtiny25 45 05 su value of the Fuse High byte FHB will be loaded in the destination register as shown below Refer to Table 21 4 for detailed description and mapping of the Fuse High byte Bit 7 6 5 4 3 2 1 0 bid FHBT FHBe HEN FHB4 FHB3 FHB FHES FHBO Fuse and Lock bits that are programmed will be read as zero Fuse and Lock bits that are unprogrammed will be read as one 20 1 4 Preventing Flash Corruption During periods of low Voc the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly These issues are the same as for board level systems using the Flash and the same design solutions should be applied A Flash program corruption can b
224. some implementa tions of the AVR architecture is so small that only SPL is needed In this case the SPH Register will not be present Bit 15 14 13 12 11 10 9 8 seis sp Seis spiz Seir SPi0_ Ses SPH E sea Sei SP se 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 Instruction Execution Timing This section describes the general access timing concepts for instruction execution The AVR CPU is driven by the CPU clock clkepy directly generated from the selected clock source for the chip No internal clock division is used Figure 4 4 shows the parallel instruction fetches and instruction executions enabled by the Har vard architecture and the fast access Register File concept This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost functions per clocks and functions per power unit ATtiny25 45 05 memme 7598G AVR 03 08 Figure 4 4 The Parallel Instruction Fetches and Instruction Executions Ti T2 T3 T4 1 I 1 I I I 1 I I anon S7 S7 X4 AS CPU 1st Instruction Fetch 1 1 1st Instruction Execute i i po 2nd Instruction Fetch l l 2nd Instruction Execute 1 1 E 3rd Instruction Fetch i i i 3rd Instruction Execute 1 1 e 4th Instruction Fetch 1 1 i i I I I I Figure 4 5 shows the internal timing concept for the Register File In a single c
225. ssed in one single instruction executed in one clock cycle The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con ventional CISC microcontrollers The ATtiny25 45 85 provides the following features 2 4 8K byte of In System Programmable Flash 128 256 512 bytes EEPROM 128 256 256 bytes SRAM 6 general purpose I O lines 32 general purpose working registers one 8 bit Timer Counter with compare modes one 8 bit high AMEL 3 2 2 4 AMEL speed Timer Counter Universal Serial Interface Internal and External Interrupts a 4 channel 10 bit ADC a programmable Watchdog Timer with internal Oscillator and three software select able power saving modes The Idle mode stops the CPU while allowing the SRAM Timer Counter ADC Analog Comparator and Interrupt system to continue functioning The Power down mode saves the register contents disabling all chip functions until the next Inter rupt or Hardware Reset The ADC Noise Reduction mode stops the CPU and all I O modules except ADC to minimize switching noise during ADC conversions The device is manufactured using Atmel s high density non volatile memory technology The On chip ISP Flash allows the Program memory to be re programmed In System through an SPI serial interface by a conventional non volatile memory programmer or by an On chip boot code running on the AVR core The ATtiny25 45 85 AVR is supported with a full suit
226. t no interrupts will occur during execution of these functions ATtiny25 45 8 5 memm 7598G AVR 03 08 ATtiny25 45 85 Assembly Code Example I EPROM write Wait for completion of previous write sbic EECR EEPE rjmp EEPROM_write Set Programming mode ldi r16 0 lt lt out EECR r16 I EPM1 O EEPMO Set up address rl17 in address register out EEARL r17 Write data rl16 to data register out EEDR r16 Write logical one to EEMWE sbi EECR EEMWE Start eeprom write by setting EEWE sbi EECR EEWE ret C Code Example void EEPROM write unsigned char ucAddress unsigned char ucData Wait for completion of previous write while EECR amp 1 lt lt EEPE Set Programming mode EECR 0 lt lt T EPM1 0 gt gt EEPMO Set up address and data registers EEARL ucAddress EEDR ucData Write logical one to EEMWE EECR 1 lt lt EEMWE Start eeprom write by setting EEWE EECR 1 lt lt EEWE AMEL i 7598G AVR 03 08 5 3 10 20 AMEL The next code examples show assembly and C functions for reading the EEPROM The exam ples assume that interrupts are controll
227. tains 128 256 512 bytes of data EEPROM memory It is organized as a separate data space in which single bytes can be read and written The EEPROM has an endurance of at least 100 000 write erase cycles The access between the EEPROM and the CPU is described in the following specifying the EEPROM Address Registers the EEPROM Data Register and the EEPROM Control Register For a detailed description of Serial data downloading to the EEPROM see page 133 5 3 1 EEPROM Read Write Access The EEPROM Access Registers are accessible in the I O space The write access times for the EEPROM are given in Table 5 1 A self timing function however lets the user software detect when the next byte can be written If the user code contains instruc tions that write the EEPROM some precautions must be taken In heavily filtered power supplies Vcc is likely to rise or fall slowly on Power up down This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used See Preventing EEPROM Corruption on page 20 for details on how to avoid problems in these situations In order to prevent unintentional EEPROM writes a specific write procedure must be followed Refer to Atomic Byte Programming on page 17 and Split Byte Programming on page 18 for details on this When the EEPROM is read the CPU is halted for four clock cycles before the next instruction is executed When the EEPROM is written the CP
228. ter clock period multiplied by 15 15 0 3 Timer Counter1 Dead Time B DT1B Bit 7 6 5 4 8 2 1 0 25 45 DT1BH3 DT1BH2 DT1BH1 DT1BHO DT1BL3 DT1BL2 DT1BL1 DT1BLO DT1B Read Write R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 The dead time value register Bis an 8 bit read write register The dead time delay of is adjusted by the dead time value register DT1B The register consists of two fields DT1BH3 0 and DT1BL3 0 one for each complementary output Therefore a differ ent dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A Bits 7 4 DT1BH3 DT1BHO Dead Time Value for OC1B Output The dead time value for the OC1B output The dead time delay is set as a number of the pres caled timer counter clocks The minimum dead time is zero and the maximum dead time is the prescaled time counter clock period multiplied by 15 e Bits 3 0 DT1BL3 DT1BLO Dead Time Value for OC1B Output The dead time value for the OC1B output The dead time delay is set as a number of the pres caled timer counter clocks The minimum dead time is zero and the maximum dead time is the prescaled time counter clock period multiplied by 15 16 Universal Serial Interface USI 16 1 Overview 7598G AVR 03 08 The Universal Serial Interface or USI provides the basic hardware resources needed for serial communication Combined with a minimum of control software the USI allows sig
229. ternal Clock Drive Waveforms sssssssssssseseeeeeneeeen nennen 148 AMEL iii 7598F AVR 08 07 AMEL 22 3 External Glock D VE uito ated etie tese einen Pts 149 22 4 ADC Characteristics Preliminary Data sssseeenn 150 22 5 Calibrated RC Oscillator Accuracy ssssssseseeeeeneeeennenennneenne 151 23 Typical Characteristics uui enn txu i eaa uan nnn buaiS oe EREEEREEEEUREEKRRE DNE RR 151 23 1 Active Supply Current sssssssssseseseseseeeenee eene nnne entretiens 152 23 2 dle Supply CUtFGlit soisin tren tee e eee haereat tee ede ure tuin 154 23 3 Power Down Supply Current sssssssssseseeseeeeeeneen nennen 158 29 4 PI Pulbupssd s eto eciieet une eite miae ee rece rer tree er 159 23 5 Pin Driver Strength sssssssssssesssssesseenene nennen nnne tenerse 162 23 6 Pin Thresholds and Hysteresis seen 165 23 7 BOD Thresholds and Analog Comparator Offset ssssssssss 168 23 8 Internal Oscillator Speed sssssssssssssseeeeeeeennneeen nennen 169 23 9 Current Consumption of Peripheral Units sssseeeeeeee 172 23 10 Current Consumption in Reset and Reset Pulse width ssesee 173 23 11 Analog to Digital Converter ssssssssseeeeeeeeneennenen nennen 174 24 Hegisler Summary issiiinsissasinas asian anis ric End AFER rea EXH
230. th both high sink and source capability As inputs Port B pins that are externally pulled low will source current if the pull up resistors are activated The Port B pins are tri stated when a reset condition becomes active even if the clock is not running Port B also serves the functions of various special features of the ATtiny25 45 85 as listed on page 54 Reset input A low level on this pin for longer than the minimum pulse length will generate a reset even if the clock is not running The minimum pulse length is given in Table 8 1 on page 36 Shorter pulses are not guaranteed to generate a reset 3 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device These code examples assume that the part specific header file is included before compilation Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent Please confirm with the C compiler documen tation for more details 4 AVR CPU Core 4 1 Introduction 7598G AVR 03 08 This section discusses the AVR core architecture in general The main function of the CPU core is to ensure correct program execution The CPU must therefore be able to access memories perform calculations control peripherals and handle interrupts AMEL s AMEL 4 2 Architectural Overview Figure 4 1 Block Diagram of the AVR Architecture Data Bus 8
231. the SCL hold time Therefore when using this feature in this case the Oscillator start up time set by the CKSEL Fuses see Clock Systems and their Distribution on page 21 must also be taken into the consideration Refer to the USISIF bit description on page 101 for further details 16 3 Alternative USI Usage 16 3 1 16 3 2 16 3 3 16 3 4 16 3 5 16 4 16 4 1 100 When the USI unit is not used for serial communication it can be set up to do alternative tasks due to its flexible design Half duplex Asynchronous Data Transfer By utilizing the Shift Register in Three wire mode it is possible to implement a more compact and higher performance UART than by software only 4 bit Counter The 4 bit counter can be used as a stand alone counter with overflow interrupt Note that if the counter is clocked externally both clock edges will generate an increment 12 bit Timer Counter Combining the USI 4 bit counter and Timer CounterO allows them to be used as a 12 bit counter Edge Triggered External Interrupt By setting the counter to maximum value F it can function as an additional external interrupt The Overflow Flag and Interrupt Enable bit are then used for the external interrupt This feature is selected by the USICS1 bit Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe USI Register Descriptions USI Data Register USIDR Bit 7i 6 5 4 3 2 1 0
232. the current conversion before performing the channel change Alternatively a conversion can be triggered automatically by various sources Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit ADATE in ADCSRA The trigger source is selected by setting the ADC Trigger Select bits ADTS in ADCSRB see description of the ADTS bits for a list of the trigger sources When a positive edge occurs on the selected trigger signal the ADC prescaler is reset and a conversion is started This provides a method of starting con versions at fixed intervals If the trigger signal still is set when the conversion completes a new conversion will not be started If another positive edge occurs on the trigger signal during con version the edge will be ignored Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared A conversion can thus be triggered without causing an interrupt However the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event AMEL 109 7598G AVR 03 08 AMEL Figure 18 2 ADC Auto Trigger Logic ADTS 2 0 B mesonsn ADIF ADATE SOURCE 1 4 CONVERSION LOGIC EDGE SOURCE n DETECTOR ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished The ADC then operates in Free Running mode con stantly sam
233. the port and a lower case n represents the bit number However when using the register or bit defines in a program the precise form must be used For example PORTB3 for bit no 3 in Port B here documented generally as PORTxn The physical I O Regis ters and bit locations are listed in Register Description for l O Ports on page 57 Three I O memory address locations are allocated for each port one each for the Data Register PORTx Data Direction Register DDRx and the Port Input Pins PINx The Port Input Pins I O location is read only while the Data Register and the Data Direction Register are read write However writing a logic one to a bit in the PINx Register will result in a toggle in the correspond ing bit in the Data Register In addition the Pull up Disable PUD bit in MCUCR disables the pull up function for all pins in all ports when set Using the I O port as General Digital I O is described in Ports as General Digital I O on page 47 Most port pins are multiplexed with alternate functions for the peripheral features on the device How each alternate function interferes with the port pin is described in Alternate Port Functions on page 52 Refer to the individual module sections for a full description of the alter nate functions Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I O 10 2 Ports as General Digital I
234. tion The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNTO slopes represent Com pare Matches between OCROx and TCNTO Figure 12 6 Fast PWM Mode Timing Diagram OCRnx Interrupt Flag Set e SI eR RE NS a ht RUTETREN OCRnx Update and i i i i i TOVn Interrupt Flag Set lt q M TONTn OCn COMnx1 0 2 om Ll U L IL como Period I s s P S 5 of 7 The Timer Counter Overflow Flag TOVO is set each time the counter reaches TOP If the inter rupt is enabled the interrupt handler routine can be used for updating the compare value AMEL s AMEL In fast PWM mode the compare unit allows generation of PWM waveforms on the OCOx pins Setting the COMOx1 0 bits to two will produce a non inverted PWM and an inverted PWM output can be generated by setting the COMOx1 0 to three Setting the COMOA1 0 bits to one allowes the ACOA pin to toggle on Compare Matches if the WGM02 bit is set This option is not available for the OCOB pin See Table 12 2 on page 72 The actual OCOx value will only be visible on the port pin if the data direction for the port pin is set as output The PWM waveform is generated by setting or clearing the OCOx Register at the Compare Match between OCROx and TCNTO and clearing or setting the OCOx Register at the timer clock cycle the counter is cleared changes from TOP to BOTTOM The PWM frequency for the output can b
235. to Digital Converter Integral Non Linearity INL Single Ended Vcc 4V Vref 4V LSB 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature vs ATtinY25 45 85 se 24 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page Ox3F SREG l T H S V N Z C page 7 Ox3E SPH m SP8 page 10 0x3D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO page 10 Ox3C Reserved 0x3B GIMSK INTO PCIE page 59 Ox3A GIFR INTFO PCIF page 59 0x39 TIMSK OCIE1A OCIE1B OCIEOA OCIEOB TOIE1 TOIEO page 76 0x38 TIFR OCF1A OCF1B OCFOA OCFOB TOV1 TOVO page 76 0x37 SPMCSR CTPB RFLB PGWRT PGERS SPMEN page 127 0x36 Reserved 0x35 MCUCR BODS PUD SE SM1 SMO BODSE ISCO1 ISCOO page 31 page 53 page 58 0x34 MCUSR WDRF BORF EXTRF PORF page 39 0x33 TCCROB FOCOA FOCOB WGM02 cso2 CS01 C500 page 74 0x32 TCNTO Timer CounterO page 75 0x31 OSCCAL Oscillator Calibration Register page 26 0x30 TCCR1 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 page 82 page 94 Ox2F TONT1 Timer Counter1 page 84 page 95 Ox2E OCR1A Timer Counter1 Output Compare Register A page 84 page 96 0x2D OCR1
236. tor Table 17 2 Analog Comparator Multiplexed Input ACME ADEN MUX1 0 Analog Comparator Negative Input 0 X Xx AIN1 1 1 XX AIN1 1 0 00 ADCO ATtiny25 45 05 memm 7598G AVR 03 08 17 1 1 Table 17 2 Analog Comparator Multiplexed Input ACME ADEN MUX1 0 Analog Comparator Negative Input 1 0 01 ADC1 1 0 10 ADC2 1 0 11 ADC3 Digital Input Disable Register 0 DIDRO Bit 7 6 5 4 3 2 1 0 SS ADCOD ADC2D ADC3D ADC1D AIN D DIDRO Read Write R R R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 1 0 AIN1D AINOD AIN1 AINO Digital Input Disable When this bit is written logic one the digital input buffer on the AIN1 0 pin is disabled The corre sponding PIN Register bit will always read as zero when this bit is set When an analog signal is applied to the AIN1 0 pin and the digital input from this pin is not needed this bit should be writ ten logic one to reduce power consumption in the digital input buffer 18 Analog to Digital Converter 18 1 7598G AVR 03 08 Features 10 bit Resolution 0 5 LSB Integral Non linearity 2 LSB Absolute Accuracy 65 260 us Conversion Time Up to 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Two differential input channels with selectable gain Temperature sensor input channel Optional Left Adjustment for ADC Result Readout 0 Vcc ADC Input Voltage Range Selectable 1
237. tput will change immediately when the clock strobe is exe cuted i e in the same instruction cycle The value shifted into the Shift Register is sampled the previous instruction cycle The bit will be read as zero When an external clock source is selected USICS1 1 the USICLK function is changed from a clock strobe to a Clock Select Register Setting the USICLK bit in this case will select the USITC strobe bit as clock source for the 4 bit counter see Table 16 2 Bit 0 USITC Toggle Clock Port Pin Writing a one to this bit location toggles the USCK SCL value either from 0 to 1 or from 1 to 0 The toggling is independent of the setting in the Data Direction Register but if the PORT value is to be shown on the pin the DDRE4 must be set as output to one This feature allows easy clock generation when implementing master devices The bit will be read as zero When an external clock source is selected USICS1 1 and the USICLK bit is set to one writ ing to the USITC strobe bit will directly clock the 4 bit counter This allows an early detection of when the transfer is done when operating as a master device 17 Analog Comparator 104 The Analog Comparator compares the input values on the positive pin AINO and negative pin AIN1 When the voltage on the positive pin AINO is higher than the voltage on the negative pin AIN1 the Analog Comparator output ACO is set The comparator can trigger a separate inter rupt exclusive to t
238. tware Break Points Non intrusive Operation Electrical Characteristics Identical to Real Device Automatic Configuration System High Speed Operation Programming of Non volatile Memories The debugWIRE On chip debug system uses a One wire bi directional interface to control the program flow execute AVR instructions in the CPU and to program the different non volatile memories AMEL 123 AMEL 19 3 Physical Interface When the debugWIRE Enable DWEN Fuse is programmed and Lock bits are unprogrammed the debugWIRE system within the target device is activated The RESET port pin is configured as a wire AND open drain bi directional I O pin with pull up enabled and becomes the commu nication gateway between target and emulator Figure 19 1 The debugWIRE Setup 1 8 5 5V O dw Figure 19 1 shows the schematic of a target MCU with debugWIRE enabled and the emulator connector The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses When designing a system where debugWIRE will be used the following observations must be made for correct operation e Pull Up resistor on the dW RESET line must be in the range of 10k to 20 kQ However the pull up resistor is optional e Connecting the RESET pin directly to Vcc will not work Capacitors inserted on the RESET pin must be disconnected when using debugWire All external reset sources must be disconnected 19 4 So
239. ues to this regis ter will increase the frequency of the internal Oscillator Writing OxFF to the register gives the highest available frequency The calibrated Oscillator is used to time EEPROM and Flash access If EEPROM or Flash is written do not calibrate to more than 8 8 MHz frequency Other wise the EEPROM or Flash write may fail The CAL7 bit determines the range of operation for the oscillator Setting this bit to O gives the lowest frequency range setting this bit to 1 gives the highest frequency range The two fre 26 ATtiny25 45 05 mememe 6 7 7598G AVR 03 08 quency ranges are overlapping in other words a setting of OSCCAL 0x7F gives a higher frequency than OSCCAL 0x80 The CAL6 0 bits are used to tune the frequency within the selected range A setting of 0x00 gives the lowest frequency in that range and a setting of Ox7F gives the highest frequency in the range Incrementing CAL6 0 by 1 will give a frequency increment of less than 2 in the fre quency range 7 3 8 1 MHz Avoid changing the calibration value in large steps when calibrating the calibrated internal RC Oscillator to ensure stable operation of the MCU A variation in frequency of more than 296 from one cycle to the next can lead to unpredicatble behavior Changes in OSCCAL should not exceed 0x20 for each calibration It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency Table 6 8 Internal RC Oscillator
240. unter1 Overflow Interrupt Enable and TOV1 are set one the Timer Counter1 Overflow interrupt is executed Bit 0 Res Reserved Bit This bit is a reserved bit in the ATtiny25 45 85 and always reads as zero PLL Control and Status Register PLLCSR Bit 7 6 5 4 3 2 1 0 se 18M RET PLE FLOCK Perosa Read Write R W R R R R R W R W R Initial value 0 0 0 0 0 0 0 1 0 Bit 7 LSM Low Speed Mode The high speed mode is enabled as default and the fast peripheral clock is 64 MHz but the low speed mode can be set by writing the LSM bit to one Then the fast peripheral clock is scaled down to 32 MHz The low speed mode must be set if the supply voltage is below 2 7 volts because the Timer Counter1 is not running fast enough on low voltage levels It is highly recom mended that Timer Counter1 is stopped whenever the LSM bit is changed Bit 6 3 Res Reserved Bits These bits are reserved bits in the ATtiny25 45 85 and always read as zero Bit 2 PCKE PCK Enable The PCKE bit change the Timer Counter1 clock source When it is set the asynchronous clock mode is enabled and fast 64 MHz or 32 MHz in Low Speed Mode PCK clock is used as Timer Counter1 clock source If this bit is cleared the synchronous clock mode is enabled and system clock CK is used as Timer Counter1 clock source This bit can be set only if PLLE bit is set It is safe to set this bit only when the PLL is locked i e the PLOCK bit is 1 The bit PCKE can only be set if
241. ure 12 7 When the OCROA value is MAX the OCn pin value is the same as the result of a down counting Compare Match To ensure AMEL s 7598G AVR 03 08 AMEL symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up counting Compare Match The timer starts counting from a value higher than the one in OCROA and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up 12 7 Timer Counter Timing Diagrams The Timer Counter is a synchronous design and the timer clock clky9 is therefore shown as a clock enable signal in the following figures The figures include information on when Interrupt Flags are set Figure 12 8 contains timing data for basic Timer Counter operation The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode Figure 12 8 Timer Counter Timing Diagram no Prescaling BOTTOM BOTTOM 1 Figure 12 9 shows the same timing data but with the prescaler enabled Figure 12 9 Timer Counter Timing Diagram with Prescaler f i 5 8 ernan Tw i TCNTn clk BOTTOM BOTTOM 1 TOVn Figure 12 10 shows the setting of OCFOB in all modes and OCFOA in all modes except CTC mode and PWM mode where OCROA is TOP 70 ATtiny25 45 05 memme Figure 12 10 Timer Counter Timing Diagram Setting of OCFOx with Prescaler f 10 8 f ex FAUE
242. used to drive other cir cuits on the system Note that the clock will not be output during reset and the normal operation of I O pin will be overridden when the fuse is programmed Any clock source including the inter nal RC Oscillator can be selected when the clock is output on CLKO If the System Clock Prescaler is used it is the divided system clock that is output ATtiny25 45 8 5 memm 7598G AVR 03 08 6 10 System Clock Prescaler The ATtiny25 45 85 system clock can be divided by setting the Clock Prescale Register CLKPR This feature can be used to decrease power consumption when the requirement for processing power is low This can be used with all clock source options and it will affect the clock frequency of the CPU and all synchronous peripherals clkyo clKApc Clkgpy and clkgi asy are divided by a factor as shown in Table 6 13 6 10 1 Clock Prescale Register CLKPR Bit 7 6 5 4 3 2 1 0 CLKPCE o 7 CLKPS3 CLKPS2 CLKPS1 CLKPSO CLKPR Read Write R W R R R R W R W R W R W Initial Value 0 0 0 0 See Bit Description Bit 7 CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits The CLKPCE bit is only updated when the other bits in CLKPR are simultaniosly written to zero CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written Rewriting the CLKPCE bit within this time out period does neither extend the time out per
243. ved for future use e Bit 3 EERIE EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set Writing EERIE to zero disables the interrupt The EEPROM Ready Interrupt generates a constant inter rupt when Non volatile memory is ready for programming e Bit2 EEMPE EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not When EEMPE is set setting EEPE within four clock cycles will program the EEPROM at the selected address If EEMPE is zero setting EEPE will have no effect When EEMPE has been written to one by software hardware clears the bit to zero after four clock cycles Bit 1 EEPE EEPROM Program Enable The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM When EEPE is written the EEPROM will be programmed according to the EEPMnh bits setting The EEMPE bit must be written to one before a logical one is written to EEPE otherwise no EEPROM write takes place When the write access time has elapsed the EEPE bit is cleared by hardware When EEPE has been set the CPU is halted for two cycles before the next instruction is executed e Bit 0 EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM When the cor rect address is set up in the EEAR Register the EERE bit must be written to one to trigger the EEPROM read The EEPROM read a
244. way between target and emulator ADCO Analog to Digital Converter Channel 0 PCINT5 Pin Change Interrupt source 5 Port B Bit 4 XTAL2 CLKO ADC2 OC1B PCINTA 54 ATtiny25 45 05 memme 7598G AVR 03 08 XTAL2 Chip Clock Oscillator pin 2 Used as clock pin for all chip clock sources except internal calibrateble RC Oscillator and external clock When used as a clock pin the pin can not be used as an I O pin When using internal calibratable RC Oscillator or External clock as a Chip clock sources PB4 serves as an ordinary I O pin CLKO The devided system clock can be output on the pin PB4 The divided system clock will be output if the CKOUT Fuse is programmed regardless of the PORTB4 and DDB4 settings It will also be output during reset ADC2 Analog to Digital Converter Channel 2 OC1B Output Compare Match output The PB4 pin can serve as an external output for the Timer Counter1 Compare Match B when configured as an output DDB4 set The OC1B pin is also the output pin for the PWM mode timer function PCINT4 Pin Change Interrupt source 4 Port B Bit 3 XTAL1 ADC3 OC1B PCINT3 XTAL1 Chip Clock Oscillator pin 1 Used for all chip clock sources except internal calibrateble RC oscillator When used as a clock pin the pin can not be used as an I O pin ADC3 Analog to Digital Converter Channel 3 OC1B Inverted Output Compare Match output The PB3 pin can serve as an external output for the Timer Counter1
245. with the function of the Analog Comparator OCOA Output Compare Match output The PBO pin can serve as an external output for the Timer CounterO Compare Match A when configured as an output DDBO set one The OCOA pin is also the output pin for the PWM mode timer function OC1A Inverted Output Compare Match output The PBO pin can serve as an external output for the Timer Counter1 Compare Match B when configured as an output DDBO set The OC1A pin is also the inverted output pin for the PWM mode timer function SDA Two wire mode Serial Interface Data AREF External Analog Reference for ADC Pullup and output driver are disabled on PBO when the pin is used as an external reference or Internal Voltage Reference with external capacitor at the AREF pin DI Data Input in USI Three wire mode USI Three wire mode does not override normal port functions so pin must be configure as an input for DI function PCINTO Pin Change Interrupt source 0 ATtiny25 45 05 mmm 7598G AVR 03 08 Table 10 4 and Table 10 5 relate the alternate functions of Port B to the overriding signals shown in Figure 10 5 on page 52 Table 10 4 Overriding Signals for Alternate Functions in PB5 PB3 Signal PB5 RESET PB4 ADC2 XTAL2 PB3 ADC3 XTAL1 Name ADCO PCINT5 OC1B PCINTA OC1B PCINT3 PUOE RSTDISBL DWEN 0 0 PUOV 1 0 0 DDOE RSTDISBL DWEN 0 0 DDOV debugWire T
246. wn counting Note 1 A special case occurs when OCROA equals TOP and COMOA1 is set In this case the Com pare Match is ignored but the set or clear is done at TOP See Phase Correct PWM Mode on page 68 for more details Bits 5 4 COMOB1 0 Compare Match Output B Mode These bits control the Output Compare pin OCOB behavior If one or both of the COMOB1 0 bits are set the OCOB output overrides the normal port functionality of the I O pin it is connected to However note that the Data Direction Register DDR bit corresponding to the OCOB pin must be set in order to enable the output driver 72 ATtiny25 45 05 memme 7598G AVR 03 08 When OCOB is connected to the pin the function of the COMOB1 0 bits depends on the WGM02 0 bit setting Table 12 1 shows the COMOAt1 0 bit functionality when the WGM02 0 bits are set to a normal or CTC mode non PWM Table 12 4 Compare Output Mode non PWM Mode COMO01 COMOO Description 0 0 Normal port operation OCOB disconnected 0 1 Toggle OCOB on Compare Match 1 0 Clear OCOB on Compare Match 1 1 Set OCOB on Compare Match Table 12 2 shows the COMOB 1 0 bit functionality when the WGMO2 0 bits are set to fast PWM mode Table 12 5 Compare Output Mode Fast PWM Mode COMO01 COMOO Description 0 0 Normal port operation OCOB disconnected 0 1 Reserved 1 0 Clear OCOB on Compare Match set OCOB at TOP 1 1 Set OCOB on Compare Match clear OC
247. written If Auto Triggering is used the exact time of the triggering event can be indeterministic Special care must be taken when updating the ADMUX Register in order to control which conversion will be affected by the new settings If both ADATE and ADEN is written to one an interrupt event can occur at any time If the ADMUX Register is changed in this period the user cannot tell if the next conversion is based on the old or the new settings ADMUX can be safely updated in the following ways a When ADATE or ADEN is cleared b During conversion minimum one ADC clock cycle after the trigger event c After a conversion before the Interrupt Flag used as trigger source is cleared When updating ADMUX in one of these conditions the new settings will affect the next ADC conversion 18 5 1 ADC Input Channels When changing channel selections the user should observe the following guidelines to ensure that the correct channel is selected In Single Conversion mode always select the channel before starting the conversion The chan nel selection may be changed one ADC clock cycle after writing one to ADSC However the simplest method is to wait for the conversion to complete before changing the channel selection In Free Running mode always select the channel before starting the first conversion The chan nel selection may be changed one ADC clock cycle after writing one to ADSC However the simplest method is to wait for the first co
248. xecuting powerful instructions in a single clock cycle the ATtiny25 45 85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed ATtiny25 45 8 5 mmm 2 1 Block Diagram 7598G AVR 03 08 Figure 2 1 Block Diagram 8 BIT DATABUS CALIBRATED INTERNAL OSCILLATOR PROGRAM STACK WATCHDOG TIMING AND COUNTER POINTER TIMER CONTROL vcc A MCU CONTROL PROGRAM REGISTER FLASH lt MCU STATUS REGISTER GND INSTRUCTION GENERAL REGISTER PURPOSE gt REGISTERS TIMER COUNTER INSTRUCTION COUNTER1 M UNIVERSAL de VJ E INTERFACE STATUS Ee INTERRUPT REGISTER UNIT PROGRAMMING LOGIC DATA EEPROM OSCILLATORS DATA REGISTER DATA DIR PORT B REG PORT B pasa RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i i DECODER TIMER l 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I I 1 1 1 1 1 1 i 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PBO PB5 The AVR core combines a rich instruction set with 32 general purpose working registers All the 32 registers are directly connected to the Arithmetic Logic Unit ALU allowing two independent registers to be acce
249. y When this Oscillator is used as the chip clock the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time out For more information on the pre programmed calibration value see the section Calibration Byte on page 132 Table 6 6 Internal Calibrated RC Oscillator Operating Modes CKSEL3 0 Nominal Frequency 0010 8 0 MHz Note 1 The device is shipped with this option selected When this Oscillator is selected start up times are determined by the SUT Fuses as shown in Table 6 7 Table 6 7 Start up Times for the Internal Calibrated RC Oscillator Clock Selection Start up Time Additional Delay from SUT1 0 from Power down Reset Vcc 5 0V Recommended Usage 00 6 CK 14CK 4 ms BOD enabled 01 6 CK 14CK 4 ms Fast rising power 100 6 CK 14CK 64 ms Slowly rising power 11 Reserved Note 1 The device is shipped with this option selected 6 6 1 Oscillator Calibration Register OSCCAL Bit 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CALO OSCCAL Read Write R W R W R W R W R W R W R W R W Initial Value Device Specific Calibration Value Bits 7 0 CAL7 0 Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process vari ations from the Oscillator frequency This is done automatically during Chip Reset When OSCCAL is zero the lowest available frequency is chosen Writing non zero val
250. y only the function of the outputs are affected by these bits Data and clock inputs are not affected by the mode selected and will always have the same function The counter and Shift Register can therefore be clocked exter nally and data input sampled even when outputs are disabled The relations between USIWM1 0 and the USI operation is summarized in Table 16 1 ATtiny25 45 05 memm 7598G AVR 03 08 Table 16 1 Relations between USIWM1 0 and the USI Operation USIWM1 USIWMO Description Outputs clock hold and start detector disabled Port pins operates as normal Three wire mode Uses DO DI and USCK pins The Data Output DO pin overrides the corresponding bit in the PORT Register in this mode However the corresponding DDR bit still controls the data direction When the port pin is set as input the pins pull up is controlled 0 1 by the PORT bit The Data Input DI and Serial Clock USCK pins do not affect the normal port operation When operating as master clock pulses are software generated by toggling the PORT Register while the data direction is set to output The USITC bit in the USICR Register can be used for this purpose Two wire mode Uses SDA DI and SCL USCK pins The Serial Data SDA and the Serial Clock SCL pins are bi directional and uses open collector output drives The output drivers are enabled by setting the corresponding bit for SDA and SCL in the DDR Register When the output driver is en

ATMEL ATtiny85 handbook (1)

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