ATMEL Atmel AVR micro controller ATmega32M1 handbook
Contents
1. Part number ATmega32C1 ATmega64C1 16 1 ATmega32M1 ATmega64M1 Flash Size 32 Kbyte 64 Kbyte 16 Kbyte 32 Kbyte 64 Kbyte RAM Size 2048 bytes 4096 bytes 1024 bytes 2048 bytes 4096 bytes EEPROM Size 1024 bytes 2048 bytes 512 bytes 1024 bytes 2048 bytes 8 bit Timer Yes 16 bit Timer Yes PSC No Yes PWM Outputs 4 4 10 10 10 Fault Inputs PSC 0 0 3 3 3 PLL 32 64 MHz 10 bit ADC Channels 10 bit DAC Analog Comparators 4 Current Source Yes CAN Yes LIN UART Yes On Chip Temp Sensor Yes SPI Interface Yes AMEL 7647DS AVR 08 08 AMEL 1 Pin Configurations Figure 1 1 ATmega16 32 64M1 TQFP32 QFN32 7 7 mm Package U E S con 5 SaB SE gt 5885 Uar F gt 2422 r LI lt 25225544 lt lt 0 LO o M ON OC CY PCINT18 PSCIN2 OC1A MISO A PD2 01 Q 24 1 PB4 4 PCINT19 TXD TXLIN OCOA SS MOSI A T 23 D PB3 AMPO PCINT3 PCINT9 PSCIN1 OC1B SS A PC1 22 PC6 ADC10 ACMP1 PCINT14 vec 4 21 AREF ISRC GND 15 20 AGND PCINT10 TO TXCAN PC2 6 19 AVCC PCINT11 T1 RXCAN ICP1B2. OxBD Reserved 9 PEV2 PEV1 PEVO PEOP page 155 0xBB PIM 2 PEVE1 PEVEO PEOPE page 155 OxBA PMIC2 POVEN2 PISEL2 PELEV2 PFLTE2 PAOC2 PRFM22 PRFM21 PRFM20 page 154 0 9 1 PISEL1 PELEV1 PFLTE1 PAOC1 PRFM12 PRFM11 PRFM10 page 154 0xB8 9 PMICO POVENO PISELO PELEVO PFLTEO PAOCO PRFM02 PRFMO01 PRFMOO page 154 0xB7 9 PCTL PPRE1 PPREO PCLKSEL PCCYC PRUN page 153 0xB6 9 POC 2 2 POEN1B POEN1A POENOB POENOA page 149 0xB5 9 PCNF PULOCK PMODE POPB POPA page 152 0xB4 9 PSYNC PSYNC21 PSYNC20 PSYNC11 PSYNC10 PSYNCO1 PSYNCOO page 150 0xB3 9 POCR RBH POCR RB11 POCR RB10 POCR RB9 POCR RB8 page 152 0xB2 9 POCR RBL POCR RB7 POCR RB6 POCR RB5 POCR RB4 POCR RB3 POCR RB2 POCR RB1 POCR RBO page 152 0xB1 9 POCR2SBH POCR2SB11 POCR2SB10 POCR2SB9 POCR2SB8 page 152 0 POCR2SBL POCR2SB7 POCR2SB6 POCR2SB5 POCR2SB4 POCR2SB3 POCR2SB2 POCR2SB1 POCR2SBO page 152 OxAF 9 POCR2RAH POCR2RA11_ POCR2RA10 POCR2RA9 POCR2RA8 page 151 OxAE 9 POCR2RAL POCR2RA7 POCR2RA6 POCR2RA5 POCR2RA4 POCR2RA3 POCR2RA2 POCR2RA1 POCR2RAO page 151 OxAD POCR2SAH POCR2SA11 POCR2SA10 POCR2SA9 POCR2SA8 page 151 0 POCR2SAL POCR2SA7 POCR2SA6 POCR2SA5 POCR2SA4 POCR2SA3 POCR2SA2 POCR2SA1 POCR2SA0 page 151 0 15 POCR1SB11 POCR1SB10 POCR1SB9 POCR1SB8 page 152 5 POCR1SBL PO
3. 6 5 4 2 1 193 9 15 TIMTTC14 TIMTTC13 TIMTTC12 TIMTTC11 TIMTTC10 TIMTTC9 TIMTTC8 page 193 OxE8 CANTTCL TIMTTC7 TIMTTC6 TIMTTC5 TIMTTC4 TIMTTC3 TIMTTC2 TIMTTC1 TIMTTCO page 193 OxE7 CANTIMH CANTIM15 CANTIM14 CANTIM13 CANTIM12 11 10 CANTIM9 CANTIM8 page 193 OxE6 CANTIML CANTIM7 CANTIM6 5 CANTIM4 CANTIM3 CANTIM2 CANTIM1 CANTIMO page 193 OxE5 CANTCON TPRSC7 TPRSC6 TPRSC5 TPRSC4 TPRSC3 TPRSC2 TRPSC1 TPRSCO page 192 OxE4 CANBT3 522 521 520 12 11 10 SMP page 192 OxE3 CANBT2 SJW1 SJWO PRS2 PRS1 PRSO page 191 OxE2 CANBT1 BRP5 BRP4 BRP3 BRP2 BRP1 BRPO 190 OxE1 CANSIT1 190 0 0 CANSIT2 15 14 SIT3 SIT2 SIT1 SITO page 190 OxDF CANIE1 190 2 1 5 1 4 1 1 2 IEMOB1 IEMOBO page 190 OxDD CANEN1 189 OxDC CANEN2 5 4 2 1 ENMOBO page 189 OxDB CANGIE ENIT ENBOFF ENRX ENTX ENERR ENBX ENERG ENOVRT page 188 OxDA CANGIT CANIT BOFFIT OVRTIM BXOK SERG CERG FERG AERG page 187 OxD9 CANGSTA OVRG TXBSY RXBSY ENFG BOFF ERRP page 186 OxD8 CANGCON ABRQ OVRQ TTC SYNTTC LISTEN TEST ENA STB SWRES page 185 OxD7 Reserved OxD6 Reserved OxD5 Reserved OxD4 R
4. 9 Pin Change Interrupt 9 TO Timer 0 clock input 6 PC2 y o TXCAN CAN Transmit Output PCINT10 Pin Change Interrupt 10 T1 Timer 1 clock input RXCAN CAN Receive Input 7 ICP1B Timer 1 input capture alternate B input PCINT11 Pin Change Interrupt 11 ADC8 Analog Input Channel 8 17 VO AMP1 Analog Differential Amplifier 1 Negative Input ACMPN3 Analog Comparator 3 Negative Input PCINT12 Pin Change Interrupt 12 ADC9 Analog Input Channel 9 1 Analog Differential Amplifier 1 Positive Input ACMP3 Analog Comparator Positive Input PCINT13 Pin Change Interrupt 13 18 5 ADC10 Analog Input Channel 10 22 PC6 ACMP1 Analog Comparator 1 Positive Input PCINT14 Pin Change Interrupt 14 D2A DAC output 25 PC7 2 Analog Differential Amplifier 2 Positive Input PCINT15 Pin Change Interrupt 15 PSCOUTOA PSC Module 0 Output A PCINT16 Pin Change Interrupt 16 29 PDO PSCINO Digital Input 0 32 PD1 CLKO System Clock Output PCINT17 Pin Change Interrupt 17 Timer 1 Output Compare PSCIN2 PSC Digital Input 2 1 PD2 y o MISO A Programming amp alternate SPI Master In Slave Out PCINT18 Pin Change Interrupt 18 TXD UART Tx data TXLIN LIN Transmit Output OCOA Timer 0 Output Compare 2 PD3 y o SS SPI Slave Select MOSI A Programming amp alternate Master Out
5. 1151 1150 AC1ICE 1 2 1 1 1 0 262 0 94 ACOIE ACOIS1 ACOISO ACCKSEL ACOM2 1 ACOMO page 261 0x93 Reserved 0 92 DACH DAC9 DAC8 DAC6 5 DAC4 DAC9 DAC3 DAC8 DAC2 page 270 0x91 DACL DAC1 DAC6 DACO DAC5 DAC3 DAC2 DAC1 270 0 90 DACON DAATE DATS2 DATS1 DATSO DALA DAOE DAEN page 269 Ox8F Reserved Ox8E Reserved Ox8D Reserved 0 8 Reserved 0 8 OCR1BH OCR1B15 OCR1B14 OCR1B13 OCR1B12 OCR1B11 OCR1B10 OCR1B9 OCR1B8 page 131 Ox8A OCR1BL OCR1B7 OCR1B6 OCR1B5 1 4 OCR1B3 OCR1B2 OCR1B1 OCR1BO page 132 0x89 OCR1AH OCR1A15 OCR1A14 OCR1A13 OCR1A12 OCR1A11 OCR1A10 OCR1A9 OCR1A8 page 131 0x88 OCR1AL OCR1A7 OCR1A6 OCR1A5 OCR1A4 OCR1A3 OCR1A2 OCR1A1 OCR1A0 page 131 0x87 ICR115 ICR114 ICR113 ICR112 ICR111 ICR110 ICR19 ICR18 page 133 0x86 ICR1L ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 ICR10 page 133 0x85 TCNT1H 115 114 TCNT113 TCNT112 TCNT111 TCNT110 TCNT19 TCNT18 page 131 0x84 TCNT1L TCNT17 TCNT16 TCNT15 14 TCNT13 TCNT12 TCNT11 TCNT10 page 131 0x83 Reserved 0 82 1 1 1 131 0 81 TCCR1B ICNC1 ICES1 13 WGM12 CS12 CS11 CS10 page 130 0x80 TCCR1A COM1A1 1
6. 0 70 Reserved Ox6F TIMSK1 1 OCIE1B OCIE1A TOIE1 page 133 Ox6E TIMSKO OCIEOA TOIEO page 105 Ox6D PCMSK3 26 25 24 85 0x6C PCMSK2 PCINT23 PCINT22 PCINT21 20 19 18 17 16 86 0 6 5 1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 10 9 PCINT8 page 86 0x6A PCMSKO PCINT7 PCINT6 5 PCINTA PCINT3 PCINT2 PCINT1 PCINTO page 86 0x69 EICRA ISC31 ISC30 ISC21 15 20 ISC11 ISC10 15 01 15 00 83 0x68 PCICR 2 1 84 0 67 Reserved 0 66 OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CALO page 33 0x65 Reserved 0 64 PRR 5 PRSPI PRLIN PRADC page 42 0x63 Reserved 0 62 Reserved 0 61 CLKPR CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPSO page 38 0x60 WDTCSR WDIE WDP3 WDCE WDE WDP2 WDP1 WDPO page 53 Ox3F Ox5F SREG H S V N 7 14 0 5 5 5 15 5 14 13 5 12 5 11 5 10 5 9 5 8 16 Ox3D 0 50 SPL 5 7 5 6 5 5 SP4 SP3 SP2 SP1 SPO page 16 Ox3C 0x5C Reserved 0 5 Reserved 0x5A Reserved 0x39 0x59 Reserved 0x38 0x58 Reserved 0x37
7. 1 1 COM1BO WGM11 WGM10 page 127 Ox7F DIDR1 AMP2PD ACMPOD AMPOPD AMPOND ADC10D ADC9D ADC8D page 246 Ox7E DIDRO ADC7D ADC6D ADC5D ADC4D ADC2D ADC1D ADCOD age 246 0 70 Reserved 14 ATmega16 32 64 M1 C1 7647DS AVR 08 08 16 32 64 1 1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x7C ADMUX REFS1 REFSO ADLAR MUX3 MUX2 MUX1 MUXO page 242 0 7 ADCSRB ADHSM ISRCEN AREFEN ADTS3 ADTS2 ADTS1 ADTSO page 244 Ox7A ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPSO page 243 0x79 ADCH ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC9 ADC3 ADC8 ADC2 page 245 0x78 ADCL ADC7 ADC1 ADC6 ADCO ADC5 ADC4 ADC2 1 245 0 77 AMP2CSR AMP2EN AMP2IS AMP2G1 260 2 AMP2TS2 AMP2TS1 AMP2TSO page 252 0x76 AMP1CSR AMP1EN 115 1 1 160 1 1 2 1 1 AMP1TSO page 252 0x75 AMPOCSR AMPOEN AMPOIS 1 AMPOTS2 AMPOTS1 AMPOTSO page 251 0x74 Reserved 0 73 Reserved 0 72 Reserved 0 71 Reserved
8. 1 mm HERREN 7647DS AVR 08 08 Ne 21 6 32 64 M1 C1 7 Package Information MA PV Package Type MA 32 Lead 7x7 mm Body Size 1 0 mm Body Thickness 0 5 mm Lead Pitch Thin Profile Plastic Quad Flat Package TQFP PV 32 Lead 5 0 5 0 mm 0 50 mm Pitch Quad Flat No Lead Package QFN 7647DS AVR 08 08 AMEL 23 7 1 2 TOP VIEW BOTTOM VIEW NDTE BACKSIDE EJECTOR PIN MARKS SEE DETAIL 8 PLACES 71113 SEE DETAIL AB UR 2 DETAIL Aa 0 MIN JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS 0 08 0 20 R 0 25 GAUGE PLANE 0 20 MIN 7 00 BSC Mo REF 9 00 BSC DETAIL 07 26 07 TITLE DRAWING No S A AME BEND MA 32 Lead 7x7 Body Size 1 0 mm Body Thickness pen 09 14306 Nantes Coders France 0 5 mm Lead Pitch Thin Profile Plastic Quad Flat Package TQFP M ATmega16 32 64 M1 C1 mmm 7647DS AVR 08 08 16 32 64 1 1 7 2 QFN32 T SEATING PLANE TOP_ VIEW iO 080 DRAWINGS NOT SCALED COMMON DIMENSIONS IN MM Option A Option B 1 Notch Pin 1 Chamfer Pin C 0 30 CO 20 R Triangle Compliant Standard MO 220 variation VKKC 07 26 07 DRAWING No TITLE PV 32 Lead 7 0x7 0 mm Body 0 65 mm Pitch Quad Flat No Lea
9. PC3 7 18 PC5 ADC9 ACMP3 AMP1 PCINT13 PCINTO MISO PSCOUT24A PBO T 17 D 1 12 mot o Oc _ EE r BEOASRAR 2 amp amp EPEE 2Rxx ZZZUU noo Ot 2 amp amp amp x lt gt Ps lt 05 a Uy xo M o od m 948 gt 8596 2545082 2 5 8 9 lt e lt lt lt 5 N lt o Note the engineering samples Parts marked AT9OPWM324 the alternate function is not located PC4 It is located on PE2 4 ATmega16 32 64 M1 C1 mmm 7647DS AVR 08 08 INC a1 6 32 64 M1 C1 Figure 1 2 ATmega32 64C1 TQFP32 QFN32 7 7 mm Package ATmega32 64C1 TQFP32 QFN32 2 a a m z a lt lt e BB 9 2 20 20s fegt m 2 amp 2 lt 55555485 lt lt 0 e Q doo rct CO QN QN QN QN PCINT18 OC1A MISO A PD2 01 241 AMPO PCINT4 PCINT19 TXD TXLIN OCOA SS MOSI_A 2 2 PB3 AMPO PCINT3 PCINT9 OC1B SS_A PC1 03 2210 PC6 ADC1O ACMP1 PCINT14 vec 4 21 1 AREF ISRC GND 5 200 AGND PCINTLO TO TXCAN 2 6 190 PCINT
10. PE2 can be used as output from the inverting Oscillator amplifier AMEL n AMEL The various special features of Port E are elaborated in Alternate Functions of Port E on page 78 and Clock Systems and their Distribution on page 29 2 3 7 AVCC is the supply voltage for the A D Converter D A Converter Current source It should be externally connected to Vcc even if the ADC DAC are not used If the ADC is used it should be connected to Vec through a low pass filter 2 3 8 AREF This is the analog reference pin for the A D Converter 2 4 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device These code examples assume that the part specific header file is included before compilation Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent Please confirm with the C compiler documen tation for more details 12 ATmegat6 32 64 M1 C1 mmm 7647DS AVR 08 08 X 16 32 64 1 1 3 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
11. 0 57 5 5 SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN page 281 0x36 0x56 Reserved 0 35 0x55 MCUCR SPIPS IVSEL IVCE page 59 amp page 68 0x34 0x54 MCUSR WDRF BORF EXTRF PORF page 49 0x33 0x53 SMCR SM2 SM1 SMO SE page 40 0x32 0x52 MSMCR Monitor Stop Mode Control Register reserved 0x31 0 51 MONDR Monitor Data Register reserved 0x30 0x50 ACSR ACAIF ACOIF AC3O AC20 AC10 ACOO page 265 Ox2F Ox4F Reserved Ox2E 0 4 SPDR SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPDO page 165 Ox2D 0x4D SPSR SPIF WCOL SPI2X page 164 0 2 0 4 5 5 SPE DORD MSTR CPOL CPHA SPR1 SPRO page 163 2 0x4B Reserved 2 0 4 Reserved 0 29 0 49 PLLCSR PLLF PLLE PLOCK page 36 0x28 0x48 OCROB OCROB7 OCROB6 5 OCROB4 OCROB3 OCROB2 OCROB1 OCROBO page 105 0x27 0x47 OCROA OCROA7 OCRO0A6 OCRO0A5 OCROA4 OCROA3 OCROA2 1 OCROAO page 105 0x26 0x46 TCNTO TCNTO7 06 TCNTOS TCNT04 TCNTOS3 TCNTO2 TCNTO1 TCNTOO page 105 0x25 0x45 TCCROB FOCOA FOCOB WGM02 502 501 500 103 0 24 0 44 1 1 WGMO1 WGMOO page 101 0x23 0x43 GTCCR TSM ICPSEL1 PSRSYNC page 88 0x22 0x42 EEARH EEAR9 EEAR8 page 23 0 21 0x41 EEARL EEAR7 EEAR6 5 EEARA EEARS3 EEAR2 EEAR1 EEARO pag
12. C1 memm 7647DS AVR 08 08 16 32 64 1 1 2 3 3 Port PB7 PBO Port B is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port B output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port B pins that are externally pulled low will source current if the pull up resistors are activated The Port B pins are tri stated when a reset condition becomes active even if the clock is not running Port B also serves the functions of various special features of the ATmega16 32 64 M1 C1 as listed on page 68 2 3 4 Port C 7 Port C is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port C output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port C pins that are externally pulled low will source current if the pull up resistors are activated The Port C pins are tri stated when a reset condition becomes active even if the clock is not running Port C also serves the functions of special features of the ATmega16 32 64 M1 C1 as listed on page 72 2 3 5 Port D PD7 PDO Port D is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port D output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port D pins that are
13. SPI Slave In PCINT19 Pin Change Interrupt 19 AMEL 7 7647DS AVR 08 08 Table 1 1 AMEL Pin out description Continued QFN32 Pin Number Mnemonic Type Name Function amp Alternate Function 12 PD4 ADC1 Analog Input Channel 1 RXD UART Rx data RXLIN LIN Receive Input ICP1A Timer 1 input capture alternate A input SCK A Programming amp alternate SPI Clock 20 Pin Change Interrupt 20 13 PD5 2 Analog Input Channel 2 ACMP2 Analog Comparator 2 Positive Input PCINT21 Pin Change Interrupt 21 14 PD6 Analog Input Channel 3 ACMPN2 Analog Comparator 2 Negative Input INTO External Interrupt O Input PCINT22 Pin Change Interrupt 22 15 PD7 Analog Comparator 0 Positive Input PCINT23 Pin Change Interrupt 23 31 PEO or RESET Reset Input OCD On Chip Debug I O PCINT24 Pin Change Interrupt 24 10 PE1 I O XTAL1 XTAL Input Timer 0 Output Compare PCINT25 Pin Change Interrupt 25 11 PE2 XTAL2 XTAL Output ADCO Analog Input Channel 0 PCINT26 Pin Change Interrupt 26 Note 1 Only for ATmega32 64M1 2 On the first engineering samples Parts marked AT90PWM324 the ACMPN3 alternate func 2 Overview tion is not located on PC4 It is located on 2 The ATmega16 32 6
14. k Branch if Same or Higher if C 0 then PC e PC k 1 None 1 2 BRLO k Branch if Lower if C 1 then PC lt 1 None 1 2 k Branch if Minus if N 1 then PC lt 1 None 1 2 BRPL k Branch if Plus if N 0 then PC 1 None 1 2 k Branch if Greater or Equal Signed if N 6 V 0 then PC e PC k 1 None 1 2 BRLT k Branch if Less Than Zero Signed if N 6 V 1 then PC PC k 1 None 1 2 BRHS k Branch if Half Carry Flag Set if H 1 then PC lt k 1 None 1 2 BRHC k Branch if Half Carry Flag Cleared if H 0 then 1 None 1 2 BRTS k Branch if T Flag Set if T 1 thenPC lt PC k 1 1 2 BRTC k Branch if T Flag Cleared if T 0 then PC lt PC k 1 None 1 2 BRVS k Branch if Overflow Flag is Set if V 1 then lt PC k 1 None 1 2 BRVC k Branch if Overflow Flag is Cleared if V 0 then lt 1 None 1 2 17 AIMEL Mnemonics Operands Description Operation Flags Clocks BRIE k Branch if Interrupt Enabled if I 1 then PC lt PC k 1 None 1 2 BRID k Branch if Interrupt Disabled if 12 0 then PC PC c k 1 None 1 2 BIT AND BIT TEST INSTRUCTIONS SBI P b Set Bit in I O Register VO P b lt 1 None 2 CBI P b Clear Bit in I O Register l O P b lt 0 None LSL Rd Logical Shift Left Rd n 1 lt Rd n Rd 0 lt 0 Z C N V LSR Rd Logical
15. one UART with HW LIN an 11 channel 10 bit ADC with two differential input stages with programmable gain a 10 bit DAC a programmable Watchdog Timer with Internal Individual Oscillator SPI serial port an On chip Debug system and four software selectable power sav AMEL SPI Unit Watchdog Timer 4 Analog Comparators HW LIN UART Timer 0 Direct Addressing Indirect Addressing Timer 1 gt 7647DS AVR 08 08 2 2 2 3 2 3 1 2 3 2 10 AMEL The Idle mode stops the CPU while allowing the SRAM Timer Counters SPI ports CAN LIN UART and interrupt system to continue functioning The Power down mode saves the regis ter contents but freezes the Oscillator disabling all other chip functions until the next interrupt or Hardware Reset The ADC Noise Reduction mode stops the CPU and all I O modules except ADC to minimize switching noise during ADC conversions In Standby mode the Crystal Reso nator Oscillator is running while the rest of the device is sleeping This allows very fast start up combined with low power consumption The device is manufactured using Atmel s high density nonvolatile memory technology The On chip ISP Flash allows the program memory to be reprogrammed in system through an SPI serial interface by a conventional nonvolatile memory programmer or by an On chip Boot program running on the AVR core The boot program can use any interface to download the applicatio
16. 11 T1 RXCAN ICP1B 7 18 PC5 ADC9 ACMP3 AMP1 PCINT13 PCINTO MISO PBO 8 17 1 PC4 ADC8 ACMPN3 AMP1 PCINT12 0 st At eb ort E G G mauua lazagaz3ogm lt lt x 256502226 aXXoooom amp Eonar gS QoxozbZt 5 gt 9 E zr a 6 lt gt a 5 C N 2 9 Note the first engineering samples Parts marked AT9OPWM324 the alternate function is not located on 4 It is located PE2 AMEL s 7647DS AVR 08 08 AMEL 11 Pin Descriptions Table 1 1 Pin out description QFN32 Pin Number Mnemonic Type Name Function amp Alternate Function 5 GND Power Ground OV reference 20 AGND Power Analog Ground OV reference for analog part 4 VCC Power Power Supply Analog Power Supply This is the power supply voltage for analog 19 part For a normal use this pin must be connected Analog Reference reference for analog converter This is the reference voltage of the A D converter As output can be used by external analog ISRC Current Source Output 21 AREF Power MISO SPI Master In Slave Out 8 PBO 2 PSC Module 2 Output A PCINTO Pin Change Interr
17. 2 None 3 LPM Rd Z Load Program Memory and Post Inc lt Z 2 lt 2 1 3 SPM Store Program Memory 2 lt R1 RO Rd lt 1 OUT P Rr Out Port P lt Rr None T PUSH Rr Push Register on Stack STACK lt Rr None 2 16 32 64 1 1 mmm 7647DS AVR 08 08 16 32 64 1 1 7647DS AVR 08 08 Note 1 These Instructions are only available in 16K and 32K parts AMEL Mnemonics Operands Description Operation Flags Clocks POP Rd Pop Register from Stack Rd lt STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep function None 1 WDR Watchdog Reset see specific descr for WDR timer None 1 BREAK Break For On chip Debug Only None N A 19 5 Errata 51 Errata Summary 5 1 1 5 1 2 5 1 3 5 1 4 Errata Description 1 2 3 4 20 ATmega32M1 C1 Rev C Mask Revision AMPCMPXx bits return 0 ATmega32M1 C1 Rev B Mask Revision The AMPCMPx bits return 0 No comparison when amplifier is used as comparator input and ADC input CRC calculation of diagnostic frames in LIN 2 x Wrong TSOFFSET manufacturing calibration value PDO PD3 set to outputs and PD4 pulled down following power on with external reset active ATmega32M1 C1 Rev A Mask Revision Inopportune reset of the CANIDM registe
18. 4 M1 C1 is a low power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture By executing powerful instructions in a single clock cycle the ATmega16 32 64 M1 C1 achieves throughputs approaching 1 MIPS per MHz allowing the sys tem designer to optimize power consumption versus processing speed 8 ATmega16 32 64 M1 C1 mmm 7647DS AVR 08 08 16 32 64 1 1 21 Block Diagram Figure 2 1 Block Diagram Program Flash Program Counter Memory Data Bus 8 bit Interrupt Unit Status and Control 32x8 Instruction General Register Purpose Registrers Instruction Decoder v Control Lines Data SRAM EEPROM DAC Lines PSC The AVR core combines a rich instruction set with 32 general purpose working registers All the 32 registers are directly connected to the Arithmetic Logic Unit ALU allowing two independent registers to be accessed in one single instruction executed in one clock cycle The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con ventional CISC microcontrollers The ATmega16 32 64 M1 C1 provides the following features 16K 32K 64K bytes of In System Programmable Flash with Read While Write capabilities 512 1024 2048 bytes EEPROM 1024 2048 4096 bytes SRAM 27 general purpose lines 32 general purpose working regis ters one Motor Power Stage Controller two flexible Timer Counters with compare modes and PWM
19. BDTIC www bdtic com ATMEL Features High Performance Low Power AVR 8 bit Microcontroller Advanced RISC Architecture 131 Powerful Instructions Most Single Clock Cycle Execution 82 x 8 General Purpose Working Registers Fully Static Operation Up to 1 MIPS throughput per MHz On chip 2 cycle Multiplier Data and Non Volatile Program Memory 16K 32K 64K Bytes Flash of In System Programmable Program Memory Endurance 10 000 Write Erase Cycles Optional Boot Code Section with Independent Lock Bits In System Programming by On chip Boot Program True Read While Write Operation 512 1024 2048 Bytes of In System Programmable EEPROM Endurance 50 000 Write Erase Cycles Programming Lock for Flash Program and EEPROM Data Security 1024 2048 4096 Bytes Internal SRAM On Chip Debug Interface debugWIRE CAN 2 0A B with 6 Message Objects ISO 16845 Certified LIN 2 1 and 1 3 Controller or 8 Bit UART One 12 bit High Speed PSC Power Stage Controller only ATmega16 32 64M1 Non Overlapping Inverted PWM Output Pins With Flexible Dead Time Variable PWM duty Cycle and Frequency Synchronous Update of all PWM Registers Auto Stop Function for Emergency Event Peripheral Features One 8 bit General purpose Timer Counter with Separate Prescaler Compare Mode and Capture Mode One 16 bit General purpose Timer Counter with Separate Prescaler Compare Mode and Capture Mode One Master Slave SPI S
20. CR1SB7 POCR1SB6 POCR1SB5 POCR1SB4 POCR1SB3 POCR1SB2 POCR1SB1 POCR1SBO page 152 0 9 1 POCR 1RA11 POCR1RA10 1 9 POCR1RA8 page 151 0xA8 9 POCR1RAL POCR1RA7 POCR1RA6 POCR1RA5 POCR1RA4 POCR1RA3 POCR1RA2 POCR1RA1 POCR1RAO page 151 0xA7 POCR1SAH POCR1SA11 POCR1SA10 POCR1SA9 POCR1SA8 page 151 0xA6 9 POCR1SAL POCR1SA7 POCR1SA6 POCR1SA5 POCR1SA4 POCR1SA3 POCR1SA2 POCR1SA1 POCR1SA0 page 151 0 5 POCROSBH POCROSB11 POCROSB10 POCROSB9 POCROSB8 page 152 0 4 POCROSBL POCROSB7 POCROSB6 POCROSB5 POCROSB4 POCROSB3 POCROSB2 POCROSB1 POCROSBO page 152 0 POCRORA11 POCRORA10 POCRORAQ POCRORA8 page 151 0 2 POCRORAL POCRORA7 POCRORA6 POCRORA5 POCRORA4 POCRORA3 POCRORA2 POCRORA1 POCRORAO page 151 0 1 POCROSAH POCROSA11 POCROSA10 POCROSA9 POCROSA8 page 151 0 POCROSAL POCROSA7 POCROSA6 POCROSA5 POCROSA4 POCROSA3 POCROSA2 POCROSA1 POCROSAO page 151 Ox9F Reserved Ox9E Reserved Ox9D Reserved Ox9C Reserved 0 9 Reserved Ox9A Reserved 0 99 Reserved 0x98 Reserved 0 97 51 150 2 1 263 0 96 2 2 AC2IE AC2IS1 AC2ISO 2 2 2 1 AC2MO page 263 0x95 AC1CON 1 ACAIE
21. Page OxFF Reserved OxFE Reserved OxFD Reserved Reserved OxFB Reserved 5 MSG 7 MSG 6 MSG 5 MSG 4 MSG 3 MSG 2 MSG 1 MSG 0 page 199 OxF9 CANSTMPH TIMSTM15 TIMSTM14 TIMSTM13 TIMSTM12 TIMSTM11 TIMSTM10 TIMSTM9 TIMSTM8 page 199 OxF8 CANSTMPL TIMSTM7 TIMSTM6 5 5 TIMSTM4 TIMSTM3 TIMSTM2 TIMSTM1 TIMSTMO page 199 OxF7 CANIDM1 IDMSK28 IDMSK27 IDMSK26 IDMSK25 IDMSK24 IDMSK23 IDMSK22 IDMSK21 page 198 OxF6 CANIDM2 IDMSK20 IDMSK19 IDMSK18 IDMSK17 IDMSK16 IDMSK15 IDMSK14 IDMSK13 page 198 OxF5 CANIDM3 IDMSK12 IDMSK11 IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5 page 198 OxF4 CANIDM4 IDMSK4 IDMSK3 IDMSK2 IDMSK1 IDMSKO RTRMSK IDEMSK page 198 OxF3 CANIDT1 IDT28 IDT27 IDT26 IDT25 IDT24 IDT23 IDT22 IDT21 page 196 OxF2 CANIDT2 IDT20 IDT19 IDT18 IDT17 IDT16 IDT15 IDT14 IDT13 page 196 OxF1 CANIDT3 IDT12 IDT11 IDT10 IDT9 IDT8 IDT7 IDT6 1075 196 CANIDT4 1074 IDT3 IDT2 IDT1 IDTO RTRTAG RB1TAG RBOTAG page 196 OxEF CANCDMOB CONMOB1 CONMOBO RPLV IDE DLC3 DLC2 DLC1 DLCO page 195 OxEE CANSTMOB DLCW TXOK RXOK BERR SERR CERR FERR AERR page 194 OxED CANPAGE 2 1 MOBNBO AINC INDX2 INDX1 INDXO page 194 OxEC CANHPMOB 2 1 CGP3 CGP2 CGP1 CGPO page 193 OxEB CANREC REC6 REC5 REC4 REC3 REC2 REC1 RECO page 193 OxEA CANTEC
22. Shift Right Rd n lt Rd n 1 Rd 7 lt 0 Z C N V ROL Rd Rotate Left Through Carry Rd 0 lt C Rd n 1 lt Rd n C lt Rd 7 Z C N V ROR Rd Rotate Right Through Carry Rd 7 lt C Rd n lt Rd n 1 C lt Rd 0 Z C N V ASR Rd Arithmetic Shift Right Rd n lt Rd n 1 0 6 Z C N V SWAP Rd Swap Nibbles Rd 3 0 lt Rd 7 4 Rd 7 4 lt Rd 3 0 None BSET 5 Set SREG s 1 SREG s BCLR 5 Clear SREG s 0 SREG s BST Rr b Bit Store from Register to T T lt Rr b BLD Rd b Bit load from T to Register Rd b T None SEC Set Carry Cel Clear Carry c lt 0 5 Set Negative Nel N CLN Clear Negative Flag N lt O N SEZ Set Zero Flag Zc 1 2 CLZ Clear Zero Flag Z lt 0 2 SEI Global Interrupt Enable 1 1 CLI Global Interrupt Disable 1 0 5 5 Set Signed Test Flag Sc 1 S CLS Clear Signed Test Flag S lt 0 5 SEV Set Twos Complement Overflow Vel V CLV Clear Twos Complement Overflow Vc 0 V SET Set T in SREG Tel Clear T in SREG T lt 0 T SEH Set Half Carry Flag in SREG Hel H CLH Clear Half Carry Flag in SREG lt 0 1 DATA TRANSFER INSTRUCTIONS MOV Rd Rr Move Between Registers lt Rr 1 MOVW Rd Rr Copy Register Word Rd 1 Rd lt Rr 1 Rr None 1 LDI Rd Load Immediate Rd K None 1 LD Rd X Load Indirect Rd lt X None 2 LD Rd L
23. TSOFFSET value check device signature byte at address OX3F if value is not 0X42 Ascii code then use the following formula TS OFFSET True 150 1 5 GAIN TS OFFSET 6 PDO PD3 set to outputs and PD4 pulled down following power on with external reset active At power on with the external reset signal active the four I O lines PDO PD3 be forced into an output state Normally these lines should be in an input state PD4 may be pulled down with internal 220 kOhm resistor Following release of the reset line whatever is the startup time with the clock running the I Os PDO PD4A will adopt their intended input state Problem fix workaround None AMEL 2 7647DS AVR 08 08 AMEL 6 Ordering Information Figure 6 1 ATmega32M1 engineering samples delivery only Automotive qualification not yet fully completed Memory Size PSC Power Supply Ordering Code Package Operation Range 32K No 2 7 5 5V 2 1 15 7 40 C to 125 C 32K No 2 7 5 5V MEGA32C 1 15MZ PV 40 C to 125 C 32K No 2 7 5 5V MEGA32C1 ESAZ MA Engineering Samples 32K No 2 7 5 5V MEGA32C1 ESMZ PV Engineering Samples 32K Yes 2 7 5 5V MEGA32M1 15AZ MA 40 C to 125 C 32K Yes 2 7 5 5V MEGA32M1 15MZ PV 40 C to 125 C 32K Yes 2 7 5 5V MEGA32M1 ESAZ MA Engineering Samples 32K Yes 2 7 5 5V MEGA32M1 ESMZ PV Engineering Samples Note All packages are Pb free fully LHF 22 16 32 64 1
24. containing such status flags The CBI and SBI instructions work with registers 0 00 to Ox1F only 4 When using the specific commands IN and OUT the I O addresses 0x00 Ox3F must be used When addressing Registers as data space using LD and ST instructions 0x20 must be added to these addresses The ATmega16 32 64 M1 C1 is a complex microcontroller with more peripheral units than can be supported within the 64 loca tion reserved Opcode for the IN and OUT instructions For the Extended I O space from 0x60 OxFF SRAM only the ST STS STD and LD LDS LDD instructions can be used 5 These registers are only available on 32 64 1 For other products described in this datasheet these locations are 16 reserved ATmega16 32 64 M1 C1 memm 7647DS AVR 08 08 16 32 64 1 1 4 Instruction Set Summary 7647DS AVR 08 08 Mnemonics Operands Description Operation Flags Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd Rr Add two Registers Rd lt Rr Z C N V H ADC Rd Rr Add with Carry two Registers lt Z C N V H ADIW Rdl K Add Immediate to Word Rdh Rdl lt Rdh Rdl Z C N V S SUB Rd Rr Subtrac
25. d Package QFN Atmel Nantes S A A mL La Chantrerie BP 70602 2 40 44306 Nantes Cedex 3 France PV AMEL 25 7647DS AVR 08 08
26. e 23 0x20 0x40 EEDR EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDRO page 23 Ox1F EECR EERIE EEMWE EEWE EERE page 23 Ox1E Ox3E GPIORO GPIORO7 GPIORO6 GPIORO5 GPIORO4 GPIORO3 GPIORO2 GPIORO1 GPIOROO page 28 Ox1D 0x3D EIMSK 2 INTO page 83 Ox1C Ox3C EIFR 2 1 INTFO page 84 Ox1B Ox3B PCIFR PCIF2 PCIF1 PCIFO page 85 AIMEL 15 7647DS AVR 08 08 EE ATMEL Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 1 0x3A GPIOR2 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 page 28 0x19 0x39 GPIOR1 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 page 28 0x18 0x38 Reserved 0 17 0 37 Reserved 0 16 0 36 TIFR1 ICF1 1 1 134 0 15 0 35 TIFRO OCFOA TOVO page 106 0x14 0x34 Reserved 0 13 0 33 Reserved 0 12 0 32 Reserved 0 11 0 31 Reserved 0 10 0 30 Reserved OxOF Ox2F Reserved OxOE 0 2 PORTE2 PORTE1 PORTEO page 81 0x2D DDRE DDE2 DDE1 DDEO pa
27. erial Interface 10 bit ADC Up To 11 Single Ended Channels and 3 Fully Differential ADC Channel Pairs Programmable Gain 5x 10x 20x 40x on Differential Channels Internal Reference Voltage Direct Power Supply Voltage Measurement 10 bit DAC for Variable Voltage Reference Comparators ADC Four Analog Comparators with Variable Threshold Detection 100pA 3 Current Source LIN Node Identification Interrupt and Wake up on Pin Change Programmable Watchdog Timer with Separate On Chip Oscillator On chipTemperature Sensor Special Microcontroller Features Low Power Idle Noise Reduction and Power Down Modes Power On Reset and Programmable Brown Out Detection In System Programmable via SPI Port High Precision Crystal Oscillator for CAN Operations 16 MHz 1 See certification on Atmel web site And note on Section 16 4 3 on page 175 AMEL 8 bit AVR Microcontroller with 16K 32K 64K Bytes In System Programmable Flash ATmega16M1 ATmega32M1 ATmega64M1 ATmega32C1 ATmega64C1 Automotive Preliminary Summary 7647DS AVR 08 08 16 32 64 1 1 Internal Calibrated RC Oscillator 8 MHz On chip PLL for fast PWM 32 MHz 64 MHz and CPU 16 MHz Operating Voltage 2 7V 5 5V Extended Operating Temperature 40 to 125 Core Speed Grade 0 8MHz Q 2 7 4 5V 0 16MHz 4 5 5 5V ATmega32 64 M1 C1 Product Line up
28. eserved OxD3 Reserved OxD2 LINDAT LDATA7 LDATA6 LDATA5 LDATA4 LDATA3 LDATA2 LDATA1 LDATAO page 226 OxD1 LINSEL LAINC LINDX2 LINDX1 LINDXO page 226 OxDO LINIDR LP1 LPO LID5 LDL1 LID4 LDLO LID3 LID2 LID1 LIDO page 225 OxCF LINDLR LTXDL3 LTXDL2 LTXDL1 LTXDLO LRXDL3 LRXDL2 LRXDL1 LRXDLO page 224 OxCE LINBRRH LDIV11 LDIV10 LDIV9 LDIV8 page 224 OxCD LINBRRL LDIV7 LDIV6 LDIV5 LDIV4 LDIV3 LDIV2 LDIV1 LDIVO page 224 OxCC LINBTR LDISR 5 LBT4 LBT3 LBT2 LBT1 LBTO page 224 OxCB LINERR LABORT LTOERR LOVERR LFERR LSERR LPERR LCERR LBERR page 223 OxCA LINENIR LENERR LENIDOK LENTXOK LENRXOK page 222 OxC9 LINSIR LIDST2 LIDST1 LIDSTO LBUSY LERR LIDOK LTXOK LRXOK page 221 OxC8 LINCR LSWRES LIN13 LCONF1 LCONFO LENA LCMD2 LCMD1 LCMDO page 220 OxC7 Reserved OxC6 Reserved OxC5 Reserved OxC4 Reserved OxC3 Reserved OxC2 Reserved OxC1 Reserved 0 0 Reserved OxBF Reserved 7647DS AVR 08 08 13 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page Reserved
29. externally pulled low will source current if the pull up resistors are activated The Port D pins are tri stated when a reset condition becomes active even if the clock is not running Port D also serves the functions of various special features of the ATmega16 32 64 M1 C1 as listed on page 75 2 3 6 Port E PE2 0 RESET XTAL1 XTAL2 7647DS AVR 08 08 Port E is an 3 bit bi directional I O port with internal pull up resistors selected for each bit The Port E output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port E pins that are externally pulled low will source current if the pull up resistors are activated The Port E pins are tri stated when a reset condition becomes active even if the clock is not running If the RSTDISBL Fuse is programmed PEO is used as an pin Note that the electrical char acteristics of PEO differ from those of the other pins of Port E If the RSTDISBL Fuse is unprogrammed PEO is used as a Reset input A low level on this pin for longer than the minimum pulse length will generate a Reset even if the clock is not running The minimum pulse length is given in Table 7 1 on page 46 Shorter pulses are not guaranteed to generate a Reset Depending on the clock selection fuse settings PE1 can be used as input to the inverting Oscil lator amplifier and input to the internal clock operating circuit Depending on the clock selection fuse settings
30. ge 81 OxOC 0x2C PINE PINE1 PINEO page 81 0x2B PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTDO page 80 0x2A DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDDO page 80 0 09 0x29 PIND PIND7 PIND6 PINDS PIND4 PIND3 PIND2 PIND1 PINDO page 81 0x08 0x28 PORTC PORTC7 PORTC6 5 PORTC4 PORTC3 PORTC2 PORTC1 PORTCO page 80 0x07 0x27 DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDCO page 80 0x06 0x26 PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINCO page 80 0x05 0x25 PORTB PORTB7 PORTB6 5 PORTBA PORTB2 PORTB1 PORTBO page 80 0 04 0x24 DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDBO page 80 0x03 0x23 PINB PINB7 PINB6 5 4 2 1 PINBO page 80 0x02 0x22 Reserved 0x01 0x21 Reserved 0 00 0 20 Reserved Note 1 For compatibility with future devices reserved bits should be written to zero if accessed Reserved I O memory addresses should never be written 2 Registers within the address range 0x00 Ox1F are directly bit accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SBIS and SBIC instructions 3 Some of the status flags are cleared by writing a logical one to them Note that unlike most other AVRs the and SBI instructions will only operate on the specified bit and can therefore be used on registers
31. n program in the application Flash memory Software in the Boot Flash section will continue to run while the Application Flash section is updated providing true Read While Write operation By combining an 8 bit RISC CPU with In System Self Programmable Flash on a monolithic chip the Atmel ATmega16 32 64 M1 C1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications The ATmega16 32 64 M1 C1 AVR is supported with a full suite of program and system develop ment tools including C compilers macro assemblers program debugger simulators in circuit emulators and evaluation kits Automotive Quality Grade The ATmega16 32 64 M1 C1 have been developed and manufactured according to the most stringent requirements of the international standard ISO TS 16949 This data sheet contains limit values extracted from the results of extensive characterization Temperature and Voltage The quality and reliability of the ATmega16 32 64 M1 C1 have been verified during regular prod uct qualification as per AEC Q100 grade 1 As indicated in the ordering information paragraph the products are available in only one tem perature grade Table 2 1 Temperature Grade Identification for Automotive Products Temperature Temperature Comments Identifier 40 125 Z Full AutomotiveTemperature Range Pin Descriptions GND Digital supply voltage Ground ATmega16 32 64 M1
32. oad Indirect and Post Inc Rd X Xc X 1 None 2 LD Rd X Load Indirect and Pre Dec X 1 Rd lt X None 2 LD Rd Y Load Indirect Rd lt Y None 2 LD Rd Y Load Indirect and Post Inc Rd Y Ye Y 1 None 2 LD Rd Y Load Indirect and Pre Dec Y 4 Rd lt Y None 2 LDD Rd Y q Load Indirect with Displacement lt Y 2 LD Rd Z Load Indirect Rd lt 2 None 2 LD Rd Z Load Indirect and Post Inc lt Z Z lt 2 1 2 LD Rd Z Load Indirect and Pre Dec Z Z 1 Rd lt 2 2 LDD Rd Z q Load Indirect with Displacement Rd lt Z q None 2 LDS Rd Load Direct from SRAM Rd lt k None 2 ST X Rr Store Indirect X Rr None 2 ST X Rr Store Indirect and Post Inc Ry 1 None 2 ST Rr Store Indirect and Pre Dec X lt X 1 X lt Rr None 2 ST Y Rr Store Indirect Y Rr None 2 ST Rr Store Indirect and Post Inc lt lt 1 2 ST Rr Store Indirect and Pre Dec Y lt Y 1 Y lt Rr None 2 STD Y q Rr Store Indirect with Displacement Y q lt Rr None 2 ST Z Rr Store Indirect 2 lt Rr None 2 ST 7 Rr Store Indirect and Post Inc 2 2 lt 2 1 2 ST Z Rr Store Indirect and Pre Dec Z lt lt Z 1 Z lt Rr None 2 STD Z q Rr Store Indirect with Displacement 2 9 lt Rr 2 STS k Rr Store Direct to SRAM lt Rr None 2 LPM Load Program Memory RO lt Z None 3 LPM Rd Z Load Program Memory Rd lt
33. rs The AMPCMPx bits return 0 No comparison when amplifier is used as comparator input and ADC input CRC calculation of diagnostic frames in LIN 2 x PDO PD3 set to outputs and PD4 pulled down following power on with external reset active Inopportune reset of the CANIDM registers After the reception of a CAN frame in a MOb the ID mask registers are reset Problem fix workaround Before enabling a MOb in reception re initialize the ID mask registers CANIDM A 1 The bits return 0 When they are read the AMPCMPx bits in AMPxCSR registers return 0 Problem fix workaround If the reading of the bits is required store the AMPCMPx value a variable in memory before writing in the AMPxCSR register and read the variable when necessary No comparison when amplifier is used as comparator input and ADC input When it is selected as ADC input an amplifier receives no clock signal when the ADC is stopped In that case if the amplifier is also used as comparator input no analog signal is propagated and no comparison is done Problem fix workaround Select another ADC channel rather than the working amplified channel CRC calculation of diagnostic frames in LIN 2 x Diagnostic frames of LIN 2 x use classic checksum calculation Unfortunately the setting of the checksum model is enabled when the HEADER is transmitted received Usually in LIN 2 x the LIN UART controller is initialized to proce
34. ss enhanced checksums and a slave task does not know what kind of frame it will work on before checking the ID Problem fix workaround This workaround is to be implemented only in case of transmission reception of diagnostics frames ATmega16 32 64 M1 C1 memm 7647DS AVR 08 08 AT Ne 21 6 32 64 M1 C1 a Slave task of master node Before enabling the HEADER the master must set the appropriate LIN13 bit value in LINCR register b For slaves nodes the workaround is in 2 parts Before enabling the RESPONSE use the following function void lin_wa_head void unsigned char temp temp LINBTR LINCR 0x00 It is not a RESET LINBTR 1 lt lt LDISR temp LINCR 1 lt lt LIN13 1 lt lt LENA 0 LCMD2 0 lt lt LCMD1 0 lt lt LCMDO LINDLR 0x88 it isn t already done Once the RESPONSE is received or sent having RxOK or TxOK as well as LERR use the following function void lin wa tail void 1 LINCR 0x00 It is not a RESET LINBTR 0x00 LINCR 0 lt lt LIN13 1 lt lt LENA 0 LCMD2 0 lt lt LCMD1 0 lt lt LCMDO The time out counter is disabled during the RESPONSE when the workaround is set 5 Wrong TSOFFSET manufacturing calibration value Erroneous value of TSOFFSET programmed in signature byte TSOFFSET was introduced from REVB silicon Problem fix workaround To identify RevB with wrong
35. t two Registers Rd Rd Rr Z C N V H SUBI Rd K Subtract Constant from Register lt Rd K Z C N V H SBC Rd Rr Subtract with Carry two Registers Rd lt Rd Rr C Z C N V H SBCI Subtract with Carry Constant from Reg lt Rd K C Z C N V H SBIW Rdl K Subtract Immediate from Word Rdh Rdl lt Rdh Rdl Z C N V S AND Rd Rr Logical AND Registers lt Rr Z N V ANDI Rd K Logical AND Register and Constant Rd lt Z N V OR Rd Rr Logical OR Registers lt Rr Z N V ORI Rd K Logical OR Register and Constant RdvK Z N V EOR Rd Rr Exclusive OR Registers Rd lt Rd Rr Z N V COM Rd One s Complement lt OxFF Rd Z C N V NEG Rd Two s Complement lt 0x00 Rd Z C N V H SBR Rd K Set Bit s in Register Rd RdvK Z N V CBR Rd K Clear Bit s in Register Rd lt Rd e OxFF K Z N V INC Rd Increment lt 1 Z N V DEC Rd Decrement lt 1 Z N V TST Rd Test for Zero or Minus lt e Rd Z N V 1 CLR Rd Clear Register Rd lt Rd 6 Rd Z N V 1 SER Rd Set Register Rd lt OxFF None t MUL Rd Rr Multiply Unsigned R1 RO lt Rd x Rr 2 2 MULS Rd Rr Multiply Signed R1 RO lt Rd x Rr ZC 2 MULSU Rd Rr Multiply Signed with Unsigned R1 RO lt Rd x Rr Z C 2 FMUL Rd Rr Fractional Multiply Unsigned R1 RO lt Rd x Rr lt lt 1 ZC 2 FMULS Rd Rr Fractional Multiply Signed R1 RO lt Rd x Rr lt lt 1 Z C 2 FMULSU Rd Rr Fractional Multiply Signed
36. upt O MOSI SPI Master Out Slave In 9 PB1 PSCOUT2B PSC Module 2 Output B PCINT1 Pin Change Interrupt 1 ADC5 Analog Input Channel 5 INT1 External Interrupt 1 Input 16 PB2 Analog Comparator 0 Negative Input PCINT2 Pin Change Interrupt 2 Analog Differential Amplifier 0 Negative Input 23 PB3 Pin Change Interrupt 3 Analog Differential Amplifier O Positive Input 24 4 PCINT4 Pin Change Interrupt 4 ADC6 Analog Input Channel 6 INT2 External Interrupt 2 Input 26 PB5 VO 1 Analog Comparator 1 Negative Input AMP2 Analog Differential Amplifier 2 Negative Input PCINTS5 Pin Change Interrupt 5 ADC7 Analog Input Channel 7 27 PB6 PSCOUT1B PSC Module 1 Output A 6 Pin Change Interrupt 6 ADCA Analog Input Channel 4 PSCOUTOB PSC Module 0 Output B SCK SPI Clock PCINT7 Pin Change Interrupt 7 28 PB7 PSC Module 1 Output A 30 PCO External Interrupt 3 Input PCINTS8 Pin Change Interrupt 8 6 ATmega16 32 64 M1 C1 memm 7647DS AVR 08 08 AT Ne 21 6 32 64 M1 C1 Table 1 1 Pin out description Continued QFN32 Pin Number Mnemonic Type Name Function amp Alternate Function PSCIN1 PSC Digital Input 1 OC1B Timer 1 Output Compare 3 PC1 SS A Alternate SPI Slave Select
37. with Unsigned R1 RO lt Rd x Rr 1 Z C 2 BRANCH INSTRUCTIONS RJMP k Relative Jump PC lt PC k 1 None 2 Indirect Jump to 2 Z None 2 JMP Direct Jump lt 3 RCALL Relative Subroutine Call lt 1 None 3 ICALL Indirect Call to Z PC lt Z None 3 CALL k Direct Subroutine Call lt 4 Subroutine Return lt STACK None 4 RETI Interrupt Return PC lt STACK 1 4 5 Compare Skip if Equal if Rd Rr PC e PC 20r3 None 1 2 3 Rd Rr Compare Rr 2 N V C H d CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Compare Register with Immediate Rd K Z N V C H 1 5 Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 20r 3 None 1 2 3 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 20r 3 None 1 2 3 SBIC P b Skip if Bit in Register Cleared if P b 0 PC lt PC 20r3 None 1 2 3 5 5 P b Skip if Bit Register is Set if P b 1 lt PC 20r 3 None 1 2 3 BRBS 5 Branch if Status Flag Set if SREG s 1 then PC lt PC k 1 None 1 2 BRBC 5 Branch if Status Cleared if SREG s 0 then PC lt PC k 1 None 1 2 k Branch if Equal if Z 1 then PC lt 1 None 1 2 BRNE k Branch if Not Equal if Z 0 then PC lt PC k 1 None 1 2 BRCS k Branch if Carry Set if C 1 then PC lt 1 None 1 2 BRCC k Branch if Carry Cleared if C 0 then PC k 1 None 1 2 BRSH
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