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ATMEL AVR microcontroller ATmega169P handbook data (1)

1. 47 9 1 Resettinig the AVR e M 47 9 2 Hieset SOURCES rete ecd dead te Gurt inira rd deb Fidi es au rgo ua ddp d nea 47 9 3 Internal Voltage Reference 51 9 4 Watchdog Timer 51 9 5 Register DescriptlOD ticus 54 10 en 56 10 1 Interrupt Vectors ATmega169P sess 56 10 2 Moving Interrupts Between Application and Boot Space 59 11 External Interr ptS S 61 11 1 Pin Change Interrupt 61 11 2 Register Description t R 62 12 1 E 65 12 1 65 12 2 Ports as General Digital 66 12 3 Alternate Port Funcions 2 etre ecc to Rege eee inde 71 12 4 Register Description for 88 13 8 bit Timer CounterO With PWM 91 13 1 Features 91 eus m M Pe 91 13 3 Timer Counter Clock Sour
2. 168 18 3 Clock Generation rie ree eA ee 170 18 4 Frame 173 18 5 USART Initialization 4 eene nennen nnns 175 18 6 Data Transmission The USART Transmitter 177 18 7 Data Reception The USART Receiver 180 18 8 Asynchronous Data Reception 185 18 9 Multi processor Communication Mode 2 188 18 10 USART Register Description 0 420404440 00 190 18 11 Examples of Baud Rate Setting 195 19 USI Universal Serial Interface es reeseesees 199 191 OVGWIOW E 199 19 2 Functional Descriptions 200 19 3 Alternative USI Usage 206 19 4 USI Register Descriptions 207 20 Analog 211 20 1 Analog Comparator Multiplexed Input 212 20 2 Analog Comparator Register Description 213 21 ADC Analog to Digital Converter serere eere nennen 215 21 1 LIUC 215 rape ETE 215 21 3 T 216 21 4 Starting a Conversion
3. 135 15 1 Prescaler Reset memet Ene Pei opt edet 135 15 2 Internal Clock 135 15 3 External Clock Source ie tdeo ette 135 15 4 Register Description E OE Coen 137 16 8 bit Timer Counter2 with PWM and Asynchronous Operation 138 16 1 OVOrVIOW ret et b iet EE 138 16 2 Timer Counter Clock Sources sse 139 16 3 Counter Unit E 139 16 4 Output Compare Unit citet ttt a te 140 16 5 Compare Match Output Unit 1 eene nennen nenne 142 16 6 Modes of Operation 143 16 7 Timer Counter Timing Diagrams sse 148 16 8 Asynchronous operation of the Timer Counter 150 16 9 Timer Counter Prescaler 22 024 4 0 000 enne nnne 152 16 10 8 bit Timer Counter Register Description 2 400 153 17 SPI Serial Peripheral Interface 2 2 2 suus 158 7735 07 07 wer 158 SEO UI S 158 163 17 4 Data MOd6S 164 17 5 Register Description eee Eton rc 165 USART c H MM 168 18 1 Features 168 18 2 OVE W
4. Leading Edge Trailing eDge SPI Mode CPOL 0 CPHA 0 Sample Rising Setup Falling 0 CPOL 0 1 Setup Rising Sample Falling 1 CPOL 1 CPHA 0 Sample Falling Setup Rising 2 CPOL 1 CPHA 1 Setup Falling Sample Rising 3 Figure 17 3 SPI Transfer Format with CPHA 0 SCK CPOL 0 L L L mode 0 LJ A LE LPL MOSI MISO worm A K H MSB first DORD 0 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB LSB first DORD 1 LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Figure 17 4 SPI Transfer Format with CPHA 1 se SLL mee LE LIL LU UL CHANGE 0 MOSI PIN SS MSB first DORD 0 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB LSB first DORD 1 LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB 1 4 169 Automotive 7735B AVR 12 07 es A 169 Automotive 17 5 Register Description 17 5 1 SPCR SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C 0x4C SPIE DORD MSTR CPOL CPHA SPRI SPRO SPCR Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set Bit6 SPE SPI Enable When t
5. 2 7 5 5 4 5 5 5 Symbol Parameter Min Max Min Max Units Oscillator Frequency 0 8 0 16 MHz Clock Period 125 62 5 ns 7 High Time 50 25 ns Low Time 50 25 ns Rise Time 1 6 0 5 us tcuc 7 Fall Time 1 6 0 5 us Change in period from one clock cycle to the 2 2 1 Values indicated represent typical data from design simulation 27 5 System and Reset Characteristics Table 27 3 Reset Brown out Internal Voltage Characteristics Symbol Parameter Condition Min Typ Max Units Vast RESET Pin Threshold Voltage Vcc23V 0 2 Voc 0 9 Voc V Minimum pulse width on RESET RST pim Vec 2 5 us Vuyst Brown out Detector Hysteresis 50 mV t Min Pulse Width on Brown out 2 BOD Reset H Voc 2 7V V Bandgap reference voltage Pu 1 0 1 1 1 2 V BG ais Ta 25 C Bandgap reference start up time ec 40 70 us AT Bandgap reference current Vec 2 7V 15 A BG consumption T 25 C H Notes 1 Values indicated represent typical data from design simulation 2 The Power on Reset will not work unless the supply voltage has been below falling Table 27 4 BODLEVEL Fuse Coding BODLEVEL 2 0 Fuses Min Units 111 BOD Disabled 110 Reserved zs 169 Automotive sue 7735B AVR 12 07 169
6. COMO COM1 5 2 169 SEO 46 Display Number of common terminals Number of segment terminals Bias system Drive system Operating voltage ATMEL 7735B AVR 12 07 SEG2 2t 2g SEG1 2c 2d 2e SEGO 1b 1c 2a 2b COMO COM COM2 Connection table TN Positive Reflective 3 21 1 3 Bias 1 3 Duty 3 0 0 3 V 239 22 4 2 240 AMEL Assembly Code Example LCD Init Use 32 kHz crystal oscillator 1 3 Bias and 1 3 duty SEG21 SEG24 is used as port pins ldi r16 1 LCDCS 1 lt lt LCDMUX1 1 LCDPM2 sts LCDCRB r16 Using 16 as prescaler selection and 7 as LCD Clock Divide gives a frame rate of 49 Hz ldi 16 1 LCDCD2 1 lt lt LCDCD1 sts LCDFRR r16 Set segment drive time to 125 Us and output voltage to 3 3 V ldi r16 1 LCDDC1 i LCDCC3 i LCDCC2 1 lt lt LCDCC1 sts LCDCCR r16 Enable LCD default waveform and no interrupt enabled ldi 16 1 LCDEN sts LCDCRA r16 ret C Code Example Void LCD Init void Use 32 kHz crystal oscillator 1 3 Bias and 1 3 duty SEG21 SEG24 is used as port pins LCDCRB 1 lt lt LCDCS 1 lt lt LCDMUX1 1 lt lt LCDPM2 Using 16 as prescaler selection and 7 as LCD Clock Divide gives a
7. MUX DECODER CHANNEL SELECTION INTERNAL REFERENCE BANDGAP REFERENCE LH ADC6 LH POS ADCS INPUT MUX ADC4 ADC3 ADC2 SINGLE ENDED DIFFERENTIAL SELECTION Y DIFFERENTIAL AMPLIFIER ADC MULTIPLEXER OUTPUT ADC1 ADCO 2 NEG INPUT MUX La The ADC converts an analog input voltage to a 10 bit digital value through successive approxi mation The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB Optionally AVCC or an internal 1 1V reference voltage may be con nected to the AREF pin by writing to the REFSn bits in the ADMUX Register The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity The analog input channel is selected by writing to the MUX bits in ADMUX Any of the ADC input pins as well as GND and a fixed bandgap voltage reference can be selected as single ended inputs to the ADC The ADC is enabled by setting the ADC Enable bit ADEN in ADCSRA Volt age reference and input channel selections will not go into effect until ADEN is set The ADC does not consume power when ADEN is cleared so it is recommended to switch off the ADC before entering power saving sleep modes The ADC generates a 10 bit result which is presented in the ADC Data Registers ADCH and
8. 1 SPI INTERRUPT INTERNAL REQUEST DATA BUS Note 1 Referto Figure 1 1 on page 2 and Table 12 6 on page 74 for SPI pin placement 18 169 Automotive memm 7735B AVR 12 07 A 169 Automotive 7735B AVR 12 07 The interconnection between Master and Slave CPUs with SPI is shown in Figure 17 2 The sys tem consists of two shift Registers and a Master clock generator The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave Master and Slave prepare the data to be sent in their respective shift Registers and the Master generates the required clock pulses on the SCK line to interchange data Data is always shifted from Mas ter to Slave on the Master Out Slave In MOSI line and from Slave to Master on the Master In Slave Out MISO line After each data packet the Master will synchronize the Slave by pulling high the Slave Select SS line When configured as a Master the SPI interface has no automatic control of the SS line This must be handled by user software before communication can start When this is done writing a byte to the SPI Data Register starts the SPI clock generator and the hardware shifts the eight bits into the Slave After shifting one byte the SPI clock generator stops setting the end of Transmission Flag SPIF If the SPI Interrupt Enable bit SPIE in the SPCR Register is set an interrupt is re
9. 169 Automotive Table 24 5 169 Boundary scan Order Continued Bit Number Signal Name Module 96 EXTCLK XTAL1 95 OSCCK Clock input and Oscillators for the main clock 94 RCCK Observe only 93 OSC32CK 92 PDO Data 91 PDO Control 90 PDO Pull up Enable 89 PD1 Data 88 PD1 Control 87 PD1 Pull up Enable 86 PD2 Data 85 PD2 Control 84 PD2 Pull up Enable 83 PD3 Data 82 PD3 Control 81 PD3 Pull up Enable 80 PD4 Data 79 PD4 Control 78 PD4 Pull up_Enable 77 PD5 Data 76 PD5 Control 75 PD5 Pull up Enable 74 PD6 Data 73 PD6 Control 72 PD6 Pull up Enable 71 PD7 Data 70 PD7 Control 69 PD7 Pul up Enable 68 PGO Data 67 PGO Control 66 PGO Pull up Enable 65 PG1 Data iu 64 PG1 Control 63 PG1 Pull up Enable 62 PCO Data 61 PCO Control AIMEL 273 7735B AVR 12 07 AMEL Table 24 5 ATmega169P Boundary scan Order Continued Bit Number Signal Name Module 60 PCO Pull up Enable 59 PC1 Data 58 PC1 Control 57 PC1 Pull up Enable 56 PC2 Data 55 PC2 Control 54 PC2 Pull up Enable 53 PC3 Data 52 PC3 Control 51 PC3 Pull up Enable 50 PC4 Data 49 PC4 Control 48 PC4 Pull up_Enable 47 PC5 Data 46 PC5 Control 45 PC5 Pull u
10. 86 169 Automotive m 7735B AVR 12 07 es 169 Automotive Table 12 23 Overriding Signals for Alternate Functions in PG3 0 Signal Name PG3 T1 SEG24 PG2 SEG4 PG1 SEG13 PGO SEG14 LCDEN LCDEN PUOE LCDPM gt 6 LCDEN LCDPM gt 0 LCDEN LCDPM gt 0 PUOV 0 0 0 0 LCDEN LCDEN DDOE LCDPMs6 LCDEN LCDPM 0 LCDEN LCDPM gt 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE LCDEN LCDEN DIEOE LCDPMs6 LCDEN LCDPMs0 LCDEN LCDPM gt 0 DIEOV 0 0 0 0 DI T1 INPUT AIO SEG24 SEG4 SEG13 SEG14 7735B AVR 12 07 AMEL 87 AMEL 12 4 Register Description for 12 4 1 12 4 2 12 4 3 12 4 4 12 4 5 12 4 6 12 4 7 88 MCUCR MCU Control Register Bit 7 6 5 4 3 2 1 0 T SEL GE Read Write R W R R R W R R R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 4 PUD Pull up Disable When this bit is written to one the pull ups in the I O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull ups DDxn PORTxn 0b01 See Con figuring the Pin on page 66 for more details about this feature PORTA Port A Data Register Bit 7 6 5 4 3 2 1 0 0x02 0x22 PORTAO PORTA Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 DDRA Port A Data Direction Register Bit
11. TIMER COUNTER2 CLOCK SOURCE The clock source for Timer Counter2 is named is by default connected to the system I O clock By setting the 52 bit in ASSR Timer Counter2 is asynchronously clocked from the TOSC1 pin This enables use of Timer Counter2 as a Real Time Counter RTC When AS2 is set pins TOSC1 and TOSC2 are disconnected from Port C A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer Counter2 The Oscillator is optimized for use with a 32 768 kHz crystal If applying an external clock on TOSC1 the EXCLK bit in ASSR must be set For Timer Counter2 the possible prescaled selections are 5 8 clKky55 32 64 25 128 256 and 1024 Additionally as well as 0 stop may be selected Setting the PSR2 bit in GTCCR resets the prescaler This allows the user to operate with a pre dictable prescaler 5 169 Automotive memm 7735B AVR 12 07 es 169 Automotive 16 10 8 bit Timer Counter Register Description 16 10 1 TCCR2A Timer Counter Control Register A Bit 7 6 5 4 3 2 5 Ww R W R W W 0 1 S21 Read Write R W R R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 FOC2A Force Output Compare The FOC2A bit is only active when the WGM bits specify a non PWM mode However for
12. 0x66 OSCCAL Oscillator Calibration Register 38 0x65 Reserved 0 64 PRR PRLCD PRTIM1 PRSPI PRUSARTO PRADC 45 0x63 Reserved 0 62 Reserved 0x61 CLKPR CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPSO 38 0x60 WDTCR WDCE WDE WDP2 WDP1 WDPO 54 Ox3F 0 5 SREG T H S V N 2 13 Ox3E 0 5 SPH 10 SP9 SP8 15 0x3D 0x5D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO 15 0 3 0x5C Reserved Ox3B 0x5B Reserved Ox3A 0x5A Reserved 0x39 0x59 Reserved 0x38 0x58 Reserved 0x37 0x57 SPMCSR SPMIE RWWSB RWWSRE BLBSET PGWRT PGERS SPMEN 291 0x36 0x56 Reserved 0x35 0x55 MCUCR JTD PUD IVSEL IVCE 60 88 276 0x34 0x54 MCUSR JTRF WDRF BORF EXTRF PORF 276 0x33 0x53 SMCR SM2 SM1 SMO SE 45 0x32 0x52 Reserved 0x31 0x51 OCDR IDRD OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDRO 255 0x30 0x50 ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACISO 213 Ox2F Ox4F Reserved Ox2E 0x4E SPDR SPI Data Register 167 Ox2D 0x4D SPSR SPIF WCOL SPI2X 166 0 2 0x4C SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPRO 165 Ox2B 0x4B GPIOR2 General Purpose I O Register 2 29 Ox2A 0x4A GPIOR1 General Purpose I O Register 1 29 0x29 0x49 Reserved 0x28 0x48 Reserved 0 27 0 47 OCROA Timer CounterO Output Compare Register 104 0x26 0x46 TCNTO Timer Counter0 8 Bit 104
13. and tx px also apply to read ing operation Table 26 13 Parallel Programming Characteristics 5V 10 9 Symbol Parameter Min Typ Max Units Vpp Programming Enable Voltage 11 5 12 5 V Ipp Programming Enable Current 250 1 Data and Control Valid before XTAL1 High 67 ns ta xn XTAL1 Low to XTAL1 High 200 ns XTAL1 Pulse Width High 150 ns txLDX Data and Control Hold after XTAL1 Low 67 ns baw XTAL1 Low to WR Low 0 ns 36 169 Automotive sue 7735B AVR 12 07 169 Automotive Table 26 13 Parallel Programming Characteristics Voc 5V 10 9 Continued Symbol Parameter Min Typ Max Units txLPH XTAL1 Low to PAGEL high 0 ns PAGEL low XTAL1 high 150 ns 1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tpLBX BS1 Hold after PAGEL Low 67 ns twi Bx BS2 1 Hold after WR Low 67 ns tPLwL PAGEL Low to WR Low 67 ns tavwL BS1 Valid to WR Low 67 ns WR Pulse Width Low 150 ns tWLAL WR Low to RDY BSY Low 0 1 us tue WR Low to RDY BSY High 3 7 4 5 ms WR Low to RDY BSY High for Chip Erase 7 5 9 ms txLoL XTAL1 Low to OE Low 0 ns tsvov BS1 Valid to DATA valid 0 250 ns OE Low to DATA Valid 250 ns toupz OE High to DATA Tri stated 250 ns Notes 1 tw Rnis valid for the Write Flash Write
14. sse nennen nnne 217 21 5 Prescaling and Conversion Timing essen 218 21 6 Changing Channel or Reference Selection 2 220 21 7 ADG Noise Cancelet ner tette ce 221 21 8 ADC Conversion Result 4 226 21 9 ADC Register Description eee nennen 227 4 169 Automotive m nenn 7735 07 07 es 169 Automotive 22 LCD CONTONE oaeee 232 PAIS 232 TE 232 22 3 Mode of Operation 235 22 4 0 08 terr 239 22 5 LCD Register Description 2 022 243 23 JTAG Interface and On chip Debug System 249 PAMELA 249 23 2 Test Access POFLE once tene eet vad eu 250 23 3 TAP Gohtroller om cette entree i 252 23 4 Using the Boundary scan Chain sse 253 23 5 Using the On chip Debug System sse 253 23 6 On chip Debug Specific JTAG Instructions 254 23 7 On chip Debug Related Register Memory 255 23 8 Using the JTAG Programming Capabilities 255 23 9 Bibliographiy
15. 169 Automotive m 7735B AVR 12 07 X 169 Automotive 7735B AVR 12 07 Figure 25 1 Read While Write vs No Read While Write Read While Write RWW Section Z pointer Addresses NRWW Z pointer Section Addresses RWW Section No Read While Write NRWW Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation AMEL 279 AIMEL T O Figure 25 2 Memory Sections Program Memory Program Memory BOOTSZ 11 BOOTSZ 10 0 0000 0 0000 5 5 8 2 Application Flash Section 2 Application Flash Section a 5 End RWW 5 End RWW 3 Start NRWW 9 Start NRWW 2 2 End Application End Application Start Boot Loader 8 Boot Loader Flash Section Start Boot Loader 8 a Flashend a Flashend o o z 2 BOOTSZ 01 BOOTSZ 00 0 0000 0 0000 9 5 9 o 2 Application Flash Section 2 Application Flash Section 2 2 o 52 5 c o rs 5 End RWW 5 End RWW End Application 5 Start NRWW 8 Start NRWW Start Boot Loader 8 8 5 End Application z Start Boot Loader 2 Boot Loader Flash Section Boot Loader Flash Section c Flashend c Flashend o o 2 2 Note 1 The parameters the figure above are given Table 25 6 on p
16. 169 Automotive m n 7735B AVR 12 07 es 169 Automotive Table 24 3 Boundary scan Signals for the ADC Continued Direction Recommen Output Values when as Seen ded Input Recommended Inputs Signal from the when not are Used and CPU is Name ADC Description in Use not Using the ADC Sample amp Hold signal Sample analog signal when low Hold signal HOLD Input when high If differential 1 1 amplifier is used this signal must go active when ACLK is high Enables Band gap IREFEN Input reference as AREF 0 0 signal to DAC MUXEN_7 Input Input Mux bit 7 0 0 MUXEN_6 Input Input Mux bit 6 0 0 MUXEN_5 Input Input Mux bit 5 0 0 MUXEN_4 Input Input Mux bit 4 0 0 MUXEN_3 Input Input Mux bit 3 0 0 MUXEN_2 Input Input Mux bit 2 0 0 MUXEN_1 Input Input Mux bit 1 0 0 MUXEN 0 Input Input Mux bit O 1 1 Input Mux for negative NEGSEL 2 Input input for differential 0 0 signal bit 2 Input Mux for negative NEGSEL 1 Input input for differential 0 0 signal bit 1 Input Mux for negative NEGSEL 0 Input input for differential 0 0 signal bit 0 Enable pass gate of PASSEN Input differential amplifier Input Precharge output latch of 1 1 comparator Active low Switch cap TEST enable Output from SCTEST Input differential amplifier is 0 0 sent out to Port Pin having ADC 4 Output of differential amplifier will settle faster ST Input
17. 70 PD gt Programming Enable ClockDR amp PROG_ENABLE TDO 26 9 10 Programming Command Register 7735B AVR 12 07 The Programming Command Register is a 15 bit register This register is used to serially shift in programming commands and to serially shift out the result of the previous command if any The JTAG Programming Instruction Set is shown in Table 26 17 The state sequence when shifting in the programming commands is illustrated in Figure 26 16 A MEL 315 AMEL Figure 26 15 Programming Command Register TDI 5 T R B E 5 Flash EEPROM Lock Bits R 5 5 D A T A TDO 169 Automotive m N 7735B AVR 12 07 es 169 Automotive Table 26 17 JTAG Programming Instruction Set address high bits b address low bits 0 Low byte 1 High Byte data out i data in x don t care 4a Enter EEPROM Write 0100011_00010001 XXXXXXX_XXXXXXXX Instruction TDI Sequence TDO Sequence Notes 0100011_ 10000000 XXXXXXX_XXXXXXXX 1a Chip Erase 0110001 10000000 XXXXXXX_XXXXXXXX P 0110011 10000000 XXXXXXX_XXXXXXXX 0110011 10000000 XXXXXXX_XXXXXXXX 1b Poll for Chip Erase Complete 0110011_ 10000000 XXXXXOX_XXXXXXXX 2 2a Enter Flash Write 0100011 00010000 XXXXXXX_XXXXXXXX 2b Load Address High Byte 0000
18. clkzy can be generated from an external or internal clock source selected by the Clock Select bits CS02 0 When no clock source is selected CS02 0 0 the timer is stopped However the TCNTO value can be accessed by the CPU regardless of whether clky is present or not CPU write overrides has priority over all counter clear or count operations The counting sequence is determined by the setting of the WGM01 and WGMOO bits located in the Timer Counter Control Register TCCROA There are close connections between how the counter behaves counts and how waveforms are generated on the Output Compare output OCOA For more details about advanced counting sequences and waveform generation see Modes of Operation on page 96 The Timer Counter Overflow Flag TOVO is set according to the mode of operation selected by the WGM01 0 bits TOVO can be used for generating CPU interrupt 13 5 Output Compare Unit The 8 bit comparator continuously compares TCNTO with the Output Compare Register OCROA Whenever TCNTO equals OCROA the comparator signals a match A match will set the Output Compare Flag OCFOA at the next timer clock cycle If enabled OCIEOA 1 and Global Interrupt Flag in SREG is set the Output Compare Flag generates an Output Compare interrupt The OCFOA Flag is automatically cleared when the interrupt is executed Alternatively the OCFOA Flag can be cleared by software by writing a logical one to its I O bit lo
19. LCD A passive display panel with terminals leading directly to a segment Segment The least viewing element pixel which can be on or off Common Denotes how many segments are connected to a segment terminal Duty 1 Number of common terminals on a actual LCD display Bias 1 Number of voltage levels used driving a LCD display 1 Frame Rate Number of times the LCD segments is energized per second 169 Automotive m 7735B AVR 12 07 ATmega169P Automotive Figure 22 1 LCD Module Block Diagram 12 bit Prescaler LCDCRB clk LCD Timing gt gt 0 LCDDR 18 15 LCDDR 13 10 Switch Array LCDDR 8 5 LCDDR 3 0 LCD Buffer 12 Vico Driver 2 3 V co 22 2 2 LCD Clock Sources The LCD Controller can be clocked by an internal synchronous or an external asynchronous clock source The clock source clk is by default equal to the system clock clkjo When the LCDCS bit in the LCDCRB Register is written to logic one the clock source is taken from the TOSC1 pin The clock source must be stable to obtain accurate LCD timing and hence minimize DC voltage offset across LCD segments 22 2 3 LCD Prescaler The prescaler consist of a 12 bit ripple counter and a 1 to 8 clock divider The
20. 1 169 Automotive sue 7735B AVR 12 07 A 169 Automotive 7735B AVR 12 07 Mnemonics Operands Description Operation Flags Clocks PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep function None 1 WDR Watchdog Reset see specific descr for WDR timer None 1 BREAK Break For On chip Debug Only None N A AMEL 361 AMEL 31 Ordering Information Speed MHz Power Supply Ordering Code Operation Range Automotive Notes 1 Pb free packaging complies to the European Directive for Restriction of Hazardous Substances RoHS directive Also Halide free and fully Green 2 For Speed vs Voc see Figure 27 1 on page 327 Package Type MD 64 Lead Thin 1 0 mm Profile Plastic Gull Wing Quad Flat Package TQFP 32 169 Automotive m H es 169 Automotive 32 Packaging Information 32 1 64 COMMON DIMENSIONS IN MM 1 20 1 0 95 0 09 0 20 16 00 5 0 100 14 00 LEAD CUPLANARITY 0 05 0 15 0 45 0 75 0 80 07 26 07 TITLE DRAWING No Atmel Nantes S A Ame La Chantrerie BP 70602 MD 64 Lead 14x14 mm Body Size 1 0 mm Body Thickness oi 49306 Nant
21. clk 1 TCNTn BOTTOM BOTTOM 1 TOVn Figure 13 9 shows the same timing data but with the prescaler enabled 169 Automotive sue 7735B AVR 12 07 es 169 Automotive 7735B AVR 12 07 Figure 13 9 Timer Counter Timing Diagram with Prescaler 8 MUU UYU BOTTOM BOTTOM 1 Figure 13 10 shows the setting of OCFOA in all modes except CTC mode Figure 13 10 Timer Counter Timing Diagram Setting of OCFOA with Prescaler 8 8 TCNTn OCRnx 1 OCRnx 1 OCRnx 2 OCRnx OCRnx Value Figure 13 11 shows the setting of OCFOA and the clearing of TCNTO CTC mode Figure 13 11 Timer Counter Timing Diagram Clear Timer on Compare Match mode with Pres caler foy 8 MMIII clk 8 1 AMEL 101 AMEL 13 9 8 bit Timer Counter Register Description 13 9 1 102 TCCROA Timer Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 0x44 COMOAD c5 Read Write Ww R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 FOCOA Force Output Compare The FOCOA bit is only active when the WGMOO bit specifies a no
22. gt Control Logic direction T C Prescaler Oscillator OCnx gt int Req Waveform OCnx Generation Timer Counter TCNTn DATA BUS Synchronized Status flags asynchronous mode select ASn clKasy Status flags 16 1 1 Registers The Timer Counter TCNT2 and Output Compare Register OCR2A are 8 bit registers Inter rupt request shorten as Int Req signals are all visible in the Timer Interrupt Flag Register 169 Automotive sume 7735B AVR 12 07 X 169 Automotive 16 1 2 Definitions TIFR2 All interrupts are individually masked with the Timer Interrupt Mask Register TIMSK2 TIFR2 and TIMSK2 are not shown in the figure The Timer Counter can be clocked internally via the prescaler or asynchronously clocked from the TOSC1 2 pins as detailed later in this section The asynchronous operation is controlled by the Asynchronous Status Register ASSR The Clock Select logic block controls which clock source the Timer Counter uses to increment or decrement its value The Timer Counter is inac tive when no clock source is selected The output from the Clock Select logic is referred to as the timer clock The double buffered Output Compare Register OCR2A is compared with the Timer Counter value at all times The result of the compare can be used by the Waveform Generator t
23. 169 Automotive PWM mode is shown in Figure 16 6 The TCNT2 value is in the timing diagram shown as a his togram for illustrating the single slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2 Figure 16 6 Fast PWM Mode Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and 7 T T TOVn Interrupt Flag Set i i i i H H H TCNTn OCnx COMnx1 0 2 ocx L IL Period 2 s f 4s sf 6 7 The Timer Counter Overflow Flag TOV2 is set each time the counter reaches MAX If the inter rupt is enabled the interrupt handler routine can be used for updating the compare value In fast PWM mode the compare unit allows generation of PWM waveforms on the OC2A pin Setting the 2 1 0 bits to two will produce a non inverted PWM and an inverted PWM output can be generated by setting the COM2A1 0 to three See Table 16 4 on page 154 The actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as out put The PWM waveform is generated by setting or clearing the OC2A Register at the compare match between OCR2A and TCNT2 and clearing or setting the OC2A Register at the timer clock cycle the counter is cleared changes from MAX to BOTTOM The PWM frequency for the output can be calc
24. AMEL Figure 28 27 LCD SEG Output Buffer Impedance LCD SEG OUTPUT BUFFER IMPEDANCE Vicd 5V 125 85 25 45 Vcom Vseg V 200 Loadcurrent UA 28 10 BOD Thresholds and Analog Comparator Offset Figure 28 28 BOD Thresholds vs Temperature BOD Level is 4 3V BOD THRESHOLDS w TEMPERATURE BOD level 4 30v BOD threshold V 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature C 169 Automotive m u H 7735B AVR 1 2 07 es 169 Automotive Figure 28 29 BOD Thresholds vs Temperature BOD Level is 2 7V BOD THRESHOLDS vs TEMPERATURE BOD level 2 70v E 1 0 a a 2 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature C Figure 28 30 Bandgap Voltage vs Temperature BANDGAP VOLTAGE vs TEMPERATURE 1 2 4 1 18 1 16 1 14 5 1 12 5 S44 m 1 08 m 1 06 1 04 1 02 45 25 5 15 35 55 75 95 115 Temperature 4 MEL 347 7735B AVR 12 07 AMEL Figure 28 31 Analog Comparator Offset Voltage vs Common Mode Voltage Voc 5V ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE Voo 5V 0 008 abc
25. WDT off Reset WDT wdr Write logical one to WDCE and WDE in r16 WDTCR ori r16 1 lt lt WDCE 1 lt lt WDE out WDTCR r16 Turn off WDT ldi r16 0 WD out WDTCR r16 1 ret C Code Example void WDT off void Reset WDT _ watchdog reset Write logical one to WDCE and WDE WDTCR 1 lt lt WDCE 1 lt lt WDE Turn off WDT WDTCR 0x00 Note 1 See About Code Examples on page 10 AMEL 53 AMEL 9 5 Register Description 9 5 1 MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset Bit 7 6 5 4 3 2 1 0 0x35 0x55 JTRF BORF EXTRF PORF MCUSR Read Write R R R R W R W R W R W R W Initial Value 0 0 0 See Bit Description Bit 4 JTRF JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR RESET This bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 38 Watchdog Reset Flag This bit is set if a Watchdog Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit2 Brown out Reset Flag This bit is set if a Brown out Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 1 EXTRF External Reset Flag This bit is set if an External Reset occurs The
26. 169 Automotive feature is similar to the OCOA toggle in CTC mode except the double buffer feature of the Out put Compare unit is enabled in the fast PWM mode 13 7 4 Phase Correct PWM Mode The phase correct PWM mode WGMO01 0 1 provides a high resolution phase correct PWM waveform generation option The phase correct PWM mode is based on a dual slope operation The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM In non inverting Compare Output mode the Output Compare OCOA is cleared on the compare match between TCNTO and OCROA while upcounting and set on the compare match while down counting In inverting Output Compare mode the operation is inverted The dual slope operation has lower maximum operation frequency than single slope operation However due to the sym metric feature of the dual slope PWM modes these modes are preferred for motor control applications The PWM resolution for the phase correct PWM mode is fixed to eight bits In phase correct PWM mode the counter is incremented until the counter value matches MAX When the counter reaches MAX it changes the count direction The TCNTO value will be equal to MAX for one timer clock cycle The timing diagram for the phase correct PWM mode is shown on Figure 13 7 The TCNTO value is in the timing diagram shown as a histogram for illustrating the dual slope operation The diagram includes non inverted and inverted PWM outputs The small horizont
27. 169 Automotive sue 7735B AVR 12 07 es 169 Automotive Figure 9 3 Start up RESET Extended Externally 1 X gt V 1 1 1 1 1 1 M V RESET ee T LLL 1 1 1 1 TIME OUT trout INTERNAL 1 RESET Table 9 1 Power On Reset Specifications Symbol Parameter Min Typ Max Units Power on Reset Threshold Voltage rising 1 1 1 4 1 7 V Vor Power on Reset Threshold Voltage falling 0 8 1 3 1 6 V VCC Max start voltage to ensure internal Power Reset signal oa Y V VCC Min start voltage to ensure internal Power 0 1 V PORMIN on Reset signal VCC Rise Rate to ensure Power on Reset 0 01 V ms Note 1 Before rising the supply has to be between and Veormax to ensure a Reset 9 2 2 External Reset An External Reset is generated by a low level on the RESET pin Reset pulses longer than the minimum pulse width see System and Reset Characteristics on page 328 will generate a reset even if the clock is not running Shorter pulses are not guaranteed to generate a reset When the applied signal reaches the Reset Threshold Voltage on its positive edge the delay counter starts the MCU after the Time out period troy has expired Figure 9 4 External Reset During Operation Vcc RESET lt trout TIME OUT INTERNAL RESET AIMEL 49 ey 7735B AVR
28. 334 28 3 Supply Current of modules 1 336 28 4 Power down Supply Current 3 1 6 nennen nen 337 28 5 Power save Supply Current sse 338 28 6 Pin E 338 28 7 Pin Thresholds and Hysteresis emen 339 28 8 Outp t leVel orate e eec rid 341 28 9 LCD Driver Output Impedance nennen 345 28 10 BOD Thresholds and Analog Comparator Offset 346 28 11 Internal Oscillator Speed 349 28 12 Current Consumption of Peripheral Units sss 350 28 13 Current Consumption in Reset and Reset Pulsewidth 353 29 Register Summary 355 30 Instruction Set Summary sima iul e d dodo E KR 359 6 169 Automotive m EN 7735 07 07 ees 169 Automotive 31 Ordering Information M 362 32 Packaging Information 363 221 363 364 33 1 ATmega169P RV Qr eden aei 364 33 2 A
29. LCDDC2 LCDDC1 LCDDCO Nominal drive time 0 0 0 300 us 0 0 1 70 us 0 1 0 150 us 0 1 1 450 us 1 0 0 575 us 1 0 1 850 us 1 1 0 1150 us 1 1 1 50 of ps Bit4 LCDMDT LCD Maxium Drive Time Writing this bit to one turns the LCD drivers on 100 on the time regardless of the drive time configured by LCDDC2 0 Bits 3 0 LCDCC3 0 LCD Contrast Control The LCDCC3 0 bits determine the maximum voltage Vi cp on segment and common pins The different selections are shown in Table 22 8 New values take effect every beginning of a new frame A MEL 247 7735B AVR 12 07 22 5 5 248 AMEL Table 22 8 LCD Contrast Control LCDCC3 LCDCC2 LCDCC1 LCDCCO Typical Voltage V cp 0 0 0 0 2 60 V 0 0 0 1 2 65 V 0 0 1 0 2 70 V 0 0 1 1 2 75 V 0 1 0 0 2 80 V 0 1 0 1 2 85 V 0 1 1 0 2 90 V 0 1 1 1 2 95 V 1 0 0 0 3 00 V 1 0 0 1 3 05 V 1 0 1 0 3 10 V 1 0 1 1 3 15 V 1 1 0 0 3 20V 1 1 0 1 3 25 V 1 1 1 0 3 30 V 1 1 1 1 3 35 V LCD Memory Mapping Write a LCD memory bit to one and the corresponding segment will be energized visible Unused LCD Memory bits for the actual display can be used freely as storage Bit COM3 COM3 COM3 COM3 COM2 COM2 COM2 COM2 COMI COMI COMI COMI COMO COMO COMO COMO Read Write Initial Value ATmega169P Automotive SEG315 SEG307 SEG223 SEG215 SEG207 5 015 5 007 SEG322 SEG314 SEG306
30. compare match clear at BOTTOM inverting mode Note 1 Aspecial case occurs when OCROA equals TOP and 1 is set In this case the com pare match is ignored but the set or clear is done at BOTTOM See Fast PWM Mode on page 97 for more details Table 13 5 shows the 1 0 bit functionality when the WGM01 0 bits are set to phase cor rect PWM mode Table 13 5 Compare Output Mode Phase Correct PWM Mode COMOA1 COMOAO Description 0 0 Normal port operation OCOA disconnected 0 1 Reserved 1 0 Clear OCOA on compare match when up counting Set OCOA on compare match when downcounting 1 1 Set OCOA on compare match when up counting Clear OCOA on compare match when downcounting Note 1 Aspecial case occurs when OCROA equals TOP and 1 is set In this case the com pare match is ignored but the set or clear is done at TOP See Phase Correct PWM Mode on page 99 for more details Bit 2 0 CS02 0 Clock Select 103 ATMEL 7735B AVR 12 07 13 9 2 13 9 3 13 9 4 104 AMEL The three Clock Select bits select the clock source to be used by the Timer Counter Table 13 6 Clock Select Bit Description 502 501 500 Description 0 0 0 No clock source Timer Counter stopped 0 0 1 clkyo No prescaling 0 1 0 clkjo 8 From prescaler 0 1 1 clk o 64 From prescaler 1 0 0 clkyo 256 From prescaler 1 0 1 clky9 1024
31. 1 lt lt Insert nop for synchronization _ no operation Read port pins i PINB Note 1 Forthe assembly program two temporary registers are used to minimize the time from pull ups are set on pins 0 1 6 and 7 until the direction bits are correctly set defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers 12 2 5 Digital Input Enable and Sleep Modes As shown in Figure 12 2 the digital input signal can be clamped to ground at the input of the Schmitt Trigger The signal denoted SLEEP in the figure is set by the MCU Sleep Controller in Power down mode Power save mode and Standby mode to avoid

ATMEL AVR microcontroller ATmega169P handbook data (1)

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