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ATMEL AVR microcontroller ATmega169P handbook data (1)(1)

1. 28 8 Output level Figure 28 18 Output low Voltage Ports A C D E F G Vcc 5V PIN OUTPUT VOLTAGE vs SINK CURRENT Ports A C D G Vcc 5v 125 85 25 45 AIMEL 341 7735B AVR 12 07 NE AMEL Figure 28 19 Output low Voltage Ports A C D E F G Vcc 3V VO PIN OUTPUT VOLTAGE vs SINK CURRENT Ports A C D E G 1 2 08 125 85 806 25 45 0 4 0 2 oF 0 1 2 3 4 5 6 7 8 9 10 mA Figure 28 20 Output low Voltage Port B Vcc 5V PIN OUTPUT VOLTAGE vs SINK CURRENT Port B only Vcc 5v 125 85 25 45 169 Automotive memm 7735B AVR 12 07 ATmega169P Automotive Figure 28 21 Output low Voltage Port B Vcc 3V VO PIN OUTPUT VOLTAGE vs SINK CURRENT Port B only Vcc 125 85 25 45 Figure 28 22 Output high Voltage Ports A C D F G Vcc 5V VO PIN OUTPUT VOLTAGE vs SOURCE CURRENT Ports A C D F G 5v 125 85 25 45 A MEL 343 7735B AVR 12 07 AMEL Figure 28 23 Output high Voltage Ports A C D F G Vcc PIN OUTPUT VOLTAGE vs SOURCE CURRENT
2. 37 7735 07 07 7 9 Clock OutpUt BUNCE iret 37 7 10 System Clock Prescaler 4 440 0000 0 nnns nnn nnns 37 7 11 Register Description 2 2 2 38 8 Power Management and Sleep Modes 40 8 1 Sleep Modes ane rra 40 8 2 1916 41 8 3 ADC Noise Reduction Mode 1 nnne 41 8 4 Power down Mode a 41 8 5 Power save Modo 42 8 6 Standby Mode re Lt e HE 42 8 7 Power Reduction Register 4 42 8 8 Minimizing Power Consumption sss 43 8 9 Register D scriptiOn _ terne ite e ere ned 45 9 System Control and Reset 47 9 1 Resettinig the AVR e M 47 9 2 Hieset SOURCES inira rd deb e Fidi es au rgo ua ddp d nea 47 9 3 Internal Voltage Reference 51 9 4 Watchdog Timer 51 9 5 Register DescriptlOD ti
3. CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation AMEL 279 AIMEL Figure 25 2 Memory Sections Program Memory Program Memory BOOTSZ 11 BOOTSZ 10 0 0000 0 0000 5 5 8 2 Application Flash Section 2 Application Flash Section a 5 End RWW 5 End RWW 3 Start NRWW 9 Start NRWW 2 2 End Application End Application Start Boot Loader 8 Boot Loader Flash Section Start Boot Loader 8 a Flashend a Flashend o o z 2 BOOTSZ 01 BOOTSZ 00 0 0000 0 0000 9 5 9 o 2 Application Flash Section 2 Application Flash Section 2 2 o 52 5 c o rs 5 End RWW 5 End RWW End Application 5 Start NRWW 8 Start NRWW Start Boot Loader 8 8 5 End Application z Start Boot Loader 2 Boot Loader Flash Section Boot Loader Flash Section c Flashend c Flashend o o 2 2 Note 1 The parameters the figure above are given Table 25 6 on page 289 20 169 Automotive m n 7735B AVR 12 07 X 169 Automotive 25 5 Boot Loader Lock Bits If no Boot Loader capability is needed the entire Flash is available for application code The Boot Loader has two separate sets of Boot Lock bits which can be set independently This gives th
4. 0 7 ADMUX REFS1 REFSO ADLAR MUX4 MUX3 MUX2 MUX1 MUXO 227 0x7B ADCSRB ACME ADTS2 ADTS1 ADTSO 213 231 0x7A ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPSO 229 0x79 ADCH ADC Data Register High byte 230 0x78 ADCL ADC Data Register Low byte 230 0x77 Reserved 0x76 Reserved 0x75 Reserved 0 74 Reserved 0x73 Reserved 0x72 Reserved 0x71 Reserved 0 70 TIMSK2 OCIE2A TOIE2 156 Ox6F TIMSK1 ICIE1 OCIE1B OCIE1A TOIE1 133 Ox6E TIMSKO TOIEO 104 0x6D Reserved 0 6 1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 63 0x6B PCMSKO PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINTO 64 Ox6A Reserved 0x69 EICRA 15 01 15 00 62 0 68 Reserved 0x67 Reserved 0x66 OSCCAL Oscillator Calibration Register 38 0x65 Reserved 0 64 PRR PRLCD PRTIM1 PRSPI PRUSARTO PRADC 45 0x63 Reserved 0 62 Reserved 0x61 CLKPR CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPSO 38 0x60 WDTCR WDCE WDE WDP2 WDP1 WDPO 54 Ox3F 0 5 SREG T H S V N 2 13 Ox3E 0 5 SPH 10 SP9 SP8 15 Ox3D 0x5D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO 15 0 3 0x5C Reserved Ox3B 0x5B Reserved Ox3A
5. compare match clear at BOTTOM inverting mode Note 1 Aspecial case occurs when OCROA equals TOP and 1 is set In this case the com pare match is ignored but the set or clear is done at BOTTOM See Fast PWM Mode on page 97 for more details Table 13 5 shows the 1 0 bit functionality when the WGM01 0 bits are set to phase cor rect PWM mode Table 13 5 Compare Output Mode Phase Correct PWM Mode COMOA1 COMOAO Description 0 0 Normal port operation OCOA disconnected 0 1 Reserved 1 0 Clear OCOA on compare match when up counting Set OCOA on compare match when downcounting 1 1 Set OCOA on compare match when up counting Clear OCOA on compare match when downcounting Note 1 Aspecial case occurs when OCROA equals TOP and 1 is set In this case the com pare match is ignored but the set or clear is done at TOP See Phase Correct PWM Mode on page 99 for more details Bit 2 0 CS02 0 Clock Select 103 ATMEL 7735B AVR 12 07 13 9 2 13 9 3 13 9 4 104 AMEL The three Clock Select bits select the clock source to be used by the Timer Counter Table 13 6 Clock Select Bit Description 502 501 500 Description 0 0 0 No clock source Timer Counter stopped 0 0 1 clkyo No prescaling 0 1 0 clkjo 8 From prescaler 0 1 1 clk o 64 From prescaler 1 0 0 clkyo 256 From prescaler 1 0 1 clky9
6. 169 Automotive feature is similar to the OCOA toggle in CTC mode except the double buffer feature of the Out put Compare unit is enabled in the fast PWM mode 13 7 4 Phase Correct PWM Mode The phase correct PWM mode WGMO01 0 1 provides a high resolution phase correct PWM waveform generation option The phase correct PWM mode is based on a dual slope operation The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM In non inverting Compare Output mode the Output Compare OCOA is cleared on the compare match between TCNTO and OCROA while upcounting and set on the compare match while down counting In inverting Output Compare mode the operation is inverted The dual slope operation has lower maximum operation frequency than single slope operation However due to the sym metric feature of the dual slope PWM modes these modes are preferred for motor control applications The PWM resolution for the phase correct PWM mode is fixed to eight bits In phase correct PWM mode the counter is incremented until the counter value matches MAX When the counter reaches MAX it changes the count direction The TCNTO value will be equal to MAX for one timer clock cycle The timing diagram for the phase correct PWM mode is shown on Figure 13 7 The TCNTO value is in the timing diagram shown as a histogram for illustrating the dual slope operation The diagram includes non inverted and inverted PWM outputs The small horiz
7. 169 Automotive m H 7735B AVR 12 07 ATmega169P Automotive 14 Capture IR 0 S Bet 26 9 2 AVR_RESET 0xC The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode The TAP controller is not reset by this instruction The one bit Reset Register is selected as Data Register Note that the reset will be active as long as there is a logic one in the Reset Chain The output from this chain is not latched The active states are Shift DR The Reset Register is shifted by the input 26 9 3 PROG_ENABLE 0x4 The AVR specific public JTAG instruction for enabling programming via the JTAG port The 16 bit Programming Enable Register is selected as Data Register The active states are the following Shift DR The programming enable signature is shifted into the Data Register Update DR The programming enable signature is compared to the correct value and Programming mode is entered if the signature is valid A MEL 313 7735B AVR 12 07 AMEL 26 9 4 PROG_COMMANDS 0x5 The AVR specific public JTAG instruction for entering programming commands via the JTAG port The 15 bit Programming Command Register is selected as Data Register The active states are the following Capture DR The result of the previous command is loaded into the Data Register Shift DR
8. 1 69P Automotive 7735B AVR 12 07 es 169 Automotive 18 5 USART Initialization 7735B AVR 12 07 The USART has to be initialized before any communication can take place The initialization pro cess normally consists of setting the baud rate setting frame format and enabling the Transmitter or the Receiver depending on the usage For interrupt driven USART operation the Global Interrupt Flag should be cleared and interrupts globally disabled when doing the initialization Before doing a re initialization with changed baud rate or frame format be sure that there are no ongoing transmissions during the period the registers are changed The TXCn Flag can be used to check that the Transmitter has completed all transfers and the RXCn Flag can be used to check that there are no unread data in the receive buffer Note that the TXCn Flag must be cleared before each transmission before UDRn is written if it is used for this purpose The following simple USART initialization code examples show one assembly and one C func tion that are equal in functionality The examples assume asynchronous operation using polling no interrupts enabled and a fixed frame format The baud rate is given as a function parameter A MEL 175 AMEL For the assembly code the baud rate parameter is assumed to be stored in the r17 r16 Registers Assembly Code Example USART Init Set baud rate sts UBRRHO r17
9. 169 Automotive sue 7735B AVR 12 07 es Nea 169P Automotive Figure 9 3 Start up RESET Extended Externally 1 X gt V 1 1 1 1 1 1 M V RESET ee T LLL 1 1 1 1 TIME OUT trout INTERNAL 1 RESET Table 9 1 Power On Reset Specifications Symbol Parameter Min Typ Max Units Power on Reset Threshold Voltage rising 1 1 1 4 1 7 V Vor Power on Reset Threshold Voltage falling 0 8 1 3 1 6 V VCC Max start voltage to ensure internal Power Reset signal oa Y V VCC Min start voltage to ensure internal Power 0 1 V PORMIN on Reset signal VCC Rise Rate to ensure Power on Reset 0 01 V ms Note 1 Before rising the supply has to be between and Veormax to ensure a Reset 9 2 2 External Reset An External Reset is generated by a low level on the RESET pin Reset pulses longer than the minimum pulse width see System and Reset Characteristics on page 328 will generate a reset even if the clock is not running Shorter pulses are not guaranteed to generate a reset When the applied signal reaches the Reset Threshold Voltage on its positive edge the delay counter starts the MCU after the Time out period troy has expired Figure 9 4 External Reset During Operation Vcc RESET lt trout TIME OUT INTERNAL RESET AIMEL 49 ey 7735B AVR 12 07
10. Read Write R W R R R W R R R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 JTD JTAG Interface Disable When this bit is zero the JTAG interface is enabled if the JTAGEN Fuse is programmed If this bit is one the JTAG interface is disabled In order to avoid unintentional disabling or enabling of the JTAG interface a timed sequence must be followed when changing this bit The application software must write this bit to the desired value twice within four cycles to change its value Note that this bit must not be altered when using the On chip Debug system If the JTAG interface is left unconnected to other JTAG circuitry the JTD bit should be set to one The reason for this is to avoid static current at the TDO pin in the JTAG interface MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset Bit 7 6 5 4 3 2 1 0 0x34 0x54 LCs JTRF WDRF PORF MCUSR Read Write R R R R W R W R W R W R W Initial Value 0 0 0 See Bit Description Bit 4 JTRF JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR RESET This bit is reset by Power on Reset or by writing a logic zero to the flag 169 Automotive m 7735B AVR 12 07 es Nea 169P Automotive 25 Boot Loader Support Read While Write Self Programming 25 1 Features Read
11. AMEL 7735B AVR 12 07 AMEL 12 2 6 Unconnected Pins If some pins are unused it is recommended to ensure that these pins have a defined level Even though most of the digital inputs are disabled in the deep sleep modes as described above float ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled Reset Active mode and ldle mode The simplest method to ensure a defined level of an unused pin is to enable the internal pull up In this case the pull up will be disabled during reset If low power consumption during reset is important it is recommended to use an external pull up or pull down Connecting unused pins directly to or GND is not recommended since this may cause excessive currents if the pin is accidentally configured as an output 70 169 Automotive m s ss 7735B AVR 12 07 Nea 169P Automotive 12 3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I Os Figure 12 5 shows how the port pin control signals from the simplified Figure 12 2 can be overridden by alternate functions The overriding signals may not be present in all port pins but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family Figure 12 5 Alternate Port Functions PUOExn PUOVxn C P PUD DDOExn DDOVxn PVOE
12. Figure 14 13 Timer Counter Timing Diagram with Prescaler 8 clky clk clk 8 TCNTn CTC and FPWM PC WEG PWM WEF TOP 1 TOP 2 TOVn FPWM and ICF n it used jo Old Value New OCRnx Value A MEL 127 7735B AVR 12 07 AMEL 14 11 16 bit Timer Counter Register Description 14 11 1 128 1 Timer Counter1 Control Register A Bit 7 6 5 4 3 2 1 0 T _ wom Read Write R W R W R W R W R R R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 COM1A1 0 Compare Output Mode for Unit A 5 4 COM1B1 0 Compare Output Mode for Unit B The COM1A1 0 and COM1B1 0 control the Output Compare pins OC1A and OC1B respec tively behavior If one or both of the COM14A1 0 bits are written to one the OC1A output overrides the normal port functionality of the I O pin it is connected to If one or both of the COM1B1 0 bit are written to one the output overrides the normal port functionality of the I O pin it is connected to However note that the Data Direction Register DDR bit correspond ing to the OC1A or OC1B pin must be set in order to enable the output driver When the OC1A or OC1B is connected to the pin the function of the COM1x1 0 bits is depen dent of the WGM13 0 bits setting Table 14 1 shows the COM1x1 0 bit functionality when the WGM
13. 26 9 24 Reading the Calibration Byte 324 gt O MN Enter JTAG instruction PROG_COMMANDS Enable Calibration byte read using programming instruction 10a Load address 0x00 using programming instruction 10b Read the calibration byte using programming instruction 10c ATmega169P Automotive m 7735B AVR 12 07 A 169 Automotive 27 Electrical Characteristics 27 1 Absolute Maximum Ratings Operating Temperature Storage Temperature Voltage on any Pin except RESET with respect to Ground Voltage on RESET with respect to Ground 0 5V to 13 0V Maximum Operating 2 6 0V DC Current 2 40 0 mA DC Current and GND 200 0 mA 40 C to 85 C m 65 C to 150 C isis eis 0 5V to 0 5 27 2 DC Characteristics 40 C to 85 C Vec 2 7V to 5 5V unless otherwise noted NOTICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 7735B AVR 12 07
14. AMEL EEPROM Write During Power down Sleep Mode When entering Power down sleep mode while an EEPROM write operation is active the EEPROM write operation will continue and will complete before the Write Access time has passed However when the write operation is completed the clock continues running and as a consequence the device does not enter Power down entirely It is therefore recommended to verify that the EEPROM write operation is completed before entering Power down Preventing EEPROM Corruption During periods of low the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly These issues are the same as for board level systems using EEPROM and the same design solutions should be applied An EEPROM data corruption can be caused by two situations when the voltage is too low First a regular write sequence to the EEPROM requires a minimum voltage to operate correctly Sec ondly the CPU itself can execute instructions incorrectly if the supply voltage is too low EEPROM data corruption can easily be avoided by following this design recommendation Keep the AVR RESET active low during periods of insufficient power supply voltage This can be done by enabling the internal Brown out Detector BOD If the detection level of the internal BOD does not match the needed detection level an external low reset Protection circuit can be used If a reset occurs w
15. M BYPASS REGISTER i ANALOG Analog input nalog inputs UNITS PERIPHERIAL lt lt UNITS BREAKPOINT SCAN CHAIN JTAG AVR CORE ARES AU DECODER OCD STATUS AND CONTROL lt lt Control amp Clock lines PORT n AIMEL ae 7735B AVR 12 07 NENNEN AMEL Figure 23 2 TAP Controller State Diagram 1 Test Logic Reset k 0 0 l Select DR Scan Select IR Scan 1 0 H Capture DR H Capture IR 0 ift DR 1 1 1 Exit1 DR Exit1 IR 0 Pause DR 0 Pause IR 0 1 1 1 0 0 gt Shift D 0 Shift IR 0 0 0 Exit2 DR 0 Exit2 IR 1 Update DR Update IR 1 0 1 23 3 Controller The TAP controller is a 16 state finite state machine that controls the operation of the Boundary scan circuitry JTAG programming circuitry or On chip Debug system The state transitions depicted in Figure 23 2 depend on the signal present on TMS shown adjacent to each state transition at the time of the rising edge at TCK The initial state after a Power on Reset is Test Logic Reset As a definition in this document the LSB is shifted in and out first for all Shift Registers Assuming Run Test Idle is the present state a typical scenario for using the JTAG interface is At the TMS input apply the sequence 1 1 0 0 at the rising edges of to enter the Shift I
16. RW RW HW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0 The Timer Counter Register gives direct access both for read and write operations to the Timer Counter unit 8 bit counter Writing to the TCNT2 Register blocks removes the compare match on the following timer clock Modifying the counter TCNT2 while the counter is running introduces a risk of missing a compare match between TCNT2 and the OCR2A Register 16 10 3 OCR2A Output Compare Register A Bit 7 6 5 4 3 2 1 0 0x83 ocmRayo ocra Read Write R W RW RW AW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8 bit value that is continuously compared with the counter value TCNT2 A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OC2A pin A MEL 155 7735B AVR 12 07 AMEL 16 10 4 TIMSK2 Timer Counter2 Interrupt Mask Register Bit 0 7 6 5 4 3 2 1 0 nee Read Write R R R R R R R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 1 OCIE2A Timer Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I bit in the Status Register is set one the Timer Counter2 Compare Match A interrupt is enabled The corresponding interrupt is executed if a compare match in Timer Counter2 occurs i e when the OCF2A bit is set in the Timer Counter 2 Interrupt Flag Register TIFR2 Bit 0 TOIE2 Timer Co
17. SREG cSREG restore SREG value I bit When using the SEI instruction to enable interrupts the instruction following SEI will be exe cuted before any pending interrupts as shown in this example Assembly Code Example sei set Global Interrupt Enable Sleep enter sleep waiting for interrupt note will enter sleep before any pending interrupt s C Code Example _ enable interrupt set Global Interrupt Enable Sleep enter sleep waiting for interrupt note will enter sleep before any pending interrupt s Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini mum After four clock cycles the program vector address for the actual interrupt handling routine is executed During this four clock cycle period the Program Counter is pushed onto the Stack The vector is normally a jump to the interrupt routine and this jump takes three clock cycles If an interrupt occurs during execution of a multi cycle instruction this instruction is completed before the interrupt is served If an interrupt occurs when the MCU is in sleep mode the interrupt execution response time is increased by four clock cycles This increase comes in addition to the start up time from the selected sleep mode A return from an interrupt handling routine takes four clock cycles During these four clock cycles the Program Counter two
18. 1 69P Automotive memme 7735B AVR 12 07 es 169 Automotive 22 5 LCD Register Description 22 5 1 LCDCRA LCD Control and Status Register A Bit 7 6 5 4 3 2 1 0 OxE4 LCDEN LCDAB LCDIF LCDIE LCDBD LCDCCD LCDBL LCDCRA Read Write R W R W R R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 LCDEN LCD Enable Writing this bit to one enables the LCD Controller Driver By writing it to zero the LCD is turned off immediately Turning the LCD Controller Driver off while driving a display enables ordinary port function and DC voltage can be applied to the display if ports are configured as output It is recommended to drive output to ground if the LCD Controller Driver is disabled to discharge the display Bit6 LCDAB LCD Low Power Waveform When LCDAB is written logic zero the default waveform is output on the LCD pins When LCDAB is written logic one the Low Power Waveform is output on the LCD pins If this bit is modified during display operation the change takes place at the beginning of a new frame Bit 5 Res Reserved Bit This bit is reserved and will always read as zero Bit4 LCDIF LCD Interrupt Flag This bit is set by hardware at the beginning of a new frame at the same time as the display data is updated The LCD Start of Frame Interrupt is executed if the LCDIE bit and the I bit in SREG are set LCDIF is cleared by hardware when executing the corresponding Interrupt Handling Vector Al
19. AMEL Symbol Parameter Condition Min Typ Max Units Input Low Voltage except B _ 1 Vit XTAL1 and RESET pins Voc 2 7V 5 5V 0 5 0 3 V Input High Voltage except _ 2 Vin XTAL1 and RESET pins Voc 2 7V 5 5V 0 6Vcc Voc 0 5 V Low Vol Vii 2 p pe 27V 55V 0 5 0 151 2 27V 5 5V 0 7Veg Voc 0 5 Viz Ba e Vec 27V 5 5V 05 0 2 V Vine eae Voc 27V 5 5V 0 9Vgq Voc 0 5 Output Low Voltage lo 10 mA 5V 0 7 V 9L Port D F G lo 5 mA 3V 0 5 V Output Low Voltage lo 20 mA Veg 5V 0 7 om Port B lo 10 mA Veg 0 5 V Output High Voltage lop 10 mA 5V 4 2 V en Port A C D E F G lop 5 MA 2 3 V Output High Voltage lop 20 mA 5V 4 2 V omi Port B 10 mA 2 3 Input Leakage Voc 5 5V pin low 1 A iE Current I O Pin absolute value M Input Leakage Voc 5 5V pin high 1 A Current I O Pin absolute value H Reset Pull up Resistor Voc 5V Vast OV 30 60 kQ I O Pin Pull up Resistor 20 50 325 AMEL Ta 40 C to 85 C Vec 2 7V to 5 5V unless otherwise noted Symbol Parameter Condition Min Typ Max Units Active 4 MHz Vcc 2 3 4 mA Active 8 MHz Voc 5V 8 4 12 mA Power Supply Current Idle 4 MHz Voc 3V 0 7 1 6 mA Idle 8 MHz 5V 3
20. IDCODE 0x1 The Instruction Register is 4 bit wide supporting up to 16 instructions Listed below are the JTAG instructions useful for Boundary scan operation Note that the optional HIGHZ instruction is not implemented but all outputs with tri state capability can be set in high impedant state by using the AVR RESET instruction since the initial state for all port pins is tri state As a definition in this datasheet the LSB is shifted in and out first for all Shift Registers The OPCODE for each instruction is shown behind the instruction name in hex format The text describes which Data Register is selected as path between TDI and TDO for each instruction Mandatory JTAG instruction for selecting the Boundary scan Chain as Data Register for testing circuitry external to the AVR package For port pins Pull up Disable Output Control Output Data and Input Data are all accessible in the scan chain For Analog circuits having off chip connections the interface between the analog and the digital logic is in the scan chain The con tents of the latched outputs of the Boundary scan chain is driven out as soon as the JTAG IR Register is loaded with the EXTEST instruction The active states are Capture DR Data on the external pins are sampled into the Boundary scan Chain Shift DR The Internal Scan Chain is shifted by the TCK input Update DR Data from the scan chain is applied to output pins Optional JTAG instruction selecti
21. The high performance AVR ALU operates in direct connection with all the 32 general purpose working registers Within a single clock cycle arithmetic operations between general purpose registers or between a register and an immediate are executed The ALU operations are divided into three main categories arithmetic logical and bit functions Some implementations of the architecture also provide a powerful multiplier supporting both signed unsigned multiplication and fractional format See the Instruction Set section for a detailed description 12 169 Automotive m E N 7735B AVR 12 07 es 169 Automotive 5 4 Status Register The Status Register contains information about the result of the most recently executed arith metic instruction This information can be used for altering program flow in order to perform conditional operations Note that the Status Register is updated after all ALU operations as specified in the Instruction Set Reference This will in many cases remove the need for using the dedicated compare instructions resulting in faster and more compact code The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt This must be handled by software 5 4 1 SREG AVR Status Register The SREG is defined as Bit 7 6 5 4 3 2 1 0 osse SREG Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0
22. 169 Automotive m HH 7735B AVR 12 07 es NC a169P Automotive 27 7 ADC Characteristics Table 27 6 ADC Characteristics Symbol Parameter Condition Min Typ Max Units Resolution Single Ended Conversion 10 Bits Vner 4V Vec 4V TUE Absolute accuracy ADC clock 200 kHz 2 0 4 0 LSB VREF 4V Vec 4V INL Integral Non Linearity ADC clock 200 KHz 0 5 1 5 LSB VREF 4V Voc 4V DNL Differential Non Linearity ADC clock 200 kHz 0 25 0 7 LSB Vner 4V Voc 4V _ _ Gain Error ADC clock 200 kHz 4 0 2 0 4 0 LSB VREF 4V Vec 4V _ Offset Error ADC clock 200 kHz 4 0 2 0 4 0 LSB Conversion Time Free Running Conversion 65 260 us Clock Frequency Single Ended Conversion 50 200 kHz AVCC Analog Supply Voltage Voc 0 3 Voc 0 3 VREF Reference Voltage Single Ended Conversion 1 0 AVCC V ViN Pin Input Voltage Single Ended Channels GND VREF Vint Internal Voltage Reference 1 0 1 1 1 2 Reer Reference Input Resistance 32 Rain Analog Input Resistance 100 MQ 27 8 LCD Controller Characteristics Table 27 7 LCD Controller Characteristics Symbol Parameter Condition Min Typ Max Units Rseg SEG Driver Output Impedance Vicp 5 0V Load 100uA 7 12 Room COM Driver Output Impedance Vicp 5 0V Load 1000 1 2 2 4 MEL 331 7735B AVR 12 07 AMEL 28 Typical Characteristics 28 1 332 The follo
23. AMEL 9 2 3 Brown out Detection ATmega169P has an On chip Brown out Detection BOD circuit for monitoring the Vec level during operation by comparing it to a fixed trigger level The trigger level for the BOD can be selected by the BODLEVEL Fuses The trigger level has a hysteresis to ensure spike free Brown out Detection The hysteresis on the detection level should be interpreted as 2 and Vepor Vuygi 2 When the BOD is enabled and Vec decreases to a value below the trigger level Vgor in Figure 9 5 the Brown out Reset is immediately activated When Vec increases above the trigger level Vao7 in Figure 9 5 the delay counter starts the MCU after the Time out period has expired The BOD circuit will only detect a drop in if the voltage stays below the trigger level for longer than tgop given in System and Reset Characteristics on page 328 Figure 9 5 Brown out Reset During Operation RESET 1 1 1 1 1 TIME OUT lt trout 1 1 INTERNAL 5 1 RESET 9 2 4 Watchdog Reset When the Watchdog times out it will generate a short reset pulse of one CK cycle duration On the falling edge of this pulse the delay timer starts counting the Time out period trout Refer to page 51 for details on operation of the Watchdog Timer Figure 9 6 Watchdog Reset During Operation Voc RESET gt lt 1 Cycle WDT TIME OUT 1 1 t RESET tro aa
24. If PORTxn is written logic zero when the pin is configured as an output pin the port pin is driven low zero 169 Automotive m 7735B AVR 12 07 es 169 Automotive 12 2 2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn independent on the value of DDRxn Note that the SBI instruction can be used to toggle one single bit in a port 12 2 3 Switching Between Input and Output When switching between tri state DDxn PORTxn 0000 and output high DDxn PORTxn 0b11 an intermediate state with either pull up enabled DDxn PORTxn 0001 or output low PORTxn 0010 must occur Normally the pull up enabled state is fully accept able as a high impedant environment will not notice the difference between a strong high driver and a pull up If this is not the case the PUD bit in the MCUCR Register can be set to disable all pull ups in all ports Switching between input with pull up and output low generates the same problem The user must use either the tri state DDxn PORTxn 0000 or the output high state DDxn PORTxn 0b11 as an intermediate step Table 12 1 on page 67 summarizes the control signals for the pin value Table 12 1 Port Pin Configurations DDxn PORTxn in MCHCHS yo Pull up Comment 0 0 X Input No Tri state Hi Z 0 1 0 Input Yes Pxn will source current if ext pulled low 0 1 1 Input No Tr
25. LCDPM gt 1 LCDPM gt 2 LCDPM gt 2 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE B B DIEOE LCDEN LCDEN LCDEN LCDEN LCDPM gt 1 LCDPM gt 1 LCDPM gt 2 LCDPM gt 2 DIEOV 0 0 0 0 DI SEG15 SEG16 SEG17 SEG18 Table 12 14 Overriding Signals for Alternate Functions in PD3 PDO Signal Name PD3 SEG19 PD2 SEG20 PD1 INTO SEG21 PDO ICP1 SEG22 PUOE LCDEN LCDEN LCDEN LCDEN LCDPM 3 LCDPM 3 LCDPM gt 4 LCDPM gt 4 PUOV 0 0 0 0 DDOE LCDEN LCDEN LCDEN LCDEN LCDPM 3 LCDPM 3 LCDPM gt 4 LCDPM gt 4 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE E IESE LCDEN LCDEN LCDEN INTO LCDEN LCDPM 3 LCDPM 3 ENABLE LCDPM gt 4 DIEOV 0 0 52 0 DI INTO INPUT ICP1 INPUT AlO 169 Automotive sume 7735B AVR 12 07 es 169 Automotive 12 3 5 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 12 15 Table 12 15 Port E Pins Alternate Functions Port Pin Alternate Function PCINT7 Pin Change Interrupt7 CLKO Divided System Clock PE6 DO PCINT6 USI Data Output or Pin Change Interrupt6 DI SDA PCINT5 USI Data Input TWI Serial DAta or Pin Change Interrupt5 USCK SCL PCINT4 USART External Clock Input Output or TWI Serial Clock or Pin Change Interrupt4 PE7 PE4 PE3 AIN1 PCINT3 Analog Comparator Negative Input or
26. TIME OUT 1 INTERNAL RESET 50 169 Automotive sume 7735B AVR 12 07 Nea 169P Automotive 9 3 Internal Voltage Reference ATmega169P features an internal bandgap reference This reference is used for Brown out Detection and it can be used as an input to the Analog Comparator or the ADC 9 3 1 Voltage Reference Enable Signals and Start up Time The voltage reference has a start up time that may influence the way it should be used The start up time is given in System and Reset Characteristics on page 328 To save power the reference is not always turned on The reference is on during the following situations 1 When the BOD is enabled by programming the BODLEVEL 2 0 Fuse 2 When the bandgap reference is connected to the Analog Comparator by setting the ACBG bit in ACSR 3 When the ADC is enabled Thus when the BOD is not enabled after setting the ACBG bit or enabling the ADC the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used To reduce power consumption in Power down mode the user can avoid the three conditions above to ensure that the reference is turned off before entering Power down mode 9 4 Watchdog Timer 7735B AVR 12 07 The Watchdog Timer is clocked from a separate On chip Oscillator which runs at 1 MHz This is the typical value at Vcc 5V See characterization data for typical values at other Voc levels By con
27. When using the JTAG interface for Boundary scan using a JTAG TCK clock frequency higher than the internal chip frequency is possible The chip clock is not required to run 169 Automotive m m H 7735B AVR 12 07 Nea 169P Automotive 24 3 Data Registers 24 3 1 24 3 2 24 3 2 1 24 3 2 2 24 3 2 3 24 3 3 7735B AVR 12 07 The Data Registers relevant for Boundary scan operations are Bypass Register Device Identification Register Reset Register Boundary scan Chain Bypass Register The Bypass Register consists of a single Shift Register stage When the Bypass Register is selected as path between TDI and TDO the register is reset to 0 when leaving the Capture DR controller state The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested Device Identification Register Figure 24 1 shows the structure of the Device Identification Register Figure 24 1 The Format of the Device Identification Register MSB LSB Bit 81 28 27 12 11 1 0 Version Manufacturerib 4 bits 16 bits 11 bits 1 bit Version Version is a 4 bit number identifying the revision of the component The JTAG version number follows the revision of the device Revision A is 0x0 revision B is 0x1 and so on Part Number The part number is a 16 bit code identifying the component The JTAG Part Number for ATmega169P is listed in Table
28. ible on the pin The port override function is independent of the Waveform Generation mode ATMEL s 7735B AVR 12 07 13 6 1 AMEL The design of the Output Compare pin logic allows initialization of the OCOA state before the output is enabled Note that some 1 0 bit settings are reserved for certain modes of operation See 8 bit Timer Counter Register Description on page 102 Compare Output Mode and Waveform Generation The Waveform Generator uses the 1 0 bits differently in Normal CTC and PWM modes For all modes setting the 0 0 tells the Waveform Generator that no action on the OCOA Register is to be performed on the next compare match For compare output actions in the non PWM modes refer to Table 13 3 on page 103 For fast PWM mode refer to Table 13 4 on page 103 and for phase correct PWM refer to Table 13 5 on page 103 A change of the COM0A1 0 bits state will have effect at the first compare match after the bits are written For non PWM modes the action can be forced to have immediate effect by using the FOCOA strobe bits 13 7 Modes of Operation 13 7 1 13 7 2 96 Normal Mode The mode of operation i e the behavior of the Timer Counter and the Output Compare pins is defined by the combination of the Waveform Generation mode WGM01 0 and Compare Output mode 1 0 bits The Compare Output mode bits do not affect the counting sequence while the Waveform G
29. 2 como Period 2s J 7735B AVR 12 07 X A 169 Automotive 7735B AVR 12 07 The Timer Counter Overflow Flag TOV1 is set each time the counter reaches BOTTOM When either OCR1A or ICR1 is used for defining the TOP value the OC1A or ICF1 Flag is set accord ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value at TOP The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers If the TOP value is lower than any of the Compare Registers a compare match will never occur between the TCNT1 and the OCR1x Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written As the third period shown in Figure 14 8 illustrates changing the TOP actively while the Timer Counter is running in the phase correct mode can result in an unsymmetrical output The reason for this can be found in the time of update of the OCR1x Reg ister Since the OCR1x update occurs at TOP the PWM period starts and ends at TOP This implies that the length of the falling slope is determined by the previous TOP value while the length of the rising slope is determined by the new TOP value When these two values differ
30. 24 0xD5 Reserved e 0xD4 Reserved ue 0 03 Reserved z 0xD2 Reserved 0 01 Reserved 25 5 0 00 Reserved 27 OxCF Reserved OxCE Reserved m OxCD Reserved OxCC Reserved m A 0 Reserved zs Ud 0xCA Reserved ar 0xC9 Reserved z 0xC8 Reserved 45 0xC7 Reserved E 0xC6 UDRO USARTO I O Data Register 190 0xC5 UBRRHO USARTO Baud Rate Register High 194 0xC4 UBRRLO USARTO Baud Rate Register Low 194 0xC3 Reserved x z 0 2 UCSROC UMSELO 1 00 05 50 UCSZO01 UCSZ00 UCPOLO 190 0 1 UCSROB RXCIEO TXCIEO UDRIEO RXENO TXENO UCSZ02 RXB80 TXB80 190 0xCO UCSROA RXCO TXCO UDREO FEO DORO UPEO U2X0 MPCMO 190 Alm L 355 7735B AVR 12 07 NENNEN lt EE Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page OxBF Reserved OxBE Reserved OxBD Reserved OxBC Reserved m 0 Reserved m ES OxBA USIDR USI Data Register 207 0 9 USISR USISIF USI
31. AMEL 7 System Clock and Clock Options Figure 7 1 on page 30 presents the principal clock systems in the AVR and their distribution All of the clocks need not be active at a given time In order to reduce power consumption the clocks to modules not being used can be halted by using different sleep modes as described in clk Flash and EEPROM U Core CPU clk Ec Reset Logic FLASH Watchdog Timer FOR Source clock Watchdog clock Oscillator Watchdog Low frequency Crystal Oscillator Calibrated RC Oscillator The CPU clock is routed to parts of the system concerned with operation of the AVR core Examples of such modules are the General Purpose Register File the Status Register and the data memory holding the Stack Pointer Halting the CPU clock inhibits the core from performing The clock is used by the majority of the I O modules like Timer Counters SPI and USART The clock is also used by the External Interrupt module but note that some external inter are detected by asynchronous logic allowing such interrupts to be detected even if the I O clock is halted Also note that start condition detection in the USI module is carried out asynchro The Flash clock controls operation of the Flash interface The Flash clock is usually active simul 7 1 Clock Systems and their Distribution Powe
32. BODLEVEL1 2 Brown out Detector trigger level 1 unprogrammed BODLEVELO 1 Brown out Detector trigger level 1 unprogrammed RSTDISBL 0 External Reset Disable 1 unprogrammed Notes 1 See Table 27 4 on page 328 for BODLEVEL Fuse decoding 2 Port is input only Pull up is always See Alternate Functions of Port on page 85 24 169 Automotive memm 7735B AVR 12 07 XX Nea 169P Automotive Table 26 4 Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN 7 Enable OCD 1 unprogrammed OCD disabled JTAGEN 6 Enable JTAG 0 programmed JTAG enabled 1 Enable Serial Program and Data 0 programmed SPI prog SPIEN 5 Downloading enabled WDTON 4 Watchdog Timer always on 1 unprogrammed EEPROM memory is preserved 1 unprogrammed EEPROM not EESAVE 3 through the Chip Erase preserved BOOTSZ1 2 Select Boot Size see Table 25 6 0 programmed for details BOOTSZO 1 Select Boot Size see Table 25 6 0 programmed for details BOOTRST 0 Select Reset Vector 1 unprogrammed Note 1 The SPIEN Fuse is not accessible in serial programming mode 2 The default value of BOOTSZ1 0 results in maximum Boot Size See Table 25 6 on page 289 for details 3 See WDTCR Watchdog Timer Control Register on page 54 for details 4 Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits and JTAGEN Fu
33. CPHA 0 Sample Falling Setup Rising 2 CPOL 1 CPHA 1 Setup Falling Sample Rising 3 Figure 17 3 SPI Transfer Format with CPHA 0 SCK CPOL 0 L L L mode 0 LJ A LE LPL MOSI MISO eo worm A K H MSB first DORD 0 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB LSB first DORD 1 LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Figure 17 4 SPI Transfer Format with CPHA 1 se SLL rr mee LE LIL LU UL CHANGE 0 MOSI PIN SS MSB first DORD 0 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB LSB first DORD 1 LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB 1 4 169 Automotive 7735B AVR 12 07 es A 169 Automotive 17 5 Register Description 17 5 1 SPCR SPI Control Register Bit 7 6 5 4 3 2 1 0 0 2 0x4C SPIE DORD MSTR CPOL CPHA SPRI SPRO SPCR Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set Bit 6 SPE SPI Enable When the SPE bit is written to one the SPI is enabled This bit must be set to enable any SPI operations Bit 5 DORD Data Order When the DORD bit is written to one the LSB
34. Enable SPI Master set clock rate fck 16 ldi r17 1 lt lt SPE 1 MSTR 1 SPRO out SPCR r17 ret SPI MasterTransmit Start transmission of data r16 out SPDR r16 Wait Transmit Wait for transmission complete sbis SPSR SPIF rjmp Wait Transmit ret C Code Example void SPI MasterInit void Set MOSI and SCK output all others input DDR SPI 1 lt lt MOST 1 lt lt DD_SCK Enable SPI Master set clock rate fck 16 SPCR 1 lt lt SPE 1 lt lt MSTR 1 lt lt SPRO void SPI MasterTransmit char cData Start transmission SPDR cData Wait for transmission complete while SPSR amp 1 lt lt SPIF D Note 1 About Code Examples on page 10 ATMEL 161 162 AMEL The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception Assembly Code Example SPI SlaveInit Set MISO output all others input ldi r17 1 DD MISO out DDR_SPI r17 Enable SPI ldi r17 1 lt lt SPE out SPCR r17 ret SPI SlaveReceive Wait for reception complete sbis SPSR SPIF rjmp SPI SlaveReceive Read received data and return in rl16 SPDR ret C Code Example void SPI SlaveInit void Set MISO output all others input DDR SPI 1 lt lt DD MISO Enable SPI SPCR 1 lt lt SPE char SPI SlaveReceive void Wait for reception co
35. Normal Value mode sleep mode This is the Digital Input to alternate functions In the figure the signal is connected to the output of the schmitt trigger but DI Digital Input before the synchronizer Unless the Digital Input is used as a clock source the module with the alternate function will use its own synchronizer A alo This is the Analog Input output to from alternate functions The AIO 9 signal is connected directly to the pad and can be used bi Input Output ae directionally The following subsections shortly describe the alternate functions for each port and relate the overriding signals to the alternate function Refer to the alternate function description for further details 72 169 Automotive sume 7735B AVR 12 07 es A 169 Automotive 12 3 1 Alternate Functions of Port A The Port A has an alternate function as COMO 3 and SEGO 3 for the LCD Controller Table 12 3 Port A Pins Alternate Functions Port Pin PA7 Alternate Function SEGS LCD Front Plane PA6 SEG2 LCD Front Plane 2 PAS PA4 SEG1 LCD Front Plane 1 SEGO LCD Front Plane 0 PAS LCD Back Plane PA2 PA1 COM1 LCD Back Plane 1 PAO 2 LCD Back Plane 2 COMO LCD Back Plane 0 Table 12 4 and Table 12 5 relates the alternate functions of Port A to the overriding signals shown in Figure 12 5 on
36. PB2 PC SEG10 MISO PCINT11 PC1 SEG11 OCOA PCINT12 PB4 PCO SEG12 OC1A PCINT13 PBS PG1 SEG13 OC1B PCINT14 6 PGO SEG14 e wo 2 2 8 NAN KH m oO Oz A A a gt o SF 9 o0 c io A E mm O OC O 8 2 o T 0 O o o Oo HH 0 E E lt t gt a 2 Q 1 1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology Min and Max values will be available after the device is characterized 2 ATmega169P Automotive m um 7735B AVR 12 07 169 Automotive 2 Overview The ATmega169P is a low power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture By execut ing powerful instructions in a single clock cycle the ATmega169P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed 21 Block Diagram Figure 2 1 Block Diagram 5 PFO PF7 PA
37. Pin change interrupts on PCINT15 0 are detected asyn chronously This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode The INTO interrupts can be triggered by a falling or rising edge or a low level This is set up as indicated in the specification for the External Interrupt Control Register EICRA When the INTO interrupt is enabled and is configured as level triggered the interrupt will trigger as long as the pin is held low Note that recognition of falling or rising edge interrupts on INTO requires the presence of an I O clock described in Clock Systems and their Distribution page 30 Low level interrupt on INTO is detected asynchronously This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode The I O clock is halted in all sleep modes except Idle mode Note that if a level triggered interrupt is used for wake up from Power down the required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt If the level disappears before the end of the Start up Time the MCU will still wake up but no inter rupt will be generated The start up time is defined by the SUT and CKSEL Fuses as described in System Clock and Clock Options on page 30 11 1 Pin Change Interrupt Timing 7735B AVR 12 07 An example of timing of a pin change interrupt is shown in Figure 11 1 on page 61 F
38. Receiver The asynchronous reception operational range depends on the accuracy of the inter nal baud rate clock the rate of the incoming frames and the frame size in number of bits 18 8 1 Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames Figure 18 5 on page 185 illustrates the sampling process of the start bit of an incoming frame The sample rate is 16 times the baud rate for Normal mode and eight times the baud rate for Double Speed mode The horizontal arrows illustrate the synchronization variation due to the sampling pro cess Note the larger time variation when using the Double Speed mode U2Xn 1 of operation Samples denoted zero are samples done when the RxD line is idle i e no communi cation activity Figure 18 5 Start Bit Sampling es DIT PPP thr Pitter m ll Pf ti When the clock recovery logic detects a high idle to low start transition on the RxD line the start bit detection sequence is initiated Let sample 1 denote the first zero sample as shown in the figure The clock recovery logic then uses samples 8 9 and 10 for Normal mode and sam ples 4 5 and 6 for Double Speed mode indicated with sample numbers inside boxes on the figure to decide if a valid start bit is received If two or more of these three samples have logical high levels the majority wins the start bit is rejected as a noise spike and the Receiver starts looking for the n
39. See Boot Loader Simple Assembly Code Example on page 288 for an example 25 8 7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits and general Lock bits write the desired data to RO write X0001001 to SPMCSR and execute SPM within four clock cycles after writing SPMCSR Bit 7 4 3 6 5 2 1 0 RO TL T See Table 25 2 and Table 25 3 for how the different settings of the Boot Loader bits affect the Flash access If bits 5 0 in RO are cleared zero the corresponding Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR The Z pointer is don t care during this operation but for future compatibility it is recommended to load the Z pointer with 0x0001 same as used for reading the Lock bits For future compatibility it is also recommended to set bits 7 and 6 in RO to 1 when writing the Lock bits When program ming the Lock bits the entire Flash can be read during the operation A MEL 285 7735B AVR 12 07 25 8 8 25 8 9 286 AMEL EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation It is recommended that the user checks the status bit FEWE in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
40. The Data Register is shifted by the TCK input shifting out the result of the previous command and shifting in the new command Update DR The programming command is applied to the Flash inputs Run Test Idle One clock cycle is generated executing the applied command not always required see Table 26 17 below 26 9 5 PROG PAGELOAD 0x6 The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port An 8 bit Flash Data Byte Register is selected as the Data Register This is physically the 8 LSBs of the Programming Command Register The active states are the following Shift DR The Flash Data Byte Register is shifted by the TCK input Update DR The content of the Flash Data Byte Register is copied into a temporary register A write sequence is initiated that within 11 TCK cycles loads the content of the temporary register into the Flash page buffer The AVR automatically alternates between writing the low and the high byte for each new Update DR state starting with the low byte for the first Update DR encountered after entering the PROG_PAGELOAD command The Program Counter is pre incremented before writing the low byte except for the first written byte This ensures that the first data is written to the address set up by PROG COMMANDS and loading the last location in the page buffer does not make the program counter increment into the next page 26 9 6 PROG PAGEREAD 0x7 The AVR speci
41. The main part of the 16 bit Timer Counter is the programmable 16 bit bi directional counter unit Figure 14 2 shows a block diagram of the counter and its surroundings Figure 14 2 Counter Unit Block Diagram DATA BUS 8 bit TOVn Int Req Edge Detector From Prescaler TEMP 8 bit TCNTnH 8 bit TCNTnL 8 bit TCNTn 16 bit Counter Control Logic TOP Signal description internal signals Count Increment or decrement TCNT1 by 1 Direction Select between increment and decrement Clear Clear TCNT1 set all bits to zero clk Timer Counter clock TOP Signalize that TCNT1 has reached maximum value BOTTOM Signalize that TCNT1 has reached minimum value zero The 16 bit counter is mapped into two 8 bit memory locations Counter High TCNT1H con taining the upper eight bits of the counter and Counter Low TCNT1L containing the lower eight bits The TCNT1H Register can only be indirectly accessed by the CPU When the CPU does an access to the TCNT1H I O location the CPU accesses the high byte temporary register TEMP The temporary register is updated with the TCNT1H value when the TCNT1L is read and TCNT1H is updated with the temporary register value when TCNT1L is written This allows the CPU to read or write the entire 16 bit counter value within one clock cycle via the 8 bit data bus It is important to notice that there are special cases of writing to the TCNT1 Registe
42. Three wire Mode Operation Simplified Diagram PORTxn Figure 19 2 shows two USI units operating in Three wire mode one as Master and one as Slave The two Shift Registers are interconnected in such way that after eight USCK clocks the data in each register are interchanged The same clock also increments the USI s 4 bit counter The Counter Overflow interrupt Flag or USIOIF can therefore be used to determine when a transfer is completed The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR 169 Automotive R 7735B AVR 12 07 es Nea 169P Automotive Figure 19 3 Three wire Mode Timing Diagram CYCLE Reference 1 2 3 4 5 6 7 8 USCK USCK DO X X 6 X 5 X X 3 X 2 X 1 X LB X X 5 4 X 3 X 2 X 1 X LSB X dui The Three wire mode timing is shown in Figure 19 3 At the top of the figure is a USCK cycle ref erence One bit is shifted into the USI Shift Register USIDR for each of these cycles The USCK timing is shown for both external clock modes In External Clock mode 0 USICSO 0 DI is sampled at positive edges and DO is changed Data Register is shifted by one at negative edges External Clock mode 1 USICSO 1 uses the opposite edges versus mode 0 i e sam ples data at negative and
43. __ tcoewz T coro Lcocne Read Write R W R W R W R W R R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 LCDCS LCD Clock Select When this bit is written to zero the system clock is used When this bit is written to one the external asynchronous clock source is used The asynchronous clock source is either Timer Counter Oscillator or external clock depending on EXCLK in ASSR See Asynchronous operation of the Timer Counter on page 150 for further details Bit 6 LCD2B LCD 1 2 Bias Select When this bit is written to zero 1 3 bias is used When this bit is written to one 12 bias is used Refer to the LCD Manufacture for recommended bias selection Bit 5 4 LCDMUX1 0 LCD Mux Select The LCDMUX 1 0 bits determine the duty cycle Common pins that are not used are ordinary port pins The different duty selections are shown in Table 22 2 Table 22 2 LCD Duty Select LCDMUX1 LCDMUXO Duty Bias COM Pin Port Pin 0 0 Static Static COMO COM1 3 0 1 1 2 1 2 or 1 3 COM0 1 COM2 3 1 0 1 3 1 2 or 1 3 2 COM3 1 1 1 4 1 2 or 1 3 COMO 3 None Note 1 1 2 bias when LCD2B is written to one and 1 3 otherwise Bit 3 Res Reserved Bit This bit is reserved and will always read as zero Bits 2 0 LCDPM2 0 LCD Port Mask The LCDPM2 0 bits determine the number of port pins to be used as segment drivers The dif ferent selections are shown in Table 22 3 Unused pins c
44. including internal RC Oscillator can be selected when CLKO serves as clock output If the System Clock Prescaler is used it is the divided system clock that is output when the CKOUT Fuse is programmed 7 10 System Clock Prescaler The 169 system clock can be divided by setting the CLKPR Clock Prescale Regis ter on page 38 This feature can be used to decrease the system clock frequency and power consumption when the requirement for processing power is low This can be used with all clock source options and it will affect the clock frequency of the CPU and all synchronous peripherals ClKyo and clkg are divided by a factor as shown Table 7 13 When switching between prescaler settings the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting nor the clock frequency corresponding to the new setting The ripple counter that implements the prescaler runs at the frequency of the undivided clock which may be faster than the CPU s clock frequency Hence it is not possible to determine the state of the prescaler even if it were readable and the exact time it takes to switch from one clock division to another cannot be exactly predicted From the time the CLKPS values are writ ten it takes between T1 T2 and T1 2 T2 before the new clock frequency
45. int Req Waveform OCnx Generation Timer Counter TCNTn DATA BUS Synchronized Status flags NE a asynchronous mode select ASn clKasy Status flags 16 1 1 Registers The Timer Counter TCNT2 and Output Compare Register OCR2A are 8 bit registers Inter rupt request shorten as Int Req signals are all visible in the Timer Interrupt Flag Register 169 Automotive sume 7735B AVR 12 07 X 169 Automotive 16 1 2 Definitions TIFR2 All interrupts are individually masked with the Timer Interrupt Mask Register TIMSK2 TIFR2 and TIMSK2 are not shown in the figure The Timer Counter can be clocked internally via the prescaler or asynchronously clocked from the TOSC1 2 pins as detailed later in this section The asynchronous operation is controlled by the Asynchronous Status Register ASSR The Clock Select logic block controls which clock source the Timer Counter uses to increment or decrement its value The Timer Counter is inac tive when no clock source is selected The output from the Clock Select logic is referred to as the timer clock The double buffered Output Compare Register OCR2A is compared with the Timer Counter value at all times The result of the compare can be used by the Waveform Generator to gener ate a PWM or variable frequency output on the Output Compare pin OC2A See Output Com
46. write the Slave counter overflows and the SCL line is forced low D If the slave is not the one the Master has addressed it releases the SCL line and waits for a new start condition If the Slave is addressed it holds the SDA line low during the acknowledgment cycle before holding the SCL line low again i e the Counter Register must be set to 14 before releasing SCL at D Depending of the R W bit the Master or Slave enables its output If the bit is set a master read operation is in progress i e the slave drives the SDA line The slave can hold the SCL line low after the acknowledge E Multiple bytes can now be transmitted all in same direction until a stop condition is given by the Master F Or a new start condition is given If the Slave is not able to receive more data it does not acknowledge the data byte it has last received When the Master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted Figure 19 6 Start Condition Detector Logic Diagram 7735B AVR 12 07 gt USISIF CLOCK oe SDA CLR Q SCL 4 Write USISIF AMEL 205 19 2 5 19 2 6 AMEL Start Condition Detector The start condition detector is shown in Figure 19 6 The SDA line is delayed in the range of 50 to 300 ns to ensure valid sampling of the SCL line The start condition detector is only enabled in
47. 0 0 31 0 0 63 0 0 38 4k 12 0 2 25 0 2 17 0 0 35 0 0 23 0 0 47 0 0 57 6k 8 3 5 16 2 1 11 0 0 23 0 0 15 0 0 31 0 0 76 8 6 7 0 12 0 2 8 0 0 17 0 0 11 0 0 23 0 0 115 2 3 8 5 8 3 5 5 0 0 11 0 0 7 0 0 15 0 0 230 4 1 8 5 3 8 5 2 0 0 5 0 0 3 0 0 7 0 0 250k 1 0 0 3 0 0 2 7 8 5 7 8 3 7 8 6 5 3 0 5M 0 0 0 1 0 0 2 7 8 1 7 8 3 7 8 1M 0 0 096 0 7 8 1 7 8 Max 1 0 5 Mbps 1 Mbps 691 2 kbps 1 3824 Mbps 921 6 kbps 1 8432 Mbps 1 UBRRn 0 Error 0 0 A MEL 197 7735B AVR 12 07 AMEL Table 18 12 Examples of UBRRn Settings for Commonly Used Oscillator Frequencies Continued fosc 16 0000 MHz U2Xn 0 U2Xn 1 Rate bps UBRRn Error UBRRn Error 2400 416 0 1 832 0 0 4800 207 0 2 416 0 1 9600 103 0 2 207 0 2 14 4k 68 0 6 138 0 1 19 2k 51 0 2 103 0 2 28 8k 34 0 8 68 0 6 38 4k 25 0 2 51 0 2 57 6k 16 2 1 34 0 8 76 8k 12 0 2 25 0 2 115 2k 8 3 5 16 2 1 230 4k 3 8 5 8 3 5 250k 3 0 0 7 0 0 0 5M 1 0 0 3 0 0 1M 0 0 0 1 0 0 Max 1 1 Mbps 2 Mbps 1 UBRRn 0 Error 0 0 15 169 Automotive m J 7735B AVR 12 07 es A 169 Automotive 19 USI Universal Serial Interface 19 1 Overview 7735B AVR 12 07 The Universal Serial Interface or USI provides the basic hardware resources needed for serial communication Combined with a mini
48. 0 0 0 0 0 Bit 7 1 Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled The individual inter rupt enable control is then performed in separate control registers If the Global Interrupt Enable Register is cleared none of the interrupts are enabled independent of the individual interrupt enable settings The I bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts The I bit can also be set and cleared by the application with the SEI and CLI instructions as described in the instruction set reference Bit6 T Bit Copy Storage The Bit Copy instructions BLD Bit LoaD and BST Bit STore use the T bit as source or desti nation for the operated bit A bit from a register in the Register File can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction Bit5 H Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations Half Carry Is useful in BCD arithmetic See the Instruction Set Description for detailed information e Bit4 S Sign Bit S N The S bit is always an exclusive or between the Negative Flag N and the Two s Complement Overflow Flag V See the Instruction Set Description for detailed information Bit 3 V Two s Complement Overflow Flag The Two s Complement Overflow Flag V support
49. 0 4 4 mA i WDT enabled 3V 6 20 uA WDT enabled 5V 13 36 uA Power down mode WDT disabled 0 2 12 uA WDT disabled 5V 0 3 20 Analog Comparator Voc 5V Vacio Input Offset Voltage Vin 2 lt 19 0 Analog Comparator Voc 5V Input Leakage Current Vin 2 2 5 Analog Comparator Voc 2 7V 750 ACPD Propagation Delay Voc 4 0V 500 Note 1 Max means the highest value where the pin is guaranteed to be read as low 2 Min means the lowest value where the pin is guaranteed to be read as high Although each port can sink more than the test conditions 20 mA at Voc 5V 10 mA at 3V for Port B and 10 mA at Vcc 5V 5 mA at for all other ports under steady state conditions non transient the following must be observed TQFP Package 1 The sum of all IOL for all ports should not exceed 400 mA 2 The sum of all IOL for ports AO A7 C4 C7 G2 should not exceed 100 mA 3 The sum of all IOL for ports B7 EO E7 G3 G5 should not exceed 100 mA 4 The sum of all IOL for ports DO D7 CO GO G1 should not exceed 100 mA 5 The sum of all IOL for ports FO F7 should not exceed 100 mA If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test condition All bits set in the Power Reduction Registe
50. 0 External Interrupt Request 0 0 1 1 Timer CounterO Compare Match 1 0 0 Timer CounterO Overflow 1 0 1 Timer Counter Compare Match B 1 1 0 Timer Counter1 Overflow 1 1 1 Timer Counter1 Capture Event DIDRO Digital Input Disable Register 0 Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 0 ADC7D ADCOD ADC7 0 Digital Input Disable When this bit is written logic one the digital input buffer on the corresponding ADC pin is dis abled The corresponding PIN Register bit will always read as zero when this bit is set When an analog signal is applied to the ADC7 0 pin and the digital input from this pin is not needed this bit should be written logic one to reduce power consumption in the digital input buffer A MEL 231 AMEL 22 LCD Controller 22 1 Features 22 2 Overview 22 2 1 232 Definitions Display Capacity of 25 Segments and Four Common Terminals Support Static 1 2 1 3 and 1 4 Duty Support Static 1 2 1 3 Bias On chip LCD Power Supply only One External Capacitor needed Display Possible in Power save Mode for Low Power Consumption Software Selectable Low Power Waveform Capability Flexible Selection of Frame Frequency Software Selection between System Clock or an External Asynchronous Clock Source Equal Source and Sink Capability to maximize LCD Life Time LCD Interrupt Can be Used for Display Data Update or Wake up from Sleep Mo
51. 1 and BS1 to 0 The status of the Extended Fuse bits can now be read at DATA 0 means programmed Set OE to 0 BS2 to 0 and BS1 to 1 The status of the Lock bits can now be read at DATA 0 means programmed Set OE to 1 34 169 Automotive sue 7735B AVR 12 07 ATmega169P Automotive Figure 26 6 Mapping Between BS1 BS2 and the Fuse and Lock Bits During Read Fuse Low Byte Extended Fuse Byte BS2 Lock Bits Fuse High Byte BS2 26 7 13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows refer to Programming the Flash on page 299 for details on Command and Address loading 1 A Load Command 0000 1000 2 B Load Address Low Byte 0x00 0x02 3 Set OE to 0 and BS to 0 The selected Signature byte can now be read at DATA 4 Set OE to 1 26 7 14 Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows refer to Programming the Flash on page 299 for details on Command and Address loading 1 Load Command 0000 1000 2 B Load Address Low Byte 0x00 3 Set OE to 0 and BS1 to 1 The Calibration byte can now be read at DATA 4 Set OE to 1 26 7 15 Parallel Programming Characteristics Figure 26 7 Parallel Programming Timing Including some General Timing Requirements txLWL XTAL1 XHXL Data amp Contol DATA XA0 1 BS1 B
52. 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature C 169 Automotive m u H 7735B AVR 1 2 07 es 169 Automotive Figure 28 29 BOD Thresholds vs Temperature BOD Level is 2 7V BOD THRESHOLDS vs TEMPERATURE BOD level 2 70v E 1 0 a a 2 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature C Figure 28 30 Bandgap Voltage vs Temperature BANDGAP VOLTAGE vs TEMPERATURE 1 2 4 1 18 1 16 1 14 5 1 12 5 S44 m 1 08 m 1 06 1 04 1 02 i 45 25 5 15 35 55 75 95 115 Temperature C A MEL 347 7735B AVR 12 07 AMEL Figure 28 31 Analog Comparator Offset Voltage vs Common Mode Voltage Voc 5V ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE Voo 5V 0 008 abc 0 006 25C gt r 40C 8 0 004 gt 2 0 002 5 8 9 Q o 1 5 2 2 5 3 3 5 4 4 5 5 Common Mode Voltage V Figure 28 32 Analog Comparator Offset Voltage vs Common Mode Voltage Vec 2 7V ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE Massy 0 003 85C 0 002 25C gt 2 0 001 S 40C gt 0 g O 0 001 9 0 002 o 0 003 0 0 5 1 1
53. 1024 From prescaler 1 1 0 External clock source on TO pin Clock on falling edge 1 1 1 External clock source on TO pin Clock on rising edge If external pin modes are used for the Timer Counter0 transitions on the TO pin will clock the counter even if the pin is configured as an output This feature allows software control of the counting TCNTO Timer Counter Register Bit T 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Timer Counter Register gives direct access both for read and write operations to the Timer Counter unit 8 bit counter Writing to the TCNTO Register blocks removes the compare match on the following timer clock Modifying the counter TCNTO while the counter is running introduces a risk of missing a compare match between TCNTO and the OCROA Register OCROA Output Compare Register A Bit 7 6 5 4 3 2 1 0 0x27 0x47 oco 1 OCROA Read Write RW RW RW AW HW RW RW RW Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8 bit value that is continuously compared with the counter value A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OCOA pin TIMSKO Timer Counter 0 Interrupt Mask Register Bit Z 6 5 4 3 2 1 0 0x6 a T Te Read Write R R R R R R R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 1 OCIEOA Timer Counter0 Output Compare M
54. 2 1 0 D ECR Read Write R R R R R W R W R W R W Initial Value 0 0 0 0 0 0 X 0 Bits 7 4 Res Reserved Bits These bits are reserved and will always read as zero Bit 3 EERIE EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the bit in SREG is set Writing EERIE to zero disables the interrupt The EEPROM Ready interrupt generates a constant inter rupt when EEWE is cleared Bit 2 EEMWE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written When EEMWE is set setting EEWE within four clock cycles will write data to the EEPROM at AMEL 7735B AVR 12 07 28 AMEL the selected address If EEMWE is zero setting EEWE will have no effect When EEMWE has been written to one by software hardware clears the bit to zero after four clock cycles See the description of the EEWE bit for an EEPROM write procedure Bit 1 EEWE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM When address and data are correctly set up the EEWE bit must be written to one to write the value into the EEPROM The EEMWE bit must be written to one before a logical one is written to EEWE oth erwise no EEPROM write takes place EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM When the corre
55. 5 Boundary scan 2 2 1 0 259 24 6 Boundary scan Order 2 0 2224 0 enne nenne 269 24 7 Boundary scan Description Language Files 275 24 8 Boundary scan Related Register Memory 2 276 25 Boot Loader Support Read While Write Self Programming 277 25 IE CAUU OS cores tis ip reet T T eases 277 Meu M 277 25 3 Application and Boot Loader Flash Sections 277 25 4 Read While Write and No Read While Write Flash Sections 278 25 5 Boot Loader Lock Bits eine 281 25 6 Entering the Boot Loader Program 282 25 7 Addressing the Flash During Self Programming 2 283 25 8 Self Programming the Flash 2 240 04 0 284 25 9 Register Description 291 7735 07 07 26 Memory Programming tem 293 26 1 Program And Data Memory Lock Bits 293 26 26056 DIIS T T E 294 26 3 Signature Bytes ce ua ire idee 296 26 4 Calibration Byte p E eh hse ER eerta 296 26 5 5126 296 26 6 Parallel Programming Parameters Pin Mapping
56. 7 Output Compare Units The 16 bit comparator continuously compares TCNT1 with the Output Compare Register OCR1x If TCNT equals OCR1x the comparator signals a match A match will set the Output Compare Flag OCF 1x at the next timer clock cycle If enabled OCIE1x 1 the Output Com pare Flag generates an Output Compare interrupt The OCF1x Flag is automatically cleared when the interrupt is executed Alternatively the OCF 1x Flag can be cleared by software by writ ing a logical one to its I O bit location The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode WGM13 0 bits and Compare Output mode COM1x1 0 bits The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation See Modes of Operation on page 118 A special feature of Output Compare unit A allows it to define the Timer Counter TOP value i e counter resolution In addition to the counter resolution the TOP value defines the period time for waveforms generated by the Waveform Generator Figure 14 4 shows a block diagram of the Output Compare unit The small n in the register and bit names indicates the device number n 1 for Timer Counter 1 and the x indicates Output Compare unit A B The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded Figure 14
57. Automotive memme 7735B AVR 1 2 07 Nea 169P Automotive Figure 28 37 AREF External Reference Current vs Voc AREF EXTERNAL REFERENCE CURRENT vs Voc larer uA Figure 28 38 Watchdog Timer Current vs Voc WATCHDOG TIMER CURRENT vs Voc 85 C 25 C 14 40 C 12 10 3 8 L1 I 0 1 5 2 2 5 3 8 5 4 4 5 5 5 5 A MEL 351 7735B AVR 12 07 AMEL Figure 28 39 Analog Comparator Current vs Voc ANALOG COMPARATOR CURRENT vs Vec 120 100 4 25C 85C lt 60 0 1 1 5 2 2 5 3 3 5 4 45 5 5 5 Voc V Figure 28 40 Programming Current vs Vcc PROGRAMMING CURRENT vs Vcc 25 40 C 20 25 C 15 8 85 V 32 169 Automotive mememe 7735B AVR 1 2 07 es Nea 169P Automotive 28 13 Current Consumption in Reset and Reset Pulsewidth Figure 28 41 Reset Supply Current vs 0 1 1 0 MHz Excluding Current Through The Reset Pull up RESET SUPPLY CURRENT vs FREQUENCY 0 1 1 0 MHz EXCLUDING CURRENT THROUGH THE RESET PULLUP 0 18 5 5V 0 16 5 0V 4 5V lt 0 1 4 0V Sed 8 0 08 3 3V v 2 7V 1 8V 0 02 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz Figure 28 42 Reset Supply Current vs 1 16 MHz
58. Clock SCL pins are bi directional and uses open collector output drives The output drivers are enabled by setting the corresponding bit for SDA and SCL in the DDR Register When the output driver is enabled for the SDA pin the output driver will force the line SDA low if the output of the Shift Register or the corresponding bit in 1 0 the PORT Register is zero Otherwise the SDA line will not be driven i e it is released When the SCL pin output driver is enabled the SCL line will be forced low if the corresponding bit in the PORT Register is zero or by the start detector Otherwise the SCL line will not be driven The SCL line is held low when a start detector detects a start condition and the output is enabled Clearing the Start Condition Flag USISIF releases the line The SDA and SCL pin inputs is not affected by enabling this mode Pull ups on the SDA and SCL port pin are disabled in Two wire mode Two wire mode Uses SDA and SCL pins 1 1 Same operation as for the Two wire mode described above except that the SCL line is also held low when a counter overflow occurs and is held low until the Counter Overflow Flag USIOIF is cleared Note 1 The DI and USCK pins are renamed to Serial Data SDA and Serial Clock SCL respectively to avoid confusion between the modes of operation Bit 3 2 USICS1 0 Clock Source Select These bits set the clock source for the Shift Register and counter The data output
59. ENDED DIFFERENTIAL SELECTION Y DIFFERENTIAL AMPLIFIER ADC MULTIPLEXER OUTPUT ADC1 ADCO 2 NEG INPUT MUX La The ADC converts an analog input voltage to a 10 bit digital value through successive approxi mation The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB Optionally AVCC or an internal 1 1V reference voltage may be con nected to the AREF pin by writing to the REFSn bits in the ADMUX Register The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity The analog input channel is selected by writing to the MUX bits in ADMUX Any of the ADC input pins as well as GND and a fixed bandgap voltage reference can be selected as single ended inputs to the ADC The ADC is enabled by setting the ADC Enable bit ADEN in ADCSRA Volt age reference and input channel selections will not go into effect until ADEN is set The ADC does not consume power when ADEN is cleared so it is recommended to switch off the ADC before entering power saving sleep modes The ADC generates a 10 bit result which is presented in the ADC Data Registers ADCH and ADCL By default the result is presented right adjusted but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX 26 169 Automotive m 7735B AVR 12 07 es Nea 169P Automotive I
60. H capacitor through the series resistance combined resistance in the input path The ADC is optimized for analog signals with an output impedance of approximately 10 KQ or less If such a source is used the sampling time will be negligible If a source with higher imped ance is used the sampling time will depend on how long time the source needs to charge the S H capacitor with can vary widely The user is recommended to only use low impedant sources with slowly varying signals since this minimizes the required charge transfer to the S H capacitor Signal components higher than the Nyquist frequency fapc 2 should not be present for either kind of channels to avoid distortion from unpredictable signal convolution The user is advised to remove high frequency components with a low pass filter before applying the signals as inputs to the ADC Figure 21 8 Analog Input Circuitry ADCn 1 100 14 pF ATmega169P Automotive m EE 7735B AVR 12 07 Nea 169P Automotive 21 7 2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements If conversion accuracy is critical the noise level can be reduced by applying the following techniques a Keep analog signal paths as short as possible Make sure analog tracks run over the analog ground plane and keep them well away from high speed switching digital track
61. High Byte Ox1E Z register Low Byte Ox1F Z register High Byte Most of the instructions operating on the Register File have direct access to all registers and most of them are single cycle instructions As shown in Figure 5 2 each register is also assigned a data memory address mapping them directly into the first 32 locations of the user Data Space Although not being physically imple mented as SRAM locations this memory organization provides great flexibility in access of the registers as the X Y and Z pointer registers can be set to index any register in the file 14 169 Automotive m 7735B AVR 12 07 X A 169 Automotive 5 5 1 The X register Y register and Z register 5 6 Stack Pointer 7735B AVR 12 07 The registers R26 R31 have some added functions to their general purpose usage These reg isters are 16 bit address pointers for indirect addressing of the data space The three indirect address registers X Y and Z are defined as described in Figure 5 3 on page 15 Figure 5 3 X Y and Z registers 15 XH XL 0 Xregister R27 0x1B R26 0x1A 15 YH YL 0 R29 0x1D R28 0x1C 15 ZH ZL 0 Z register R31 0x1F R30 0x1E In the different addressing modes these address registers have functions as fixed displacement automatic increment and automatic decrement see the instruction set reference for details The Stack is mainl
62. INTFO 63 Alm L 357 7735B AVR 12 07 NENNEN Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1B 0x3B Reserved 0x1A 0x3A Reserved 0x19 0x39 Reserved 0x18 0x38 Reserved 0x17 0x37 TIFR2 OCF2A TOV2 156 0x16 0x36 TIFR1 ICF1 OCF1B OCF1A TOV1 134 0x15 0x35 TIFRO 0 105 0 14 0 34 PORTG PORTG5 PORTG4 PORTG3 PORTG2 PORTG1 PORTGO 90 0x13 0x33 DDRG 0065 0064 0063 0062 DDG1 DDGO 90 0x12 0x32 PING PINGS PING4 PING3 PING2 PING1 PINGO 90 0x11 0x31 PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTFO 90 0x10 0x30 DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDFO 90 OxOF Ox2F PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINFO 90 OxOE 0x2E PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTEO 89 0x0D 0x2D DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDEO 89 0 0 0 2 PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINEO 90 0 0x2B PORTD PORTD7 PORTD6 5 4 2 PORTD1 PORTDO 89 0 2 DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDDO 89 0x09 0x29 PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PINDO 89 0x08 0x28 PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORT
63. LCDEN Note 1 See About Code Examples page 10 Before a re initialization is done the LCD controller driver should be disabled Updating the LCD Display memory LCDDRO LCDDRt1 LCD Blanking LCDBL Low power waveform LCDAB and contrast control LCDCCR are latched prior to every new frame There are no restrictions on writing these LCD Register locations but an LCD data update may be split between two frames if data are latched while an update is in progress To avoid this an interrupt routine can be used to update Display memory LCD Blanking Low power waveform and con trast control just after data are latched 169 Automotive sume 7735B AVR 12 07 es 169 Automotive In the example below we assume SEG10 and COM1 and SEG4 in COMO are the only segments changed from frame to frame Data are stored in r20 and r21 for simplicity Assembly Code Example LCD update LCD Blanking and Low power waveform are unchanged Update Display memory sts LCDDRO r20 sts LCDDR6 r21 ret Code Example Void LCD update unsigned char datal data2 Update Display memory LCDDRO datal LCDDR6 data2 LCD Blanking and Low power waveform are unchanged xf Note 1 See About Code Examples on page 10 22 4 3 Disabling the LCD 7735B AVR 12 07 In some application it may be necessary to disable the LCD This is the case
64. OCn value at MAX must correspond to the result of an up counting Compare Match timer starts counting from a value higher than the one in 2 and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up A MEL 147 AMEL 16 7 Timer Counter Timing Diagrams The following figures show the Timer Counter in synchronous mode and the timer clock is therefore shown as a clock enable signal In asynchronous mode clk o should be replaced by the Timer Counter Oscillator clock The figures include information on when Interrupt Flags are set Figure 16 8 contains timing data for basic Timer Counter operation The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode Figure 16 8 Timer Counter Timing Diagram no Prescaling BOTTOM BOTTOM 1 Figure 16 9 shows the same timing data but with the prescaler enabled Figure 16 9 Timer Counter Timing Diagram with Prescaler 0 8 TOVn Figure 16 10 shows the setting of OCF2A in all modes except CTC mode 148 169 Automotive memm ATmega169P Automotive Figure 16 10 Timer Counter Timing Diagram Setting of OCF2A with Prescaler fi 8 OCRnx 2 OCRnx 1 OCRnx OCRnx Value Figure 16 11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode Figure 16 11 Timer Counter Timing Diagram Clear Timer
65. PCMSB Because 70 ene 218 is not used the ZPCMSB equals PCMSB 1 Bit in Z register that is mapped to PAGEMSB Because ER Z0 is not used the ZPAGEMSB equals PAGEMSB 1 PCPAGE PC 12 6 713 77 Program Counter page address Page select for Page Erase and Page Write Program Counter word address Word select for filling PCWORD PC 5 0 26 21 temporary buffer must be zero during Page Write operation Note 1 Z15 Z14 always ignored 20 should be zero for all SPM commands byte select for the LPM instruction See Addressing the Flash During Self Programming on page 283 for details about the use of Z pointer during Self Programming 20 169 Automotive memm 7735B AVR 12 07 es 169 Automotive 25 9 Register Description 25 9 1 SPMCSR Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to con trol the Boot Loader operations Bit 7 6 5 4 3 2 1 0 oer Breset PGWRT PGERS Read Write R W R R R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 SPMIE SPM Interrupt Enable When the SPMIE bit is written to one and the I bit in the Status Register is set one the SPM ready interrupt will be enabled The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is cleared Bit6 RWWSB Read While Write Section B
66. PINEZ PET PINE PINE Read Write R W R W R W R W R W R W R W R W Initial Value N A N A N A N A N A N A N A N A PORTF Port Data Register Bit 7 6 5 4 3 2 1 0 0x11 0x31 PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTFO PORTF Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 DDRF Port F Data Direction Register Bit 7 6 5 4 3 2 1 0 T Bore bors T pors oor ober Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 PINF Port F Input Pins Address Bit 7 6 5 4 3 2 1 0 OxOF Ox2F PINF7 PINF6 5 PINF4 PINF3 PINF2 PINF1 PINFO Read Write R W R W R W R W R W R W R W R W Initial Value N A N A N A N A N A N A N A N A PORTG Port G Data Register Bit 7 6 5 4 3 2 1 0 _ ___ Ponca Pontos PORTGz Pontet Porte Read Write R R R R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 DDRG Port Data Direction Register Bit 7 6 5 4 3 2 1 0 0x13 0x33 T 0555 5063 6062 5661 6660 Read Write R R R R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 PING Port Input Pins Address Bit 7 6 5 4 3 2 1 0 pines pings PmGz Pwer Pme Read Write R R R R W R W R W R W R W Initial Value 0 0 0 N A N A N A N A N A 169 Automotive sume 7735B AVR 12 07 es 169 Automotive
67. Pin Change Interrupts XCK AINO PCINT2 USART External Clock or Analog Comparator Positive Input or Pin Change Interrupt2 PE2 PE1 TXD PCINT1 USART Transmit Pin or Pin Change Interrupt1 PEO RXD PCINTO USART Receive Pin or Pin Change InterruptO PCINT7 Port E Bit 7 PCINT7 Pin Change Interrupt Source 7 The PE7 pin can serve as an external interrupt source CLKO Divided System Clock The divided system clock can be output on the PE7 pin The divided system clock will be output if the CKOUT Fuse is programmed regardless of the PORTE7 and DDE7 settings It will also be output during reset DO PCINT6 Port E Bit 6 DO Universal Serial Interface Data output PCINT6 Pin Change Interrupt Source 6 The PE6 pin can serve as an external interrupt source DI SDA PCINTS Port E Bit 5 DI Universal Serial Interface Data input SDA Two wire Serial Interface Data PCINT5 Pin Change Interrupt Source 5 The 5 pin can serve as an external interrupt source USCK SCL PCINT4 Port E Bit 4 USCK Universal Serial Interface Clock SCL Two wire Serial Interface Clock PCINT4 Pin Change Interrupt Source 4 The PE4 pin can serve as an external interrupt source AIN1 PCINTS Port E Bit 3 AIN1 Analog Comparator Negative input This pin is directly connected to the negative input of the Analog Comparator PCINT3 Pin Change Interrupt Source 3 The PE3 pin can serve as an external interrupt sourc
68. Register Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software To read the Lock bits load the Z pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR When an LPM instruc tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR the value of the Lock bits will be loaded in the destination register The BLBSET and SPMEN bits will auto clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles When BLB SET and SPMEN are cleared LPM will work as described in the Instruction set Manual Bit 5 4 3 2 7 6 1 0 Re T Re i82 The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits To read the Fuse Low byte load the Z pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR the value of the Fuse Low byte FLB will be loaded in the destination register as shown below Refer to Table 26 5 on page 295 for a detailed description and mapping of the Fuse Low byte Bit 7 6 5 4 3 2 1 0 7 FBO Similarly when reading the Fuse High byte load 0x0003 in the Z pointer When an LPM instruc tion is executed within three cycles after the BLBSET and S
69. SPMCSR is cleared This means that the interrupt can be used instead of polling the SPMCSR Register in software When using the SPM interrupt the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading How to move the interrupts is described in Interrupts on page 56 25 8 5 Consideration While Updating BLS Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11 unprogrammed An accidental write to the Boot Loader itself can corrupt the entire Boot Loader and further software updates might be impossible If it is not necessary to change the Boot Loader software itself it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes 25 8 6 Prevent Reading the RWW Section During Self Programming During Self Programming either Page Erase or Page Write the RWW section is always blocked for reading The user software itself must prevent that this section is addressed during the self programming operation The RWWSB in the SPMCSR will be set as long as the RWW section is busy During Self Programming the Interrupt Vector table should be moved to the BLS as described in Interrupts on page 56 or the interrupts must be disabled Before addressing the RWW section after the programming is completed the user software must clear the RWWSB by writing the RWWSRE
70. Settings 1 UPMOn Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled Even Parity 1 1 Enabled Odd Parity Bit 3 USBSn Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter The Receiver ignores this setting Table 18 6 USBSn Bit Settings USBSn Stop Bit s 0 1 bit 1 2 bit Bit 2 1 UCSZ1n 0 Character Size The UCSZ1n 0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits Character SiZe in a frame the Receiver and Transmitter use Table 18 7 57 Bits Settings UCSZn2 UCSZ1n 0 570 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit Bit 0 UCPOLn Clock Polarity This bit is used for synchronous mode only Write this bit to zero when asynchronous mode is used The UCPOLn bit sets the relationship between data output change and data input sample and the synchronous clock XCK Table 18 8 UCPOLn Bit Settings 0 Rising XCK Edge Falling XCK Edge 1 Falling XCK Edge Rising XCK Edge A MEL 193 7735B AVR 12 07 AMEL 18 10 5 UBRRLn and UBRRHn USART Baud Rate Registers Bit 15 14 13 12 11 10 9 8 0x05 0 4 UBRRn 7 0 UBRRLn 7 6 5 4 3 2 1 0 Read Write R R R R R W R W R W R W R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0
71. TWO WIRE USI TWO WIRE SDA PORTE5 USI_SCL_HOLD DDO 0 DDE5 PORTE4 DDE4 USI USI TWO WIRE 1 3 PVOE CKOUT WIRE DDES USI TWO WIRE DDE4 PVOV ClKyo DO 0 0 PTOE 0 USITC PCINT5 PCIEO PCINT4 PCIEO DIEOE PCINT7 PCIEO PCINT6 PCIEO USISIE DIEOV 1 1 1 1 DI SDA INPUT USCKL SCL INPUT DI PCINT7 INPUT PCINT6 INPUT AIO Note 1 CKOUT is one if the CKOUT Fuse is programmed 169 Automotive m s 7735B AVR 12 07 169 Automotive Table 12 17 Overriding Signals for Alternate Functions in Signal PE3 AIN1 PE2 XCK AINO PE1 TXD Name PCINT3 PCINT2 PCINT1 PEO RXD PCINTO PUOE 0 0 TXENn RXENn PUOV 0 0 0 PORTEO PUD DDOE 0 0 TXENn RXENn DDOV 0 1 0 PVOE 0 XCK OUTPUT ENABLE TXENn 0 PVOV 0 XCK TXD 0 PTOE DIEOE SANTO 1 PCIEO DIEOV PCINT3 PCIEO PCINT2 PCIEO 1 1 DI PCINT3 INPUT XCK PCINT2 INPUT PCINT1 INPUT RXD PCINTO INPUT AIO AIN1 INPUT AINO INPUT Note 1 AINOD and AIN1D is described in DIDR1 Digital Input Disable Register 1 on page 214 Alternate Functions of Port F 7735B AVR 12 07 The Port F has an alternate function as analog input for the ADC as shown in Table 12 18 If some Port F pins are configured as outputs it is esse
72. The Clock Select logic block controls which clock source and edge the Timer Counter uses to increment or decrement its value The Timer Counter is inactive when no clock source is selected The output from the Clock Select logic is referred to as the timer clock AMEL s 7735B AVR 12 07 13 2 2 Definitions AMEL The double buffered Output Compare Register OCROA is compared with the Timer Counter value at all times The result of the compare can be used by the Waveform Generator to gener ate a PWM or variable frequency output on the Output Compare pin OCOA See Output Compare Unit on page 93 for details The compare match event will also set the Compare Flag OCFOA which be used to generate an Output Compare interrupt request Many register and bit references in this section are written in general form A lower case n replaces the Timer Counter number in this case 0 A lower case x replaces the Output Com pare unit number in this case unit A However when using the register or bit defines in a program the precise form must be used i e TCNTO for accessing Timer CounterO counter value and so on The definitions in Table 13 1 are also used extensively throughout the document Table 13 1 Timer Counter Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00 MAX The counter reaches its MAXimum when it becomes OxFF decimal 255 TOP The counter reaches the TOP when it becomes e
73. The counter is then cleared at the following timer clock cycle The timing diagram for the fast PWM mode is shown in Figure 14 7 The figure shows fast PWM mode when or ICR1 is used to define TOP The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1 The OC1x Interrupt Flag will be set when a compare match occurs Figure 14 7 Fast PWM Mode Timing Diagram OCRnx TOP Update and TOVn Interrupt Flag Set and Interrupt RUE UI EA IRE RACER OR EU E EMO Y Flag Set or ICFn Y Y Y Y P Interrupt Flag Set NE Interrupt on TOP Y Y TCNTn y Y y OCnx 1 0 2 OCnx 1 0 3 Period 1 2 3 4 5 6 T gt 8 The Timer Counter Overflow Flag TOV1 is set each time the counter reaches TOP In addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A 169 Automotive EN 7735B AVR 12 07 es 169 Automotive or ICR1 is used for defining the TOP value If one of the interrupts are enabled the interrupt han dler routine can be used for updating the TOP and compare values When changing the TOP value the program must ensure
74. Two wire mode The start condition detector is working asynchronously and can therefore wake up the processor from the Power down sleep mode However the protocol used might have restrictions on the SCL hold time Therefore when using this feature in this case the Oscillator start up time set by the CKSEL Fuses see Clock Systems and their Distribution on page 30 must also be taken into the consideration Refer to the USISIF bit description on page 207 for further details Clock speed considerations Maximum frequency for SCL and SCK is f_CK 4 This is also the maximum data transmit and receieve rate in both two and three wire mode In two wire slave mode the Two wire Clock Con trol Unit will hold the SCL low until the slave is ready to receive more data This may reduce the actual data rate in two wire mode 19 3 Alternative USI Usage 19 3 1 19 3 2 19 3 3 19 3 4 19 3 5 206 When the USI unit is not used for serial communication it can be set up to do alternative tasks due to its flexible design Half duplex Asynchronous Data Transfer By utilizing the Shift Register in Three wire mode it is possible to implement a more compact and higher performance UART than by software only 4 bit Counter The 4 bit counter can be used as a stand alone counter with overflow interrupt Note that if the counter is clocked externally both clock edges will generate an increment 12 bit Timer Counter Combining the USI 4 b
75. a Brown out Reset USI start condition interrupt an external level interrupt on INTO or a pin change interrupt can wake up the MCU This sleep mode basically halts all generated clocks allowing operation of asynchronous modules only Note that if a level triggered interrupt is used for wake up from Power down mode the changed level must be held for some time to wake up the MCU Refer to External Interrupts on page 61 for details When waking up from Power down mode there is a delay from the wake up condition occurs until the wake up becomes effective This allows the clock to restart and become stable after having been stopped The wake up period is defined by the same CKSEL Fuses that define the Reset Time out period as described in Clock Sources on page 31 AMEL n 8 5 8 6 8 7 42 AMEL Power save Mode When the SM2 0 bits are written to 011 the SLEEP instruction makes the MCU enter Power save mode This mode is identical to Power down with one exception If Timer Counter2 and or the LCD controller are enabled they will keep running during sleep The device can wake up from either Timer Overflow or Output Compare event from Timer Counter2 if the corresponding Timer Counter2 interrupt enable bits are set in TIMSK2 and the Global Interrupt Enable bit in SREG is set It can also wake up from an LCD controller interrupt If neither Timer Counter2 nor the LCD controller is running Power down mode is recommended in
76. as listed on Alternate Functions of Port A on page 73 Port B PB7 PBO Port B is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port B output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port B pins that are externally pulled low will source current if the pull up resistors are activated The Port B pins are tri stated when a reset condition becomes active even if the clock is not running Port B has better driving capabilities than the other ports Port B also serves the functions of various special features of the ATmega169P as listed on Alternate Functions of Port B on page 74 Port C PC7 PCO Port C is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port C output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port C pins that are externally pulled low will source current if the pull up resistors are activated The Port C pins are tri stated when a reset condition becomes active even if the clock is not running Port C also serves the functions of special features of the ATmega169P as listed on Alternate Functions of Port C on page 77 Port D PD7 PD0 Port D is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port D output buffers have symmetrical drive characteristics with both
77. byte using programming instruction 4b Load address Low byte using programming instruction 4c Load data using programming instructions 4d and 4e Repeat steps 4 and 5 for all data bytes in the page Write the data using programming instruction 4f Poll for EEPROM write complete using programming instruction 4g or wait for tw gi refer to Table 26 13 on page 306 9 Repeat steps 3 to 8 until all data have been programmed Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM 26 9 19 Reading the EEPROM ON d c Enter JTAG instruction PROG COMMANDS Enable EEPROM read using programming instruction 5a Load address using programming instructions 5b and 5c Read data using programming instruction 5d Repeat steps 3 and 4 until all data have been read Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM Or qm o Noct A MEL 323 7735B AVR 12 07 AMEL 26 9 20 Programming the Fuses 26 9 21 26 9 22 Enter JTAG instruction PROG_COMMANDS Enable Fuse write using programming instruction 6a Load data high byte using programming instructions 6b A bit value of 0 will program the corresponding fuse a 1 will unprogram the fuse Write Fuse High byte using programming instruction 6c Poll for Fuse write complete using programming instruction 6d or wait for ty ay refer to Table 26 13 on page 306 Load data low byte using programming i
78. bytes is popped back from the Stack the Stack Pointer is incremented by two and the I bit in SREG is set 169 Automotive memm 7735B AVR 12 07 ees 169 Automotive 6 AVR Memories This section describes the different memories in the ATmega169P The AVR architecture has two main memory spaces the Data Memory and the Program Memory space In addition the ATmega169P features an EEPROM Memory for data storage All three memory spaces lin ear and regular 6 1 In System Reprogrammable Flash Program Memory 7735B AVR 12 07 The ATmega169P contains 16K bytes On chip In System Reprogrammable Flash memory for program storage Since all AVR instructions are 16 or 32 bits wide the Flash is organized as 8K x 16 For software security the Flash Program memory space is divided into two sections Boot Program section and Application Program section The Flash memory has an endurance of at least 10 000 write erase cycles The ATmega169P Program Counter PC is 13 bits wide thus addressing the 8K program memory locations The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in Boot Loader Support Read While Write Self Programming on page 277 Memory Programming on page 293 contains a detailed description on Flash data serial downloading using the SPI pins or the JTAG interface Constant tables can be allocated within the entire prog
79. chain is not latched The active states are Shift DR The Reset Register is shifted by the TCK input Mandatory JTAG instruction selecting the Bypass Register for Data Register The active states are Capture DR Loads a logic 0 into the Bypass Register Shift DR The Bypass Register cell between TDI and TDO is shifted 24 5 Boundary scan Chain 24 5 1 The Boundary scan chain has the capability of driving and observing the logic levels on the digi tal I O pins as well as the boundary between digital and analog logic for analog circuitry having off chip connection Scanning the Digital Port Pins 7735B AVR 12 07 Figure 24 3 shows the Boundary scan Cell for a bi directional port pin with pull up function The cell consists of a standard Boundary scan cell for the Pull up Enable PUExn function and a bi directional pin cell that combines the three signals Output Control OCxn Output Data ODxn and Input Data IDxn into only a two stage Shift Register The port and pin indexes are not used in the following description The Boundary scan logic is not included in the figures in the datasheet Figure 24 4 shows a simple digital port pin as described in the section I O Ports on page 65 The Boundary scan details from Figure 24 3 replaces the dashed box in Figure 24 4 A MEL 259 AMEL When no alternate port function is present the Input Data ID corresponds to the PINxn Reg ister value b
80. cycle waveform output in fast PWM mode can be achieved by set ting OC1A to toggle its logical level on each compare match COM1A1 0 1 This applies only if OCR1A is used to define the TOP value WGM13 0 15 The waveform generated will have a maximum frequency of focia 2 when OCR1A is set to zero 0x0000 This feature is similar to the OC1A toggle in CTC mode except the double buffer feature of the Output Com pare unit is enabled in the fast PWM mode A MEL 121 7735B AVR 12 07 14 9 4 122 ATmega169P Automotive AMEL Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode WGM13 0 1 2 3 10 or 11 provides a high resolution phase correct PWM waveform generation option The phase correct PWM mode is like the phase and frequency correct PWM mode based on a dual slope operation The counter counts repeatedly from BOTTOM 0x0000 to TOP and then from TOP to BOTTOM In non inverting Compare Output mode the Output Compare OC1x is cleared on the compare match between TCNT1 and OCR1x while upcounting and set on the compare match while downcounting In inverting Output Compare mode the operation is inverted The dual slope operation has lower maximum operation frequency than single slope operation However due to the symmetric feature of the dual slope PWM modes these modes are preferred for motor control applications The PWM resolution for the phase correct PWM mode c
81. external clock edge detector by a Timer CounterO Compare Match or by software using USICLK or USITC strobe bits The clock source depends of the setting of the USICS1 0 bits For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit This feature is enabled by write a one to the USICLK bit while setting an external clock source USICS1 1 Note that even when no wire mode is selected USIWM1 0 0 the external clock input USCK SCL are can still be used by the counter 19 4 3 USICR USI Control Register Bit 7 6 5 4 3 2 1 0 0xB8 USISIE USIWMO USICS1 USICSO USICLK USITC USICR Read Write R W R W R W R W R W R W Ww Initial Value 0 0 0 0 0 0 0 0 The Control Register includes interrupt enable control wire mode setting Clock Select setting and clock strobe Bit 7 USISIE Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt If there is a pending inter rupt when the USISIE and the Global Interrupt Enable Flag is set to one this will immediately be executed Refer to the USISIF bit description on page 207 for further details Bit 6 USIOIE Counter Overflow Interrupt Enable Setting this bit to one enables the Counter Overflow interrupt If there is a pending interrupt when the USIOIE and the Global Interrupt Enable Flag is set to one this will immediately be executed Refer to the USIOIF bit de
82. filtered The filter function requires four successive equal valued samples of the ICP1 pin for changing its output The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled Bit6 ICES1 Input Capture Edge Select This bit selects which edge on the Input Capture pin ICP1 that is used to trigger a capture event When the ICES1 bit is written to zero a falling negative edge is used as trigger and when the ICES 1 bit is written to one a rising positive edge will trigger the capture 169 Automotive um 7735B AVR 12 07 es Nea 169P Automotive When a capture is triggered according to the ICES1 setting the counter value is copied into the Input Capture Register ICR1 The event will also set the Input Capture Flag ICF1 and this can be used to cause an Input Capture Interrupt if this interrupt is enabled When the ICR1 is used as TOP value see description of the WGM13 0 bits located in the and the TCCR1B Register the ICP1 is disconnected and consequently the Input Cap ture function is disabled Bit 5 Reserved Bit This bit is reserved for future use For ensuring compatibility with future devices this bit must be written to zero when TCCR1B is written Bit 4 3 WGM13 2 Waveform Generation Mode See TCCR1A Register description Bit 2 0 CS12 0 Clock Select The three Clock Select bits select the clock source to be used b
83. followed when accessing the 16 bit registers These procedures are described in the section Accessing 16 bit Registers on page 109 The Timer Counter Control Registers TCCR1A B are 8 bit registers and have no CPU access restrictions Interrupt requests abbreviated to Int Req in the figure signals are all visible in the Timer Interrupt Flag Register TIFR1 All interrupts are individually masked with the Timer Interrupt Mask Register TIMSK1 TIFR1 and TIMSK1 are not shown in the figure The Timer Counter can be clocked internally via the prescaler or by an external clock source on the T1 pin The Clock Select logic block controls which clock source and edge the Timer Counter uses to increment or decrement its value The Timer Counter is inactive when no clock source is selected The output from the Clock Select logic is referred to as the timer clock The double buffered Output Compare Registers OCR1A B are compared with the Timer Counter value at all time The result of the compare can be used by the Waveform Gener ator to generate a PWM or variable frequency output on the Output Compare pin OC1A B See A MEL 107 14 2 2 14 2 3 108 Definitions Compatibility AMEL Output Compare Units page 115 The compare match event will also set the Compare Match Flag OCF1A B which can be used to generate an Output Compare interrupt request The Input Capture Register can capture the Timer Counter value a
84. for pin Pxn RDx READ DDRx QCxn OUTPUT CONTROL for pin Pxn WRx WRITE PORTx ODxn OUTPUT DATA to pin Pxn RRx READ PORTx REGISTER IDxn INPUT DATA from pin Pxn RPx READ PORTx PIN SLEEP SLEEP CONTROL X WPx WRITE PINx REGISTER CLKyo VO CLOCK A MEL 261 7735B AVR 12 07 AMEL 24 5 2 Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard reset operation and 12V active high logic for High Voltage Parallel programming An observe only cell as shown in Figure 24 5 is inserted both for the 5V reset signal RSTT and the 12V reset signal RSTHV Figure 24 5 Observe only Cell ShiftDR Cell From System Pin e gt To System Logic 1 V A From ClockDR Previous Cell 24 5 3 Scanning the Clock Pins The AVR devices have many clock options selectable by fuses These are Internal RC Oscilla tor External Clock High Frequency Crystal Oscillator Low frequency Crystal Oscillator and Ceramic Resonator Figure 24 6 shows how each Oscillator with external connection is supported in the scan chain The Enable signal is supported with a general Boundary scan cell while the Oscillator clock out put is attached to an observe only cell In addition to the main clock the timer Oscillator is scanned in the same way The output from the internal RC Oscillator is not scanned as this Oscillator does not have external connections Figure 24 6 Boundary scan Cells for Oscillators an
85. hardware The user soft ware can poll this bit and wait for a zero before writing the next byte When EEWE has been set the CPU is halted for two cycles before the next instruction is executed The user should poll the EEWE bit before starting the read operation If a write operation is in progress it is neither possible to read the EEPROM nor to change the EEAR Register The calibrated Oscillator is used to time the EEPROM accesses Table 6 1 lists the typical pro gramming time for EEPROM access from the CPU Table 6 1 EEPROM Programming Time Number of Calibrated Symbol RC Oscillator Cycles Typical Programming Time EEPROM write from CPU 27 072 3 3 ms The following code examples show one assembly and one C function for writing to the EEPROM To avoid that interrupts will occur during execution of these functions the examples assume that interrupts are controlled e g by disabling interrupts globally The examples also assume that no Flash Boot Loader is present in the software If such code is present the EEPROM write function must also wait for any ongoing SPM command to finish AMEL 24 AMEL Assembly Code Example EEPROM_write Wait for completion of previous write sbic EECR EEWE rjmp EEPROM write Set up address 118 117 in address register out EEARH r18 out EEARL r17 Write data r16 to Data Register out EEDR r16 Write logical one to EEMWE sbi EECR EEMWE Start eeprom write
86. in the description of the Self Program ming are given Table 25 6 Boot Size Configuration Boot Reset N 8 Address n 2 Boot Loader End Start Boot S 8 S Application Flash Flash Application Loader m m A Section Section Section Section 1 1 128 2 0x0000 0x1F7F Ox1F80 0x1FFF 0x1F7F 0x1F80 words 256 1 0 4 0 0000 1 Ox1F00 Ox1FFF Ox1EFF 0x1F00 words 0 1 die 8 0x0000 0x1DFF 0x1E00 Ox1FFF Ox1DFF 0x1E00 words 1024 0 0 16 0x0000 0x1BFF 0x1C00 Ox1FFF Ox1BFF 0x1C00 words Note 1 The different BOOTSZ Fuse configurations are shown in Figure 25 2 289 7735B AVR 12 07 AMEL AMEL Table 25 7 Read While Write Limit Section Pages Address Read While Write section RWW 112 0x0000 0x1BFF No Read While Write section NRWW 16 0 1 00 Ox1FFF Note 1 For details about these two section see NRWW No Read While Write Section on page 278 and RWW Read While Write Section on page 278 Table 25 8 Explanation of different variables used in Figure 25 3 and the mapping to the Z pointer Corresponding Variable Z value Description Most significant bit in the Program Counter The ROUSE Program Counter is 13 bits PC 12 0 Most significant bit which is used to address the words PAGEMSB 5 within one page 64 words in a page requires six bits PC 5 0 Bit in Z register that is mapped to
87. in the same state as before shutdown Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption See Supply Current of I O modules on 336 for examples In all other sleep modes the clock is already stopped 169 Automotive m um 7735B AVR 12 07 169 Automotive 8 8 8 8 1 8 8 2 8 8 3 8 8 4 8 8 5 7735B AVR 12 07 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system In general sleep modes should be used as much as possible and the sleep mode should be selected so that as few as possible of the device s functions are operating All functions not needed should be disabled In particular the following modules may need special consideration when trying to achieve the lowest possible power consumption Analog to Digital Converter If enabled the ADC will be enabled in all sleep modes To save power the ADC should be dis abled before entering any sleep mode When the ADC is turned off and on again the next conversion will be an extended conversion Refer to ADC Analog to Digital Converter page 215 for details on ADC operation Analog Comparator When entering Idle mode the Analog Comparator should be disabled if not used When entering ADC Noise Reduction mode the Analog Comparator should be disabled In other s
88. instruction PROG_COMMANDS 2 Enable Flash read using programming instruction 3a 3 Load address using programming instructions 3b and 3c 4 Read data using programming instruction 3d 5 Repeat steps 3 and 4 until all data have been read A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction Enter JTAG instruction PROG COMMANDS Enable Flash read using programming instruction 3a 3 Load the page address using programming instructions 3b and 3c PCWORD refer to Table 26 7 on page 296 is used to address within one page and must be written as 0 4 Enter JTAG instruction PROG PAGEREAD 5 Readthe entire page or Flash by shifting out all instruction words in the page or Flash starting with the LSB of the first instruction in the page Flash and ending with the MSB of the last instruction in the page Flash The Capture DR state both captures the data from the Flash and also auto increments the program counter after each word is read Note that Capture DR comes before the shift DR state Hence the first byte which is shifted out contains valid data 6 Enter JTAG instruction PROG COMMANDS 7 Repeat steps 3 to 6 until all data have been read 26 9 18 Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed see Performing Chip Erase on page 322 Enter JTAG instruction PROG_COMMANDS Enable EEPROM write using programming instruction 4a Load address High
89. is altered The remaining locations remain unchanged If polling RDY BSY is not used the user must wait at least twp eeprom before issuing the next page See Table 26 15 In a chip erased device no OxFF in the data file s need to be programmed 6 Any memory location can be verified by using the Read instruction which returns the con tent at the selected address at serial output MISO 7 Atthe end of the programming session RESET can be set high to commence normal operation 8 Power off sequence if needed Set RESET to 1 Turn power off Table 26 15 Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay lwp FusE 4 5 ms lwp FLASH 4 5 ms lwp EEPROM 9 0 ms lwp ERASE 9 0 ms Figure 26 11 Serial Programming Waveforms MOSI MISO SERIAL CLOCK INPUT SCK 4 MEL 309 7735B AVR 12 07 26 8 3 Serial Programming Instruction set Table 26 16 and Figure 26 12 on page 311 describes the Instruction set Table 26 16 Serial Programming Instruction Set AMEL Instruction Format Instruction Operation Byte 1 Byte 2 Byte 3 Byte4 Programming Enable AC 53 00 00 Chip Erase Program Memory EEPROM AC 80 00 00 Poll RDY BSY FO 00 00 data byte out Load Instructions Load Extended Address byte 4D 00 Extended adr 00 Load Progr
90. is blanked after completing the current frame All seg ments and common pins are connected to GND discharging the LCD Display memory is preserved Display blanking should be used before disabling the LCD to avoid DC voltage across segments and a slowly fading image A MEL 237 AMEL 22 3 8 Port Mask For LCD with less than 25 segment terminals it is possible to mask some of the unused pins and use them as ordinary port pins instead Refer to Table 22 3 for details Unused common pins are automatically configured as port pins 169 Automotive memme 7735B AVR 12 07 es Nea 169P Automotive 22 4 LCD Usage The following section describes how to use the LCD 22 4 1 LCD Initialization Prior to enabling the LCD some initialization must be preformed The initialization process nor mally consists of setting the frame rate duty bias and port mask LCD contrast is set initially but can also be adjusted during operation Consider the following LCD as an example Figure 22 8 LCD usage example LCD a 1b 2f 2b X 2g a 7 7 1 2 2c 24 N COMO COM1 5 2 169 SEO 46 Display Number of common terminals Number of segment terminals Bias system Drive system Operating vo
91. is shown in Table 26 17 The state sequence when shifting in the programming commands is illustrated in Figure 26 16 A MEL 315 AMEL Figure 26 15 Programming Command Register TDI 5 T R B E 5 Flash EEPROM Lock Bits R 5 5 D A T A TDO 169 Automotive m N 7735B AVR 12 07 es 169 Automotive Table 26 17 JTAG Programming Instruction Set address high bits b address low bits 0 Low byte 1 High Byte data out i data in x don t care 4a Enter EEPROM Write 0100011_00010001 XXXXXXX_XXXXXXXX Instruction TDI Sequence TDO Sequence Notes 0100011_ 10000000 XXXXXXX_XXXXXXXX 1a Chip Erase 0110001 10000000 XXXXXXX_XXXXXXXX P 0110011 10000000 XXXXXXX_XXXXXXXX 0110011 10000000 XXXXXXX_XXXXXXXX 1b Poll for Chip Erase Complete 0110011_ 10000000 XXXXXOX_XXXXXXXX 2 2a Enter Flash Write 0100011 00010000 XXXXXXX_XXXXXXXX 2b Load Address High Byte 0000111_aaaaaaaa XXXXXXX_XXXXXXXX 9 2c Load Address Low Byte 0000011 bbbbbbbb XXXXXXX_XXXXXXXX 2d Load Data Low Byte 0010011 iiiiiiii XXXXXXX_XXXXXXXX 2e Load Data High Byte 0010111 iiiiiiii XXXXXXX_XXXXXXXX 0110111 00000000 XXXXXXX_XXXXXXXX 2f Latch Data 1110111_00000000 XXXXXXX_XXXXXXXX 1 0110111 00000000 XXXXXXX_XXXXXXXX 0110111_00000000 XXXXXXX_XXXXXXXX 0110101_00000000 XXXXXXX_XXXXXXXX Eg VH
92. latch ensures that the output is changed at the opposite edge of the sampling of the data input DI SDA when using external clock source USCK SCL When software strobe or Timer CounterO Compare Match clock option is selected the output latch is transparent and therefore the output is changed immediately Clearing the USICS1 0 bits enables software strobe option When using this option writing a one to the USICLK bit clocks both the Shift Register and the counter For external clock source USICS1 1 the USICLK bit is no longer used as a strobe but selects between external clocking and software clocking by the USITC strobe bit A MEL 209 7735B AVR 12 07 AMEL Table 19 2 shows the relationship between the USICS1 0 and USICLK setting and clock source used for the Shift Register and the 4 bit counter Table 19 2 Relations between the USICS1 0 and USICLK Setting USICS1 USICSO USICLK Shift Register Clock Source 4 bit Counter Clock Source 0 0 0 No Clock No Clock 0 0 1 Software clock strobe Software clock strobe USICLK USICLK 0 1 X Timer Counter0 Compare Timer CounterO Compare Match Match 1 0 0 External positive edge External both edges 1 1 0 External negative edge External both edges 1 0 1 External positive edge Software clock strobe USITC 1 1 1 External negative edge Software clock strobe USITC Bit 1 USICLK Clock Strobe Writing a one to this bit location st
93. logical one to the FOC2A bit an immediate compare match is forced on the Waveform Generation unit The OC2A output is changed according to its 2 1 0 bits setting Note that the FOC2A bit is implemented as a strobe Therefore it is the value present in the COM2A1 0 bits that determines the effect of the forced compare A FOCAA strobe will not generate any interrupt nor will it clear the timer CTC mode using OCR2A as TOP The FOC2A bit is always read as zero Bit 6 3 WGM21 0 Waveform Generation Mode These bits control the counting sequence of the counter the source for the maximum TOP counter value and what type of waveform generation to be used Modes of operation supported by the Timer Counter unit are Normal mode Clear Timer on Compare match CTC mode and two types of Pulse Width Modulation PWM modes See Table 16 2 and Modes of Operation on page 143 Table 16 2 Waveform Generation Mode Bit Description WGM 1 WGM20 Timer Counter Mode of Update of TOV2 Flag Mode CTC2 PWM2 Operation TOP OCR2A at Set on 0 0 0 Normal OxFF Immediate MAX 1 0 1 PWM Phase Correct OxFF TOP BOTTOM 2 1 0 CTC OCR2A Immediate MAX 3 1 1 Fast PWM OxFF BOTTOM MAX Note 1 The CTC2 and PWM2 bit definition names are now obsolete Use the WGM21 0 definitions However the functionality and location of these bits are compatible with previous versions of the timer 5 4 COM2A1 0 Compare

ATMEL AVR microcontroller ATmega169P handbook data (1)(1)

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