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ATMEL AT90CAN64 English technology data

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1. jam Oscillator ShiftDR Cell EXTEST Next t ShiftDR Cell From Digital Logic gt 0 ENABLE OUTPUT gt To System Logic 1 0 1 D QD Q 0 T E From ClockDR UpdateDR Previous From ClockDR Cell Previous Cell Table 23 5 summaries the scan registers for the external clock pin XTAL1 oscillators with XTAL1 XTAL2 connections as well as external Timer2 clock pin TOSC1 and 32kHz Timer2 Oscillator Table 23 5 Scan Signals for the Oscillators 9 Scanned Clock Line when not Used EXTCLKEN EXTCLK XTAL1 External Main Clock 0 Enable Signal Scanned Clock Line Clock Option External Crystal 1 SECO SEU External Ceramic Resonator OSC32EN OSC32CK Low Freq External Crystal 1 TOSKON TOSCK 32 kHz Timer2 Oscillator 1 Notes 1 Do not enable more than one clock source as clock at a time 2 Scanning an Oscillator output gives unpredictable results as there is a frequency drift between the internal Oscillator and the JTAG TCK clock If possible scanning an external clock is preferred 3 The main clock configuration is programmed by fuses As a fuse is not changed run time the main clock configuration is considered fixed for a given application The user is advised to scan the same clock option as to be used in the final system The enable signals are sup ported in the scan chain because the system logic can disable clo
2. OCnx Period 7 12 The Timer Counter Overflow Flag TOVn is set each time the counter reaches TOP In addition the OCnA or ICFn flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value If one of the interrupts are enabled the interrupt han dler routine can be used for updating the TOP and compare values COMnx1 0 2 When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers If the TOP value is lower than any of the Compare Registers a compare match will never occur between the TCNTn and the OCRnx Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value The ICRn Register is not double buffered This means that if ICRn is changed to a low value when the counter is running with none or a low prescaler value there is a risk that the new ICRn value written is lower than the current value of TCNTn The result will then be that the counter will miss the compare match at the TOP value The counter will then have to count to the MAX value OxFFFF and wrap around starting at 0x0000 before the compare match can occur The OCRnA Register however is double buffered This feature allows the OCRnA
3. Signal Name PE7 INT7 ICP3 PEG INT6 T3 5 PEA4 INT4 OC3B PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 OC3C ENABLE OC3B ENABLE PVOV 0 0 OC3C OC3B PTOE 0 0 0 0 DIEOE INT7 ENABLE INT6 ENABLE INT5 ENABLE INT4 ENABLE DIEOV INT7 ENABLE INT6 ENABLE INT5 ENABLE INT4 ENABLE DI 22 n 1 INT5 INPUT INT4 INPUT AlO 7679F CAN 1 1 07 Table 9 17 Overriding Signals for Alternate Functions in PE3 PEO Signal Name PE3 AIN1 OC3A PE2 AINO XCKO PE1 PDO TXDO PEO PDI RXDO PUOE 0 0 TXENO RXENO PUOV 0 0 0 PORTEO PUD DDOE 0 0 TXENO RXENO DDOV 0 0 1 0 PVOE OC3A ENABLE UMSELO TXENO 0 PVOV OC3A XCKO OUTPUT TXDO 0 PTOE 0 0 0 0 DIEOE AIN1D AINOD 0 0 DIEOV 0 0 0 0 DI 0 XCKO INPUT RXDO AIN1 INPUT AINO INPUT 1 AINOD AIN1D is described in Digital Input Disable Register 1 DIDR1 272 9 3 7 Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 9 18 If some Port F pins are configured as outputs it is essential that these do not switch when a con version is in progress This might corrupt the result of the conversion If the JTAG interface is enabled the pull up resistors on pins PF7 TDI PF5 TMS and PF4 will be activated even if a reset occurs Table 9 18 Port Pin PF7 Port F Pin
4. Frequency Figure 28 3 Active Supply Current vs Vcc Internal RC Oscillator 8 MHz ACTIVE SUPPLY CURRENT vs Vcc Internal RC Oscillator 8 MHz NM A AMEL 7679F CAN 11 07 e 5 50V 5 00V 4 50V e 4 00V e 3 30V g 3 00V amp 2 70V e 85 C m 25 C amp 40 C 385 ATMEL Figure 28 4 Active Supply Current vs Vcc Internal RC Oscillator 1 MHz ACTIVE SUPPLY CURRENT vs Vcc Internal RC Oscillator 1 MHz 2 5 e 85 C z 25 C amp _ 40 mA 2 5 3 3 5 4 4 5 5 5 5 Figure 28 5 Active Supply Current vs Vcc 32 kHz Watch Crystal ACTIVE SUPPLY CURRENT vs Vcc 32 kHz Watch Crystal 140 120 e 25 C Icc uA 2 5 3 3 5 4 4 5 5 5 5 AT90CAN32 64 128 memme 28 2 Idle Supply Current Figure 28 6 Supply Current vs Frequency 0 1 1 0 MHz IDLE SUPPLY CURRENT vs FREQUENCY 25 C 0 1 1 MHz 1 6 1 4 1 2 a e 5 50V 1 5 00V lt 4 50V 0 8 e 4 00V 2 ae e 3 30V 3 00 Tn pec 2 70 0 2 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz Figure 28 7 Idle Supply Current vs Frequency 1 16 MHz
5. 320 7679F CAN 11 07 AMEL 425 AMEL 24 Boot Loader Support Read While Write Self Programming 321 24 Foa E 321 24 2 Application and Boot Loader Flash Sections 321 24 3 Read While Write and No Read While Write Flash Sections 321 24 4 Boot Loader Lock BiS ote emer tees 324 24 5 Entering the Boot Loader 325 24 6 Addressing the Flash During Self Programming 2 327 24 7 Self Programming the 328 25 Memory Programming 336 25 1 Program and Data Memory Lock Bits 336 25 2 RUSE 337 253 Sigriat re BVIes ences idi avenues 339 25 4 Calibration Byte tene eee iere 339 25 5 Parallel Programming Overview 339 25 6 Parallel nennen 342 25 7 SPI Serial Programming Overview 2 348 25 8 Serial Programming sse 349 25 9 JTAG Programming Overview sse enne nnne 352 26 Electrical Characteristics 0 itti 365 26 1 Absolute Maximum Ratings sssrin anaana ae RAA eee 365 26 2 DC Characteristics 2 24 4 044 0 00 0 00000 enemies nnne nnn 366 26 3 External Clock Drive Characterist
6. SRL2 SRL1 SRLO Sector Addressing Lower sector N A Upper sector XMem start OXFFFF Lower sector XMem start 0x1 Upper sector 0x2000 OxFFFF Lower sector XMem start Upper sector 0x4000 OxFFFF Lower sector XMem start OxSFFF i i Upper sector 0x6000 OxFFFF Lower sector XMem start Ox7FFF Upper sector 0 8000 OxFFFF Lower sector XMem start OX9FFF Upper sector 0xA000 OxFFFF Lower sector XMem start OxBFFF Upper sector 0 000 OxFFFF Lower sector XMem start OxDFFF Upper sector 0 000 OxFFFF Note 1 See Table 4 1 on page 18 for XMem start setting Bit 3 2 SRW11 SRW10 Wait state Select Bits for Upper Sector The SRW11 and SRW10 bits control the number of wait states for the upper sector of the exter nal memory address space see Table 4 4 Bit 1 0 SRW01 SRWOO Wait state Select Bits for Lower Sector SRWO01 and SRWOO bits control the number of wait states for the lower sector of the exter nal memory address space see Table 4 4 Table 4 4 Wait States SRWn1 SRWnO Wait States 0 0 No wait states 0 1 Wait one cycle during read write strobe 1 0 Wait two cycles during read write strobe Wait two cycles during read write and wait one cycle before driving out new address 1 1 Note 1 n 0 or 1 lower upper sector For further details of the
7. The alternate pin configuration is as follows PCINT7 ICP3 Port E Bit 7 INT7 External Interrupt source 7 The PE7 pin can serve as an external interrupt source ICP3 Input Capture Pin3 The PE7 pin can act as an input capture pin for Timer Counter3 INT6 T3 Port E Bit 6 INT6 External Interrupt source 6 The pin can serve as an external interrupt source Timer Counter3 counter source INT5 OC3C Port E Bit 5 INT5 External Interrupt source 5 The pin can serve as an External Interrupt source OC3C Output Compare Match C output The pin can serve as an External output for the Timer Counter3 Output Compare C The pin has to be configured as an output DDE5 set to serve this function The OC3C pin is also the output pin for the PWM mode timer function INT4 OC3B Port E Bit 4 INT4 External Interrupt source 4 The PE4 pin can serve as an External Interrupt source OC3B Output Compare Match B output The PE4 pin can serve as an External output for the Timer Counter3 Output Compare B The pin has to be configured as an output DDE4 set one to serve this function The OC3B pin is also the output pin for the PWM mode timer function AIN1 OC3A Port E Bit 3 AIN1 Analog Comparator Negative input This pin is directly connected to the negative input of the Analog Comparator OC3A Output Compare Match A output The PES pin can serve as an Externa
8. 14 3 8 Reset and Interrupt Handling 15 4 Memories RM aranean 18 4 1 In System Reprogrammable Flash Program Memory 18 4 2 SRAM Data aaa aaea iiia Nae 19 4 3 EEPROM Data Memory 1 22 4 4 pex 27 4 5 External Memory Interface nennen 27 4 6 General Purpose Registers 36 5 CIOCK 37 5 1 Clock Systems and their Distribution 2 37 5 2 esse c 38 5 3 Default Glock Source eee adn ince eon ede 38 5 4 Orystal Oscillator e tete tt EI e Ee E Doa eae rte tatus 39 5 5 Low frequency Crystal Oscillator 40 5 6 Calibrated Internal RC Oscillator 41 5 7 External Glok sssini 42 5 8 Clock Output BU fer 43 AMEL 421 7679F CAN 11 07 AMEL 5 9 Timer Counter2 Oscillator 2 2 404 20 43 5 10 System Clock nens 44 6 Power Management and Sleep Modes s 46 6 1 Mode aa 47 6 2 ADC Noise
9. Description Operation Flags Clocks IN Rd P In Port Rd e None 1 OUT P Rr Out Port lt None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Hd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep function None 1 WDR Watchdog Reset see specific descr for WDR timer None 1 BREAK Break For On chip Debug Only None N A m 7679F CAN 1 1 07 31 Ordering Information 1 AMEL Notes 1 tion and minimum quantities 32 Packaging Information Package Type 64 Lead Thin 1 0 mm 0 03937 in Plastic Gull Wing Quad Flat Package Green 64 Lead QFN Exposed Die Attach Pad D2 E2 5 4 0 1mm 0 212 0 004 in Ordering Code Speed MHz Power Supply V Package Operation Range Product Marking AT90CAN32 16AI 16 27 55 A264 Industrial 40 to 85 C AT90CAN32 16AI AT90CAN32 16MI 16 27 55 764 1 Industrial 40 to 85 C AT90CAN32 16MI AT90CAN32 16AU 16 2 7 5 5 A2 64 40 to 85 C AT90CAN32 16AU AT90CAN32 16MU 16 27 55 764 1 a 40 1 85 AT90CAN32 16MU AT90CAN64 16AI 16 27 55 A264 Industrial 40 to 85 C AT90CAN64 16AI AT90CAN64 16MI 16 27 55 264 2 Industrial 40 to 85 C 64 16 AT90CAN64 16AU 16 2 7 5 5 A2 64 2 40710 85 C AT90CAN64 16AU AT90CAN6
10. SDA from 7 Receiver We NA a INL SLA R W STOP REPEATED START or Next Data Byte Data Byte 18 3 5 Combining Address and Data Packets Into a Transmission A transmission basically consists of a START condition a SLA R W one or more data packets and a STOP condition An empty message consisting of a START followed by a STOP condi tion is illegal Note that the Wired ANDing of the SCL line can be used to implement handshaking between the master and the slave The slave can extend the SCL low period by pulling the SCL line low This is useful if the clock speed set up by the master is too fast for the slave or the slave needs extra time for processing between the data transmissions The slave extending the SCL low period will not affect the SCL high period which is determined by the master As a consequence the slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle Figure 18 6 shows a typical data transmission Note that several data bytes can be transmitted between the SLA R W and the STOP condition depending on the software protocol imple mented by the application software Figure 18 6 Typical Data Transmission AddrLSB Data MSB DataLSB ACK SCL START SLA R W Data Byte STOP 18 4 Multi master Bus Systems Arbitration and Synchronization 7679F CAN 11 07 The TWI protocol al
11. 35 Fou E 25 20 e 85 m 25 C 2 15 40 10 5 0 T 0 0 5 1 1 5 2 2 5 VoL V 28 8 Pin Thresholds and Hysteresis Figure 28 23 1 0 Input Threshold Voltage vs Vcc Pin Read as 1 VO PIN INPUT THRESHOLD VOLTAGE vs VCC VH PIN READ AS 1 2 1 75 _ 15 gt 85 C 1 25 25 C a 40 C 1 0 75 0 5 2 5 3 3 5 4 4 5 5 5 5 AMEL 395 7679F CAN 11 07 AMEL Figure 1 Input Threshold Voltage vs Vcc Vi Pin Read as 0 VO PIN INPUT THRESHOLD VOLTAGE vs VCC VIL VO PIN READ AS 0 2 1 75 zo 15 e 85 1 25 a 25 C amp 40 C E o 0 75 0 5 2 5 3 3 5 4 4 5 5 5 5 Vcc V Figure 2 1 0 Input Hysteresis vs Vcc VO PIN INPUT HYSTERESIS vs VCC 0 6 0 5 _ 0 4 e 85 E 0 3 25 C amp 40 C 0 2 0 1 0 2 5 3 3 5 4 4 5 5 5 5 396 AT90CAN32 64128 7679F CAN 1 1 07 28 9 BOD Thresholds and Analog Comparator Offset Figure 28 24 BOD Thresholds vs Temperature BOD level is 4 1 BOD THRESHOLDS vs TEMPERATURE BOD level is 4 1V 44 4 2 c 4 3 e Rising Vcc 5 m Falling Vcc 3 8 H 3 6 3 4 60 40 20 0 20 40 60 80 100 Figure 28 25 BOD Thresholds vs Temperature BOD level is
12. Table 12 3 shows the 1 0 bit functionality when the WGMO 1 0 bits are set to fast PWM mode Table 12 3 Compare Output Mode Fast PWM Mode 1 Description 0 0 Normal port operation OCOA disconnected 0 1 Reserved 1 0 Clear OCOA on compare match Set OCOA at TOP 1 1 Set OCOA on compare match Clear OCOA at TOP 110 7679F CAN 11 07 Note 1 Aspecial case occurs when OCROA equals TOP and 1 is set In this case the com pare match is ignored but the set or clear is done at TOP See Fast PWM Mode on page 105 for more details Table 12 4 shows the 1 0 bit functionality when the WGMO01 0 bits are set to phase cor rect PWM mode Table 12 4 Compare Output Mode Phase Correct PWM Mode COMOA1 Description 0 0 Normal port operation OCOA disconnected 0 1 Reserved Clear OCOA on compare match when up counting 1 0 Set OCOA on compare match when downcounting Set OCOA on compare match when up counting Clear OCOA on compare match when downcounting Note 1 Aspecial case occurs when OCROA equals TOP and 1 is set In this case the com pare match is ignored but the set or clear is done at TOP See Phase Correct PWM Mode on page 107 for more details Bit 2 0 CS02 0 Clock Select The three Clock Select bits select the clock source to be used by the Timer Counter Table 12
13. 0 gt e lt OCFnC Int Req Generation From Analog Comparator Ouput Noise Canceler gt ICFn Int Req Edge Detector BEB RPP Reese TCCRnA TCCRnB TCCRnC Note 1 Refer to Figure 1 2 page 5 or Figure 1 3 on page 6 Table 9 6 on page 76 and Table 9 15 on page 83 for Timer Counter1 and 3 pin placement and description The Timer Counter TCNTn Output Compare Registers OCRnx and Input Capture Register ICRn are all 16 bit registers Special procedures must be followed when accessing the 16 bit registers These procedures are described in the section Accessing 16 bit Registers on page 116 The Timer Counter Control Registers TCCRnx are 8 bit registers and have no CPU access restrictions Interrupt requests abbreviated to Int Req in the figure signals are all visible in the Timer Interrupt Flag Register TIFRn All interrupts are individually masked with the Timer Interrupt Mask Register TIMSKn TIFRn and TIMSKn are not shown in the figure The Timer Counter can be clocked internally via the prescaler or by an external clock source on the Tn pin The Clock Select logic block controls which clock source and edge the Timer Counter 14 2 64 1 28 m NE 7679F CAN 1 1 07 13 2 2 Definitions 13 2 3 Compatibility 7679F CAN 11 07 uses to increment or decrement its value The Timer Counter is inactive when no clock source
14. Table 26 9 External Data Memory Characteristics Voc 4 5 5 5 Volts SRWn1 1 SRWn0 0 8 MHz Oscillator Variable Oscillator 0 1 Oscillator Frequency 0 0 16 MHz 10 Read Low to Data Valid 325 3 0 tere 50 ns 12 tuin RD Pulse Width 365 3 0 tci c 10 ns 15 Data Valid to WR High 375 3 0 tei ns 16 WR Pulse Width 365 3 0 terc 10 ns Table 26 10 External Data Memory Characteristics Vcc 4 5 5 5 Volts SRWn1 1 SRWnO 1 Bormes 8 MHz Oscillator Variable Oscillator Uni Min Max Min Max 0 1 Oscillator Frequency 0 0 16 MHz 10 Read Low to Data Valid 200 3 0 tci c 50 ns 12 span RD Pulse Width 365 3 0 tore 10 ns 14 twupx Data Hold After WR High 240 2 0 tci c 10 ns 15 tpywu Data Valid to WR High 375 3 0 tore ns 16 tw wu WR Pulse Width 365 3 0 tci c 10 ns Table 26 11 External Data Memory Characteristics Vcc 2 7 5 5 Volts No Wait state 4 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min Max Min Max 0 terc Oscillator Frequency 0 0 16 MHz Y ALE Pulse Width 235 toc 15 ns 2 er Address Valid A to ALE Low 115 0 5 toe 10 ns 3a 1 Address Hold After ALE Low 5 5 js write access E pa E after ALE Low 5 5 ris tac Address Valid C to ALE Low 115 0 5 tore 10 ns 5 tavRL Address Valid to RD Low 235 1 0 tei cj 15 ns 6 tavwL Address V
15. 5V 15 Power Supply Current 16 MHz 5V 29 mA Active Mode external clock 4 MHz 4 8 MHz 3V 8 MHz 5V Power Supply Current 16 MHz Voc 5V 17 mA loc Idle Mode external clock 4 MHz 3 mA 8 MHz Vec 3V 5 mA WDT enabled 5V 40 Power Supply Current WDT disabled 5V 18 Power down Mode WDT enabled Voc 3V 25 WDT disabled Veg 3V 10 Analog Comparator Voc 5V Vacio Input Offset Voltage Vin 2 0 20 36 90 32 64 1 28 7679F CAN 11 07 40 C to 85 C Voc 2 7V to 5 5V unless otherwise noted Continued Symbol lACLK Parameter Condition Min Typ Max Units Analog Comparator Voc 5V Input Leakage Current Vin Voc 2 50 50 nA taciD Analog Comparator Voc 2 7V 170 ns Propagation Delay Common Mode Vcc 2 Voc 5 0 180 ns Notes 1 2 3 Max means the highest value where the pin is guaranteed to be read as low Min means the lowest value where the pin is guaranteed to be read as high Although each I O port can sink more than the test conditions 20 mA at 5V 10 mA at under steady state conditions non transient the following must be observed TQFP and QFN Package 1 The sum of all IOL for all ports should not exceed 400 mA 2 The sum of all IOL for ports AO A7 G2 C7
16. ISCn1 ISCnO Description 0 0 The low level of INTn generates an interrupt request 0 1 Any logical change on INTn generates an interrupt request 1 0 The falling edge of INTn generates asynchronously an interrupt request 1 1 The rising edge of INTn generates asynchronously an interrupt request Note 1 n 3 2 10r0 When changing the ISCn1 ISCn0O bits the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register Otherwise an interrupt can occur when the bits are changed Table 10 2 Asynchronous External Interrupt Characteristics Symbol Faameter min Typ Wax unns t Minimum pulse width for asynchronous 50 INT external interrupt ns Synchronous External Interrupt Control Register B EICRB Bit 7 6 4 3 2 1 0 ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 EICRB Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 7 0 ISC71 ISC70 ISC41 ISC40 Synchronous External Interrupt 7 4 Sense Control Bits The External Interrupts 7 4 are activated by the external pins INT7 4 if the SREG I flag and the corresponding interrupt mask in the EIMSK is set The level and edges on the external pins that activate the interrupts are defined in Table 10 3 The value on the INT7 4 pins are sampled before detecting edges If edge or toggle interrupt is selected pulses that last longer than one clock period will generate an interrupt
17. is 300 mV voltage on ADC2 is 500 mV ADCR 512 1 300 500 2560 41 0x029 ADCL will thus read 0x40 and ADCH will read OxOA Writing zero to ADLAR right adjusts the result ADCL 0x00 ADCH 0x29 26 AT90CAN32 64128 mm 7679F CAN 1 1 07 21 8 ADC Register Description 21 8 1 ADC Multiplexer Selection Register ADMUX 7679F CAN 11 07 Bit 7 6 5 4 3 2 1 0 REFS muxs moxi MUxo Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 REFS1 0 Reference Selection Bits These bits select the voltage reference for the ADC as shown in Table 21 3 If these bits are changed during a conversion the change will not go in effect until this conversion is complete ADIF in ADCSRA is set The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin Table 21 3 Voltage Reference Selections for ADC REFS1 REFSO Voltage Reference Selection 0 0 AREF Internal Vref turned off 0 1 AVcc with external capacitor on AREF pin 1 0 Reserved 1 1 Internal 2 56V Voltage Reference with external capacitor on AREF pin Bit 5 ADLAR ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register Write one to ADLAR to left adjust the result Otherwise the result is right adjusted Chan
18. Address Valid to RD Low 115 1 0 tere 10 ns 6 Address Valid to WR Low 115 1 0 tere 10 ns 7 tuw ALE Low to WR Low 47 5 67 5 0 5 tore 15 0 5 tec 5 2 ns 8 ALE Low to Low 47 5 67 5 0 5 tore 15 0 5 tec 57 ns 9 Data Setup to RD High 40 40 ns 10 Read Low to Data Valid 75 1 0 tere 50 ns 11 Data Hold After RD High 0 0 ns UE TS RD Pulse Width 115 1 0 terc 10 ns 13 Data Setup to WR Low 42 5 0 5 tore 20 ns 14 twupx Data Hold After WR High 115 1 0 tere 10 ns 15 tpywn Data Valid to WR High 125 1 0 tei ci ns 16 funt WR Pulse Width 115 1 0 terc 10 ns Notes 1 This assumes 50 clock duty cycle The half period is actually the high time of the external clock XTAL1 2 This assumes 50 clock duty cycle The half period is actually the low time of the external clock XTAL1 Table 26 8 External Data Memory Characteristics Voc 4 5 5 5 Volts 1 Cycle Wait state 8 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min Max Min Max 0 1 Oscillator Frequency 0 0 16 MHz 10 1 Read Low to Data Valid 200 2 0 tci c 50 ns eae RD Pulse Width 240 2 0 10 ns 15 Data Valid to WR High 240 20 teici ns 16 tawa WR Pulse Width 240 2 0 ty c 10 ns 375 7679F CAN 11 07 AMEL
19. BRP2 7 canen Read Write z R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 Bit 7 Reserved Bit This bit is reserved for future use For compatibility with future devices it must be written to zero when CANBTI is written Bit 6 1 BRP5 0 Baud Rate Prescaler ATMEL 257 AMEL The period of the CAN controller system clock Tscl is programmable and determines the individ ual bit timing BRP 5 0 1 Tscl clkio frequency If BRP 5 0 0 see Section 19 4 3 Baud Rate on page 242 and Section Bit 0 SMP Sample Point s on page 259 Bit 0 Reserved Bit This bit is reserved for future use For compatibility with future devices it must be written to zero when CANBTI is written 19 10 9 CAN Bit Timing Register 2 CANBT2 Bit 7 6 5 4 3 2 1 0 2 Read Write R W R W R W R W R W Initial Value 0 0 0 0 0 Bit 7 Reserved Bit This bit is reserved for future use For compatibility with future devices it must be written to zero when 2 is written Bit 6 5 SJW1 0 Re Synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers the control ler must re synchronize on any relevant signal edge of the current transmission The synchronization jump width defines the maximum number of clock cycles A bit period may be shortened or lengthened
20. COMMANDS Enable Signature byte read using programming instruction 9a Load address 0x00 using programming instruction 9b Read first signature byte using programming instruction 9c Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes respectively 25 9 3 12 Heading the Calibration Byte 1 Enter JTAG instruction PROG COMMANDS 2 Enable Calibration byte read using programming instruction 10a 3 Load address 0x00 using programming instruction 10b 4 Read the calibration byte using programming instruction 10c 334 90 32 64 1 28 memme 26 Electrical Characteristics 2 26 1 Absolute Maximum Ratings Industrial Operating Temperature 40 C to 85 C NOTICE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam Storage Temperature 65 C to 150 age to the device This is a stress rating only and functional operation of the device at these or Voltage on any Pin except RESET other conditions beyond those indicated in the with respect to 0 5V to Vcc40 5V operational sections of this specification is not implied Exposure to absolute maximum rating Voltage on RESET with respect to Ground 0 5V to 13 0V conditions for extended periods may affect device reliability Voltage on Voc with respect to Groun
21. INTF2 INTEO age 95 0x1B 0x3B Reserved AIMEL 407 ey AMEL Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3A Reserved 0x19 0x39 Reserved 0x18 0x38 TIFR3 ICF3 OCF3B OCF3A TOV3 page 143 0x17 0x37 TIFR2 OCF2A TOV2 page 162 0x16 0x36 TIFR1 ICF1 OCF1C OCF1B OCF1A TOV1 page 143 0x15 0x35 TIFRO OCFOA TOVO page 112 0x14 0x34 PORTG PORTG4 PORTG3 PORTG2 PORTG1 PORTGO page 92 0x13 0x33 DDRG DDG4 DDG3 DDG2 DDG1 DDGO page 92 0x12 0x32 PING PING4 PING2 PING1 PINGO page 92 0x11 0x31 PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTFO page 91 0x10 0x30 DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDFO page 91 OxOF 0x2F PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINFO page 92 OxOE 0 2 PORTE PORTE7 PORTE6 5 4 2 PORTE1 PORTEO page 91 Ox0D 0x2D DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDEO page 91 0 0 0x2C PINE PINE7 PINE6 PINES PINE4 PINES PINE2 PINE PINEO page 91 0x0B 0x2B PORTD PORTD7 PORTD6 5 4 2 PORTD1 PORTDO page 91 0x2A DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD DDDO page 91 0x09 0x29 PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PINDO page 91 0x08 0x28 PO
22. UBRRn UBRRn UBRRn Error UBRRn 2400 95 0 0 191 0 0 103 0 2 207 0 2 191 0 0 383 0 0 4800 47 0 0 95 0 0 51 0 2 103 0 2 95 0 0 191 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4k 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2k 11 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8k 7 0 0 15 0 0 8 3 5 16 2 1 15 0 0 31 0 0 38 4k 5 0 0 11 0 0 6 7 0 12 0 2 11 0 0 23 0 0 57 6k 3 0 0 7 0 0 3 8 5 8 3 5 7 0 0 15 0 0 76 8k 2 0 0 5 0 0 2 8 5 6 7 0 5 0 0 11 0 0 115 2k 1 0 0 3 0 0 1 8 5 3 8 5 3 0 0 7 0 0 230 4k 0 0 0 1 0 0 0 8 5 1 8 5 1 0 0 3 0 0 250k 0 7 8 1 7 8 0 0 0 1 0 0 1 7 8 3 7 8 500k 0 7 8 0 0 0 0 7 8 1 7 8 1 0 7 8 Max 230 4 Kbps 460 8 Kbps 250 Kbps 0 5 Mbps 460 8 Kbps 921 6 Kbps Note 1 UBRRn 0 Error 0 0 ATMEL 201 7679F CAN 11 07 AMEL Table 17 11 Examples of UBRRn Settings for Commonly Frequencies Continued Baud 8 0000 MHz fclk 10 000 MHz fcik 11 0592 MHz Rate U2Xn 0 U2Xn 1 U2Xn z 0 U2Xn 1 U2Xn 0 U2Xn 1 bps UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0 2 416 0 1 259 0 2 520 0 0 287 0 0 575 0 0 4800 103 0 2 207 0 2 129 0 2 259 0 2 143 0 0 287 0 0 9600 51 0 2 103 0 2 64 0 2 129 0 2 71 0 0 143 0 0 14 4k 34 0 8 68 0 6 42 0 9 86
23. sow 14D S 4 fast 0 1 5 5 Sum of character size and parity size D 5 to 10 bit S Samples per bit S 16 for Normal Speed mode and S 8 for Double Speed mode Sp First sample number used for majority voting 8 for normal speed and Se 4 for Double Speed mode Su Middle sample number used for majority voting 5 9 for normal speed and Sy 5 for Double Speed mode slow S the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate Riast 1 the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate Table 17 2 and Table 17 3 list the maximum receiver baud rate error that can be tolerated Note that Normal Speed mode has higher toleration of baud rate variations Table 17 2 Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode U2Xn 0 Data PU Bit Psiow Max Total Error Kea E e 5 93 20 106 67 6 67 6 8 3 0 6 94 12 105 79 5 79 5 88 25 7 94 81 105 11 5 11 5 19 2 0 8 95 36 104 58 4 58 4 54 2 0 9 95 81 104 14 4 14 4 19 1 5 10 96 17 103 78 3 78 3 83 1 5 Table 17 3 Recommended Maximum Receiver Baud Rate Error for Double Speed Mode U2Xn 1 Data spall Bit Psiow eae Max Total Error Becher E T 5 94 12 105 66 5 66 5 88 25 6 94 92 104 92 4 92 5 08 20 7 95 52 104 35 4 35 4 48 15 8 96
24. Note 1 These options should only be used if frequency stability at start up is not important for the application 5 6 Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides a fixed 8 0 MHz clock The frequency is nominal value at 3V and 25 C If 8 MHz frequency exceeds the specification of the device depends on Voc the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 dur ing start up The device is shipped with the CKDIV8 Fuse programmed See System Clock Prescaler on page 44 for more details This clock may be selected as the system clock by pro gramming the CKSEL Fuses as shown in Table 5 7 If selected it will operate with no external components During reset hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator At 5V and 25 C this calibration gives a fre quency within 10 of the nominal frequency Using calibration methods as described in application notes available at www atmel com avr it is possible to achieve 2 accuracy at any given Vcc and temperature When this Oscillator is used as the chip clock the Watchdog Oscil lator will still be used for the Watchdog Timer and for the Reset Time out For more information on the pre programmed calibration value see the section Calibration Byte on page 339 Table 5 7 Internal Calibrated RC Oscillator Operating Modes CKSEL3 0 Nominal Frequency 0010
25. Reply valid RPLV in a identical flow to the one described in Section 19 5 2 3 Rx Data amp Remote Frame on page 244 When remote frame matches automatically the RTRTAG and the reply valid bit RPLV are reset No flag or interrupt is set at this time Since the CAN data buffer has not been used by the incoming remote frame the MOb is then ready to be in transmit mode without any more setting The IDT the IDE the other tags and the DLC of the received remote frame are used for the reply When the transmission of the reply is completed the TXOK flag is set interrupt All the parameters and data are available in the MOb until a new initialization 19 5 2 5 Frame Buffer Heceive Mode This mode is useful to receive multi frames The priority between MObs offers a management for these incoming frames One set MObs including non consecutive MObs is created when the MObs are set in this mode Due to the mode setting only one set is possible A frame buffer completed flag or interrupt BXOK will rise only when all the MObs of the set will have received their dedicated CAN frame 1 2 7679F CAN 11 07 MObs in frame buffer receive mode need to be initialized as MObs in standard receive mode The MObs are ready to receive data or a remote frames when their respective config urations are set CONMOB When frame identifier is received on CAN network the CAN channel scans all the MObs in receive mode tries to fi
26. Status Code TWSR Prescaler Bits are 0 0 8 Status of the Two wire Serial Bus and Two wire Serial Interface Hard ware Own SLA R has been received ACK has been returned Application Software Response To TWCR To from TWDR STA STO Load data byte or 0 Load data byte TWINT 1 1 TWEA Next Action Taken by TWI Hardware Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received 0 0 Arbitration lost in SLA R W as mas ter own SLA R has been received ACK has been returned Load data byte or Load data byte 1 1 Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received 0xB8 Data byte in TWDR has been transmitted ACK has been received Load data byte or Load data byte Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received 0xCO Data byte in TWDR has been transmitted NOT ACK has been received eo No TWDR action or No TWDR actionor 0 0 TWDR action or 1 0 No TWDR action 1 0 Switched to the not addressed slave mode no recognition of own SLA or GCA Switched to the not addressed slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 Switched to the not addressed slave mode no recogniti
27. 1 1 lt lt XMMO sts XMCRB r16 write OxAA to address 0x0001 of external memory 141 16 sts 0x0001 OFFSET r16 re enable PC7 5 for external memory ldi r16 0 lt lt 1 0 lt lt XMMO sts XMCRB r16 Store 0x55 to address OFFSET 1 of external memory 141 16 0 55 sts Ox0001 OFFSET r16 C Code Example define OFFSET 0x2000 void XRAM example void unsigned char p unsigned char OFFSET 1 DDRC OXFF PORTC 0x00 XMCRB 1 XMM1 1 lt lt XMMO p XMCRB 0x00 p 0 55 Note 1 The example code assumes that the part specific header file is included Care must be exercised using this option as most of the memory is masked away AMEL 35 4 6 4 6 1 4 6 2 4 6 3 36 AMEL General Purpose I O Registers The AT90CAN32 64 128 contains three General Purpose I O Registers These registers can be used for storing any information and they are particularly useful for storing global variables and status flags The General Purpose Register 0 within the address range 0x00 Ox1F is directly bit acces sible using the SBI CBI SBIS and SBIC instructions General Purpose I O Register 0 GPIORO Bit 7 6 5 4 3 2 1 0 GPIORO7 GPIORO6 GPIOROS5 GPIORO04 GPIORO3 GPIORO2 GPIORO1 GPIOROO GPIORO Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 General Purpose I O Register 1
28. 7679F CAN 11 07 AMEL 9 4 18 Port F Input Pins Address Bit 7 6 5 4 3 2 1 0 Pm PINES rr Pme Read Write R W R W R W R W R W R W R W R W Initial Value N A N A N A N A N A N A N A N A 9 4 19 Port G Data Register PORTG Bit 7 6 5 4 3 2 1 0 PORTG4 PORTG3 PORTG2 PORTG1 PORTGO PORTG Read Write R R R R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 9 4 20 Port G Data Direction Register DDRG Bit 7 6 5 4 3 2 1 0 _ DDG4 0063 DDG2 DDRG Read Write R R R R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 9 4 21 Port Input Pins Address PING Bit 7 6 5 4 3 2 1 0 T Fins TPG Read Write R R R R W R W R W R W R W Initial Value 0 0 0 N A N A N A N A N A 7679F CAN 11 07 10 External Interrupts The External Interrupts are triggered by the INT7 0 pins Observe that if enabled the interrupts will trigger even if the INT7 0 pins are configured as outputs This feature provides a way of gen erating a software interrupt The External Interrupts can be triggered by a falling or rising edge or a low level This is set up as indicated in the specification for the External Interrupt Control Reg isters EICRA INT3 0 and EICRB INT7 4 When the external interrupt is enabled and is configured as level triggered the interrupt will trigger as long as the pin is held low Note that recognition of fa
29. ATMEL Table 4 5 Port C Pins Released as Normal Port Pins when the External Memory is Enabled XMM2 XMM1 XMMO Bits for External Memory Address Released Port Pins 0 0 0 8 Full External Memory Space None 0 0 1 7 PC7 0 1 0 6 PC7 PC6 0 1 1 5 PC7 PC5 1 0 0 4 PC7 4 1 0 1 3 PC7 1 1 0 2 PC7 PC2 1 1 1 No Address high bits Full Port C Using all Locations of External Memory Smaller than 64 KB Since the external memory is mapped after the internal memory as shown in Figure 4 4 the external memory is not addressed when addressing the first ISRAM size bytes of data space It may appear that the first ISRAM size bytes of the external memory are inaccessible external memory addresses 0x0000 to ISRAM end However when connecting an external memory smaller than 64 KB for example 32 KB these locations are easily accessed simply by address ing from address 0 8000 to ISRAM end 0x8000 Since the External Memory Address bit A15 is not connected to the external memory addresses 0x8000 to ISRAM end 0x8000 will appear as addresses 0x0000 to ISRAM end for the external memory Addressing above address ISRAM end 0x8000 is not recommended since this will address an external mem ory location that is already accessed by another lower address To the Application software the external 32 KB memory will appear as one linear 32 KB address space from XMem st
30. G Input Data ID lt A A A From Last Cell ClockDR UpdateDR AMEL 305 7679F CAN 11 07 AMEL Figure 23 4 General Port Pin Schematic Diagram See Boundary scan Description for Details DATA BUS SYNCHRONIZER PUD PULLUP DISABLE WDx WRITE DDRx Y PUExn PULLUP ENABLE for pin Pxn RDx READ DDRx OCxn OUTPUT CONTROL for pin Pxn WPx WRITE ODxn OUTPUT DATA to pin Pxn RRx READ PORTx REGISTER IDxn INPUT DATA from pin Pxn RPx READ PORTx PIN SLEEP SLEEP CONTROL I O CLOCK 23 6 2 Boundary scan and the Two wire Interface The two Two wire Interface pins SCL and SDA have one additional control signal in the scan chain Two wire Interface Enable TWIEN As shown in Figure 23 5 the TWIEN signal enables a tri state buffer with slew rate control in parallel with the ordinary digital port pins A general scan cell as shown in Figure 23 9 is attached to the TWIEN signal Notes 1 separate scan chain for the 50 ns spike filter on the input is not provided The ordinary scan support for digital port pins suffice for connectivity tests The only reason for having TWIEN in the scan path is to be able to disconnect the slew rate control buffer when doing boundary scan 2 Make sure the OC and TWIEN signals