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ANALOG DEVICES AD5821 Manual

1. TYPICAL PERFORMANCE CHARACTERISTICS INL Vpp 3 8V TEMP 25 C DNL LSB INL LSB OUTPUT CURRENT mA 92 0 91 5 91 0 90 5 90 0 89 5 89 0 88 5 88 0 53 5 6 56 112 168 224 280 336 392 448 504 616 672 728 784 840 896 952 o o irs CODE Figure 5 Typical INL vs Code Plot DNL Vpp 3 8V TEMP 25 C POT TH TOE TE THE REET ATT Mii rm m CODE Figure 6 Typical DNL vs Code Plot 200 0 6 TIME 100 06 150 0 6 250 0 6 Figure 7 to Scale Settling Time Vpp 3 6 V 05034 004 05034 006 300 0 6 333 1 6 05034 005 Rev 0 Page 7 of 16 lout A VERT 50us DIV period afi nt n Pul t e pM PUT M50 0us HORIZ 468 A DIV AD5821 ru et fne mi dtl 05034 007 Figure 8 Settling Time for a 4 LSB Step Voo 3 6 V VERT 2uA DIV HORIZ 2s DIV 05034 008 Figure 9 0 1 Hz to 10 Hz Noise Plot Vpp 3 6 V 05034 009 0 14 lout 25 C 0 12 gt lout iE 7 0 10 0 08 0 06 0 04 0 02 0 Cc q Q OWN co dt OQ Q CN o dt GO Q NO xt OG ON coo or ON OO 0 O t OO OTF HRN DTT DWH ON CODE Figure 10 Sink Current vs Code vs Temperature Vpp 3 6 V AD5821 Figure 11 AC Power Supply Rejection Vpp 3 6 V 100 1k FREQUENCY 10k 05034 010 e o x POSITIVE INL Vpp 3 A PO
2. This is due to a combination of the offset errors in the DAC and output amplifier Zero code error is expressed in milliamperes mA Gain Error Gain error is a measurement of the span error of the DAC It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as a percent of the full scale range Gain Error Dri Gain error drift E ech ED with changes in t mp reMftis eXpressed imsls Digital to Analog Glitch Impulse This is the impulse injected into the analog output when the input code in the DAC register changes state It is normally specified as the area of the glitch in nanoamperes per second nA s and is measured when the digital input code is changed by 1 LSB at the major carry transition Digital Feedthrough Digital feedthrough is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but it is measured when the DAC output is not updated It is specified in nanoamperes per second nA s and measured with a full scale code change on the data bus that is from all 0s to all 1s and vice versa Offset Error Offset error is a measurement of the difference between Isinx actual and Iour ideal in the linear region of the transfer function expressed in milliamperes mA Offset error is measured on the AD5821 with Code 16 loaded into the DAC register Offset Error Drift Offset error drift is a measurement of the change in offset err
3. All devices on an PC bus have their SDA pin connected to the SDA line and their SCL pin connected to the SCL line of the master device C devices can only pull the bus lines low pulling high is achieved by pull up resistors Re The value of Re depends on the data rate bus capacitance and the maximum load current that the PC device can sink 3 mA for a standard device 1 8V SDA I2C MASTER I2C SLAVE I2C SLAVE DEVICE DEVICE DEVICE Figure 21 Typical C Bus 05950 016 AD5821 When the bus is idle SCL and SDA are both high The master device initiates a serial bus operation by generating a start condition which is defined as a high to low transition on the SDA low while SCL is high The slave device connected to the bus responds to the start condition and shifts in the next eight data bits under control of the serial clock These eight data bits consist of a 7 bit address plus a read write R W bit that is 0 if data is to be written to a device and 1 if data is to be read from a device Each slave device on an C bus must have a unique address The address of the AD5821 is 0001100 however 0001101 0001110 and 0001111 address the part because the last two bits are unused dont cares see Figure 22 and Figure 23 Because the address plus the R W bit always equals eight bits of data the write address of the AD5821 is 00011000 0x18 and the read address is 00011001 0x19 see Figure 22 and Figure 23 At the end of the addres
4. 026 50 30 10 10 30 50 70 90 TEMPERATURE C Figure 17 SCL and SDA Logic Low Level Vii vs Supply Voltage and Temperature TEMPERATURE C Figure 18 XSHUTDOWN Logic High Level Vinx vs Supply Voltage and Temperature VOLTAGE V AD5821 Vpp 7 5 5V Vpp 7 4 5V Vpp 3 6V Vpp 2 7V 0 4 50 Figure 19 DNL vs XSHUTDOWN Logic Low Level Vii vs 30 10 10 30 50 70 TEMPERATURE C Supply Voltage and Temperature C com AL Rev 0 Page 9 of 16 90 05950 027 AD5821 TERMINOLOGY Relative Accuracy For the DAC relative accuracy or integral nonlinearity is a measurement of the maximum deviation in LSB from a straight line passing through the endpoints of the DAC transfer function A typical INL vs code plot is shown in Figure 5 Differential Nonlinearity DNL Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB maximum ensures monotonicity This DAC is guaranteed monotonic by design A typical DNL vs code plot is shown in Figure 6 Zero Code Error Zero code error is a measurement of the output error when zero code 0x0000 is loaded to the DAC register Ideally the output is 0 mA The zero code error is always positive in the AD5821 because the output of the DAC cannot go below 0 mA
5. 1 8 V 5 Input filtering on both the SCL and the SDA inputs suppresses noise spikes that are less than 50 ns 7 XSHUTDOWN is active low Rev 0 Page 3 of 16 AD5821 AC SPECIFICATIONS Vpp 2 7 V to 5 5 V AGND DGND 0 V load resistance Ri 25 Q connected to Vpp unless otherwise noted Table 2 B Version 2 Parameter Min Typ Max Unit Test Conditions Comments Output Current Settling Time 250 Hs Voo 3 6 V Ri 25 O L 680 uH scale to 34 scale change 0x100 to 0x300 Slew Rate 0 3 mA us Major Code Change Glitch Impulse 0 15 nA s 1 LSB change around major carry Digital Feedthrough 0 06 nA s Temperature range is as follows B Version 40 C to 85 C Guaranteed by design and characterization not production tested 3 See the Terminology section TIMING SPECIFICATIONS Vop 2 7 V to 3 6 V All specifications Tmn to Tmax unless otherwise noted Table 3 B Version Parameter Limit at Tmn Tmax Unit Description fsa 400 kHz max SCL clock frequency ti 2 5 us min SCL cycle time t 0 6 us min thich SCL high time t3 1 3 us min tiow SCL low time ta 0 D stay start ffepeated start dition h im ts bal data Setup time te 9 D pay data ime 0 us min t 0 6 us min tsu sr setup time for repeated start ts 0 6 us min tsu sro Stop condition setup time to 1 3 us min teur bus free time between a stop condition and a start condition to 300 ns max tr rise time of both SCL and SDA wh
6. ANALOG DEVICES 120 mA Current Sinking 10 Bit I C9 DAC AD5821 FEATURES 120 mA current sink Available in 3 x 3 array WLCSP package 2 wire I C compatible 1 8 V serial interface 10 bit resolution Integrated current sense resistor 2 7 V to 5 5 V power supply Guaranteed monotonic over all codes Power down to 0 5 pA typical Internal reference Ultralow noise preamplifier Power down function Power on reset CONSUMER APPLICATIONS Lens autofocus Image stabilization Optical zoom Shutters lris exposure Neutral density ND fil Lens cover Camera phones Digital still cameras Camera modules Digital video cameras camcorders Camera enabled devices Security cameras BDII C INDUSTRIAL APPLICATIONS Heater controls Fan controls Cooler Peltier controls Solenoid controls Valve controls Linear actuator controls Light controls Current loop controls GENERAL DESCRIPTION The AD5821 is a single 10 bit digital to analog converter with 120 mA output current sink capability It features an internal reference and operates from a single 2 7 V to 5 5 V supply The DAC is controlled via a 2 wire PC compatible serial interface that operates at clock rates up to 400 kHz The AD5821 incorporates a power on reset circuit that ensures that the DAC output powers up to 0 V and remains there until a valid write takes place It has a power down feature that reduces the current consumption offthe de opti o
7. SITIVE INL Vpp 4 5V INL LSB In Li POSITIVE INL Vpp 3 6V EGATIVE y INL Vpp 3 6V Figure 12 INL vs Temperature vs Supply Voltage 40 30 20 10 0 E i Y E i LT E EGATIVE INL Vpp 4 5V 15 25 35 45 55 65 75 85 TEMPERATURE C POSITIVE DNL Vpp 3 6V POSITIVE DNL Vpp 4 5V DNL LSB e NEGATIVE D 40 30 20 10 0 Figure 13 DNL vs Temperature vs Supply Voltage POSITIVE DNL Vpp 3 8V NEGATIVE DNL Vpp 4 5V NEGATIVE DNL Vpp 3 6V TEMPERATURE C 05034 012 15 25 35 45 55 65 75 85 Rev 0 Page 8 of 16 FULL SCALE ERROR mA ZERO CODE ERROR mA VOLTAGE V o a e Aa o 0 40 30 20 10 0 15 25 35 45 55 65 75 85 TEMPERATURE C Figure 14 Zero Code Error vs Supply Voltage vs Temperature 1 5 4 5V o o a e l be a l e 40 30 20 10 0 15 25 35 45 55 65 75 85 TEMPERATURE C Figure 15 Full Scale Error vs Temperature vs Supply Voltage TEMPERATURE C Figure 16 SCL and SDA Logic High Level Vinx vs Supply Voltage and Temperature 05950 013 05950 014 05950 024 VOLTAGE V VOLTAGE V Vpp 4 5V 05950
8. WN 80 nA XSHUTDOWN 0 Output Compliance 0 6 Vop V Output voltage range over which maximum 120 mA sink current is available Output Compliance 0 48 Vop V Output voltage range over which 90 mA sink current is available Power UDITi us S pi go AS n mode Vop 5 V LOGIC INPUTSAX T Input Current 1 uA Input Low Voltage Vin 0 54 V Voo 2 7 V to 5 5 V Input High Voltage Viu 1 3 V Voo 2 7 V to 5 5 V Pin Capacitance 3 pF LOGIC INPUTS SCL SDA Input Low Voltage Vint 0 3 40 54 V Voo 2 7 V to 3 6 V Input High Voltage Viu 1 26 Voo 0 3 V Voo 2 7 V to 3 6 V Input Low Voltage Vint 0 3 0 54 V Voo 3 6 V to 5 5 V Input High Voltage Viu 1 4 Voo 0 3 V Voo 3 6 V to 5 5 V Input Leakage Current lin 1 uA Vin OV to Vop Input Hysteresis Vuvsr 0 05 Voo V Digital Input Capacitance Civ 6 pF Glitch Rejection 50 ns Pulse width of spike suppressed POWER REQUIREMENTS Vpp 2 7 5 5 V Ipp Normal Mode Ipp specification is valid for all DAC codes Voo 2 7 V to 3 6 V 2 5 4 mA Vin 1 8 V Vin GND Voo 3 6 V Ibo Power Down Mode 0 5 yA Vind 1 8 V Vin GND 1 Temperature range is as follows B Version 30 C to 85 C See the Terminology section Linearity is tested using a reduced code range Code 32 to Code 1023 To achieve near zero output current use the power down feature 5 Guaranteed by design and characterization not production tested XSHUTDOWN is active low SDA and SCL pull up resistors are tied to
9. ad operation data is read in the same bit order Rev 0 Page 11 of 16 AD5821 SCL SDA START BY ACK BY ACK BY ACK BY STOP BY MASTER AD5821 AD5821 AD5821 MASTER FRAME 1 SERIALBUS ADDRESS BYTE FRAME 2 FRAME 3 a MOST SIGNIFICANT 44 LEAST SIGNIFICANT gt DATA BYTE DATA BYTE 05950 017 Figure 22 Write Operation SCL SDA START BY ACK BY ACK BY ACK BY STOP BY MASTER AD5821 AD5821 AD5821 MASTER FRAME 1 FRAME 2 FRAME 3 2 SERIAL BUS gt MOST SIGNIFICANT 4 LEAST SIGNIFICANT E ADDRESS BYTE DATA BYTE ATA BYT 8 Figure 23 Read Operation Table 6 Data Format Serial Data Words High Byte Low Byte Serial Data Bits SD7 1 SDO SD7 SD6 SD5 SD4 S S SD1 SDO Input Register 8 Function D R9 R 6 R4 R1 RO D5 D D X X VBATTERY 1 XSHUTDOWN soft pow wn POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in an application it is beneficial to consider power supply and ground return layout on the PCB The PCB for the AD5821 should have separate analog and digital VcoiL power supply sections Where shared AGND and DGND is NS IRA ANE necessary the connection of grounds should be made at only one point as close as possible to the AD5821 Special attention should be paid to the layout of the AGND return SDA path and and it should be trac
10. and camcorders The AD5821 also has many industrial applications such as controlling temperature light and movement over the range of 40 C to 85 C without derating The PC address for the AD5821 is 0x18 DGND 05950 001 Web PC cameras FUNCTIONAL BLOCK DIAGRAM XSHUTDOWN Vpp RESET spa A I2C SERIAL AO BIT sc Oams rw AD5821 O DGND Figure 1 Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2007 Analog Devices Inc All rights reserved AD5821 TABLE OF CONTENTS Features ere S LU LL er Consumer Applications eerte tette Industrial Applications eene General Description scssi Functional Block Diagram eee Revision History siessen Specifications cene entente e mere e eene dei AC Specifications eee aee pe Dp bete tite tet eerte Timing Specifications oc eeeesesseesesseesesesseseeseeseeseeneeneenesses Abs
11. dequate for available commercial linear motors or voice coils Another factor that makes the AD5821 the ideal solution for these applications is the monotonicity of the device ensuring that lens positioning is repeatable for the application of a given digital word SD lb Figure 26 shows a typical application circui Vcc V DD VOICE XSHUTDOWN P 12C SERIAL E COSE B SERE OUTPUT DAC AD5821 I2C MASTER DEVICE S 1H e z t 3 05950 028 Figure 26 Typical Application Circuit Rev 0 Page 14 of 16 OUTLINE DIMENSIONS BALL 1 IDENTIFIER ORDERING GUIDE 0 65 0 59 1 575 0 53 1 515 e 1 455 j 1 750 1 690 1 630 ES TOP VIEW 0 28 BALL SIDE DOWN 0 24 0 20 AD5821 SEATING PLANE a C OO ux O O Ole BALL PITCH BOTTOM VIEW BALL SIDE UP 110405 0 Figure 27 9 Ball Wafer Level Chip Scale Package WLCSP CB 9 1 Dimensions shown in millimeters Branding Model AD5821BCBZ i AD5821BCBZ RE AD5821 WAFER 40 C to 85 C AD5821D WAFER 40 C to 85 C EVAL AD5821EBZ Chip Scale a ig Scale Bare Die Wafer Bare Die Wafer on Film Evaluation Board D82 D82 a fe P P Z Pb free part Rev 0 Page 15 of 16 AD5821 NOTES ww BOM C com AL Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser und
12. e is to use a multilayer board with ground and power planes where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side However this is not always possible with a 2 layer board Rev 0 Page 13 of 16 AD5821 APPLICATIONS INFORMATION The AD5821 is designed to drive both spring preloaded and nonspring linear motors used in applications such as lens auto v focus image stabilization or optical zoom The operation principle is of the spring preloaded motor is that the lens position is controlled z by the balancing of a voice coil and spring Figure 25 shows the E transfer curve of a typical spring preloaded linear motor for E autofocus The key points of this transfer function are displace MT ment or stroke which is the actual distance the lens moves in CUURENT millimeters mm and the current through the motor measured 0 4 in milliamps mA A start current is associated with spring preloaded linear 40 20 30 40 50 60 70 80 90 400 110 120 9 motors which is a threshold current that must be exceeded for SINK CURRENT mA E any displacement in the lens to occur The start current is usually Figure 25 Spring Preloaded Voice Coil Stroke vs Sink Current 20 mA or greater the rated stroke or displacement is usually 0 25 mm to 0 4 mm and the slope of the transfer curve is approximately 10 um mA or less The AD5821 is designed to sink up to 120 mA which is more than a
13. en receiving 0 ns min May be CMOS driven tu 250 ns max tr fall time of SDA when receiving 300 ns max tr fall time of both SCL and SDA when transmitting 20 0 1 Ce ns min Cs 400 pF max Capacitive load for each bus line 1 Guaranteed by design and characterization not production tested A master device must provide a hold time of at least 300 ns for the SDA signal referred to the VinHmin of the SCL signal to bridge the undefined region of the SCL falling edge 3 Cgis the total capacitance of one bus line in pF tr and tr are measured between 0 3 Voo and 0 7 Vop Timing Diagram SDA SCL START REPEATED STOP 3 CONDITION START CONDITION 3 CONDITION i Figure 2 2 Wire Serial Interface Timing Diagram Rev 0 Page 4 of 16 AD5821 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 4 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress Vop to AGND 0 3 V to 5 5 V rating only functional operation of the device at these or any Voo to DGND 0 3 V to Voo 0 3 V other conditions above those indicated in the operational AGND to DGND 0 3 V to 40 3 V section of this specification is not implied Exposure to absolute SCL SDA to DGND 0 3 V to Vpp 0 3 V maximum rating conditions for extended periods may affect XSHUTDOWN to DGND 0 3 V to Voo 0 3 V device reliability Isink to AGND 0 3 V to Voo 0 3 V Op
14. er the Philips PC Patent Rights to use these components in an lC system provided that the system conforms to the I C Standard Specification as defined by Philips 2007 Analog Devices Inc All rights reserved Trademarks and AN ALOG registered trademarks are the property of their respective owners D05950 0 1 07 0 DEVICES www analog com Rev 0 Page 16 of 16
15. erating Temperature Range Industrial B Version 30 C to 85 C ESD CAUTION Storage Temperature Range escape xps pue Junction Temperature T max 150 C A without detection Although this product features WLFCSP Power Dissipation T max Ta Osa patented or proprietary protection circuitry damage Osa Thermal Impedance Mounted on 4 Layer Board Lead Temperature Soldering Maximum Peak Reflow Temperature may occur on devices subjected to high energy ESD Aviad Therefore proper ESD precautions should be taken to 95 C W avoid performance degradation or loss of functionality 260 C 5 C To achieve the optimum 0 it is recommended that the AD5821 be soldered on a 4 layer board As per JEDEC J STD 020C ww BDI C comi AD Rev 0 Page 5 of 16 AD5821 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 05950 021 VIEW FROM BALL SIDE Figure 3 9 Ball WLCSP Pin Configuration Table 5 9 Ball WLCSP Pin Function Description Ball Number Mnemonic Description A1 Isink Output Current Sink A2 NC No Connection A3 XSHUTDOWN Power Down Asynchronous power down signal active low B1 AGND Analog Ground Pin B2 DGND Digital Ground Pin B3 SDA PC Interface Signal C1 DGND Digital Ground Pin C2 Voo Digital Supply Voltage C3 SCL G Inte XSHUTDOWN 1 1690um 05950 030 Figure 4 Metallization Photo Dimensions shown in microns um Rev 0 Page 6 of 16
16. fore lower supplies can be used with the voice coil motor As the current increases to 120 mA through the voice coil Vc increases Vprop decreases and eventually approaches the minimum specified compliance voltage of 600 mV or 480 mV if Isvx 90 mA The ground return path is modeled by the components Rc and Lc The track resistance between the voice coil and the AD5821 is modeled as Rr The inductive effects of Lc influence Rsensz and Rc equally and because the current is maintained as a constant it is not as critical as the purely resistive component of the ground return path When the maximum sink current is flowing through the motor the resistive elements E and voltage com For example if Veartery 3 6 V Re 0 5 Q Rr 0 5 Q Iswx 120 mA Voror 600 mV the compliance voltage Then the largest value of resistance of the voice coil Rc is R Vzar lVprop sm X Rr s X Re _ C I SINK 3 6 V 600 mV 2x 120 mA x0 5 Q 120 mA 240 AD5821 Using another example if Vearttery 3 6 V Rg 0 50 Rr 0 5 0 Isink 90 mA Voror 480 mV the compliance voltage specification at 90 mA Then the largest value of resistance of the voice coil Re is Vear lVprop Ismer X Rr Gsm X Re Ro 7 SINK 3 6 V 480 mV 2 x 90 mA x 0 5 Q 90 mA 33 660 For this reason it is important to minimize any series impedance on both the ground return path and interconnec
17. ked between the voice coil motor and Is to minimize any series resistance Figure 24 shows the output current sink of the AD5821 and illustrates the importance XSHUTDOWN of reducing the effective series impedance of AGND and the track resistance between the motor and Isi The voice coil is modeled as Inductor Lc and Resistor Rc The current through the voice coil DGND I I I i GROUND is effectively a dc current that results in a voltage drop Vc when L 3 1 RETURN 3 the AD5821 is sinking current The effect of any series inductance f 8 is minimal Figure 24 Effect of PCB Trace Resistance and Inductance Rev 0 Page 12 of 16 When sinking the maximum current of 120 mA the maximum voltage drop allowed across Rsensz is 400 mV and the minimum drain to source voltage of Q1 is 200 mV This means that the AD5821 output has a compliance voltage of 600 mV If Vprop falls below 600 mV the output transistor Q1 can no longer operate properly and Ismnk may not be maintained as a constant When sinking 90 mA the maximum voltage drop allowed across Rsense is 300 mV and the minimum drain to source voltage of Q1 is 180 mV This means that the AD5821 output has a compliance voltage of 480 mV If V pror falls below 480 mV the output transistor Q1 can no longer operate properly and Iswx may not be maintained as a constant As Isivx decreases the voltage required across the transistor Q1 also decreases and there
18. olute Maximum Ratings eerte Pin Configuration and Function Descriptions REVISION HISTORY 1 07 Revision 0 Initial Version Typical Performance Characteristics sseeeeeee 7 Terminology oce heRP RUE URDU Re eh 10 Theory of Operation eate bee pr eee eH ed 11 Serial Interface et t RID Re 11 PG B s Operation 1 epe teeta 11 Data Format ote acta eee Sel ass 11 Power Supply Bypassing and Grounding 12 Applications Information eerte 14 Outline DIMENSIONS sirsiran 15 Ordering Guide RE 15 ww BDI C com AD Rev 0 Page 2 of 16 SPECIFICATIONS AD5821 Vpp 2 7 V to 5 5 V AGND DGND 0 V load resistance Ri 25 Q connected to Vpn all specifications Tmn to Tmax unless otherwise noted Table 1 B Version Parameter Min Typ Max Unit Test Conditions Comments DC PERFORMANCE Voo 3 6 V to 4 5 V device operates over 2 7 V to 5 5 V with reduced performance Resolution 10 Bits 117 pA LSB Relative Accuracy X15 4 LSB Differential Nonlinearity 3 1 LSB Guaranteed monotonic over all codes Zero Code Error 0 1 5 mA All Os loaded to DAC Offset Error Code 16 0 5 mA Gain Error 0 6 ofFSR 25 C Offset Error Drift 10 pA C Gain Error Drift 0 2 40 5 LSB C OUTPUT CHARACTERISTICS Minimum Sink Current 3 mA Maximum Sink Current 120 mA Output Current During XSHUTDO
19. or with a change in temperature It is expressed in microvolts per C C m ALI Rev 0 Page 10 of 16 THEORY OF OPERATION The AD5821 is a fully integrated 10 bit digital to analog converter DAC with 120 mA output current sink capability It is intended for driving voice coil actuators in applications such as lens autofocus image stabilization and optical zoom The circuit diagram is shown in Figure 20 A 10 bit current output DAC coupled with Resistor R generates the voltage that drives the noninverting input of the operational amplifier This voltage also appears across the Rsenss resistor and generates the sink current required to drive the voice coil Resistor R and Resistor Rsensz are interleaved and matched Therefore the temperature coefficient and any nonlinearities over temperature are matched and the output drift over tempera ture is minimized Diode D1 is an output protection diode XSHUTDOWN Vpp DGND POWER ON RESET 10 BIT CURRENT OUTPUT DAC 05950 001 SERIAL INTERFACE The AD5821 is controlled using the industry standard C 2 wire serial protocol Data can be written to or read from the DAC at data rates of up to 400 kHz After a read operation the contents of the input register are reset to all Os PC BUS OPERATION An IC bus operates with one or more master devices that generate the serial clock SCL and read and write data on the serial data line SDA to and from slave devices such as the AD5821
20. s data after the R W bit the slave device that recognizes its own address responds by generating an acknowledge ACK condition This is defined as the slave device pulling SDA low while SCL is low before the ninth clock pulse and keeping it low during the ninth clock pulse Upon receiving ACK the master device can clock data into the AD5821 in a write operation or it can clock it out in a read operation jed of the clock diod define a start Wie a stop condition TC data is divided into blocks of eight bits and the slave generates an ACK at the end of each block Because the AD5821 requires 10 bits of data two data words must be written to it when a write operation occurs or read from it when a read operation occurs At the end of a read or write operation the AD5821 acknowledges the second data byte The master generates a stop condition defined as a low to high transition on SDA while SCL is high to end the transaction DATA FORMAT Data is written to the AD5821 high byte first MSB first and is shifted into the 16 bit input register After all data is shifted in data from the input register is transferred to the DAC register Because the DAC requires only 10 bits of data not all bits of the input register data are used The MSB is reserved for an active high software controlled power down function Bit 14 is unused Bit 13 to Bit 4 correspond to the DAC data bits Bit 9 to Bit 0 Bit 3 to Bit 0 are unused During a re
21. t between the AD5821 and the motor It is also important to note that for lower values of Isxx the compliance voltage of the output stage also decreases This decrease allows the user to either use voice coil motors with high resistance values or decrease the power supply voltage on the voice coil motor The compliance voltage decreases as the Iswx current decreases The power supply of the AD5821 or the regulator used to supply the AD5821 should be eet Best practice power supply decoupling recommends h e ly be decoupled Macitor should be of E wpupply or regulator and clean sueird C oupling may not be required The ADS821 should be decoupled locally with a 0 1 uF ceramic capacitor and this 0 1 uF capacitor should be located as close as possible to the Vp pin The 0 1 uF capacitor should be ceramic with a low effective series resistance and effective series inductance The 0 1 uF capacitor provides a low impedance path to ground for high transient currents The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground Avoid crossover of digital and analog signals if possible When traces cross on opposite sides of the board they should run at right angles to each other to reduce feedthrough effects through the board The best techniqu

ANALOG DEVICES AD5821 Manual

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