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ANALOG DEVICES ADSP-21065L technology Manual

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1. Bits Bits 7654 3210 0000 0001 0010 0011 0100 0101 0110 0111 0000 RO 0 0 LO BO FADDR USTATI 0001 R1 1 1 L1 Bl DADDR USTAT2 0010 R2 2 2 L2 B2 0011 R3 3 3 L3 B3 PC 0100 R4 4 4 L4 B4 PCSTK 0101 R5 5 5 L5 B5 PCSTKP 0110 R6 6 6 L6 B6 LADDR 0111 R7 7 7 L7 B7 CURL CNTR 000 R8 8 8 L8 B8 LCNTR 001 R9 9 9 L9 B9 IRPTL 010 R10 0 0 L10 B10 MODE2 011 R11 1 1 L11 B11 MODE1 100 R12 2 2 L12 B12 ASTAT 101 R13 3 3 L13 B13 IMASK 110 R14 4 4 L14 B14 STKY 111 R15 5 5 LTS B15 IMASKP A 26 ADSP 21065L SHARC DSP Technical Reference Instruction Set Reference Table A 10 Map 2 universal register codes Bits Bits 7654 3210 1000 1001 1010 1011 1100 1101 1110 1111 0000 1011 PX 1100 PX1 1101 PX2 TILIL ADSP 21065L SHARC DSP Technical Reference A 27 Group Instructions Compute amp Move Group I Instructions Compute amp Move Compute dreg gt DM dreg gt PM Type 1 on page A 30 Parallel data memory and program memory transfers with Register File optional compute operation e Compute Type 2 on page A 32 Compute operation optional condition e Compute ureg DMI PM register modify Type 3 on page A 33 Transfer between data or program memory and universal register optional condition optional compute operation e Compute dreg DM PM immediate modify Type 4
2. Position Latch Type Signal 71 0 SPAREO 72 SPAREO 73 TRQO 74 TROL 75 TRQ2 76 OE SPARE6 output enable 77 0 SPARE6 78 I SPARE6 79 0 RFSO 80 I RFSO 81 OE RFSO output enable 82 OE RCLKO output enable 83 OE TFSO output enable I Input O Output OE OutputEnable 1 Drive the associated signals during EXTEST and INTEST instructions 0 Disable the associated signals during EXTEST and INTEST instructions NC Do not connect D 12 ADSP 21065L SHARC DSP Technical Reference JTAG Test Access Port Table D 2 Scan path position definitions Contd Position Latch Type Signal 84 0 RCLKO 85 I RCLKO 86 I DRO_A 87 I DRO_B 88 0 TFSO 89 I TFSO 90 0 TCLKO a I TCLKO 92 OE TCLKO output enable 93 OE DTO_A output enable 94 OE DTO_B output enable 95 0 DTO_A 96 0 DTO_B I Input O Output OE OutputEnable 1 Drive the associated signals during EXTEST and INTEST instructions 0 Disable the associated signals during EXTEST and INTEST instructions NC Do not connect ADSP 21065L SHARC DSP Technical Reference D 13 Boundary R egister Table D 2 Scan path position definitions Contd Position Latch Type Signal 97 0 RFS1 98 I RFS1 99 OE RFS1 output enable 00 OE RCLK1 out
3. Bit Field Description States COMPUTE Compute operation field see Appendix B Com pute Operation Refer ence COND Status Condition codes 0 31 CI Clear interrupt code 0 Do not clear current interrupt 1 Clear current inter rupt CU Computation unit select 90 ALU codes 01 Multiplier 10 Shifter DATA Immediate data field DEC Counter decrement code 0 No counter decrement 1 Counter decrement DMD Memory access direction 0 Read 1 Write DMI Index I register num 0 7 bers DAGI DMM Modify M register 0 7 numbers DAG1 DREG Register file locations 0715 E ELSE clause code 0 No ELSE clause 1 ELSE clause A 20 ADSP 21065L SHARC DSP Technical Reference Table A 5 Opcode acronyms Contd Instruction Set Reference Bit Field Description States FC Flush cache code o cache flush 1 Cache flush G DAG Memory select 0 DAGI or Data Memory 1 DAG2 or Program Mem ory INC Counter increment code 0 o counter increment Counter increment J Jump Type 0 ondelayednondelayed Delayed LPO Loop stack pop code 0 No stack pop Stack pop LPU Loop stack push code 0 No stack push Stack push LR Loop reentry code 0 o loop reentry Loop reentry UM Interrupt vector 0 7 OPCODE Computation unit opcodes see Appendix B Compute Operation Reference PMD Memory access direction 0 Read 1 Write PMI Index I register num
4. Syntax Opcode Rn Rx Ry 0000 0001 Rn Rx Ry 0000 0010 Rn Rx Ry CI 0000 0101 Rn Rx Ry CI 1 0000 0110 Rn Rx Ry 2 0000 1001 COMP Rx Ry 0000 1010 Rn Rx CI 0010 0101 Rn Rx CI 1 0010 0110 Rn Rx 1 0010 1001 Rn Rx 1 0010 1010 Rn Rx 0010 0010 Rn ABS Rx 0011 0000 Rn PASS Rx 0010 0001 ADSP 21065L SHARC DSP Technical Reference B 3 Single Function Operations Table B 1 Fixed point ALU operations Contd Syntax Opcode Rn Rx AND Ry 0100 0000 Rn Rx OR Ry 0100 0001 Rn Rx XOR Ry 0100 0010 Rn NOT Rx 0100 0011 Rn MIN Rx Ry 0110 0001 Rn MAX Rx Ry 0110 0010 Rn CLIP Rx BY Ry 0110 0011 Table B 2 Floating point ALU operations Syntax Opcode Fn Fx Fy 000 0001 Fn Fx Fy 000 0010 Fn ABS Fx Fy 001 0001 Fn ABS Fx Fy 001 0010 Fn Fx Fy 2 000 1001 Fn COMP Fx Fy 000 1010 Fn Fx 010 0010 Fn ABS Fx 011 0000 Fn PASS Fx 010 0001 B 4 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference Table B 2 Floating point ALU operations Cont d Syntax Opcode Fn RND Fx 010 010 Fn SCALB Fx BY Ry 011 110 Rn MANT Fx 010 110 Rn LOGB Fx 00
5. NC Do not connect ADSP 21065L SHARC DSP Technical Reference D 27 Device Identification Register Table D 2 Scan path position definitions Contd Position Latch Type Signal 279 OE SPARE2 output enable 280 0 SPARE2 281 I SPARE2 282 I ID1 283 I IDO 284 0 EMU This end closest to TDI scan in last I Inp O Output OE OutputEnable 1 Drive the associated signals during EXTEST and INTEST instructions 0 Disable the associated signals during EXTEST and INTEST instructions NC Do not connect Device Identification Register The ADSP 21065L does not include a device identification register Built In Self Test Instructions BIST The ADSP 12065L does not support self test functions D 28 ADSP 21065L SHARC DSP Technical Reference JTAG Test Access Port Private Instructions Loading a value of 001xx into the instruction register enables the private instructions reserved for emulation The ADSP 21065L EZ ICE emula tor uses the TAP and boundary scan to access the processor in the target system The EZ ICE emulator requires a target board connector for access to the TAP For details see EZ ICE Emulator on page 12 36 in ADSP 21065L SHARC DSP User s Manual References Bleeker Harry P van den Eijnden amp F de Jong Boundary Scan Test A Practical Approach Kluwer Academic Press 1993 Hewlett Packard Co HP Bo
6. 25 COMPUTE Bits Description COND Specifies the test condition If no condition is specified COND is true and the instruction is executed E Specifies whether or not an ELSE clause is used B Selects the branch type jump or call For calls A and CI are ignored J Determines whether the branch is layed delayed or nonde A 50 ADSP 21065L SHARC DSP Technical Reference Instruction Set Reference Bits Description A Activates loop abort CI Activates clear interrupt COMPUTE Defines a compute operation to be performed in parallel with the data access this is a NOP if no compute operation is specified in the instruction RELADDR Holds a 6 bit twos complement value that is added to the current PC value to generate the branch address PMI Specifies the I register for indirect branches The I register is premodified but not updated by the M register PMM Specifies the M register for premodifies ADSP 21065L SHARC DSP Technical Reference A 51 Group II Instructions Program Flow Control Indirect Jump or Compute dreg DM Type 10 Indirect or PC relative jump or optional compute operation with trans fer between data memory and Register File w Type 10 instructions require IF COND Syntax IF COND Jump compute DM Ia Mb dreg PC lt reladdr6 gt compute dreg DM Ia Mb Md Ic Else Function Conditional jump to the specified PC relative
7. issues Chapter 9 Serial Ports DMA Chapter 6 DMA Chapter 7 Multiprocessing Chapter 8 Host terface External port Chapter 6 DMA Chapter 7 Multiprocessing Chapter 8 Host terface High frequency design Chapter 12 System Design Host interface ter 8 Host Interface Instruction cache Memo ter 3 Program Sequencing Chapter 5 y xvi ADSP 21065L SHARC DSP Technical Reference Preface For information on See Instruction set Appendix A Instructio Appendix B Compute Operation Reference Set Reference Appendix C Numeric Formats Internal buses Chapter 5 Memory Chapter 6 DMA Chapter 8 Host Interface Interrupts JTAG test port Chapter 3 Program Sequencing Chapter 5 Memory Appendix F Interrupt Vector Addresses Chapter 12 System Design Appendix D JTAG Test Access Port emory Chapter 5 Memory ultiplier operation Chapter2 Computation Units Compute Operation Reference Appendix B ultiprocessing Chapter 7 Multiprocessing Pin definitions Chapter 12 System Design Processor Chapter 1 Introduction architecture Processor Appendix E Control and Status Registers configuration Program flow Chapter 3 Program Sequencing Programmable I 0 Chapter 11 Programmable Timers and I 0 ports Ports Programmable timers Chapter 11 Programm
8. Bit Name Description 0 FLG4 Status of the FLAG4 I O port 1 FLG5 Status of the FLAGS I O port 2 FLG6 Status of the FLAG6 I O port 3 FLG7 Status of the FLAG7 I O port 4 FLG8 Status of the FLAG8 I O port E 76 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers Table E 20 Flag Pin Values on the IOSTAT register Cont d Bit Name Description 5 FLG9 Status of the FLAG9 I 0 port 6 FLG1O Status of the FLAG10 I O port 7 FLG11 Status of the FLAG11 I 0 port 8 31 Reserved ADSP 21065L SHARC DSP Technical Reference E 77 IOP Registers RDIVx TDIVx SPORT Divisor Registers The TDIVO TDIV1 RDIVO and RDIV1 registers contain divisor values that determine the frequencies for internally generated serial port clocks and frame syncs Figure E 10 on page E 79 shows the RDIVx register bits and Figure E 11 on page E 79 shows the TDIVx register bits For details on using the RDIVx and TDIVx registers in ADSP 21065L SHARC DSP Users Manual see e Chapter 3 Program Sequencing e Chapter 9 Serial Ports In this manual see Appendix A Instruction Set Reference These four registers are memory mapped in internal memory at addresses Ox00E4 Ox00F4 0x00E6 and 0x00F6 respectively These registers are not initialized after reset E 78 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers 31 30 29 28 27 26
9. COMPUTE Type 10 Opcode with PC relative jump 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 111 D DMI DM COND RELADDR DREG z TPP ETE EE EEL COMPUTE ADSP 21065L SHARC DSP Technical Reference A 53 Group II Instructions Program Flow Control Bits Description COND Specifies the condition to test PMI Specifies the I register for indirect branches The register is premodified but not updated by the M register PMM Specifies the M register for premodifies D Selects the data memory access type read or write DREG Specifies the Register File location DMI Specifies the I register which is postmodified and updated by the M register DMM Identifies the M register for postmodifies COMPUTE Defines a compute operation to be performed in parallel with the data access this is a NOP if no compute operation is specified in the instruction RELADDR Holds a 6 bit twos complement value that is added to the current PC value to generate the branch address A 54 ADSP 21065L SHARC DSP Technical Reference Instruction Set Reference Return From Subroutine Interrupt Compute Type 11 Indirect or PC relative jump or optional compute operation with trans fer between data memory and Register File Syntax IF COND RTS DB compute LR ELSE compute DB LR IF COND RTI DB
10. F11 R12 F12 R13 F13 R14 F14 R15 F15 Figure B 4 Valid input registers for multifunction computations ADSP 21065L SHARC DSP Technical Reference B 95 Multifunction Computations Dual Add Subtract Fixed Pt The dual add subtract operation computes the sum and the difference of two inputs and returns the two results to different registers This opera tion has fixed point and floating point versions Syntax fixed point version Ra Rx Ry RS Rx Ry Compute Field PEEP EPP PP EEE EEE 0 00 0111 RS RA RX RY Function Does a dual add subtract of the fixed point fields in registers Rx and Ry The sum is placed in the fixed point field of register Ra and the difference in the fixed point field of Rs The floating point extension fields of Ra and Rs are set to all Os In saturation mode the ALU saturation mode bit in MODE set positive overflows return the maximum positive number Ox7FFF FFFF and negative overflows return the minimum negative num ber 0x8000 0000 Status Flags Flag Description AZ Set if either of the fixed point outputs is all Os otherwise cleared AU Cleared B 96 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference Flag Description AN Set if the most significant output bit is 1 of either of the outputs otherwise cleared AV Set if the XOR of the carries of the two most signif icant adder stages of either of the o
11. PMODE Packing mode Specifies the internal word width for the packing mode 00 no packing unpacking Ol 16 bit amp 32 bit 0 16 bit 48 bit l 32 bit 48 bit Used with the HBW bits SYSCON which spec ify the external word width MSWF ost significant word first Specifies the word order for packing 16 bit data to 32 or 48 bit data O LSW 16 bit word first 1 16 bit word first E 58 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers Table E 16 DMACx register Contd Bit Name Description MASTER DMA master mode enable In combination with HSHAKE and EXTERN to set the DMA transfer mode 0 disable 1 enable See Table E 17 on page E 61 10 HSHAKE DMA handshake enable In combination with HSHAKE and EXTERN to set the DMA transfer mode 0 disable 1 enable See Table E 17 on page E 61 11 INTIO Single word I O interrupt enable Enables disables interrupts for individual words the external port buffers transmit or receive 0 disable ith TRAN 0 a full or partially full EPBx RX buffer generates an interrupt ith TRAN 1 an empty or partially full EPBx TX buffer generates an interrupt Single word I O interrupts are useful for implementing interrupt driven single word transfers under the control of the proces sor s core ADSP 21065L SHARC DSP Te
12. e E mail questions to dsp support analog com or dsp europe analog com European customer support What s This Book About and Who s It For The ADSP 21065L documentation set contains two manuals the ADSP 21065L SHARC DSP Users Manual and the ADSP 21065L SHARC DSP Technical Reference These manuals are reference guides for hardware and software engineers who want to develop applications using the ADSP 21065L These manuals assume that the user has a working knowledge of the ADSP 21065L s Super Harvard Architecture The ADSP 21065L SHARC DSP User s Manual describes the architecture and operation of the ADSP 21065L s individual components intercom ponent connections and access off chip connections and access and the processor s hardware software interface xiv ADSP 21065L SHARC DSP Technical Reference Preface The information in this book includes e Pin definitions and instructions for connecting the pins to external devices and peripherals in single and multiprocessor systems e Processor features and instructions for configuring the processor for specific operation options e Internal and external data paths and instructions for moving data between internal components and between the processor and exter nal devices and peripherals e Timing sequencing and throughput of control signals and data accesses The ADSP 21065L SHARC DSP Technical Reference provides detailed technical information on programming th
13. Return from subroutine or interrupt optional condition optional compute operation e Do Until Counter Expired Type 12 on page A 58 Load loop counter do loop until loop counter expired e Do Until Type 13 on page A 60 Do until termination d For all program flow control instructions except type 10 instructions IF COND is optional A 44 ADSP 21065L SHARC DSP Technical Reference Instruction Set Reference Direct Jump Call Type 8 Direct or PC relative jump call optional condition Syntax IF COND lt addr24 gt DB JUMP PC lt reladdr24 gt LA CI DB LA DB CI IF COND lt addr24 gt DB CALL PC lt reladdr24 gt Function A jump or call to the specified address or PC relative address The PC rel ative address is a 24 bit twos complement value If the delayed branch DB modifier is specified the branch is delayed otherwise it is nonde layed If the loop abort LA modifier is specified for a jump the loop stacks and PC stack are popped when the jump is executed Use the LA modifier if the jump transfers program execution outside of a loop If there is no loop or the jump address is within the loop do not use the LA modifier The clear interrupt CI modifier enables reuse of an interrupt while it is being serviced Normally the processor ignores and does not latch an interrupt that reoccurs while its service routine is already executing Locate the J
14. Table E 2 lists the effect latency and read latency for the ADSP 21065L system registers Table E 2 Read and effect latencies of the system registers Register Read latency Effect Latency ASTAT 0 1 TRPTL 0 1 IMASK 0 IMASKP 1 MODE1 0 MODE2 0 STKY 0 USTATI 0 0 USTAT2 0 0 0 Write takes effect on the cycle immediately after the write instruction executes 1 One cycle of latency System Register Bit Manipulation Instruction Application software can use the system register bit manipulation instruc tion to set clear toggle or test specific bits in the system registers An immediate field in the bit manipulation instruction specifies the affected bits For a detailed description of this instruction see Group IV Miscellaneous in Appendix A Instruction Set Reference ADSP 21065L SHARC DSP Technical Reference E 5 System Registers For example BIT SET MODE2 0x00000070 BIT TST ASTAT 0x00002000 result in BTF flag Although both the Shifter and ALU have bit manipulation capabilities these computations operate on Register File locations only System register bit manipulation instructions eliminate the overhead asso ciated with transferring system registers to and from the Register File Table E 3 lists these operations Table E 3 System register bit manipulation operations Bit Instruction Syst
15. compute ELSE compute Function A return from a subroutine RTS or return from an interrupt service rou tine RTI If the delayed branch DB modifier is specified the return is delayed otherwise it is nondelayed A return causes the processor to branch to the address stored at the top of the PC stack The difference between RTS and RTI is that the RTI instruction not only pops the return address off the PC stack but also 1 pops status stack if the ASTAT and MODE status registers have been pushed if the interrupt was IRQ 9 the timer interrupt or the VIRPT vector interrupt and 2 clears the appropriate bit in the interrupt latch register IRPTL and the interrupt mask pointer IMASKP The return is executed if a condition is specified and is true If a compute operation is specified without the ELSE it is performed in parallel with the return If a compute operation is specified with the ELSE it is per formed only if the condition is false Note that a condition must be specified if an ELSE compute clause is specified If a nondelayed call is used as one of the last three instructions of a loop the loop reentry LR modifier must be used with the RTS instruction ADSP 21065L SHARC DSP Technical Reference A 55 Group II Instructions Program Flow Control that returns from the subroutine The LR modifier assures proper reentry into the loop In counter based loops for example the termination condition is c
16. no boot mode setting IVT to 1 selects an internal vector table and setting IIVT to 0 selects an external vector table IIVT has no effect when an external source boots the proces sor while it is in other than no boot mode ADSP 21065L SHARC DSP Technical Reference F 3 Figure F 1 on page F 5 shows the bit values in the IRPTL and IMASK registers The default values are valid for the IMASK register only the processor clears IRPTL after reset For IMASK 1 unmasked enabled and 0 masked enabled F 4 ADSP 21065L SHARC DSP Technical Reference Interrupt Vector Addresses 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 User sw Ext Port Buf 0 DMA interrupt 3 EPB1I SFT2l Ext Port Buf 1 DMA User sw 3 CB7I 2 interrupt DAGI SFT1I Circular Buf 7 User sw Overflow interrupt 1 CBi5I SFTOI DAG2 User sw Circular Buf 15 interrupt 0 Overflow FLTII TMZLI Fit pt Timer Expired invalid except low priority FLTUI FIXI Fit pt FLTOI Fxd pt overflow underflow except Fit pt overflow except 15 14 1312 1110 9 8 7 6 54 3 2 1 0 SPT1I RSTI SPORT1 xmit A B Reset nonmaskable DMA chn 6 7 read only SOVFI SPTOI SPORTO xmit A B Stack Full Overflow DMA chn 4 5 TMZHI Timer Expired SPR1I Ga SPORTI rev A B high priority DMA chn 2 3 VIRPTI Multiprocessor SPROI Vector interrupt SPORTO Rev A B IRQ2I DMA chn 0 1 IRQ2 Asserted IRQOI IRQ1I IRQO Asserted IRQ1 Asserted Figure F 1 IRPTL IMASK reg
17. on page A 35 PC relative transfer between data or program memory and Register File optional condition optional compute operation e Compute ureg ureg Type 5 on page A 37 Transfer between two universal registers optional condition optional compute operation e Immediate Shift dregDM PM Type 6 on page A 39 Immediate shift operation optional condition optional transfer between data or program memory and Register File A 28 ADSP 21065L SHARC DSP Technical Reference Instruction Set Reference e Compute modify Type 7 on page A 42 Index register modify optional condition optional compute opera tion d For all compute and move modify instructions IF COND is optional ADSP 21065L SHARC DSP Technical Reference A 29 Group Instructions Compute amp Move Compute dreg DM dreg PM Type 1 Parallel data memory and program memory transfers with Register File option compute operation Syntax compute DM Ia Mb dregl dregl DM Ia Mb PM Ic Md dreg2 dreg2 PM Ic Md Function Parallel accesses to data memory and program memory from the Register File The specified I registers address data memory and program memory The I values are postmodified and updated by the specified M registers Premodify offset addressing is not supported For more information on register restrictions see Chapter 4 Data Addressing in ADSP 21065L SHARC DSP User s Manual
18. pins see Boot mode pins selecting 12 50 when IIVT 1 5 30 Boot select override see BSO boot select override Boot sequence and kernel loading 12 51 Booting 12 49 described 12 49 host boot sequence 12 58 loading an entire program 12 49 loading routine 12 49 modes see Boot modes multiprocessor systems 12 58 selecting 12 50 Branch instructions call 3 16 delayed see Delayed branches described 3 16 jump 3 16 nondelayed see Nondelayed branches parameters 3 16 program memory data accesses 3 11 RTI 3 16 RTS 3 16 Broadcast writes CS 8 23 defined 8 23 implementing 8 23 REDY 8 23 BRx BTC and 7 12 8 8 connection in a multiprocessor system 7 3 multiprocessor bus arbitration 7 10 pin definition 12 14 state after reset 12 22 system bus acquisition 7 12 BSEL 5 53 boot mode 12 50 EPROM boot mode 5 53 host booting 12 56 multiprocessor host booting 12 59 pin connection 5 53 pin definition 12 14 state after reset 12 23 BSO boot select override accessing EPROM after bootstrap 12 55 overriding BMS 12 55 writing to BMS memory space 12 56 Bstop command 10 30 defined 10 5 BSYN bus synchronization bit 7 22 7 42 8 40 BTC BRx and 7 12 8 8 bus mastership timeout and 7 18 defined 8 5 external accesses and 7 14 external bus in 7 13 multiprocessing events that trigger a 7 12 1 8 ADSP 21065L SHARC DSP User s Manual multiprocessing transfer sequence 7 13 multiprocessor bus arbitration 7 12 without CPA 7 19 BT
19. EB2WS External bank 2 number of wait states For parameter values see EBOWS parameter on page E 113 15 16 EB3WM External bank 3 wait state mode For parameter values see EBOWM parameter on page E 113 17 19 EB3WS External bank 3 number of wait states For parameter values see EBOWS parameter on page E 113 20 21 RBWM ROM boot wait mode Controls the wait mode for accesses that use the BMS pin See the BSO bit in Table E 25 on page E 101 For parameter values see EBOWM parameter on page E 113 22 24 RBWS ROM boot wait state Controls the wait state for accesses that use the BMS pin See the BSO bit in Table E 25 on page E 101 For parameter values see EBOWS parameter on page E 113 E 114 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers Table E 27 WAIT register Cont d Bit Name Description 25 28 Reserved 29 MMSWS Multiprocessor memory space wait state Single wait state for multiprocessor memory Space accesses 30 HIDMA Handshake idle cycle for DMA Single idle cycle for DMA handshake Sul Reserved Bus idle cycle an inactive bus cycle the processor automatically generates to avoid bus driving conflicts For d devices with slow disable time enable bus idle cycle generation with EBxWS pa rameter Does not apply to SDRAM accesses Hold time cycle an inactive bus cycle the processor automatically generates at the end of a read or wri
20. TPWIDTH 9 Timer counter output pulse width registers for timers 0 and 1 VIRPT Vector interrupt register WAIT External memory wait state register ADSP 21065L SHARC DSP Technical Reference E 39 IOP Registers Table E 14 lists the initialization values of the major IOP registers after reset All control and status bits are active high unless otherwise noted Bit values shown are the default values after reset If no value is shown the bit is undefined at reset or its value depends on processor inputs Make sure your application software always writes zeros 0 to reserved bits Table E 14 Initialization values of the IOP registers after reset Register Initialization after reset DMACx 0x0000 0000 DMASTAT Oxnnnn nnnn not initialized IOCTL 0x0000 0000 IOSTAT 0x0000 0000 RDIVx TDIVx Oxnnnn nnnn not initialized SRCTLX 0x0000 0000 STCTLx 0x0000 0000 SYSCON 0x0000 0020 SYSTAT 0x0000 nnno WAIT Ox200D 6B5A l Bits 11 4 depend on the value of the ID _ inputs IOP Register Access Restrictions Because the IOP registers are memory mapped you cannot write to them directly with data from memory Instead you must write data from or read data to the processor s core registers usually one of the Register File s E 40 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers general purpose registers R15 RO External devices
21. host DMA transfers 8 18 T O bus operations 6 27 incrementing and decrementing the modify register 6 28 internal to external memory transfers 6 75 internal to external transfer sequence slave mode 6 61 operating modes 6 11 operation 6 7 6 27 prioritizing external direct accesses to internal memory 6 37 prioritizing requests 6 35 prioritizing TCB chain loading 6 37 priority of I O bus accesses 6 74 redefining priority for external port channels 6 38 request and grant 6 35 request timing 6 65 rotating priority for external port channels 6 37 SPORT DMA chaining 9 85 SPORT DMA channels 6 27 9 77 9 78 system bus access deadlock resolution 8 50 system bus accesses 8 50 three cycle pipeline 6 64 DMA data packing 48 bit internal words 6 53 DATAx lines used for 32 bit DMA data 6 53 EPBx buffers DMA 6 51 LSWF packing format 6 52 MSWF packing format 6 52 PMODE and HBW combina tions summary of 6 52 flushing partially packed data 6 18 HMSWF host packing order bit 6 54 host boot mode 12 57 host data transfers 8 22 in external handshake mode DMA 6 70 multiprocessing DMA transfers 7 31 order of DMA transfers 6 17 packing sequence for download of 1 24 ADSP 21065L SHARC DSP User s Manual processor instructions from a 16 bit bus 6 53 packing sequence for download of processor instructions from a 32 bit bus 6 52 packing sequence for host to processor 8 to 48 bit words 6 54 P
22. program sequencer see Program sequencer program structures 3 1 programmable timers and 3 53 saving and restoring the status stack 3 48 software interrupts 3 49 subroutines 3 1 variation in program flow diagram of 3 3 vector interrupt feature using 3 52 Program structures 3 1 branches 3 11 IDLE 3 1 interrupts 3 1 jumps 3 1 loops 3 1 3 11 subroutines 3 1 Programmable I O and SDRAM control register see JOCTL register Programmable I O ports bitwise operations on 11 13 described 11 13 1 90 ADSP 21065L SHARC DSP User s Manual FLAGI1 4 11 13 functionality 11 13 IOSTAT register and 11 13 MODE register and 11 13 Programmable I O status register see OSTAT register Programmable timer pins see PWM_EVENTx Programmable timers 3 53 control bits and interrupt vectors 11 8 see Timer control bits and inter rupt vectors counters maximum period of 3 53 enabling 11 1 features 3 53 functions 11 1 I O pins 3 53 input output pin 11 1 interrupts and the status stack 11 9 see Timer interrupts and the sta tus stack pulse width count capture 11 1 see WIDTH _CNT timer mode pulse width waveform generation 11 1 see PWMOUT timer mode PWM_EVENT x pins 3 53 registers 11 1 TCOUNTx register 3 53 timer counter mode see PMWOUT INDEX timer counters size of 11 1 timer register default values 11 11 timer disable timing diagram of 11 2 TPERIODx register 3 53 TPWIDTH x registers 3 53 Programmin
23. wise cleared AN Set if the floating point result is negative other wise cleared AV Set if the postrounded result overflows unbiased exponent gt 127 otherwise cleared AC Cleared AS Cleared Al Set if either of the input operands is a NAN or if they are opposite signed Infinities otherwise cleared B 26 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference Fn Fx Fy Function Subtracts the floating point operand in register Fy from the floating point operand in register Fx The normalized result is placed in register Fn Rounding is to nearest IEEE or by truncation to a 32 bit or to a 40 bit boundary as defined by the rounding mode and rounding boundary bits in MODE Postrounded overflow returns Infinity round to nearest or NORM MAxX round to zero Postrounded denormal returns Zero Denormal inputs are flushed to Zero A NAN input returns an all 1s result Status Flags Flag Description AZ Set if the postrounded result is a denormal unbiased exponent lt 126 or zero otherwise cleared AU Set if the postrounded result is a denormal other wise cleared AN Set if the floating point result is negative other wise cleared AV Set if the postrounded result overflows unbiased exponent gt 127 otherwise cleared AC Cleared AS Cleared Al Set if either of the input operands is a NAN or if they are like signed
24. 8 15 bers DAG2 ADSP 21065L SHARC DSP Technical Reference A 21 Opcode Notation Table A 5 Opcode acronyms Contd Bit Field Description States PMM Modify M register 8 15 numbers DAG2 PPO PC stack pop code 0 No stack pop 1 Stack pop PPU PC stack push code 0 No stack push 1 Stack push RELADDR PC relative address field SPO Status stack pop code 0 No stack pop 1 Stack pop SPU Status stack push code 9 No stack push 1 Stack push SREG System Register code 0 15 see Universal Register Codes on page A 24 TERM Termination Condition 0 31 codes U Update index 1 reg 0 Premodify no update ister 1 Postmodify with update UREG Universal Register code 0 256 see Universal Register Codes on page A 24 RA RM RN Register file loca 0 15 RS RX RY tions for compute oper ands and results A 22 ADSP 21065L SHARC DSP Technical Reference Instruction Set Reference Table A 5 Opcode acronyms Contd Bit Field Description States RXA ALU x operand Register 8 11 File location for mul tifunction operations RXM Multiplier x operand 0 3 Register File location for multifunction oper ations RYA ALU y operand Register 12 15 File location for mul tifunction operations RYM Multiplier y operand 4 7 Register File location for multifunction oper ations ADSP 21065L SHARC DSP Tec
25. A data GPTOA TITOB IMTOB 16 18 DMA channel 5 parameter registers CTOB CPTOB SPORTO transmit B data GPTOB IIT1A IMT1A 16 32 DMA channel 6 parameter registers CTIA CPT1A SPORTI transmit A data GPT1A I B IMT1B 16 32 DMA channel 7 parameter registers CTIB GPI LB SPORTI transmit B data GPT1B TIEPO IMEPO 16 32 DMA channel 8 parameter registers CEPO CPEPO external port buffer 0 GPEPO EIEPO EMEPO ECEPO IIEP1 IMEP1 16 32 DMA channel 9 parameter registers CERI CREPT external port buffer 1 GPEP1 EIEPI EMEP1 ECEP1 E 34 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers Table E 12 DMA buffer DB IOP registers Register Width Description EPBO 48 External port FIFO buffer 0 EPB1 48 External port FIFO buffer 1 DMACO 16 DMA channel 8 control register or external port buffer 0 DMAC1 16 DMA channel 9 control register or external port buffer 1 Table E 13 Serial port SP IOP registers Register Width Description STCTLO 32 SPORTO transmit control register SRCTLO 32 SPORTO receive control register TXO_A 32 SPORTO transmit data buffer A RXO_A 32 SPORTO receive data buffer A TDIVO 32 SPORTO transmit divisors RDIVO 32 SPORTO receive divisors TCSO 32 SPORTO ltichannel transmit selector RCSO 32 SPORTO ltichanne
26. B COMPUTE OPERATION REFERENCE Compute operations execute in the Multiplier the ALU and the Shifter The 23 bit compute field is like a mini instruction within the instruction and can be specified for a variety of compute operations This appendix describes each compute operation in detail including its assembly lan guage syntax and opcode field A compute operation is one of the following e Single function operations involve a single computation unit e Multifunction operations specify parallel operation of the Multi plier and the ALU or two operations in the ALU e The MR register transfer is a special type of compute operation used to access the fixed point accumulator in the Multiplier For more information see MR Rn Rn MR on page B 60 The operations in each category are described in the following sections For each operation the assembly language syntax the function and the opcode format and contents are specified For more information see Table A 1 on page A 11 ADSP 21065L SHARC DSP Technical Reference B 1 Single Function Operations Single Function Operations The compute field of a single function operation looks like PRP EPSP E PP PPE EEE PEE OQ CU OPCODE RN RX RY An operation determined by 0PCODE is executed in the computation unit specified by CU The x and the y operands are received from data registers RX and RY The result operand is returned to data register RN The CU com
27. Bits to the left of the extracted field are set to 0 in register Rn The float ing point extension field of Rn bits 7 0 of the 40 bit word is set to all Os Bit6 and len6 can take values between 0 and 63 inclusive allowing for extraction of fields ranging in length from 0 to 32 bits and from bit posi tions ranging from 0 to off scale left 39 7 0 Rx extract field bit6 starting bit position for extract referenced from LSB of 32 bit field bit6 reference point 39 7 0 i M extracted bits placed in Rn starting at LSB of 32 bit field Figure B 3 Field alignment B 82 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference Example 39 31 23 5 7 0 assaz abc defghijk 1mn jerem RX len6 bits bit position bit6 from reference point 39 31 23 5 7 0 00000000 00000000 00abcdef ghijkimn 00000000 Rn Status Flags Flag Description SZ Set if the output operand is 0 otherwise cleared SV Set if any bits are extracted from the left of the 32 bit fixed point input field i e if leno bit6 gt 32 otherwise cleared SS Cleared ADSP 21065L SHARC DSP Technical Reference B 83 Shifter Operations Rn FEXT Rx BY Ry SE Rn FEXT Rx BY lt bit gt lt len gt SE Function Extracts and sign extends a field from register Rx to register Rn The output field is placed right aligned in the fixed point field of Rn Its length is determined by the Jen field in register
28. CONTENTS Sie Oe ax ccndu ania maienisrsenee Rn LSHIFT Rx BY Ry Raes LSHIFT Re BY cabs oiccicso lei iccencadidac sg ney iesauecodenze Rn Rn OR LSHIFT Rx BY Ry Rn Rn OR LSHIPT Rx BY lt cdataBs socccscccccccecsesecnae dint ia Rn ASHIFT Rx BY Ry Kn ASHIFT Re BY lt clataB se accociscdsinsisansecssedcanacnetuannsiads Rn Rn OR ASHIFT Rx BY Ry Rn Rn OR ASHIFT Rx BY lt data8 gt oo ceeceeeeceeeeeceeeeeeeeeeees Rn ROT Rx BY Ry Rive ROT Re BY lt a eera sees adeodis Rn BCLR Rx BY Ry Ras BCLR Re EY adati oe otic et ects nai ada eatedde Rn BSET Rx BY Ry Rn BSET Rx BY lt data8 gt nicorae Rn BTGL Rx BY Ry Rn BIG Re BY edata8 gt veces cdisiosinsintimeicnletasineecaeueleads BTST Rx BY Ry Biot Re ET ogee ie ees Rn FDEP Rx BY Ry Rn FDEP Rx BY lt bitG gt lt lenG gt o cee eee cece eeeeeceeeeceeeeees Rn Rn OR FDEP Rx BY Ry Rn Rn OR FDEP Rx BY lt bitG gt lt lenG gt oo eee eeeceeeceeeee Rn FDEP Rx BY Ry SE Rn FDEP Rx BY lt bit6 gt lt len6 gt SE cece eee ceeeeeecee eee Rn Rn OR EDEP Rx BY Ry SE Rn Rn OR FDEP Rx BY lt bit6 gt lt len6 gt SE wo viii ADSP 21065L SHARC DSP Technical Reference CONTENTS Rn FEXT Rx BY Ry Rive FEAT Rs BY cbt lene gicicicmeciedersnasatinoarmanss B 82 Rn FEXT Rx BY Ry SE Rn FEXT Rx BY lt bitG gt lt lenG gt SE ccccccccccevevecscnsveservesens B 84 Ris E Pe ca eh lee B 86 ee ee E A EN E EA B 87 Ras LETIA Ei e
29. Examples R7 BSET R6 BY RO DM IO M3 R5 PM 1I11 M15 R4 R8 DM 14 M1 PM 112 M12 RO Type 1 Opcode 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 DM DM DREG PMI PM PM DREG lap fo ss Oo F es tn E 21 20 19 18 17 16 15 14 13 12 11f10 9 fe 7 fe J5 l4 3 COMPUTE A 30 ADSP 21065L SHARC DSP Technical Reference Description Instruction Set Reference Bits DMD PMD DM DREG PM DREG DMI PMI DMM PMM COMPUTE Select the access types read or write Specify Register File locations Specify I reg Specify M reg ters Defines a co parallel wit no compute op tion isters for data and program memory isters used to update the I regis pute operation to be performed in the data accesses this is a NOP if eration is specified in the instruc ADSP 21065L SHARC DSP Technical Reference A 31 Group Instructions Compute amp Move Compute Type 2 Compute operation optional condition Syntax IF COND compute Function Conditional compute instruction The instruction is executed if the speci fied condition tests true Examples IF MS MRF 0 F6O F2 F3 2 Type 2 Opcode 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 000 00001 COND COMPUTE Bits Descr
30. Host Interface In this manual see Appendix A Instruction Set Reference The SYSTAT register is memory mapped in internal memory at address 0x0003 After reset all bits in SYSTAT except IDC 1 0 and CRBM 1 0 are initialized to zero 0 as shown in Figure E 19 After reset IDC 1 0 is equal to the value of the processor s ID _ inputs and CRBM 1 0 is equal to the ID of the current bus master E 106 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141312 1110 9 8 7 6 54 3 2 1 HSTM Host Mastership BSYN Bus Synchronization CRBM Current Bus Master IDC ID Code SWPD Data Pending in Slave Write FIFO VIPD Vector Interrupt Pending HPS Host Packing Status 0 fully packed 1 partially packed Figure E 19 SYSTAT register bits ADSP 21065L SHARC DSP Technical Reference E 107 IOP Registers Table E 26 lists and describes the individual bits of the SYSTAT register Table E 26 SYSTAT register Bit Name Description 0 HSTM Host mastership Indicates whether or not the host processor is the current bus master 0 bus slave 1 bus master 1 BSYN Bus synchronization Indicates whether or not bus arbitration logic is synchronized 0 unsynchronized 1 synchronized 23 Reserved 4 5 CRBM Current bus master Identifies the ID code of the ADSP 21065L that is the current bus ma
31. Immediate Move eseseeecereeereesrsn A 62 Ureg DM PM direct addressing Type 14 eeeeeeenee A 63 Ureg lt gt DM PM indirect addressing Type 15 neeesser A 65 Immediate data DM PM Type 16 cseeceesessesseeeeseeteeees A 67 Immediate data ureg Type 17 cscssceseeseesescessereeseeseeseeneeees A 69 Group TY Instructions Miscellaneous ccc tcsisccccstccccceascessctecesecess A 70 System Register Bit Manipulation Type 18 sscnccscsccuseacecensecce A 71 Register Modity bit reverse Type 19 sccvssoisniisnrnsnetwsiensescons A 73 iv ADSP 21065L SHARC DSP Technical Reference CONTENTS Push Pop Scacks Flush Cache Type 20 scsccoisctscsssxeescasiccrscoys A 75 Popi eS II arangis A 77 Te CE nen A A 78 idele Dpr 2 acceso shee ese eit ees A 79 Jomp Rirame Type J4 acai sicchicatainadigu te ateapmsianeannaewinainednns A 81 COMPUTE OPERATION REFERENCE Sinple Function Operations sradicare asa a a B 2 ALU MeO ceopiusri a eai B 2 Ris het RY eee A N B 6 Ris Ba Py cennere AAR B 7 kes Teeny eG ap ee B 8 Ras Rro Rya eee eee B 9 Ris iBReA TEN aenn a E A B 10 COMPR RY sestiseicatiitessentanaracivedeiiaasinwiacabeeualdntsiamedoiaas B 11 Rie Rte Ci cxcoinnsaniouuiennione aoe B 12 Ris Peel l aenn cians B 13 LEN e E a EE A E E B 14 ia Toe pera meets B 15 ile Re sonaa e E E B 16 Ro SABS Ri ccncoreninonaiota tann e B 17 Ris TASS Di acai ee ee ieee B 18 Ris RAND RY censere B 19 Pets ORDF sanieren B 20 kraf a OR Ry pn E So
32. Modify Summary sccccscticsiccierssessoussaicscneres Program Flow Control Summary sacwmicetisccensecrcttetisrcenees Immediate Moye Summary ose oe ees Miscellancous Instructions Samnmaiy smserisrrsniissnsnis Reference Notation SUMMAry sescecccoeesescestenriectacesecnomeeseon A 11 R sister Types SUMMAT iaaiiai enra a NAi A 15 Memory Addressing Summary ssaricenisinesonaraenon nina A 18 eae Morio aara eee A 19 Univeral Register Codet srnrisedecrinrneina A 24 ADSP 21065L SHARC DSP Technical Reference ill CONTENTS Group I Instructions Compute amp Move siincineincrscemccciinveeteoins A 28 Compute dreg DM dreg PM Type 1 w eeeeseeceseereteeeenees A 30 Compote Type Z roresnirpenrori nnana oah A 32 Compute ureg DM PM register modify Type 3 seess A 33 Compute dreg DM PM immediate modify Type 4 A 35 Compute ureg neg CINE S ccrieiiolcemnianioieenenas A 37 Immediate Shift dreg lt DM PM Type 6 eeeeseeeseeeteeeeees A 39 Lompute miodity ly pt T ssisinscrdancmndneiaionimacsenainen A 42 Group II Instructions Program Flow Control neseser A 44 Direct Fume a Oe vectectarertieicnieene eerie A 45 Indirect Jumys Call f Compute Type J ancnssonsssassiaaa A 48 Indirect Jump or Compute dreg DM Type 10 eeeeeee A 52 Return From Subroutine Interrupt Compute Type 11 A 55 Do Until Comater Expired Type 12 scccsesassussversseoatciececsecances A 58 A E oc ee AAA eee A 60 Group III Instructions
33. SPORT 1 transmit count reg SPORT 1 receive divisor reg SPORT 1 receive count reg SPORT 1 multichannel xmit selector SPORT 1 multichn xmit compand selector y E 122 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers SPORT 1 multichn rev compand selector SPORT 1 multichn rev compand selector SPORT 1 keyword register SPORT 1 keyword mask register define MTCCS1 Oxfa define MRCCS1 Oxfb define KEYWD1 Oxfc define IMASK1 Oxfd define TXO_A Oxe2 define RXO_A Oxe3 define TX1_A Oxf2 define RX1_A Oxf3 define TXO_B Oxee define RXO_B Oxef define TX1_B Oxfe define RX1_B Oxff Aliases for TX and Rx SPORT 0 transmit data buffer A SPORT 0 receive data buffer A SPORT 1 transmit data buffer A SPORT 1 receive data buffer A SPORT 0 transmit data buffer B SPORT 0 receive data buffer B SPORT 1 transmit data buffer B SPORT 1 receive data buffer B a ADSP 21065L SHARC DSP Technical Reference E 123 SYMBOL DEFINITIONS FILE def21065L h E 124 ADSP 21065L SHARC DSP Technical Reference F INTERRUPT VECTOR ADDRESSES Table F 1 lists all processor interrupts according to their bit position in the IRPTL and IMASK registers Four memory locations separate each interrupt vector For each vector Table F 1 also lists the address mne monic not required by the assembler and priority
34. Table E 17 DMA transfer modes MASTER HSHAKE EXTERN Description 0 0 0 Slave mode The DMA controller generates a DMA request whenever an RX buffer is not empty or a TX buffer is not fulll 0 0 1 Reserved ADSP 21065L SHARC DSP Technical Reference E 61 IOP Registers Table E 17 DMA transfer modes Cont d MASTER HSHAKE EXTERN Description 0 1 0 Hand Appl cha The DMA is a data asse Shake mode jes to the EPBx buffers nels 8 and 9 only DMA controller generates a equest when the DMARx line sserted and transfers the when the DMAGx line is ted Exte Appl cha den exce fers emo al handshake mode jes to the EPBx buffers els 8 and 9 only tical to handshake mode pt the DMA controller trans the data between external y and an external device Mast The tran buf eep is eep is fer is not full in master mode er mode DMA controller attempts to sfer data whenever the DMA ter gt 0 and either the RX er is not empty or the TX DMAR1 high if DMA channel 8 DMAR2 high if DMA channel9 in master mode Rese rved E 62 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers Table E 17 DMA transfer modes Cont d MASTER HSHAKE EXTERN Description 1 1 0 Paced master mode Applies to the EPBx
35. Table E 25 SYSCON register Contd Bit Name Description 8 IMDWO Internal memory block 0 data width Specifies the data word width of internal memory block 0 0 32 bit data 1 40 bit data Applications can store 48 bit instructions in block 0 regardless of the value of this bit For details see Chapter 5 Memory in ADSP 21065L SHARC DSP User s Manual 9 IMDW1 Internal memory block 1 data width Specifies the data word width of internal memory block 1 O 32 bit data 1 40 bit data Applications can store 48 bit instructions in block 1 regardless of the value of this bit For details see Chapter 5 Memory in ADSP 21065L SHARC DSP User s Manual 10 ADREDY Active drive REDY Changes the REDY signal to an active drive output 0 open drain o d l active drive a d ADSP 21065L SHARC DSP Technical Reference E 103 IOP Registers Table E 25 SYSCON register Contd Bit Name Description 11 BHD Buffer hang disable Enables disables the hang condition that occurs when the processor s core or an exter nal device tries to read an empty buffer or write a full buffer 0 enable buffer hang 1 disabled buffer hang After reset this bit is enabled Disabling this bit is useful for debugging applica tions 12 15 Reserved 16 17 EBPR External bus priority Specifies which of the processor s three internal buses PM DM and I 0 has priority
36. bootstrapping 256 word instructions 12 52 BSEL 12 51 CS 12 51 data bus alignment 5 53 DATA 12 51 described 12 51 DMACO register 12 49 12 52 12 53 EPROM chip select 12 53 external memory space address of first instruction 12 49 external port data EPD lines 12 53 generating EPROM addresses 5 53 MSx chip select line 5 53 multiprocessing 12 51 pin configuration 12 51 pin connections 5 53 12 51 program counter address at reset 12 53 reset start up sequence 12 53 RTI instructions 12 54 see also Host booting wait states and 12 52 wait states configuration 5 53 EPROM boot select see BSEL EPROM booting accessing EPROM after bootstrap 12 55 ACK 12 52 ADDR x 12 54 BMS and 12 53 boot hold off 12 52 BSO bit 12 55 DATAx 12 54 DMA controller operation 12 54 DMA count register and 12 54 EPROM chip select 12 53 external port data EPD lines 12 53 l 34 ADSP 21065L SHARC DSP User s Manual interrupt vector table locating 12 61 loading remaining EPROM data 12 55 multiprocessing 12 59 overriding BMS 12 55 program counter address at reset 12 53 reset start up sequence 12 53 RTI instructions 12 54 writing to BMS memory space 12 56 EQ condition 3 13 Execute cycle 3 4 Executing program from external memory space 40 bit data accesses 5 52 aligning internal addresses with external memory space 5 50 data access addressing 5 52 data packing 5 49 described 5 49 example add
37. carry Bit 4 ALU X input sign ABS amp MANT ops Bit 5 ALU fltg pt invalid operation Bit 6 Multiplier result negative Bit 7 Multiplier overflow Bit 8 Multiplier flt pt underflow Bit 9 Multiplier flt pt invalid op Bit 10 ALU fltg pt op Bit 11 Shifter overflow Bit 12 Shifter result zero Bit 13 Shifter input sign Bit 18 Bit test flag for system regs Bit 19 FLAGO value ADSP 21065L SHARC DSP Technical Reference E 117 SYMBOL DEFINITIONS FILE def21065L h define FLG1 define FLG2 define FLG3 define CACCO define CACC1 define CACC2 define CACC3 define CACC4 define CACC5 define CACC6 define CACC7 STKY register define AUS define AVS define AOS define AIS define MOS define MVS define MUS define MIS define CB7S define CB15S define PCFL define PCEM define SSOV define SSEM define LSOV define LSEM 0x00100000 0x00200000 0x00400000 0x01000000 0x02000000 0x04000000 0x08000000 0x 10000000 0x20000000 0x40000000 0x80000000 0x00000001 0x00000002 0x00000004 0x00000020 0x00000040 0x00000080 0x00000100 0x00000200 0x00020000 0x00040000 0x00200000 0x00400000 0x00800000 0x01000000 0x02000000 0x04000000 Bit 20 Bit 21 Bit 22 Bit 24 Bit 28 FLAGI value FLAG value FLAG3 value Compare Accumulation Bit 0 Bit 25 Bit 26
38. channels 9 79 SDA10 pin definition 12 10 state after reset 12 23 SDCKE pin definition 12 11 state after reset 12 23 SDCLKx pin definition 12 10 state after reset 12 23 SDEN SPORT DMA enable bit 6 23 9 16 9 22 defined 9 34 I S SPORT mode 9 65 multichannel receive comparisons and 9 74 setting up DMA on SPORT channels 9 79 SDRAM 2x clock output see SDCLKx SDRAM A10 pin see SDA10 SDRAM access 10 26 A11 pin and 16M devices 10 27 DQM pin operation 10 27 mapping ADDRx bits 10 26 multiplexed 32 bit SDRAM address diagram of 10 26 INDEX SDRAM bank select bit see SDRAM configuration SDRAM burst stop command see Bstop command SDRAM clock enable see SDCKE SDRAM column access strobe see CAS SDRAM configuration 10 13 active command delay 10 21 buffering option 10 17 CAS latency value 10 18 clock enables and non SDRAM systems 10 15 clock enables for heavy clock loads 10 16 clock enables for minimal clock loads 10 15 configuration parameters summary of 10 13 DSDCK1 10 9 10 15 DSDCTL 10 9 10 15 external memory bank mapping 10 16 IOCTL control bits 10 9 IOCTL register 10 9 10 13 IOCTL register default bit values diagram of 10 12 mapping processor addresses to SDRAM addresses 10 18 number of banks 10 16 page size 10 18 page size and device organization 10 19 page size and number of banks ADSP 21065L SHARC DSP User s Manual 1 101 INDEX 10 18 power up mode 10 19 power up sequence 10 9 power u
39. define TDIV1 Oxf4 define TCNT1 Oxf5 define RDIV1 Oxf6 define RCNT1 Oxf7 define MTCS1 Oxf8 define MRCS1 Oxf9 Serial Port registers DMA channel 8 index reg DMA channel 8 modify reg DMA channel 8 count reg DMA channel 8 chain pointer reg DMA channel 8 general purpose reg DMA channel 8 external index reg DMA channel 8 external modify reg DMA channel 8 external count reg DMA channel 9 index reg DMA channel 9 modify reg DMA channel 9 count reg DMA channel 9 chain pointer reg DMA channel 9 general purpose reg DMA channel 9 external index reg DMA channel 9 external modify reg DMA channel 9 external count reg SPORT 0 transmit control reg SPORT 0 receive control reg SPORT 0 transmit data buffer SPORT 0 receive data buffer SPORT 0 transmit divisor reg SPORT 0 transmit count reg SPORT 0 receive divisor reg SPORT 0 receive count reg SPORT 0 multichannel xmit selector SPORT 0 multichannel rev selector SPORT 0 multichn xmit compand selector SPORT 0 multichn rev compand selector SPORT 0 keyword register SPORT 0 keyword mask register SPORT 1 transmit control reg SPORT 1 receive control reg SPORT 1 transmit data buffer SPORT 1 receive data buffer SPORT 1 transmit divisor reg
40. enabling and disabling DMA interrupts 6 46 restrictions 6 40 PCSTKP data values 3 24 described 3 24 empty value 3 24 overflow value 3 24 pushing and popping 3 7 reading and delayed branches 3 24 write latency 3 24 PERIOD_CNYTx timer period count enable bit 11 6 described 11 8 Pin definitions 12 3 ACK 12 7 ADSP 21065L SHARC DSP User s Manual I 83 INDEX ADDR x 12 4 asynchronous inputs 12 3 BMS 12 13 BMSTR 12 13 BRx 7 10 12 14 BSEL 12 14 CAS 12 10 CLKIN 12 14 CPA 7 11 12 16 CS 12 8 DATAx 12 4 DMAGx 12 5 DMAR x 12 5 DQM 12 10 DRx_X 12 11 DTx_X 12 11 EMU 12 19 external port 12 4 FLAGx 12 16 GND 12 20 HBG 12 8 HBR 12 9 host interface 12 7 IDx 7 10 12 16 IRQx 12 17 JTAG emulator 12 19 miscellaneous 12 20 MSx 12 5 multiprocessor bus arbitration 7 10 NC 12 20 PWM_EVENTx 12 17 RAS 12 10 RCLKx 12 12 RD 12 17 REDY 12 9 RESET 12 18 RFSx 12 12 SBTS 12 6 SDA10 12 10 SDCKE 12 11 SDCLKx 12 10 SDRAM interface 12 10 SDWE 12 11 serial port 12 11 SW 12 6 synchronous inputs 12 3 system control 12 13 TCK 12 19 TCLKx 12 12 TDI 12 19 TDO 12 20 TFSx 12 12 TMS 12 20 TRST 12 20 unused inputs 12 3 VDD 12 20 WR 12 18 XTAL 12 19 Pin operation 12 26 asynchronous inputs 12 27 CLKIN frequencies see CLKIN frequencies external interrupt and timer pins 12 28 EZ ICE emulator see EZ ICE emulator Flag inputs see FLAGx 12 31 1 84 ADSP 21065L
41. format 2 4 temporary data storage 2 2 Compute type 2 instruction described A 32 example A 32 opcode A 32 syntax summary A 4 Compute and move modify instructions compute type 2 instructions A 4 compute dreg lt gt DM PM ADSP 21065L SHARC DSP User s Manual I 13 INDEX immediate modify type 4 instructions A 5 compute ureg lt gt DMI PM register modify type 3 instructions compute uregureg type 5 instructions A 5 IF COND A 4 immediate Shift dreg 7DM PM type 6 instructions A 5 summary of A 4 Compute operation reference compute operations B 1 multifunction operations B 94 see Multifunction operations multiplier operations B 50 see Multiplier operations shifter operations B 63 see Shifter operations single function operations see Single function compute oper ations compute operation reference single function operations B 2 Compute operations described B 1 types B 1 Compute dreg DM dreg PM type 1 instruction described A 30 example A 30 opcode A 30 Compute dreg lt DM PM immediate modify type 4 instruction described A 35 example A 35 opcode A 36 syntax summary A 5 Compute modify type 7 instruction example A 42 opcode A 42 Compute ureg gt DM PM register modify type 3 instruction example A 33 opcode A 34 syntax summary A 4 Compute ureg gt ureg type 5 instruction described A 37 example A 37 opcode A 37 syntax summary A 5 Concurrent DMA accesses of external me
42. internal interrupt vector table IIVT bit 5 30 multiprocessing data transfers and 7 25 SRST 7 21 7 23 SYSTAT register address of E 106 bit definitions 8 40 E 108 BSYN 7 22 7 42 8 40 CRBM 7 42 8 40 default bit values diagram of 7 41 8 43 E 107 described E 106 HPS 7 43 8 42 INDEX HSTM 7 41 8 40 IDC 7 42 8 41 initialization value E 106 multiprocessing data transfers and 7 25 multiprocessing status information 8 40 status bits 7 40 SWPD 7 35 7 42 VIPD 3 52 7 39 7 42 8 38 8 42 System bus arbitrating for control of 8 44 arbitration unit 8 44 8 51 core accesses of 8 48 host interface with 8 44 ISA 8 44 master processor accesses of 8 46 PCI 8 44 System bus access deadlock HBR 8 49 resolving SBTS 8 49 SBTS and HBR combination 8 49 System clock cycle reference for host interface operations 8 7 frequencies of operations 12 26 System configuration register see SYSCON register System configurations for interprocessor DMA 6 70 System control ADSP 21065L SHARC DSP User s Manual 1 119 INDEX BMS 12 13 BMSTR 12 13 BRx 12 14 BSEL 12 14 CLKIN 12 14 CPA 12 16 FLAGx 12 16 IDx 12 16 IRQx 12 17 pin definitions 12 13 PWM_EVENT x 12 17 RD 12 17 RESET 12 18 WR 12 18 XTAL 12 19 System design 12 1 accessing on chip emulation features 12 34 asynchronous inputs 12 3 12 27 basic single processor system diagram of 12 2 boot modes see Boot modes booting see Booting CLKIN fre
43. or by truncation as defined by the rounding mode bit in the MODE register Status Flags Flag Description AZ Set if the fixed point output is all Os otherwise cleared AU Cleared AN Set if the most significant output bit is 1 otherwise cleared AV Cleared AC Set if the carry from the most significant adder stage is 1 otherwise cleared AS Cleared Al Cleared B 10 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference COMP Rx Ry Function Compares the fixed point field in register Rx with the fixed point field in register Ry Sets the AZ flag if the two operands are equal and the AN flag if the operand in register Rx is smaller than the operand in register Ry The ASTAT register stores the results of the previous eight ALU compare operations in bits 24 31 These bits are shifted right bit 24 is overwritten whenever a fixed point or floating point compare instruction is executed The MSB of ASTAT is set if the X operand is greater than the Y operand its value is the AND of AZ and AN otherwise it is cleared Status Flags Flag Description AZ Set if the operands in registers Rx and Ry are equal otherwise cleared AU Cleared AN Set if the operand in the Rx register is smaller than the operand in the Ry register otherwise cleared AV Cleared AC Cleared AS Cleared Al Cleared ADSP 21065L SHARC DSP Technical Reference B 11 Single Function Operatio
44. parallel accumulators use as 2 29 Register File transfers 2 30 Multiplier operations 2 27 B 50 denormal operands 2 36 described 2 27 B 50 fixed point 2 27 fixed point operand format 2 27 fixed point results 2 28 see Multiplier fixed point results floating point 2 27 floating point operating modes 2 32 see Multiplier floating point op erating modes Fn Fx Fy B 62 input output rate 2 27 MOD1 options described B 52 summary of B 53 MOD2 options described B 51 summary of B 52 MR registers and fixed point results 2 28 MR Rn Rn MR B 60 MRB 0 B 59 MRB MRB Rx Ry mod2 B 55 MRB MRB Rx Ry mod2 B 56 MRB RND MRB mod1 B 58 MRB Rx Fy mod2 B 54 MRB SAT MRB mod1 B 57 MRF 0 B 59 MRF MRF Rx Ry mod2 B 55 MRF MRF Rx Ry mod2 B 56 MRF RND MRF mod1 B 58 MRF Rx Ry mod2 B 54 MRF SAT MRF mod1 B 57 Register File 2 27 Rn MRB Rx Ry mod2 B 55 Rn MRB Rx Ry mod2 B 56 Rn MRF Rx Ry mod2 B 55 Rn MRF Rx Ry mod2 B 56 Rn RND MRB mod1 B 58 Rn RND MRF mod1 B 58 Rn Rx Ry mod2 B 54 Rn SAT MRB mod1 B 57 Rn SAT MRF mod1 B 57 status flag update 2 34 status of most recent 2 34 summary of B 50 Multiplier registers summary of A 17 Multiplier status flags 2 34 ASTAT status bits summary of 2 34 1 76 ADSP 21065L SHARC DSP User s Manual described 2 34 fixed point underflow results 2 37 floating point invalid operation 2 36 MI floating point invalid operation 2 34 MIS floating point invalid operation 2 34 MN result negative 2 34 MO
45. see RDI Vx register SPORT receive comparison mask register see IMASK register INDEX SPORT receive comparison register see KEYWDx register SPORT receive control register see SRCTLx register SPORT receive data buffer see RXx_z data buffer SPORT RESET data buffer read write results 9 7 data buffer status bits and 9 7 described 9 7 hardware method 9 8 methods 9 7 RXS receive data buffer status bits 9 7 RXx_z data buffer 9 7 software method 9 8 transmit receive operability 9 8 TXS transmit data buffer status bits 9 7 TXx_z data buffer 9 7 SPORT serial word length 9 48 described 9 48 DMA chaining and 9 49 RXx_z buffer operation 9 49 SLEN bit value 9 48 TXx_z buffer operation 9 49 SPORT single word transfers BHD buffer hang disable bit 9 86 core hang condition and 9 86 core updates of STCTLx and SRCTL register status bits 9 86 described 9 86 ADSP 21065L SHARC DSP User s Manual 1 113 INDEX interrupt driven I O implementing 9 86 interrupts 9 86 SPORT transmit clock and frame sync divisors register see TDIVx register SPORT transmit control register see STCTLx register SPORT transmit data buffer see TXx_z data buffer SPORTO receive DMA channel 0 1 interrupt 9 6 SPORTO transmit DMA channel 4 5 interrupt 9 6 SPORT1 receive DMA channel 2 3 interrupt 9 6 SPORTI transmit DMA channel 6 7 interrupt 9 6 SPROI interrupt function and priority 9 6 SPRII interrupt function and priority 9 6 SPT
46. teas active command time 10 7 bank cycle time and 10 41 tec bank cycle time 10 7 tecp RAS to CAS delay 10 8 tgp precharge time 10 8 TRST pin definition 12 20 power up procedures and 12 35 state after reset 12 25 TRUE condition 3 12 3 15 TRUNC floating point rounding mode bit 2 14 multiplier floating point operation 2 32 multiplier floating point operations 2 33 round to nearest 2 15 round to zero 2 15 treovuc switching characteristic 8 12 TUVE transmit underflow status bit 9 14 9 17 9 38 defined 9 36 described 9 39 TXS transmit data buffer status bits 9 17 9 38 defined 9 37 described 9 39 SPORT reset and 9 7 TXx_z data buffer 9 5 9 9 data formats and 9 44 described 9 13 memory mapped address and reset value 9 10 9 11 9 12 multichannel operation with DMA enabled 9 69 multichannel TFS operation 9 69 operation see TXx_z data buffer operation read write restrictions 9 15 reading writing 9 14 size of 9 13 SPORT reset and 9 7 transmit shift buffer 9 44 writes to a full buffer 9 14 TXx_z data buffer operation 9 13 architecture 9 13 described 9 13 interrupts 9 14 storage capacity 9 14 transmit underflow condition 9 14 Type 10 instruction 8 48 and core accesses of the system bus 8 48 U Unconditional instructions 1 124 ADSP 21065L SHARC DSP User s Manual IF TRUE 3 12 Uniprocessor to microprocessor bus interface 8 51 Universal registers A 15 and bit wise operations 12 29 and bitwise o
47. writes to a full slave write FIFO buffer and 8 17 Ref command 10 38 Refresh command SDRAM see Ref command Register File 2 9 access characteristics 2 9 alternate registers 2 11 see Alternate register file registers computation units and 2 9 data writes sources of 2 10 defined 5 6 fields for Shifter bit field deposit and extract operations diagram of 2 42 fields for Shifter instructions diagram of 2 42 individual data registers 2 10 see Individual register file registers MR register transfers 2 30 multifunction operation operands and 2 50 multifunction operations and B 94 multiplier fixed point results 2 28 PM data bus transfers and 5 11 shifter operations and B 63 shifter output 2 41 SPORT control registers and 9 12 structural and functional characteristics 2 9 system register bit manipulation instruction and E 6 register file ALU operations and 2 13 Register handshake message passing protocol 7 37 8 37 I 94 ADSP 21065L SHARC DSP User s Manual Register modify bit reverse type 19 instruction described A 73 example A 73 opcode with bit reverse A 74 opcode without bit reverse A 73 Register types multiplier registers A 17 summary of A 15 universal registers A 15 Register write back message passing protocol 7 38 8 38 Reinitializing DMA channels FLSH 6 18 latency 6 18 restrictions 6 18 Requesting bus lock 7 34 RESET bit write restriction 3 44 bus arbitration synchronization after 7 21 input hyste
48. 000 Rn FIX Fx BY Ry 01 100 Rn FIX Fx 00 100 Rn TRUNC Fx BY Ry 01 110 Rn TRUNC Fx 00 110 Fn FLOAT Rx BY Ry 01 1010 Fn FLOAT Rx 00 1010 Fn RECIPS Fx 00 0100 Fn RSQRTS Fx 00 0101 Fn Fx COPYSIGN Fy 10 0000 Fn MIN FX Fy 10 0001 FN MAX FX Fy 10 0010 Fn CLIP Fx BY Fy 10 0011 ADSP 21065L SHARC DSP Technical Reference B 5 Single Function Operations Rn Rx Ry Function Adds the fixed point fields in registers Rx and Ry The result is placed in the fixed point field in register Rn The floating point extension field in Rn is set to all Os In saturation mode the ALU saturation mode bit in MODE set positive overflows return the maximum positive number Ox7FFF FFFF and negative overflows return the minimum negative number 0x8000 0000 Status Flags Flag Description AZ Set if the fixed point output is all Os otherwise cleared AU Cleared AN Set if the most significant output bit is 1 otherwise cleared AV Set if the XOR of the carries of the two most signif icant adder stages is 1 otherwise cleared AC Set if the carry from the most significant adder stage is 1 otherwise cleared AS Cleared Al Cleared B 6 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference Rn Rx Ry Function Subtracts the fixed point field in register Ry from the fixed point field in register Rx The result is placed in the fixed
49. 1 Bit reverse for I0 uses DMSO only define SRCU 0x00000004 Bit 2 Alt reg select for comp units define SRD1H 0x00000008 Bit 3 DAGI alt register select 7 4 define SRDIL 0x00000010 Bit 4 DAGI alt register select 3 0 define SRD2H 0x00000020 Bit 5 DAG2 alt reg select 15 12 define SRD2L 0x00000040 Bit 6 DAG2 alt register select 11 8 define SRRFH 0x00000080 Bit 7 Reg File alt select R 15 8 define SRRFL 0x00000400 Bit 0 Reg File alt select R 7 0 define NESTM 0x00000800 Bit 11 Interrupt nesting enable define IRPTEN 0x00001000 Bit 12 Global interrupt enable define ALUSAT 0x00002000 Bit 13 Enable ALU fixed pt saturation define SSE 0x00004000 Bit 14 Enable short word sign exten define TRUNC 0x00008000 Bit 15 1 flt pt trunc 0 Rnd to near define RND32 0x00010000 Bit 16 1 32b flt pt round 0 40b rnd define CSEL 0x00060000 Bit 17 18 CSelect Bus Mastership E 116 ADSP 21065L SHARC DSP Technical Reference MODE2 register define IRQOE 0x00000001 define IRQIE 0x00000002 define IRQ2E 0x00000004 define PERIOD_CNTO 0x00000008 define CADIS 0x00000010 define TIMENO 0x00000020 define BUSLK 0x00000040 define PWMOUTO 0x00000080 define INT_HIO 0x00000100 define PULSE _HI0 0x00000200 define PERIOD_CNT1 0x00000400 define TIMEN1 0x00000800 define PWMOUT1 0x00001000 define INT_HI1 0x00002000 def
50. 12 36 executing synchronous multiprocessor operations 12 40 I 38 ADSP 21065L SHARC DSP User s Manual JTAG interface and 12 36 pin connections in nontesting environments 12 38 probe 12 36 scan path diagram of 12 40 signal termination 12 39 target board connector 12 36 see EZ ICE target board connec tor EZ ICE target board connector diagram of 12 38 pin strip header 12 37 specifications 12 37 F FDEP bit field deposit instruction 2 43 bit field diagram of 2 43 example diagram of 2 44 Fetch address register 3 6 Fetch cycle 3 4 FEXT bit field extract instruction 2 43 example diagram of 2 45 FEXT Rx BY Ry operation described B 82 example B 83 shifter status flags B 83 Fixed priority for external port channels 6 38 Fixed point formats 2 7 32 bit formats diagram of C 8 64 bit signed products diagram of C 10 INDEX 64 bit unsigned products diagram of C 9 ALU data and C 9 described C 8 fractional format C 8 multiplier data C 9 types C 8 Fixed point MR register operations clear MR register 2 30 described 2 30 rounding MR register 2 30 saturate MR register 2 31 Fixed point multiplier results see Multiplier fixed point results Fixed point multiply and accumulate instructions summary of 2 51 Fixed point operations ALU inputs 2 13 ALU results 2 13 ALU single function compute Operations summary of B 3 operands and results format of 2 13 results format of 2 13 Fixed point saturation 2 14 F
51. 12 45 Series terminated transmission line 12 43 Setting DMA channel prioritization 6 35 Setting up DMA transfers 6 9 loading the C count register 6 9 see also DMA parameter registers loading the II index register 6 9 see also DMA parameter registers loading the IM modify register ADSP 21065L SHARC DSP User s Manual 1 105 INDEX 6 9 see also DMA parameter registers writing the DMA control registers 6 9 see also DMACx registers writing the DMA parameter registers 6 9 see also DMA parameter registers Setting up multiple DMA operations 6 39 Setting up SPORT DMA transfers 6 23 see SPORT DMA Shadow write FIFO 5 39 7 32 Shared bus multiprocessing 8 36 Shifter bit field deposit and extract operations 2 42 bit field definitions 2 43 described 2 42 FDEP bit field deposit instruction example diagram of 2 44 FDEP instruction 2 43 FDEP instruction bit field diagram of 2 43 FEXT bit field extract instruction 2 43 example diagram of 2 45 Register File fields for diagram of 2 42 Y input 2 42 Shifter instruction set summary 2 47 Shifter operations 2 41 bit field deposit and extract 2 42 see Shifter bit field deposit and ex tract operations BTST Rx BY data8 B 73 BTST Rx BY Ry B 73 data transfers 2 41 described B 63 FDEP field alignment diagram of B 78 FDEP diagram of B 74 FEXT field alignment diagram of B 82 FEXT Rx BY Ry B 82 Fn FUNPACK Rx B 92 instruction set summary 2 47 operand
52. 23 control registers 6 22 data transfers 6 7 6 22 and the STCTLx and SRCTLx registers 6 23 data packing 6 22 direction of 6 7 6 22 SCHEN DMaA control bit 6 23 INDEX setting up 6 23 DMaA driven data transfer mode 9 65 see DMA driven data transfer mode enabling 9 65 internal DMA request and grant 6 35 interrupt driven data transfer mode 9 65 see Interrupt driven data transfer mode interrupts 6 23 SDEN DMA control bit 6 23 SPORT DMA block transfers channel priorities 9 78 described 9 77 DMA channels 9 77 DMA interrupts with packing enabled 9 79 packing 9 78 word size 9 78 SPORT DMA chaining 9 85 chain pointer register and 9 85 described 9 85 see also DMA chaining SPORT DMA channels 9 77 SPORT DMA interrupts EPOI 6 23 EP1I 6 23 SPROI 6 23 SPRII 6 23 SPTOI 6 23 SPT1I 6 23 ADSP 21065L SHARC DSP User s Manual I 111 INDEX SPORT DMA operation 9 79 count register and interrupts 9 81 DMA chaining enabling 9 79 DMA parameter registers 9 79 see SPORT DMA parameter reg asters enabling 9 79 RX buffer transfers 9 80 SCHEN 9 79 SDEN 9 79 TX buffer transfers 9 80 SPORT DMA parameter registers 9 79 architecture 9 81 chain pointer register 9 82 count register 9 81 CPRx_X 9 80 CPTx_X 9 80 CRx_X 9 80 CTx_X 9 80 described 9 81 GPRx_X 9 80 GPTx_X 9 80 IIRx_X 9 80 IITTx_X 9 80 IMRx_X 9 80 IMTx_X 9 80 index register 9 81 internal memory data buffer and 9 81 interrupts 9 81 loadin
53. 25 VIRPT register 7 25 I 78 ADSP 21065L SHARC DSP User s Manual Multiprocessing DMA transfers 7 30 described 7 30 DMA packing 7 31 DMAGx 7 30 DMAR x 7 30 extending internal memory space access 7 30 external handshake mode DMA configuration 7 32 external port DMA channels and 7 30 handshake mode DMA configuration 7 31 slave mode DMA configuration 7 31 to on chip memory 7 30 7 31 types 7 30 Multiprocessing EPBx transfers 7 27 core hang 7 29 DEN DMA enable bit 7 29 DMA block transfers 7 27 external port buffers 7 27 FLSH DMA flush buffers and status bit 7 29 flushing the EPBx buffers 7 29 interrupts 7 29 single word transfers 7 27 7 28 single word non DMaA transfers 7 29 types 7 27 writing to a full buffer 7 28 Multiprocessing ID see Dx INDEX Multiprocessing system architecture cluster multiprocessing see Cluster multiprocessing data bandwidth bottlenecks 7 6 data flow multiprocessing see Data flow multiprocessing interprocessor communication overhead 7 6 nodes 7 6 shared global memory 7 6 Multiprocessor booting 12 58 BEL 12 59 BMS 12 59 CS 12 59 EPROM boot sequence 12 59 from one EPROM diagram of 12 60 HBR 12 59 host boot pin configuration 12 59 host boot sequence 12 59 Multiprocessor bus arbitration 7 10 acquiring the bus 7 12 BRx 7 10 BIC 7 12 bus request and read write timing diagram of 7 15 bus synchronization operation 7 11 core priority access see
54. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1312 1110 9 8 7 MASTER DMA Master mode O disable 1 enable HSHAKE DMA Handshake O disable 1 enable INTIO Single word Interrupts ext port FIFO O disable 1 enable EXTEN Ext Devices to Ext Mem DMA 1 ext mode FLSH Flush Ext Port FIFO 1 flush FS Ext Port FIFO Status MSWE 00 empty Most Significant Word First packing order 10 partially full O disable 11 full 1 enable Figure E 6 DMAC x register bits 5 4 3 2 1 DEN DMA Enable for ext port O disable 1 enable CHEN DMA Chaining Enable for ext port O disable 1 enable TRAN DMA chn direction O read from ext mem 1 write to ext mem PS Packing Status read only 00 packing done 01 1st stage all modes 10 2nd stage 16 to 48 mode or 32 to 48 mode DTYPE Data Type O data 1 instructions PMODE Packing Mode 00 no packing 01 16 32 10 16 48 11 32 48 ADSP 21065L SHARC DSP Technical Reference E 55 IOP Registers Table E 16 lists and describes the individual bits of the DMACx register Table E 16 DMACx register Bit Name Description 0 DEN DMA enable for external ports Enables disables DMA operations on the external port buffers 0 disable 1 enable 1 CHEN DMA chaining enable for external ports Enables disables DMA chaining operations on the external port buffers 0 disable With DEN 0 specifies both DMA and DMA chaining disabled With DEN 1
55. 34 SENDN 9 35 setting the serial clock frequency 9 60 SLEN 9 35 SPEN 9 35 SPL 9 36 TCLK 9 28 TFS 9 30 TFSR 9 36 transmit configuration 9 59 transmit control bits 9 15 TUVE 9 36 TXS 9 37 using both transmitters simultaneously 9 59 Starting a new DMA sequence 6 9 6 29 Starting address for contiguous 32 bit data 5 37 Starting address of 32 bit data equations for 5 35 Starting and stopping DMA sequences 6 48 Status stack 3 7 current values of ASTAT and MODEI 3 49 flags 3 54 programmable timer interrupts and 11 9 pushing and popping 3 7 pushing and popping ASTAT 12 34 pushing and popping IOSTAT 12 34 RTI pop of 3 16 size of 3 48 stack pointer status 3 49 Status stack empty flag 3 54 Status stack flags 3 54 access of 3 54 empty 3 55 overflow and full 3 54 setting 3 54 summary of 3 54 Status stack overflow flag 3 54 Status stack pointer moving 3 49 status stack pushes and pops of 3 49 Status stack save and restore 3 48 ASTAT register 3 48 I 116 ADSP 21065L SHARC DSP User s Manual described 3 48 FLAG3 9 bit values 3 48 interrupts that automatically push the status stack 3 48 JUMP CI instruction 3 48 MODE register 3 48 RTI instruction 3 48 status and control bit preservation 3 48 status and mode contexts 3 48 STCTL register 6 23 9 9 9 15 address of E 90 bit definitions E 94 CHNL 9 17 9 26 CKRE 9 16 9 26 control bit definitions 9 26 control bits summary of 9 1
56. 63 multichannel SPORT mode transmit data valid signal 9 69 pin definition 12 12 SPORT loopback mode 9 88 state after reset 12 24 TIMEN x timer enable bit 11 1 described 11 8 Timer control bits and interrupt vectors INT_HIcx timer interrupt vector location 11 9 PERIOD_CNT lt x timer period count enable 11 8 PULSE_HIx timer leading edge select 11 8 PWMOUTx timer mode control 11 8 TIMEN timer enable 11 8 INDEX Timer counter timer mode see PMWOUT Timer interrupts and the status stack 11 9 described 11 9 logical OR of both timer interrupts 11 9 TMZHI and 11 9 Timer pins see PWM_EVENTx Timer registers IOP register addresses of 11 12 TCOUNTx 11 11 TPERIODx 11 11 TPWIDTH x 11 11 TMS pin definition 12 20 state after reset 12 25 TPERIOD x register 11 1 PWMOUT timer mode 11 3 reset values 11 11 size of 11 1 TPWIDTHx register 11 1 PWMOUT timer mode 11 3 reset values 11 11 size of 11 1 TRAN DMA transfer direction bit 6 14 8 28 described 6 15 direction of DMA transfers 6 15 single word EPBx transfers 8 20 Transfer control block see TCB Transfer timing example multichannel SPORT mode 9 68 ADSP 21065L SHARC DSP User s Manual 1 123 INDEX Transferring data between the PM and DM buses 5 12 Transferring data to and from memory 5 7 Transmit clock TCLKx pins 9 4 Transmit frame sync TFSx pins 9 4 Transmit shift register 9 5 Transmit underflow status see TUVF transmit underflow status bit
57. 9 accesses by external devices 9 12 bit definitions 9 26 changing operation mode 9 13 control and status bit active state 9 12 core updates of status bits 9 15 IMASK 9 9 9 11 9 12 KEYWDx 9 9 9 10 9 12 memory mapped addresses and reset values summary of 9 10 MRCCSx 9 9 9 10 9 12 MRCSx 9 9 9 10 9 11 MTCCSx 9 9 9 10 9 11 MTCSx 9 9 9 10 9 11 programming 9 12 RDIVx 9 9 9 10 9 11 reading writing 9 12 SRCTLx 9 9 9 10 9 11 status bits 9 38 STCTLzx 9 9 9 10 9 11 summary of 9 9 symbolic names 9 12 TDIVx 9 9 9 10 9 11 transmit and receive 9 15 see also STCTLx register and SRCTLx register write and effect latency 9 13 SPORT data buffers 9 9 core hang condition 9 15 described 9 13 memory mapped addresses and reset values summary of 9 10 read write restrictions 9 15 reads write of 9 14 I 110 ADSP 21065L SHARC DSP User s Manual receive data buffer operation 9 14 receive shift register 9 13 RXx_z 9 9 9 10 9 11 9 12 size of 9 13 summary of 9 9 transmit data buffer operation 9 13 TXx_z 9 9 9 10 9 11 9 12 SPORT data packing and unpacking 9 47 data justification 9 47 interrupts 9 48 short word space addresses and 9 48 SPORT data word formats 9 44 companding see Companding data type 9 44 see also DTYPE data type bits SPORT divisor registers see RDIVx register and TDIVx register SPORT DMA 9 65 channel assignments 6 22 channels 6 22 connection to internal memory space 6 27 control bits 6
58. 9 4 data transfer synchronization 9 4 data transfers between SPORTs and memory see SPORT memory transfers 1 104 ADSP 21065L SHARC DSP User s Manual data transmit outputs 9 4 data type and nonmultichannel operation 9 44 data word formats 9 44 diagram of 9 3 DMA operation 9 79 driver considerations 9 88 DRx_X 12 11 DTx_X 12 11 features 9 1 frame sync logic level 9 55 frame sync options 9 52 see SPORT frame sync options frame synchronization 9 5 IS mode 9 61 see S SPORT mode internally generated clock frequencies 9 5 interrupts see SPORT interrupts loopback mode 9 88 MSB LSB data word format 9 48 multichannel mode 9 67 see Multichannel SPORT mode operation cycles 12 27 operation summary 9 5 pin definitions 12 11 pin states after reset 12 24 point to point connections on 12 45 programming examples 9 89 RCLKx 12 12 RDIV x register 9 5 receive clock signal RCLKx 9 5 receive frame sync signal RFS INDEX 9 5 receive shift register 9 5 register and control parameter symbolic names 9 37 reset see SPORT RESET RFSx 12 12 RS 232 devices and 9 5 serial data word length 9 48 SPORT data buffer read write results 9 7 standard mode see Standard SPORT mode TCLKx 12 12 TDIVx register 9 5 TFSx 12 12 transmit clock signal TCLKx 9 5 transmit frame sync signal TFS 9 5 transmit shift register 9 5 TXx_z data buffer 9 5 UARTSs and 9 5 Serial RESET see SPORT RESET Series termination resistors
59. BMAX Bus timeout maximum register DMAC p External port DMA control register for DMA channels 8 and 9 DMASTAT DMA channel status register Contains the status bits for each DMA channel IOCTL SDRAM and programmable I O port for FLAG _4 control regis ter IOSTAT Programmable I O port status register for FLAG 1_4 ADSP 21065L SHARC DSP Technical Reference E 37 IOP Registers KEYMASK o Key word mask registers for serial ports 0 and 1 KEYWD1 9 Key word registers for serial ports 0 and 1 MRCCS o Multichannel receive companding control registers for serial ports 0 and 1 MRCS Multichannel receive control registers for serial ports 0 and 1 MSG7_9 Message registers MTCCS 0 Multichannel transmit companding control registers for serial ports 0 and 1 MTCS o Multichannel transmit control registers for serial ports 0 and 1 RDIV o Receive clock divisor registers for serial ports 0 and 1 SDRDIV SDRAM refresh counter register E 38 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers SROTLig Receive control registers for serial ports 0 and 1 STCTL9 Transmit control registers for serial ports 0 and 1 SYSCON System control register SYSTAT System status register TCOUNT 9 Counter register for timers 0 and 1 T IV iG Transmit clock divisor registers for serial ports 0 and 1 TPERIOD 9 Timer count period registers for timers 0 and 1
60. CPTOB 0x0053 DA DMA chn 5 chain pointe GPTOB 0x0054 N DA DMA chn 5 general purpose Reserved 0x0055 0x0057 IIT1B 0x0058 DA DMA c 7 index SPORT1 xmit B IMT1B 0x0059 DA DMA c 7 modify CT1B Ox005A DA DMA c 7 count CPT1B 0x005B DA DMA c 7 chain ointe GPT1B Ox005C DA DMA chn 7 general purpose Reserved 0x005D 0x005F IIROA 0x0060 NI DA DMA chn 0 index SPORTO rcv A Groups DA DMA Address register DB DMA Buffer SC System Control SP Serial Port NI Not Initialized E 48 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers Table E 15 IOP register addresses reset values and groups Cont d Register Address Reset Group Description Value IMROA 0x0061 DA DMA chn 0 modify CROA 0x0062 DA DMA c 0 count CPROA 0x0063 DA DMA c 0 chain pointe GPROA 0x0064 DA DMA c 0 general purpose Reserved 0x0065 0x0067 IIRIA 0x0068 DA DMA c 2 index SPORTI rev A IMR1A 0x0069 DA DMA c 2 modify CRIA 0x006A DA DMA c 2 count CPRIA 0x006B DA DMA c 2 chain pointe GPRIA 0x006C DA DMA c 2 general purpose Reserved 0x006D 0x006F TITOA 0x0070 NI DA DMA chn 4 index SPORTO xmit A IMTOA 0x0071 NI DA DMA chn 4 modify Groups DA DMA Address register DB DMA Buffer SC System Control SP Serial Port NI Not Initialized ADSP 21065L SHARC DSP Technical Refer
61. Control and Status Registers Table E 27 lists and describes the individual bits of the WAIT register Table E 27 WAIT register Bit Name Description 0 1 EBOWM External bank 0 wait state mode 00 external acknowledge only ACK 0l internal wait states only 10 both internal and external acknowledge required 11 either internal or external acknowledge required 24 EBOWS External bank 0 number of wait states 000 0 wait states no bus idle cyclel no hold time cycle 001 1 wait state a bus idle cycle no hold time cycle 010 2 wait states a bus idle cycle no hold time cycle 011 3 wait states a bus idle cycle no hold time cycle 100 4 wait states no bus idle cycle a hold time cycle 101 5 wait states no bus idle cycle a hold time cycle 110 6 wait states no bus idle cycle a hold time cycle 111 0 wait states a bus idle cycle no hold time cycle 5 6 EB1WM External bank 1 wait state mode For parameter values see EBOWM parameter on page E 113 ADSP 21065L SHARC DSP Technical Reference E 113 IOP Registers Table E 27 WAIT register Contd Bit Name Description 7 9 EB1WS External bank 1 number of wait states For parameter values see EBOWS parameter on page E 113 10 11 EB2WM External bank 2 wait state mode For parameter values see EBOWM parameter on page E 113 12 14
62. Core priority access CPA 7 11 described 7 10 DMA transfers and 7 17 HBG 7 10 ADSP 21065L SHARC DSP User s Manual I 79 INDEX HBR 7 10 IDx 7 10 pin definitions 7 10 protocol 7 12 SDRAM and 7 17 timing diagram 7 13 Multiprocessor memory space 7 4 access address fields 5 25 access timing 5 67 5 68 address boundaries 5 19 address range of IDx processor 5 24 automatic wait state option 5 62 core accesses of internal memory space through 5 25 defined 5 5 7 5 described 5 24 diagram of 5 24 host interface and 8 6 invalid addresses 5 25 map of 5 24 multiprocessing data transfers 7 25 single wait state MMSWS 5 57 wait states and acknowledge 5 61 Multiprocessor system 7 1 BRx pins 7 3 bus arbitration see Multiprocessor bus arbitration data transfers see Multiprocessing data transfers defined 7 5 determining the current bus master 7 11 diagram of 7 2 IDx pin connections 7 3 pin connections between two processors 7 3 processor self configuration 7 11 Multiprocessor vector interrupts 3 52 described 3 52 minimum latency 3 52 VIPD bit 3 52 VIRPT 3 52 MUS multiplier underflow bit 2 34 described 2 36 MV multiplier overflow bit 2 34 described 2 35 MR register values and 2 35 MV condition 3 13 MVS multiplier floating point overflow bit 2 34 N NC pin definition 12 20 NCH number of channel slots bit 9 22 defined 9 32 described 9 71 NE condition 3 14 Nested interrupt
63. EPBx packing modes 8 19 host EPBx transfers 8 24 packing individual data words INDEX 8 19 High frequency design issues 12 42 clock distribution 12 43 clock specifications and jitter 12 42 clock with two frequency inputs diagram of 12 42 controlled impedance transmission line 12 43 crosstalk reducing 12 45 decoupling capacitors and ground planes see Decoupling capacitors and ground planes end of line termination see End of line termination oscilloscope probes see Oscilloscope probes point to point connections on serial ports see Point to point connections on serial ports propagation delay 12 43 reflections reducing 12 46 signal integrity see Signal integrity source termination see Source termination HMSWFE host packing order bit 6 54 8 27 and 48 bit DMA words 6 53 Host asynchronous accesses broadcast writes see Broadcast writes buses used for 8 16 CS 8 11 host interface buffers 8 12 ADSP 21065L SHARC DSP User s Manual I 45 INDEX in multiprocessor systems 8 14 initiating 8 16 maximum throughput reads 8 15 rate of 8 15 read cycle sequence 8 15 read write example timing diagram of 8 13 REDY see REDY timing 8 11 treoyHc switching characteristic and transfer timing 8 12 write cycle sequence 8 14 Host boot mode boot sequence and kernel loading 12 51 12 54 booting sequence 12 58 described 12 56 DMACO register 12 49 12 57 external memory space address of first instruction 12 49
64. Floating point underflow excep tion 27 0x6C FLTI FLoating point invalid exception 28 0x70 SFTO User software interrupt 0 29 0x74 SFT1 User software interrupt 1 30 0x78 SFT2 User software interrupt 2 31 0x7C SFT3 User software interrupt 3 ADSP 21065L SHARC DSP Technical Reference E 15 System Registers MODE Register The MODE register provides control of ALU and Multiplier fixed and floating point operations interrupt nesting and DAG x operation For details on using the MODE register in ADSP 21065L SHARC DSP User s Manual see e Chapter 2 Computation Units e Chapter 3 Program Sequencing e Chapter 4 Data Addressing e Chapter 5 Memory In this manual see Appendix A Instruction Set Reference After reset the MODE register is initialized to 0x0000 0000 as shown in Figure E 3 E 16 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CSEL Condition Code Select 00 bus master condition RND32 0 round float pt data to 40 bits 1 round float pt data to 32 bits TRUNC Float Pt Rounding O round to nearest 1 truncate SSE Shrt Wrd Sign Extend O disable 1 enable ALUSAT ALU Saturation O disable 1 enable IRPTEN Interrupt Enable O disable 1 enable NESTM _ Interrupt Nesting O disable 1 enable SRRFL R7 RO Enable 0 R7 0 primary 1 R7 0 alternate SRRFH R15 R8 Enable 0
65. HBR 12 58 pin configuration 12 51 see also Host booting Host booting 12 56 BMS 12 56 boot sequence 12 58 BSEL 12 56 DATA 60 12 58 DMA controller operation 12 58 DMA data packing 12 57 DMA done interrupt 12 58 DMACO initialization after reset interrupt vector table locating 12 61 multiprocessing 12 59 pin configuration 12 56 reset boot sequence 12 56 RTI instruction 12 58 slave processor mode 12 56 writing directly to EPBO 12 58 writing to the IOP registers 12 58 Host bus acknowledge see REDY Host bus acquisition 8 8 accessing the processor 8 8 BRx 8 8 example timing diagram of 8 10 HBG 8 8 HBR 8 8 host signal buffers 8 9 HTC 8 8 restrictions 8 10 SBTS 8 11 Host bus grant see HBG Host bus mastership avoiding temporary loss of 8 10 HBG 8 8 HBR 8 8 8 10 REDY 8 8 relinquishing the bus 8 11 Host bus request see HBR Host control of processor asynchronous transfers 8 9 and SDRAM 8 9 CS 8 9 12 56 host driven signals 8 9 HBR 12 58 relinquishing the bus 8 11 1 46 ADSP 21065L SHARC DSP User s Manual Host data packing 8 24 16 to 48 bit packing 8 35 32 to 48 bit packing 8 34 32 bit data 8 31 32 bit data reads 8 31 32 bit data writes 8 33 48 bit instructions 8 34 8 to 48 bit packing 8 35 changing the value of HBW 8 26 diagram of 8 32 for all IOP register accesses except the EPBx buffers 8 24 for EPBx accesses 8 24 for non EPBx IOP registers 8 24 HBW 8 24 individual
66. In this manual see Appendix A Instruction Set Reference The DMASTAT register is memory mapped in internal memory at address 0x0037 For a particular channel the DMA controller sets the channel active status bit when DMA is enabled and the current DMA sequence has not fin ished It sets the chaining status bit if the channel is currently performing chaining operations or if a chaining operation is pending A single cycle of latency occurs between the time changes in internal status occur and the time the DMA controller updates the DMASTAT register Status does not change on the master ADSP 21065L during an external port DMA operation until the external portion has finished until the EPBx buffers are empty In chain insertion mode DEN 0 CHEN 1 a channel s chaining status will never be 1 Make sure to test channel status for readiness so your program can rewrite the channels s chain pointer CPx register E 64 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers The processor does not initialize the DMASTAT register at reset as shown in Figure E 7 31 30 29 28 27 26 2 24 23 22 21 20 19 18 17 16 DMA Channel Status Ch7 Tx1_B Ch8 EPBO 0 inactive Chain Status Chain Status 1 active DMA Chaining Stat eaaa Ch5 Tx0_B Ch9 EPB1 1 enabled Chain Status Chain Status 15 14 13 12 11 10 9 8 7 6 54 3 2 1 0 Ch3 Rx1_B ChO Rx0_A Status Chain Status Ch2 Rx1_A Sta
67. LADDR register described 3 33 loop address stack pointer and 3 33 value when loop address stack empty 3 33 LAFS late TFS RFS bit 9 16 9 22 defined 9 29 described 9 56 late frame sync mode 9 56 Late frame sync mode 9 56 described 9 56 Latencies and throughput summary of 12 65 system registers effect and read latencies E 4 Latency between DMA request and DMA grant signals handling 6 65 LCE condition 3 12 3 14 CURLCNTR current loop count and 3 12 DO UNTIL instruction 3 12 IF NOT LCE instruction and 3 13 LCNTR 3 25 3 34 CURLCNTR and 3 35 described 3 35 last loop iteration 3 35 loop counter stack and 3 35 nested loops setting up count value for 3 35 reads of 3 37 LE condition 3 13 Least significant word LSW format 5 29 Loading routine see Booting Local bus host interface and 8 6 Loop abort LA modifier 3 34 Loop address stack 3 7 described 3 32 DO UNTIL instruction and 3 33 empty state 3 33 layout 3 32 loop abort LA modifier and 3 34 overflow 3 33 PUSH LOOP instruction and 3 33 pushing and popping 3 7 stack pointer and the LADDR register 3 33 STKY register and 3 33 Loop counter stack 3 34 LCNTR value and 3 35 pushing for nested loops diagram of 3 36 see LCNTR Loop counters and stack 3 34 current loop counter see CURLCNTR loop counter stack 3 34 loop counter see LCNTR Loop instructions 3 1 counter based loops 3 28 DO FOREVER 3 12 DO UNTIL 3 11 see DO UNTIL instruction 3 25 instruction pipeline
68. Master Slave mode a P 0 TX is slave pacl 1 TX is master Figure E 16 STCTL x register bits I S mode E 92 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers 31 30 29 28 27 26 25 24 23 22 21 20 1918 17 16 LTFS TXS_A Active State TFS Status O active high TX A Data Buffer 1 active low 00 empty 10 partially full SDEN_A 11 full SPORT xmit DMA enable A TUVE A O disable Status sticky 1 enable TX A Underflow SCHEN_A CHNL SPORT xmit DMA Currently Selected Chn chaining enable A O disable MFD 1 enable Multichn Frame Delay Status is read only 15 14 1312 1110 9 8 7 6 54 3 2 1 0 DTYPE TFS Data Data Type Dependency x0 r justify fill MSB w Os 0 depend x1 r justify sign ext MSB 1 independ Ox compand u law CKRE 1x compand A law Active Clock Edge SENDN O falling edge Endian word format 1 rising edge O MSB first 1 LSB first OPMODE PACK SLEN Operation Mode 16 32 bit pack Serial Word Length 1 O non I2S mode O no pack 1 I2S mode iapeck Figure E 17 STCTLx register bits multichannel mode ADSP 21065L SHARC DSP Technical Reference E 93 IOP Registers Table E 24 lists and describes the individual bits of the STCTL x register Table E 24 STCTLx bits Bit Standard 12S Multichn Description 0 SPEN_A SPEN_A Reserved SPORT enable A 0 disable 1 enable 1 2 DTYPE 9 Reserved DTYPEy 9 D
69. Mode 0 DSP SPORT mode 1 Multichn Mode LRFS Active State RFS O active high SDEN_A 1 active low SPORT rcv DMA enable A O disable 1 enable SCHEN_A SPORT rcv DMA chaining enable A O disable 1 enable MCE IMAT Rev Compare Data O accept if false 1 accept if true 6 54 3 2 1 0 DTYPE Data Type x0 r justify fill MSB w Os x1 r justify sign ext MSB Ox compand p law 1x compand A law SENDN 16 32 bit pack O no pack 1 pack ICLK Rev Clk Source O external 1 internal Endian word format O MSB first OPMODE SLEN 1 LSB first Serial Word Length 1 Operation Mode O non I2S mode 1 I2S mode Figure E 14 SRCTLx register bits multichannel mode E 84 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers Table E 23 lists and describes the individual bits in the SRCTL x register Table E 23 SRCTLx bits Bit Standard 12S Multichn Description 0 SPEN_A SPEN_A Reserved SPORT enable A 0 disable 1 enable 1 2 DTYPE 9 Reserved DTYPEy 9 Data type 00 right justify fill MSBs w 0s Ol right justify Sign extend MSBs 10 compand with p law 11 compand with A law 3 SENDN Reserved SENDN Endian word format 0 MSB first 1 LSB first 4 8 SLEN4 g SLEN4 9 SLEN 4 9 Serial word length 1 9 PACK PACK PACK 16 to 32 bit word packing 0 disable packing l enable packing ADSP 21065L SHARC DSP Technical Referenc
70. NORM MAxX round to zero Denormal returns Zero Denormal inputs are flushed to Zero A NAN input returns an all 1s result Status Flags Flag Description AZ Set if the result is a denormal unbiased exponent lt 126 or zero otherwise cleared AU Set if the postrounded result is a denormal other wise cleared AN Set if the floating point result is negative other wise cleared AV Set if the result overflows unbiased exponent gt 127 otherwise cleared AC Cleared AS Cleared Al Set if the input is a NAN an otherwise cleared B 36 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference Rn MANT Fx Function Extracts the mantissa fraction bits with explicit hidden bit excluding the sign bit from the floating point operand in Fx The unsigned magnitude result is left justified 1 31 format in the fixed point field in Rn Round ing modes are ignored and no rounding is performed because all results are inherently exact Denormal inputs are flushed to Zero A NAN or an Infinity input returns an all 1s result 1 in signed fixed point format Status Flags Flag Description AZ Set if the result is zero otherwise cleared AU Cleared AN Cleared AV Cleared AC Cleared AS Set if the input is negative otherwise cleared Al Set if the input operands is a NAN or an Infinity otherwise cleared ADSP 21065L SHARC DSP Technical Reference B
71. R11 8 R15 12 Compute Field EEEE EEEE EP EEE PEER Syntax Floating point versions Fm F3 0 F7 4 Fa F11 8 F15 12 Fs F11 8 F15 12 Compute Field Pa PPE Per E EEE PEELE 1 11 FS FM FA FXM FYM FXA FYA The Multiplier x and y operands are received from data registers RXM FXM and RYM FYM The Multiplier result operand is returned to data register RM FM The ALU x and y operands are received from data regis ters RXA FXA and RYA FYA The ALU result operands are returned to data register RA FA and RS FS B 104 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference The result operands can be returned to any registers within the Register File Each of the four input operands is restricted to a different set of four data registers as shown in Table B 11 Table B 11 Valid sources of the input operands Input Valid Sources Multiplier X R3 RO F3 FO Multiplier Y R7 R4 7 4 ALU X R11 R8 F11 F8 ALU Y R15 R12 F15 F12 ADSP 21065L SHARC DSP Technical Reference B 105 Multifunction Computations B 106 ADSP 21065L SHARC DSP Technical Reference C NUMERIC FORMATS The processor supports several numeric formats e JEEE Standard 754 854 32 bit single precision floating point format e An extended precision version of the 32 bit single precision floating point format that has eight additional bits in the mantissa 40 bits to
72. Rn MR2F MROB Rn Rn MROB MRIB Rn Rn MR1B MR2B Rn Rn MR2B Compute Field 1 00000 T AI RK The MR register is specified by Ai and the data register by Rk The direction of the transfer is determined by T O to Register File 1 to MR register Ai MR Register 0000 ROF 0001 RIF 0010 R2F 0100 ROB B 60 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference Ai MR Register 0101 MR1B 0110 MR2B Status Flags Flag Description N Cleared V Cleared U Cleared I Cleared ADSP 21065L SHARC DSP Technical Reference B 61 Multiplier Operations Fn Fx Fy Function Multiplies the floating point operands in registers Fx and FY The result is placed in the register Fn Status Flags Flag Description N Set if the result is negative otherwise cleared V Set if the unbiased exponent of the result is greater than 127 otherwise cleared U Set if the unbiased exponent of the result is less than 126 otherwise cleared I Set if either input is a NAN or if the inputs are Infinity and Zero otherwise cleared Reminder The individual registers file are prefixed with an F when used in floating point computations The registers are prefixed with an R when used in fixed point computations The following instructions for example use the same registers FO Fl F2
73. Ry or by the immediate len6 field in the instruction The field is extracted from the fixed point field of Rx starting from a bit position determined by the bit field in register Ry or by the immediate bit field in the instruction The MSBs of Rn are sign extended by the MSB of the extracted field unless the MSB is extracted from off scale left The floating point extension field of Rn bits 7 0 of the 40 bit word is set to all 0s Bit6 and len6 can take values between 0 and 63 inclusive allowing for extraction of fields ranging in length from 0 to 32 bits and from bit posi tions ranging from 0 to off scale left Example 39 31 23 5 7 0 Jone Se abc defghijk 1mn eins Hee Rx len6 bits bit position bit6 from reference point 39 31 23 5 7 0 aaaaaaaa aaaaaaaa aaabcdef ghijkilmn 00000000 Rn Nei e raisin ein taint Sitar sign extension B 84 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference Status Flags Flag Description SZ Set if the output operand is 0 otherwise cleared SV Set if any bits are extracted from the left of the 32 bit fixed point input field i e if len6 bit6 gt 32 otherwise cleared SS Cleared ADSP 21065L SHARC DSP Technical Reference B 85 Shifter Operations Rn EXP Rx Function Extracts the exponent of the fixed point operand in Rx The exponent is placed in the shf field in register Rn The exponent is calculated as t
74. SHARC DSP User s Manual Flag outputs see FLAGx 12 33 FLAGx 12 28 input synchronization delay 12 27 internal clock and phase lock 12 27 internal clock generation 12 26 JTAG interface pins see JTAG emulator signal recognition phase 12 27 single bit signaling 12 28 synchronization delay 12 27 XTAL and CLKIN 12 26 Pin states after reset 12 22 ACK 12 22 ADDRx 12 22 BMS 12 23 BMSTR 12 22 BRx 12 22 BSEL 12 23 bus master driven pins 12 22 CAS 12 22 CLKIN 12 23 CPA 12 23 CS 12 23 DATAx 12 23 DMAGx 12 22 DMAR x 12 23 DQM 12 22 DRx_X 12 24 DTx_X 12 24 EMU 12 25 FLAGx 12 24 HBG 12 22 INDEX HBR 12 24 IDx 12 24 IRQx 12 24 JTAG emulator 12 25 MSx 12 22 PWM_EVENTx 12 24 RAS 12 23 RCLKx 12 24 RD 12 23 REDY 12 24 RESET 12 24 RFSx 12 24 SBTS 12 24 SDA10 12 23 SDCKE 12 23 SDCLKx 12 23 SDWE 12 23 serial port pins 12 24 SW 12 23 TCK 12 25 TCLKx 12 24 TDI 12 25 TDO 12 25 TFSx 12 24 TMS 12 25 TRST 12 25 WR 12 23 XTAL 12 24 Pipelining 3 19 described 3 4 execution cycles 3 5 system register writes and 3 8 Placing all SDRAM signals in a high impedance state 10 9 ADSP 21065L SHARC DSP User s Manual I 85 INDEX Placing the SDCLK1 signal only in a high impedance state 10 9 PM bus address bits diagram of 5 8 and EPBx buffers 8 18 connection to memory 5 7 core memory accesses 5 10 data storage 5 8 data transfer destinations 5 11 data transfer t
75. The addresses in the vector table represent offsets from a base address For an interrupt vector table in internal memory the base address is 0x0000 8000 the beginning of Block 0 For an interrupt vector table in external memory the base address is 0x0002 0000 Table F 1 IRPTL IMASK interrupt vectors and priorities Bit Address Name Description Priority 0 0x00 Reserved 1 0x04 RSTI Reset read only non Highest maskable 2 0x08 Reserved 3 Ox0C SOVF Status stack or loop stack overflow or PC full 4 0x10 TMZH Timer high priority option 5 0x14 VIRPTI Vector interrupt 6 0x18 IRQ2 IRQ2 asserted 7 0x1C IRQ1 IRQI asserted ADSP 21065L SHARC DSP Technical Reference F 1 Table F 1 IRPTL IMASK interrupt vectors and priorities Contd Bit Address Name Description Priority 8 0x20 IRQOI TROO asserted 9 0x24 Reserved 0 0x28 SPRO DMA channel 0 1 SPORTO eceive A amp B 1 Ox2C SPR1 DMA channel 2 3 SPORTI eceive A amp B 2 0x30 SPTO DMA channel 4 5 SPORTO transmit A amp B 3 0x34 SPT1 DMA channel 6 7 SPORT1 transmit A amp B l4 0x38 Reserved US Ox3C Reserved 6 0x40 EPOI DMA channel 8 Ext port buffer 0 7 0x44 EP1I DMA channel 9 Ext port buffer 1 18 0x48 Reserved 19 0x4C Reserved 20 0x50 Reserved 21 0x54 CB7I Circular buffer 7 ove
76. a denormal unbiased exponent lt 126 or zero otherwise cleared AU Set if the postrounded result is a denormal other wise cleared AN Set if the floating point result is negative other wise cleared AV Set if the postrounded result overflows unbiased exponent gt 127 otherwise cleared AC Cleared AS Cleared Al Set if either of the input operands is a NAN or if they are opposite signed Infinities otherwise cleared B 30 ADSP 21065L SHARC DSP Technical Reference Compute Operation Reference COMP Fx Fy Function Compares the floating point operand in register Fx with the floating point operand in register Fy Sets the AZ flag if the two operands are equal and the AN flag if the operand in register Fx is smaller than the operand in reg ister Fy The ASTAT register stores the results of the previous eight ALU compare operations in bits 24 31 These bits are shifted right bit 24 is overwritten whenever a fixed point or floating point compare instruction is executed The MSB of ASTAT is set if the X operand is greater than the Y operand its value is the AND of AZ and AN otherwise it is cleared Status Flags Flag Description AZ Set if the operands in registers Fx and Fy are equal otherwise cleared AU Cleared AN Set if the operand in the Fx register is smaller than the operand in the Fy register otherwise cleared AV Cleared AC Cleared AS Cleared Al Set if either of
77. a mask The set operation sets all the bits in the specified sys tem register that are also set in the specified data value The clear operation clears all the bits that are set in the data value The toggle oper ation toggles all the bits that are set in the data value The test operation sets the bit test flag BTF in ASTAT if all the bits that are set in the data value are also set in the system register The XOR operation sets the bit test flag BTF in ASTAT if the system register value is the same as the data value For more information on Shifter operations see Appendix B Compute Operation Reference For more information on system registers see Appendix E Control and Status Registers Examples BIT SET MODE2 0x00000070 BIT TST ASTAT 0x00002000 ADSP 21065L SHARC DSP Technical Reference A 71 Group IV Instructions Miscellaneous Type 18 Opcode 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 10100 BOP SREG DATA 31 30 29 28 27 26 25 24 upper 8 bits DATA lower 24 bits Bits Description BOP Selects one of the five bit operations SREG Specifies the system register DATA Specifies the data value A 72 ADSP 21065L SHARC DSP Technical Reference Instruction Set Reference Register Modify bit reverse Type 19 Immediate I register modify with or without bit reverse Syntax MODIFY Ia lt data32 gt Ic lt data24 gt BITREV Ia
78. address or premodified I register value or optional compute operation in parallel with a transfer between data memory and the Register File In this instruction the IF condition and ELSE keyword are not optional and must be used If the specified condition is true the jump is executed If the specified condition is false the compute operation and data memory transfer are performed in parallel Only the compute operation is optional in this instruction The PC relative address for the jump is a 6 bit twos complement value If an I register is specified Ic it is modified by the specified M register Md to generate the branch address The I register is not affected by the modify operation Note that the delay branch DB loop abort LA and clear interrupt CI modifiers are not available for this jump instruction For the data memory access the I register Ia provides the address The I register value is postmodified by the specified M register and is updated with the modified value Premodify addressing is not available for this data memory access A 52 ADSP 21065L SHARC DSP Technical Reference Instruction Set Reference For more information on indirect branches see Chapter 4 Data Address ing in ADSP 21065L SHARC DSP User s Manual Examples IF TF JUMP M8 18 ELSE R6 DM I6 M1 IF NE JUMP PC 0x20 ELSE F12 FLOAT R10 BY R3 R6 DM 15 MOQ Type 10 Opcode with indirect jump
79. between the time the SDRAM detects the read command and the time the data is available at its outputs 00 no SDRA 01 1 cycle 10 2 cycles 11 3 cycles 18 20 SDTRAS SDRAM ta Spec in number of clock cycles 21 23 SDTRP SDRAM ty spec in number of clock cycles 24 SDPM SDRAM power up option Specifies the sequence of commands in the SDRAM power up cycle 0 precharge 8 CBR mode register set l precharge mode register set 8 CBR E 72 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers Table E 19 IOCTL register Cont d Bit Name Description 25 27 SDBS SDRAM bank select Specifies which of the ADSP 21065L s exter al memory bank connects to SDRAM 000 no SDRAM 100 bank 0 101 bank 1 110 bank 2 111 bank 3 other reserved For proper operation of the SDRAM control ler in the WAIT register set the EBxWS bits to 0 and the EBxWM bits appropriately for the external memory bank to which the SDRAM connects See Table E on page E 113 28 SDBUF SDRAM buffer Enables disables pipelining of address and control signals when using external buffer ing between the ADSP 21065L and SDRAM Sup ports multiple SDRAMs connected in parallel 0 disable 1 enable ADSP 21065L SHARC DSP Technical Reference E 73 IOP Registers Table E 19 IOCTL register Cont d Bit Name Description 29 30 SDBN SDRAM number of ban
80. buffers channels 8 and 9 only The DMARX signal paces DMA trans fers The DMA controller gener ates a DMA request when DMARx is asserted DMARx requests function the same way as in handshake mode and the DMA controller transfers the data when RD or WR is asserted The address is driven as in nor mal master mode ORing the RD DMAGx and WR DMAGx pairs requires no external gates enabling buffer access with zero wait state and no idle states Wait states and Acknowledge ACK apply to paced master mode trans fers For details see Chapter 5 Memory in ADSP 21065L SHARC DSP User s Manual il il 1 Reserved If TRAN 1 for an external read of the EPBx buffer the DMA controller fills the buffer as soon as the DEN bit is set to 1 You cannot use DMA paced master mode or external handshake mode with SDRAM transfers 3 When an external DMA channel is configured for output TRAN 1 the EPBx buffer starts to fill as soon as the channel becomes enabled whether or not DMAR x assertions or DMA slave mode DMA buffer reads have been made ADSP 21065L SHARC DSP Technical Reference E 63 IOP Registers DMASTAT DMA Channel Status Register The DMASTAT register maintains status bits for each DMA channel For details on using the DMASTAT register in ADSP 21065L SHARC DSP Users Manual see e Chapter 6 DMA e Chapter 7 Multiprocessing e Chapter 8 Host Interface e Chapter 9 Serial Ports
81. effect latency 9 70 ADSP 21065L SHARC DSP User s Manual I 65 INDEX I S SPORT mode enabling 9 62 OPMODE and 9 70 standard SPORT mode enabling 9 59 Memory 32 and 40 bit data configuration for 5 40 32 and 48 bit words using 5 30 access restrictions 5 27 access timing of multiprocessor memory space 5 67 ACK 5 47 address boundaries 5 19 address decoding table 5 20 ADDR x pin 5 44 architecture diagram of 5 2 bandwidth 5 1 boot modes 5 53 bus idle cycle see Bus idle cycle bus master accesses of external memory space 5 66 5 67 cache miss 5 10 core accesses internal memory space through multiprocessor memory space 5 25 over the PM bus 5 10 DAG operation see DAG operation data transfers 5 7 48 bit accesses of program memory 5 14 address sources 5 11 between memory and registers 5 12 between universal registers 5 12 example code for 48 bit pro gram memory access 5 14 over DM bus 5 11 over PM bus 5 11 PX register transfers diagram of 5 13 single cycle number of 5 17 with the Register File 5 11 DATAx 5 45 DM bus see DM bus dual data accesses see Dual data accesses EPROM boot mode 5 53 see EPROM boot mode executing program from external memory space 5 49 extending off chip memory accesses 5 53 external memory address space 5 44 external memory banks and SDRAM see SDRAM interface external memory banks see External memory banks external memory space access address fields 5 26 external memory sp
82. external memory space 5 52 direct 5 11 immediate 5 11 indirect 5 11 ADDRx and host accesses 8 11 EPROM booting and 12 54 external memory space interface and 5 44 generating addresses outside the address range of external memory space 6 30 parallel SDRAM refresh command 10 28 pin definition 12 4 state after reset 12 22 ADI product information sources of xix xiii ADI product literature xxiv xviii ADREDY bit active drive REDY switching between open and active drain output 8 12 ADSP 21065L block diagram 6 2 AF ALU floating point operation bit 2 16 described 2 19 Al ALU floating point invalid operation bit 2 16 described 2 19 setting 2 19 AIS ALU floating point invalid operation bit 2 17 described 2 19 setting 2 19 Alternate DAG registers 4 3 architecture 4 4 context switching and 4 3 described 4 3 diagram of 4 4 MODE control bits for 4 5 SRD1H DAG alternate register select 7 4 4 5 SRD1L DAGI alternate register select 3 0 4 5 SRD2H DAG alternate register select 15 12 4 5 SRD2L DAG alternate register select 11 8 4 5 Alternate register file registers 2 11 context switching 2 11 control bits 2 11 described 2 11 effect latency of activation 2 11 selecting the active sets 2 11 SRRFH 2 11 SRRFL 2 11 ALU data formats 2 12 described 2 1 instruction set summary 2 21 instruction types 2 12 operating modes 2 14 I 2 ADSP 21065L SHARC DSP User s Manual see ALU operating modes status flags 2
83. format the Multiplier sets the result to the maxi mum value Otherwise the MR value is unaffected The result is placed either in the fixed point field in register Rn or one of the MR accumulation registers which must be the same MR register that provided the input If Rn is specified only the portion of the result that has the same format as the inputs is transferred bits 31 0 for integers bits 63 32 for fractional The floating point extension field in Rn is set to all 0s If MRF or MRB is specified the entire 80 bit result is placed in MRF or MRB Status Flags Flag Description MN Set if the result is negative otherwise cleared MV Cleared MU Set if the upper 48 bits of a fractional result are all zeros signed or unsigned result or ones signed result and the lower 32 bits are not all zeros Inte ger results do not underflow MI Cleared ADSP 21065L SHARC DSP Technical Reference B 57 Multiplier Operations Rn Rn MRB RND MRF mod RND MRB mod MRF RND MRF mod RND MRB mod Function Rounds the specified MR value to nearest at bit 32 the MR1 MRO boundary The result is placed either in the fixed point field in register Rn or one of the MR accumulation registers which must be the same MR register that provided the input If Rn is specified only the portion of the result that has the same format as the inputs is transferred bits 31 0 for integers bits 63 32 for fractional The floating poin
84. gt DM PM direct addressing type 14 instruction A 63 ureg lt gt DM PM indirect addressing type 15 instruction A 65 Group IV miscellaneous instructions Cjump Rframe type 24 instruction A 81 IDLE type 22 instruction A 78 configuration 7 31 data source and destination selection 6 63 described 6 55 6 62 DMAGx 6 62 7 31 8 22 DMAR x 6 62 7 31 8 22 enabling 6 63 EXTERN bit 7 31 8 22 external transfers and the ECEPx register 6 63 hardware handshake signals 6 62 host data transfers to internal memory space 8 22 HSHAKE bit 7 31 8 22 MASTER bit 7 31 8 22 multiprocessing DMA accesses of internal memory 7 31 Hardware SPORT reset 9 8 HBG and host signal buffers 8 9 1 44 ADSP 21065L SHARC DSP User s Manual host interface 8 8 multiprocessor bus arbitration 7 10 pin definition 12 8 state after reset 12 22 HBR BCNT register and 7 18 host booting 12 58 host interface 8 8 maintaining host bus mastership 8 10 multiprocessor booting 12 59 multiprocessor bus arbitration 7 10 pin definition 12 9 relinquishing the bus 8 11 resolving system bus access deadlock 8 49 signal glitches avoiding 8 46 state after reset 12 24 HBW host bus width bits 8 22 8 24 8 26 changing the initialization after reset value 8 26 changing the packing mode 12 57 EPBx packing modes 6 16 external port DMA packing mode 6 51 host boot mode 12 57 host data transfers 8 24 host
85. indirect addressing using I registers The I register is premodified with an immediate value specified in the instruction The I register is not updated Data memory address modifiers are 32 bits wide 0 to 232_1 Program memory address modifiers are 24 bits wide 0 to 974 1 The ureg may not be from the same DAG that is DAG1 or DAG2 as Ia Mb or Ic Md For more information on register restrictions see Chapter 4 Data Addressing in ADSP 21065L SHARC DSP User s Manual Examples DM 24 15 TCOUNT USTATI1 PM offs 113 offs is a defined constant ADSP 21065L SHARC DSP Technical Reference A 65 Group Ill Instructions Immediate Move Type 15 Opcode 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 101 G I D UREG DATA upper 8 bits z erp EP EEE EEE DATA lower 24 bits Bits Description D Selects the access type read or write G Selects the memory type data or program UREG Specifies the number of a universal register DATA specifies the immediate modify value for the I register A 66 ADSP 21065L SHARC DSP Technical Reference Instruction Set Reference Immediate data gt gt DM PM Type 16 Immediate data write to data or program memory Syntax DM Ia Mb lt data32 gt PM Ic Md Function A write of 32 bit immediate data to data or program memory with indi rect addressing The data is placed in the most s
86. input sign ABS and MANT operations 5 AI ALU floating point invalid operation 6 N ultiplier result negative 7 V ultiplier overflow 8 U ultiplier floating point underflow 9 I ultiplier floating point invalid operation 10 AF ALU floating point operation 11 SV Shifter overflow 12 SZ Shifter result zero 13 SS Shifter input sign 14 17 Reserved 18 BTF Bit test flag for system registers 19 FLGO FLAGO value 20 FLG1 FLAGI value E 10 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers Table E 4 ASTAT register Cont d Bit Name Description 21 FLG2 FLAG2 value 22 FLG3 FLAG3 value 23 Reserved 24 31 CACC Compare accumulation shift register ADSP 21065L SHARC DSP Technical Reference E 11 System Registers IMASK and IRPTL Interrupt Mask and Latch Registers The IMASK and IRPTL registers have identical bit positions 0 through 31 that correspond to the ADSP 21065L interrupts in order of priority from highest to lowest For details on using the IMASK and IRPTL registers in ADSP 21065L SHARC DSP User s Manual see e Chapter 2 Computation Units e Chapter 3 Program Sequencing e Chapter 4 Data Addressing e Chapter 5 Memory e Chapter 6 DMA e Chapter 7 Multiprocessing e Chapter 8 Host Interface In this manual see Appendix A Instruction Set Reference After reset the IRPTL register is initialized to 0x0000 0000 and the IMASK register is initialized to 0x0000 000
87. interrupt vector table no boot mode BSEL 0 BMS 0 Specifies the location of the interrupt vec tor table when processor configured for no boot mode 0 in external memory at 0x0002 0000 1 in internal memory at 0x0000 8000 After reset initialized to zero placing the interrupt vector table in external memory for no boot mode When the processor is configured for one of the boot modes the internal interrupt vector table always resides in internal memory regardless of the value of this bit 3 Reserved ADSP 21065L SHARC DSP Technical Reference E 101 IOP Registers Table E 25 SYSCON register Contd Bit Name Description 4 5 HBW Host bus width Specifies the external word width of the host bus for host accesses to the processor s EPBx IOP registers 00 32 bit host bus 01 16 bit host bus 10 8 bit host bus 11 reserved Host accesses to all other IOP registers are always 32 bits regardless of the value of this bit 6 HMSWF Host packing order Specifies the packing order for host accesses 0 LSW first 1 MSW first This bit ignored for 32 to 48 bit packing 7 HPFLSH Host packing status flush Resets the host packing status flush packing status This bit always reads as 0 Host must not access the IOP registers while the core writes this bit E 102 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers
88. memory access 5 14 multiprocessing see Multiprocessing data transfers multiprocessing DMA 7 30 multiprocessing IOP register reads see OP register reads of 40 bit DM data bus 5 14 over DM bus 5 11 over PM bus 5 11 over the external bus 5 43 packed data 5 43 PM bus destinations 5 11 PX register data alignment 5 12 PX register transfers diagram of ADSP 21065L SHARC DSP User s Manual I 19 INDEX 5 13 single cycle number of 5 17 universal register to register 5 12 with memory 5 7 Data transmit DTx_X pins 9 4 DATAx and host accesses 8 30 EPROM boot mode and 12 51 EPROM boot sequence after reset 12 54 external memory space interface and 5 45 external port data alignment diagram of 8 31 host booting and 12 58 pin definition 12 4 state after reset 12 23 DB modifier 3 18 Decode address register 3 6 Decode cycle 3 4 Decoded memory address lines MSx 5 49 Decoding table for memory addresses 5 20 Decoupling capacitors and ground planes 12 46 power plane 12 46 VDD pins 12 46 def21065L h file 9 12 complete listing E 116 Delayed branches 3 18 call return address 3 19 DB modifier and 3 18 defined 3 19 instructions following restriction 3 20 interrupt processing and 3 23 pipelined stages of jumps calls 3 19 pipelined stages of returns 3 20 reading PC stack PC stack pointer and 3 24 DEN DMA enable bit 6 9 6 14 8 28 described 6 15 enabling disabling DMA 8 20 single word EPBx data transfer control
89. mode B 13 Rn Rx Ry fixed point operation ALU status flags B 6 described B 6 saturation mode B 6 Rn Rx Ry Cl fixed point operation ALU status flags B 8 described B 8 saturation mode B 8 Rn Rx 1 fixed point operation ALU status flags B 15 described B 15 Rn Rx Ry fixed point operation ALU status flags B 7 described B 7 saturation mode B 7 Rn Rx Ry Cl fixed point operation ALU status flags B 9 described B 9 saturation mode B 9 Rn SAT MRB mod 1 operation INDEX described B 57 multiplier status flags B 57 Rn SAT MRF mod1 operation described B 57 multiplier status flags B 57 Rn TRUNC Fx BY Ry operation ALU status flags B 40 described B 39 Rn TRUNC Fx operation ALU status flags B 40 described B 39 RND322 floating point rounding boundary bit 2 14 32 bit data in 40 bit systems using 5 41 32 bit IEEE results 2 15 40 bit results 2 15 multiplier floating point operation 2 32 2 33 vs IMDWx 5 41 ROM boot wait mode RBWM 5 56 ROM boot wait state RBWS 5 57 Rotating priority for external port DMA channels 6 37 DCPR bit 6 37 described 6 37 vs fixed priority 6 38 vs SPORT channel priorities 6 38 Rounding modes described 2 7 round toward zero 2 7 Rounding MR register 2 30 ADSP 21065L SHARC DSP User s Manual I 99 INDEX Round toward zero rounding mode 2 7 ROVE receive overflow status bit 9 22 9 38 defined 9 33 described 9 38 RTFS active state RFS bit described 9 55 RTI instruction 8
90. nearest TDO An x specifies a don t care state None of the public instructions place data registers into test modes The instruc tions affect the ADSP 21065L as defined in the 1149 1 specification The ADSP 21065L does not support the optional instructions RUNBIST IDCODE or USERCODEL Table D 1 Test instructions Bits Register 4 3 2 1 0 Name Serial Path Type IX X X X BYPASS Bypass Public 0 0 0 0 0 EXTEST Boundary Public 0 0 0 0 1 SAMPLE PRELOAD Boundary Public 0 0 0 1 0 Reserved for emulation NA Private 0 0 0 1 1 INTEST Boundary Public 0 0 1 0 0 Reserved for emulation NA Private 0 0 1 0 1 Reserved for emulation NA Private ADSP 21065L SHARC DSP Technical Reference D 3 Instruction Register Table D 1 Test instructions Bits Register 4 3 2 1 0 Name Serial Path Type 0 0 1 Reserved for emulation NA Private 0 0 1 Reserved for emulation NA Private 0 1 x Reserved for emulation NA Private The entry under Register is the serial scan path either Boundary or Bypass in this case that the instruction enabled Figure D 1 shows these register paths The single bit Bypass register is fully defined in the 1149 1 specification The Boundary register is described in the next section You do not need to write special values into any register prior to selecting any instruction As Table D 1 shows certain instructions are r
91. of 12 21 data lines EPD and EPROM boot sequence after reset 12 53 DATAx 12 4 defined 5 3 DMA data transfers 7 30 DMAGx 12 5 DMAR x 12 5 host interface and 8 2 MSx 12 5 multiprocessing data transfers 7 25 7 27 pin definitions 12 4 SBTS 12 6 SW 12 6 tions summary of 6 52 described 6 50 disabling 6 67 DMA registers 6 12 EPBx buffers 6 50 fixed channel priority 6 38 internal DMA request and grant 6 35 interrupts 6 45 master mode DMA interrupts see DMA interrupts 6 45 modes see DMA modes 6 55 non DMaA single word transfers 6 50 priority of TCB chain loading see External port buffer 0 interrupt 9 6 TCB chain loading External port buffer 1 interrupt 9 6 redefining DMA channel priority External port DMA 6 38 block data transfers 6 7 buffer size 6 50 changing DMA channel priority assignment example of 6 38 channels 6 30 6 50 clearing EPBx buffers 6 50 connection to internal memory space 6 27 control bit definitions 6 14 core read write of EPBx buffers restrictions 6 50 data packing 6 51 LSWF packing format 6 52 MSWF packing format 6 52 packing logic 6 51 PMODE and HBW combina re enabling 6 67 rotating channel priority 6 37 6 38 transfer rate 6 50 External port DMA control registers see DMACX registers External port FIFO buffers see EPBx buffers EZ ICE emulator board level testing 12 38 CLKIN connection 12 40 connection requirements 12 36 described
92. operation described B 67 shifter status flags B 67 Rn BCLR Rx BY data8 operation described B 70 shifter status flags B 70 Rn BCLR Rx BY Ry operation described B 70 shifter status flags B 70 Rn BSET Rx BY data8 operation described B 71 shifter status flags B 71 Rn BSET Rx BY Ry operation described B 71 shifter status flags B 71 Rn BTGL Rx BY data8 operation described B 72 shifter status flags B 72 Rn BTGL Rx BY Ry operation described B 72 shifter status flags B 72 Rn CLIP Rx BY Ry fixed point operation ALU status flags B 25 described B 25 Rn EXP Rx operation described B 86 shifter status flags B 86 Rn EXP Rx EX operation described B 87 shifter status flags B 87 Rn FDEP Rx BY bit6 len6 operation described B 74 example B 75 shifter status flags B 75 Rn FDEP Rx BY bit6 len6 SE operation described B 78 example B 79 shifter status flags B 79 Rn FDEP Rx BY Ry SE operation described B 78 example B 79 shifter status flags B 79 Rn FDEP Rx BY Ry operation described B 74 example B 75 shifter status flags B 75 Rn FEXT Rx BY bit6 len6 SE operation described B 84 I 96 ADSP 21065L SHARC DSP User s Manual example B 84 shifter status flags B 85 Rn FEXT Rx BY bit6 len6 operation described B 82 example B 83 shifter status flags B 83 Rn FEXT Rx BY Ry SE operation described B 84 example B 84 shifter status flags B 85 Rn FIX Fx BY Ry operation ALU status flags B 40 described B 3
93. or compute dreg gt DM type 10 instruction described A 52 example A 53 IF COND A 52 opcode with indirect jump A 53 opcode with PC relative jump A 53 syntax summary A 6 Indirect jump call compute type 9 instruction described A 48 example A 49 opcode with indirect branch ADSP 21065L SHARC DSP User s Manual I 53 INDEX A 50 opcode with PC relative branch A 50 Individual register file registers assembly language prefix identifier 2 10 described 2 10 fixed point computations 2 10 floating point computations 2 10 Input signal conditioning 12 41 input inverter and 12 41 Input synchronization delay 12 27 Inserting a high priority DMA chain in an active DMA chain 6 44 Instruction addresses 3 6 Instruction cache architecture see Instruction cache architecture cache hit 3 58 cache miss 3 58 5 10 defined 5 3 described 3 58 disable and freeze 3 61 see Instruction cache disable and freeze dual data accesses 5 9 efficiency 3 60 see Instruction cache efficiency instruction fetches 5 10 operation 3 58 5 10 operation after reset 3 62 PM bus conflict 5 10 PM data bus accesses 5 10 program memory data accesses 3 10 program sequencing 3 7 size of 3 58 three instruction pipeline and 3 58 Instruction cache architecture addressing entry sets 3 59 cache hit 3 59 cache miss 3 59 described 3 58 diagram of 3 59 entry 3 58 entry sets 3 59 entry valid bit 3 59 instruction address mapping 3 59 3 60 LRU bit 3 59
94. point field in register Rn The floating point extension field in Rn is set to all 0s In saturation mode the ALU saturation mode bit in MODE set positive overflows return the maximum positive number 0x7FFF FFFF and negative overflows return the minimum negative number 0x8000 0000 Status Flags Flag Description AZ Set if the fixed point output is all Os otherwise cleared AU Cleared AN Set if the most significant output bit is 1 otherwise cleared AV Set if the XOR of the carries of the two most signif icant adder stages is 1 otherwise cleared AC Set if the carry from the most significant adder stage is 1 otherwise cleared AS Cleared Al Cleared ADSP 21065L SHARC DSP Technical Reference B 7 Single Function Operations Rn Rx Ry Cl Function Adds with carry AC from ASTAT the fixed point fields in registers Rx and Ry The result is placed in the fixed point field in register Rn The floating point extension field in Rn is set to all 0s In saturation mode the ALU saturation mode bit in MODE set positive overflows return the maximum positive number 0x7FFF FFFF and negative overflows return the minimum negative number 0x8000 0000 Status Flags Flag Description AZ Set if the fixed point output is all Os otherwise cleared AU Cleared AN Set if the most significant output bit is 1 otherwise cleared AV Set if the XOR of the carries of the two most signif ic
95. pulsewidth generation mode PWM_EVNT pin is output 8 INT_HIO Timer 0 interrupt vector location For interrupt stat on page E 26 s values see Table E 8 9 PULSE_HIO 10 PERIOD_CNT1 Timer 0 counter leading edge select pulse width ode only 0 low high to high transition to low transition Timerl period cou ode only t enable pulse counter 0 enable width count capture enable period count capture 11 TIMEN1 Timer 1 enable 0 disable 1 enable E 24 ADSP 21065L SHARC DSP Technical Reference Control and Status Registers Table E 7 MODE2 register Cont d Bit Name Description 12 PWMOUT1 Timer 1 mode control O enable pulse counter mode PWM_EVENT pin is input 1 enable pulsewidth generation mode PWM_EVNT pin is output 13 INT_HI1 Timer 1 interrupt vector location For interrupt status values see Table E 8 on page E 26 14 PULSE_HI1 Timer 1 leading edge select pulse width counter mode only 0 low to high transition 1 high to low transition 15 FLGOO FLAGO status O input 1 output 16 FLG10 FLAG status O input 1 output 17 FLG20 FLAG2 status 0 input 1 output 18 FLG 30 FLAG3 status 0 input 1 output ADSP 21065L SHARC DSP Technical Reference E 25 System Registers Table E 7 MODE2 registe
96. read writes 7 16 host interface 8 7 host writes to 8 16 mode 12 56 Slave write FIFO 7 26 8 15 host EPBx writes 8 18 host read delay 8 17 writes to a full 8 16 SLEN serial word length bits 9 16 9 21 defined 9 35 described 9 48 I S SPORT mode 9 63 Soft processor reset see SRST Software interrupts 3 49 activating 3 49 IRPTL register 3 49 Software SPORT reset 9 8 Source termination 12 43 diagram of 12 44 guidelines for using 12 44 SPEN SPORT enable bit 9 15 9 21 defined 9 35 SPL SPORT loopback mode bit 9 22 defined 9 36 described 9 88 SPORT clock and frame sync frequencies 9 39 CLKIN 9 41 clock divisor value equation for ADSP 21065L SHARC DSP User s Manual 1 109 INDEX calculating 9 42 frame sync divisor value limitation 9 43 maximum clock rate restrictions 9 43 number of serial clock cycles between frame sync pulses equation for calculating 9 42 serial clock frequency equation 9 42 value of frame sync divisor equation for calculating 9 42 SPORT clock signal options 9 50 CKRE 9 50 clock edge 9 50 clock source 9 50 frequency 9 50 ICLK 9 50 internal vs external clocks 9 50 see also SPORT clock source RCLKx 9 50 single clock for input and output use of 9 50 TCLKx 9 50 SPORT clock source 9 50 external 9 51 ICLK 9 50 internal clock 9 50 RCLKx 9 50 serial clock divisor value 9 50 serial clock divisors and external clock source 9 51 TCLKx 9 50 SPORT control registers 9
97. registers are initialized to 0x0000 0000 as shown in fig ures E 12 E 13 and E 14 When changing operating modes make sure you write all zeros 0 to the serial port s control register to clear it before writing the new mode Some bit definitions of the SRCTLx register depend on the mode stan dard IS or multichannel for which the serial port is configured ADSP 21065L SHARC DSP Technical Reference E 81 IOP Registers 31 30 29 28 27 26 25 24 23 22 21 20 1918 17 16 LRFS Active Low RFS RXS_A Status O active high RX A Data Buffer 1 active low 00 empty LAFS 10 partially full 11 lt full Late RFS O early ROVF_A 1 late Status sticky SDEN_A SPORT Rev RX A Overflow RXS_B DMA enable A ROVF B O disable z 1 enable SPEN Te SCHEN_A SPORT Enable B MCE SPORT Rev DMA O disable SPORT Mode chaining enable A 1 enable 0 DSP SPORT mode O disable 1 Multichn mode 1 enable SPL SDEN_B SPORT Loopback O disable SCHEN_B Status is read only 1 enable 15 14 1312 1110 9 8 7 6 54 3 2 1 0 SPEN_A RFS Source 16 32 bit pack SPORT Enable A 0 external O no pack O disable 1 internal 1 pack 1 enable RFSR ICLK micas RFS Requirement Rev Clk Source FERAE fill MSB w 0s O no RFS required O external 01 Be sign ext MSB 1 RFS required 1 internal iOeeoneecd ee CKRE OPMODE 11 compand A law Active Clock Edge Operation Mode SENDN O falling edge Q non I2S mode Endian word format t rising edge 42125
98. s Manual I 3 INDEX Fn CLIP Fx BY Fy B 49 Fn FLOAT Rx B 41 Fn FLOAT Rx BY Ry B 41 Fn Fx COPYSIGN Fy B 46 Fn Fx Fy B 26 Fn Fx Fy B 27 Fn MAX Fx Fy B 48 Fn MIN Fx Fy B 47 Fn PASS Fx B 34 Fn RECIPS Fx B 42 Fn RND Fx B 35 Fn RSQRTS Fx B 44 Fn SCALB Fx BY Ry B 36 Rn Rx B 16 Rn Rx Ry 2 B 10 Rn ABS Rx B 17 Rn CLIP Rx BY Ry B 25 Rn FIX Fx B 39 Rn FIX Fx BY Ry B 39 Rn LOGB Fx B 38 Rn MANT Fx B 37 Rn MAX Rx Ry B 24 Rn MIN Rx Ry B 23 Rn NOT Rx B 22 Rn PASS Rx B 18 Rn Rx AND Ry B 19 Rn Rx OR Ry B 20 Rn Rx XOR Ry B 21 Rn Rx Ry B 7 Rn Rx Ry Cl B 9 Rn TRUNC Fx B 39 Rn TRUNC Fx BY Ry B 39 ALU status flags 2 16 AC ALU fixed point carry 2 16 AF ALU floating point operation 2 16 Al ALU floating point invalid operation 2 16 AIS ALU floating point invalid operation 2 17 AN ALU result negative 2 16 AOS ALU fixed point overflow 2 17 AS ALU x input sign 2 16 ASTAT status bits summary of 2 16 AUS ALU floating point underflow 2 17 AV ALU overflow 2 16 AVS ALU floating point overflow 2 17 AZ ALU result 0 or floating point underflow 2 16 CACC compare accumulation register 2 16 CACC update timing 2 16 Rn Rx 1 B 14 dual add subtract fixed point Rn Rx Cl B 12 B 96 Rn Rx Cl 1 B 13 dual add subtract floating point Rn Rx Ry B 6 B 98 Rn Rx Ry Cl B 8 fixed point carry flag 2 18 Rn Rx 1 B 15 floating to fixed point 1 4 ADSP 21065L SHARC DSP User s Manual conversions
99. see DMA Cx registers cycle defined 6 28 data buffers 6 4 data packing through the EPBx buffers 6 51 data transfers see DMA data transfers disabling chaining 6 39 enabling 6 9 external port FIFO buffers EPBx see EPBx buffers flushing the request counter FLSH 6 18 grant outputs 6 3 6 64 see also DMAGx II index register overflow 6 29 interrupts 6 45 maximum number of requests without a grant 6 64 mode configurations summary of 6 56 operation 6 27 operation modes 6 11 overall throughput of multiple ADSP 21065L SHARC DSP User s Manual I 21 INDEX DMA channel memory accesses 6 74 packing sequence for download of processor instructions from a 16 bit bus 6 53 packing sequence for download of processor instructions from a 32 bit bus 6 52 packing sequence for host to processor 8 to 48 bit words 6 54 parameter registers see DMA parameter registers polling for DMA status restrictions on 6 26 request inputs 6 3 see also DMARx sequence 6 29 6 39 6 48 6 49 system configurations for interprocessor operatio