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ANALOG DEVICES ADSP-BF522 handbook

1. o 0000000006969 0660000000006 00000000007 0000000060070 000900000000 gt GND DDINT O O O O O O O O O O O O O O O O O O O O O e 22 23 e N A 2 N p SS x r 2 o 3 B o ES e 11 v i5 5 A1 BALL PAD CORNER e e ecee0o0o0000 000000080860 BOTTOM VIEW eeoooooooooc O O E E E E E E 0600000000070 00000000000 KEY GND DDINT e000000000000000000000e 6 1 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 54 32 BGA Ball Configuration Bottom View Ball CS Figure 66 289 Page660f72 August 2008 Rev PrE ADSP BF522 523 524 525 526 527 208 BALL CSP_BGA BALL ASSIGNMENT Table 51 lists the CSP_BGA balls by signal mnemonic Table 52 on Page 68 lists the CS
2. w oo oo Y oo 23222120191817161514131211109 8 7 654321 TOP VIEW BEN BOTTOM VIEW PLLIM ut 140 4 0 20 MIN 111 DETAIL A SIDE VIEW 9 7 2 4 NOTES 1 DIMENSIONS ARE IN MILLIMETERS pt 2 COMPLIES WITH JEDEC REGISTERED OUTLINE Ed MO 195 VARIATION AJ AND EXCEPTION TO PACKAGE HEIGHT AND BALL HEIGHT 0 35 SEATING PLANE 3 MINIMUM BALL HEIGHT 0 20 BALL DIAMETER 0 30 DETAIL A 0 25 Figure 69 289 Ball CSP_BGA BC 289 2 Rev PrE Page700f72 August 2008 ADSP BF522 523 524 525 526 527 17 10 A1 CORNER 17 00 SQ INDEX AREA 46 an 20 18 16 14 12 108 6 4 2 16 90 9 17 6 151 9 7 5 3 1 000000000 A OOOOOOOOO B oo c OO D A1BALL 99 E CORNER 1850 HE BSC SQ OO K oo L 99 N 8 20 BSC oo v Y OO W TOP VIEW BOTTOM VIEW DETAIL A 1 75 CN 1 36 161 DETAIL A 1 26 1 46 1 16 0 35 0 30 MIN A 21 2 0 50 copLANaRITY SEATING 045 0 12 0 40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO 205 AM WITH EXCEPTION TO PACKAGE HEIGHT AND BALL DIAMETER Figure 70 208 Ball BC 208 2 SURFACE MOUNT DESIGN Table 53 is provided as an aide to PCB design 4 standard de
3. eoo ooooooe Y amp VDDMEM 123456 78 9 10 11 12 13 14 15 16 17 18 19 20 TOP VIEW INN AL Figure 67 208 Ball CSP Configuration View A1 BALL PAD CORNER A e B eooooo 660060070000 H o e e e e e o o 4 o e e e e e o o L o e e eo e e 6 o 8 0000000 60 R o VDDINT GND T U oo VDDEXT w o VDDMEM Y e 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW Figure 68 208 Ball CSP_BGA Ball Configuration Bottom View Rev PrE Page690f72 August 2008 ADSP BF522 523 524 525 526 527 OUTLINE DIMENSIONS Dimensions in Figure 69 289 Ball CSP_BGA BC 289 2 are shown in millimeters 0 5 BSC he _____ 12 00 BSC SQ BALL 11 00 BSC SQ 1 BALL 2 PAD CORNER A1 BALL PAD CORNER 50220422222 4 00000900000 K oo L o e 00 e o N oo 00000600000 oo P oo R 000006000000 T
4. tupspip topspip tpspui MISOx OUTPUT 1 MOSIx INPUT MSB VALID LSB VALID 0 tupspip topspip tpspui MISOx OUTPUT 0 gt tsspip 5 VALID gt LSB VALID Figure 26 Serial Peripheral Interface SPI Port Slave Timing Rev PrE Page480f72 August 2008 ADSP BF522 523 524 525 526 527 Universal Asynchronous Receiver Transmitter UART Ports Receive and Transmit Timing Figure 27 describes the UART ports receive and transmit opera and the external data operations These latencies are negligible tions The maximum baud rate is SCLK 16 There is some at the data transmission rates for the UART latency between the generation of internal UART interrupts CLKOUT SAMPLE CLOCK RECEIVE STOP INTERNAL UART RECEIVE UARTRECEIVE BIT SET BY DATA STOP INTERRUPT CLEARED BY FIFO READ START UARTx Tx DATA 5 8 X y 1 STOP 1 2 TRANSMIT INTERNAL UART TRANSMIT BIT SET BY PROGRAM UART TRANSMIT CLEARED BY WRITE TO TRANSMIT INTERRUPT Figure 27 UART Ports Receive and Transmit Timing General Purpose Port Timing Table 34 and Figure 28 describe INT TE port operations d Table 34 General Purpose Port Timing ADSP BF522 524 526 ADSP BF523 525 527 1 8 V Vig 2 5 3 3 V 1 8 V Vopr 2 5 3 3 V Parameter Min Max Min Max Min Max Mi
5. Referenced to drive edge i Table 29 Serial Ports Internal Clock ADSP BF522 524 526 ADSP BF523 525 527 Vopext 1 8 V Vopexr 2 5 3 3 Vopexr 1 8 V Vopexr 2 5 3 3 V Parameter Min Min Max Min Max Min Max Unit Timing Requirements TFSx RFSx Setup Before TSCLKx RSCLKx 11 3 11 3 9 6 9 6 ns TFSx RFSx Hold After TSCLKx RSCLKx 1 5 1 5 1 5 1 5 ns tg Data Setup Before RSCLKx 11 3 11 3 9 6 9 6 ns thor Receive Data Hold After RSCLKx 1 5 1 5 1 5 1 5 ns Switching Characteristics TSCLKx RSCLKx Width 5 4 5 4 4 5 4 5 ns TSCLKx RSCLKx Period 18 0 18 0 15 0 15 0 ns tors TFSx RFSx Delay After TSCLKx RSCLKx 3 0 3 0 3 0 3 0 ns Internally Generated TFSx RFSx tuor TFSx RFSx Hold After TSCLKx RSCLKx 4 0 4 0 1 0 1 0 ns Internally Generated TFSx RFSx toon Transmit Data Delay After TSCLKx 3 0 3 0 3 0 3 0 ns tup Transmit Data Hold After 5 18 18 1 0 1 0 ns Referenced to sample edge Referenced to drive edge Rev PrE Page440f72 August 2008 Table 30 Serial Ports Enable and Three State ADSP BF522 523 524 525 526 527 ADSP BF522 524 526 ADSP BF523 525 527 Vopext 1 8 V Vopexr 2 5 3 3 V Vopexr 1 8 V Vopecr 2 5 3 3 V Parameter Min Max Min Max Min Max Min Max Unit Switching Characteristics toreng Data Enable Delay from External 5 1 0
6. 3 3 V 25 TBD uA State Lj Applies to input balls 2 Applies to JTAG input balls TMS TRST Applies to three statable balls Applies to bidirectional balls SCL and SDA Applies to all signal balls 9 Guaranteed but not tested Rev PrE Page310f72 August 2008 ADSP BF522 523 524 525 526 527 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in the table may cause perma nent damage to the device These are stress ratings only Functional operation of the device at these or any other condi tions greater than those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Parameter Rating Internal Supply Voltage tod V to tbd V External I O Supply Voltage 0 3 V to 3 8 V Vopext Vopmem Input Voltage 0 5 V to 3 6 V Input Voltage 23 0 5 V to 45 5 V Input Voltage 4 0 5V to 45 25 V Output Voltage Swing 0 5 V to Vbpext Voomemt 0 5 V Load Capacitance 200 pF Storage Temperature Range 65 C to 150 Junction Temperature Underbias 110 C 1 Applies to 100 transient duty cycle For other duty cycles see Table 18 2 Applies only when is within specifications When Vppexr is outside speci fications the range is 0 2 Volts Applies to balls SCL and SDA
7. ETxD1 0 ETxEN q treFcLKov Figure 37 10 100 Ethernet MAC Controller Timing RMII Transmit Signal MII CRS COL 1 5 tecoLH tecoLL Figure 38 10 100 Ethernet MAC Controller Timing Asynchronous Signal MDC OUTPUT 1 1 tupcon MDIO OUTPUT 4 wpcov gt MDIO INPUT 4 9 Figure 39 10 100 Ethernet MAC Controller Timing Station Management Rev PrE Page560f72 August 2008 ADSP BF522 523 524 525 526 527 JTAG Test And Emulation Port Timing Table 46 and Figure 40 describe JTAG port operations Table 46 JTAG Port Timing 1 8 V 2 5 3 3 V Parameter Min Max Min Max Unit Timing Parameters te Period 20 20 ns TDI TMS Setup Before High 4 4 ns TDI TMS Hold After High 4 4 ns tssys System Inputs Setup Before High 4 4 ns tusys System Inputs Hold After TCK High 5 5 ns trastw TRST Pulse Width measured cycles 4 4 TCK Switching Characteristics toroo Delay from Low 10 10 ns tpsys System Outputs Delay After Low 12 12 ns System Inputs DATA15 0 ARDY SCL SDA PF15 0 PG15 0 15 0 TRST RESET NMI BMODE3 0 250 MHz Maximum 3 System Outputs DATA15 0 ADDRI9 1 1 0 AOE ARE AWE 53 0 SRAS S
8. 1 8 V Vp 2 5 3 3 V Parameter Min Max Max Min Max Max Unit terercLkov REF CLK Rising Edge 8 1 8 1 7 5 7 5 ns to Tx Output Valid Data Out Valid tererctxo REF Rising Edge 2 2 2 2 ns to Tx Output Invalid Data Out Hold RMII outputs synchronous to RMII REF CLK are ETxD1 0 Rev PrE Page540f72 August 2008 ADSP BF522 523 524 525 526 527 Table 44 10 100 Ethernet MAC Controller Timing MII RMII Asynchronous Signal Vos 1 8 V 2 5 3 3 V Parameter Min Min Max Unit COL Pulse Width High X 1 5 tenax X 1 5 ns terxcik X 1 5 terxcik X 1 5 COL Pulse Width Low X 1 5 X 1 5 ns terxcik X 1 5 terxcik X 1 5 CRS Pulse Width High X 1 5 X 1 5 ns CRS Pulse Width Low X 1 5 X 1 5 ns asynchronous signals are COL and CRS These signals are applicable in both and RMII modes The asynchronous COL input is synchronized separately to both the ETxCLK and the and the COL input must have a minimum pulse width high or low at least 1 5 times the period of the slower of the two clocks 2 The asynchronous CRS input is synchronized to the ETxCLK and the CRS input must have a minimum pulse width high or low at least 1 5 times the period of ETxCLK Table 45 10 100 Ethernet MAC Controller Timing MII Station
9. Clock TDO Serial Data Out C TDI Serial Data In TMS JTAG Mode Select TRST JTAG Reset This ball should be pulled low if the port is not used EMU Emulation Output C Rev PrE Page250f72 August 2008 ADSP BF522 523 524 525 526 527 Table 10 Signal Descriptions Continued Driver Signal Name Type Function Clock CLKIN Clock Crystal Input XTAL Crystal Output CLKBUF Buffered XTAL Output C Mode Controls RESET Reset NMI Nonmaskable Interrupt This ball should be pulled high when not used BMODE3 0 Boot Mode Strap 3 0 ADSP BF523 525 527 Voltage Regulator VRseL External Internal Voltage Regulator Select VRout EXT_WAKE1 External FET Drive Wake up Indication 1 G EXT WAKEO Wake up Indication 0 SS PG Soft Start Power Good ADSP BF522 524 526 Voltage Regulation EXT WAKE1 Wake up Indication 1 EXT WAKEO Wake up Indication 0 C PG Power Good Power Supplies ALL SUPPLIES MUST BE POWERED See Qperating Conditions for ADSP BF523 525 5220m Page 29 and s e Operating CondiffonsffOn ADSPBE 522 524 52Ib on Page 27 Uo Power Supply Vopint Internal Power Supply Real Time Clock Power Supply Vppuse P 3 3 V USB Phy Power Supply VppMEM P MEM Power Supply Vpporp P OTP Power Supply Programming Voltage Ground for All Su
10. Driver Signal Name Type Function Port GPIO and Multiplexed Peripherals PFO PPI DO DROPRI ND DOA GPIO PPI Data 0 SPORTO Primary Receive Data C NAND Alternate Data 0 PF1 PPI D1 RFSO ND D1A I O GPIO PPI Data 1 SPORTO Receive Frame Sync C NAND Alternate Data 1 PF2 PPI D2 RSCLKO ND D2A GPIO PPI Data 2 SPORTO Receive Serial Clock D NAND Alternate Data 2 Alternate Capture Input 0 PF3 PPI D3 DTOPRI ND D3A I O GPIO PPI Data 3 SPORTO Transmit Primary Data C NAND Alternate Data 3 PFA PPI DA TFSO ND DAA TACLKO VO GPIO PPI Data 4 SPORTO Transmit Frame Sync C NAND Alternate Data 4 Alternate Timer Clock 0 PF5 PPI D5 TSCLKO ND D5A TACLK1 I O GPIO PPI Data 5 SPORTO Transmit Serial Clock D NAND Alternate Data 5 Alternate Timer Clock 1 PF6 PPI D6 DTOSEC ND_D6A TACIO I O GPIO PPI Data 6 SPORTO Transmit Secondary Data C NAND Alternate Data 6 Alternate Capture Input 0 PF7 PPI D7 DROSEC ND_D7A TACI1 GPIO PPI Data 7 SPORTO Receive Secondary Data C NAND Alternate Data 7 Alternate Capture Input 1 PF8 PPI D8 DR1PRI lO GPIO PPI Data 8 SPORTI Primary Receive Data C PF9 PPI D9 RSCLK1 SPISEL6 lO GPIO PPI Data 9 SPORT1 Receive Serial Clock SPI Slave Select 6 D PF10 PPI D10 RFS1 SPISEL7 lO GPIO PPI Data 10 SPORT1 Receive Frame Sync SPI Slave Select 7 C PF11 PPI D11 TFST1 CZM OF GPTOZPPI Data Vf7SPORT1 Transmit Fram Synd Cauntei Zero Marker C PF12 PPI D12 DT1PRI SPISEL2 CDG 4 VOL GPIO PPI Da
11. Applies to balls USB DP USB DM and For proper SDRAM controller operationythemaxi load capacitance is50 pF at 3 3 V or 30 pF at 2 5 V for ADDRI9 1 DATAI5 0 ABE1 0 SDQM1 0 CLKOUT SCKE 5410 SRAS SCAS SWE and SMS Table 18 Maximum Duty Cycle for Input Transient Voltage Vin Min V Vin Max V Maximum Duty Cycle TBD TBD 100 96 TBD TBD 4096 TBD TBD 2596 TBD TBD 1596 TBD TBD 1096 Applies to all signal balls with the exception of CLKIN XTAL WAKEI When programming OTP memory on the ADSP BF522 524 526 processors the VPPOTP ball must be set to the write value specified in the Operating Conditions for ADSP BF522 524 526 on Page 27 There is a finite amount of cumula tive time that the write voltage may be applied dependent on voltage and junction temperature to VPPOTP over the lifetime of the part Therefore maximum OTP memory programming time for the ADSP BF522 524 526 processors is shown in Table 19 The ADSP BF523 525 527 processors do not have a similar restriction Rev PrE Page320f72 Table 19 Maximum OTP Memory Programming Time for ADSP BF522 524 526 Processors Temperature T VPPOTP Voltage V 25 85 110 125 C 6 9 104 sec tbdsec tbdsec tbd sec 7 0 2400sec tbdsec tbdsec sec 7 1 1000 tbdsec tbdsec tbd sec ESD SENSITIVITY ESD electrostatic discharge sensitive device Charged devices and
12. 1 5 X tak 1 5 X ta INS edge INT mode tij Data hold after HOST RD rising 1 0 1 0 1 0 1 0 ns edge NM Not Measured This parameter is not measured because the time for which HOST ACK is low is system design dependent HOST ADDR HOST CE t om HOST RD HOST ACK pnpHRDY HOST D15 0 Figure 32 HOSTDP A C Host Read Cycle Rev PrE Page520f72 August 2008 ADSP BF522 523 524 525 526 527 HOSTDP A C Timing Host Write Cycle Table 39 describes the HOSTDP A C Host Write Cycle timing requirements Table 39 Host Write Cycle Timing Requirements ADSP BF522 524 526 ADSP BF523 525 527 1 8 V 2 5 3 3 V Vona 1 8 V 2 5 3 3 V Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements tap HOST ADDR HOST CE Setup 4 4 4 4 ns before HOST WR falling edge tuos HOST ADDR HOST CE Hold 2 5 2 5 2 5 2 5 ns after HOST WR rising edge tu HOST WR pulse width low Torovwat trovero Torovwat trovero Toroywat trovero Toroywat trovero ns ACK mode towaHaoy oway towrneoy towrneoy HOST_WR pulse width low 1 5 X tsa 8 7 1 5 X tsak 8 7 1 5 X 8 7 1 5 X tsa 8 7 ns INT mode tww HOST WR pulse width high 2X te 2X 2 X 2 ns or time between HOST WR rising edge and HOST RD falling edge towenroy HOST WR rising edge delay 0 0 0 0 ns after HOST rising edge ACK mod
13. Voot RTC internal logic and crystal I O Memory logic VppMEM USB PHY logic Vppusg OTP logic VpporP All other I O Vppexr The dynamic power management feature of the processor allows both the processor s input voltage and clock fre quency to be dynamically controlled The power dissipated by a processor is largely a function of its clock frequency and the square of the operating voltage For example reducing the clock frequency by 2596 results in a 2596 reduction in dynamic power dissipation while reducing the voltage by 2596 reduces dynamic power dissipation by more than 4096 Further these power savings are additive in that if the clock frequency and supply voltage are both reduced the power savings can be dramatic as shown in the following equations August 2008 ADSP BF522 523 524 525 526 527 Power Savings Factor 2 CCLKRED 5 5 TRED VpDINTNO NOM 96 Power Savings 1 Power Savings Factor x 100 where the variables in the equations are is the nominal core clock frequency Fccixrep 15 the reduced core clock frequency is the nominal internal supply voltage Vppiwragp is the reduced internal supply voltage is the duration running at Tren is the duration running at ADSP BF523 525 527 VOLTAGE REGULATION The ADSP BF523 525 527 provides an on ch
14. single instruction cycle The Blackfin processor assembly language uses an algebraic syn tax for ease of coding and readability The architecture has been optimized for use in conjunction with the C C compiler resulting in fast and efficient software implementations MEMORY ARCHITECTURE The Blackfin processor views memory as a single unified 4G byte address space using 32 bit addresses All resources including internal memory external memory and I O control registers occupy separate sections of this common address space The memory portions of this address space are arranged in a hierarchical structure to provide a good cost performance balance of some very fast low latency on chip memory as cache or SRAM and larger lower cost and performance off chip memory systems See Figure 3 The on chip L1 memory system is the highest performance memory available to the Blackfin processor The off chip mem ory system accessed through the external bus interface unit Rev PrE 5 of 72 EBIU provides expansion with SDRAM flash memory and SRAM optionally accessing up to 516M bytes of physical memory The memory DMA controller provides high bandwidth data movement capability It can perform block transfers of code or data between the internal memory and the external memory spaces OxFFFF FFFF gt OxFFEO 0000 SYSTEM MMR REGISTERS 2M BYTES OxFFCO 0000 gt OxFFBO 1000 OxFFBO 0000 OxFF
15. 1 9 DATA10 P2 0 PFO 7 PH13 N22 Voor 17 07 1 AB8 DATA11 R2 GND 1 IPFI B8 14 N23 Vppexr R17 U8 ADDR2 AC8 DATA12 N1 N12 PF2 8 15 P22 T17 U9 ADDR3 AB7 DATA13 2 GND 3 PF3 B9 6 U17 U10 ADDR4 AC7 DATA14 M2 GND N14 PF4 B11 1 87 85 911 5 DATA15 M1 GND N15 PF5 B10 RESET V22 Vpaw 8 U12 ADDR6 EMU J2 GND PF6 B12 U23 9 U13 ADDR7 4 WAKEO AC19 GND P10 PF7 B13 RTXO V23 Voonr H10 014 ADDR8 5 GND 1 P11 PF8 B16 SA10 AClO Vppgar 11 U15 ADDR9 5 GND A23 GND P12 PF9 20 SCAS AC11 Vpp wr 12 016 ADDR10 GND B6 GND P13 PF10 815 5 AB13Vppw H13 Vppore AC12 ADDR11 GND G16 GND P14 PF11 B17 SCL B22 Vbonr H14 W23 ADDR12 GND G17 GND P15 PF12 B18 SDA C22 15 Vppuss W22 ADDR13 2 GND H17 GND R9 PF13 B19 SMS H16 23 ADDR14 AC2 GND H22 GND R10 PF14 9 12 28 INC G23 ADDR15 2 GND J22 GND R11 15 A10 SS PG AC20 Vppwr 216 18 16 W2 GND 9 GND R12 PGO H2 22 ADDR17 Y2 110 GND Ri13 PGl GI 1
16. 9 123 K17 Voomem 7 DATA7 T1 M14 NC 123 PH10 M22 117 P7 8 R1 GND M15 U22 11 R22 Vbpex M17 87 NOTE In this table BOLD TYPE indicates the sole signal function for that ball on ADSP BF522 524 526 processors For ADSP BF52xC compatibility connect this ball to Vppexr Rev PrE Page640f72 August 2008 ADSP BF522 523 524 525 526 527 Table 50 289 Ball CSP_BGA Ball Assignment Numerically by Ball Number Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal No GND B23 NC H22 GND L22 PH8 22 15 022 NMI 5 ADDR9 2 12 PG8 23 123 7 23 XTAL 023 AC6 ADDR5 A3 PG13 2 PG6 1 TDI M1 DATA15 R1 DATA8 V1 DATA4 7 ADDRA 4 PG14 C22 SDA 2 EMU 2 DATA14 R2 DATA11 V2 8 ADDR2 A5 15 C23 NC U7 7 Vppmem R7 Vppmem 22 9 ABE1 SDQM1 CLK TMRCLKD1 PG4 08 Vppint 8 Vponr 23 RTXO 10 SA10 A7 02 PG5 J9 GND 9 GND R9 GND W1 DATA2 11 SCAS A8 022 NC J10 GND 10 GND R10 GND 2 ADDR16 12 A9 PF14 D23 NC J11 GND M11 GND R11 GND 22 Vppuse 13 SMS A10 PF15 BMODE2 12 GND 12 GND R12 GND W23 Vppnrc 14 ARDY A11 PHO E2 J13 GND 13 GND R13 GND DATAO 15 12 1 E22 NC 14 GND M14 GND R14 GND Y2
17. C PH7 ND_D7 ETxD1 HOST_D7 I O GPIO NAND D7 Ethernet or RMII Transmit D1 Host DMA D7 C PH8 SPISEL4 ERxD1 HOST_D8 TACLK2 GPIO Alternate Capture Input 2 Ethernet or RMII Receive D1 Host DMA D8 SPI Slave Select 4 PH9 SPISEL5 ETxD2 HOST D9 TACLK3 VO GPIO SPI Slave Select 5 Ethernet Transmit D2 Host DMA D9 C Alternate Timer Clock 3 PH10 ND 2 5 D10 V Or GPIO ANAND Chip Enable Ethernet MIlReceiveiD2 LHost D10 C PH11 ND_WE ETxD3 HOST 011711 UO GPIO NAND Write ErablefEthelnet Ml m d DMA D11 C PH12 ND RE ERxD3 HOST D12 GPIO NAND Read Enable Ethernet MII Receive D3 Host D12 C PH13 ND BUSY ERxCLK HOST D13 VO GPIO NAND Busy Ethernet Receive Clock Host DMA D13 C PH14 ND CLE ERXDV HOST D14 GPIO NAND Command Latch Enable Ethernet or Receive Data C Valid Host DMA D14 PH15 ND ALE COL HOST D15 GPIO NAND Address Latch Enable Ethernet Collision Host DMA Data 15 Port J Multiplexed Peripherals PJO FS1 TMRO I O Frame 5 1 0 PJ1 PPI CLK TMRCLK PPI Clock Timer Clock PJ2 SCL 5V Serial Clock This pin is an open drain output and requires a pull up E resistor PJ3 SDA 5V TWI Serial Data This pin is an open drain output and requires a pull up E resistor Real Time Clock RTXI Crystal Input This ball should be pulled low when not used RTXO Crystal Output JTAG Port TCK
18. DECAY 47 Vioap The time for the voltage on the bus to decay by AV is dependent PIN T on the capacitive load C and the load current I This decay time can be approximated by the equation d 1 Figure 54 Equivalent Device Loading for Measurements The time is calculated with test loads C and I and with Includes All Fixtures equal to 0 5 V for nominal 2 5 V 3 3 V The time tj mrasuren is the interval from when the reference sig nal switches to when the output voltage decays AV from the measured output high or output low voltage Rev PrE Page600f72 August 2008 ADSP BF522 523 524 525 526 527 Example System Hold Time Calculation To determine the data output hold time in a particular system first calculate using the equation given above Choose AV to be the difference between the processor s output voltage and the input threshold for the device requiring the hold time is the total bus capacitance per data line and I is the total leak age or three state current per data line The hold time will be tpscay plus the various output disable times as specified in the Timing Specifications on Page 33 for example tpspar for an SDRAM write cycle as shown in SDRAM Interface Timing on Page 39 Capacitive Loading Output delays and holds are based on standard capacitive loads of an average of 6 pF on all balls see
19. 1 8 V 2 5 V or 3 3 V Grid Array 5 BGA ADSP BF527BBCZ 5AX 40 to 85 208 Ball Chip Scale Package Ball 208 2 533 MHz 1 15 Vinternal 1 8 V 2 5 V or 3 3 rid Array ESP BGA 1 Referenced temperature is ambient tempera 7 ture 2 This is the voltage required to run at the DIMM ion tate Lesser frequencies may xequire lower operating voltages Please 1 Table 12 and Table 15 for details 2008 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www analo g com PR06675 0 9 08 PrE DEVICES Rev PrE Page720f72 August 2008
20. CONFIG at least once before beginning to con figure the Host DMA Port After completing the configuration the host is required to poll the READY bit in HOST STATUS before beginning to transfer data When the host sends an HIRQ control command the boot kernel issues a CALL instruction to address 0000 It is the host s responsibility to ensure that valid code has been placed at this address The routine at OXFFAO 0000 can simple initialization routine to configure internal resources such as the SDRAM controller which then returns using an RTS instruction The routine may also by the final application which will never return to the boot kernel Boot from 8 Bit Host BMODE OxF In this mode the Host DMA port is configured in 8 bit interrupt mode with little endian data formatting Unlike other modes the host is responsible for interpreting the boot stream It writes data blocks individually into the Host DMA port Before configuring the DMA settings for each a blocky th host may either 22 ALLOW CONFIG bit in HOST STATUS or waitko be interrupted by the HWAIT signal When using HWAIT the host must still check ALLOW CONFIG at least once before beginning to con figure the Host DMA Port The host will receive an interrupt from the HOST signal every time it is allowed to send the next FIFO depths worth sixteen 32 bit words of information When the host sends an HIRQ con trol command the bo
21. Page420f72 August 2008 ADSP BF522 523 524 525 526 527 SYNC IS DRIVEN DATAO IS OUT DRIVEN OUT PPI CLK POLC 0 POLC 1 luorsPE 4 POLS 1 PPI FS1 POLS 0 PPI DATA Figure 22 PPI GP Tx Mode with Internal Frame Sync Timing INN D N ALI Rev PrE Page430f72 August 2008 ADSP BF522 523 524 525 526 527 Serial Ports Table 28 through Table 31 on Page 45 and Figure 23 on Page 46 through Figure 24 on Page 46 describe serial port operations Table 28 Serial Ports External Clock ADSP BF522 524 526 ADSP BF523 525 527 1 8 V 2 5 3 3 V 1 8 V Vp 2 5 3 3 V Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements TFSx RFSx Setup Before TSCLKx RSCLKx 3 0 3 0 3 0 3 0 ns tuse TFSx RFSx Hold After TSCLKx RSCLKx 3 0 3 0 3 0 3 0 ns Receive Data Setup Before RSCLKx 3 0 3 0 3 0 3 0 ns Data Hold After RSCLKx 3 6 3 6 3 0 3 0 ns TSCLKx RSCLKx Width 54 54 4 5 4 5 ns TSCLKx RSCLKx Period 18 0 18 0 15 0 15 0 ns Switching Characteristics torse TFSx RFSx Delay After TSCLKx RSCLKx 12 0 12 0 10 0 10 0 ns Internally Generated TFSx RFSx tuorse TFSx RFSx Hold After TSCLKx RSCLKx 0 0 0 0 0 0 0 0 ns Internally Generated TFSx RFSx toore Transmit Data Delay After TSCLKx 12 0 12 0 10 0 10 0 ns tup Transmit Data Hold After TSCLKx x 1 09 0 0 4 0 0 0 0 ns
22. Receive Data Setup Before 3 5 3 5 3 5 3 5 ns tuprpe Receive Data Hold After PPI_CLK 1 5 1 5 1 5 1 5 ns Switching Characteristics GP Output and Frame Capture Modes torspe_ Internal Frame Sync Delay After PPI CLK 8 8 8 8 8 0 8 0 ns tuorspe Internal Frame Sync Hold After PPI_CLK 1 7 1 7 1 7 1 7 ns tppre Transmit Data Delay After PPI_CLK 8 8 8 8 8 0 8 0 ns Transmit Data Hold After 1 8 1 8 1 8 1 8 ns PPI CLK frequency cannot exceed 2 5 4 i DATAO IS DATA1 IS SAMPLED SAMPLED PPI CLK POLC 0 POLC 1 POLS 1 FS1 a POLS 0 POLS 1 PPI FS2 a POLS 0 tspRPE Figure 19 PPI GP Rx Mode with External Frame Sync Timing Rev PrE Page410f72 August 2008 ADSP BF522 523 524 525 526 527 PPI_CLK POLC 0 PPI_CLK POLC 1 POLS 1 PPI_FS1 POLS 0 15 1 52 POLS 0 PPI DATA POLC 0 PPI CLK PPI CLK POLC 1 POLS 1 PPI FS1 POLS 0 POLS 1 PPI_FS2 POLS 0 DRIVING DRIVING FRAME FRAME SYNC SYNC SAMPLING SAMPLING EDGE EDGE SFSPE ipprPE luprpE Figure 20 Mode with Extemal Frame Syne Timing 1 SYNC IS DATAO DRIVEN IS OUT SAMPLED DFSPE uorsPE O spnpE Figure 21 PPI GP Rx Mode with Internal Frame Sync Timing Rev PrE
23. ADDR17 AC16 AMS2 A13 PH2 E23 NC 15 GND 15 GND R15 GND Y22 USB ID 17 50 A14 PHA F1 PG3 016 Voowr 16 R16 Vppinr 23 18 15 F2 BMODE1 017 Vppexr M17 Vppext R17 1 ADDR18 19 EXT WAKEO A16 NC F22 NC 22 GND M22 10 R22 11 2 15 AC20 SS PG A17 NC F23 NC 23 NC M23 PH12 R23 AA22USB DP 21 USB RSET A18 NC G1 1 K1 TDO N1 DATA12 1 DATA7 AA23USB XO 22 USB VREF A19 NC 52 BMODEO K2 TRST N2 DATA13 2 DATA6 AB1 ADDR19 23 GND A20 PF9 57 Vppext 7 Vppmem Vppmem 7 Vooww 2 ADDR13 21 58 K8 Vppir 8 Vppwr AB3 11 22 9 GND GND T9 4 ADDR7 A23 GND 610 ST N10 6ND 0 5 ADDR B1 PG7 G11 AY 4 GND N11 GND B2 PG9 512 Vppexr K12 GND N12 GND T12 Vopn 7 ADDR3 B3 11 513 Vppext K13 GND N13 GND T13 Vopn 8 ADDRI B4 10 514 Vopexr K14 GND N14 GND T14 Vopn 9 ABEO SDOMO B5 G15 Vppexr K15 GND N15 GND T15 Vopn 10 SWE B6 GND 516 GND K16 N16 T16 11 B7 FS1 TMRO 17 GND K17 N17 117 AB12 SRAS B8 PF1 G22 NC K22 PH6 N22 PH13 22 GND 13 SCKE B9 G23 NC K23 PH5 23 14 T23 PH9 AB14 AWE B10 PF5 H1 PG2 L1 TCK P1 DATA9 1 DATA5 AB15 AMS3 B11 H2 PGO L2 TMS P2 DATA1
24. ADSP BF522 523 524 525 526 527 HOSTDP A C Timing Host Read Cycle Table 38 describe the HOSTDP A C Host Read Cycle timing requirements Table 38 Host Read Cycle Timing Requirements ADSP BF522 524 526 ADSP BF523 525 527 1 8 V 2 5 3 3 V 1 8 V 2 5 3 3 V Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements HOST_ADDR and HOST CE Setup 4 4 4 4 ns before HOST_RD falling edge tp HOST ADDR and HOST CE Hold 2 5 2 5 2 5 2 5 ns after HOST RD rising edge HOST RD pulse width low Vosovep rovero toroveo trovero Torovaot trovero Torovrow trovero ns ACK mode toroHRoy torney pulse width low 1 5 X tak 8 7 1 5 X tsx 8 7 1 5 X tac 8 7 1 5 X tsak 8 7 ns INT mode tow 5 RD pulse width high 2 X tsc 2 X tsak 2 X tsak 2 X tsak ns or time between HOST_RD rising edge and HOST_WR falling edge HOST RD rising edge delay after 0 0 0 0 ns HOST ACK rising edge mode Switching Characteristics tm Data valid prior HOST rising 4 5 3 5 4 5 3 5 ns edge ACK mode Host assertion delay after deae cen 1 5 x 15 1 5 INS HOST RD HOST 192 7 towo _ low pulse width NM Ins for Read access ACK mode Data disable after HOST RD 9 0 9 0 9 0 9 0 Ins Data valid after HOST RD falling 1 5 X 1 5
25. Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure Level 1 L1 memories are those that typically operate at the full processor speed with little or no latency At the 1 1 level the instruction memory holds instructions only The two data memories hold data and a dedicated scratchpad data memory stores stack and local variable information In addition multiple L1 memory blocks are provided offering a configurable mix of SRAM and cache The memory manage ment unit MMU provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access The architecture provides three modes of operation user mode supervisor mode and emulation mode User mode has restricted access to certain system resources thus providing a protected software environment while supervisonmode 25 unrestricted access to the systeni andicore resources The Blackfin processor instruction set has been optimized so that 16 bit opcodes represent the most frequently used instruc tions resulting in excellent compiled code density Complex DSP instructions are encoded into 32 bit opcodes representing fully featured multifunction instructions Blackfin processors support a limited multi issue capability where a 32 bit instruc tion can be issued in parallel with two 16 bit instructions allowing the programmer to use many of the core resources in
26. 119 R1 TDI Y3 DATA10 A2 PF9 B20 GND H14 Vopint 120 53 R2 YA PF11 C1 PF5 H19 USB VREF 1 PG5 R19 SMS Y5 DATA6 4 SCL C2 PF6 H20 WAKEO M2 PG6 R20 Y6 4 A5 PF13 C19 CLKBUF J1 11 M7 T1 Y7 2 15 C20 USB ID J2 12 8 T2 Y8 DATAO A7 PHO 7 M9 GND T19 58 5 Y9 BMODE2 A8 PH2 D2 PF4 J8 M10 GND T20 SWE Y10 BMODEO A9 019 J9 GND M11 GND U1 TRST Y11 ADDR19 A10 XTAL D20 USB RSET 10 GND M12 GND 02 5 Y12 ADDR17 A11 E1 PF1 J11 GND M13 GND 019 SA10 13 ADDR15 A12 PH8 PF2 J12 GND M14 Vppwr U20 SCAS Y14 ADDR13 A13 10 E19 USB VBUS 13 GND M19 AMS2 V1 DATA15 Y15 ADDRI1 A14 RTXI E20 USB DP 14 Vopr M20 V2 Y16 ADDR9 A15 RTXO F1 PFO 19 50 1 V19 ABEO SDOMO Y17 ADDR7 A16 F2 PPI FSI TMRO J20 EXT PG4 V20 1 50 1 Y18 ADDRS5 A17 GND F19 VRsg Vpprxr K1 9 7 W1 14 Y19 ADDR3 A18 USB XO F20 USB DM K2 PG10 8 W2 DATA13 Y20 GND A19 USB 61 15 7 Vopba s GND W3 _ DATA11 A20 GND G2 N10 GND w4 vy Bl PF7 Gr Vee GND INT GND W5 B2 PF8 G8 K10 GND N12 GND W6 DATAS B3 1 G9 K11 GND N13 GND W7 DATA3 B4 SDA 610 K12 GND N14 Vppwr W8 B5 12 611 GND 19 W9 BMODE3 B6 14 G12 K14 Vpoir N
27. 2 Must remain powered even if the associated function is Hot sed 1 4 is the supply to the voltage TP 17 GPIO If not used power with Vpprxr 1 5 Balls that use DATA15 0 ADDR19 1 0 ARE AWE AOE 53 0 ARDY 5410 SWE SCAS CLKOUT SRAS SMS SCKE These balls are not tolerant to voltages higher than When not using the USB peripheral on the ADSP BF525 BF527 or terminating Vppusg on the ADSP BF523 must be powered by Vppexr 7 Bidirectional balls PF15 0 PG15 0 PH15 0 and input balls RTXI TDI TMS TRST CLKIN RESET NMI and BMODE3 0 of the ADSP BF522 523 524 525 526 527 processors are 3 3 V tolerant always accept up to 3 6 V maximum Vj Voltage compliance on outputs Von is limited by the Vppexr supply voltage Parameter value applies to all input and bidirectional balls except USB DP USB DM USB VBUS SDA and SCL The min and max value vary with the selection in the TWI DT field ofthe NONGPIO DRIVE register See Vgusrw min and max values in Table 11 on Page 27 SDA and SCL are pulled up to See Table 11 on Page 27 Rev PrE Page290f72 August 2008 ADSP BF522 523 524 525 526 527 ADSP BF523 525 527 Clock Related Operating Conditions Table 15 describes the core clock timing requirements for the ADSP BF523 525 527 processors Take care in selecting MSEL SSEL and CSEL ratios so
28. 5 1 0 1 5 2 0 2 5 3 0 SOURCE VOLTAGE V 50 E Figure 42 Drive Current A High 2 TBD 0 2 o 6 50 o o 100 150 0 0 5 10 1 5 2 0 25 3 0 SOURCE VOLTAGE V Figure 45 Drive Current C Low Rev PrE Page580f72 August 2008 150 100 50 SOURCE CURRENT mA 100 150 0 150 100 50 SOURCE CURRENT mA 4 TBD 0 5 1 0 1 5 2 0 2 5 3 0 SOURCE VOLTAGE V Figure 46 Drive Current C High Vppex Vppmew TBD 150 100 50 SOURCE CURRENT mA 100 150 0 0 5 1 0 1 5 2 0 2 5 3 0 SOURCE VOLTAGE V Figure 47 Drive Current D Low TBD 0 5 1 0 1 5 2 0 2 5 3 0 SOURCE VOLTAGE V Figure 48 Drive Current D High Rev PrE Page590f72 ADSP BF522 523 524 525 526 527 150 100 50 TBD SOURCE CURRENT mA 100 150 0 0 5 1 0 1 5 2 0 2 5 3 0 SOURCE VOLTAGE V Figure 49 Drive Current E Low Vppexy 150 100 50 TBD SOURCENCURRENT mA T 100 0 0 5 1 0 1 5 2 0 2 5 3 0 SOURCE VOLTAGE V Figure 50 Drive Current E High 150 100 50 TBD SOURCE CURRENT mA 10
29. A IVG12 40 5 1 5 IMASK1 1581 1 Port G Interrupt B 612 41 5 7 1581 IWR1 MDMA Stream 0 1 42 1 6 E MARS 1 ISR1 IWR1 MDMA Stream 1 IVG13 43 6 IAR5 IMASK1 1581 1 Software Watchdog Timer IVG13 44 6 IAR5 IMASK1 ISR1 IWR1 Port F Interrupt A IVG13 45 6 IAR5 IMASK1 1581 1 Port F Interrupt B IVG13 46 6 IAR5 IMASK1 1581 1 SPI Status IVG7 47 0 IAR5 IMASK1 1581 1 NFC Status IVG7 48 0 IAR6 1 5 1 1581 1 HOSTDP Status IVG7 49 0 IAR6 IMASK1 1581 WR1 Host Read Done 50 0 6 1 5 1 1581 1 USB EINT Interrupt IVG10 51 3 IAR6 1 5 1 1581 1 USB INTO Interrupt IVG10 52 3 IAR6 1 5 1 1581 1 USB Interrupt IVG10 53 3 IAR6 1 5 1 1581 1 USB INT2 Interrupt IVG10 54 3 IAR6 1 5 1 1581 1 USB DMAINT Interrupt IVG10 55 3 IAR6 IMASK1 1581 1 Event Control event has been accepted into the system This register is updated automatically by the controller but it may be writ Th id flexibl hanism t trol th E 260 ten only when its corresponding IMASK bit is cleared processing of events In the CEC three registers are used to coordinate and control events Each register is 16 bits wide CEC interrupt mask register IMASK Controls the CEC interrupt latch register ILAT Indicates when masking and unmasking of individual events Whena bit is events have been latched The appr
30. All Speed Grades Parameter Max Unit Core Clock Frequency tbd V minimum 400 MHz Core Clock Frequency 4 V minimum 350 MHz Core Clock Frequency tbd V minimum 300 MHz Core Clock Frequency V minimum TBD MHz Core Clock Frequency V minimum TBD MHz See the Ordering Guide on Page 72 Preliminary data indicates a value of 1 33 V Applies only to 400 MHz speed grade only See the Ordering Guide on Page 72 Preliminary data indicates a value of 1 235 V Preliminary data indicates a value of 1 14 V Table 13 Phase Locked Loop Operating Conditions Parameter Minimum Maximum Unit fvco Voltage Controlled Oscillator VCO Frequency 50 Speed Grade MHz See the Ordering Guide on Page 72 7 Table 14 ADSP BF522 524 526 Processors Maximum SCLK Conditions Parameter 1 8 V 2 5 V 3 3 V Nominal Unit fa CLKOUT SCLK Frequency Voon gt V 80 MHz CLKOUT SCLK Frequency Voon lt tod V tbd MHz 1 fax must be less than or equal to and is subject to additional restrictions for SDRAM interface operation See Table 25 on Page 39 Rev PrE Page280f72 August 2008 ADSP BF522 523 524 525 526 527 OPERATING CONDITIONS FOR ADSP BF523 525 527 Parameter Conditions Min Nomin
31. An emulation event causes the processor to enter emulation mode allowing command and control of the processor via the JTAG interface RESET This event resets the processor Nonmaskable Interrupt NMI The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor The NMI event is frequently used as a power down indicator to initiate an orderly shut down of the system Exceptions Events that occur synchronously to program flow in other words the exception is taken before the instruction is allowed to complete Conditions such as data alignment violations and undefined instructions cause exceptions Interrupts Events that occur asynchronously to program flow They are caused by input signals timers and other peripherals as well as by an explicit software instruction August 2008 ADSP BF522 523 524 525 526 527 Each event type has an associated register to hold the return address and an associated return from event instruction When Table 2 Core Event Controller CEC an event is triggered the state of the processor is saved on the Priority supervisor stack 015 Highest Event Class EVT Entry The processor event controller consists of two stages the core 0 Emulation Test Control EMU event controller CEC and the system interrupt controller 1 RESET RST SIC The core event controller works with the system interrupt 2 Nonmaskable Interrup
32. CLKIN Period 20 0 100 0 ns CLKIN Low Pulse 10 0 ns tekini CLKIN High Pulse 10 0 ns tBUFDLAY CLKIN to CLKBUF Delay 10 ns RESET Asserted Pulse Width Low 11 tekn ns Applies to bypass mode and non bypass mode Applies after power up sequence is complete At power up the processor s internal phase locked loop requires no more than 2000 CLKIN cycles while RESET is asserted assuming stable power supplies and CLKIN not including start up time of external clock oscillator CLKIN 4 tpurpLay 779 twrst RESET 2 Figure 9 Clock and Reset Timing Rev PrE Page330f72 August 2008 ADSP BF522 523 524 525 526 527 Asynchronous Memory Read Cycle Timing Table 22 Asynchronous Memory Read Cycle Timing Voomem 1 8 V 2 5 3 3 V Parameter Min Max Min Max Unit Timing Requirements 15 0 Setup Before CLKOUT 2 1 2 1 ns 15 0 Hold After CLKOUT 0 8 0 8 ns tsarpy ARDY Setup Before CLKOUT 4 0 4 0 ns tuarpy ARDY Hold After CLKOUT 0 0 0 0 ns Switching Characteristics tpo Output Delay After CLKOUT 6 0 6 0 ns tuo Output Hold After CLKOUT 0 8 0 8 ns Output balls include 53 0 0 ADDRI19 1 AOE ARE HOLD SETUP PROGRAMMED READ ACCESS ACCESS EXTENDED IE 4 CYCLES 4 CYCLES 3 CYCLES lt tho 5 gt 1 a pe
33. CLKOUT 1 5 1 5 1 5 1 5 ns Data Hold After CLKOUT 0 8 0 8 0 8 0 8 ns Switching Characteristics CLKOUT Period 12 5 12 5 75 7 5 ns CLKOUT Width High 2 5 2 5 2 5 2 5 ns Width Low 2 5 2 5 2 5 2 5 ns tocapo Command Address Data Delay After CLKOUT 44 44 4 0 4 0 ns tucap Command Address Data Hold After CLKOUT 1 0 1 0 1 0 1 0 ns tospar Disable After CLKOUT 5 0 5 0 5 0 5 0 ns tenspar Data Enable After CLKOUT 0 0 0 0 0 0 0 0 ns The value is the inverse of the specification discussed in Table 14 and Table 17 Package type and reduced supply voltages affect the best case values listed here Command balls include SRAS SCAS SWE SDOM SMS SA10 SCKE DATA IN tospat 6 gt tucap ra DATA OUT COMMAND ADDRESS OUT NOTE COMMAND SRAS 5 5 SWE SDQM SMS SA10 SCKE Figure 17 SDRAM Interface Timing Rev PrE Page390f72 August 2008 ADSP BF522 523 524 525 526 527 External DMA Request Timing Table 26 and Figure 18 describe the External DMA Request operations Table 26 External DMA Request Timing 1 8 V Vopexr Voomem 2 5 3 3 V Parameter Min Max Min Max Unit Timing Parameters tor DMARx Asserted to CLKOUT High Setup 6 0 6 0 ns ton CLKOUT High to DMARx Deasserted Hold Ti
34. Disabled Off Sleep Operating Mode High Dynamic Power Savings The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core CCLK The PLL and system clock SCLK however continue to operate in this mode Typi cally an external event or RTC activity wakes up the processor When in the sleep mode asserting a wakeup enabled in the SIC_IWRx registers causes the processor to sense the value of the BYPASS bit in the PLL control register PLL_CTL If BYPASS is disabled the processor transitions to the full on mode If BYPASS is enabled the processor transitions to the active mode System DMA access to L1 memory is not supported in sleep mode Deep Sleep Operating Mode Maximum Dynamic Power Savings The deep sleep mode maximizes dynamic power savings by dis abling the clocks to the processor CCLK rend te all synchronous peripherals peripherals such as the RTC may still berunning internal resources or external memory This powered down mode can only be exited by assertion of the reset interrupt RESET or by an asynchronous interrupt generated by the RTC When in deep sleep mode an RTC asynchronous interrupt causes the proces sor to transition to the Active mode Assertion of RESET while in deep sleep mode causes the processor to transition to the full on mode Hibernate State Maximum Static Power Savings The hibernate
35. Figure 56 is equal to 2 The graphs of Figure 57 through Figure 64 show how output rise time varies with capacitance The delay and hold specifications given should be derated by a factor derived from these figures The graphs in these figures may not be linear outside the ranges shown TESTER PIN ELECTRONICS 500 VLoAD 1 500 impedance 252 D 34 04 1118 9 0 5 4000 4 NOTES THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED THE TRANSMISSION LINE TD IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT IF NECESSARY A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES Figure 56 Equivalent Device Loading for AC Measurements Includes All Fixtures Rev 61 of 72 Figure 57 Typical Rise and Fall Times 1096 9096 versus Load Capacitance for Driver A at Min coni AG Figure 58 Typical Rise and Fall Times 1096 9096 versus Load Capacitance for Driver at Vppex Vppmem August 2008 ADSP BF522 523 524 525 526 521 Preliminary Technical Data Figure 59 Typical Rise and Fall Times 1096 9096 versus Load Capacitan
36. INFORMATION PHYSICAL PROPERTY OR INTELLECTUAL PROPERTY WA D ALI Rev PrE Page220f72 August 2008 SIGNAL DESCRIPTIONS Signal definitions for the ADSP BF522 524 526 and ADSP BF523 525 527 processors are listed in Table 10 In order to maintain maximum function and reduce package size and ball count some balls have dual multiplexed functions In cases where ball function is reconfigurable the default state is shown in plain text while the alternate function is shown in italics All pins are three stated during and immediately after reset ADSP BF522 523 524 525 526 527 output pin CLKBUF On the external memory interface the stated of the pins that need pull ups or pull downs as noted in control and address lines are driven high with the exception of CLKOUT which toggles at the system clock rate If however the BR pin is asserted then the memory pins are also three All T O pins have their input buffers disabled with the exception with the exception of the external memory interface asynchro Table 10 nous and synchronous memory control and the buffered XTAL Table 10 Signal Descriptions Driver Signal Name Type Function Type EBIU ADDR19 1 Address Bus A DATA15 0 I O Bus ABE1 0 SDOM1 0 Byte Enables Data Mask A AMS3 0 Bank Select A ARDY Hardware Ready Control AOE Output Enable A ARE Read Enable A AWE Write Enable A SRAS i
37. Management ADSP BF522 524 526 ADSP BF523 525 527 Vovext 1 8 V Voor 2 5 3 3 V Vooo 1 8 V Vo 2 5 3 3 V Parameter Min Max Min Max Min Max Min Max Unit tmpios Input Valid to MDC Rising Edge Setup 11 5 11 5 10 10 ns MDC Rising Edge to Input Invalid Hold 11 5 11 5 10 10 ns MDC Falling Edge to Output Valid 25 25 25 25 ns MDC Falling Edge to Output Invalid Hold 1 1 1 1 ns MDC MDIO is a 2 wire serial bidirectional port for controlling one or mose externakRHYs MDC is an output clock whosegminimum period is programmable as a multiple of the system clock SCLK is ibidirectionalidata line a terxcLK ERx_CLK a terxcLkw gt ERxD3 0 ERxDV ERxER Figure 34 10 100 Ethernet MAC Controller Timing Receive Signal P 4 MII TxCLK lt teTxcLkw gt terxcLKoH ETxD3 0 ETxEN 4 8 terxcLkov Figure 35 10 100 Ethernet MAC Controller Timing Transmit Signal Rev PrE Page550f72 August 2008 ADSP BF522 523 524 525 526 527 m tREFCLK REF lt tREFCLKW ERxD1 0 ERxDV ERxER gt a treFcikis tREFCLKIH Figure 36 10 100 Ethernet MAC Controller Timing RMII Receive Signal tnEFCLK REF 1 1 f tREFCLKOH
38. SDRAM Raw Addres Str be 7 SCAS SDRAM Colum Address Stfobe SWE SDRAM Write Enable A SCKE SDRAM Clock Enable A CLKOUT SDRAM Clock Output B SA10 SDRAM A10 Signal A SMS SDRAM Bank Select A USB 2 0 HS OTG USB DP Data This ball should be pulled low when USB is unused or present USB DM Data This ball should be pulled low when USB is unused or not present F USB XI USB Crystal Input This ball should be pulled low when USB is unused not present USB XO USB Crystal Output This ball should be left unconnected when USB is unused F or not present USB ID USB OTG mode This ball should be pulled low when USB is unused or not present USB VREF USB voltage reference Connect to GND through a 0 1 capacitor or leave unconnected if USB is unused or not present USB RSET USB resistance set This ball should be left unconnected when USB is unused or not present USB_VBUS 5V USB VBUS USB_VBUS is an output only during initialization of USB OTG F session request pulses Host mode or OTG type A mode require that an external voltage source of 5V at 8mA or more per the OTG specification be applied to VBUS Other OTG modes require that this external voltage be disabled This ball should be pulled low when USB is unused or not present Rev PrE Page230f72 August 2008 ADSP BF522 523 524 525 526 527 Table 10 Signal Descriptions Continued
39. SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register Table 6 Example System Clock Ratios Example Frequency Ratios Signal Name Divider Ratio MHz SSEL3 0 VCO SCLK vco SCLK 0001 1 1 100 100 0110 6 1 300 50 1010 10 1 500 50 August 2008 ADSP BF522 523 524 525 526 527 The core clock CCLK frequency can also be dynamically pins of the reset configuration register sampled during power changed by means of the CSEL1 0 bits of the PLL_DIV register on resets and software initiated resets implement the modes Supported CCLK divider ratios are 1 2 4 and 8 as shown in shown in Table 8 Table 7 This programmable core clock capability is useful for fast core frequency modifications Table 8 Booting Modes Table 7 Core Clock Ratios 0 Description 0000 Idle No boot Frequency Ratios 0001 Boot from 8 or 16 bit external flash memory Signal Name Divider Ratio 0010 Boot from 16 bit asynchronous FIFO CSEL1 0 VCO CCLK VCO CCLK 0011 Boot from serial SPI memory EEPROM or flash 00 1 1 300 300 0100 Boot from SPI host device 01 2 1 300 150 0101 Boot from serial TWI memory EEPROM flash 10 4 1 500 125 0110 Boot from TWI host 11 8 1 200 25 0111 Boot from UARTO Host The maximum CCLK frequency not only depends on the part s 1000 Boot from UART1 Host speed grade
40. TRANSMIT INTERNAL CLOCK DATA TRANSMIT EXTERNAL CLOCK DRIVE SAMPLE DRIVE SAMPLE EDGE EDGE EDGE EDGE scLkiw tscLkew TSCLKx X TSCLKx 1 gt 4 4 1 4 gt turse TFSx TFSx 9 tppre gt DTx DTx gt 1 Y EDGE OR FALLING EDGE RSCLKx TSCEKx CAN BE USED AS THE ACTIVE EDGE Figure23 5 5 EXTERNAL RFSx IN MULTI CHANNEL MODE WITH MCE 1 DRIVE SAMPLE DRIVE RSCLKx tuorsEA DDTTE lt 1ST tprENLES 2ND BIT DTx loprirsg LATE EXTERNAL TFSx DRIVE SAMPLE DRIVE TSCLKx t tsrsen HOFSE I tpreNLFS t 15 BIT 2ND BIT tppriFsE lt Figure 24 External Late Frame Sync Rev PrE Page460f72 August 2008 ADSP BF522 523 524 525 526 527 Serial Peripheral Interface SPI Port Master Timing Table 32 and Figure 25 describe SPI port master operations Table 32 Serial Peripheral Interface SPI Port Master Timing ADSP BF522 524 526 ADSP BF523 525 527 1 8 Voor 22 5 3 3 V Vg 1 8 Vg 2 5 3 3 V Parameter Min Max Max Unit Timing Requirements tsspiom Data Inp
41. TWI host selects the slave with the unique ID Ox5F The processor replies with an acknowledgement and the host then downloads the boot stream The TWI host agent should comply with the Philips Bus Specification version 2 1 An multiplexer can be used to select one processor at a time when booting multiple processors from asingle TWI Boot from UARTO host on Port BMODE 0x7 Using an autobaud handshake sequence a boot stream for matted program is downloaded by the host The host selects a bit rate within the UART clocking capabilities When performing the autobaud the UART expects a 0x40 character eight bits data one start bit one stop bit no parity bit on the UARTORX pin to determine the bit rate The UART then replies with an acknowledgement composed of 4 bytes OxBF the value of UARTO DLL the value of UARTO then 0x00 The host can then download the boot stream To hold off the host the Blackfin processor signals the host with the boot host wait HW AIT signal Therefore the host must monitor HWAIT before every transmitted byte Boot from UARTI host on Port F BMODE 0x8 Same as BMODE 0x7 except that the UARTI port is used Rev PrE Page190f72 Boot from SDRAM BMODE 0xA This is a warm boot scenario where the boot kernel starts booting from address 0x0000 0010 The SDRAM is expected to contain a valid boot stream and the SDRAM controller must be configured by the OTP s
42. Voltage Regulation 15 ADSP BF522 524 526 Voltage Regulation 16 i eas 16 REVISION HISTORY 06 08 Revision PrE Numerous small clarifications and corrections throughout document Changes to voltage regulator in Block Diagram 1 Changes to processor comparison data Table 1 on Page 3 Changes to hibernate state description Page 15 Changes to voltage regulator description Page 16 Changes to booting modes description Page 18 Changes to signal descriptions Table 10 on Page 23 Added Lockbox Secure Technology Disclaimer Page 21 Rev PrE Page 2 of 72 Booting Modet eu tA rA IU ERN MEER 18 Instruction Set Description 20 Development aineas oM o 21 Designing an Emulator Compatible Processor Board Target 228 28445444543488 21 Related 21 Lockbox Secure Technology Disclaimer 21 22 26 Operating Conditions for ADSP BF522 524 526 26 Operating Conditions for ADSP BF523 525 527 28 Electrical Chara 30 Absolute Maximum Ratings oos eec areis 31 ESD SOUS VIDE RENI ERA 31 Packag
43. application code and supervisor O S kernel device drivers debuggers ISRs modes of opera tion allowing multiple levels of access to core processor resources The assembly language which takes advantage of the proces sor s unique architecture offers the following advantages e Seamlessly integrated DSP MCU features are optimized for both 8 bit and 16 bit operations multi issue load store modified Harvard architecture which supports two 16 bit MAC or four 8 bit ALU two load store two pointer updates per cycle All registers I O and memory are mapped into a unified 4G byte memory space providing a simplified program ming model Microcontroller features such as arbitrary bit and bit field manipulation insertion and extraction integer operations on 8 16 and 32 bit data types and separate user and supervisor stack pointers Code density enhancements which include intermixing of 16 bit and 32 bit instructions no mode switching no code segregation Frequently used instructions are encoded in 16 bits Rev 21 72 DEVELOPMENT TOOLS The processor is supported with a complete set of CROSSCORE software and hardware development tools including Analog Devices emulators and VisualDSP devel opment environment The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP BF522 524 526 and ADSP BF523 525 527 processors EZ KIT Li
44. as not to exceed the maximum core clock and system clock see Table 17 Table 16 describes phase locked loop operating conditions Table 15 Core Clock CCLK Requirements ADSP BF523 525 527 Processors All Speed Grades Parameter Internal Regulator Setting Max Unit Core Clock Frequency 1 14 V minimum 1 20V 600 MHz Core Clock Frequency Vppinr 1 093 V minimum 1 15 V 533 MHz Core Clock Frequency 0 95 V minimum 1 0V 400 MHz See the Ordering Guide on Page 72 Applies only to 600 MHz speed grades See the Ordering Guide on Page 72 Applies only to 533 MHz and 600 MHz speed grades See the Ordering Guide on Page 72 Table 16 Phase Locked Loop Operating Conditions Parameter Minimum Maximum Unit fuco Voltage Controlled Oscillator VCO Frequency 50 Speed Grade MHz See the Ordering Guide on Page 72 1 Table 17 ADSP BF523 525 527 MAYN Maximum SCUK Conditions 7 Parameter Vppext Vopmem 1 8 V Nominal Vopext Vppmem 2 5 V 3 3 V Nominal Unit CLKOUT SCLK Frequency Vy gt 1 14 V 100 133 MHz CLKOUT SCLK Frequency Voon lt 1 14 V 100 100 MHz If either or are operating at 1 8V nominal is constrained to 100MHz 2 must be less than or equal to and is subject to additional restrictions for SDRAM interface operation See Table 25 on Page 39 Rounded
45. by a programmable 0 5x to 64x multiplication factor bounded by specified minimum and maximum VCO frequencies The default multiplier is 10x but it can be modi fied by a software instruction sequence On the fly frequency changes can be effected by simply writing to the PLL_DIV register The maximum allowed CCLK and SCLK rates depend on the applied voltages and VCO is always permitted to run up to the frequency specified by the part s speed grade The CLKOUT pin reflects the SCLK frequency to the off chip world It is part of the SDRAM interface but it functions as a reference signal in other timing specifications as well While active by default it can be disabled using the EBIU SDGCTL and EBIU AMGCTL registers FINE ADJUSTMENT REQUIRES PLL SEQUENCING PLL 0 5xto 64x Figure 7 Frequency Modification Methods COARSE ADJUSTMENT ON THE FLY SCLK CLKIN SCLK lt CCLK SCLK lt 133 MHz All on chip peripherals are clocked by the system clock SCLK The system clock frequency is programmable by means of the SSEL3 0 bits of the DIV register The values programmed into the SSEL fields define a divide ratio between the PLL output VCO and the system clock SCLK divider values are 1 through 15 Table 6 illustrates typical system clock ratios Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of The
46. changed or operated below the speci fied frequency during normal operation This signal is connected to the processor s CLKIN pin When an external clock is used the XTAL pin must be left unconnected August 2008 ADSP BF522 523 524 525 526 527 Alternatively because the processor includes an on chip oscilla tor circuit an external crystal may be used For fundamental frequency operation use the circuit shown in Figure 6 A paral lel resonant fundamental frequency microprocessor grade crystal is connected across the CLKIN and XTAL pins The on chip resistance between CLKIN and the XTAL pin is in the 500 kQ range Further parallel resistors are typically not recom mended The two capacitors and the series resistor shown in Figure 6 fine tune phase and amplitude of the sine frequency The capacitor and resistor values shown in Figure 6 are typical values only The capacitor values are dependent upon the crystal manufacturers load capacitance recommendations and the PCB physical layout The resistor value depends on the drive level specified by the crystal manufacturer The user should verify the customized values based on careful investigations on multiple devices over temperature range BLACKFIN cLkouT lt TO PLL CIRCUITRY XTAL 1 OPERATION 18 pF 18 pF l y y 7 NOTE VALUES MARKED WITH MUST BE CUSTOMIZED DEPENDING ON THE CRYSTAL AND LAYOUT PLEASE ANA
47. con troller include single linear buffer that stops upon completion A circular auto refreshing buffer that interrupts on each full or fractionally full buffer 1 D or 2 D DMA using a linked list of descriptors 2 D DMA using an array of descriptors specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels there are two memory DMA channels provided for transfers between the various menrori s bobo system This enables trans fers of blocks of data betyeenfany of the memories including external SDRAM ROM SRAM and flash memory with mini mal processor intervention Memory DMA transfers can be controlled by a very flexible descriptor based methodology or by a standard register based autobuffer mechanism The processor also has an external DMA controller capability via dual external DMA request pins when used in conjunction with the external bus interface unit EBIU This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communications peripherals such as USB 2 0 It allows control of the number of data transfers for memory DMA The number of transfers per edge is program mable This feature can be programmed to allow memory DMA to have an increased priority on the external bus relative to the core HOST DMA PORT The host port interface allows an external host to be a DMA master to transfer data
48. designed to minimize supervi sion bus use or message processing by the rest of the processor system Some standard features are Support of MII and protocols for external PHYs Full duplex and half duplex modes Data framing and encapsulation generation and detection of preamble length padding and FCS Media access management in half duplex operation col lision and contention handling including control of retransmission of collision frames and of back off timing Flow centrol insfull duplex dperation generation and detection of PAUSE fraies Station management generation of MDC MDIO frames for read write access to PHY registers SCLK operating range down to 25 MHz active and sleep operating modes Internal loopback from Tx to Rx Some advanced features are Buffered crystal output to external PHY for support ofa single crystal system e Automatic checksum computation of IP header and IP payload fields of Rx frames Independent 32 bit descriptor driven Rx and Tx DMA channels Frame status delivery to memory via DMA including frame completion semaphores for efficient buffer queue management in software Tx DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations Convenient frame alignment modes support even 32 bit alignment of encapsulated Rx or Tx IP packet data in mem ory after the 14 byte MAC header A
49. events by writ ing the appropriate values into the interrupt assignment registers SIC IARx Table 3 describes the inputs into the SIC and the default mappingsinto the a Table 3 System Interrupt AN YAY SIC General Purpose Default Peripheral Interrupt Event Interrupt at RESET Peripheral Interrupt Core Interrupt ID SIC Registers PLL Wakeup Interrupt IVG7 0 0 IARO IMASKO ISRO IWRO DMA Error 0 generic IVG7 1 0 IMASKO ISRO IWRO DMARO Block Interrupt IVG7 2 0 IARO IMASKO ISRO IWRO DMARI Block Interrupt IVG7 3 0 IARO IMASKO ISRO IWRO DMARO Overflow Error IVG7 4 0 IARO IMASKO ISRO IWRO DMARI Overflow Error IVG7 5 0 IARO IMASKO ISRO IWRO Error IVG7 6 0 IARO IMASKO ISRO IWRO MAC Status IVG7 7 0 IARO 1 ISRO IWRO SPORTO Status IVG7 8 0 IAR1 1 ISRO IWRO SPORTI Status IVG7 9 0 IAR1 1 ISRO IWRO Reserved IVG7 10 0 IAR1 1 ISRO IWRO Reserved IVG7 11 0 IAR1 1 ISRO IWRO UARTO Status IVG7 12 0 IAR1 1 ISRO IWRO UART1 Status IVG7 13 0 IAR1 1 ISRO IWRO RIC IVG8 14 1 IAR1 1 ISRO IWRO DMA Channel 0 PPI NFC IVG8 15 1 IAR1 IMASKO ISRO IWRO DMA 3 Channel SPORTO RX IVG9 16 2 IAR2 IMASKO ISRO IWRO DMA 4 Channel SPORTO TX 69 17 2 IAR2 IMASKO ISRO IWRO 5 Channel 5 1 IVG9 18 2 IAR2 IMASKO ISRO IWRO 6 Channel SPORT TX IVG9 19 2 IAR2
50. for TMRx signals in width capture and external clock modes They also apply to the PF15 or PPI_CLK signals PWM output mode Either a valid setup and hold time or a valid pulse width is sufficient 48 tosresynchronize programmable flag inputs a INN D CLKOUT MRx OUTPUT luro MRx INPUT Figure 29 Timer Cycle Timing Rev PrE Page500f72 August 2008 Timer Clock Timing ADSP BF522 523 524 525 526 527 Table 36 and Figure 30 describe timer clock timing Table 36 Timer Clock Timing 18V Vopr 2 5 3 3 V Parameter Min Max Min Max Unit Switching Characteristic tropp Timer Output Update Delay After PPI_CLK High 12 64 12 64 ns PPI CLK tropp MRx OUTPUT Figure 30 Timer Clock Timing Up Down Counter Rotary Encoder Timing Table 37 Up Down Counter Rotary Encoder Timing Vy 1 8 V 2 5 3 3 V Parameter Min Max Min Max Unit Timing Requirements ST a tweount Up Down Counter Input Pulse Width 1 ns tas Counter Input Setup Time Before CLKOUT Low 4 0 4 0 ns Counter Input Hold Time After CLKOUT Low1 4 0 4 0 ns Either a valid setup and hold time or a valid pulse width is sufficient There is no need to resynchronize counter inputs CLKOUT CUD CDG CZM twcount Figure 31 Up Down Counter Rotary Encoder Timing Rev PrE Page510f72 August 2008
51. goal of avoiding bad blocks and equally distributing memory accesses across all address locations Hardware features of the NFC include Support for page program page read and block erase of NAND flash devices with accesses aligned to page boundaries Error checking and correction ECC hardware that facili tates error detection and correction A single 8 bit external bus interface for commands addresses and data Support for SLC single level cell NAND flash devices unlimited in size with page sizes of 256 and 512 bytes Larger page sizes can be supported in software e Capability of releasing external bus interface pins during long accesses Support for internal bus requests of 16 bits DMA engine to transfer data between internal memory and NAND flash device One Time Programmable Memory The processor has 64K bits of one time programmable non vol atile memory that can be programmed by the developer only one time It includes the array and logic to support read access and programming Additionally its pages can be write protected Rev PrE Page60f72 OTP enables developers to store both public and private data on chip In addition to storing public and private key data for applications requiring security it also allows developers to store completely user definable data such as customer ID product ID MAC address etc Hence generic parts can be shipped which are then programmed and protected
52. in and out of the device The host device masters the transactions and the Blackfin is the DMA slave The host port is enabled through the interface Once enabled the DMA is controlled by the external host which can then program the DMA to send receive data to any valid inter nal or external memory location The host port interface controller has the following features Allows external master to configure read write data transfers and read port status e Uses asynchronous memory protocol for external interface August 2008 ADSP BF522 523 524 525 526 527 8 16 bit external data interface to host device Half duplex operation Little big endian data transfer Acknowledge mode allows flow control on host transactions Interrupt mode guarantees a burst of FIFO depth host transactions REAL TIME CLOCK The real time clock RTC provides a robust set of digital watch features including current time stopwatch and alarm The RTC is clocked by a 32 768 kHz crystal external to the Blackfin processor The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state The RTC provides several programmable interrupt options including interrupt per second minute hour or day clock ticks interrupt on programmable stopwatch countdown or interrupt at a pro grammed alarm time The 32 768 kHz input clo
53. of data Up to three frame synchronization signals are also pro vided In ITU R 656 mode the PPI provides half duplex bidirectional transfer of 8 or 10 bit video data Additionally on chip decode of embedded start of line SOL and start of field SOF preamble packets is supported General Purpose Mode Descriptions The general purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications Three distinct submodes are supported 1 Input mode Frame syncs and data are inputs into the PPI 2 Frame capture mode Frame syncs are outputs from the PPI but data are inputs 3 Output mode Frame syncs and data are outputs from the Input Mode Input mode is intended for ADC applications as well as video communication with hardware signaling In its simplest form PPI FSI is an external frame sync input that controls when to read data The DELAY allows for a delay in PPI CLK cycles between reception of this frame sync and the initiation of data reads The number of input data samples is August 2008 ADSP BF522 523 524 525 526 527 user programmable and defined by the contents of the PPI_COUNT register The PPI supports 8 bit and 10 bit through 16 bit data programmable in the PPI CONTROL register Frame Capture Mode Frame capture mode allows the video source s to act as a slave for frame capture for example The ADSP BF522 524 526 and ADSP BF523
54. see Page 72 it also depends on the applied Vppinr 1001 Reserved voltage See Table 12 and Table 15 for details The maximal sys 1010 Boot from SDRAM rate T on the p 2 m 1011 Boot from memory gt gt t Table 17 d ld M QM LE 1100 Boot from 8 bit NAND flash via using PORTF data pins BOOTING MODES 1101 Boot from 8 bit NAND flash The processor has several mechanisms listed in Table 8 for NEC using PORTH data pins automatically loading internal and external memory after a 1110 Boot from 16 Bit Host DMA reset The boot mode is defined by four BMODE input pins 1111 Boot from 8 Bit Host dedicated to this purpose afe YNES 7 modes In master boot modes the pro essor agtively loads data boot mode BMQDE 0x0 In this mode the from parallel or serial memories In slave boot modes the pro processor goes into idle The idle boot mode helps recover cessor receives data from external host devices from illegal operating modes such as when the OTP mem The boot modes listed in Table 8 provide a number of mecha ory has been misconfigured nisms for automatically loading the processor s internal and Boot from 8 bit or 16 bit external flash memory external memories after a reset By default all boot modes use BMODE 0x1 In this mode the boot kernel loads the the slowest meaningful configuration settings Default settings first block header from address 0x2
55. watchdog timer a Host DMA HOSTDP interface and a par allel peripheral interface PPI PROCESSOR PERIPHERALS The ADSP BF522 524 526 and ADSP BF523 525 527 proces sors contain a rich set of peripherals connected to the core via several high bandwidth buses providing flexibility in system configuration as well as excellent overall system performance see the block diagram on Page 1 These Blackfin processors contain dedicated network communication modules and high speed serial and parallel ports an interrupt controller for flexi ble management of interrupts from the on chip peripherals or external sources and power management control functions to tailor the performance and power characteristics of the proces sor and system to many application scenarios All of the peripherals except for the general purpose I O TWI real time clock and timers are supported by a flexible DMA structure There are also separate memory DMA channels dedi cated to data transfers between the processor s various memory spaces including external SDRAM and asynchronous memory Multiple on chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on chip and external peripherals August 2008 ADSP BF522 523 524 525 526 527 The ADSP BF523 525 527 processors include an on chip volt age regulator in support of the processor s dynamic power management capability The voltage r
56. 0 150 0 0 5 1 0 1 5 2 0 2 5 3 0 SOURCE VOLTAGE V Figure 51 Drive Current F Low Vppexy August 2008 ADSP BF522 523 524 525 526 527 Output Enable Time Measurement at Output balls are considered to be enabled when they have made a transition from a high impedance state to the point when they 100 start driving The output enable time tj is the interval from the point when E reference signal reaches a high or low voltage level to the point E 4 2 TBD when the output starts driving as shown on the right side of o Figure 55 2 o 50 o o 100 ipis 5 MEASURED 150 0 0 5 1 0 1 5 2 0 2 5 3 0 tois tena SOURCE VOLTAGE V VoH MEASURED Von MEASURED AV Vrgie HIGH Figure 52 Drive Current F High Vppex Vppmew MEASURED AV Vraie LOW oL VoLtMEASURED MEASURED POWER DISSIPATION Total power dissipation has two components one due to inter nal circuitry and one due to the switching of external OUTPUT STOPS DRIVING OUTPUT STARTS DRIVING output drivers P See the ADSP BF52x Blackfin Processor Hardware Reference Manual for definitions of the various operating modes and for Figure 55 Output Enable Disable instructions on how to minimize system power HIGH IMPEDANCE STATE The time tg measurep 1 the intezval from when th
57. 0 0 0 0 0 0 0 ns Data Disable Delay from External TSCLKx 10 0 10 0 10 0 10 0 ns totem Data Enable Delay from Internal TSCLKx 2 0 2 0 2 0 2 0 ns Data Disable Delay from Internal TSCLKx 3 0 3 0 3 0 3 0 ns Referenced to drive edge Table 31 External Late Frame Sync ADSP BF522 524 526 ADSP BF523 525 527 Vopext 1 8 V 2 5 3 3 V Vg 1 8 V Vo 2 5 3 3 V Parameter Min Max Max Min Max Max Unit Switching Characteristics toptirse Data Delay from Late External TFSx 10 0 10 0 10 0 10 0 ns or External RFSx in multi channel mode with 0 Data Enable from Late FS or in multi channel mode with 0 0 0 0 0 0 0 0 ns MED 0 When in multi channel mode TFSx enable and TFSx valid follow and TDDTLESE 2 If external RFSx TFSx setup to RSCLKx TSGLKx gt 2 then 17 and apply otherwisertppmremandstoreny sap Rev PrE Page450f72 August 2008 ply ADSP BF522 523 524 525 526 527 DATA RECEIVE INTERNAL CLOCK DATA RECEIVE EXTERNAL CLOCK DRIVE SAMPLE DRIVE SAMPLE EDGE EDGE EDGE EDGE tscukiw 3 tscLkEw RSCLKx RSCLKx RFSx RFSx t tspgi tupni gt 4 5 gt tupnE DRx DRx NOTE EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE DATA
58. 0 U2 DATA3 AB16 51 B12 PF6 H7 L7 VpowtM P7 Vppmem 7 Voomem 17 B13 PF7 H8 Vppir L8 Vppir P8 Vppnr U8 Voomem 18 CLKOUT B14 PH3 Vppir L9 GND P9 GND U9 Vpomem AB19 CLKBUF B15 PF10 Vopr L10 GND P10 GND U10 Vbomem 20 USB_VBUS B16 PF8 H11 L11 GND P11 GND U11 Vopww 21 USB DM B17 PF11 H12 L12 GND P12 GND 012 Vppmem AB22 VRsg Vppexr B18 PF12 H13 L13 GND P13 GND U13 Vopww 23 USB B19 PF13 H14 L14 GND P14 GND U14 GND B20 NC H15 Vppir L15 GND P15 GND U15 Vbomem 2 ADDR14 B21 NC H16 116 Vppir P16 U16 Voomem ADDR12 B22 SCL H17 GND 117 Vppga 17 Vppexr 017 Vopexr ADDR10 NOTE In this table BOLD TYPE indicates the sole signal function for that ball on ADSP BF522 524 526 processors For ADSP BF52xC compatibility connect this ball to Rev PrE Page650f72 August 2008 CN co CN LC CN CN LCD CN N N LO LL E a e co lt EEN PED lt 4 Ow mas A A Bo i o Eg 25 o n 2 2 n Ww o 5 oD d D s H 3 E o Figure 66 shows the top view of the BC guration 2 5 ball confi A1 BALL PAD CORNER
59. 000 0000 and depend can be altered via the initialization code feature at boot time or ing on instructions contained in the header the boot by proper OTP programming at pre boot time The BMODE kernel performs an 8 or 16 bit boot or starts program exe cution at the address provided by the header By default all configuration settings are set for the slowest device possible 3 cyde hold time 15 cycle R W access times 4 cycle setup The ARDY is not enabled by default but it can be enabled through OTP programming Similarly all interface behav ior and timings can be customized through OTP programming This includes activation of burst mode or page mode operation In this mode all asynchronous interface signals are enabled at the port muxing level Boot from 16 bit asynchronous FIFO BMODE 0x2 In this mode the boot kernel starts booting from address 0x2030 0000 Every 16 bit word that the boot kernel has to read from the FIFO must be requested by placing a low pulse on the DMARI pin Boot from serial SPI memory EEPROM or flash BMODE 0x3 8 16 24 or 32 bit addressable devices are supported The processor uses the PG1 GPIO pin to select a single SPI EEPROM flash device and sub Rev PrE Page180f72 August 2008 ADSP BF522 523 524 525 526 527 mits a read command and successive address bytes 0x00 until a valid 8 16 24 or 32 bit addressable device is detected Pull up resistors are required on
60. 1 K16 XTAL P23 ADDR18 AA1 GND Jy Uu 14 4 62 3 H1 VES ADDR19 GND 12 Ris JPas4 FI Kt 716 AMSO AC17 GND J13 GND T22 PG TMS 12 M8 AMST AB16 GND J14 GND 5 02 TRST K2 16 AMS2 AC16 GND J15 GND AC23 PG6 C2 USB DM 21 N8 AMS3 AB15 GND 15 PG7 1058 DP 22 N16 AOE AC15 GND K10 A16 PG8 USB ID Y22 P8 ARDY AC14 GND K11 NC 17 PG9 82 USB RSET AC21 Vpge P16 ARE AB17 GND K12 NC A18 PG10 B4 10858 VBUS 20 R8 AWE AB14 GND K13 INC 19 PG11 USB VREF AC22 Vppw R16 BMODEO G2 GND 14 NC 21 PG12 2 USB 23 T8 BMODE1 2 K15 INC A22 PG13 05 23 T9 BMODE2 L9 B20 14 4 G7 110 BMODE3 GND L10 INC B21 PG15 5 G8 111 CLKBUF AB19 GND L11 INC 823 PHO 11 G9 112 CLKIN R23 GND 112 INC C23 PH 12 G10 13 CLKOUT AB18 GND 113 022 PH2 13 611 14 DATAO GND 114 D23 PH3 814 G12 15 DATA1 V2 15 INC E22 PH4 A14 G13 T16 DATA2 W1 GND M9 INC E23 5 K23 G14 27 DATA3 U2 GND M10 INC F22 PH6 K22 G15 7 DATA4 V1 M11 NC F23 PH7 123 H7 17 DATAS 01 GND M12 NC G22 PH8 122 17 Voomem 7 DATA6 T2 M13 INC H23
61. 20 AOE W10 BMODE1 B7 G13 19 51 P1 W11 ADDR18 B8 614 Vppwr K20 CLKOUT P2 PG2 W12 ADDRI6 B9 5 G19 SS PG 7 P7 W13 ADDR14 B10 PH6 G20 Vppuse L2 PG8 P8 W14 ADDR12 11 PH7 L7 Vppea P9 W15 ADDR10 B12 PH9 H2 PG14 18 10 Vopmem W16 ADDR8 B13 11 H7 L9 GND 11 Vopmem W17 ADDR6 B14 12 H8 110 GND 12 Vppwr W18 ADDR4 15 PH13 H9 GND 11 GND 13 Vppwr W19 ADDR2 16 14 H10 GND 12 GND 14 Vppwr W20 1 B17 15 H11 GND 113 GND P19 ARDY 1 GND B18 RESET 12 GND 114 P20 5 Y2 DATA12 NOTE In this table BOLD TYPE indicates the sole signal function for that ball on ADSP BF522 524 526 processors Rev PrE Page 68 of 72 August 2008 ADSP BF522 523 524 525 526 527 Figure 67 shows the top view of the CSP_BGA ball configura tion Figure 68 shows the bottom view of the CSP_BGA ball configuration A1 BALL PAD CORNER 000000 0000008 B oo 000006066906 oo oo J K oo L oo M N P R T VDDINT GND U oo v
62. 33 Serial Peripheral Interface SPI Port Slave Timing ADSP BF522 524 526 ADSP BF523 525 527 1 8V Vopecr 22 5 3 3 V Vg 1 8V Voon 2 5 3 3 V Parameter Min Min Max Min Max Min Unit Timing Requirements tspicus Serial Clock High Period 2 1 5 2 1 5 2 1 5 2 X 1 5 ns tspicis Serial Clock Low Period 2 1 5 2 1 5 2X 1 5 2 1 5 ns Serial Clock Period 4 4 X 4x 4 X ns tups Last SCK Edge to SPISS Not Asserted 2 X tsak 2 X tak 2 2 ns tserrps Sequential Transfer Delay 2Xtsck 2 2 X 2Xtsck ns tsosa SPISS Assertion to First SCK Edge 2X 2 2 X 2 ns Data Input Valid to SCK Edge Data Input Setup 1 6 1 6 1 6 1 6 ns tuspip SCK Sampling Edge to Data Input Invalid 1 6 1 6 1 6 1 6 ns Switching Characteristics SPISS Assertion to Data Out Active 0 12 010 12 0 0 10 3 0 10 3 ns tpspui SPISS Deassertion to Data High Impedance 0 85 0 8 5 0 8 10 8 Ins tppseip SCK Edge to Data Out Valid Data Out Delay 10 10 10 10 ns tupseip SCK Edge to Data Out Invalid Data Out Hold 0 0 0 0 ns aNFUT 7 t t SPICHS ee 4 tips tspitps lt Hh lt j H SCKx CPOL 0 INPUT tspsci tspicus SCKx 1 INPUT t topspip
63. 3V and is 11ns at 1 8V gt ND CE ND CLE tCLHWL tALLWL A mt TALH ND ALE Figure 12 NAND Flash Controller Interface Timing Command Write Cycle Rev PrE Page360f72 August 2008 ADSP BF522 523 524 525 526 527 me CWL ND CE i tAaLHWL_ fALH taLHWL_ tALH EH 9 4 9 ES twc gt tDWS tpws tpWH e a i Le C WL D gt a 7 ND CE 1 85 ND CLE tALHWL gt ND ALE ee tww Figure 14 NAND Flash Controller Interface Timing Data Write Operation Rev PrE Page370f72 August 2008 ADSP BF522 523 524 525 526 527 ia CRL 1 4 gt e a lt _ H twHWL lt tpws 08 fDWH e a Figure 16 NAND Flash Controller Interface Timing Write Followed by Read Operation Rev PrE Page380f72 August 2008 ADSP BF522 523 524 525 526 527 SDRAM Interface Timing Table 25 SDRAM Interface Timing ADSP BF522 524 526 ADSP BF523 525 527 1 8 V 2 5 3 3 V 1 8 V 2 5 3 3 V Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements tssoar Data Setup Before
64. 525 527 processors control when to read from the video source s PPI_FS1 is an HSYNC output and PPI FS2 isa VSYNC output Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs Typically a single frame sync is appropriate for data converter applications whereas two or three frame syncs could be used for sending video with hard ware signaling ITU R 656 Mode Descriptions The ITU R 656 modes of the PPI are intended to suit a wide variety of video capture processing and transmission applica tions Three distinct submodes are supported 1 Active video only mode 2 Vertical blanking only mode 3 Entire field mode Active Video Mode Active video only mode is used VM fhelactivevideo pot tion ofa field is of interest and not any of the blanking intervals The PPI does not read in any data between the end of active video EAV and start of active video SAV preamble symbols or any data present during the vertical blanking intervals In this mode the control byte sequences are not stored to memory they are filtered by the PPI After synchronizing to the start of Field 1 the PPI ignores incoming samples until it sees an SAV code The user specifies the number of active video lines per frame in PPI COUNT register Vertical Blanking Interval Mode In this mode the PPI only transfers vertical blanking interval VBI data Entire Field Mode In this mode the entire inc
65. 527 processors 3 3 V tolerant always accept up to 3 6 V maximum Voltage compliance on outputs Von is limited by the supply voltage 7 Parameter value applies to all input and bidirectional balls except USB DP 058 DM USB VBUS SDA and SCL The min and max value vary with the selection in the TWI_DT field ofthe NONGPIO DRIVE register See Vgusrw min and max values in Table 11 SDA and SCL are pulled up to See Table 11 Table 11 shows settings for TWI_DT in the NONGPIO DRIVE register Set this register prior to using the TWI port Table 11 TWI DT Field Selections and TWI DT Vppexr Nominal Vsusrw Minimum Nominal Veustw Maximum Unit 000 default 3 3 2 97 3 3 3 63 V 001 1 8 1 27 1 8 2 35 V 010 2 5 2 97 3 3 3 63 V 011 1 8 2 97 3 3 3 63 V 100 3 3 4 5 5 5 5 V 101 1 8 2 25 2 5 2 75 V 110 2 5 2 25 2 5 2 75 V 111 reserved Rev PrE Page270f72 August 2008 ADSP BF522 523 524 525 526 527 ADSP BF522 524 526 Clock Related Operating Conditions Table 12 describes the core clock timing requirements for the ADSP BF522 524 526 processors Take care in selecting MSEL SSEL and CSEL ratios so as not to exceed the maximum core clock and system clock see Table 14 Table 13 describes phase locked loop operating conditions Table 12 Core Clock CCLK Requirements ADSP BF522 524 526 Processors
66. 7 proces sors are completely code compatible with other Blackfin processors The ADSP BF523 525 527 processors offer perfor mance up to 600 MHz The ADSP BF522 524 526 processors offer performance up to 400 MHz and reduced static power consumption Differences with respect to peripheral combina tions are shown in Table 1 Table 1 Processor Comparison N m wu NIN AN wu A A A A Feature Host 1 1 1 1 1 1 058 1 1 1 1 Ethernet MAC z Internal Voltage Regulator 1 TWI 1 1 1 1 1 1 SPORTs 2 2 2 2 2 2 5 2 2 2 2 2 2 SPI 1 1 1 1 1 1 GP Timers 8 8 818 8 8 Watchdog Timers 1 1 1 1 1 RIC 1 1 1 1 1 1 Parallel Peripheral Interface 1 1 1 1 1 GPIOs 48 48 48 48 48 48 L1 Instruction SRAM 48K 48K 48K 48K 48K 48K L1 Instruction SRAM Cache 16K 16K 16 16K 16K 16K 11 Data 5 32K 32K 32K 32K 32K 32K 5 L1 Data SRAM Cache 32K 32K 32K 32K 32K 32K gt 11 Scratchpad 4K 4K 4 4K 4K 4K L3 Boot ROM 32K 32K 32K 32K 32K 32K Maximum Speed Grade 400 MHz 600 MHz Maximum System Clock Speed 80 MHz 133 MHz Package Options 289 Ball CSP_BGA 208 Ball CSP_BGA Maximum speed grade is not available with every possible SCLK selection Rev PrE Page 3 of 72 By integrating a rich set of industry leading system
67. A1 4000 OxFFA1 0000 1 C000 OxFFAO 0000 OxFF90 8000 OxFF90 4000 OxFF90 0000 OxFF80 8000 gt OxFF80 4000 OxFF80 0000 gt T 8000 0 00 0000 25 0 2040 0000 9 0 2030 0000 9 0 2020 0000 0 2010 0000 0 2000 0000 0x08 00 0000 gt Figure 3 Internal External Memory Map OxFFAO 8000 INTERNAL MEMORY MAP EXTERNAL MEMORY MAP 0 0000 0000 Internal On Chip Memory The processor has three blocks of on chip memory providing high bandwidth access to the core The first block is the L1 instruction memory consisting of 64K bytes SRAM of which 16K bytes can be configured as a four way set associative cache This memory is accessed at full processor speed The second on chip memory block is the L1 data memory con sisting of up to two banks of up to 32K bytes each Each memory bank is configurable offering both cache and SRAM functional ity This memory block is accessed at full processor speed The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories but is only accessible as data SRAM and cannot be configured as cache memory August 2008 ADSP BF522 523 524 525 526 527 External Off Chip Memory External memory is accessed via the EBIU This 16 bit interface provides a glueless connection to a bank of synchronous DRAM SDRAM as w
68. ANALOG DEVICES Blackfin Embedded Processor ADSP BF522 523 524 525 526 527 FEATURES Up to 600 MHz high performance Blackfin processor Two 16 bit MACs two 40 bit ALUs four 8 bit video ALUs 40 bit shifter RISC like register and instruction model for ease of programming and compiler friendly support Advanced debug trace and performance monitoring Accepts a wide range of supply voltages for internal and I O operations See Operating Conditions for ADSP BF523 525 527 on Page 29 and Operating Condi tions for ADSP BF522 524 526 on Page 27 Programmable on chip voltage regulator ADSP BF523 525 527 processors only 289 ball 12 mm x 12 mm and 208 ball 17 mm x 17 mm CSP_BGA packages MEMORY 132K bytes of on chip memory See Table 1 on Page 3 for L1 and L3 memory size details External memory controller with glueless support for SDRAM and asynchronous 8 bit and 16 bit memories Flexible booting options from external flash SPI and TWI memory or from host deviceS including SPI Wi and UART Code Security with Lockbox Secure Technology One Time Programmable OTP Memory Memory management unit providing memory protection WATCHDOG TIMER JTAG TEST AND EMULATION VOLTAGE REGULATOR HALE BACK 2 1 1 11 INSTRUCTION MEMORY 1j ACCESS BUS INTERRUPT CONTROLLER DMA CONTROLLER DCB lt gt DEB EXTERNAL PORT BOOT a FLASH SDRAM CONTROL ROM REGULAT
69. CAS SWE SCKE CLKOUT 5410 SMS SCL SDA PF15 0 15 0 15 0 TDO EMU gt TMS TDI tprpo TDO SYSTEM INPUTS SYSTEM OUTPUTS Figure 40 JTAG Port Timing Rev PrE Page570f72 August 2008 ADSP BF522 523 524 525 526 527 OUTPUT DRIVE CURRENTS Figure 41 through Figure 52 show typical current voltage char 150 acteristics for the output drivers of the ADSP BF523 525 527 and ADSP BF522 524 526 processors The curves represent the 100 current drive capability of the output drivers as a function of m output voltage See Table 10 on Page 23 for information about s which driver type corresponds to a particular ball 2 o 150 amp 50 o o 100 100 lt 0 etg 0 5 1 0 15 2 0 2 5 3 0 5 1 1 TBD SOURCE VOLTAGE V o Figure 43 Drive Current Low amp 50 2 o o 100 150 0 0 5 1 0 1 5 2 0 2 5 3 0 SOURCE VOLTAGE V Figure 41 Drive Current A Low Vppexy 2 1 5 o 150 2 o o 100 f 50 5 0 0 5 1 0 1 5 2 0 25 3 0 2 TBD SOURCE VOLTAGE V tr 2 Figure 44 Drive Current B High o T 50 o o 150 100 150 0 0
70. G10 ADDR18 W11 GND B20 PF3 01 PH9 12 Vppex G11 ADDR19 11 GND H9 PF4 02 10 13 Vppe H7 AMSO J19 JGND H10 5 B13 H8 51 K19 GND H11 PF6 C2 12 14 7 52 M19 GND H12 PF7 B1 13 15 J8 AMS3 120 GND H13 PF8 B2 14 16 Vppex K7 AOE N20 GND J9 PF9 A2 15 17 Vppex K8 ARDY P19 GND J10 PF10 B3 PPI 62 L7 ARE M20 GND J11 PF11 PPI FST TMRO F2 Voowr G12 AWE N19 GND J12 12 B5 RESET 18 G13 BMODEO Y10 GND J13 1 A5 A14 G14 BMODE1 W10 GND Ko 14 B6 A15 H14 BMODE2 Y9 GND K10 PF15 SA10 019 J14 BMODE3 W9 GND K11 PGO R2 SCAS 020 K14 CLKBUF C19 GND K12 PG1 P1 5 P20 L14 CLKIN A11 GND K13 PG2 P2 A4 M14 CLKOUT K20 GND 19 ISDA B4 Vopir N14 DATAO Y8 GND 110 PG4 2 SMS R19 P12 8 GND 111 5 1 SRAS T19 P13 NOTE In this table BOLD TYPE indicates the sole signal function for that ball on ADSP BF522 524 526 processors Rev PrE Page670f72 August 2008 ADSP BF522 523 524 525 526 527 Table 52 208 Ball CSP_BGA Ball Assignment Numerically by Ball Number Ball Signal Ball Signal Ball Signal Signal Ball Signal Ball Signal No No No No No No Al GND 19 NMI H13 GND
71. IMASKO ISRO IWRO TWI IVG10 20 3 2 IMASKO ISRO IWRO Rev PrE Page70f72 August 2008 ADSP BF522 523 524 525 526 527 Table 3 System Interrupt Controller SIC Continued General Purpose Default Peripheral Interrupt Event Interrupt at RESET Peripheral Interrupt ID Core Interrupt ID SIC Registers DMA 7 Channel SPI IVG10 21 3 IAR2 IMASKO ISRO IWRO 8 Channel UARTO IVG10 22 3 IAR2 IMASKO ISRO IWRO DMA Channel UARTO TX IVG10 23 3 IAR2 IMASKO ISRO IWRO DMA10 Channel UART1 IVG10 24 3 IAR3 5 ISRO IWRO 11 Channel UART1 TX IVG10 25 3 IAR3 5 ISRO IWRO OTP Memory Interrupt IVG11 26 4 IAR3 5 ISRO IWRO GP Counter IVG11 27 4 IAR3 5 ISRO IWRO Channel MAC RX HOSTDP IVG11 28 4 IAR3 5 ISRO IWRO Port H Interrupt A IVG11 29 4 IAR3 5 ISRO IWRO DMA2 Channel MAC TX NFC IVG11 30 4 IAR3 5 ISRO IWRO Port H Interrupt B IVG11 31 4 IAR3 5 ISRO IWRO Timer 0 IVG12 32 5 1 4 IMASK1 1581 1 Timer 1 IVG12 33 5 IARA IMASK1 1581 1 Timer 2 IVG12 34 5 IARA IMASK1 1581 1 Timer 3 IVG12 35 5 IARA IMASK1 1581 1 Timer 4 IVG12 36 5 IARA IMASK1 1581 1 Timer 5 IVG12 37 5 IARA IMASK1 1581 1 Timer 6 IVG12 38 5 IARA IMASK1 1581 1 Timer 7 IVG12 39 5 IARA IMASK1 1581 1 Port G Interrupt
72. LYZE CAREFULLY Figure 6 External Crystal Connections A third overtone crystal can be used for frequencies above 25 MHz The circuit is then modified to ensure crystal operation only at the third overtone by adding a tuned inductor circuit as shown in Figure 6 A design procedure for third overtone oper ation is discussed in detail in application note EE 168 Using Third Overtone Crystals with the ADSP 218x DSP on the Analog Devices website www analog com use site search on EE 168 The pin is an output pin which is a buffered version of the input clock This pin is particularly useful in Ethernet applications to limit the number of required clock sources in the system In this type of application a single 25 MHz or 50 MHz crystal may be applied directly to the processor The 25 MHz or 50 MHz output of CLKBUF can then be connected to an exter nal Ethernet MII or RMII PHY device If instead of a crystal an external oscillator is used at CLKIN CLKBUF will not have the 40 60 duty cycle required by some devices The CLKBUF output is active by default and can be disabled for power savings rea sons using the register Rev 17 72 The Blackfin core runs at a different clock rate than the on chip peripherals As shown in Figure 7 the core clock CCLK and system peripheral clock SCLK are derived from the input clock CLKIN signal An on chip PLL is capable of multiplying the CLKIN signal
73. MA Write Enable C PG12 DMAR1 UART1TXA HOST_ACK GPIO DMA Request 1 Alternate UART1 Transmit Host DMA Acknowledge C Rev PrE Page240f72 August 2008 Table 10 Signal Descriptions Continued ADSP BF522 523 524 525 526 527 Driver Signal Name Type Function PG13 DMARO UARTTRXA HOST ADDR TACI2 O J GPIO DMA Request 0 Alternate UART1 Receive Host Address Alternate Capture Input 2 PG14 TSCLKOA 1 MDC HOST RD lO 5 Alternate 1 Transmit Ethernet Management Channel Clock D Host DMA Read Enable PG15 TFSOA MII PHYINT RMII MDINT HOST CE O Alternate Transmit Frame Sync Ethernet MII PHY Interrupt RMII C Management Channel Data Interrupt Host DMA Chip Enable Port GPIO and Multiplexed Peripherals PHO ND DO MIICRS RMIICRSDV HOST DO VO GPIO NAND DO Ethernet or RMII Carrier Sense Host DMA DO C PH1 ND_D1 ERxER HOST_D1 I O GPIO NAND D1 Ethernet Receive Error Host DMA D1 C PH2 ND D2 MDIO HOST D2 lO GPIO NAND D2 Ethernet Management Channel Serial Data Host DMA D2 C PH3 ND D3 ETxEN HOST D3 GPIO NAND D3 Ethernet Transmit Enable Host DMA D3 C PH4 ND_D4 MIITxCLK RMIIREF_CLK HOST_D4 O GPIO NAND D4 Ethernet RMII Reference Clock Host D4 C PH5 ND_D5 ETxDO HOST_D5 VO GPIO NAND D5 Ethernet or RMII Transmit DO Host DMA D5 G PH6 ND_D6 ERxDO HOST_D6 GPIO NAND D6 Ethernet RMII Receive DO Host DMA
74. OR AVAILABLE ON ADSP BF523 525 527 PROCESSORS ONLY PERIPHERALS USB 2 0 high speed on the go OTG with Integrated PHY IEEE 802 3 compliant 10 100 Ethernet MAC Parallel peripheral interface PPI supporting ITU R 656 video data formats Host DMA port HOSTDP Two dual channel full duplex synchronous serial ports SPORTs supporting eight stereo 125 channels 12 peripheral DMAs 2 mastered by the Ethernet MAC Two memory to memory with external request lines Event handler with 54 interrupt inputs Serial peripheral interface SPI compatible port Two 5 with IrDA support Two wire interface TWI controller Eight 32 bit timers counters with PWM support 32 bit up down counter with rotary support Real time clock RTC and watchdog timer 32 bit core timer 48 general purpose 1 05 GPIOs with programmable hysteresis Debug JTAG interface On chip PLL capable of 0 5 x to 64 frequency multiplication OTP MEMORY 2 5 ese TWI Figure 1 Processor Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices Inc Rev PrE Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change withou
75. P_BGA by ball number Table 51 208 Ball CSP_BGA Ball Assignment Alphabetically by Signal Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball No No No No No No ABEO SDOMO V19 DATA2 Y7 GND L12 PG6 M2 SS PG G19 Vppwr P14 ABET SDOM1 V20 DATA3 W7 GND L13 PG7 L1 T20 L8 ADDRO1 W20 DATA4 Y6 GND M9 8 12 V2 7 ADDRO2 W19 DATA5 GND M10 PG9 R1 M8 ADDRO3 Y19 DATA6 Y5 GND M11 PG10 K2 11 7 ADDRO4 W18 DATA7 W5 GND M12 PG11 Ji TMS 02 N8 ADDROS5 Y18 DATA8 YA GND M13 PG12 J2 01 7 ADDRO6 W17 DATA9 4 GND 1 H1 USB DM F20 Vppmem P8 ADDRO7 17 DATA10 GND N10 PG14 H2 USB DP E20 P9 ADDRO8 W16 DATA11 W3 GND N11 PG15 G1 1058 ID C20 10 ADDROO9 Y16 DATA12 Y2 N12 PHO A7 05 RSET 020 P11 ADDR10 W15 DATA13 W2 GND N13 PH1 B7 USB VBUS E19 Vpporp R20 ADDR11 Y15 DATA14 1 GND PH2 A8 USB VREF 19 A16 ADDR12 W14 DATA15 V1 GND Y20 PH3 USB XI A19 Vppuse D19 ADDR13 Y14 EMU T2 B19 PH4 9 05 XO A18 Vppuse G20 ADDR14 W13 EXT_WAKE1 J20 VPPOTP 119 5 B9 G7 WAKEO H20 ADDR15 Y13 GND A Ful PHE B10 Vppexr F19 ADDR16 W12 GND AM BIT Mos JXTAL A10 ADDR17 Y12 GND A20 PF2 E2 PH8 A12 Vppe
76. Rx Input Invalid Data In Hold 7 5 7 5 ns inputs synchronous to ERxCLK are ERxD3 0 ERxDV and ERxER Table 41 10 100 Ethernet MAC Controller Timing MII Transmit Signal 1 8 V 2 5 3 3 V Parameter Min Max Min Max Unit ETXCLK Frequency SCLK Frequency None 25 4 196 None 25 4 196 MHz 196 1 Width Period 35 tena X 65 tec X 3596 tenax X 65 lns terxcikov ETxCLK Rising Edge to Tx Output Valid Data Out Valid 20 20 ns terxaikou Rising Edge to Tx Output Invalid Data Qut Hold 0 0 ns MII outputs synchronous to ETxCLK BYRDS d j Table 42 10 100 Ethernet MAC Controller Timing RMII Receive Signal Vos 1 8 V 2 5 3 3 V Parameter Min Max Min Max Unit terercixr REF Frequency SCLK Frequency None 50 196 None 50 4 196 MHz 2x fsck 1 2 1 terercuxw EREF_CLK Width terercix EREFCLK Period X 35 terercix X 65 teneri X 35 terercix X 65 5 tererctkis Rx Input Valid to RMII REF_CLK Rising Edge Data In Setup 4 4 ns REF_CLK Rising Edge to Rx Input Invalid Data In Hold 2 2 ns RMII inputs synchronous to REF CLK are ERxD1 0 5 DV and Table 43 10 100 Ethernet MAC Controller Timing RMII Transmit Signal ADSP BF522 524 526 ADSP BF523 525 527 1 8 V Vopexr 2 5 3 3 V
77. al Max Unit Internal Supply Voltage 0 95 1 26 V Vppexr External Supply Voltage Internal Voltage Regulator Disabled 1 70 1 8 2 50r3 3 3 6 V Vppxr External Supply Voltage Internal Voltage Regulator Enabled 2 25 2 5 or 3 3 3 6 V RTC Power Supply Voltage 2 25 3 6 V Supply Voltage 1 70 1 8 2 5 3 3 3 6 V Vppore OTP Supply Voltage 2 25 2 5 2 75 V OTP Programming Voltage 2 25 2 5 2 75 V Vopuss USB Supply Voltage 3 0 3 3 3 6 V Vin High Level Input Voltage Vppext Vppmem 1 90 V 1 1 3 6 V Vin High Level Input Voltage 2 75 V 1 7 3 6 V Vin High Level Input Voltage 3 6 V 2 0 3 6 V High Level Input Voltage Vopext 1 90 V 2 75 V 3 6 V 0 7 X Veustwi V Vi Low Level Input Voltage 8 Vppexi 1 7 V 0 3 0 6 V Vi Low Level Input Voltage 8 Vopext Vppmem 2 25 V 0 3 0 7 V Low Level Input Voltage 8 3 0 V 0 3 0 8 V Vitm Low Level Input Voltage Vppexr minimum 0 3 0 3xVgusr Tj Junction Temperature 289 Ball BGA 0 C to 70 C 0 105 Junction Temperature 208 Ball BGA 0 C to 70 0 105 Junction Temperature 208 Ball 40 to 85 40 105 1 The voltage regulator can generate at levels of tbd V to 04 V with tbd96 to tbd tolerance
78. ar to the two GPIO control registers that are used to set and clear individual pin values one GPIO interrupt mask register sets bits to enable interrupt function and the other GPIO interrupt mask register clears bits to disable interrupt function GPIO pins defined as inputs can be configured to generate hardware interrupts while output pins can be triggered by software interrupts GPIO interrupt sensitivity registers The two GPIO inter rupt sensitivity registers specify whether individual pins are level or edge sensitive and specify if edge sensitive whether just the rising edge or both the rising and falling edges of the signal are significant One register selects the type of sensitivity and one register selects which edges are significant for edge sensitivity PARALLEL PERIPHERAL INTERFACE PPI The processor provides a parallel peripheral interface PPI that can connect directly to parallel A D and D A converters video encoders and decoders and other general purpose peripherals The PPI consists of a dedicated input clock pin up to three frame synchronization pins and up to 16 data pins The input clock strpports phrall l data 7 up to half the system clock rate and the synchronizgtton signdls can be configured as either inputs or outputs The PPI supports a variety of general purpose and ITU R 656 modes of operation In general purpose mode the PPI provides half duplex bidirectional data transfer with up to 16 bits
79. by the developer within this non volatile memory Memory Space The processor does not define a separate I O space resources are mapped through the flat 32 bit address space On chip I O devices have their control registers mapped into mem ory mapped registers MMRs at addresses near the top of the 4G byte address space These are separated into two smaller blocks one which contains the control for all core func tions and the other which contains the registers needed for setup and control of the on chip peripherals outside of the core The MMRs are accessible only in supervisor mode and appear as reserved space to on chip peripherals Booting The processor contains a small on chip boot kernel which con figures the appropriate peripheral for booting If the processor is configured to boot from boot ROM memory space the proces sor starts executing from the on chip boot ROM For more information see Booting Modes on Page 18 Event Handling The the pede handles all asynchronous and synchronous eyents to thspr cessor The processor pro vides event handling that supports both nesting and prioritization Nesting allows multiple event service routines to be active simultaneously Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event The controller provides support for five different types of events Emulation
80. ce Figure 62 Typical Rise and Fall Times 1096 9096 versus Load Capacitance for Driver at Min for Driver C at Max Figure 60 Typical Rise and Fall Times 1096 9096 versus Load Capacitance Figure 63 Typical Rise and Fall Times 1096 9096 versus Load Capacitance for Driver B at Vppex V pomem for Driver D at Min Figure 61 Typical Rise and Fall Times 1096 9096 versus Load Capacitance Figure 64 Typical Rise and Fall Times 1096 9096 versus Load Capacitance for Driver C at Vopexi DDMEM Min for Driver D at Vppgxi DDMEM Max Rev PrE Page620f72 August 2008 ADSP BF522 523 524 525 526 527 ENVIRONMENTAL CONDITIONS To determine the junction temperature on the application printed circuit board use Toaspt where T Junction temperature Tcasg Case temperature C measured by customer at top center of package From Table 48 Pp Power dissipation see Power Dissipation on Page 60 for the method to calculate Pp Values of are provided for package comparison and printed circuit board design considerations can be used for a first order approximation of T by the equation T4 974 x Pp where T4 Ambient temperature Values of are provided for package comparison and printed circuit board design considerations when an external heat sink is req
81. circuit boards can discharge without detection Although this product features patented or proprietary circuitry damage may occur 2 A on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality PACKAGE INFORMATION The information presented in Figure 8 and Table 20 provides details about the package branding for the ADSP BF522 524 526 and ADSP BF523 525 527 processors For a complete listing of product availability see Ordering Guide on Page 72 ADSP BF52x tppZccc VVVVVV X n n yyww country of origin Figure 8 Product Information on Package Table 20 Package Brand Information Brand Key Field Description ADSP BF52x Product Name t Temperature Range pp Package Type Z RoHS Compliant Designation ccc See Ordering Guide VVVVVV X Assembly Lot Code Silicon Revision yyww Date Code See product names in the Ordering Guide on Page 72 August 2008 ADSP BF522 523 524 525 526 527 TIMING SPECIFICATIONS Clock and Reset Timing Table 21 and Figure 9 describe clock and reset operations Per the CCLK and SCLK timing specifications in Table 12 to Table 17 combinations of CLKIN and clock multipliers must not select core peripheral clocks in excess of the processor s speed grade Table 21 Clock and Reset Timing Parameter Min Max Unit Timing Requirements tcv
82. ck frequency is divided down toa 1 Hz signal by a prescaler The counter function of the timer consists of four counters a 60 second counter a 60 minute counter a 24 hour counter and an 32 768 day counter When enabled the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register There are two alarms The firstalarmeis for a time of day The second alarm 4 forg day and time of that day The stopwatch function counts down from a programmed value with one second resolution When the stopwatch is enabled and the counter underflows an interrupt is generated Like the other peripherals the RTC can wake up the processor from sleep mode upon generation of any RTC wakeup event Additionally an RTC wakeup event can wake up the processor from deep sleep mode or cause a transition from the hibernate state Rev PrE Page100f72 Connect RTC pins RTXI and RTXO with external components as shown in Figure 4 RTXI RTXO 1 SUGGESTED COMPONENTS 1 ECLIPTEK EC38J THROUGH HOLE PACKAGE OR EPSON 405 12 pF LOAD SURFACE MO UNT PACKAGE C1 22 pF C2 22 pF R1 10 MQ NOTE C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1 CONTACT CRYSTAL MANUFACTURER FOR DETAILS C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF c2 Figure 4 External Components for RTC WATCHDOG TIMER The processor includes a 32 bit timer that can be used to imple men
83. d DMA channels one for transmit and one for receive These DMA channels have lower default priority than most DMA channels because of their relatively low service rates Each UART port s baud rate serial data format error code gen eration and status and interrupts are programmable e Supporting bit rates ranging from 1 048 576 to 16 bits per second Supporting data formats from seven to 12 bits per frame Both transmit and receive operations can be configured to generate maskable interrupts to the processor The UART port s clock rate is calculated as 16 Divisor UART Clock Rate Where the 16 bit UART Divisor comes from the VAR most significant 8 bits and significant 8 bits registers In conjunction with the general purpose timer functions baud detection is supported The capabilities of the UARTS are further extended with sup port for the infrared data association IrDA serial infrared physical layer link specification SIR protocol USBON THE GO DUAL ROLE DEVICE CONTROLLER The USB OTG controller provides a low cost connectivity solu tion for consumer mobile devices such as cell phones digital still cameras and MP3 players allowing these devices to transfer data using a point to point USB connection without the need for a PC host The USBDRC module can operate in a traditional USB peripheral only mode as well a
84. e epa 31 SPec CANONS 32 Output Drive Currents 57 Power Dissipation 59 cann i e 59 5 1 62 289 BalLCSP BGA Ball UN 63 208 Ball Ball assignment 66 Di ecd tates 69 Surface Mount 70 Mon b D RM 71 Changes to processor specifications starting on Page 27 Major changes include Added timing Page 36 Changes to SPI Page 47 Added UART timing Page 49 Added Up Down Counter timing Page 51 Changes to HOSTDP timing Page 52 and Page 53 Changes to ball assignment tables Page 64 and Page 67 August 2008 ADSP BF522 523 524 525 526 527 GENERAL DESCRIPTION The ADSP BF522 524 526 and ADSP BF523 525 527 proces sors are members of the Blackfin family of products incorporating the Analog Devices Intel Micro Signal Architec ture MSA Blackfin processors combine a dual MAC state of the art signal processing engine the advantages of a clean orthogonal RISC like microprocessor instruction set and sin gle instruction multiple data SIMD multimedia capabilities into a single instruction set architecture The ADSP BF522 524 526 and ADSP BF523 525 52
85. e tawy Data Hold after HOST WR 2 5 2 5 2 5 2 5 ns rising edge Data Setup before HOSTUWR 2 5 2 5 7 25 2 5 ns rising edge M VU 4 Switching Characteristics HOST ACK low delay after 1 5 1 5 X 1 5 X ty 1 5 ns HOST WR HOST CE asserted ACK mode to HOST ACK low pulse width for NM NM NM NM ns Write access ACK mode NM Not Measured This parameter is not measured because the time for which HOST is low is system design dependent HOST ADDR HOST CE tsapwrL HOST WR HOST towrHRDY tspaTwH luparwH HOST D15 0 Figure 33 HOSTDP A C Host Write Cycle Rev PrE Page530f72 August 2008 ADSP BF522 523 524 525 526 527 10 100 Ethernet MAC Controller Timing Table 40 through Table 45 and Figure 34 through Figure 39 describe the 10 100 Ethernet MAC Controller operations Table 40 10 100 Ethernet MAC Controller Timing MII Receive Signal Vior 1 8 V 2 5 3 3 V Parameter Min Max Min Max Unit terxcixr ERXCLK Frequency SCLK Frequency None 25 4 196 None 25 4 196 MHz 196 1 terxcLkw ERXCLK Width ERXCLK Period terxcik X 35 X 65 X 35 65 ns Rx Input Valid to ERxCLK Rising Edge Data In Setup 7 5 7 5 ns terxcixin ERXCLK Rising Edge to
86. e reference sig Power dissipation specifications for the ADSP T BF522 523 524 525 526 527 prockespis ike UBD S nal ehe Py gut reaches Vs high or Maso low XV an high is 2 0 low is 1 0 V for TEST CONDITIONS Vopexr nominal 2 5 V 3 3 V Time tz is the interval from when the output starts driving to when the output reaches All timing parameters appearing in this data sheet were mea the high or low trip voltage TRIP TRIP sured under the conditions described in this section Figure 53 shows the measurement point for AC measurements except Time is calculated as shown the equation output enable disable The measurement point Vyas is 2 ENA MEASURED T TRIP 2 Vopexr nominal 1 8 V 2 5 V 3 3 V If multiple balls such as the data bus are enabled the measure ment value is that of the first ball to start driving INPUT Output Disable Time Measurement OR VMEAS n OUTPUT Output balls are considered to be disabled when they stop driv ing go into a high impedance state and start to decay from their output high or low voltage The output disable time tps is the Figure 53 Voltage Reference Levels for AC difference between ty yeasurep and as shown on the left side Measurements Except Output Enable Disable of Figure SE tors pis MEASURED
87. egulator provides a range of core voltage levels when supplied from The voltage regulator can be bypassed at the user s discretion ADDRESS ARITHMETIC UNIT BLACKFIN PROCESSOR CORE As shown in Figure 2 the Blackfin processor core contains two 16 bit multipliers two 40 bit accumulators two 40 bit ALUs four video ALUs and a 40 bit shifter The computation units process 8 16 or 32 bit data from the register file The compute register file contains eight 32 bit registers When performing compute operations on 16 bit operand data the register file operates as 16 independent 16 bit registers All operands for compute operations come from the multiported register file and instruction constant fields TO MEMORY DATA ARITHMETIC UNIT CONTROL UNIT Figure 2 Blackfin Processor Core Each MAC can perform a 16 bit by 16 bit multiply in each cycle accumulating the results into the 40 bit accumulators Signed and unsigned formats rounding and saturation are supported The ALUs perform a traditional set of arithmetic and logical operations on 16 bit or 32 bit data In addition many special instructions are included to accelerate various signal processing tasks These include bit operations such as field extract and pop ulation count modulo 2 multiply divide primitives saturation and rounding and sign exponent detection The set of video instructions include byte alig
88. el configtirable to ansmit or receive data streams The SPI s DMA channel can only service unidirectional accesses at any given time The SPI port s clock rate is calculated as SPI Clock Rate 2x SPL BAUD Where the 16 bit SPI_BAUD register contains a value of 2 to 65 535 During transfers the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines The serial clock line synchronizes the shifting and sam pling of data on the two serial data lines UART PORTS The processors provide two full duplex universal asynchronous receiver transmitter UART ports which are fully compatible with PC standard UARTs Each UART port provides a simpli fied UART interface to other peripherals or hosts supporting full duplex DMA supported asynchronous transfers of serial August 2008 ADSP BF522 523 524 525 526 527 data A UART port includes support for five to eight data bits one or two stop bits and none even or odd parity Each UART port supports two modes of operation PIO programmed I O The processor sends or receives data by writing or reading I O mapped UART registers The data is double buffered on both transmit and receive DMA direct memory access The DMA controller trans fers both transmit and receive data This reduces the number and frequency of interrupts required to transfer data to and from memory The UART has two dedicate
89. ell as up to four banks of asynchronous memory devices including flash EPROM ROM SRAM and memory mapped I O devices The SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM A separate row can be open for each SDRAM internal bank and the SDRAM controller supports up to 4 internal SDRAM banks improving overall performance The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices Each bank occupies a 1M byte segment regardless of the size of the devices used so that these banks are only contiguous if each is fully populated with 1M byte of memory NAND Flash Controller NFC The ADSP BF522 524 526 and ADSP BF523 525 527 proces sors provide a NAND flash controller NFC NAND flash devices provide high density low cost memory However NAND flash devices also have long random access times invalid blocks and lower reliability over device lifetimes Because of this NAND flash is often used for read only code storage In this case all DSP code can be stored in NAND flash and then transferred to a faster memory such as SDRAM or SRAM before execution Another common use of NAND flashgs fery storage of multimedia files or other IA ata Segments In this case a software file system may be used manage teading and writing ofthe NAND flash device The file system selects mem ory segments for storage with the
90. er ABE ADDRESS ADDR19 1 AOE 1 gt tbo tuo ARE gt 14 tsarpy Figure 10 Asynchronous Memory Read Cycle Timing Rev PrE Page340f72 August 2008 ADSP BF522 523 524 525 526 527 Asynchronous Memory Write Cycle Timing Table 23 Asynchronous Memory Write Cycle Timing 1 8 V Voomen 2 5 3 3 V Parameter Min Max Min Max Unit Timing Requirements tsarpy ARDY Setup Before CLKOUT 4 0 4 0 ns ARDY Hold After CLKOUT 0 0 0 0 ns Switching Characteristics DATA15 0 Disable After CLKOUT 6 0 6 0 ns tenpar DATA15 0 Enable After CLKOUT 0 0 0 0 ns too Output Delay After CLKOUT 6 0 6 0 ns tuo Output Hold After CLKOUT 0 8 0 8 ns Output balls include 53 0 1 0 ADDR19 1 15 0 AOE AWE ACCESS SETUP PROGRAMMED WRITE EXTENDED HOLD 2 CYCLES ACCESS 2 CYCLES 1CYCLE 1 CYCLE ee ai CLKOUT gt 4 5 a MEVS TTE a 0 ABE ADDRESS ADDR19 1 too tu HO AWE ARDY tsarpy 4 topat DATA15 0 WRITE DATA Figure 11 Asynchronous Memory Write Cycle Timing Rev PrE Page350f72 August 2008 ADSP BF522 523 524 525 526 527 NAND Flash Controller Interface Timing Table 24 and Figure 12 on Page 36 through Figure 16 on Page 38 describe NAND Flash C
91. ettings Boot from OTP memory BMODE 0xB This provides a stand alone booting method The boot stream is loaded from on chip OTP memory By default the boot stream is expected to start from OTP page 0x40 and can occupy all public OTP memory up to page OxDF This is 2560 bytes Since the start page is programmable the maximum size of the boot stream can be extended to 3072 bytes Table 9 Fourth Byte for Large Page Devices Bit Parameter Value Meaning 01 00 Page Size 00 1K byte excluding spare area 01 2K byte 10 4K byte 11 8K byte D2 Spare Area Size 00 8 byte 512 byte 01 16 byte 512 byte 05 04 Block Size 00 64K byte excluding spare area 01 128K byte 10 256K byte 11 512 byte D6 Width 00 8 03 07 Not Used for configuration 01 not supported Boot from 8 bit external NAND flash memory BMODE 0 and BMODE 0 0 In this mode auto detection of the NAND flash device is performed BMODE 0xC the processor configures PORTF GPIO pins PF7 0 for the NAND data pins and PORTH pins PH15 10 for the NAND control signals BMODE 0 the processor configures PORTH GPIO pins PH7 0 for the NAND data pins and PORTH pins PH15 10 for the NAND control signals For correct device operation pull up resistors are required on both ND CE PH10 and ND BUSY PH 13 signals default a value of 0x0033 is written to the NFC_CTL regis ter The booting procedure always starts by boo
92. ever the latency can be much higher depend ing on the activity within and the state of the processor DMA CONTROLLERS The processor has multiple independent DMA channels that support automated data transfers with minimal overhead for the processor core DMA transfers can occur between the pro cessor s internal memories and any of its DMA capable peripherals Additionally DMA transfers can be accomplished between any of the DMA capable peripherals and external devices connected to the external memory interfaces including the SDRAM controller and the asynchronous memory control Rev PrE Page90f72 ler DMA capable peripherals include the Ethernet MAC NFC HOSTDP USB SPORTS SPI port UARTS and PPI Each indi vidual DMA capable peripheral has at least one dedicated DMA channel The processor DMA controller supports both one dimensional 1 D and two dimensional 2 D DMA transfers DMA trans fer initialization can be implemented from registers or from sets of parameters called descriptor blocks The 2 D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements and arbitrary row and column step sizes up to 32K elements Furthermore the column step size can be less than the row step size allowing implementation of interleaved data streams This feature is especially useful in video applications where data can be de interleaved on the fly Examples of DMA types supported by the processor DMA
93. imple system warning by interrupts when programmable count values are exceeded SERIAL PORTS The processors incorporate two dual channel synchronous serial ports SPORTO and SPORT L forserial andjhultiptoces sor communications The SPORIS slpport the following features capable operation e Bidirectional operation Each SPORT has two sets of inde pendent transmit and receive pins enabling eight channels of S stereo audio Buffered 8 deep transmit and receive ports Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers Clocking Each transmit and receive port can either use an external serial clock or generate its own in frequencies ranging from 131 070 Hz to 2 Hz Wordlength Each SPORT supports serial data words from 3 to 32 bits in length transferred most significant bit first or least significant bit first Framing Each transmit and receive port can run with or without frame sync signals for each data word Frame sync signals can be generated internally or externally active high or low and with either of two pulse widths and early or late frame sync Companding in hardware Each SPORT can perform companding according to ITU recommen dation G 711 Companding can be selected on the transmit and or receive channel of the SPORT without add
94. ip voltage regula tor that can generate processor core voltage levels from an external supply Figure 5 shows the typical external components required to complete the power management system The regu lator controls the internal logic voltage levels and is programmable with the voltage regulator control register VR CTL in increments of 50 mV To reduce standby power consumption the internal voltage regulator can be programmed to remove power to the processor core while keeping L Q power supplied While in the hibernate Au all external supplies Vppugw applied ing the need for external buffers V must be applied at all times for correct hibernate operation The voltage regulator can be activated from this power down state either through an RTC wakeup a USB wakeup an ethernet wakeup or by asserting the RESET pin each of which then initiates a boot sequence The regulator can also be disabled and bypassed at the user s discretion SET OF DECOUPLING 2 25V TO 3 6V CAPACITORS INPUT VOLTAGE RANGE VDDEXT LOW INDUCTANCE 100uF 100nF m 2 Grosera 10 ZHCS1000 100pF 55 LOW ESR SHORT AND LOW EXT WAKE1 INDUCTANCE WIRE SEE H W REFERENCE SYSTEM DESIGN CHAPTER TO DETERMINE VALUE VRseL NOTE DESIGNER SHOULD MINIMIZE TRACE LENGTH FDS9431A Figure 5 ADSP BF523 525 527 Voltage Regulator C
95. ircuit Rev PrE Page160f72 The voltage regulator has two modes set by the pin the normal pulse width control of an external FET and the external supply mode which can signal a power down during hibernate to an external regulator Set to to use an external regulator or set to GND to use the internal regulator In the external mode VRoyr becomes EXT WAKEI If the internal regulator is used EXT WAKEO can control other power sources in the system during the hibernate state Both signals are high true for power up and may be connected directly to the low true shut down input of many common regulators The mode of the SS PG Soft Start Power Good signal also changes according to the state of VRsgr When using an internal regula tor the SS PG pin is Soft Start and when using an external regulator it is Power Good The Soft Start feature is recom mended to reduce the inrush currents and to reduce voltage overshoot when coming out of hibernate or changing voltage levels The Power Good PG input signal allows the processor to start only after the internal voltage has reached a chosen level In this way the startup time of the external regula tor is detected after hibernation For a complete description of Soft Start and Power Good functionality refer to the ADSP BF52x Blackfin Processor Hardware Reference ADSP BF522 524 526 VOLTAGE REGULATION The ADSP BF522 524 526 processor requires an exter
96. isters SIC ISRx As multiple peripherals can be mapped to a single event these registers allow the software to determine which peripheral event source triggered the interrupt A set bit indicates the peripheral is asserting the interrupt and a cleared bit indi cates the peripheral is not asserting the event SIC interrupt wakeup enable registers SIC IWRx By enabling the corresponding bit in these registers a periph eral can be configuredstogwakeup the processor should the core be idled or in sleep AY UA the eyentiis generated For more information see Dynamic Power Management on Page 14 Because multiple interrupt sources can map to a single general purpose interrupt multiple pulse assertions can occur simulta neously before or during interrupt processing for an interrupt event already detected on this interrupt input The IPEND reg ister contents are monitored by the SIC as the interrupt acknowledgement The appropriate ILAT register bit is set when an interrupt rising edge is detected detection requires two core clock cycles The bit is cleared when the respective IPEND register bit is set The IPEND bit indicates that the event has entered into the proces sor pipeline At this point the CEC recognizes and queues the next rising edge event on the corresponding event input The minimum latency from the rising edge transition of the general purpose interrupt to the IPEND output asserted is three core clock cycles how
97. itional latencies Rev 11 of 72 DMA operations with single cycle overhead Each SPORT can automatically receive and transmit multiple buffers of memory data The processor can link or chain sequences of DMA transfers between a SPORT and memory Interrupts Each transmit and receive port generates interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA Multichannel capability Each SPORT supports 128 chan nels out of a 1024 channel window and is compatible with the H 100 H 110 MVIP 90 and HMVIP standards SERIAL PERIPHERAL INTERFACE SPI PORT The processors have an SPI compatible port that enables the processor to communicate with multiple SPI compatible devices The SPI interface uses three pins for transferring data two data pins Master Output Slave Input MOSI and Master Input Slave Output MISO and a clock pin serial clock SCK An SPI chip select input pin SPISS lets other SPI devices select the processor and seven SPI chip select output pins SPISEL7 1 let the processor select other SPI devices The SPI select pins are reconfigured general purpose I O pins Using these pins the SPI port provides a full duplex synchronous serial interface which supports both master slave modes and multimaster environments The SPLports baud yate phase polarities are pro grammable and it inate DMA chann
98. me 0 0 0 0 ns tomaracr DMARx Active Pulse Width 1 0 X 1 0 X ns DMARx Inactive Pulse Width 1 75 1 75 X ns Because the external DMA control pins are part of the power domain and the CLKOUT signal is part of the Vppmem power domain systems in which Vppexr and Vppmem are NOT equal may require level shifting logic for correct operation CLKOUT lt lt toy DMARO 1 Active Low B DMARO 1 t Active High DMARACT Figure 18 External DMA Request Timing Rev PrE Page400f72 August 2008 ADSP BF522 523 524 525 526 527 Parallel Peripheral Interface Timing Table 27 and Figure 19 on Page 41 Figure 23 on Page 46 and Figure 24 on Page 46 describe parallel peripheral interface operations Table 27 Parallel Peripheral Interface Timing ADSP BF522 524 526 ADSP BF523 525 527 Vopext 1 8 2 5 3 3 V 1 8 Vox 2 5 3 3 Parameter Min Max Min Max Min Unit Timing Requirements Width 6 4 6 4 6 0 6 0 ns CLK Period 16 0 16 0 15 0 15 0 ns Timing Requirements GP Input and Frame Capture Modes tsrs External Frame Sync Setup Before PPI_CLK 6 7 6 7 6 7 6 7 ns Nonsampling Edge for Rx Sampling Edge for Tx ture External Frame Sync Hold After 1 0 1 0 1 0 1 0 ns
99. n Max Unit Timing Requirement General Purpose Port Ball Input Pulse Width tsak 1 tsak 1 tsek 1 1 ns Switching Characteristics tepop General Purpose Port Ball Output Delay from CLKOUT Low 0 9 66 0 9 66 0 6 0 6 ns CLKOUT tapon GPIO OUTPUT GPIO INPUT Figure 28 General Purpose Port Timing Rev PrE Page490f72 August 2008 ADSP BF522 523 524 525 526 527 Timer Cycle Timing Table 35 and Figure 29 describe timer expired operations The input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre quency of fgcyx 2 MHz Table 35 Timer Cycle Timing ADSP BF522 524 526 ADSP BF523 525 527 1 8 V 2 5 3 3 V Voor 1 8 V 2 5 3 3 V Parameter Min Max Min Max Min Max Min Max Unit Timing Characteristics tw Timer Pulse Width Input Low 1 X 1 1 X 1 X ns Measured In SCLK Cycles tw Timer Pulse Width Input High 1 X 1 X 1 1 X ns Measured In SCLK Cycles tns Timer Input Setup Time Before CLKOUT Low 5 5 5 5 ns Timer Input Hold Time After CLKOUT Low 2 2 2 2 ns Switching Characteristics tuto Timer Pulse Width Output 1 22 1 1 222 1 1 22 1 6 1 222 1 6 ns Measured In SCLK Cycles trop Timer Output Update Delay After CLKOUT High 8 1 8 1 6 6 ns 1 The minimum pulse widths apply
100. n the later case Bits 6 4 in the system reset configuration SYSCR register can be used to bypass the pre boot routine and or boot kernel in case of a software reset They can also be used to simu late a wakeup from hibernate boot in the software reset case The boot process can be further customized by initialization code This is a piece of code that is loaded and executed prior to the regular application boot Typically this is used to configure the SDRAM controller or to speed up booting by managing the PLL clock frequencies wait states or serial bit rates The boot ROM also features C callable function that can be called by the user application at run time This enables second stage boot or boot management schemes to be implemented with ease INSTRUCTION SET DESCRIPTION The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability The instructions have been specifically tuned to pro vide a flexible densely encoded instruction set that compiles to avery small final memory size The instruction set also provides fully featured multifunction instructions that allow the pro grammer to use many of the processor core resoungessinmagsingle instruction Coupled with manyjfeatures more often seen microcontrollers this instruction set is very efficientawhen com piling C and C source code In addition the architecture supports both user algorithm
101. nal volt age regulator to power the Vppmr domain To reduce standby power consumption the external voltage regulator can be sig naled through EXT WAKEO0 WAKEI to remove power from ffe pfoceSSot Core These signals are high true fer power up and may coninect d directly to the low true shut down input of many common regulators While in the hibernate state all external supplies Vppugw can still be applied eliminating the need for external buffers Vppgrc must be applied at all times for correct hibernate operation The external voltage regulator can be activated from this power down state either through an RTC wakeup a USB wakeup an ethernet wakeup or by asserting the RESET pin each of which then initiates a boot sequence EXT WAKEO EXT WAKEI indicate a wakeup to the external voltage regula tor The Power Good PG input signal allows the processor to start only after the internal voltage has reached a chosen level In this way the startup time of the external regulator is detected after hibernation For a complete description of the Power Good functionality refer to the ADSP BF52x Blackfin Processor Hard ware Reference CLOCK SIGNALS The processor can be clocked by an external crystal a sine wave input or a buffered shaped clock derived from an external clock oscillator Ifan external clock is used it should be a TTL compatible signal and must not be halted
102. neral purpose I O GPIO pins allocated across three separate GPIO modules PORTFIO PORTGIO and PORTHIO associated with Port F Port G and Port H respectively Port J does not provide GPIO functional ity Each GPIO capable pin shares functionality with other processor peripherals via a multiplexing scheme however the GPIO functionality is the default state of the device upon power up Neither GPIO output nor input drivers are active by default Each general purpose port pin can be individually con trolled by manipulation of the port control status and interrupt registers GPIO direction control register Specifies the direction of each individual GPIO pin as input or output GPIO control and status registers The processor employs a write one to modify mechanism that allows any combi nation of individual GPIO pins to be modified in a single instruction without affecting the level of any other GPIO pins Four control registers are provided One register is written in order to set pin values one register is written in order to clear pin values one register is written in order to Rev Page 13 of 72 toggle pin values and one register is written in order to specify a pin value Reading the GPIO status register allows software to interrogate the sense of the pins GPIO interrupt mask registers The two GPIO interrupt mask registers allow each individual GPIO pin to function as an interrupt to the processor Simil
103. nment and packing operations 16 bit and 8 bit adds with clipping 8 bit average operations Rev PrE Page40f72 and 8 bit subtract absolute value accumulate SAA operations Also provided are the compare select and vector search instructions For certain instructions two 16 bit ALU operations can be per formed simultaneously on register pairs a 16 bit high half and 16 bit low half of a compute register If the second ALU is used quad 16 bit operations are possible The 40 bit shifter can perform shifts and rotates and is used to support normalization field extract and field deposit instructions The program sequencer controls the flow of instruction execu tion including instruction alignment and decoding For program flow control the sequencer supports PC relative and August 2008 ADSP BF522 523 524 525 526 527 indirect conditional jumps with static branch prediction and subroutine calls Hardware is provided to support zero over head looping The architecture is fully interlocked meaning that the programmer need not manage the pipeline when executing instructions with data dependencies The address arithmetic unit provides two addresses for simulta neous dual fetches from memory It contains a multiported register file consisting of four sets of 32 bit index modify length and base registers for circular buffering and eight additional 32 bit pointer registers for C style indexed stack manipulation
104. number Actual test specification is SCLK period of 7 5 ns See Table 25 on Page 39 Rev PrE Page300f72 August 2008 ADSP BF522 523 524 525 526 527 ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min Typical Max Unit Vou High Level Output Voltage Domem 1 7 V lou 0 5 mA 1 35 V Vou High Level Output Voltage Vopex 2 25 V 0 5 2 0 V Vou High Level Output Voltage Vopex Vopmem 3 0 V lou 0 5 mA 24 V VoL Low Level Output Voltage 1 7 V 2 25 V 3 0 V 0 4 V lo 2 0 mA Low Level Output Voltage Vopex Vopmem 1 7 V 2 25 V 3 0 V TBD V lo 2 0 mA V High Level Input Current Vopex 3 6 V Vin 3 6 V 10 0 lu Low Level Input Current Vopext Vppmem 3 6 V Vin 0 V 10 0 line High Level Input Current Vopext 3 6 V Vin 3 6 V 50 0 lozu Three State Leakage Current Vopext Vppmem 3 6 V Vy 3 6 V 10 0 lozurwi Three State Leakage Current Vpprxr 73 0 V Vy 5 5 V 10 0 Three State Leakage Current Vopext Vppmem 3 6 V Vy 0 V 10 0 Input Capacitance fin 1 MHZ Tampient 25 C V 2 5 TBD TBD pF Total Current for All Domains in VppRic7 Vppuse 3 3 V TBD Hibernate State 2 5 V VopiNT 0 V CLKIN 0 MHz GT 25 DOE Total Current for in Hibernate
105. og com use site search on EE 68 This document is updated regularly to keep pace with improvements to emulator support RELATED DOCUMENTS The following publications that describe the ADSP BF522 524 526 and ADSP BF523 525 527 processors and related processors can be ordered from any Analog Devices sales office or accessed electronically on our website Getting Started With Blackfin Processors ADSP BF52x Blackfin Processor Hardware Reference Blackfin Processor Programming Reference ADSP BF522 524 526 Blackfin Processor Anomaly List ADSP BF523 525 527 Blackfin Processor Anomaly List LOCKBOX SECURE TECHNOLOGY DISCLAIMER Analog Devices products containing Lockbox Secure Technol ogy are warranted by Analog Devices as detailed in the Analog Devices Standard Terms and Conditions of Sale To our knowl edge the Lockbox Secure Technology when used in accordance August 2008 ADSP BF522 523 524 525 526 527 with the data sheet and hardware reference manual specifica tions provides a secure method of implementing code and data safeguards However Analog Devices does not guarantee that this technology provides absolute security ACCORDINGLY ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE LOCKBOX SECURE TECHNOLOGY CANNOT BE BREACHED COMPROMISED OR OTHERWISE CIR CUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS DAMAGE DESTRUC TION OR RELEASE OF DATA
106. oming bit stream is read in through the PPI This includes active video control preamble sequences and ancillary data that may be embedded in horizontal and ver tical blanking intervals Data transfer starts immediately after synchronization to Field 1 Data is transferred to or from the synchronous channels through eight DMA engines that work autonomously from the processor core Rev PrE Page140f72 CODE SECURITY WITH LOCKBOX SECURE TECHNOLOGY security system consisting of a blend of hardware and soft ware provides customers with a flexible and rich set of code security features with Lockbox secure technology Key features include OTP memory Unique chip ID Code authentication Secure mode of operation The security scheme is based upon the concept of authentica tion of digital signatures using standards based algorithms and provides a secure processing environment in which to execute code and protect assets See Lockbox Secure Technology Dis claimer on Page 21 DYNAMIC POWER MANAGEMENT The processor provides four operating modes each with a dif ferent performance power profile In addition dynamic power management provides the control functions to dynamically alter the processor core supply voltage further reducing power dissi pation When configured for a 0 volt core supply voltage the processor enters the hibernate state Control of clocking to each of the processor peripherals also reduces power con
107. ontroller Interface operations Table 24 NAND Flash Controller Interface Timing Parameter Min Max Unit Write Cycle Switching Characteristics ND CE Setup Time AWE Low 1 0 4 ns tcu ND CE Hold Time From AWE High 3 0 4 ns ND CLE Setup Time High to AWE Low 0 0 ns ND CLE Hold Time From AWE high 25 4 ns ND ALE Setup Time Low to AWE Low 0 0 ns tun ND ALE Hold Time From AWE High 25 4 ns tw AWE Low to AWE high WR DLY 41 0 4 ns twawe AWE High to AWE Low 4 0 X ts 4 ns AWE Low to AWE Low WR DLY 45 0 4 ns tows Data Setup Time for a Write Access WR_DLY 1 5 x tgak 4 ns town Data Hold Time for a Write Access 2 5 4 ns Read Cycle Switching Characteristics tear ND_CE Setup Time to ARE Low 1 0 4 ns torn ND_CE Hold Time From ARE High 3 0 4 ns tgp ARE Low to ARE High RD DLY 1 0 tsa 4 ns ARE High to bow i Tox Ok 4 ns tac ARE Low to ARE Low DLY 50 x 4 ns Timing Requirements tors Data Setup Time for a Read Transaction 8 0 ns tory Data Hold Time for a Read Transaction 0 0 ns Write Followed by Read Switching Characteristics twunL AWE High to ARE Low 5 0x 4 ns WR DLY and RD DLY are defined in the register 2 only parameter that differs from 1 8V to 2 5 3 3V operation is tpgs which is 8 0ns at 2 5 3
108. opriate bit is set when set inthe IMASK i the processor has latched the event and cleared when the processed by prin ue IMASK register masks the event preventing the processor from servicing the event even though the event may be latched in the ILAT register This register may be read or Rev PrE Page80f72 August 2008 ADSP BF522 523 524 525 526 527 written while in supervisor mode Note that general pur pose interrupts can be globally enabled and disabled with the STI and CLI instructions respectively CEC interrupt pending register IPEND The IPEND register keeps track of all nested events A set bit in the IPEND register indicates the event is currently active or nested at some level This register is updated automatically by the controller but may be read while in supervisor mode The SIC allows further control of event processing by providing three pairs of 32 bit interrupt control and status registers Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 7 SIC interrupt mask registers SIC 5 Control the masking and unmasking of each peripheral interrupt event When a bit is set in these registers that peripheral event is unmasked and is processed by the system when asserted A cleared bit in the register masks the peripheral event pre venting the processor from servicing the event SIC interrupt status reg
109. ot kernel issues a CALL instruction to address 0000 It is the host s responsibility to ensure valid code has been placed at this address The rou tine at OxFFAO 0000 can be a simple initialization routine to configure internal resources such as the SDRAM con troller which then returns using an RTS instruction The routine may also by the final application which will never return to the boot kernel For each of the boot modes a 16 byte header is first read from an external memory device The header specifies the number of bytes to be transferred and the memory destination address Multiple memory blocks may be loaded by any boot sequence Once all blocks are loaded program execution commences from the address stored in the register Prior to booting the pre boot routine interrogates the OTP memory Individual boot modes can be customized or even dis abled based on OTP programming External hardware especially booting hosts may watch the HWAIT signal to deter mine when the pre boot has finished and the boot kernel starts the boot process By programming OTP memory the user can August 2008 ADSP BF522 523 524 525 526 527 also instruct the pre boot routine to customize the PLL Internal Voltage Regulator ADSP BF523 525 527 only SDRAM Con troller and Asynchronous Memory Controller The boot kernel differentiates between a regular hardware reset and a wakeup from hibernate event to speed up booting i
110. peripherals and memory Blackfin processors are the platform of choice for next generation applications that require RISC like program mability multimedia support and leading edge signal processing in one integrated package PORTABLE LOW POWER ARCHITECTURE Blackfin processors provide world class power management and performance They are produced with a low power and low voltage design methodology and feature on chip dynamic power management which is the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption This capability can result in a substantial reduc tion in power consumption compared with just varying the frequency of operation This allows longer battery life for portable appliances SYSTEM INTEGRATION The ADSP BF522 524 526 and ADSP BF523 525 527 proces sors are highly integrated system on a chip solutions for the next generation of embedded network connected applications By combining industry standard interfaces with a high perfor mance signal processing core cost effective applications can be developed quickly without the need for costly external compo nents The system peripherals include an IEEE compliant 802 3 1041 00 EthernetsMA 1058 0 high speed OTG controller a TWI Controllers NAND flash controller two UART ports an SPPport two serial 5 SPORTS eight general purpose 32 bit timers with PWM capability a core timer a real time clock a
111. ply with the specification in Table 9 Any NAND flash array configuration from Table 9 exclud ing 16 bit devices that also complies with the command set listed below are directly supported by the boot kernel There are no restrictions on the page size or block size as imposed by the small page boot kernel For devices consisting of a five byte signature only four are read The fourth must comply as outlined above Large page devices must support the following command set Reset Read Electronic Signature 0x90 Read 0x00 0x30 confirm command Large page devices must not support or react to NAND flash command 0x50 This is a small page NAND flash command used for device auto detection By default the boot kernel will always issue five address cycles therefore if a large page device requires only four cycles the device must be capable of ignoring the addi tional address cycles Rev PrE Page200f72 Boot from 16 Bit Host BMODE OxE In this mode the host DMA port is configured in 16 bit Acknowl edge mode with little endian data formatting Unlike other modes the host is responsible for interpreting the boot stream It writes data blocks individually into the Host DMA port Before configuring the DMA settings for each block the host may either poll the ALLOW CONFIG bit in HOST STATUS or wait to be interrupted by the HWAIT signal When using HWAIT the host must still check
112. pplies See Output Drive Currents on Page 58 for more information about each driver type HWAIT must be pulled high or low to configure polarity See Booting Modes on Page 18 When driven low this ball can be used to wake up the processor from the hibernate state either in normal GPIO mode or in Ethernet mode as MII PHYINT If the ball is used for wake up enable the feature with the PHYWE bit in the VR CTL register and pull up the ball with a resistor 4 Consult version 2 1 of the specification for the proper resistor value Rev PrE Page260f72 August 2008 ADSP BF522 523 524 525 526 527 SPECIFICATIONS Specifications are subject to change without notice OPERATING CONDITIONS FOR ADSP BF522 524 526 Parameter Conditions Min Nominal Max Unit Vopint Internal Supply Voltage tbd tbd tbd V Vppr External Supply Voltage 1 70 1 8 2 50r3 3 3 6 V Vpprtc RTC Power Supply Voltage 2 25 3 6 V Vbomem Supply Voltage 1 70 1 8 2 5 0r 3 3 3 6 V Vppore OTP Supply Voltage 2 25 2 5 2 75 V Vepore Programming Voltage For Reads 2 25 2 5 2 75 V For Writes 6 9 7 0 7 1 V Vppuss USB Supply Voltage 3 0 3 3 3 6 V High Level Input Voltage Vppext Voomem 1 90 V 1 1 3 6 V High Level Input Voltage 2 75 V 1 7 3 6 V High Level Input Voltage Vppext Vppmem 3 6 V 2 0 3 6 V High Level Input Voltage 1 90 V 2 75 V 3 6 V 0 7 X Vgusrwi VBust
113. rnal clock input to the PPI CLK input pin or to the internal SCLK The timer units can be used in conjunction with the two UARTs to measure the width of the pulses in the data stream to provide a software auto baud detect function for the respective serial channels August 2008 ADSP BF522 523 524 525 526 527 The timers can generate interrupts to the processor core provid ing periodic events for synchronization either to the system clock or to a count of external signals In addition to the eight general purpose programmable timers a ninth timer is also provided This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts UP DOWN COUNTER AND THUMBWHEEL INTERFACE A 32 bit up down counter is provided that can sense 2 bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels The counter can also operate in general purpose up down count modes Then count direction is either controlled by a level sensitive input pin or by two edge detectors A third input can provide flexible zero marker support and can alternatively be used to input the push button signal of thumb wheels All three pins have a programmable debouncing circuit An internal signal forwarded to the timer unit enables one timer to measure the intervals between count events Boundary regis ters enable auto zero operation or s
114. s the host mode presented in the On The Go supplement to the USB 2 0 Specifica tion In host mode the USB module supports transfers at high speed 480Mbps full speed 12Mbps and low speed 1 5Mbps rates Peripheral only mode supports the high and full speed transfer rates TWI CONTROLLER INTERFACE The processors include a two wire interface TWT module for providing a simple exchange method of control data between multiple devices The TWI is compatible with the widely used bus standard TWI module offers the capabilities of simultaneous master and slave operation support for both 7 bit addressing and multimedia data arbitration The TWI interface Rev PrE Page120f72 utilizes two pins for transferring clock SCL and data SDA and supports the protocol at speeds up to 400k bits sec The TWI interface pins are compatible with 5 V logic levels Additionally the TWI module is fully compatible with serial camera control bus SCCB functionality for easier control of various CMOS camera sensor devices 10 100 ETHERNET MAC The ADSP BF526 and ADSP BF527 processors offer the capa bility to directly connect to a network by way of an embedded Fast Ethernet Media Access Controller MAC that supports both 10 BaseT 10M bits sec and 100 BaseT 100M bits sec operation The 10 100 Ethernet MAC peripheral on the proces sor is fully compliant to the IEEE 802 3 2002 standard and it provides programmable features
115. sign recommendations refet to IPC 7351 Generic Requirements for Surface Mount Design Bind Land Pattern i Standard Table 53 Surface Mount Design Supplement Package Ball Attach Type Solder Mask Opening Ball Pad Size 289 Ball 5 BGA Solder Mask Defined 0 26 mm diameter 0 35 mm diameter 208 Ball 5 BGA Solder Mask Defined 0 40 mm diameter 0 50 mm diameter Rev PrE Page710f72 August 2008 ADSP BF522 523 524 525 526 527 ORDERING GUIDE Table 54 ADSP BF522 524 526 Processors Temperature Package Instruction Operating Voltage ADSP BF526KBCZ 4X 0 Cto 70 C 289 Ball Chip Scale Package Ball BC 289 2 400 MHz tod V internal 1 8 V 2 5 V or 3 3 V Grid Array CSP_BGA ADSP BF526BBCZ 4AX 409 to 85 C 208 Ball Chip Scale Package Ball BC 208 2 400 MHz tod V internal 1 8 V 2 5 V or 3 3 V Grid Array CSP_BGA ADSP BF526BBCZ 3AX 409 to 85 C 208 Ball Chip Scale Package Ball BC 208 2 400 MHz tod V internal 1 8 V 2 5 V or 3 3 V tid Array 5 Referenced temperature is ambient temperature Table 55 ADSP BF523 525 527 Processors Temperature Package Instruction Operating Voltage ADSP BF527KBCZ 6X 0 Cto 70 C 289 Chip Scale Package Ball 289 2 600 MHz 1 2 V internal 1 8 V 2 5 V or 3 3 V Grid Array 5 BGA ADSP BF527KBCZ 6AX QeCto 709C 208 Ball Chip Scale Package Ball 208 2 600 MHz 1 2 V internal
116. state maximizes static power savings by disabling the voltage and clocks to the processor core CCLK and to all of the synchronous peripherals SCLK The internal voltage regu lator ADSP BF523 525 527 only for the processor can be shut off by writing b 00 to the FREQ bits of the VR register This setting sets the internal power supply voltage Vppmr to 0 V to provide the lowest static power dissipation Any critical information stored internally for example memory contents register contents and other information must be written to a non volatile storage device prior to removing power the pro cessor state is to be preserved Writing b 00 to the FREQ bits also causes EXT WAKEO and EXT WAKEI to transition low which can be used to signal an external voltage regulator to shut down Since and Vppmem can still be supplied in this mode all of the external pins three state unless otherwise specified This allows other devices that may be connected to the processor to still have power applied without drawing unwanted current Rev PrE Page150f72 The Ethernet or USB modules can wake up the internal supply regulator ADSP BF525 and ADSP BF527 only or signal an external regulator to wake up using EXT WAKEO or EXT WAKEI If PG15 does not connect as a PHYINT signal to an external PHY device 15 can be pulled low by any other device to wake the processor up The processor can also be woken up by a real time clock
117. sumption See Table 4 for a summary of the power settings for each mode Full On opg Modet Performance n the full on mode the PLL T enabled and is not bypassed providing capability for maximum operational frequency This is the power up default execution state in which maximum per formance can be achieved The processor core and all enabled peripherals run at full speed Active Operating Mode Moderate Dynamic Power Savings In the active mode the PLL is enabled but bypassed Because the PLL is bypassed the processor s core clock CCLK and system clock SCLK run at the input clock CLKIN frequency DMA access is available to appropriately configured L1 memories In the active mode it is possible to disable the PLL through the PLL control register If disabled the PLL must be re enabled before transitioning to the full on or sleep modes Table 4 Power Settings Core System PLL Clock Clock Core Mode State PLL CCLK SCLK Power Full On Enabled No Enabled Enabled On Active Enabled Yes Enabled Enabled On Disabled August 2008 ADSP BF522 523 524 525 526 527 Table 4 Power Settings Continued Core System PLL Clock Clock Core Mode State PLL Bypassed CCLK SCLK Power Sleep Enabled Disabled Enabled On Deep Sleep Disabled Disabled Disabled On Hibernate Disabled Disabled
118. t NMI controller to prioritize and control all system events Conceptu 3 Exception EVX ally interrupts from the peripherals enter into the SIC and are 4 Reserved then routed directly into the general purpose interrupts of the CEC 5 Hardware Error IVHW 6 Core Timer IVTMR Core Event Controller CEC 7 General Purpose Interrupt 7 IVG7 The CEC supports nine general purpose interrupts IVG15 7 8 General Purpose Interrupt 8 IVG8 in addition to the dedicated interrupt and exception events Of 9 General Purpose Interrupt 9 IVG9 these general purpose interrupts the two lowest priority interrupts IVG15 14 are recommended to be reserved for 10 General Purpose Interrupt 10 software interrupt handlers leaving seven prioritized interrupt 11 General Purpose Interrupt 11 IVG11 inputs to support the peripherals of the processor Table 2 12 General Purpose Interrupt 12 IVG12 describes the inputs to the identifies their names in the 13 General Purpose Interrupt 13 IVG13 event vector table EVT and lists their priorities 14 General Purpose Interrupt 14 IVG14 System Interrupt Controller SIC 15 General Purpose Interrupt 15 IVG15 The system interrupt controller provides the mapping and rout ing of events from the many peripheral interrupt sources to the prioritized general purpose interrupt inputs of the CEC Although the processor provides a default mapping the user can alter the mappings and priorities of interrupt
119. t a software watchdog function A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset nonmaskable interrupt or gener l prirpase interrupt if the timer expires before beinp reset by software The programmer initial ies thecotnt Value of the timters nables the appropriate interrupt then enables the timer Thereafter the software must reload the counter before it counts to zero from the pro grammed value This protects the system from remaining in an unknown state where software which would normally reset the timer has stopped running due to an external noise condition or software error If configured to generate a hardware reset the watchdog timer resets both the core and the processor peripherals After a reset software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register The timer is clocked by the system clock SCLK at a maximum frequency of TIMERS There are nine general purpose programmable timer units in the processors Eight timers have an external pin that can be configured either as a pulse width modulator PWM or timer output as an input to clock the timer or as a mechanism for measuring pulse widths and periods of external events These timers can be synchronized to an external clock input to the sev eral other associated PF pins an exte
120. t notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2008 Analog Devices Inc All rights reserved ADSP BF522 523 524 525 526 527 TABLE OF CONTENTS Genera Description 3 Portable Low Power Architecture 3 System Integration anh pPRe SUE Na v E Processor Penpherals 3 Blackin Processor Care emot ep fO 4 Memory 5 DMA Coutrollets 9 Host OMA 9 Real Time Clock secs c cossnissesdsstnesamnvacenenereancaaconesi 10 TINGED T 10 El 10 Up Down Counter and Thumbwheel Interface 10 i AT 11 Serial Peripheral Interface SPI Port 11 UART M 11 USB On The Go Dual Role Device Controller 12 TWI Controller Interface Liceo err rte tr nea 12 10 100 Ethernet MAG 12 PER 12 Parallel Peripheral Interface A V 13 Code Security with Lockbox 5 14 Power Manapgemelt 14 ADSP BF523 525 527
121. ta 12 SPORT 1 4 Select 2 Counter Down Gate PF13 PPI D13 TSCLK1 SPISEL3 CUD I O GPIO PPI Data 13 SPORT1 Transmit Serial Clock SPI Slave Select 3 Counter Up D Direction PF14 PPI D14 DT1SEC UART1TX lO GPIO PPI Data 14 SPORT1 Transmit Secondary Data UART1 Transmit PF15 PPI D15 DR1SEC UART1RX TACI3 I O GPIO PPI Data 15 SPORT1 Receive Secondary Data C UART1 Receive Alternate Capture Input 3 Port G GPIO and Multiplexed Peripherals PGO HWAIT lO GPIO Boot Host Wait C PG1 SPISS SPISEL 1 lO GPIO SPI Slave Select Input SPI Slave Select 1 C PG2 SCK GPIO SPI Clock D PG3 MISO DROSECA lO GPIO SPI Master In Slave Out Sport 0 Alternate Receive Data Secondary C PG4 MOSI DTOSECA lO GPIO SPI Master Out Slave In Sport 0 Alternate Transmit Data Secondary C 5 FS2 VO GPIO Timer1 PPI Frame Sync2 C PG6 DTOPRIA TMR2 PPI_FS3 I O GPIO SPORTO Alternate Primary Transmit Data 2 PPI Frame Sync3 C PG7 TMR3 DROPRIA UARTOTX lO GPIO Timer3 Sport 0 Alternate Receive Data Primary UARTO Transmit PG8 TMR4 RFSOA UARTORX TACI4 I O GPIO Timer 4 Sport 0 Alternate Receive Clock Frame Sync C UARTO Receive Alternate Capture Input 4 PG9 TMR5 RSCLKOA TACI5 GPIO Timer5 Sport 0 Alternate Receive Clock D Alternate Capture Input 5 PG10 TMR6 TSCLKOA TACI6 I O GPIO Timer 6 Sport 0 Alternate Transmit D Alternate Capture Input 6 PG11 TMR7 HOST_WR VO GPlO Timer7 Host D
122. te Evaluation Board For evaluation of ADSP BF523 525 527 processors use the ADSP BF527 EZ KIT Lite board available from Analog Devices Order part number ADZS BF527 EZLITE The board comes with on chip emulation capabilities and is equipped to enable software development Multiple daughter cards are available An ADSP BF526 EZ KIT Lite board is under development DESIGNING AN EMULATOR COMPATIBLE PROCESSOR BOARD TARGET The Analog Devices family of emulators are tools that every sys tem developer needs in order to test and debug hardware and software systems Analog Devices has supplied an IEEE 1149 1 JTAG Test Access Port TAP on each JTAG processor The emulator uses the TAP to access the internal features of the pro cessor allowing the developer to load code set breakpoints observe variables observe memory and examine registers The processor must be halted to send data and commands but once an operation has been completed by the emulator the processor syStenrissettutfhing at full speed with no impact on System timing To use these emulators the target board must include a header that connects the processor s JTAG port to the emulator For details on target board design issues including mechanical layout single processor connections multiprocessor scan chains signal buffering signal termination and emulator pod logic see EE 68 Analog Devices JTAG Emulation Technical Reference on the Analog Devices website www anal
123. the SPISEL1 and MISO pins By default a value of 0x85 is written to the SPI_BAUD register Boot from SPI host device BMODE 0x4 The proces sor operates in SPI slave mode and is configured to receive the bytes of the LDR file from an SPI host master agent The HWAIT signal must be interrogated by the host before every transmitted byte A pull up resistor is required on the SPISS input A pull down on the serial clock SCK may improve signal quality and booting robustness Boot from serial TWI memory EEPROM flash BMODE 0x5 The processor operates in master mode and selects the TWI slave connected to the TWI with the unique ID 0 The processor submits successive read commands to the memory device starting at internal address 0x0000 and begins clocking data into the processor The TWI memory device should comply with the Philips Bus Specifica tion version 2 1 and should be able to auto increment its internal address counter such that the contents of the memory device can be read sequentially By default a PRESCALE value of 0OxA and a TWI_CLKDIV value of 0x0811 are used Unless altered by OTP settings an memory that takes two address bytes is assumed The development tools ensure that data booted to memories that cannot be accessed by ti Blackfin 6 written intermediate storage logation aud then copied to the final destination via memory DMA Boot from TWI host BMODE 0x6 The
124. ting from byte 0 of block 0 of the NAND flash device August 2008 ADSP BF522 523 524 525 526 527 NAND flash boot supports the following features Device Auto Detection Error Detection amp Correction for maximum reliability No boot stream size limitation Peripheral DMA providing efficient transfer of all data excluding the ECC parity data Software configurable boot mode for booting from boot streams spanning multiple blocks including bad blocks Software configurable boot mode for booting from multiple copies of the boot stream allowing for han dling of bad blocks and uncorrectable errors Configurable timing via OTP memory Small page NAND flash devices must have a 512 byte page size 32 pages per block a 16 byte spare area size and a bus configuration of 8 bits By default all read requests from the NAND flash are followed by four address cycles If the NAND flash device requires only three address cycles the device must be capable of ignoring the additional address cycles The small page NAND flash device must comply with the following command set Reset OxFF Read lower half of page 0x00 Read upper half of page 94 Read spare area 0x50 For large page NAND flash devices the four byte elec tronic signature is read in order to configure the kernel for booting which allows support for multiple large page devices The fourth byte of the electronic signature must com
125. ugust 2008 ADSP BF522 523 524 525 526 527 Programmable Ethernet event interrupt supports any com bination of Any selected Rx or Tx frame status conditions PHY interrupt condition e Wakeup frame detected Any selected MAC management counter s at half full DMA descriptor error 47 MAC management statistics counters with selectable clear on read behavior and programmable interrupts on half maximum value Programmable Rx address filters including a 64 bin address hash table for multicast and or unicast frames and programmable filter modes for broadcast multicast uni cast control and damaged frames Advanced power management supporting unattended transfer of Rx and Tx frames and status to from external memory via DMA during low power sleep mode System wakeup from sleep operating mode upon magic packet or any of four user definable wakeup frame filters Support for 802 3Q tagged VLAN frames Programmable MDC clock rate and preamble suppression In operation seven unused pins may be configured as GPIO pins for other purposes 5 Because of the rich set of peripherals the processor groups the many peripheral signals to four ports Port F Port G Port H and Port J Most of the associated pins are shared by multiple signals The ports function as multiplexer controls General Purpose 1 GPIO The processor has 48 bidirectional ge
126. uired 1 a Values of are provided for comparisonland printed circuit board design considerations In Table 48 airflow measurements comply with JEDEC stan dards JESD51 2 and JESD51 6 and the junction to board measurement complies with JESD51 8 The junction to case measurement complies with MIL STD 883 Method 1012 1 All measurements use a 252 JEDEC test board Table 47 Thermal Characteristics BC 208 1 Parameter Condition Typical Unit 0 linear m s air flow 23 20 C W 1 linear m s air flow 20 20 C W Oya 2 linear m s air flow 19 20 C W 13 05 C W 6 92 C W Table 48 Thermal Characteristics 289 2 Parameter Condition Typical Unit Oja 0 linear m s air flow 34 5 C W 1 linear m s air flow 31 1 C W 2 linear m s air flow 29 8 C W 20 3 C W 8 8 C W Rev PrE Page630f72 August 2008 ADSP BF522 523 524 525 526 527 289 BALL CSP_BGA BALL ASSIGNMENT Table 49 lists the CSP_BGA balls by signal mnemonic Table 50 on Page 65 lists the CSP_BGA by ball number Table 49 289 Ball CSP_BGA Ball Assignment Alphabetically by Signal Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball Signal Ball No No No No No No No ABEO SDQMO 9 DATA9 GND VPPOTP 2 M23 N17 T7
127. ut Valid to SCK Edge Data Input Setup 11 6 11 6 9 6 9 6 ns SCK Sampling Edge to Data Input Invalid 1 5 1 5 1 5 1 5 ns Switching Characteristics tsosam SPISELx low to First SCK Edge 2 Xtsak 2 X 2 Xtsak 2x tspicum Serial Clock High Period 2 1 5 2 1 5 2 1 5 2 1 5 ns Serial Clock Low Period 2xtsak 1 5 2 1 5 2 1 5 2 1 5 ns Serial Clock Period 4 X 4 X 4 X 4 X tscik ns tuosm Last SCK Edge to SPISELx High 2 X tak 2 2 2 Xtsak ns tserpu Sequential Transfer Delay 2Xtsck 2 X 2X 2 X ns topspiom SCK Edge to Data Out Valid Data Out Delay 6 6 6 6 ns tupspiom SCK Edge to Data Out Invalid Data Out Hold 1 0 1 0 1 0 1 0 ns SPISELx OUTPUT tspscim t SCK CPOL 0 OUTPUT tspicum Lala SCK CPOL 1 OUTPUT topspipm MOSI OUTPUT 1 MISO INPUT tupspipm topspipm MOSI OUTPUT MSB LSB 0 tsspipm tuspipm NUT MSB VALID ae e LSB VALID Figure 25 Serial Peripheral Interface SPI Port Master Timing Rev PrE Page470f72 August 2008 ADSP BF522 523 524 525 526 527 Serial Peripheral Interface SPI Port Slave Timing Table 33 and Figure 26 describe SPI port slave operations Table
128. wakeup event or by asserting the RESET pin All hibernate wakeup events initiate the hardware reset sequence Individual sources are enabled by the VR CTL register The EXT WAKEx signals are provided to indicate the occurrence of wakeup events As long as is applied the register maintains its state during hibernation other internal registers and memo ries however lose their content in the hibernate state State variables may be held in external SRAM or SDRAM The SCK ELOW bit in the VR CTL register controls whether or not SDRAM operates in self refresh mode which allows it to retain its content while the processor is in hibernate and through the subsequent reset sequence Power Savings As shown in Table 5 the processor supports six different power domains which maximizes flexibility while maintaining com pliance with industry standards and conventions By isolating the internal logic of the processor into its own power domain separate from the RTC and other I O the processor can take advantage of dynamic power management without affecting the RTC or other 1 0 deyites Th re are no sequencing require ments for the various power domains but all domains must powered aecording to the appropriate Specifications table for processor Operating Conditions even if the feature peripheral is not used Table 5 Power Domains Power Domain Vpp Range All internal logic except RTC Memory USB
129. wi V Low Level Input Voltage 1 7 V 0 3 0 6 V Low Level Input Vppext Vpopmem 2 25 V 0 3 0 7 V Vi Low Level Input Voltage Vppext Vppmem 3 0 V 0 3 0 8 V View Low Level Input Voltage Vooext minimum 0 3 0 3 x V Tj Junction Temperature 289 BalLCSP 0 C 1047026 105 C T Junction Tem per MAA 208 Ball GSP_BGA 05 209 0 105 C Junction Temperature 208 Ball 40 to 85 C 40 105 Must remain powered even if the associated function is not used 21 not used power with Vppexr 3 Balls that use are DATA15 0 ADDRI9 1 0 ARE AWE AOE 53 0 ARDY SA10 SWE SCAS CLKOUT SRAS SMS SCKE These balls are not tolerant to voltages higher than The voltage for writes must only be applied when programming OTP memory There is a finite amount of cumulative time that this voltage may be applied dependent on voltage and junction temperature over the lifetime of the part Please see Table 19 on Page 32 for details 5 When not using the USB peripheral on the ADSP BF524 BF526 or terminating Vppusg on the ADSP BF522 Vppuss must be powered by Vpprxr 5 Bidirectional balls PF15 0 PG15 0 PH15 0 and input balls TDI TMS TRST CLKIN RESET NMI and BMODE3 0 of the ADSP BF522 523 524 525 526

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