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ANALOG DEVICES ADG1311 handbook

1. 600 Vpp 12V Vss 0V 500 TA 85 C Ze Vpp 15V G 9 x Vss 400 ss 15V o o z z Ei E b 5 300 o o I Lu TE d 200 Ta 40 C TA 25 C 100 0 ESTAN i 15 12 9 6 3 0 3 6 9 12 15 0 2 4 6 8 10 12 SOURCE OR DRAIN VOLTAGE V SOURCE OR DRAIN VOLTAGE V Figure 3 On Resistance as a Function of Vp Vs for Dual Supply Figure 6 On Resistance as a Function of Vp Vs for Different Temperatures Single Supply S E u Ek 9 T 15V DS Ton 5 o rd E tt z o SOURCE OR DRAIN VOLTAGE V TEMPERATURE C Figure 4 On Resistance as a Function of Vp Vs for Single Supply Figure 7 Ton Torr Times vs Temperature 0 Vpp 15V 710 vas 15V 20 Ta 25 C _ 30 S m ur E 40 Oo z z o lt E 50 E lt 60 2 a z k 70 o 6 80 90 100 8 110 8 15 10 5 0 5 10 15 10k 100k 1M 10M 100M 1G SOURCE OR DRAIN VOLTAGE V FREQUENCY Hz Figure 5 On Resistance as a Function of Vp Vs for Different Figure 8 Off Isolation vs Frequency Temperatures Dual Supply Rev 0 Page 8 of 12 ADG1311 ADG1312 ADG1313 CROSSTALK dB 1 o o 05676 018 10k 100k 1M 10M 100 FREQUENCY Hz Figure 9 Crosstalk vs Frequency
2. 0 3 V to Voo 0 3 V or 30 mA whichever occurs first GND 0 3 V to Vpp 0 3 V or 30 mA whichever occurs first 100 mA pulsed at 1 ms 10 duty cycle max 25 mA 40 C to 105 C 65 C to 150 C 150 C 112 C W 77 C W 260 C DS 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Table 4 ADG1311 ADG1312 Truth Table ADG1311 INx ADG1312 INx Switch Condition 0 1 On 1 0 Off Table 5 ADG1313 Truth Table ADG1313 INx Switch 1 4 Switch 2 3 0 Off On 1 On Off 1 Overvoltages at IN S or D are clamped by internal diodes Currentshould be limited to the maximum ratings given ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality LP ESD S
3. IN WC A AL Rev 0 Page 9 of 12 ADG1311 ADG1312 ADG1313 TEST CIRCUITS ls OFF VWs Ron Vi lps Vs Vp Y Y Figure 10 Test Circuit 1 0On Resistance Figure 11 Test Circuit 2 Off Leakage Figure 12 Test Circuit 3 On Leakage 05676 020 Vp NC NO CONNECT 05676 022 nl 05676 021 Vy ADG1312 Vout O Vin ADG1311 Cc RL 3009 35pF Vout aa 05676 023 ton torr Figure 13 Test Circuit 4 Switching Times RL CL 3000 T 35pF O Vour2 RL CL 3000 T 35pF 05676 024 Figure 14 Test Circuit 5 Break Before Make Time Delay Vin ADG1312 ON OFF Vin ADG1311 Vour AVour Qing CL x AVour Figure 15 Test Circuit 6 Charge Injection 05676 025 Rev 0 Page 10 of 12 ADG1311 ADG1312 ADG1313 NETWORK ANALYZER NETWORK ANALYZER Vour 3 Vour WITH SWITCH E OFF ISOLATION 20 log Vs 8 INSERTION LOSS 20 log Voor WITHOUT SWITCH 2 Figure 16 Test Circuit 7 Off Isolation Figure 18 Test Circuit 9 Bandwidth NETWORK ANALYZER Vout O Vous vs Jl 05676 027 ay a m CHANNEL TO CHANNEL CROSSTALK 20109 T Figure 17 Test Circuit 8 Channel to Channel Crosstalk Rev 0 Page 11 of 12 ADG1311 ADG1312 ADG1313 OUTLINE DIMENSIONS SEATING PLANE 09 Y 0 75 0 30 ry 8 gt e 0 60 0 65 0 0 45 BSC COPLANARITY 0 10 COMPLIANT TO JEDEC STANDARDS MO 153 AB Figure 19
4. 40 C to 105 C 16 Lead Narrow Body Small Outline Package SOIC NI R 16 ADG1312YRZ REEL7 40 C to 105 C 16 Lead Narrow Body Small Outline Package SOIC NI R 16 ADG1313YRUZ 40 C to 105 C 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 ADG1313YRUZ REEL7 40 C to 105 C 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 ADG1313YRZ 40 C to 105 C 16 Lead Narrow Body Small Outline Package SOIC NI R 16 ADG1313YRZ REEL7 40 C to 105 C 16 Lead Narrow Body Small Outline Package SOIC_N R 16 Z Pb free part 2005 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D05676 0 10 05 0 Bus Rev 0 Page 12 of 12
5. The drain leakage current with the switch off Ip Is On The channel leakage current with the switch on Vint The maximum input voltage OH OM Visi The minimum input voltage for Logic 1 Tint Ima The input current of the digital input Cs Off The off switch source capacitance measured with reference to ground C Off The off switch drain capacitance measured with reference to ground C Cs On The on switch capacitance measured with reference to ground Cw The digital input capacitance ton The delay between applying the digital control input and the output switching on See Figure 13 torr The delay between applying the digital control input and the output switching off See Figure 13 Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching Off Isolation A measure of unwanted signal coupling through an off switch Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance Bandwidth The frequency which the olo is attenuated by 3 dB On Response The frequency response of the on switch Insertion Loss The loss due to the on resistance of the switch Rev 0 Page 7 of 12 ADG1311 ADG1312 ADG1313 TYPICAL PERFORMANCE CHARACTERISTICS
6. 0 Vss 15 V 10 GND 0 V unless otherwise noted Table 1 Y Version Parameter 25 C 40 Cto 105 C Unit Test Conditions Comments ANALOG SWITCH Analog Signal Range Voo to Vss V On Resistance Ron 130 230 Otyp Vs 10V Is 1 mA Figure 10 200 Q max Voo 13 5 V Vss 13 5 V On Resistance Match Between 5 Otyp Vs 10V ls 1mA Channels ARon 10 Q max On Resistance Flatness RELATON 25 Q typ Vs 5 V 0 V 5 V Is 1 mA 65 Q max LEAKAGE CURRENTS Voo 16 5 V Vss 16 5 V Source Off Leakage Is Off 10 nA typ Vs 10 V Vo x10 V Figure 11 Drain Off Leakage Ip Off 10 nA typ Vs 10V Vo x 10 V Figure 11 Channel On Leakage lp Is On 10 nA typ Vs Vp 10 V Figure 12 DIGITAL INPUTS Input High Voltage Vinx 2 0 V min Input Low Voltage Viu 0 8 V max Input Current lint or link 0 005 HA typ Vin Vine Or Vin ST 1 A uA mak Digital Input Capacitance N i 4 25 i pF typ N j DYNAMIC CHARACTERISTICS2 ton 105 ns typ Ri 300 O Ci 35 pF 125 180 ns max Vs 10 V Figure 13 torr 40 ns typ Ri 300 O C 35 pF 50 60 ns max Vs 10 V Figure 13 Break Before Make Time Delay to 25 ns typ Ri 300 0 C 35 pF ADG1313 Only 10 ns min Vs Vs2 10V Figure 14 Charge Injection 2 pC typ Vs 0V Rs 00 C_ 1 nF Figure 15 Off Isolation 80 dB typ Ri 500 CL 5 pF f 1 MHz Figure 16 Channel to Channel Crosstalk 90 dB typ Ri 500 CL 5 pF f 1 MHz Figure 17 3 dB Bandwidth 600 MHzty
7. 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 Dimensions shown in millimeters 10 00 0 3937 n 9 80 0 3858 a 4 00 0 1575 9 6 20 0 2441 3 80 0 1496 i s 5 80 0 2283 ps 1 27 0 0300 1 75 0 0689 27 0 1 75 0 0689 0 50 0 0197 BSC 1 35 0 0531 625 09098 45 0 25 0 0098 0 70 0 0039 MET L gt e OR amp mie COPLANARITY Rad BEA T 0 25 0 0098 0 1 27 0 0500 0 10 0 31 0 0122 0 17 0 0067 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 012 AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 20 16 Lead Standard Small Outline Package SOIC N Narrow Body R 16 Dimensions shown in millimeters and inches ORDERING GUIDE Model Temperature Range Package Description Package Option ADG1311YRUZ 40 C to 105 C 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 ADG1311YRUZ REEL7 40 Gto M05 G 16 Lead Thin Shrink SmalFOutline Package TSSOP RU 16 ADG1311YRZ 400 W M T 16 Lead Narrow Body Small Outline Package TSOIC_N R 16 ADG1311YRZ REEL7 40 C to 105 C 16 Lead Narrow Body Small Outline Package SOIC_N R 16 ADG1312YRUZ 40 C to 105 C 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 ADG1312YRUZ REEL7 40 C to 105 C 16 Lead Thin Shrink Small Outline Package TSSOP RU 16 ADG1312YRZ
8. ANALOG DEVICES 15 V 12 V Quad SPST Switches ADG1311 ADG1312 ADG1313 FEATURES FUNCTIONAL BLOCK DIAGRAM 33 V supply range Fully specified at 12 V 15 V 130 Q on resistance No V supply required 3 V logic compatible inputs Rail to rail operation 16 lead TSSOP and 16 lead SOIC Typical power consumption 0 03 uW APPLICATIONS Signal switching Battery powered systems 05676 001 SWITCHES SHOWN FOR A LOGIC 1 INPUT Communication systems Figure t Audio video signal routing GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG1311 ADG1312 ADG1313 are monolithic CMOS 1 3 V logic compatible digital inputs Vm 2 0 V Vu 0 8 V devices containing four independently selectable switches 2 No Vi logic power supply required desigosd ona CMOS protes 3 16 lead TSSOP and ry packages The ADG1311 ADG1312 ADG1313 contain four RAT 1 1 single pole single throw SPST switches The ADG1311 and ADG1312 differ only in that the digital control logic is inverted The ADG1311 switches are turned on with Logic 0 on the appro priate control input while Logic 1 is required for the ADG1312 The ADG1313 has two switches with digital control logic similar to the ADG1311 the logic is inverted on the other two switches The ADG1313 exhibits break before make switching action for use in multiplexer applications Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies I
9. ENSITIVE DEVICE Rev 0 Page 5 of 12 ADG1311 ADG1312 ADG1313 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADG1311 ADG1312 ADG1313 TOP VIEW 05676 002 NC NO CONNECT Figure 2 SOIC TSSOP Pin Configuration Table 6 Pin Function Descriptions Pin No Mnemonic Description 1 IN1 Logic Control Input 2 D1 Drain Terminal Can be an input or output 3 S1 Source Terminal Can be an input or output 4 Vss Most Negative Power Supply Potential 5 GND Ground 0 V Reference 6 S4 Source Terminal Can be an input or output 7 D4 Drain Terminal Can be an input or output 8 IN4 Logic Control Input 9 IN3 LagieGontrolinput J 10 D3 i Drain Yerminal Gan be an input or output j 11 S3 Source Terminal Can Deaf inputer output 12 NC No Connection 13 Voo Most Positive Power Supply Potential 14 S2 Source Terminal Can be an input or output 15 D2 Drain Terminal Can be an input or output 16 IN2 Logic Control Input Rev 0 Page 6 of 12 ADG1311 ADG1312 ADG1313 TERMINOLOGY Ibo The positive supply current Iss The negative supply current Vo Vs The analog voltage on Terminal D and Terminal S Ron The ohmic resistance between D and S RELAT ON Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range Is Off The source leakage current with the switch off Ip Off
10. max Digital Input Capacitance Cin 3 pF typ DYNAMIC CHARACTERISTICS ton 120 ST nstypy JAR B00 0 CH 35 pF 15 210 ns max LAE torr 45 ns typ Ri 300 Q C 35 pF 65 80 ns max Vs 8V Figure 13 Break Before Make Time Delay to 50 ns typ Ri 300 O C 35 pF ADG1313 Only 10 ns min Vs1 Vs2 8 V Figure 14 Charge Injection 2 pC typ Vs 6V Rs 00 C 1 nF Figure 15 Off Isolation 80 dB typ R 500 CL 5 pF f 1 MHz Figure 16 Channel to Channel Crosstalk 90 dB typ RL 500 CL 5 pF f 1 MHz Figure 17 3 dB Bandwidth 500 MHztyp RL 500 C 5 pF Figure 18 Cs Off 5 pF typ Co Off 5 pF typ Cp Cs On 10 pF typ POWER REQUIREMENTS Voo 13 2 V Ibo 0 001 uA typ Digital inputs 0 V or Voo 1 0 HA max Ibo 220 uA typ Digital inputs 5 V 320 HA max 1 Temperature range for Y Version is 40 C to 105 C 2 Guaranteed by design not subject to production test Rev 0 Page 4 of 12 ADG1311 ADG1312 ADG1313 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 3 Parameter Rating Voo to Vss 35V Vop to GND 0 3V to 25 V Vss to GND 0 3 V to 25V Analog Inputs Digital Inputs Peak Current S or D Continuous Current per Channel S or D Operating Temperature Range Automotive Storage Temperature Range Junction Temperature 16 Lead TSSOP Oja Thermal Impedance 4 layer board 16 Lead SOIC Bu Thermal Impedance Reflow Soldering Peak Temperature Pb free Vss
11. n the off condition signal levels up to the supplies are blocked Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2005 Analog Devices Inc All rights reserved ADG1311 ADG1312 ADG1313 TABLE OF CONTENTS Features EE EE DE GE e 1 Applications ito en e e HR UR RED 1 Functional Block Diagram see 1 General Description esse sesse se ee sege ee oe gek eg gek eek ge ee eek eke 1 Product Highlights tetti etm Ee 1 Specifications N cited 3 Dual SupplYs EES ei DE EG LEAD 3 Ui UR OE Oe ON ias 4 REVISION HISTORY 10 05 Revision 0 Initial Version Rev 0 Page 2 of 12 Absolute Maximum Ratings ESD Caution Terminology Test Circuits Outline Dimensions Ordering Guide Pin Configuration and Function Descriptions Typical Performance Characteristics ADG1311 ADG1312 ADG1313 SPECIFICATIONS DUAL SUPPLY Vpp 15 V 1
12. p R 50Q C 5 pF Figure 18 Cs Off 5 pF typ Cp Off 5 pF typ Cp Cs On 10 pF typ POWER REQUIREMENTS Voo 16 5 V Vss 16 5 V Ibo 0 001 HA typ Digital inputs 0 V or Voo 1 0 HA max Ipp 220 HA typ Digital inputs 5 V 320 HA max Iss 0 001 HA typ Digital inputs 0 V or Voo 1 0 HA max Iss 0 001 HA typ Digital inputs 5 V 1 0 HA max Temperature range for Y Version is 40 C to 105 C Guaranteed by design not subject to production test Rev 0 Page 3 of 12 ADG1311 ADG1312 ADG1313 SINGLE SUPPLY Vpp 12 V 10 Vss 0 V GND 0 V unless otherwise noted Table 2 Y Version Parameter 25 C 40 C to 105 C Unit Test Conditions Comments ANALOG SWITCH Analog Signal Range OV to Voo V On Resistance Ron 325 520 QO typ Vs OV 10V Ils 1 mA Figure 10 500 O max Voo 10 8 V Vss OV On Resistance Match Between 10 Q typ Vsz0V 10V lsz 1mA Channels ARon 15 O max On Resistance Flatness RELATON 65 Q typ Vs 3 V 6 V 9 V ls 1 mA LEAKAGE CURRENTS Voo 13 2 V Vss 0 V Source Off Leakage Is Off 10 nA typ Vs 1 V 10 V Vo 10 V 1 V Figure 11 Drain Off Leakage Ip Off 10 nA typ Vs 1 V 10V Vo 10 V 1 V Figure 11 Channel On Leakage lp Is On 10 nA typ Vs Vp 1 V or 10 V Figure 12 DIGITAL INPUTS Input High Voltage Vin 2 0 V min Input Low Voltage Vin 0 8 V max Input Current lint or linn 0 001 HA typ Vin Vine Or Vink 0 1 HA

ANALOG DEVICES ADG1311 handbook

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