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ANALOG DEVICES ADG3242 handbook

1. Figure 34 3 3 V to 1 8 V Voltage Translation SEL 0V Rev A Page 12 of 16 BUS ISOLATION A common requirement of bus architectures is low capacitance loading of the bus Such systems require bus bridge devices that extend the number of loads on the bus without exceeding the spec ifications Because the ADG3242 is designed specifically for applications that do not need drive yet require simple logic func tions it solves this requirement The device isolates access to the bus thus minimizing capacitance loading BUS BACKPLANE BUS SWITCH LOCATION 04309 034 Figure 35 Location of Bus Switched in a Bus Isolation Application HOT PLUG AND HOT SWAP ISOLATION The ADG3222 is suitable for hot swap and hot plug applications The output signal of the ADG3242 is limited to a voltage that is below the Vcc supply as shown in Figure 30 Figure 32 and Figure 34 Thus the switch acts like a buffer to take the impact from the hot insertion protecting vital and expensive chipsets from damage 1 In hot plug applications the system dhnndt be shutidown when new hardware is being added To overcome this a bus switch can be positioned on the backplane between the bus devices and the hot plug connectors The bus switch is turned off during hot plug Figure 36 shows a typical example of this type of application CARD i CARD I O PLUG IN CARD I O CARD 2 04309 035 Figure 36 ADG3242 in a Hot Plug Application
2. 0 0 02 0 04 0 06 0 08 0 10 lo A Figure 13 Output Low Characteristic 3 0 Ta 25 C Va Vcc 2 5 BE 0 2 0 Vcc SEL 3 3V 1 5 1 0 ygg SEL 2 5V a 0 5 Vcc 33V SEL 0V 0 0 10 0 08 0 06 0 04 0 02 0 lo A Figure 14 Output High Characteristic Ta 25 C SEL Vec ON OFF CL 1nF 0 0 5 1 0 1 5 2 0 2 5 3 0 ValVg V Figure 15 Charge Injection vs Source Voltage 04309 012 04309 013 04309 014 ATTENUATION dB ATTENUATION dB ATTENUATION dB Ta 25 C Vcc 3 3V 2 5V SEL Voc Vin 0dBm N W ANALYZER RL Rg 500 FREQUENCY MHz Figure 16 Bandwidth vs Frequency Ta 25 C Voc 3 3V 2 5V SEL Voc Vin 0dBm N W ANALYZER RL Rg 500 0 03 0 1 1 10 100 1000 FREQUENCY MHz Figure 17 Crosstalk vs Frequency 0 TA 25 C 10 Voc 3 3VI2 5V SEL Voc 20 Vin 0dBm N W ANALYZER 30 f R Rs 500 40 50 60 70 80 90 100 0 1 1 10 100 1000 FREQUENCY MHz Figure 18 Off Isolation vs Frequency 04309 015 04309 016 04309 017 Rev A Page 8 of 16 TIME ns TIME ns JITTER ps p p ENABLE A TUIS END TEMPERATUR
3. There are many systems such as docking stations PCI boards for servers and line cards for telecommunications switches that require the ability to handle hot swapping If the bus can be isolated prior to insertion or removal there is more control over the hot swap event This isolation can be achieved using bus switches The bus switches are positioned on the hot swap card between the con nector and the devices During hot swap the ground pin of the hot swap card must connect to the ground pin of the backplane before connecting to any other signal or power pins ANALOG SWITCHING Bus switches are used in many analog switching applications for example video graphics Bus switches can have lower on resistance smaller on and off channel capacitance and better frequeney performance than K l analog counterparts The bus switch channel itself gonsisting solely of an NMOS switch limits the operating voltage see Figure 4 for a typical plot but in many cases this does not present an issue HIGH IMPEDANCE DURING POWER UP POWER DOWN To ensure the high impedance state during power up or power down BE must be tied to Vcc through a pull up resistor The minimum value of the resistor is determined by the current sink ing capability of the driver Rev A Page 13 of 16 OUTLINE DIMENSIONS E 2 90 BSC 1 60 BSC 2 80 BSC PIN 1 INDICATOR E EJ amp 0 65 BS
4. 300 150 150 mV C 50 30 30 pF Vr 1 5 0 9 0 9 V Rev A Page 11 of 16 BUS SWITCH APPLICATIONS MIXED VOLTAGE OPERATION LEVEL TRANSLATION Bus switches provide an ideal solution for interfacing between mixed voltage systems The ADG3242 is suitable for applications where voltage translation from 3 3 V technology to a lower voltage technology is needed This device translates from 3 3 V to 1 8 V from 2 5 V to 1 8 V or from a bidirectional 3 3 V directly to 2 5 V Figure 28 shows a block diagram ofa typical application in which a user needs to interface between a 3 3 V ADC and a 2 5 V micro processor The microprocessor does not have 3 3 V tolerant inputs therefore placing the ADG3242 between the two devices allows the devices to communicate easily The bus switch directly connects the two blocks therefore introducing minimal propagation delay timing skew or noise 3 3V 3 3V 2 5V Q Oo 2 5V MICROPROCESSOR 3 3V ADC Figure 28 Level Translation Between a 3 3 V ADC and a 2 5 V Microprocessor 04309 027 3 3 V TO 2 5 V TRANSLATION When Vcc is 3 3 V SEL 3 3 V and the input signalvangedsy 0 V to Vcc the maximum output Sigdal iscfaniped to Within al voltage threshold below the Vcc Supply In this case the output is limited to 2 5 V as shown in Figure 30 This device can be used for translation from 2 5 V to 3 3 V devices and also between two 3 3 V devices 3 3V o 3 3V E gt 2 5V 2 5V 2
5. 5V Figure 29 3 3 V to 2 5 V Voltage Translation SEL Vec 04309 028 Vout 3 3V SUPPLY SEL 3 3V ov SWITCH 3 3V INPUT Figure 30 3 3 V to 2 5 V Voltage Translation SEL Vcc 04309 029 2 5 V TO 1 8 V TRANSLATION When Vcc is 2 5 V SEL 2 5 V and the input signal range is 0 V to Vcc the maximum output signal is also clamped within a voltage threshold below the Vcc supply In this case the output is limited to approximately 1 8 V as shown in Figure 32 2 5V 2 5V 5 1 8V Figure 31 2 5 V to 1 8 V Voltage Translation SEL 2 5 Vcc 04309 030 Vour 2 5V SUPPLY SEL 2 5V SWITCH OUTPUT ViN ov SWITCH 2 5V INPUT Figure 32 2 5 V to 1 8 V Voltage Translation SEL Vcc 3 3 WTO NSIV VAT The ADG3242 offers th option Of interfacing between a 3 3 V device and a 1 8 V device This is possible through use of the SEL pin The SEL pin is an active low control pin SEL activates inter nal circuitry in the ADG3242 that allows voltage translation between 3 3 V devices and 1 8 V devices 04309 031 When Vcc is 3 3 V and the input signal range is 0 V to Vcc the maximum output signal is clamped to 1 8 V as shown in Figure 34 To do this the SEL pin must be tied to Logic 0 If SEL is unused it can be tied directly to Vcc 3 3V 3 3V B 1 8V Figure 33 3 3 V to 1 8 V Voltage Translation SEL 0V 04309 032 Vout 3 3V SUPPLY SEL 0V 1 8V 55 Fo 35 no Vin ov SWITCH 3 3V INPUT 04309 033
6. ANALOG DEVICES 2 5 V 3 3 V 2 Bit Common Control Level Translator Bus Switch FEATURES 225 ps propagation delay through the switch 4 5 Q switch connection between ports Data rate 1 5 Gbps 2 5 V 3 3 V supply operation Selectable level shifting translation Level translation 3 3 V to 2 5 V 3 3 V to 1 8 V 2 5 V to 1 8 V Small signal bandwidth 710 MHz 8 lead SOT 23 package APPLICATIONS 3 3 V to 2 5 V voltage translation 3 3 V to 1 8 V voltage translation 2 5 V to 1 8 V voltage translation Bus switching Bus isolation Hot swap Hot plug Analog switch applications i 4 I GENERAL DESCRIPTION The ADG3242 is a 2 5 V or 3 3 V 2 bit 2 port common control digital switch It is designed on a low voltage CMOS process and provides low power dissipation yet gives high switching speed and very low on resistance This allows the inputs to be connected to the outputs without additional propagation delay or generating additional ground bounce noise These switches are enabled by means of a common bus enable BE input signal This digital switch allows a bidirectional signal to be switched when on In the off condition signal levels up to the supplies are blocked This device is ideal for applications requiring level translation When operated from a 3 3 V supply level translation from 3 3 V inputs to 2 5 V outputs is allowed Similarly if the device is oper ated from a 2 5 V supply and 2 5 V inputs are applied the devi
7. C 1 95 1 30 BSC 115 0 90 CES 145MAX 0 22 Y i 008 FT 0 60 F 0 38 8 gt 045 SASMAN 0227 l sEATING 0 30 PLANE 0 COMPLIANT TO JEDEC STANDARDS MO 178 BA Figure 37 8 Lead Small Outline Transistor Package SOT 23 RJ 8 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ADG3242BRJ R2 40 C to 85 C 8 Lead Small Outline Transistor SOT 23 RJ 8 SCA ADG3242BRJ REEL 40 C to 85 C 8 Lead Small Outline Transistor SOT 23 RJ 8 SCA ADG3242BRJ REEL7 40 C to 85 C 8 Lead Small Outline Transistor SOT 23 RJ 8 SCA ADG3242BRJZ REEL7 40 C to 85 C S Lead Small Outline Transistor SOT 23 RJ 8 SOU ADG3242BCZ SF3 40 P uA Die Chip T Z Pb free part Rev A Page 14 of 16 NOTES ww BDI C com ALI NOTES INN D ALI 2006 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners C04309 0 9 06 A DEVICES www analo g com Rev A Page 16 of 16
8. E C Figure 19 Enable Disable Time vs Temperature 4 0 3 5 3 0 ENABLE 2 5 DISABLE 1 5 40 20 0 0 60 80 20 4 TEMPERATURE C Figure 20 Enable Disable Time vs Temperature 100 Voc SEL 3 3V 90 Vin 1 5V p p 20dB ATTENUATION Figure 21 Jit 1 1 1 3 1 5 1 7 1 9 DATA RATE Gbps ter vs Data Rate PRBS 31 04309 018 04309 019 04309 020 EYE WIDTH 100 95 90 Vcc SEL 3 3V Vin 1 5V p p 85 20dB ATTENUATION 80 75 70 65 60 55 EYE WIDTH CLOCK PERIOD JITTER p p CLOCK PERIOD x 100 50 0 5 07 0 9 1 1 1 3 1 5 1 7 1 9 DATA RATE Gbps Figure 22 Eye Width vs Data Rate PRBS 31 TET Voc 3 3V 50mV DIV SEL 3 3V ATTENUATION 200ps DIV Vin 1 5V p p Ta 25 C 04309 022 Figure 23 Eye Pattern 1 5 Gbps Vcc 3 3 V PRBS 31 04309 021 Rev A Page 9 of 16 Voc 2 5V 20mVIDIV SEL 2 5V ATTENUATION 200ps DIV Vin 1 5V p p Ta 25 C Figure 24 Eye Pattern 1 244 Gbps Vcc 2 5 V PRBS 31 04309 023 TERMINOLOGY Voc Positive power supply voltage GND Ground 0 V reference Vina Minimum input voltage for Logic 1 Vint Maximum input voltage for Logic 0 k Input leakage current at the control inputs Ioz Off state leakage current It is the maximum leakage current at the switch pin i
9. E 1 Bus Switch Applications aaaaaaaaacasaaaaaa navssnunnnnnnnnaaaanaaananannnnnnnna 12 Functional Block Diagram serene 1 Mixed Voltage Operation Level Translation 12 General Description eerte tette 1 3 3 V to 2 5 V Translation serere 12 Product Highlights oe teet tens 1 2 5 V to 1 8 V Translafi onee 12 REVISION HIStory sss Ss 2 3 3 V to 1 8 V Translation seen 12 Specificationss Sau TL LC UE 3 BUI cos E 13 Absolute Maximum Ratings seen 4 Hot Plug and Hot Swap Isolation sse 13 ESD CON cine it et ede 4 Analog Switching tete ite iare 13 Pin Configurations and Function Descriptions 5 High Impedance during Power Up Power Down 13 Typical Performance Characteristics sss 6 O tline Dimensions tete tei iR te 14 Terminology ionic neenon e nU PSP ERI terrm 10 Ordering Guide cien easet ot ie retten 14 REVISION HISTORY T 4 9 06 Rev 0 to Rev A NWV Updated FOMA eite these ttt Universal Added YA WI Mm 5 Changes to the Ordering Guide sss 14 8 03 Revision 0 Initial Version Rev A Page 2 of 16 SPECIFICATIONS Voc 2 3 V to 3 6 V GND 0 V all specifications Tmn to Tmax unless otherwise noted Table 1 B Version Para
10. ESD A Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality NAL Rev A Page 4 of 16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SEL Vcc BE ADI DIE MARK BE 1 8 Voc AO Ao 2 Beane SEL ADG3242 At 5 NGO to scale BO TOP VIEW Not to Scale 8 Not to Scale GND 4 5 B1 amp E BO Al B1 GND R Figure 2 Pin Configuration Figure 3 Die Pad Configuration Die size 550 um x 820 um Table 3 Pin Function Descriptions Pin No Mnemonic Description 1 BE Bus Enable Active Low 2 AO Port AO Input or Output 3 AT Port AT Input or Output 4 GND Ground 0 V Reference 5 B1 D Port BT put or Output 6 BO j Port BO Input Or Output 7 SEL E Level Translation Select 8 Vcc Positive Power Supply Voltage Table 4 Die Pad Coordinates Measured from the Center of the Die Mnemonic X pm Y pm BE 93 303 AO 102 150 Al 168 139 GND 126 266 B1 88 247 BO 168 121 SEL 111 4279 Vcc 7 303 Table 5 Truth Table BE SEL Function L L AO BO A1 B1 3 3 V to 1 8 V Level Shifting L H AO BO A1 B1 3 3 V to 2 5 V 2 5 V to 1 8 V Level Shifting H X Disconnect SEL 0 V only when Voo 3 3 V 10 Rev A Page 5 of 16 TYPICAL PERFORMANCE CHARACTERISTICS Ron Ron Ron Q Ta 25 C
11. L Vcc Va 1 7 V lea 8 mA 12 28 Q Vcc 2 3 V SEL Vcc Va 0 V lsa 8 mA 5 9 Q Vcc 2 3 V SEL Vcc Va 1 V lsa 8 mA 9 18 Q V 3 V SEL 0 V Va 0 V lg 8 mA 5 8 Q Vc 3 V SEL 0 V Va 1 V lsa 8 mA 12 Q On Resistance Matching ARon Vcc 3 V SEL Vcc Va 0 V la 8 mA 0 1 0 5 Q Vcc 3 V SEL 0 V Va 0 V la 8 mA 0 1 0 5 Q POWER REQUIREMENTS Vcc 2 3 3 6 V Quiescent Power Supply Current Icc Digital inputs 0 V or Vcc SEL Vcc 0 01 1 uA Digital inputs 0 V or Vcc SEL 0 V 0 1 0 2 mA Increase in Icc per Input Alcc Vcc 3 6 V BE 3 0 V SEL Vec 0 15 8 uA 1 Temperature range is as follows B version 40 C to 85 C Typical values are at 25 C unless otherwise stated 3 Guaranteed by design not subject to production test 4 The digital switch contributes no propagation delay other than the RC delay of the typical Ron of the switch and the load capacitance when driven by an ideal voltage source Because the time constant is much smaller than the rise fall times of typical driving signals it adds very little propagation delay to the system Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side gt Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF See Timing Measuremen
12. TES as SEL Vcc cc 30 25 Voc 3 3V 20 15 10 Vec 3 6V 5 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 ValVg V Figure 4 On Resistance vs Input Voltage 0 0 5 1 0 1 5 2 0 2 5 3 0 ValNg V Figure 5 On Resistance vs Input Voltage 40 TA F 2c Vec 3V 35 SEL 0V 30 25 Vec 3 3V 20 15 Voc 3 6V 10 5 0 0 0 5 1 0 13 2 0 2 5 3 0 3 5 ValVg V Figure 6 On Resistance vs Input Voltage 04309 003 04309 004 04309 005 Row Q ValVg V Figure 7 On Resistance vs Input Voltage for Different Temperatures 15 Row Q 0 0 5 1 0 1 2 ValVg V Figure 8 On Resistance vs Input Voltage for Different Temperatures 3 0 2 5 2 0 1 5 Vout V 1 0 0 5 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 ValVg V Figure 9 Pass Voltage vs Vcc Rev A Page 6 of 16 04309 006 04309 007 04309 008 Vout V 0 0 5 1 0 1 5 2 0 2 5 3 0 ValVg V Figure 10 Pass Voltage vs Vcc Vout V 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 ValVg V Figure 11 Pass Voltage vs Vcc lcc HA 0 5 10 15 20 25 30 35 40 45 50 ENABLE FREQUENCY MHz Figure 12 lcc vs Enable Frequency 04309 009 04309 010 04309 011 Vout V Rev A Page 7 of 16 Vout V Qs pC
13. ce translates the outputs to 1 8 V In addition a level translating select pin SEL is indluded When SEL is low Vcc is reduced Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM A l Bo Al B1 BE E Figure 1 NAL internally allowing for level translation between 3 3 V inputs and 1 8 V outputs This makes the device suitable for applications requiring level translation between different supplies such as converter to DSP microcontroller interfacing PRODUCT HIGHLIGHTS 1 3 3 V or 2 5 V supply operation 2 Extremely low propagation delay through switch 3 4 5 Q switches connect inputs to outputs 4 Level voltage translation 5 Tiny SOT 23 package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 02006 Analog Devices Inc All rights reserved TABLE OF CONTENTS Features IA AA a a 1 Timing Measurement Information see 11 AP PlICALLONS iro te e RHEIN
14. meter Symbol Conditions Min Typ Max Unit DC ELECTRICAL CHARACTERISTICS Input High Voltage VinH Vcc 2 7 V to 3 6 V 2 0 V Vcc 2 3 V to 2 7 V 1 7 V Input Low Voltage Vint Vc 2 7 V to 3 6 V 0 8 V Vcc 2 3 V to 2 7 V 0 7 V Input Leakage Current h 0 01 1 uA Off State Leakage Current loz 0 lt A B lt Vic 0 01 1 uA On State Leakage Current 0 lt A B lt Vec 0 01 1 uA Maximum Pass Voltage Vp Va Vs Vcc SEL 3 3 V lo 5 uA 2 0 2 5 2 9 V Va Vs Vcc SEL 2 5 V lo 5 pA 15 18 2 1 V Va Ve Vc 3 3 V SEL O V lo 5 pA 1 5 1 8 2 1 V CAPACITANCE3 A Port Off Capacitance Ca OFF f 1 MHz 3 5 pF B Port Off Capacitance Cs OFF f 1 MHz 3 5 pF A B Port On Capacitance Ca Ce ON f 1 MHz 7 pF Control Input Capacitance Cn f 1 MHz 4 pF SWITCHING CHARACTERISTICS Propagation Delay A to B or B to A tro tut teLH C 50 pF Vec SEL 3V 0 225 ns Propagation Delay Matching 5 ps Bus Enable Time BE to A or B5 tezi tezi poe Vec 3 0 V to 3 6 V SEL Vcc 1 32 4 6 ns Vec 28 0 V to 3 6 SEE QW WF 1 3 4 ns UM Vcc 2 3 Mto 2 7 SEL cc 1 3 4 ns Bus Disable Time BE to A or B texz teiz Vcc 3 0 V to 3 6 V SEL Vc 1 3 4 ns V 3 0 V to 3 6 V SEL 0 V 1 2 5 3 8 ns Vc 2 3 V to 2 7 V SEL Vcc 1 2 5 34 ns Maximum Data Rate Vcc SEL 3 3 V V Vs 2 V 1 5 Gbps Channel Jitter Vcc SEL 3 3 V V Vs 2 V 45 ps p p DIGITAL SWITCH On Resistance Ron Vcc 3 V SEL Vcc Va OV Isa 8 mA 4 5 8 Q Vcc 3 V SE
15. n the off state Ior On state leakage current It is the maximum leakage current at the switch pin in the on state Vr Maximum pass voltage The maximum pass voltage relates to the clamped output voltage of an NMOS device when the switeh input voltage is equal to the supply Ve rey Ron Ohmic resistance offered by a switch in the on state It is measured at a given voltage by forcing a specified amount of current through the switch ARon On resistance match between any two channels that is Ron max to Ron min Cx OFF Off switch capacitance Cx ON On switch capacitance Cm Control input capacitance This consists of BE and SEL Icc Quiescent power supply current This current represents the leakage current between the Vcc and ground pins It is measured when all control inputs are at logic high or low level and the switches are off Alcc Extra power supply current component for the EN control input when the input is not driven at the supplies tern teur Data propagation delay through the switch in the on state Propaga tion delay is related to the RC time constant Ron x Ci where Ci is the load capacitance trzy tezi Bus enable times These are the times taken to cross the Vr in response to the control signal BE truz triz Bus disable times These are the times taken to place the switch in the high impedance off statein response to the control signal They re nfeasufed as the time tip for the out
16. put voltage to change by Vwfrom the originaleqdiescent level with reference to the logic level transition at the control input See Figure 27 for enable and disable times Max Data Rate Maximum rate at which data can be passed through the switch Channel Jitter Peak to peak value of the sum of the deterministic and random jitter of the switch channel Rev A Page 10 of 16 TIMING MEASUREMENT INFORMATION For the following load circuit and waveforms the notation that is used is Vin and Vour where Vin Va and Vour VB or Vm Vs and Vour Va Vcc PULSE GENERATOR NOTES 1 PULSE GENERATOR FOR ALL PULSES tg 2 5ns tp lt 2 5ns FREQUENCY lt 10MHz 2 CL INCLUDES BOARD STRAY AND LOAD CAPACITANCES 3 RT IS THE TERMINATION RESISTOR SHOULD BE EQUAL TO Zout OF THE PULSE GENERATOR Figure 25 Load Circuit CONTROL INPUT BE Vour Figure 26 Propagation Delay sw1 ENABLE CONTROL INPUT BE l 2 x Vcc Vour Vec 1 ViN 70V SW1 Q 2Vcc GND i Table 6 Switch Position MU de m Vout Vin Vec sw1 GND Vr Vu VA 0V ov Figure 27 Enable and Disable Times DISABLE VINH EP com Vr ov tpuz lt gt 04309 026 5 Test S1 tpiz tezi 2xVcc z tpuz tezH GND 04309 025 Table 7 Test Conditions L Symbol Vc 3 3 V 0 3 V SEL Vcc Vcc 2 5 V 0 2 V SEL Vcc Vc 3 3 V 0 3 V SEL 0 V Unit R 500 500 500 Q Va
17. t Information section 7 This current applies to the Control Pin BE only The A and B ports contribute no significant ac or dc currents as they transition Rev A Page 3 of 16 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational Table 2 Parameter Rating Vcc to GND 0 5 V to 4 6 V Digital Inputs to GND 0 5 V to 4 6 V DC Input Voltage 0 5 V to 4 6 V DC Output Current Operating Temperature Range Industrial B Version Storage Temperature Range Junction Temperature Osa Thermal Impedance Lead Temperature Soldering 10 sec IR Reflow Peak Temperature 20 sec section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 25 mA per channel 40 C to 4 85 C 65 C to 4 150 C 206 C W 300 C 235 C 150 C Only one absolute maximum rating can be applied at any one time ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge J without detection Although this product features A patented or proprietary protection circuitry damage may occur on devices subjected to high energy

ANALOG DEVICES ADG3242 handbook

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