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ANALOG DEVICES ADM6820 handbook

1. 05133 013 Figure 19 ADM6820 Applications Diagram When the primary supply is above the desired threshold the ADM6819 ADM6820 are designed to control the N channel FET in the secondary power path to enable the secondary supply The GATE pin is held low while both Vcc and Vcez are below the undervoltage threshold ensuring that the FET is held off When Vcc or Vcc is above UVLO and the primary supply is above the desired level dictated by the resistor divider to the VSET pin the external FET is driven on after the delay has expired An internal charge pump enhances the external FET A FET with a low drain source resistance and low Vry should be chosen to reduce voltage drop across the drain source when the FET is fully enhanced Either supply may act as the primary source if Vcc or Vcc is greater that 2 95 V A decoupling capacitor of typically 100 nF should be used on whichever Vcc is the main supply SETV PIN The ADM6819 ADM6820 enable a supply after a monitored supply voltage exceeds a programmed threshold This threshold is programmed by a R1 R2 resistor divider on the SETV pin Once the voltage on SETV exceeds the 0 618 V threshold the FET switches on after the delay timer expires On the ADM6820 this delay is programmable using a capacitor on the SETD pin On the ADM6819 this delay is fixed at 300 ms and the EN pin must be valid high to begin the timer The required turn on voltage is calculated by the following equation
2. R1 R2 VTRIP Vrn 1 where VTRIP is the minimum turn on voltage at the supply being monitored Vry 0 618 V High value resistors can be used because the SETV input current is typically 10 nA EN PIN The ADM6819 has an enable EN pin connected to the input of a second comparator which is identical to that on the VSET pin EN can be used as a digital input provided the signal Vor is belows0 6 VeAlternatively the d A input can be used to validate a Second supply THejfixed 300 ms timer does not begin counting until both SETV and EN are above the threshold As a result the output is not enabled until this timer has expired GATE PIN The internal charge pump is capable of driving the gate of an N channel MOSFET with no external capacitors This ensures that the MOSFET is enhanced to provide a minimum voltage drop across the MOSFET thus reducing the voltage drop across the FET This charge pump is designed to drive the high imped ance capacitive load of a MOSFET gate input The GATE pin should not be resistively loaded because it reduces the gate drive capability During undervoltage lockout GATE is held to GND SETD PIN The ADM6820 features a capacitor adjustable sequencing delay A capacitor connected to the SETD pin determines the length of the sequencing delay The sequencing delay can be calculated by the following equation tprray s 2 652 x 10 x CSET The ADM6819 has a fixed 300 ms delay Rev 0 P
3. 05133 014 Figure 2 ADM6819 Solution for Validating Two Supplies Before Sequencing VsETV VGATE toeLay ADM6819 300ms ADM6820 ADJ Figure 3 ADM6819 ADM6820 Timing Diagram Using SETV for Sequencing 05133 015 VGATE 05133 016 300ms Figure 4 ADM6819 Timing Diagram Using EN and SETV for Sequencing Rev 0 Page 4 of 12 ADM6819 ADM6820 ADM6819 ADM6820 ADM6819 ADM6820 GND R2 Figure 5 ADM6819 ADM6820 Solution for Sequencing Three Supply Rails 05133 017 Rev 0 Page 5 of 12 ADM6819 ADM6820 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating Veca Vc 0 3V to 6 0 V SETV SETD EN 0 3V to 30V GATE 0 3 V to Vc 11 V Storage Temperature 65 C to 150 C Operating Temperature Range 40 C to 85 C Lead Temperature Soldering 10 sec 300 C Junction Temperature 150 C ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000V readily accumulate on Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL CHARACTERISTICS Oya is specified for the worst case
4. Icc2 mA Vaart V 0 20 0 15 0 10 I 0 1 2 3 4 5 6 7 Voce V Figure 9 Icc2 vs Vccz 05133 005 05133 008 Voce V 0 50 0 45 Ven 2V 0 40 0 35 0 30 0 25 Icc2 mA Vaart V 0 20 05133 009 Vcc2 V Figure 13 Vaart vs Vcc2 05133 006 Voce V Figure 10 Icc2 vs Vcca Rev 0 Page 8 of 12 ADM6819 ADM6820 VsETV VGATE 5V DIV Vaate V 0 1 2 3 4 5 Vece V o 20ps DIV 05133 010 05133 018 Figure 14 Vaart vs Veca Figure 16 Gate Turn Off Time 340 T3 q34 T r qo Sa 3 T3 330 320 310 300 290 tperav ms 280 270 V GATE 5V DIV 260 250 Croan 1500pF 240 50 25 0 25 50 75 100 125 150 TEMPERATURE C 05133 019 1ms DIV 05133 011 Figure 15 toeay vs Temperature Figure 17 Gate Turn On Time Rev 0 Page 9 of 12 ADM6819 ADM6820 THEORY OF OPERATION The ADM6819 ADM6820 provide local voltage sequencing in multisupply systems Figure 18 and Figure 19 show typical application diagrams for these devices Vin 3 3V Vout 3 3V Vin 3 0V Vout 3 0V 05133 012 Figure 18 ADM6819 Applications Diagram Vout 3 3V Vout 3 0V
5. GND Vca or Vcc Slew Rate 6 V s ADM6819 1 2 toeLay V s ADM6820 Undervoltage Lockout Vuvio 2 4 2 525 2 65 V Vcc falling SETV PIN SETV Threshold Vra 0 602 0 618 0 634 V Vserv rising enables GATE SETV Input Current 10 100 nA SETV Threshold Hysteresis 1 96 Vserv falling disables GATE SETV to GATE Delay toetay 240 300 350 ms Vsetv gt VrH Ven gt Vra ADM6819 SETD PIN ADM6820 SETD Ramp Current Iseto 300 500 730 nA 400 500 600 nA Ta 25 C SETD Voltage Vsetp 1 295 1 326 1 357 V GATE PIN GATE Turn On Time ton 0 5 1 5 10 ms Coate 1500 pF Vcc2 3 3 V Vaate 7 8 V GATE Turn Off Time torr 30 us Coate 1500 pF Vcc2 3 3 V Veate 0 5 V GATE Voltage Veate 45 5 5 6 0 V With respect to Vco Reate gt 50 MO to Vecx i 40 5 0 6 V With respect Vecx Reate gt 5 MQ to Veo 8 9 9 4 9 9 V With respeetfo Vcc Reate gt 50 MO to Vco 8 2 8 6 9 1 V With respect to Vcox Reate gt 5 MQ to Vec ENABLE PIN EN Input Voltage Low Vit 0 4 V Vca or Vec2 must be gt 2 95 V EN Input Voltage High Viu 2 0 V Vca or Vec2 must be gt 2 95 V 1 10096 production tested at TA 25 C Specifications over temperature limit are guaranteed by design Guaranteed by design not production tested 3 tpaiav s 2 65 x 10 x Cser Highest supply pin is represented by Vccx 2 95 V 5 Highest supply pin is represented by Vcc 5 5 V Rev 0 Page 3 of 12 ADM6819 ADM6820 TIMING DIAGRAMS Vcc2 ADM6819
6. on the GATE output enhances the secondary supply FET Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Vcci Vcc2 ADM6819 ADM6820 05133 001 SETD ADM6820 Figure 1 1 ALI The ADM6819 features an enable EN pin that is fed to the input of an additional comparator and reference circuit This pin can be used as a digital enable or a secondary power good comparator to monitor a second supply and enables the GATE only if both supplies are valid When both inputs ofthe internal comparators are above the threshold a fixed 300 ms timeout occurs before the GATE is driven high and the secondary supply is enabled The ADM6820 has only one comparator that is on the SETV pin It also features a timeout period that is adjustable via a single external capacitor on the SETD pin The ADM6819 ADM6820 are packaged in small 6 lead SOT 23 packages One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices In
7. ANALOG DEVICES FET Drive Simple Sequencers ADM6819 ADM6820 FUNCTIONAL BLOCK DIAGRAM FEATURES Single chip enables power supply sequencing of two supplies On board charge pump fully enhances N channel FET Adjustable primary supply monitor to 0 618 V Delay from primary supply to secondary supply enabled Fixed 300 ms delay ADM6819 Capacitor adjustable delay ADM6820 Logic analog driven enable input ADM6819 40 C to 85 C operating range Packaged in small 6 lead SOT 23 package Pin to pin compatibility with MAX6819 MAX6820 APPLICATIONS Multivoltage systems Dual voltage microprocessors FPGAs ASICs DSPs Network processors Telecom and datacom systems PC server applications GENERAL DESCRIPTION j The ADM6819 and ADM6820 are simple power supply sequencers with FET drive capability for enhancing N channel MOSFETS These devices can monitor a primary supply voltage and enable disable an external N channel FET for a secondary supply The ADM6819 has the ability to monitor two supplies When more than two voltages require sequencing multiple ADM6819 ADM6820 devices can be cascaded to achieve this The devices operate over a supply range of 2 95 V to 5 5 V An internal comparator monitors the primary supply using the VSET pin The input to this comparator is externally set via a resistor divider from the primary supply When the voltage at the VSET pin rises above the comparator threshold an internal charge pump
8. N is driven high GATE drive is immediately disabled when EN is driven low Connect this pin to the higher of Vcci or Vcc2 if not used EN is internally identical to SETV 0 618 V threshold and therefore can be used as a second supply monitor enabling two supplies to be validated before sequencing begins GATE Delay Set Input Connect an external capacitor from SETD to GND to adjust the delay from SETVe Vruto GATE turn on tgaav 3 7 2 652 x 10 x Cser F GATE Drive Output GATE drives an exterbal Cabo rer to connect Vcc2 to the load GATE drive enablesttpeavafteRSETV exceeds Vra andeENABLE is driven high GATE drive is immediately disabled when SETV drops below Vra or ENABLE is driven low When enabled an internal charge pump drives GATE above Vcc to fully enhance the external N channel FET Supply Voltage 2 Either Vcc or Vcc must be greater than the UVLO to enable the external FET Drive Rev 0 Page 7 of 12 ADM6819 ADM6820 TYPICAL PERFORMANCE CHARACTERISTICS 0 50 0 65 0 64 lcc2 Vec1 3 3V Voca 5V 0 63 0 62 0 61 0 60 SUPPLY CURRENT mA o w 6 SUPPLY CURRENT mA 50 25 0 25 50 75 100 125 150 TEMPERATURE C 05133 004 05133 007 TEMPERATURE C Figure 8 Supply Current vs Temperature Figure 11 Supply Current vs Temperature 0 50 Vec1 OV 0 45 F Ven 2V Vgetv 2V 0 40 0 35 0 30 0 25
9. age 10 of 12 ADM6819 ADM6820 OUTLINE DIMENSIONS BE 1 60 BSC 2 80 BSC PIN1 INDICATOR ES EH ES 0 95 BSC 1 90 1 30 BSC 115 0 90 f 1 45 MAX 0 15 MAX 0 50 SI X 0 30 i SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO 178 AB Figure 20 6 Lead Small Outline Transistor Package SOT 23 RJ 6 Dimensions shown in millimeters ORDERING GUIDE FAN i Model Temperature Rang Package Description Package Option Branding ADM6819ARJZ REEL7 40 C to 85 C 6 Lead Small Outline Transistor Package SOT 23 RJ 6 M2R ADM6820ARJZ REEL7 40 C to 85 C 6 Lead Small Outline Transistor Package SOT 23 RJ 6 M2S Z Pb free part Rev 0 Page 11 of 12 ADM6819 ADM6820 NOTES INN D ALI 2006 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D05113 0 7 06 0 DEVICES www analo g com Rev 0 Page 12 of 12
10. c All rights reserved ADM6819 ADM6820 TABLE OF CONTENTS Features S tete etm ese user 1 Pin Configuration and Function Descriptions 7 Applications eoe n OR OR UR Eget veces 1 Typical Performance Characteristics see 8 Functional Block Diagram sse 1 Theory of Operation sssini 10 General Description cescecssessesssesesseesessesssessessesstesessessesseesees 1 SEP VEPA ipa qeu stet 10 REVISION Hist ORY sc ectetur AL 2 BING PUt cose siesta Sah tess Be Ne DS oue 10 Specifications sospetto te et dte OP E Reit Re eode 3 GATE PiN uet optet ien ime idet ue 10 Timing Diagrams 4 SELD Pins tete 10 Absolute Maximum Ratings seen 6 Outlin Dimensions ertet setti tete ienas 11 Thermal Characteristics itte emere 6 Ordering Gilde ette eite td ede 11 ESD Caution costes enteseedetenetentiiesitp editi 6 REVISION HISTORY 7 06 Rev 0 Initial Version IN D ALI Rev 0 Page 2 of 12 ADM6819 ADM6820 SPECIFICATIONS Vcaor Vee 2 95 V to 5 5 V Ta 40 C to 85 C unless otherwise noted Typical values are at Ta 25 C Table 1 Parameter Min Typ Max Units Conditions Vca Vec2 PINS Vcci or Vec2 must be gt 2 95 V Operating Voltage Range Vcci or Vc2 0 9 5 5 V Vca or Vec2 must be gt 2 95 V Vcci or Vcc Supply Current Icc 350 500 uA Veer Vec 3 3 V Vcci or Vcc Disable Mode Current 250 pA Vcci Vec 3 3 V EN
11. conditions that is a device soldered in a circuit board for surface mount packages Table 3 Thermal Resistance Package Type Osa Unit 6 Lead SOT 23 169 5 C W the human body and test equipment and can discharge without detection Although this product features MM PT t S proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Ah electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality i ESD SENSITIVE DEVICE Rev 0 Page 6 of 12 ADM6819 ADM6820 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Veer GND 2 sETV 5 ADM6819 TOP VIEW 5 GATE Not to Scale m z 05133 002 Figure 6 ADM6819 Pin Configuration Table 4 Pin Function Descriptions Veer 1 6 Voce ADM6820 GND 2 TOP VIEW s5 GATE Not to Scale sETV 3 o m 4 rs 05133 003 Figure 7 ADM6820 Pin Configuration Pin Number ADM6819 ADM6820 Mnemonic Description 1 1 Veci GND SETV EN SETD VH i Vcc2 Supply Voltage 1 Either Vcc or Vcc must be greater than the UVLO to enable external FET Drive Chip Ground Pin Sequenced Threshold Set Connect to an external resistor divider to set the Vcc threshold that enables GATE turn on The internal reference is 0 618 V Active High Enable GATE drive is enabled toewa after E

ANALOG DEVICES ADM6820 handbook

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