ANALOG DEVICES ADM1066 handbook
Contents
1. ILoAp HA Figure 13 Vevo Weak Pull Up to VPx vs loan 04609 057 04609 058 DNL LSB INL LSB HITS PER CODE Rev D Page 12 of 32 Figure 14 DNL for ADC 4000 P a uL AM LLL 0 1000 2000 3000 12000 10000 8000 6000 4000 2000 CODE Figure 15 INL for ADC 9894 4000 2047 2048 2049 CODE Figure 16 ADC Noise Midcode Input 10 000 Reads 04609 066 04609 063 04609 064 ADM1066 1 005 1 004 1 003 2 v vew mA 1 002 1 001 E 5222 pupas aa 3 100 u 11 in 111 CE 4148 11 OUTPUT L PROBE 2 E lt 0 999 i a 0 998 0 997 BD gt 8 E 8 0 996 g 200mv M1 00ps CH1 756mV 0 995 5 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 17 Transient Response DAC Code Change into Typical Load Figure 19 DAC Output vs Temperature 1 2 1 GN DR A ER M ROS RTA x 3 1 E DAC 100k 2 E Ep Oe Tee owt e onm di i BUFFER w o 1V OUTPUT 4 1 PROBE j POINT VWWV iD 1 _ 200 M1 00us CH1 944mV UU 40 220 0 20 40 60 80 100 TEMPERATURE C Figure 18 Transient Response of DAC to Turn On from High Z State Figure 20 REFOUT vs Temperature Rev D Page 13 of 32 ADM1062. 100 pA 0 25 mV Sinking current 100 pA Minimum Load Capacitance 1 uF Capacitor required for decoupling stability PSRR 60 dB DC PROGRAMMABLE DRIVER OUTPUTS High Voltage Charge Pump Mode PDO1 to PDO6 Output Impedance 500 kQ Von 11 12 5 14 V lou O pA Von 10 5 12 13 5 V lon 1 pA 8 10 13 5 V lou 7 pA loutave 20 uA 2 lt lt 7 Standard Digital Output Mode PDO1 to PDO10 Vou 24 V Veu pull up to VDDCAP or VPx 2 7 V lou 0 5 mA 4 5 V Veu to VPx 6 0 V lou 2 0 mA Veu 0 3 V Vru 2 7 V lou 0 5 mA Vor 0 0 50 V lo 20 mA lo 20 mA Maximum sink current per PDOx pin 60 mA Maximum total sink for all PDOx pins RpuLt up 16 20 29 kQ Internal pull up Isource VPX 2 mA Current load on any VPx pull ups that is total source current available through any number of PDO pull up switches configured onto any one VPx pin Three State Output Leakage 10 uA 14 4 V Current Oscillator Frequency 90 100 110 kHz All on chip time delays derived from this clock Rev D Page 6 of 32 ADM1066 Parameter Min Typ Max Unit Test Conditions Comments DIGITAL INPUTS VXx AO A1 Input High Voltage Vin 2 0 V Maximum Vin 5 5 V Input Low Voltage Vit 0 8 V Maximum Vin 5 5 V Input High Current liu 1 yA Vin 5 5V Input Low Current li 1 uA 0 Input Capacitance 5 pF Programmable Pull Down 20 VDDCAP 4 75 V Ta 25 C
3. sse 31 11 06 Rev B to Rev C Updated Universal Changes to Features cea REY 1 Ch riges to FIguTe 2 e o qd 3 Changes to Buffered Voltage Output DACS sss 5 Changes to Table2 ee ttp eee tte yt 7 Chariges to Table 6 5 ote qe et tere 14 Changes to Programming the Supply Fault Detectors Section 14 Changes to 9 Changes to Figure 36 and Figure 37 5 06 Rev A to Rev B Changes to Features Section sse 1 Changes to Table 1 E Changes to Table 2 2 8 Changesto Table g 15 reparte ERREUR ERI S UE 10 Added E 10 Added Default Output Configuration 19 Changes to Fault Reporting Section sss 19 Added RE S 30 Changes to Ordering Guide sse 36 1 05 Rev 0 to Rev A Changesito Figure I eee etd 1 Changes to Absolute Maximum Ratings Section 8 Change to Supply Sequencing Through Configurable Output Drivers Sector ret EH 16 Chan ges to Figure 33er i t DR HERD SUE REED RERUM 23 Chanige to Table 10 itn ame e ttes 32 10 04 Revision 0 Initial Version NAL Rev D Page 3 of 32 ADM1066 The device also provides up to 10 programmable inputs for moni toring undervoltage faults overvoltage faults or out of window This design enables very flexible seq
4. SLAVE ADDRESS COMMAND CODE 9 1 SCL CONTINUED SDA CONTINUED Figure 36 General SMBus Write Timing Diagram SLAVE BY FRAME MASTER DATA BYTE ACK BY STOP 04609 036 Rev D Page 27 of 32 ADM1066 1 9 1 9 SCL SDA 0 1 1 0 3 RvN orX ey os prX DON ee START BY ACK BY ACK BY MASTER SLAVE MASTER FRAME 1 r FRAME 2 SLAVE ADDRESS DATA BYTE SCL CONTINUED JE og pep e ERES E SDA CONTINUED 04609 037 a FRAME MASTER DATA BYTE tsu sto tup paT tsu DAT a gt SDA L Pais EN Figure 38 Serial Bus Timing Diagram SMBus PROTOCOLS FOR RAM AND EEPROM The ADM1066 uses the following SMBus write protocols The ADM1066 contains volatile RAM And nonvolatile SendByt registers EEPROM User adress 0x00 to Tfi a setid byt operation the faster device sends a single Address 0xDF the EEPROM occupies Address OxF800 to Address 0xFBFF Data can be written to and read from both the RAM and the EEPROM as single data bytes Data can be written only to unprogrammed EEPROM locations To write new data to a programmed location the location contents must first be erased EEPROM erasure cannot be done at the byte level The EEPROM command byte to a slave device as follows 1 The master device asserts
5. 13 14 15 DATA Alp z 8 Figure 47 Block Read from the EEPROM or RAM with gt Rev D Page 30 of 32 OUTLINE DIMENSIONS INDICATOR PIN 1 4 12 MAX 0 80 PLANE 0 18 0 20 REF 0 85 i SEATING 023 PIN 1 INDICATOR a EXPOSED PAD BOTTOM VIEW COPLANARITY 0 08 COMPLIANT TO JEDEC STANDARDS MO 220 VJJD 2 Figure 48 40 Lead Lead Frame Chip Scale Package LFCSP VO VIEW A ROTATED 90 CCW 6mm x 6 mm Body Very Thin Quad CP 40 1 Dimensions shown in millimeters PINS DOWN LEAD PITCH 0 22 COMPLIANT TO JEDEC STANDARDS MS 026ABC Figure 49 48 Lead Thin Plastic Quad Flat Package TOFP 0 25 MIN ADM1066 SU 48 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADM1066ACP 40 C 85 C 40 Lead LFCSP_VQ CP 40 1 ADM1066ACP REEL ADM1066ACP REEL7 ADM1066ACPZ ADM1066ACPZ REEL ADM1066ACPZ REEL7 ADM1066ASU ADM1066ASU REEL ADM1066ASU REEL7 ADM1066ASUZ ADM1066ASUZ REEL ADM1066ASUZ REEL7 EVAL ADM1066LFEBZ EVAL ADM1066TQEBZ 40 C 85 C 40 C 85 C 40 C to 85 C 40 C to 85 40 C to 85 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 40 C to 85 C 40 C to 85 C 40 Lead LFCSP_VQ 40 Lead LFCSP_VQ 40 Lead LFCSP_VQ 40 Lead LFCSP_VQ 40 Lead L
6. Central office systems Servers routers Multivoltage system line cards DSP FPGA supply sequencing In circuit testing of margined supplies GENERAL DESCRIPTION The ADM1066 Super Sequencer is a configurable supervisory sequencing device that offers a single chip solution for supply monitoring and sequencing in multiple supply systems In addition to these functions the ADM1066 integrates a 12 bit ADC and six 8 bit voltage output DACs These circuits can be used to implement a closed loop margining system that enables supply adjustment by altering either the feedback node or reference of a dc to dc converter using the DAC outputs Supply margining can be performed with a minimum of external components The margining loop can be used for in circuit testing of a board during production for example to verify board func tionality at 596 of nominal supplies or it can be used dynamically to accurately control the output voltage of a dc to dc converter One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2004 2008 Analog Devices Inc All rights reserved ADM1066 TABLE OF CONTENTS Features aerea or oe EE E EEE EEE 1 Functional Block Diagram sette 1 Applications IA 1 General Descriptions eet et RICE a 1 REVISION History 3 Detailed Block Diagram seen 4 Specificationis eicit
7. The six on board voltage DACs DACI to DAC6 can drive into the feedback pins of the power modules to be margined The simplest circuit to implement this function is an attenuation resistor that connects the DACx pin to the feedback node of a dc to dc converter When the DACx output voltage is set equal to the feedback voltage no current flows into the attenuation resistor and thewdostozdc converter output voltage does not change Taking DAQX above the feedback voltage forces current into the feedback node and the output of the dc to dc converter is forced to fall to compensate for this The dc to dc converter output can be forced high by setting the DACXx output voltage lower than the feedback node voltage The series resistor can be split in two and the node between them can be decoupled with a capacitor to ground This can help to decouple any noise picked up from the board Decoupling to a ground local to the dc to dc converter is recommended The ADM1066 can be commanded to margin a supply up or down over the SMBus by updating the values on the relevant DAC output OUTPUT DC TO DC CONVERTER FEEDBACK GND D ATTENUATION RESISTOR R3 PCB TRACE NOISE DECOUPLING CLOSED LOOP SUPPLY MARGINING A more accurate and comprehensive method of margining is to implement a closed loop system see Figure 33 The voltage on the rail to be margined can be read back to accurately margin the rail to the target voltage The ADM
8. and the second data byte is the actual data as shown in Figure 43 1 2 3 4 5 6 8 9 10 EEPROM 04609 043 Figure 43 Single Byte Write to the EEPROM Block Write In a block write operation the master device writes a block of data to a slave device The start address for a block write must have been set previously In the ADM1066 a send byte opera tion sets RAM address and a write byte word operation sets EEPROM adress as follows 1 2 1 2 3 4 5 6 7 8 9 SLAVE A COMMAND 0 BYTE DATA DATA ADDRESS BLOCK WRITE COUNT 1 2 The master a start condition on SDA The master sends the 7 bit slave address followed by the write bit low The addressed slave device asserts an ACK on SDA The master sends a command code that tells the slave device to expect a block write The ADM1066 command code for a block write is OxFC 1111 1100 The slave asserts an ACK on SDA The master sends a data byte that tells the slave device how many data bytes are being sent The SMBus specification allows a maximum of 32 data bytes in a block write The slave asserts an ACK on SDA The master sends N data bytes The slave asserts an ACK on SDA after each data byte The master asserts a stop condition on SDA to end the transaction 10 DATA 04609 044 Figure 44 Block Write to the EEPROM or RAM ADM1066 Unlike some EEPROM devices that limit block writes to within a page boundary there is no li
9. if known logic state is required Current lputt bown SERIAL BUS DIGITAL INPUTS SDA SCL Input High Voltage Viu 2 0 V Input Low Voltage Vit 0 8 V Output Low Voltage Vo 0 4 V lout 3 0 mA SERIAL BUS TIMING Clock Frequency fsck 400 kHz Bus Free Time teur 4 7 us Start Setup Time tsu sta 4 7 us Stop Setup Time tsu sto 4 us Start Hold Time tupsta 4 us SCL Low Time trow 4 7 us SCL High Time 4 us SCL SDA Rise Time tr 1000 us SCL SDA Fall Time tr 300 us Data Setup Time tsu pat 250 ns Data Hold Time 5 ns d Input Low Current li 4 1 A Vi 0 i SEQUENCING ENGINE TIMING State Change Time 10 Us At least one of the VH VPx pins must be 23 0 V to maintain the device supply on VDDCAP Specification is not production tested but is supported by characterization data at initial product release Rev D Page 7 of 32 ADM1066 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating Voltage on VH Pin 16V Voltage on VPx Pins 7V Voltage on VXx Pins 0 3V to 6 5V Voltage on AUX1 AUX2 Pins 0 3V to 45V Voltage on AO A1 Pins 0 3V to 7 V Voltage on REFIN REFOUT Pins 5V Voltage on VDDCAP VCCP Pins 6 5V Voltage on DACx Pins 6 5V Voltage on PDOx Pins 16V Voltage on SDA SCL Pins 7V Voltage on GND AGND PDOGND REFGND Pins 0 3 V to 0 3 V Input Current at Any Pin 5 mA Package Input Current 20 mA Maximum Junction Temperature
10. 75 V VDDCAP 2 7 4 75 5 4 V Regulated LDO output Cvppcap 10 uF Minimum recommended decoupling capacitance POWER SUPPLY Supply Current lva lvex 4 2 6 mA VDDCAP 4 75 V PDO1 to PDO10 off DACs off ADC off Additional Currents All PDO FET Drivers On 1 mA VDDCAP 4 75 V PDO1 to PDO6 loaded with 1 uA each PDO7 to PDO10 off Current Available from 2 mA Maximum additional load that can be drawn from all PDO VDDCAP pull ups to VDDCAP DAC Supply Currents 22 mA Six DACs on with 100 uA maximum load on each ADC Supply Current 1 mA Running round robin loop EEPROM Erase Current 10 mA 1 ms duration only VDDCAP 3V SUPPLY FAULT DETECTORS VH Pin Input Impedance 52 kQ Input Attenuator Error 0 05 1 96 Midrange and high range Detection Ranges i High Range 144 V Midrange 2 5 6 V VPx Pins Input Impedance 52 kQ Input Attenuator Error 0 05 Low range and midrange Detection Ranges Midrange 2 5 6 V Low Range 1 25 3 V Ultralow Range 0 573 1 375 V No input attenuation error VXx Pins Input Impedance 1 MO Detection Range Ultralow Range 0 573 1 375 V No input attenuation error Absolute Accuracy 1 VREF error DAC nonlinearity comparator offset error input attenuation error Threshold Resolution 8 Bits Digital Glitch Filter 0 Us Minimum programmable filter length 100 Us Maximum programmable filter length ANALOG TO DIGITAL CONVERTER Signal Range 0 Vren V The ADC can convert signals presented to the VH VPx and VXx pins VPx and VH
11. T max 150 C Storage Temperature Range 65 C to 150 C Lead Temperature 215 C Soldering Vapor Phase 60 sec ESD Rating All Pins 2000 V THERMAL RESISTANCE is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 3 Thermal Resistance Package Type Osa Unit 40 Lead LFCSP 25 C W 48 Lead TQFP 50 C W ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of thexdeyiee at theseJor other conditions above those ind AM Mia gperational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability NAL Rev D Page 8 of 32 ADM1066 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR NC NO CONNECT Figure 3 LFCSP Pin Configuration ADM1066 TOP VIEW Not to Scale Table 4 Pin Function Descriptions N 1 INDICATOR A
12. There are 256 DAC settings available The midcode value is located at DAC Code 0x7F as close as possible to the middle of the 256 code range The full output swing of the DACs is 302 mV 128 codes and 300 mV 127 codes around the selected midcode voltage The voltage range for each midcode voltage is shown in Table 10 Table 10 Ranges for Midcode Voltages Midcode Minimum Voltage Maximum Voltage Voltage V Output V Output V 0 6 0 300 0 902 0 8 0 500 1 102 1 0 0 700 1 302 1 25 0 950 1 552 CHOOSING THE SIZE OF THE ATTENUATION RESISTOR The size of the attenuation resistor R3 determines how much the DAC voltage swing affects the output voltage of the dc to dc converter that is being margined see Figure 33 Because the voltage at the feedback pin remains constant the current flowing from the feedback node to GND through R2 is a constant In addition the feedback node itself is high impedance This means that the current flowing through is the same as the current flowing through R3 Therefore a direct relationship exists between the extra voltage drop across R1 during margining and the voltage drop across R3 This relationship is given by the following equation RI AVour Vrs Voacour R3 where AVour is the change in Vour Vrs is the voltage at the feedback node of the dc to dc converter Voacour is the voltage output of the margining DAC This equation demonstrates that if the
13. a start condition on SDA 2 The master sends the 7 bit slave address followed by the write bit low 3 addressed slave device asserts an acknowledge ACK on SDA 3 4 The master sends a command code is arranged as 32 pages of 32 bytes each and an entire page The slave asserts an ACK on SDA erased 6 The master asserts a stop condition on SDA and the Page erasure is enabled by setting Bit 2 in the UPDCFG register transaction ends Address 0x90 to 1 If this bit is not set page erasure cannot occur even if the command byte 0xFE is programmed across the SMBus In the ADM1066 the send byte protocol is used for two purposes WRITE OPERATIONS e To write a register address to the RAM for a subsequent The SMBus specification defines several protocols for different single byte read from the same address or for a block read or block write starting at that address as shown in Figure 39 types of read and write operations The following abbreviations are used in Figure 39 to Figure 47 ARAS a _ ADDRESS A S Start 0x00 TO OxDF 1 2 3 4 5 6 04609 039 P Stop Figure 39 Setting a RAM Address for Subsequent Read R Read W Write e To erase page of FERROM memory EEPROM memory A Acknowledge can be written to only if it is unprogrammed Before writing to one or more EEPROM memory locations that are already programmed the page s containing those locations must first be erased EEPRO
14. input signals are attenuated depending on the selected range a signal at the pin corresponding to the selected range is from 0 573 V to 1 375 V at the ADC input Input Reference Voltage on 2 048 V REFIN Pin Resolution 12 Bits INL 2 5 LSB Endpoint corrected Vrerin 2 048 V Gain Error 0 05 VngriN 2 048 V Rev D Page 5 of 32 ADM1066 Parameter Min Typ Max Unit Test Conditions Comments Conversion Time 0 44 ms One conversion on one channel 84 ms All 12 channels selected 16x averaging enabled Offset Error 2 LSB Vrerin 2 048 V Input Noise 0 25 LSBms Direct input no attenuator AUX1 AUX2 Input Impedance 1 MQ BUFFERED VOLTAGE OUTPUT DACs Resolution 8 Bits Code 0x7F Output Voltage Six DACs are individually selectable for centering on one of four output voltage ranges Range 1 0 592 0 6 0 603 V Range 2 0 796 0 8 0 803 V Range 3 0 996 1 1 003 V Range 4 1 246 1 25 1 253 V Output Voltage Range 601 25 mV Same range independent of center point LSB Step Size 2 36 mV INL 0 75 LSB Endpoint corrected DNL 0 4 LSB Gain Error 1 Maximum Load Current Source 100 uA Maximum Load Current Sink 100 uA Maximum Load Capacitance 50 pF Settling Time to 50 pF Load 2 us Load Regulation 2 5 mV Per mA PSRR 60 dB DC A0 57 100 mV step in20 nslwith 5Q pF load REFERENCE OUTPUT j i Reference Output Voltage 2 043 2 048 2 053 V No load Load Regulation 0 25 mV Sourcing current
15. rte a eroe ede edits 5 Absolute Maximum Ratings eerte 8 Thermal Resistance te RID Reda 8 ESD Caution ARR ies 8 Pin Configurations and Function Descriptions 9 Typical Performance Characteristics sssses 11 Powering the 1066 2 2 14 Inp tsz nodes 15 Supply Supervision rettet repe reete etn 15 Programming the Supply Fault 15 Input Comparator Hysteresis sse 15 Input Glitch Filtering 16 Supply Supervision with VXx VV DAN LIA 2 emt iJ 16 V Xx Pins as Digital Inputs oerte 16 t 17 Supply Sequencing Through Configurable Output Drivers 17 Default Output Configuration sse 17 Sequencing Engine ienei pta netten trente teinte tineis 18 Uu 18 Warnings es Rane SNe 18 SMBus Jump Unconditional 18 Sequencing Engine Application 19 Fault and Status Reporting eerte 20 Voltage Readbatk tite tti ete tete heey 21 Supply Supervision with the ADC ses 21 Marpiningisccose onset 22 er a n PIRE 22 Open Loop Supply Margining see 22 Closed Loop Supply M
16. stop condition on SDA to end the transaction 1 2 3 4 5 6 7 8 9 10 11 12 gt SLAVE A COMMAND 0xFD SLAVE BYTE a ADDRESS BLOCK READ ADDRESS COUNT 1 u 13 DATA Figure 46 Block Read from the EEPROM or RAM Error Correction 04609 046 The ADM1066 provides the option of issuing a packet error correc tion PEC byte after a write to the RAM a write to the EEPROM a blod writetaitlie RA M EEPROM or a block read from the This option enables the user to verify that the data received by or sent from the ADM1066 is correct The PEC byte is an optional byte sent after the last data byte has been written to or read from the ADM1066 The protocol is the same as a block read for Step 1 to Step 12 and then proceeds as follows 13 The ADM1066 issues a PEC byte to the master The master checks the PEC byte and issues another block read if the PEC byte is incorrect 14 A NACK is generated after the PEC byte to signal the end of the read 15 The master asserts a stop condition on SDA to end the transaction Note that the PEC byte is calculated using CRC 8 The frame check sequence FCS conforms to CRC 8 by the polynomial C x x8 x x 1 See the SMBus Version 1 1 specification for details An example of a block read with the optional PEC byte is shown in Figure 47 10 11 1 1 2 3 4 56 7 8 9 2 SLAVE A COMMAND OxFD SLAVE BYTE DATA A ADDRESS BLOCK READ ADDRESS COUNT 1
17. the configuration in the RAM must be restored at power up by downloading the contents of the EEPROM nonvolatile memory to the local latches This download occurs in steps as follows 1 With no power applied to the device the PDOs are all high impedance 2 When 1 2 V appears on any of the inputs connected to the VDD arbitrator VH or VPx the PDOs are all weakly pulled to GND with a 20 resistor 3 When the supply rises above the undervoltage lockout of the device UVLO is 2 5 V the EEPROM Starts to download to the 4 EEPROM downloads its contents to all Latch As 5 When the contents of the EEPROM are completely downloaded to the Latch As the device controller signals all Latch As to download to all Latch Bs simultaneously completing the configuration download 6 0 5 ms after the configuration download completes the first state definition is downloaded from the EEPROM into the SE Note that any attempt to communicate with the device prior to the completion of the download causes the ADM1066 to issue a no acknowledge NACK UPDATING THE CONFIGURATION After power up with all the configuration settings loaded from the EEPROM into the RAM registers the user may need to alter the configuration of functions on the ADM1066 such as changing the undervoltage or overvoltage limit of an SFD changing the fault output of an SFD or adjusting the rise time delay of one of the PDOs ADM1066 Th
18. timeout e Delay timers for the sequence and timeout blocks can be programmed independently and changed with each state change The range of timeouts is from 0 ms to 400 ms e Output condition of the 10 PDO pins is defined and fixed within a state e Transition from one state tojthe UM made in les than 20 us which is the time needed to download a state definition from EEPROM to the SE Table 7 Sample Sequence State Entries MONITOR TIMEOUT SEQUENCE 04609 029 Figure 26 State Cell The ADM1066 offers up to 63 state definitions The signals monitored to indicate the status of the input pins are the outputs of the SFDs WARNINGS The SE also monitors warnings These warnings can be generated when the ADC readings violate their limit register value or when the secondary voltage monitors on VPx or VH are triggered The warnings are ORed together and are available as a single warning input to each of the three blocks that enable exiting a state SMBus JUMP UNCONDITIONAL JUMP The SE can be forced to advance to the next state unconditionally This enables the user to force the SE to advance Examples of the use of this featuresincludeymoying to a margining state or debugging REWA The or go to command can be sechas an therlinputito s quefice and timeout blocks to provide an exit from each state State Sequence Timeout Monitor IDLE1 If VX1 is low go to State IDLE2 IDLE2 If VP1 is okay go to State EN3
19. us appears on the output of the glitch filter block The output is delayed with respect to the input by 100 us The filtering process is shown in Figure 23 INPUT PULSE SHORTER INPUT PULSE LONGER THAN GLITCH FILTER TIMEOUT THAN GLITCH FILTER TIMEOUT PROGRAMMED PROGRAMMED TIMEOUT INPUT to ter to ter OUTPUT OUTPUT x to ter to ter E Figure 23 Input Glitch Filter Function SUPPLY SUPERVISION WITH VXx INPUTS The VXx inputs have two functions They can be used as either supply fault detectors or digital logic inputs When selected as analog SFD inputs the VXx pins have functionality that is very similar to the VH and VPx pins The primary difference is that the VXx pins have only one input range 0 573 V to 1 375 V Therefore these inputs can directly supervise only the very low supplies However the input impedance of the VXx pins is high allowing an external resistor divide network to be connected to the pin Thus potentially any supply can be divided down into the input range of the VXx pin and supervised This enables the ADM1066 to monitor other supplies such as 24 V 48 V and 5 V An additional supply supervision function is available when the VXx pins are selected as digital inputs In this case the analog function is available as a second detector on each of the dedi cated analog inputs VPx and VH The analog function of VX1 is mapped to VP1 VX2 is mapped to VP2 and so on VX5 is mapped to VH In t
20. user wants the output voltage to change by 300 mV then R3 If the user wants the output voltage toghange by d mV R1 22 x R3 and so on It is best to use the fih DAC tput range to margin a supply Choosing the attenuation resistor in this way provides the most resolution from the DAC meaning that with one DAC code change the smallest effect on the dc to dc converter output voltage is induced If the resistor is sized up to use a code such as 27 decimal to 227 decimal to move the dc to dc converter output by 5 it takes 100 codes to move 5 each code moves the output by 0 0596 This is beyond the readback accuracy of the ADC but it should not prevent the user from building a circuit to use the most resolution DAC LIMITING AND OTHER SAFETY FEATURES Limit registers called DPLIMx and DNLIMX on the device offer the user some protection from firmware bugs that can cause catastrophic board problems by forcing supplies beyond their allowable output ranges Essentially the DAC code written into the DACx register is clipped such that the code used to set the DAC voltage is given by DAC Code DACx DACx 2 DNLIMx and DACx DPLIMx DNLIMx DACx DNLIMx DPLIMx DACx DPLIMx In addition the DAC output buffer is three stated if DNLIMx gt DPLIMx By programming the limit registers this way the user can make it very difficult for the DAC output buffers to be turned on during normal system operation The limi
21. 1066 incorporates all the circuits required to do this with the 12 bit successive approximation ADC used to read back the level of the supervised voltages and the six voltage output DACs implemented as described in the Open Loop Supply Margining section used to adjust supply levels These circuits can be used along with other intelligence such as a microcontroller to implement a closed loop margining system that allows any dc to dc converter or LDO supply to be set to any voltage accurate to within 0 5 of the target To implement closed loop margining l Disable the six DACx outputs 2 Setthe DAC output voltage equal to the voltage on the feedback node 3 Enable the DAC 4 Read the voltage at the dc to dc converter output that is connected to one of the VPx VH or VXx pins 5 modify the DACx output code up or down to adjust the dc to dc converterputput voltage Otherwise stop Because Ke target has been reached 6 output voltage fora value that alters the supply output by the required amount for example 5 7 Repeat Step 4 through Step 6 until the measured supply reaches the target voltage Step 1 to Step 3 ensure that when the DACx output buffer is turned on it has little effect on the dc to dc converter output The DAC output buffer is designed to power up without glitching by first powering up the buffer to follow the pin voltage It does not drive out onto the pin at thi
22. 1066 makes this type of operation possible The local volatile registers RAM are all double buffered latches Setting Bit 0 ofthe UPDCFG register to 1 leaves the double buffered latches open at all times If Bit 0 is set to 0 when a RAM write occurs across the SMBus only the first side of the double buffered latch is written to The user must then write a 1 to Bit 1 ofthe UPDCFG register This generates a pulse to update all the second latches at once EEPROM writes occur in a similar way The final bit in this register can enable or disable EEPROM page erasure If this bit is set high the contents ofan EEPROM page can all be set to 1 If this bit is set low the contents ofa page cannot be erased even if the command code for page erasure is programmed across the SMBus The bit map for the UPDCFG register is shown in the AN 698 Application Note at www analog com A flow diagram for download at power up and subsequent configuration updates is shown in Figure 35 Rev D Page 25 of 32 ADM1066 POWER UP Vec gt 2 5V DEVICE CONTROLLER LATCHA FUNCTION OV THRESHOLD ON VP1 04609 035 Figure 35 Configuration Update Flow Diagram UPDATING THE SEQUENCING ENGINE Sequencing engine SE functions are not updated in the same way as regular configuration latches The SE has its own dedicated 512 byte nonvolatile electrically erasable programmable read only memor
23. 6 POWERING THE ADM1066 The ADM1066 is powered from the highest voltage input on either the positive only supply inputs VPx or the high voltage supply input VH This technique offers improved redundancy because the device is not dependent on any particular voltage rail to keep it operational The same pins are used for supply fault detection see the Supply Supervision section A arbitrator on the device chooses which supply to use The arbitrator can be considered an OR ing of five low dropout regulators LDOs together A supply comparator chooses the highest input to provide the on chip supply There is minimal switching loss with this architecture 0 2 V resulting in the ability to power the ADM1066 from a supply as low as 3 0 V Note that the supply on the VXx pins cannot be used to power the device An external capacitor to GND is required to decouple the on chip supply from noise This capacitor should be connected to the VDDCAP pin as shown in Figure 21 The capacitor has another use during brownouts momentary loss of power Under these conditions when the input supply VPx or VH dips transiently below Von the synchronous rectifier switch immediately turns off so that it does not pull down The capacitor can then act as a reservoir to keep the device active until the next highest supply takes over the powering of the device A 10 uF capacitor is recommended for this reservoir decoupling function 1 Th
24. ANALOG DEVICES Super Sequencer with Margining Control and Auxiliary ADC Inputs ADM1066 FEATURES Complete supervisory and sequencing solution for up to 10 supplies 10 supply fault detectors enable supervision of supplies to lt 0 5 accuracy at all voltages at 25 C lt 1 0 accuracy across all voltages and temperatures 5 selectable input attenuators allow supervision of supplies to 14 4 V on VH 6 V on VP1 to VP4 VPx 5 dual function inputs VX1 to VX5 VXx High impedance input to supply fault detector with thresholds between 0 573 V and 1 375 V General purpose logic input 10 programmable driver outputs PDO1 to PDO10 PDOx Open collector with external pull up Push pull output driven to VDDCAP or VPx Open collector with weak pull up to VDDCAP or VPx Internally charge pumped high drive for use with external N FET PDO1 to PDO6 only Sequencing engine SE implements state machine control of PDO outputs State changes conditional o input events Enables complex control of boards Power up and power down sequence control Fault event handling Interrupt generation on warnings Watchdog function can be integrated in SE Program software control of sequencing through SMBus Complete voltage margining solution for 6 voltage rails 6 voltage output 8 bit DACs 0 300 V to 1 551 V allow voltage adjustment via dc to dc converter trim feedback node 12 bit ADC for readback of all supervised voltages 2 auxiliary single ended A
25. DC inputs Reference input REFIN has 2 input options Driven directly from 2 048 V 0 25 REFOUT pin More accurate external reference for improved ADC performance Device powered by the highest of VPx VH for improved redundancy User EEPROM 256 bytes Industry standard 2 wire bus interface SMBus Guaranteed PDO low with VH VPx 1 2 V Available in 40 lead 6 mm x 6 mm LFCSP and 48 lead 7 mm x 7 mm TQFP packages For more information about the ADM1066 register map refer to the AN 698 Application Note at www analog com Rev D Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM AUX1 AUX2 REFIN REFOUT REFGND SDA SCL A1 0 MEN T 7 Q SMBus INTERFACE CLOSED LOOP MARGINING SYSTEM CONFIGURABLE DUAL FUNCTION OUTPUT INPUTS DRIVERS HV CAPABLE OF DRIVING GATES OF N FET LOGIC INPUTS OR CONFIGURABLE OUTPUT DRIVERS LV CAPABLE OF DRIVING LOGIC SIGNALS 04609 001 O O O O O O O DAC1 DAC2 DAC3 4 DAC5 DAC6 VCCP GND 1 APPLICATIONS
26. DM1066 TOP VIEW Not to Scale 13 14 19 20 21 22 oa NO 56 54545 a AAAA 04609 003 04609 004 NC NO CONNECT Figure 4 TQFP Pin Configuration 1 LFCSP TQFP Mnemonic Deseriptioh 1 12 13 NC No Connection 24 25 36 37 48 1to5 2to6 VX1 to VX5 VXx High Impedance Inputs to Supply Fault Detectors Fault thresholds can be set from 0 573 V to 1 375 V Alternatively these pins can be used as general purpose digital inputs 6to9 7to 10 VP1toVPA VPx Low Voltage Inputs to Supply Fault Detectors Three input ranges can be set by altering the input attenuation on a potential divider connected to these pins the output of which connects to a supply fault detector These pins allow thresholds from 2 5 V to 6 0 V from 1 25 V to 3 00 V and from 0 573 V to 1 375 V 10 11 VH High Voltage Input to Supply Fault Detectors Two input ranges can be set by altering the input attenuation on a potential divider connected to this pin the output of which connects to a supply fault detector This pin allows thresholds from 6 0 V to 14 4 V and from 2 5 V to 6 0 V 11 14 AGND Ground Return for Input Attenuators 12 15 REFGND Ground Return for On Chip Reference Circuits 13 16 REFIN Reference Input for ADC Nominally 2 048 V This pin must be driven by a reference voltage The on board reference can be used by connecting the REFOUT pin to the REFIN pin 14 17 REFOUT Reference Outp
27. FCSP_VQ 48 Lead 48 Lead 48 Lead TOFP 48 Lead 48 Lead 48 Lead Evaluation Kit LFCSP Version Evaluation Kit TOFP Version CP 40 1 CP 40 1 CP 40 1 CP 40 1 CP 40 1 SU 48 SU 48 SU 48 SU 48 SU 48 SU 48 17 RoHS Compliant Part Rev D Page 31 of 32 ADM1066 NOTES INN D ALI 2004 2008 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D04609 0 5 08 D DEVICES www analo g com Rev D Page 32 of 32
28. M memory is erased by writing a command byte Rev D Page 28 of 32 A No acknowledge The master sends a command code telling the slave device to erase the page The ADM1066 command code for a page erasure is OxFE 1111 1110 Note that for a page erasure to take place the page address must be given in the previous write word transaction see the Write Byte Word section In addition Bit 2 in the UPDCFG register Address 0x90 must be set to 1 1 2 3 4 5 6 SAVE COMMAND ADDRESS BYTE OxFE Figure 40 EEPROM Page Erasure 04609 040 As soon as the ADM1066 receives the command byte page erasure begins The master device can send a stop command as soon as it sends the command byte Page erasure takes approximately 20 ms If the ADM1066 is accessed before erasure is complete it responds with a no acknowledge NACK Write Byte Word In a write byte word operation the master device sends a command byte and one or two data bytes to the slave device as follows 1 The master device asserts a start condition on SDA 2 master sends the 7 bit slave address followed by the write bit low 1 3 The addressed slave deyice SDA 4 The master sends a command code 5 slave asserts on SDA 6 The master sends a data byte 7 The slave asserts an ACK on SDA 8 The master sends a data byte or asserts a stop condition 9 The slave asserts an ACK on SDA 10 The maste
29. NPUT CHANGE OR FAULT DETECTION 1 BIT FAULT DETECTOR 04609 033 Figure 29 Monitoring Fault Detector Block Diagram Timeout Detector The timeout detector allows the user to trap a failure to ensure proper progress through a power up or power down sequence In the sample application shown in Figure 28 the timeout next state transition is from the EN3V3 and EN2V5 states For the EN3V3 state the signal 3V3ON is asserted on the PDOI output pin upon entry to this state to turn on a 3 3 V supply This supply rail is connected to the VP2 pin and the sequence detector looks for the VP2 pin to go above its undervoltage threshold which is set in the supply fault detector SFD attached to that pin The power up sequence progresses when this change is detected If however the supply fails perhaps due to a short circuit overloading this supply the timeout block traps the problem In this example if the 3 3 V supply fails within 10 ms the SE moves to the DIS3V3 state and turns off this supply by bringing PDOI low It also indicates that a fault has occurred by taking PDO3 high Timeout delays of 100 us to 400 ms can be programmed FAULT AND STATUS REPORTING The ADM1066 has a fault latch for recording faults Two registers FSTAT1 and FSTAT2 are set aside for this purpose A single bit is assigned to each input of the device and a fault on that input Sets the relevant bit The c ntents ef the fault register can be read Out
30. V3 EN3V3 If VP2 is okay go to State EN2V5 DIS3V3 If VX1 is high go to State IDLE1 EN2V5 If VP3 is okay go to State PWRGD DIS2V5 If VX1 is high go to State IDLE1 FSEL1 If VP3 is not okay go to State DIS2V5 FSEL2 If VP2 is not okay go to State DIS3V3 PWRGD If VX1 is high go to State DIS2V5 If VP2 is not okay after 10 ms go to State DIS3V3 If VP3 is not okay after 20 ms go to State DIS2V5 If VP1 is not okay go to State IDLE1 If VP1 or VP2 is not okay go to State FSEL2 If VP1 or VP2 is not okay go to State FSEL2 If VP1 is not okay go to State IDLE1 If VP1 VP2 or VP3 is not okay go to State FSEL1 Rev D Page 18 of 32 SEQUENCING ENGINE APPLICATION EXAMPLE The application in this section demonstrates the operation of the SE Figure 28 shows how the simple building block of a single SE state can be used to build a power up sequence for a three supply system Table 8 lists the PDO outputs for each state in the same SE implementation In this system a good 5 V supply on VP1 and the VX1 pin held low are the triggers required to start a power up sequence The sequence next turns on the 3 3 V supply then the 2 5 V supply assuming successful turn on of the 3 3 V supply When all three supplies have turned on correctly the PWRGD state is entered where the SE remains until a fault occurs on one of the three supplies or until it is instructed to go through a power down sequence by VX1 g
31. VXx digital pins no warnings are received from any of the inputs of the device and at other times The PDOs can be used for a variety of functions The primary function is to provide enable signals for LDOs or dc to dc converters that generate supplies locally on a board The PDOs can also be used to provide a PWRGD signal when all the SFDs are in tolerance or a RESET output if one of the SFDs goes out of specification this can be used as a status signal for a DSP FPGA or other microcontroller The PDOs can be programmed to pull up to a number of different options The outputs can be programmed as follows 1 e Open drain allowing th UJ y nect anexternal pull up resistor e drain with weak pull up to Vp e drain with strong pull up to e Open drain with weak pull up to VPx e Open drain with strong pull up to VPx e Strong pull down to GND e Internally charge pumped high drive 12 V PDOI to PDO6 only The last option available only on PDOI to PDO6 allows the user to directly drive a voltage high enough to fully enhance an external N FET which is used to isolate for example a card side voltage from a backplane supply a PDO can sustain greater than 10 5 V into a 1 pA load The pull down switches can also be used to drive status LEDs directly CFG4 CFG5 CFG6 SE DATA SMBus DATA CLK DATA The data driving each of the PDOs can come from one of three sources The source c
32. ad In a block read operation the master device reads a block of data from a slave device The start address for a block read must have been set previously In the ADM1066 this is done by a send byte operation to set a RAM address or a write byte word operation to set an EEPROM address The block read operation itself consists of a send byte operation that sends a block read command to the slave immediately followed by a repeated start 04609 045 and a read operation that reads out multiple data bytes as follows 1 The master device asserts a start condition on SDA 2 master sends the 7 bit slave address followed by the write bit low 3 The addressed slave device asserts an ACK on SDA 4 The master sends a command code that tells the slave device to expect a block read The ADM1066 command code for a block read is OxFD 1111 1101 5 slave asserts an ACK on SDA master asserts a repeat start condition on SDA 7 master sends the 7 bit slave address followed by the read bit high 8 slave asserts an ACK on SDA 9 The ADM1066 sends a byte count data byte that tells the master how many data bytes to expect The ADM1066 always returns 32 data bytes 0x20 which is the maximum allowed by the SMBus Version 1 1 specification 10 The master asserts an ACK on SDA 11 The master receives 32 data bytes 12 The master asserts an ACK on SDA after each data byte 13 The master asserts a
33. al pull up of suitable value tied from the PDOx pin to the required pull up voltage The 20 kO resistor must be accounted for in calculating a suitable value For example if PDOx must be pulled up to 3 3 V and 5 V is available as an external supply the pull up resistor value is given by 3 3 V 25V x 20 kO Rup 20 Therefore 100 66 3 3 V 10 Vpp VP4 PDO 04609 028 Figure 25 Programmable Driver Output Rev D Page 17 of 32 ADM1066 SEQUENCING ENGINE OVERVIEW The ADM1066 sequencing engine SE provides the user with powerful and flexible control of sequencing The SE implements state machine control of the PDO outputs with state changes conditional on input events SE programs can enable complex control of boards such as power up and power down sequence control fault event handling interrupt generation on warnings among others A watchdog function that verifies the continued operation of a processor clock can be integrated into the SE program The SE can also be controlled via the SMBus giving software or firmware control of the board sequencing The SE state machine comprises 63 state cells Each state has the following attributes e Monitors signals indicating the status of the 10 input pins to VP4 VH and VX1 to VX5 e be entered from any other state e Three exit routes move the state machine onto a next state sequence detection fault monitoring and
34. an be enabled in the PDOxCFG configu ration register see the AN 698 Application Note for details The data sources are as follows e Output from the SE e Directly from the SMBus A PDO can be configured so that the SMBus has direct control over it This enables software control of the PDOs Therefore a microcontroller can be used to initiate a software power up power down sequence e On chip clock 100 kHz clock is generated on the device This clock can be made available on any of the PDOs It can be used for example to clock an external device such as an LED DEFAULT OUTPUT CONFIGURATION All of the internal registers in an unprogrammed ADM1066 device from the factory are set to 0 Because of this the PDOx pins are pulled to GND by a weak 20 on chip pull down resistor As the input supply to the ADM1066 ramps up on VPx or VH all PDOx pins behave as follows e Input supply 0 V to 1 2 V The PDOs are high impedance e Input supply 1 2 V to 2 7 V The PDOs are pulled to GND byea weak 20 k on chip pull down resistor Supply gt devices continue to pull all PDOs to GND by a weak 20 on chip pull down resistor Programmed devices download current EEPROM configuration data and the programmed setup is latched The PDO then goes to the state demanded by the configuration This provides a known condition for the PDOs during power up The internal pull down can be overdriven with an extern
35. and five digital inputs or a combination thereof If an input is used as an analog input it cannot be used as a digital input Therefore a configuration requiring 10 analog inputs has no available digital inputs Table 6 shows the details of each input PROGRAMMING THE SUPPLY FAULT DETECTORS The ADM1066 can have up to 10 SFDs on its 10 input channels These highly programmable reset generators enable the supervision of up to 10 supply voltages The supplies can be as low as 0 573 V and as high as 14 4 V The inputs can be configured to detect an undervoltage fault the input voltage drops below a prepro grammed value an overvoltage fault the input voltage rises above a preprogrammed value or an out of window fault the input voltage is outside a preprogrammed range The thresholds can be programmed to an 8 bit resolution in registexsyprovidedjin the ADM1066 This translates 19 WW resoltttign thatis dependent on the range selected The resolution is given by Step Size Threshold Range 255 Therefore if the high range is selected on VH the step size can be calculated as follows 14 4 V 6 0 V 255 2 32 9 mV Table 5 lists the upper and lower limits of each available range the bottom of each range and the range itself Vr Table 5 Voltage Range Limits The threshold value required is given by Vr Vr x N 255 Vg where Vris the desired threshold voltage undervoltage or overvoltage Vr is the vo
36. argining eee 22 Writing to the 0 2 0 a 23 Choosing the Size of the Attenuation Resistor 23 DAC Limiting and Other Safety 23 Applications Diagram essere 24 Communicating with the ADM1066 125 Configuration Download at 25 Updating the Configuration eerte 25 Updating the Sequencing Engine ses 26 Internal Registers z nin sted cL Rt RE 26 EEPROM DKY n LAM t 26 Serial Bus CAU ETHER 26 SMBus Protocols for RAM and 28 Write Operations tee 28 Read Operations iieri ete 30 Outline Dimensi ns 31 Ordering Guide cese ett nn 31 Rev D Page 2 of 32 ADM1066 REVISION HISTORY 5 08 Rev C to Rev D Changes to Powering the ADM1066 Section 14 Changes to Table 5 reete 15 Changes to Default Output Configuration Section 17 Changes to Sequence Detector Section 19 Changes to Configuration Download at Power Up Section 25 Changes to TableTT cisci reete eerie edite 26 Changes to Fig re 36 eene 27 Changes to FIgure 37 ER ERR 28 Changes to Figure 46 and Error Correction Section 30 Changes to Ordering Guide
37. be programmed to turn on in any state in the SE program For example it can be set to start after a power up sequence is complete and all supplies are known to be within expected tolerance limits Note that a latency is built into this supervision dictated by the conversion time of the ADC With all 12 channels selected the total time for the round robin operation averaging off is approximately 6 ms 500 us per channel selected Supervision using the ADC therefore does not provide the same real time response as the SFDs Rev D Page 21 of 32 ADM1066 SUPPLY MARGINING OVERVIEW It is often necessary for the system designer to adjust supplies either to optimize their level or force them away from nominal values to characterize the system performance under these condi tions This is a function typically performed during an in circuit test ICT such as when a manufacturer wants to guarantee that a product under test functions correctly at nominal supplies minus 1096 OPEN LOOP SUPPLY MARGINING The simplest method of margining a supply is to implement an open loop technique see Figure 32 A popular way to do this is to switch extra resistors into the feedback node of a power module such as a dc to dc converter or LDO The extra resistor alters the voltage at the feedback or trim node and forces the output voltage to margin up or down by a certain amount The ADMI1066 can perform open loop margining for up to six supplies
38. d version of the input When configured for edge detection a pulse of programmable width is output from the digital block once the logic transition is detected The width is programmable from 0 us to 100 us The digital blocks feature the same glitch filter function that is available on the SFDs This enables the user to ignore spurious transitions on the inputs For example the filter can be used to debounce a manual reset switch When configured as digital inputs each VXx pin has a weak 10 pA pull down current source available for placing the input into a known condition even if left floating The current source if selected weakly pulls the input to GND GLITCH FILTER VXx DIGITAL INPUT gt TO SEQUENCING ENGINE 04609 027 Figure 24 VXx Digital Input Function Rev D Page 16 of 32 ADM1066 OUTPUTS SUPPLY SEQUENCING THROUGH CONFIGURABLE OUTPUT DRIVERS Supply sequencing is achieved with the ADM1066 using the programmable driver outputs PDOs on the device as control signals for supplies The output drivers can be used as logic enables or as FET drivers The sequence in which the PDOs are asserted and therefore the supplies are turned on is controlled by the sequencing engine SE The SE determines what action is taken with the PDOs based on the condition of the ADM1066 inputs Therefore the PDOs can be set up to assert when the SFDs are in tolerance the correct input signals are received on the
39. ds and Ranges Input Function Voltage Range V Maximum Hysteresis Voltage Resolution mV Glitch Filter ps VH High Voltage Analog Input 2 5 to 6 0 425 mV 13 7 100 6 0 to 14 4 1 02V 32 9 Oto 100 VPx Positive Analog Input 0 573 to 1 375 97 5 mV 3 14 Oto 100 1 25 to 3 00 212 mV 6 8 to 100 2 5 to 6 0 425 mV 13 7 to 100 VXx High Z Analog Input 0 573 to 1 375 97 5 mV 3 14 100 Digital Input 0 to 5 0 N A N A 100 Rev D Page 15 of 32 ADM1066 The hysteresis value is given by Vr x Nrunssul 255 where Vuysr is the desired hysteresis voltage is the decimal value of the 5 bit hysteresis code Note that Nrures has a maximum value of 31 The maximum hysteresis for the ranges is listed in Table 6 INPUT GLITCH FILTERING The final stage of the SFDs is a glitch filter This block provides time domain filtering on the output of the SFD comparators which allows the user to remove any spurious transitions such as supply bounce at turn on The glitch filter function is in addition to the digitally programmable hysteresis of the SFD comparators The glitch filter timeout is programmable up to 100 us For example when the glitch filter timeout is 100 us any pulse appearing on the input of the glitch filter block that is less than 100 us in duration is prevented from appearing on the output of the glitch filter block Any input pulse that is longer than 100
40. e ADM1066 provides several options that allow the user to update the configuration over the SMBus interface The following three options are controlled in the UPDCFG register Option 1 Update the configuration in real time The user writes to the RAM across the SMBus and the configuration is updated immediately Option 2 Update the Latch As without updating the Latch Bs With this method the configuration of the ADM1066 remains unchanged and continues to operate in the original setup until the instruction is given to update the Latch Bs Option 3 Change the EEPROM register contents without changing the RAM contents and then download the revised EEPROM contents to the RAM registers With this method the configuration of the ADM 1066 remains unchanged and continues to operate in the original setup until the instruction is given to update the RAM The instruction to download from the EEPROM in Option 3 is also a useful way to restore the original EEPROM contents if revisions to the configuration are unsatisfactory For example if the user needsito alter atroyervoltage threshold the RAM register can be updated as derived in Option 1 However ifthe user is not satisfied Witli the change and wants to revert to the original programmed value the device controller can issue a command to download the EEPROM contents to the RAM again as described in Option 3 restoring the ADM1066 to its original configuration The topology of the ADM
41. e VH input pin can accommodate supplies mp to 14 4 V which allows the ADM1066 to be powered using Vibackplane supply In cases where this 12 V supply is hot swapped it is recommended that the ADM1066 not be connected directly to the supply Suitable precautions such as the use of a hot swap controller should be taken to protect the device from transients that could cause damage during hot swap events When two or more supplies are within 100 mV of each other the supply that first takes control keeps control For example if VP1 is connected to a 3 3 V supply powers up to approximately 3 1 V through VP1 If VP2 is then connected to another 3 3 V supply VP1 still powers the device unless VP2 goes 100 mV higher than VDDCAP VP1 VP2Q VP3 4 INTERNAL DEVICE SUPPLY VH Ny SUPPLY COMPARATOR Figure 21 Voo Arbitrator Operation 04609 022 Rev D Page 14 of 32 ADM1066 INPUTS SUPPLY SUPERVISION The ADM1066 has 10 programmable inputs Five of these are dedicated supply fault detectors SFDs These dedicated inputs are called VH and VPx VP1 to VP4 by default The other five inputs are labeled VXx VX1 to VX5 and have dual functionality They can be used either as SFDs with functionality similar to that of VH and VPx or as CMOS TTL compatible logic inputs to the device Therefore the ADM1066 can have up to 10 analog inputs a minimum of five analog inputs
42. eted as a stop signal If the operation is a write operation the first data byte after the slave address is a command byte This command byte tells the slave device what to expect next It may be an instruction telling the slave device to expect a block write or it may be a register address that tells the slave where subsequent data is to be written Because data can flow in only one direction as defined by the R W bit sending a command to a slave device during a read operation is not possible Before a read operation it may be necessary to perform a write operation to tell the slave what sort of read operation to expect and or the address from which data is to be read Step 3 When all data bytes have been read or written stop conditions are established write naedegthe master pulls the data line high during the 10th Cock pulse tdjassert a stop condition In read node tHe master d vicelreleases the SDA line during the low period before the ninth clock pulse but the slave device does not pull it low This is known as a no acknowledge The master then takes the data line low during the low period before the 10th clock pulse and then high during the 10th clock pulse to assert a stop condition 1 9 1 9 SCL ecc Jp dec e p e p po es ee s ppp p nes pep s E Pe p eas pes p ul SDA of 1 1 0 1 arXao rw 07 ps 2 DON eee START BY ACK BY ACK BY MASTER SLAVE SLAVE FRAME 1 FRAME 2
43. his case these SFDs can be viewed as secondary or warning SFDs The secondary SFDs are fixed to the same input range as the primary SFDs They are used to indicate warning levels rather than failure levels This allows faults and warnings to be generated on a single supply using only one pin For example if VP1 is set to output a fault when a 3 3 V supply drops to 3 0 V VX1 can be set to output a warning at 3 1 V Warning outputs are available for readback from the status registers They are also ORed together and fed into the SE allowing warnings to generate interrupts on the PDOs Therefore in this example if the supply drops to 3 1 V a warning is generated and remedial action can be taken before the supply drops out of tolerance VXx PINS AS DIGITAL INPUTS As discussed in the Supply Supervision with VXX Inputs section the VXx input pins on the ADM1066 have dual functionality The second function is as a digital logic input to the device Therefore the ADM1066 can be configured for up to five digital inputs These inputs are TTL CMOS compatible Standard logic signals can be applied to the pins RESET from reset generators PWRGD signals fault flags and others These signals are available as inputs to the SE and therefore can be used to control the status of the PDOs The inputs can be configured to detect either a change in level or an edge When configured for level detection the output of the digital block is a buffere
44. improved mechanical stability n a typical application all ground pins are connected together WY D ALI Rev D Page 10 of 32 ADM1066 TYPICAL PERFORMANCE CHARACTERISTICS 180 160 5 140 4 120 2 100 z 5 7 amp 80 a 2 gt 2 60 40 1 8 20 8 0 E 0 3 0 1 2 3 4 5 6 0 1 2 3 4 5 6 V Vvp1 V Figure 5 vs Vvp1 Figure 8 Ive vs VP 1 Not as Supply 6 5 0 4 5 5 4 0 3 5 4 z 3 0 a amp 3 25 8 z 2 2 0 445 1 0 1 3 0 5 3 o 3 o 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 V Wu V Figure 6 VS Figure 9 ly vs VH as Supply 5 0 350 4 5 300 4 0 3 5 250 3 0 T 200 25 E 450 2 20 1 5 100 1 0 50 0 5 8 8 0 3 0 3 0 1 2 3 4 5 6 0 1 2 3 4 5 6 V V Figure 7 lve vs VP1 as Supply Figure 10 ly vs VH Not as Supply Rev D Page 11 of 32 ADM1066 Vppo1 V CHARGE PUMPED Vppox1 V Vppo1 V Figure 11 Charge Pumped Veo FET Drive Mode vs 5 0 o 2 5 5 0 7 5 10 0 12 5 HA 04609 056 E e o EN N 3 4 5 mA Figure 12 Veo Strong Pull Up to VPx vs
45. its EEPROM Therefore access to the ADM1066 is restricted until the download is complete Identifying the ADM1066 on the SMBus The ADM1066 has a 7 bit serial bus slave address see Table 11 The device is powered up with a default serial bus address The five MSBs of the address are set to 01101 the two LSBs are determined by the logical states of Pin Al and Pin AO This allows the connection of four ADM1066s to one SMBus Table 11 Serial Bus Slave Address A1 Pin AO Pin Hex Address 7 Bit Address Low Low 0x68 0110100x Low High Ox6A 0110101x High Low 0 6 0110110 High High Ox6E 0110111x x Read write bit The address is shown only as the first 7 MSBs Rev D Page 26 of 32 The device also has several identification registers read only that can be read across the SMBus Table 12 lists these registers with their values and functions Table 12 Identification Register Values and Functions Name Address Value Function MANID OxF4 0x41 Manufacturer ID for Analog Devices REVID OxF5 0x02 Silicon revision MARK1 OxF6 0x00 Software brand MARK2 OxF7 0x00 Software brand General SMBus Timing Figure 36 Figure 37 and Figure 38 are timing diagrams for general read and write operations using the SMBus The SMBus specification defines specific conditions for different types of read and write operations which are discussed in the Write Operations and the Read Operations secti
46. loop of conversions 16 times before returning a result for each channel At the end of this cycle the results are written to the output registers The ADC samples single sided inputs with respect to the AGND pin A 0 V input gives out Code 0 and an input equal to the voltage on REFIN gives out full code 4095 decimal The inputs to the ADC come directly from the VXx pins and from the back of the input attenuators on the VPx and VH pins as shown in Figure 30 and Figure 31 DIGITIZED NO ATTENUATION VOLTAGE READING VXx 04609025 048 Figure 30 ADC Reading VXx Pins ATTENUATION NETWORK VPXIVH _ gt DEPENDS ON RANGE SELECTED DIGITIZED VOLTAGE READING 2 048V VREF 04609 026 Figure 31 ADC Reading on VPx VH Pins The voltage at the input pin can be derived from the following equation ADC Code V 4095 where Vrern 2 048 V when the internal reference is used that is the REFIN pin is connected to the REFOUT pin x Attenuation Factor x Vrerw The ADC input voltage ranges for the SFD input ranges are listed in Table 9 ADM1066 Table 9 ADC Input Voltage Ranges SFD Input Attenuation ADC Input Voltage Range V Factor Range V 0 573 to 1 375 1 0 to 2 048 1 25 to 3 00 2 181 0 to 4 46 2 5 to 6 0 4 363 0 to 6 0 6 0 to 14 4 10 472 0 to 14 4 upper limit is the absolute maximum allowed voltage on the VPx and VH pins The t
47. ltage range Nis the decimal value of the 8 bit code Vz is the bottom of the range Reversing the equation the code for a desired threshold is given by N 255 x Vr Vg Vn For example if the user wants to set a 5 V overvoltage threshold on the code to be programmed in the PSTOVTH register as discussed in the AN 698 Application Note at www analog com is given by N 255 x 5 2 5 3 5 Therefore N 182 1011 0110 or OxB6 INPUT COMPARATOR HYSTERESIS The UV and OV comparators shown in Figure 22 are always looking at VPx To avoid chatter multiple transitions when the input is very close to the set threshold level these comparators have digitally programmable hysteresis The hysteresis can be programmed up fo theyyalues in Table 6 RANGE SELECT ov COMPARATOR FAULT OUTPUT GLITCH FILTER UV FAULT TYPE COMPARATOR SELECT 04609 023 Figure 22 Supply Fault Detector Block The hysteresis is added after a supply voltage goes out of tolerance Therefore the user can program the amount above Voltage Range V Ve V Ve V the undervoltage threshold to which the input must rise before 0 573 to 1 375 0 573 0 802 an undervoltage fault is deasserted Similarly the user can program 1 25 to 3 00 1 25 1 75 the amount below the overvoltage threshold to which an input 2 5 to 6 0 25 35 must fall before an overvoltage fault is deasserted 6 0to 14 4 6 0 8 4 Table 6 Input Functions Threshol
48. mitation on the start address when performing a block write to EEPROM except when e There must be atleast N locations from the start address to the highest EEPROM address OxFBFF to avoid writing to invalid addresses e address crosses a page boundary In this case both pages must be erased before programming Note that the ADM1066 features a clock extend function for writes to the EEPROM Programming an EEPROM byte takes approxi mately 250 us which limits the SMBus clock for repeated or block write operations The ADM1066 pulls SCL low and extends the clock pulse when it cannot accept any more data READ OPERATIONS The ADM1066 uses the following SMBus read protocols Receive Byte In a receive byte operation the master device receives a single byte from a slave device as follows 1 The master device asserts a start condition on SDA 2 The master sends the 7 bit slave address followed by the read bit high The addressed slave device asserts an ACK on SDA The master receives a data byte z The master asserts on DA The master asserts a stop condition on SDA and file transaction ends amp In the ADMI1066 the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte word operation as shown in Figure 45 1 2 3 4 5 6 SLAVE Figure 45 Single Byte Read from the EEPROM or RAM Block Re
49. ns the state definitions for the SE Although referred to as read only memory the EEPROM can be written to as well as read from using the serial bus in exactly the same way as the other registers The major differences between the EEPROM and other registers are as follows e An EEPROM location must be blank before it can be written to If it contains data the data must first be erased e Writing to the EEPROM is slower than writing to the RAM e Writing to the EEPROM should be restricted because it has a limited write cycle life of typically 10 000 write operations due to the usual EEPROM wear out mechanisms The first EEPROM is split into 16 0 to 15 pages of 32 bytes each Page 0 to Page 6 starting at Address OxF800 hold the configuration data for the applications on the ADM1066 such as the SFDs and PDOs These EEPROM addresses are the same as the RAM register addresses prefixed by F8 Page 7 is reserved Page 8 to Page 15 are for customer use Data be aed from theJEEPROM to the RAM in one 0f the following ways e At power up when Page 0 to Page 6 are downloaded e By setting Bit 0 of the UDOWNLD register 0xD8 which performs a user download of Page 0 to Page 6 SERIAL BUS INTERFACE The ADM1066 is controlled via the serial system management bus SMBus and is connected to this bus as a slave device under the control of a master device It takes approximately 1 ms after power up for the ADM1066 to download from
50. oing high Faults are dealt with throughout the power up sequence on a case by case basis The following three sections the Sequence Detector section the Monitoring Fault Detector section and the Timeout Detector section describe the individual blocks and use the sample application shown in Figure 28 to demonstrate the actions of the state machine Sequence Detector The sequence detector block is used to detect when a step in a sequence has been completed It looks for one of the SE inputs to change state and is most often used as the gate for successful progress through a power upjonpowerzdown sequence timer block that is included in thigdetectoricanjinsett delays into a power up or power down sequence if required Timer delays can be set from 10 us to 400 ms Figure 27 is a block diagram of the sequence detector SUPPLY FAULT VPA DETECTION VX50 LOGIC INPUT CHANGE OR FAULT DETECTION SEQUENCE DETECTOR INVERT FORCE FLOW UNCONDITIONAL JUMP Figure 27 Sequence Detector Block Diagram SELECT 04609 032 Table 8 PDO Outputs for Each State ADM1066 If a timer delay is specified the input to the sequence detector must remain in the defined state for the duration of the timer delay If the input changes state during the delay the timer is reset The sequence detector can also help to identify monitoring faults In the sample application shown in Figure 28 the FSEL1 and FSEL2 states first identify
51. ons The general SMBus protocol operates as follows Step 1 The master initiates data transfer by establishing a start condition defined as a high to low transition on the serial data line SDA while the serial clock line SCL remains high This indicates that a data stream follows All slave peripherals connected to the serial bus respond to the start condition and shift in the nexteight bits consisting of a 7 bit slave address MBB first plusan R W bit This bit determines the directiorrof the data transferzthat is whether data is written to or read from the slave device 0 write 1 read The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse known as the acknowledge bit and by holding it low during the high period of this clock pulse ADM1066 All other devices on the bus remain idle while the selected device waits for data to be read from or written to it If the R W bit is a 0 the master writes to the slave device If the R W bit is a 1 the master reads from the slave device Step 2 Data is sent over the serial bus in sequences of nine clock pulses eight bits of data followed by an acknowledge bit from the slave device Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low to high transition when the clock is high could be interpr
52. over the SMBus to d which input s faulted The fault register can be m or disabled in each state To latch data from one state ensure that the fault latch is disabled in the following state This ensures that only real faults are captured and not for example undervoltage conditions that may be present during a power up or power down sequence The ADM1066 also has a number of status registers These include more detailed information such as whether an undervoltage or overvoltage fault is present on a particular input The status registers also include information on ADC limit faults Note that the data in the status registers is not latched in any way and therefore is subject to change at any time See the AN 698 Application Note at www analog com for full details about the ADM1066 registers Rev D Page 20 of 32 VOLTAGE READBACK The ADM1066 has an on board 12 bit accurate ADC for voltage readback over the SMBus The ADC has a 12 channel analog mux on the front end The 12 channels consist of the 10 SFD inputs VH VPx and VXx and two auxiliary single ended ADC inputs AUX1 and AUX2 Any or all of these inputs can be selected to be read in turn by the ADC The circuit controlling this operation is called the round robin circuit This circuit can be selected to run through its loop of conversions once or continuously Averaging is also provided for each channel In this case the round robin circuit runs through its
53. r asserts a stop condition on SDA to end the transaction In the ADM1066 the write byte word protocol is used for three purposes To write a single byte of data to the RAM In this case the command byte is RAM Address 0x00 to RAM Address OxDF and the only data byte is the actual data as shown in Figure 4 1 7 8 2 3 4 5 6 RAM ADAE ADDRESS DATA 0x00 TO OxDF Figure 41 Single Byte Write to the RAM 04609 041 To set up a 2 byte EEPROM address for a subsequent read write block read block write or page erase In this case the command byte is the high byte of EEPROM Address OxF8 to EEPROM Address OxFB The only data byte is the low byte of the EEPROM address as shown in Figure 42 Rev D Page 29 of 32 EEPROM SLAVE ADDRESS ADDRESS DATA ADDRESS HIGH BYTE LOW BYTE 0xF8 TO OxFB 0x00 TO OxFF ADM1066 1 2 3 4 5 6 7 8 EEPROM EEPROM SLAVE ADDRESS ADDRESS ADDRESS HIGH BYTE LOW BYTE 0 8 TO OxFB 0x00 TO OxFF Figure 42 Setting an EEPROM Address 04609 042 Because a page consists of 32 bytes only the three MSBs of the address low byte are important for page erasure The lower five bits of the EEPROM address low byte specify the addresses within a page and are ignored during an erase operation To write a single byte of data to the EEPROM In this case the command byte is the high byte of EEPROM Address OxF8 to EEPROM Address OxFB The first data byte is thelow byte of the EEPROM address
54. s time Once the output buffer is properly enabled the buffer input is switched over to the DAC and the output stage of the buffer is turned on Output glitching is negligible MICROCONTROLLER ADM1066 DEVICE CONTROLLER SMBus 04609 067 Figure 32 Open Loop Margining System Using the ADM1066 Rev D Page 22 of 32 DC TO DC VH VPx VXx CONVERTER OUTPUT ATTENUATION RESISTOR R3 FEEDBACK PCB GND TRACE NOISE DECOUPLING CAPACITOR ADM1066 MICROCONTROLLER DEVICE CONTROLLER SMBus 04609 034 Figure 33 Closed Loop Margining System Using the ADM1066 WRITING TO THE DACs Four DAC ranges are offered They can be placed with midcode Code 0x7F at 0 6 V 0 8 V 1 0 V and 1 25 V These voltages are placed to correspond to the most common feedback voltages Centering the DAC outputs in this way provides the best use of the DAC resolution For most supplies it is possible to place the DAC midcode at the point where the dc to dc converter output is not modified thereby giving half of the DAC range to margin up and the other half to margin down The DAC output voltage is set by the code written to the DACx register The voltage is linear with the unsigned binary number in this register Code Ox7F is placed at the midcode voltage as described previously The output YAT is given by DAC Output DACx 0 7 055 V 0 6045 Milt where Vorr is one of the four offset voltages
55. t registers are among the registers downloaded from EEPROM at startup Rev D Page 23 of 32 ADM1066 APPLICATIONS DIAGRAM 12V IN a 12V OUT 5V IN MM 5V OUT 3V IN 3V OUT IN DC TO DC1 EN OUT 3 3V OUT ADM1066 5V OUT PDO1 3V OUT PDO2 3 3V OUT IN 2 5V OUT 1 8V OUT PDO3 DC TO DC2 1 2 OUT PDO4 EN OUT 2 5V OUT 0 9V OUT PDO5 POWRON SIGNAL VALID RESET PDO7 IN SYSTEM RESET TO p PDOS DC TO DC3 PDO9 EN OUT 1 8V OUT PDO10 REFOUT DAC1 REFIN VCCP VDDCAP GND 0 9V OUT ONLY ONE MARGINING CIRCUIT SHOWN FOR CLARITYzDAC1 TO DAC 12007 ALE OWsMARGINING FOR UP W RAILS DC TO DC4 04609 068 Figure 34 Applications Diagram Rev D Page 24 of 32 COMMUNICATING WITH THE ADM1066 CONFIGURATION DOWNLOAD AT POWER UP The configuration of the ADM1066 undervoltage overvoltage thresholds glitch filter timeouts PDO configurations and so on is dictated by the contents of the RAM The RAM comprises digital latches that are local to each function on the device The latches are double buffered and have two identical latches Latch A and Latch B Therefore when an update to a function occurs the contents of Latch A are updated first and then the contents of Latch B are updated with identical data The advantages of this architecture are explained in detail in the Updating the Configuration section The two latches are volatile memory and lose their contents at power down Therefore
56. uencing of the outputs based on the condition of the inputs faults on up to 10 supplies In addition 10 programmable outputs The device is controlled via configuration data that can be can be used as logic enables Six of these programmable outputs programmed into an EEPROM The entire configuration can can also provide up to a 12 V output for driving the gate of an N be programmed using an intuitive GUI based software package FET that can be placed in the path of a supply provided by Analog Devices Inc The logical core of the device is a sequencing engine This state machine based construction provides up to 63 different states DETAILED BLOCK DIAGRAM REFIN REFOUT AUX2 AUX1 REFGND SDA SCL A1 A0 SMBus INTERFACE DEVICE CONTROLLER CONFIGURABLE GPI SIGNAL CONDITIONING OUTPUT DRIVER B HV SIGNAL CONFIGURABLE CONDITIONING OUTPUT DRIVER SEQUENGING HV sro ENGINE CONFIGURABLE OUTPUT DRIVER LV CONFIGURABLE OUTPUT DRIVER LV PDOGND 04609 002 DAC1 DAC2 DAC3 DAC4 DAC5 DA Figure 2 Detailed Block Diagram Rev D Page 4 of 32 SPECIFICATIONS ADM1066 VH 3 0 V to 14 4 V VPx 3 0 V to 6 0 V Ta 40 C to 85 C unless otherwise noted Table 1 Parameter Min Typ Max Unit Test Conditions Comments POWER SUPPLY ARBITRATION VH VPx 3 0 V Minimum supply required on one of VPx VH VPx 6 0 V Maximum VDDCAP 5 1 V typical VH 14 4 V VDDCAP 4
57. ut 2 048 V Typically connected to REFIN Note that the capacitor must be connected between this pin and REFGND A 10 uF capacitor is recommended for this purpose 151020 1810 23 DAC1 to DAC6 Voltage Output DACs These pins default to high impedance at power up 21 to 30 26 to 35 PDO10 to PDO1 Programmable Driver Outputs 31 38 PDOGND Ground Return for Driver Outputs 32 39 VCCP Central Charge Pump Voltage of 5 25 V A reservoir capacitor must be connected between this pin and GND A 10 pF capacitor is recommended for this purpose 33 40 AO Logic Input This pin sets the seventh bit of the SMBus interface address 34 41 A1 Logic Input This pin sets the sixth bit of the SMBus interface address 35 42 SCL SMBus Clock Pin Bidirectional open drain pin that requires external resistive pull up 36 43 SDA SMBus Data Pin Bidirectional open drain pin that requires external resistive pull up 37 38 44 45 AUX2 AUX 1 Auxiliary Single Ended ADC Inputs Rev D Page 9 of 32 ADM1066 Pin No LFCSP TQFP Mnemonic Description 39 46 VDDCAP Device Supply Voltage Linearly regulated from the highest of the VPx VH pins to a typical of 4 75 V Note that the capacitor must be connected between this pin and GND A 10 pF capacitor is recommended for this purpose 40 47 GND Supply Ground The LFCSP has an exposed pad on the bottom This pad is a no connect NC If possible this pad should be soldered to the board for
58. which of the VP1 VP2 or VP3 pins has faulted and then they take appropriate action SEQUENCE STATES TIMEOUT STATES MONITOR FAULT STATES 04609 030 Figure 28 Sample Application Flow Diagram PDO Outputs IDLE1 IDLE2 EN3V3 EN2V5 DIS3V3 DIS2V5 PWRGD FSEL1 FSEL2 PDO1 3V3ON 0 0 1 1 0 1 1 1 1 PDO2 2V50N 0 0 0 1 1 0 1 1 1 PDO3 FAULT 0 0 0 0 1 1 0 1 1 Rev D Page 19 of 32 ADM1066 Monitoring Fault Detector The monitoring fault detector block is used to detect a failure on an input The logical function implementing this is a wide OR gate that can detect when an input deviates from its expected condition The clearest demonstration of the use of this block is in the PWRGD state where the monitor block indicates that a failure on one or more of the VP1 VP2 or VP3 inputs has occurred No programmable delay is available in this block because the triggering of a fault condition is likely to be caused by a supply falling out of tolerance In this situation the device must react as quickly as possible Some latency occurs when moving out of this state because it takes a finite amount of time 20 us for the state configuration to download from the EEPROM into the SE Figure 29 is a block diagram of the monitoring fault detector MONITORING FAULT DETECTOR 1 FAULT DETECTOR SUPPLY FAULT 1 DETECTION 1 gt 4 s 1 FAULT DETECTOR VX50 LOGIC I
59. y EEPROM for storing state definitions providing 63 individual states each with a 64 bit word one state is reserved At power up the first state is loaded from the SE EEPROM into the engine itself When the conditions of this state are met the next state is loaded from the EEPROM into the engine and so on The loading of each new state takes approximately 10 us To alter a state the required changes must be made directly to the EEPROM RAM for each state does not exist The relevant alterations must be made to the 64 bit word which is then uploaded directly to the EEPROM INTERNAL REGISTERS The ADM1066 contains a large Number Of data registers The principal registers are the address pointer register and the configuration registers Address Pointer Register The address pointer register contains the address that selects one ofthe other internal registers When writing to the ADM1066 the first byte of data is always a register address that is written to the address pointer register Configuration Registers The configuration registers provide control and configuration for various operating parameters of the ADM1066 EEPROM The ADM1066 has two 512 byte cells of nonvolatile EEPROM from Register Address OxF800 to Register Address The EEPROM is used for permanent storage of data that is not lost when the ADM1066 is powered down One EEPROM cell contains the configuration data of the device the other contai
60. ypical way to supply the reference to the ADC on the REFIN pin is to connect the REFOUT pin to the REFIN pin REFOUT provides a 2 048 V reference As such the supervising range covers less than half the normal ADC range It is possible however to provide the ADC with a more accurate external reference for improved readback accuracy Supplies can also be connected to the input pins purely for ADC readback even though these pins may go above the expected supervisory range limits but not above the absolute maximum ratings on these pins For example a 1 5 V supply connected to the VX1 pin can be correctly read out as an ADC code of approxi mately 3 4 full scale but it always sits above any supervisory limits that can be set on that pin The maximum setting for the REFIN pin is 2 048 V SUPPLY SUPERVISION WITH THE ADC In addition to the readback capability another level of supervision is provided by the on chip 12 bit ADC The ADM1066 has limit registers with which the user can program a maximum or minimum allowable threshold Exceeding the threshold generates a warning that can either be read back from the status registers or input into the SE to determine what sequencing action the ADM 1066 should take Only one register is provided for each input channel Therefore either an undervoltage threshold or overvoltage threshold but not both can be set for a given channel The round robin circuit can be enabled via an SMBus write or it can
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