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ANALOG DEVICES ADP2140 handbook

1. 1 83 180 LOAD CURRENT 1mA LOAD CURRENT 5mA 160 LOAD CURRENT 10mA 1 82 140 Ei u 18 120 E g E 100 S 1 80 a 5 a 8 a 5 E 179 LOAD CURRENT 1mA S e H LOAD CURRENT 5mA ro LOAD CURRENT 10mA 40 1 78 LOAD CURRENT z S0mA 20 LOAD CURRENT 50mA LOAD CURRENT 100mA LOAD CURRENT 100mA geg LOAD CURRENT 300mA LOAD CURRENT 300mA 40 5 25 85 125 40 5 25 85 125 JUNCTION TEMPERATURE C B JUNCTION TEMPERATURE C 2 Figure 42 Output Voltage vs Junction Temperature Different Loads Figure 45 Ground Current vs Junction Temperature Different Loads g p g p g p 1 820 160 1 815 140 1 810 z 120 E 3 1 805 5 100 lt Ww a E O 1 800 5 80 gt o 5 a E 1 795 Z 60 5 o o rc 1 790 O 40 1 785 20 1 780 0 1 10 100 1000 1 10 100 1000 3 LOAD CURRENT mA LOAD CURRENT mA S Figure 43 Output Voltage vs Load Current Figure 46 Ground Current vs Load Current 1 820 160 1 815 140 _ 1 810 120 3 S S g 1 805 E 100 5 E 9 1 800 2 8 5 a amp 1795 Z 60 5 LOAD CURRENT 1mA S gege LOAD CURRENT 5mA O 49 eee inem zim OAD CURRENT 10mA LOAD CURRENT 5mA 1 785 LOAD CURRENT 50mA 20 LOAD CUR
2. Rev 0 Page 5 of 32 ADP2140 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PGND VIN1 sw gt 32 ADP2140 9 lt 7 PG AGND 273 TOP VIEW g 7 pw FB EN2 VIN2 VOUT2 Not to Scale NOTES 1 THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GROUND INSIDE THE PACKAGE IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED TO THE GROUND PLANE ON THE CIRCUIT BOARD 07932 003 Figure 3 Pin Configuration Table 5 Pin Function Descriptions Pin Mnemonic Description 1 PGND Power Ground 2 SW Connection from Power MOSFETs to Inductor 3 AGND Analog Ground 4 FB Feedback from Buck Output 5 VIN2 LDO Input Voltage 6 VOUT2 LDO Output Voltage 7 EN2 Logic 1 to Enable LDO or No Connect for Autosequencing 8 EN1 Logic 1 to Enable Buck or Initiate Sequencing This is a dual function pin and the state of EN2 determines which function is operational 9 PG Power Good Open drain output PG is held low until both output voltages which includes the external inductor and capacitor sensed by the FB pin rise above 92 of nominal value PG is held high until both outputs fall below 85 of nominal value 10 VIN1 Analog Power Input EP Exposed Pad The exposed pad on the bottom of the LFCSP package enhances thermal performance and is electrically connected to ground inside the package It is recommended that the exposed pad be connected to the ground plane
3. SW_COND 7 Roscon _p xD R x 1 D x ll DS ON _N OUT Vi where D OUT IN The internal resistance of the power switches increases with temperature but decreases with higher input voltage Inductor Losses Inductor conduction losses are caused by the flow of current through the inductor which has an internal resistance DCR associated with it Larger size inductors have smaller DCR which can decrease inductor conduction losses Inductor core losses relate to the magnetic permeability of the core material Because the ADP2140 is a high switching frequency dc to dc converter shielded ferrite core material is recommended for its low core losses and low EMI To estimate the total amount of power lost in the inductor use the following equation P DCR x Iou Core Losses Table 8 1 0 uH Inductors ADP2140 Switching Losses Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency Each time a power device gate is turned on and turned off the driver transfers a charge AQ from the input supply to the gate and then from the gate to ground Estimate switching losses using the following equation Psw oan p Coaten x Vi x fsw where Cesare p is the gate capacitance of the internal high side switch Ceare_n is the gate capacitance of the internal low side switch fsw is the switching frequency Transition Losses Transition lo
4. Vout2 0 3 V to 5 5 V lour 10 mA 0 05 0 05 96 V Load Regulation AVout2 Alourz lour2 1 mA to 300 mA 0 001 0 005 96 mA Dropout Voltage VoRoPour lourz 10 mA Vour 1 8 V 4 7 mV lour2 300 mA Vous 1 8 V 110 200 mV Ground Current lacno No load buck disabled 22 35 yA lourz 10 mA 65 90 HA lour 300 mA 150 220 uA Power Supply Rejection Ratio PSRR Vu Vour2 1 V Vmi 5 V lour2 10 MA PSRR on Mu 10 kHz Vour 1 2 V 1 8V 3 3 V 65 dB 100 kHz Vour 3 3 V 53 dB 100 kHz Voutz 1 8 V 54 dB 100 kHz Voutz 1 2 V 55 dB Rev 0 Page 3 of 32 ADP2140 Parameter Symbol Test Conditions Comments Min Typ Max Unit Output Noise OUTnoise Mu Vm 5 V lour 10 mA 10 Hz to 100 kHz Vour 0 8 V 29 UN rms 10 Hz to 100 kHz Vour 1 2 V 40 UN rms 10 Hz to 100 kHz Vour 1 8 V 50 UN rms 10 Hz to 100 kHz Vour 2 5 V 66 UN rms 10 Hz to 100 kHz Vour 3 3 V 88 UN rms Current Limit lum Ty 25 C 360 500 760 mA Input Leakage Current ILEAK LDO EN2 GND Viv 5 5 V and Voutz OV 1 uA Start Up Time tsrART UP Vour 3 3 V 300 mA load 70 us Soft Start Time SStime Vourz 3 3 V 300 mA load 130 us ADDITIONAL FUNCTIONS Undervoltage Lockout UVLO Input Voltage Rising UVLOasE 223 23 V Input Voltage Falling UNO 2 05 2 16 V EN Input ENT EN2 Input Logic High Vin 2 3V lt Vin lt 5 5 V 1 0 V ENT EN2 Input Logic Low Vi 23VsVmwi lt 5 5 V 0 27 V ENT EN2 Input Leakage IEN LKG ENT EN2 Vii or GND 0 0
5. 8x fsw XAVour Increasing the output capacitor has no effect on stability and increasing the output capacitance may further reduce output ripple and enhance load transient response When choosing this value it is also important to account for the loss of capacitance due to output voltage dc bias INPUT CAPACITOR Input capacitance is required to reduce input voltage ripple there fore place the input capacitor as close as possible to the VINx pins As with the output capacitor a low ESR X7R or X5R type Cour 2 Rev 0 Page 24 of 32 capacitor is recommended to help minimize the input voltage ripple Use the following equation to determine the minimum input capacitance Vour Vin Vour CIN i Ti oap max V IN I EFFICIENCY Efficiency is defined as the ratio of output power to input power The high efficiency of the ADP2140 has two distinct advantages First only a small amount of power is lost in the dc to dc con verter package which in turn reduces thermal constraints In addition high efficiency delivers the maximum output power for the given input power thereby extending battery life in portable applications Power Switch Conduction Losses Power switch dc conduction losses are caused by the flow of output current through the P channel power switch and the N channel synchronous rectifier which have internal resis tances Rpsow associated with them The amount of power loss can be approximated by P
6. 125 C To ensure the junction temper ature stays below this maximum value the user needs to be aware of the parameters that contribute to junction temperature changes These parameters include ambient temperature power dissipa tion in the power device and thermal resistances between the junction and ambient air 05 The Dua number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pins to the DCH Table 10 shows typical Du values of the 10 lead 3 mm x 3 mm LFCSP for various PCB copper sizes Table 10 Typical Du Values Copper Size mm Du C W 0 42 5 50 40 0 100 38 8 300 37 2 500 36 2 The device is soldered to minimum size pin traces The junction temperature of the ADP2140 can be calculated from the following equation T Ta Pp x Oya 2 where Ta is the ambient temperature Pp is the total power dissipation in the die given by Pp Pipo Psuck where Pipo Vin Vovr X Ioan Vin x Lewvn 3 Psucx Psw Prran Den coup 4 where Loan is the LDO load current Leun is the analog ground current Vin and Vovr are the LDO input and output voltages respectively Psw Prran and Psw cowp are defined in the Efficiency section For a given ambient temperature and total power dissipation there exists a minimum copper size requirement for the PCB to ensure the junction temperature does not rise above 125 C The
7. CH1 100mA CH2 100mV M40 0yus A CH1_ 68mA B CH1 1 00V CH2 5 00mV M2 00us A CH4_ 12mV 3 10 40 8 10 20 g Figure 62 Load Transient Response Vin2 4 V Vourz 3 3 V Figure 65 Line Transient Response Vourz 3 3 V Load Current 1 mA 1 mA to 300 mA Load Current Rise Time 200 ns V2 2 4Vto 5 V 1 us Rise Time Rev 0 Page 17 of 32 ADP2140 Vmi 5 V Vm 2 3 V Vourz 1 8 V Iour 10 mA Cro Cour 1 uF Ta 25 C unless otherwise noted XII ViN2 III CH1 1 00V CH2 5 00mV M2 00us A CH4_ m CH1 1 00V CH2 5 00mV M2 00ps A CH4_ 12mV B 10 20 g 10 20 g Figure 66 Line Transient Response Vourz 1 8 V Load Current 300 mA Figure 68 Line Transient Response Vourz 3 3 V Load Current 300 mA V2 2 4Vto 5V 1 us Rise Time Vin2 4V to 5 V 1 us Rise Time 1 ViN2 ER Vour2 ED CH1 1 00V CH2 5 00mV M2 00ps A CH4_ m 10 20 g Figure 67 Line Transient Response Vourz 1 2 V Load Current 300 mA V2 2 4Vto 5V 1 us Rise Time Rev 0 Page 18 of 32 THEORY OF OPERATION ADP2140 DRIVER AND ANTISHOOT THROUGH ZERO CROSS COMPARATOR 07932 068 Figure 69 Internal Block Diagram BUCK SECTION The ADP2140 contains a step down dc to dc converter that uses a fixed frequency high speed current mode architecture The high 3 MHz switching frequency and tiny 10 lead 3 mm x 3 mm LFCS
8. S Figure 23 Line Transient Vour 1 2 V PWM Mode 600 mA Wa 4V to 5V Figure 26 Load Transient Vour 1 8 V 200 mA to 600 mA Load Current Rise 4us Rise Time Time 200 ns INPUT VOLTAGE F v SWITCH NODE ED OUTPUT VOLTAGE LOAD OUTPUT EN ED EP ER SWITCH NODE OUTPUT VOLTAGE CH1 1 00V CH2 50 0mV M20 0ys A CH _ 4 68V M CH1 100mA CH2 50 0mV M20 0us A CH1 136mA i CH3 5 00V 11 60 CH3 5 00V 10 40 2 Figure 24 Line Transient Vour 3 3 V PSM Mode 50 mA Vw 4 V to 5 V Figure 27 Load Transient Vour 1 8 V 50 mA to 250 mA Load Current Rise 4 us Rise Time Time 200 ns Rev 0 Page 10 of 32 ADP2140 Vini 4 V Vour 1 8 V Iovr 10 mA Cm Cour 10 uF Ta 25 C unless otherwise noted U t SWITCH NODE I SWITCH NODE i LOAD CURRENT LOAD CURRENT OUTPUT VOLTAGE CH1 50 0mA CH2 50 0mV MZ20 0us A CH1 JS 51 0mA CH1 50 0mA CH2 100 0mV M20 0us A CH1 50 0mA 07932 028 07932 031 CH3 5 00V 10 40 CH3 5 00V 10 40 Figure 28 Load Transient Vour 1 8 V 10 mA to 110 mA Load Current Rise Figure 31 Load Transient Vour 3 3 V 10 mA to 110 mA Load Current Rise Time 200 ns Time 200 ns Pe BOUR VORAUS IURE C PE RE Er GR RU RT RE TUR RA i A ain EE EE SE eee TT fect OUTPUT VOLTAGE CH1 200mA CH2 100 0mV M20 0us A CH1 7 292mA 3 CH1 200 0mA CH2 50 0mV M20 0ys A
9. The synchronous rectifier stays on for the remainder of the cycle unless the inductor current reaches zero which causes the zero crossing comparator to turn off the N channel MOSFET PSM OPERATION The ADP2140 has a smooth transition to the variable frequency PSM mode of operation when the load current decreases below the pulse skipping threshold current switching only as necessary to maintain the output voltage within regulation When the output voltage dips below regulation the ADP2140 enters PWM mode for a few oscillator cycles to increase the output voltage back to regulation During the wait time between bursts both power switches are off and the output capacitor supplies the entire load current Because the output voltage occasionally dips and recovers the output voltage ripple in this mode is larger than the ripple in the PWM mode of operation PULSE SKIPPING THRESHOLD The output current at which the ADP2140 transitions from variable frequency PSM control to fixed frequency PWM control is called the pulse skipping threshold The pulse skipping threshold has been optimized for excellent efficiency over all load currents Rev 0 Page 19 of 32 ADP2140 SELECTED FEATURES SHORT CIRCUIT PROTECTION The ADP2140 includes frequency foldback to prevent output current runaway on a hard short When the voltage at the feed back pin falls below 5096 of the nominal output voltage indicating the possibility of a hard short at the o
10. V NOISE uV rms 07932 055 Rev 0 Page 16 of 32 10 0 100n m 10u 100p 1m LOAD CURRENT A 10m 100m 1 Figure 59 Output Noise vs Load Current and Output Voltage Vin2 5V 07932 261 ADP2140 Von 5 V Vm 2 3 V Vourz 1 8 V Iour 10 mA Cro Cour 1 uF Ta 25 C unless otherwise noted mut TTT F 1 1 Vour2 t Vour2 ES CH1 100mA CH2 100mV M40 0us A CH 68mA B CH1 1 00V CH2 5 00mV M2 00ys A CH4 12mV 3 10 40 8 10 20 g Figure 60 Load Transient Response Vu 4 V Vour2 1 2 V Figure 63 Line Transient Response Vovr 1 8 V Load Current 1 mA 1 mA to 300 mA Load Current Rise Time 200 ns Vin2 4 V to 5 V 1 us Rise Time y LOAD CURRENT Vour2 ER CH1 100mA CH2 100mV M40 0us A CH1 68mA CH1 1 00V CH2 5 00mV M2 00ys A CH4 12mV 3 10 40 8 10 20 g Figure 61 Load Transient Response Vu 4 V Vour2 1 8 V Figure 64 Line Transient Response Voutz 1 2 V Load Current 1 mA 1 mA to 300 mA Load Current Rise Time 200 ns Vin2 4 V to 5 V 1 us Rise Time Y LOAD CURRENT Vour2 ER
11. activation treser m TIME 07932 069 Figure 70 Individual Activation Mode Rev 0 Page 21 of 32 ADP2140 E qQ EN2 UNCONNECTED Nal 1 l I 1 i d 85 Vi po i T c treser je TIME leranr La it H792 V tss 92 Vi po Vibo 07932 111 Figure 71 Autosequencing Mode Buck First Then LDO Q ENZ UNCONNECTED H tstart as ilss i X 85 Vguck I VBuck J tReG12 07932 112 ingsET Le TIME Figure 72 Autosequencing Mode LDO First Then Buck The PG responds to the last activated regulator As described in the Power Sequencing section the regulator order in the auto sequencing mode is defined by the voltage option combination Therefore if the sequence is buck first the LDO and the PG signal are active low for treser after Vino reaches 92 of the rated output voltage at which time PG goes high and remains high for as long as Vipo is above 8696 of the rated output voltage When the sequencing is LDO first then buck Vsucx controls PG This control scheme also applies when the individual activation mode is selected As soon as either regulator output voltage drops below 8696 of the respective nominal level the PG pin is forced low 92 Vauck 3 85 Veuck Ph T 85 N_ Veuck B
12. is where the two regulators turn on in a specified order and delay after a low to high transition on the ENI pin Select the activation mode individual or autosequence by decoding the state of Pin EN2 The individual activation mode is selected when the EN2 pin is driven externally or hardwired to a voltage level VIN1 or PGND The autosequencing mode is selected when the EN2 pin remains unconnected floating To minimize quiescent current consumption the mode selection executes one time only during the rising edge of VIN1 The detection circuit then activates for the time needed to assess the EN2 state after which time the circuit is disabled until VIN1 falls below 0 5 V When EN2 is unconnected the internal control circuit provides a termination resistance to ground The 100 kQ termination resistance is low enough to guarantee insensitivity to noise and transients The termination resistor is disabled in the event that the EN2 pin is driven externally to a logic level high individual activation mode assumed to reduce the quiescent current con sumption When the autosequencing mode is selected the ENT pin is used to start the on off sequence of the regulators A logic high sequences the regulators on whereas a logic low sequences the regulators off The regulator activation order is associated with the voltage selected for the buck regulator and the LDO When the turn on or turn off autosequence starts the start up delay betwe
13. 10mA Vprop 50mA 1 50 Vprop 100mA ve Vprop 300mA 4 60 165 1 70 1 75 180 185 190 1 95 2 00 E 10 100 1k 10k 100k 1M 10M INPUT VOLTAGE V FREQUENCY Hz Ed Figure 50 Output Voltage vs Input Voltage in Dropout Figure 53 Power Supply Rejection Ratio vs Frequency Vour2 1 2 V Vivi 5 V Vin2 1 7V Rev 0 Page 15 of 32 ADP2140 Vii 5 V Vm 2 3 V Vourz 1 8 V Iour 10 mA Cro Cour 1 uF Ta 25 C unless otherwise noted PSRR dB 10 100 1k 10k 100k 1M 10M FREQUENCY Hz 07932 254 Figure 54 Power Supply Rejection Ratio vs Frequency Vour2 3 3 V Vint 5 V Vin2 4 3 V PSRR dB 10 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 55 Power Supply Rejection Ratio vs Frequency Vour2 1 8 V Vii 5 V Vin2 2 8 V 10 1 2V 1 8V 2 5V 3 3V 1 H r Ka E EI Di 0 01 10 100 1k 10k 100k FREQUENCY Hz Figure 56 Output Noise Spectrum Vinz 5 V Load Current 10 mA PSRR dB 100 1k 10k 100k FREQUENCY Hz 1M 10M 07932 256 Figure 57 Power Supply Rejection Ratio vs Frequency Vour2 3 3 V PSRR dB 07932 255 100 Vivi 1k 5V Vin2 3 8V 10k 100k FREQUENCY Hz 1M 10M 07932 257 Figure 58 Power Supply Rejection Ratio vs Frequency Vour2 1 8 V Vivi 5 V Vine 2 3
14. 140ACPZ1533R7 1 5 3 3 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LEX ADP2140ACPZ1812R7 1 8 1 2 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LEU ADP2140ACPZ1815R7 1 8 1 5 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LEY ADP2140ACPZ1833R7 1 8 3 3 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LEZ ADP2140ACPZ18812R7 1 875 1 2 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LH8 ADP2140ACPZ2518R7 2 5 1 8 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LGE ADP2140ACPZ3312R7 3 3 1 2 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LFO ADP2140ACPZ3315R7 3 3 1 5 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LF1 ADP2140ACPZ3318R7 3 3 1 8 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LF2 ADP2140ACPZ3325R7 3 3 2 5 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LF4 ADP2140ACPZ3328R7 3 3 2 8 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LF3 ADP2140CP EVALZ Evaluation Board ADP2140CPZ REDYKIT Evaluation Board 1 Z RoHS Compliant Part Rev 0 Page 30 of 32 ADP2140 NOTES Rev 0 Page 31 of 32 ADP2140 NOTES 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D07932 0 6 10 0 DEVICES www analo g com Rev 0 Page 32 of 32
15. 19 ib 40 E WW a 30 1 18 20 10 1 17 0 1 10 100 1000 1 10 100 1000 amp LOAD CURRENT mA LOAD CURRENT mA S Figure 12 Load Regulation Vour 1 2 V Wa 2 3 V Figure 15 Efficiency vs Load Current Vour 1 8 V Different Temperatures Rev 0 Page 8 of 32 Vini 4 V Vour 1 8 V Iovr 10 mA Cm Cour 10 uF Ta 25 C unless otherwise noted 100 90 80 70 60 50 40 EFFICIENCY 95 30 20 10 Figure 16 Efficiency vs Load Current Vour 1 2 V Different Input Voltages 100 EFFICIENCY a e Figure 17 Efficiency vs Load Current Vour 1 2 V Different Temperatures 2 5N 3 0V 4 0V rr 5 0V BEN 1 10 100 1000 LOAD CURRENT mA 1 10 100 1000 LOAD CURRENT mA PUT VOLTAGE OUTPUT VOLTAGE SWITCH NOD CH1 1 00V CH2 50 0mV M20 0ys A CH 4 68V CH3 5 00V 11 60 07932 020 Figure 18 Line Transient Vour 1 8 V Power Save Mode 50 mA Vw 4V to 5 V 4 us Rise Time EFFICIENCY 07932 016 EFFICIENCY 07932 017 100 90 80 ADP2140 70 60 50 40 30 20 10 100 LOAD CURRENT mA 1000 07932 019
16. 5 uA EN1 EN2 Vii or GND 1 uA Shutdown Current Isuur Vu 5 5 V ENT EN2 GND T 40 C to 85 C 0 3 1 2 uA Thermal Shutdown Threshold TSsp Ts rising 150 C Hysteresis TSsp Hys 20 oC Power Good Rising Threshold PGrise 92 N out Falling Threshold PGrau 86 NVouT Power Good Hysteresis PGuys 6 90Vour Output Low Vo Isink 4 mA 0 2 V Leakage Current lon Power good pin pull up voltage 5 5 V 1 uA Buck to LDO Delay toeLay PWM mode only 5 ms Power Good Delay tneseT PWM mode only 5 ms 1 Start up time is defined as the time between the rising edge of ENx to Vourx being at 10 of the Vour nominal value Soft start time is defined as the time between Vour being at 10 to Vourx being at 90 of the Vourx nominal value 3 Based on an endpoint calculation using 1 mA and 300 mA loads 4 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage This applies only for output voltages above 2 3 V RECOMMENDED SPECIFICATIONS CAPACITORS AND INDUCTOR Table 2 Parameter Symbol Test Conditions Comments Min Typ Max Unit MINIMUM INPUT AND OUTPUT CAPACITANCE Ta 40 C to 125 C Buck Cmn 7 5 10 uF LDO Cmn 0 7 1 0 uF CAPACITOR ESR Ta 40 C to 125 C Q Buck Resr 0 001 0 01 Q LDO Resr 0 001 1 Q MINIMUM INDUCTOR INDmin 0 7 1 uH The minimum input and output capacitance should be greater than 0 70 uF over the full range of operat
17. 65 V to 5 5 V allows it to operate from either the input or output of the buck Supply current in shutdown mode is typically 0 3 pA Internally the LDO consists of a reference an error amplifier a feedback voltage divider and a pass device The output current is delivered via the pass device which is controlled by the error amplifier forming a negative feedback system ideally driving the feedback voltage to be equal to the reference voltage If the feedback voltage is lower than the reference voltage the negative feedback drives more current increasing the output voltage If the feedback voltage is higher than the reference voltage the negative feedback drives less current decreasing the output voltage The positive supply for all circuitry except the pass device is the VINI pin The LDO has an internal soft start that limits the output voltage ramp period to approximately 130 us The LDO is available in 0 8 V 1 0 V 1 1 V 1 2 V L3 V 1 5 V 2 5 V 2 8 V 3 0 V and 3 3 V output voltage options Rev 0 Page 20 of 32 APPLICATIONS INFORMATION POWER SEQUENCING The ADP2140 has a flexible power sequencing system supporting two distinct activation modes e Individual activation control is where ENI controls only the buck regulator and EN2 controls only the LDO A high level on Pin ENI turns on the buck and a high level on Pin EN2 turns on the LDO A logic low level turns off the respective regulator e Autosequencing
18. ANALOG DEVICES 3 MHz 600 mA Low Quiescent Current Buck with 300 mA LDO Regulator ADP2140 FEATURES Input voltage range 2 3 V to 5 5 V LDO input VIN2 1 65 V to 5 5 V Buck output voltage range 1 0 V to 3 3 V LDO output voltage range 0 8 V to 3 3 V Buck output current 600 mA LDO output current 300 mA LDO quiescent current 22 pA with zero load Buck quiescent current 20 pA in PSM mode Low shutdown current 0 3 pA Low LDO dropout 110 mV 300 mA load High LDO PSRR 65 dB 10 kHz at Vour2 1 2 V 55 dB 100 kHz at Vourz 1 2 V Low noise LDO 40 pV rms at Vour 1 2 V Initial accuracy 1 Current limit and thermal overload protection Power good indicator Optional enable sequencing 10 lead 0 75 mm x 3 mm x 3 mm LFCSP package APPLICATIONS Mobile phones Personal media players Digital camera and audio devices Portable and battery powered equipment GENERAL DESCRIPTION The ADP2140 includes a high efficiency low quiescent 600 mA stepdown dc to dc converter and a 300 mA LDO packaged in a small 10 lead 3 mm x 3 mm LFCSP The total solution requires only four tiny external components The buck regulator uses a proprietary high speed current mode constant frequency pulse width modulation PWM control scheme for excellent stability and transient response To ensure the longest battery life in portable applications the ADP2140 has a power saving variable frequency mode to reduce switching fre quency under light load
19. CH P 376mA 3 CH3 5 00V 10 40 S CH3 5 00V 10 40 ZS Figure 29 Load Transient Vour 3 3 V 200 mA to 600 mA Load Current Rise Figure 32 Load Transient Vour 1 2 V 200 mA to 600 mA Load Current Rise Time 200 ns Time 200 ns SWITCH NODE ke kee lj U a i EE iti et eee LOAD CURRENT r TPUT VOLTAGE CH1 100mA CH2 100 0mV M20 0us A CH1 7 80 0mA M CH1 100 0mA CH2 50 0mV M20 0ys A CH1 P 154mA 5 CH3 5 00V 10 40 B CH3 5 00V 10 40 8 Figure 30 Load Transient Vour 3 3 V 50 mA to 250 mA Load Current Rise Figure 33 Load Transient Vour 1 2 V 50 mA to 250 mA Load Current Rise Time 200 ns Time 200 ns Rev 0 Page 11 of 32 ADP2140 Vini 4 V Vovr 1 8 V lou 10 mA Cm Cour 10 uF Ta 25 C unless otherwise noted OUTPUT VOLTAGE CH1 50 0mA CH2 50 0mV MZ20 0us A CH1 JS 48 0mA CH3 5 00V 10 40 07932 034 Figure 34 Load Transient Vour 1 2 V 10 mA to 110 mA Load Current Rise Time 200 ns SWITCH NODE TERT INDUCTOR CURRENT OUTPUT VOLTAGE CH1 500mA CH2 1 00V M100ys A CH4 2 70V CH3 5 00V CH4 5 00V 10 40 Figure 35 Startup Vour 1 8 V 10 mA INDUCTOR OUTPUT VOLTAGE CH1 500mA CH2 1 00V M40 0us A CHA J 2 70V CH3 5 00V CH4 5 00V 10 40 Figure 36 Startup Vour 1 8 V 600
20. Figure 19 Efficiency vs Load Current Vour 3 3 V Different Temperatures 4 0V 10 100 LOAD CURRENT mA 5 0V 5 5V 1000 07932 018 Figure 20 Efficiency vs Load Current Vour 3 3 V Different Input Voltages CH1 1 00V CH3 5 00V CH2 20 0mV M20 0us 11 60 A CH 4 68V 07932 021 Figure 21 Line Transient Vour 1 8 V PWM Mode 600 mA Ma 4 V to 5 V Rev 0 Page 9 of 32 4 us Rise Time ADP2140 Vini 4 V Vovr 1 8 V lou 10 mA Cm Cour 10 uF Ta 25 C unless otherwise noted CLIE HEIDE OUTPUT VOLTAGE B N H EP 1 SWITCH NODE ux st a qe itt O e Km mm r des oahi h huid S CH1 1 00V CH2 50 0mV M20 0us A CH JS 4 68V E CH1 1 00V CH2 20 0mV M20 0us A en J 4 68V i CH3 5 00V 11 60 CH3 5 00V 11 60 8 Figure 22 Line Transient Vour 1 2 V PSM Mode 50 mA Vw 2 4Vto 5 V Figure 25 Line Transient Vour 3 3 V PWM Mode 600 mA Vw 2 4 V to 5 V 4us Rise Time 4us Rise Time PUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE SWITCH NODE CH1 1 00V CH2 20 0mV M20 0us A CH JS 4 32V H CH1 200mA CH2 50 0mV M20 0yus A CH 288mA H CH3 5 00V 10 80 S CH3 5 00V 10 40
21. P package allow for a small step down dc to dc converter solution The ADP2140 operates with an input voltage from 2 3 V to 5 5 V Output voltage options are 1 0 V 1 1 V 1 2 V 1 5 V 1 8 V 1 875 V 2 5 V and 3 3 V CONTROL SCHEME The ADP2140 operates with a fixed frequency current mode PWM control architecture at medium to high loads for high efficiency but shifts to a variable frequency control scheme at light loads for lower quiescent current When operating in fixed frequency PWM mode the duty cycle of the integrated switches adjust to regulate the output voltage but when operating in power saving mode PSM at light loads the switching frequency adjusts to regulate the output voltage The ADP2140 operates in the PWM mode only when the load current is greater than the pulse skipping threshold current At load currents below this value the converter smoothly transitions to the PSM mode of operation PWM OPERATION In PWM mode the ADP2140 operates at a fixed frequency of 3 MHz set by an internal oscillator At the start of each oscillator cycle the P channel MOSFET switch is turned on putting a positive voltage across the inductor Current in the inductor increases until the current sense signal crosses the peak inductor current level that turns off the P channel MOSFET switch and turns on the N channel MOSFET synchronous rectifier This puts a negative voltage across the inductor causing the inductor current to decrease
22. RENT 10mA LOAD CURRENT 100mA LOAD CURRENT Gm m t70 E ECAD CURRENTE soma 0 LOAD CURRENT 300mA 2 2 2 6 3 0 3 4 3 8 4 2 4 6 5 0 5 4 INPUT VOLTAGE V 2 2 2 6 3 0 3 4 3 8 4 2 4 6 5 0 5 4 INPUT VOLTAGE V Figure 44 Output Voltage vs Input Voltage Different Loads Figure 47 Ground Current vs Input Voltage Different Loads 07932 244 07932 247 Rev 0 Page 14 of 32 ADP2140 Vii 5 V Vm 2 3 V Vourn 1 8 V Iovr 10 mA Cro Cour 1 uF Ta 25 C unless otherwise noted 1 0 200 0 9 180 0 8 Ei z E 0 7 a B ne A 5 S oO 05 2 z o E a 9 S E S 2 6 icno 1mA 7 lcnn 5mA icno 10mA icno 50mA icno 100mA Ignp 300mA E 1 6 17 1 8 19 20 amp TEMPERATURE C S INPUT VOLTAGE V Figure 48 Shutdown Current vs Temperature at Various Input Voltages Figure 51 Ground Current vs Input Voltage in Dropout DROPOUT VOLTAGE mV PSRR dB 1 10 100 1000 10 100 1k 10k 100k 1M tom LOAD CURRENT mA FREQUENCY Hz Ed Figure 49 Dropout Voltage vs Load Current Figure 52 Power Supply Rejection Ratio vs Frequency Vour2 1 2 V Vivi 5 V Vin2 2 2 V 1 85 1 80 _ 1 75 B 1 70 PS lt a d D 3 e Q 1 65 S E a a 1 60 2 Vprop 1mA 1 55 Vprop 5mA Vprop
23. T TORT RON NO EX a ae ees d pri LDO OUTPUT VOLTAGE CH1 50 0mV CH2 10 0mV M40 0us A CH1 P 27 0mV S CH1 10 0mV CH2 10 0mV M2 00ys A CH1 P 800pV 3 48 00 8 48 00 g Figure 89 LDO as a Postregulator see Figure 2 Vour 1 8 V Figure 90 LDO as a Postregulator see Figure 2 Vovr 1 8 V Load Current 50 mA Vourz 1 2 V Load Current 50 mA Load Current 500 mA Vour 1 2 V Load Current 50 mA Rev 0 Page 27 of 32 ADP2140 THERMAL CONSIDERATIONS In most applications the ADP2140 does not dissipate much heat due to its high efficiency However in applications with high ambient temperature and high supply voltage to output voltage differential the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125 C When the junction temperature exceeds 150 C the converter enters thermal shutdown It recovers only after the junction temperature has decreased below 130 C to prevent any permanent damage Therefore thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions The junction temperature of the die is the sum of the ambient temperature of the environment and the tempera ture rise of the package due to the power dissipation as shown in Equation 2 To guarantee reliable operation the junction temperature of the ADP2140 must not exceed
24. Transition vs Input Voltage Different Temperatures Rev 0 Page 7 of 32 ADP2140 Vini 4 V Vovr 1 8 V lou 10 mA Cm Cour 10 uF Ta 25 C unless otherwise noted 1 82 3 350 1 81 3 325 e e w 1 80 ul o o lt lt S 1 79 S 3 300 gt 2 E E 2 2 E E E 178 LOAD CURRENT 1mA gt B LOAD CURRENT 10mA 9 dors LOAD CURRENT 50mA 1 77 LOAD CURRENT 100mA LOAD CURRENT 300mA LOAD CURRENT 600mA 1 76 3 250 7 23 27 31 35 39 43 47 51 55 8 1 10 100 1000 5 INPUT VOLTAGE V S LOAD CURRENT mA Figure 10 Line Regulation Vovr 1 8 V Different Loads Figure 13 Load Regulation Vour 3 3 V 100 90 80 E 70 ul Q g o d 2 9 D 50 E o E E 40 LE TT 3 30 25V 20 3 0V AN 10 5 0V 5 5V m 0 z 3 1 10 100 1000 LOAD CURRENT mA LOAD CURRENT mA g Figure 11 Load Regulation Vour 1 8 V Vi 2 3 V Figure 14 Efficiency vs Load Current Vovr 1 8 V Different Input Voltages 1 22 100 90 1 21 80 E 70 ul Q g 1 20 60 d 2 9 D 50 E o g 1
25. UCK BUCK i 07932 072 Figure 73 Individual Activation Mode Both Regulators Sensed EN1 92 Vi po 1 1 1 1 1 1 1 1 77X 85 Vi po 1 i 1 1 1 1 1 1 T 1 1 _ treset 07932 073 Figure 74 Individual Activation Mode One Regulator Only Buck Sensed EN2 F 92 Veuck 85 Vaucx Vpuck 92 Vi po 85 Vi po Vibo tRESET 0 E ki A S 9 g S Figure 75 Individual Activation Mode No Activation Deactivation Delay Between Regulators EN1 and EN2 Pins Tied GE CH1 500mV CH2 500mV Mi 00ms A CH3 S 1 16V CH3 2 00V 10 00 07932 101 Figure 76 Autosequence Mode Turn On Behavior Buck Voltage 1 8 V LDO Voltage 1 2 V Buck Load 500 mA LDO Load 100 mA CH1 500mV CH2 500mV M40 0us A CH3 J 1 16V CH3 2 00V 10 00 07932 102 Figure 77 Autosequence Mode Turn On Behavior Buck Voltage 1 8 V LDO Voltage 1 2 V Buck Load 500 mA LDO Load 100 mA Rev 0 Page 22 of 32 ADP2140 LDO OUTPUT Z BUCK OUTPUT UTPUT ER 2 CH1 500mV CH2 500mV M40 0us A CH3 1 16V E CH1 500mV CH2 1 00V M40 0us A CH3 2 04V F CH3 2 00V 10 00 g CH3 2 00V 10 00 Figure 78 Autosequence Mode Turn On Behavior Buck Voltage 1 8 V Figure 81 Autosequence Mode Turn On Behavior Buck Voltage 1 0 V LDO Voltage 1 2 V Buck Load 500 mA LDO L
26. ed from the board temperature Ts and power dissipation Pp using the formula T Ts Pp x Yp 5 The typical Ys value for the 10 lead 3 mm x 3 mm LFCSP is 16 9 C W 140 N e e e JUNCTION TEMPERATURE C o 60 Tg 25 C 40 Tg 50 C Tp 65 C Tp 85 C Ty max 20 0 05 10 15 20 25 30 35 40 45 5 0 TOTAL POWER DISSIPATION W Figure 95 Junction Temperature vs Power Dissipation 07932 082 ADP2140 PCB LAYOUT CONSIDERATIONS Improve heat dissipation from the package by increasing the amount of copper attached to the pins of the ADP2140 However as listed in Table 10 a point of diminishing returns is eventually reached beyond which an increase in the copper size does not yield significant heat dissipation benefits Poor layout can affect the ADP2140 buck performance causing electromagnetic interference EMI and electromagnetic compa tibility EMC performance ground bounce and voltage losses thus regulation and stability can be affected Implement a good layout using the following rules e Place the inductor input capacitor and output capacitor close to the IC using short tracks These components carry high switching frequencies and long large tracks act like antennas e Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference e Use agro
27. en the first and the second regulator is fixed to 5 ms in PWM mode treci2 as shown in Figure 71 and Figure 72 When the application requires activating and deactivating the regulators at the same time use the individual activation mode which connects the EN1 and EN pins together as shown in Figure 75 ADP2140 Table 6 Power Sequencing Modes EN2 EN1 Description 0 0 Individual mode both regulators are off 0 1 Individual mode buck regulator is on 1 0 Individual mode LDO regulator is on 1 1 Individual mode both regulators are on NC Rising edge Autosequence Buck regulator turns on then the LDO regulator turns on The LDO voltage is less than the buck voltage NC Rising edge Autosequence LDO regulator turns on then the buck regulator turns on The LDO voltage is greater than the buck voltage NC Rising edge Autosequence If the buck voltage is 1 875 V then the LDO regulator always turns on first NC Falling edge Autosequence The LDO and buck regula tors turn off at the same time NC means not connected Figure 70 to Figure 75 use the following symbols as described in Table 7 Table 7 Timing Symbols Typical Symbol Description Value tstart Time needed for the internal circuitry 60 us to activate the first regulator tss Regulator soft start time 330 us treseT Time delay from power good 5ms condition to the release of PG treci2 Delay time between buck and LDO 5 ms
28. ffects the transi tion between CFM to PSM efficiency output ripple and current limit values Use the following equation to calculate the inductor ripple current Vour X Vin Vovr Vin x sw xL AI where fsw is the switching frequency 3 MHz typical L is the inductor value The dc resistance DCR value of the selected inductor affects efficiency but a decrease in this value typically means an increase in root mean square rms losses in the core and skin As a minimum requirement the dc current rating of the inductor should be equal to the maximum load current plus half of the inductor current ripple as shown by the following equation AI L 10Ap MAx 2 Ij I PK OUTPUT CAPACITOR Output capacitance is required to minimize the voltage over shoot and ripple present on the output Capacitors with low equivalent series resistance ESR values produce the lowest output ripple therefore use capacitors such as the X5R dielectric Do not use the Y5V and Z5U capacitors they are not suitable for this application because of their large variation in capacitance over temperature and dc bias voltage Because ESR is important select the capacitor using the following equation ESReour S Tuen AL where ESRcour is the ESR of the chosen capacitor Vase is the peak to peak output voltage ripple Use the following equations to determine the output capacitance V C gt IN SS 27 x fsw D xLx VippE Al
29. following figures show junction temperature calculations for different ambient temperatures total power dissipation and areas of PCB copper 145 135 125 115 105 95 85 75 65 55 45 35 25 JUNCTION TEMPERATURE C 0 0 25 0 50 0 75 1 00 1 25 1 50 1 75 2 00 2 25 2 50 2 75 3 00 TOTAL POWER DISSIPATION W 07932 078 Figure 91 Junction Temperature vs Power Dissipation Ta 25 C 140 130 120 110 100 90 80 70 JUNCTION TEMPERATURE C 60 50 0 0 25 0 50 0 75 1 00 1 25 1 50 1 75 2 00 2 25 2 50 TOTAL POWER DISSIPATION W 07932 079 Figure 92 Junction Temperature vs Power Dissipation Ta 50 C Rev 0 Page 28 of 32 145 135 125 115 105 95 85 JUNCTION TEMPERATURE C 75 GC 0 2 0 4 10 1 2 1 4 16 18 2 0 mod POWER DISSIPATION W 07932 080 Figure 93 Junction Temperature vs Power Dissipation Ta 65 C 115 105 JUNCTION TEMPERATURE C e a 85 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 TOTAL POWER DISSIPATION W 07932 081 Figure 94 Junction Temperature vs Power Dissipation Ta 85 C In cases where the board temperature is known use the thermal characterization parameter Vj to estimate the junction temper ature rise Maximum junction temperature Ty is calculat
30. he direction and amount of current to 1000 mA flowing through the power switch and synchronous rectifier The positive current limit on the power switch limits the amount of current that can flow from the input to the output and the negative current limit on the synchronous rectifier prevents the inductor current from reversing direction and flowing out of the load The ADP2140 also provides a negative current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in forced continuous conduction mode Under negative current limit conditions both the high side and low side switches are disabled POWER GOOD PIN The ADP2140 has a dedicated pin PG to signal the state of the monitored output voltages The voltage monitor circuit has an active high open drain output requiring an external pull up resistor typically supplied from the I O supply rail as shown in Figure 1 The voltage monitor circuit has a small amount of hysteresis and is deglitched to ensure that noise or external perturbations do not trigger the PG line LDO SECTION The ADP2140 low dropout linear regulator uses an advanced proprietary architecture to achieve low quiescent current and high efficiency regulation It also provides high power supply rejection ratio PSRR low output noise and excellent line and load transient response with just a small 1 uF ceramic output capa citor The wide input voltage range of 1
31. ing conditions The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met X7R and X5R type capacitors are recommended Y5V and Z5U capacitors are not recommended for use with any LDO Rev 0 Page 4 of 32 ABSOLUTE MAXIMUM RATINGS Table 3 Parameter Rating VIN1 VIN2 to PGND AGND 0 3 V to 6 5V VOUT2 to PGND AGND 0 3 V to Vina SW to PGND AGND 0 3 V to Vii FB to PGND AGND 0 3 V to 6 5 V PG to PGND AGND 0 3 V to 6 5 V ENT EN2 to PGND AGND 0 3 V to 6 5V Storage Temperature Range 65 C to 150 C Operating Ambient Temperature Range 40 C to 85 C Operating Junction Temperature Range 40 C to 125 C Soldering Conditions JEDEC J STD 020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL DATA Absolute maximum ratings apply individually only not in com bination The ADP2140 can be damaged when the junction temperature limits are exceeded Monitoring ambient temperature does not guarantee that T is within the specified temperature limits In applicati
32. irements Ceramic capacitors are manufactured with a variety of dielectrics each with different behavior over temperature and applied voltage Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions X5R or X7R dielectrics with a voltage rating of 6 3 V or 10 V are recommended for best performance Y5V and Z5U dielectrics are not recommended for use with any LDO because oftheir poor temperature and dc bias characteristics Figure 88 depicts the capacitance vs voltage bias characteristic of a 0402 1 uF 10 V X5R capacitor The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating In general a capacitor in a larger package or higher voltage rating exhibits better stability The temperature variation of the X5R dielectric is about 15 over the 40 C to 85 C tempera ture range and is not a function of package or voltage rating MURATA PART NUMBER GRM155R61A105KE15 ON 2 4 6 8 1 1 2 0 8 0 6 CAPACITANCE pF 0 4 0 2 0 0 0 07932 077 VOLTAGE V Figure 88 Capacitance vs Voltage Characteristic Use Equation 1 to determine the worst case capacitance accounting for capacitor variation over temperature component tolerance and voltage Cerr Caas x 1 TEMPCO x 1 TOL 1 where Caras is the effective capacitance at the operating voltage TEMPCO is the wors
33. is an active high open drain output requiring an external pull up resistor typically supplied from the I O supply rail as shown in Figure 1 When the sensed output voltages are below 92 of their nominal value the PG pin is held low When the sensed output voltages rise above 92 of the nominal levels the PG line is pulled high after treser The PG pin remains high as long as the sensed output voltages are above 86 of the nominal output voltage levels The typical PG delay when the buck is in PWM mode is 5 ms When the part is in PSM mode the PG delay is load dependent because the internal clock is disabled to reduce quiescent current during the sleep stage PG delay varies from hundreds of micro seconds at 10 mA up to seconds at current loads of less than 10 uA 07932 109 CH1 2 00V CH2 2 00V M2 00ms CH3 2 00V CH4 2 00V 10 20 A CH1 J 2 20V 07932 285 Figure 85 Typical PG Timing EXTERNAL COMPONENT SELECTION The external component selection for the ADP2140 application circuit that is shown in Table 8 Table 9 and Figure 86 is dependent on input voltage output voltage and load current requirements Additionally trade offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components SELECTING THE INDUCTOR The high frequency switching of the ADP2140 allows the selection of small chip inductors The inductor value a
34. mA 07932 035 07932 036 Rev 0 Page 12 of 32 CH1 500mA CH2 2 00V M40 0us A CH4 2 70V CH3 5 00V CH4 5 00V 10 40 Figure 37 Startup Vour 3 3 V 10 mA Se tele Lann ln UA ansias SWITCH NODE INDUCTOR CURRENT OUTPUT VOLTAGE ENABLE 1 CH1 500mA CH2 2 00V M40 0us A CH4 2 70V CH3 5 00V CH4 5 00V 10 40 Figure 38 Startup Vour 3 3 V 600 mA SWITCH NODE INDUCTOR CURRENT CH1 200mA CH2 1 00V M100ys A CHA 2 30V CH3 5 00V CH4 5 00V 10 40 Figure 39 Startup Vour 1 2 V 10 mA 07932 037 07932 100 07932 039 ADP2140 Vini 4 V Vour 1 8 V Iovr 10 mA Cm Cour 10 uF Ta 25 C unless otherwise noted RIES EL ERARI FARRA ES ISI LU TE CT Lun INDUCTOR CURRENT OUTPUT VOLTAGE CH1 500mA CH2 1 00V M40 0us A CHA S 2 30V E CH1 1 00V CH2 1 00V M2 00ms A CH4 2 30V E CH3 5 00V CH4 5 00V 10 00 E CH3 5 00V CHA 5 00V 10 00 Figure 40 Startup Vour 1 2 V 600 mA Figure 41 Startup Autosequence Mode Vour 1 8 V Voutz 1 2 V Rev 0 Page 13 of 32 ADP2140 LDO OUTPUT Vii 5 V Vm 2 3 V Vovr 1 8 V Iour 10 mA Cm Cour 1 uF Ta 25 C unless otherwise noted
35. nts Min Typ Max Unit BUCK SECTION Input Voltage Range Vini 2 3 5 5 V Buck Output Accuracy Vom lour 10 mA 1 5 41 5 Man 2 3 V or Vout 0 5 V to 5 5 V lour z 1 mAto600mA 2 5 42 5 96 Transient Load Regulation VrRAOAD Vo 1 8 V Load 50 mA to 250 mA rise fall time 200 ns 75 mV Load 200 mA to 600 mA rise fall time 200 ns 75 mV Transient Line Regulation Vue Line transient 4 V to 5 V 4 us rise time Vour 2 1 0V 40 mV Vour 2 1 8V 25 mV Vout 3 3 V 25 mV PWM To PSM Threshold Mun 2 3 V or Vout 0 5 V to 5 5 V 100 mA Output Current lour 600 mA Current Limit lum Mun 2 3 V or Vout 0 5 V to 5 5 V 1100 1300 mA Switch On Resistance PFET Rerer Vin 2 3 V to 5 5 V 250 mO NFET Rurer Vin 2 3 V to 5 5 V 250 moO Switch Leakage Current ILEAK sw ENT GND VIN1 5 5 V and SW 0V 1 uA Quiescent Current lo No load device not switching 20 30 uA Minimum On Time ON TIMEmin 70 ns Oscillator Frequency FREQ 2 55 3 0 3 15 MHz Frequency Foldback Threshold Vroip Output voltage where fsw lt 50 of nominal frequency 50 Start Up Time tsrART UP Vout 1 8 V 600 mA load 70 us Soft Start Time SStime Vout 1 8 V 600 mA load 150 us LDO SECTION Input Voltage Range Vine 1 65 5 5 V LDO Output Accuracy Vour2 lour2 10 mA T 25 C 1 T1 96 1 mA lt lour lt 300 mA Vinz2 Vour 0 3 V to 5 5 V T 1 5 41 5 96 25 C 1 mA lt lour2 lt 300 mA Vii Vour2 0 3 V to 5 5 V 3 3 Line Regulation AVout2 AVin2 Vinz
36. oad 100 mA LDO Voltage 3 3 V Buck Load 500 mA LDO Load 100 mA Expanded Version of Figure 80 LDO OUTPUT BUCK OUTPUT 7 CH1 1 00V CH2 1 00V Mi00ms A CH3 3 04V S CH1 500mV CH2 1 00V M40 0us A CHL 2 04V CH3 2 00V g CH3 2 00V 10 00 g Figure 79 Autosequence Mode Turn On Behavior Buck Voltage 1 8 V Figure 82 Autosequence Mode Turn Off Behavior Buck Voltage 1 0 V LDO Voltage 1 2 V Buck Load 1 mA LDO Load 100 mA LDO Voltage 3 3 V Buck Load 500 mA LDO Load 100 mA LDO OUTPUT LDO OUTPUT EP 2 CH1 500mV CH2 1 00V M2 00ms A CH3 2 04V i CH1 500mV CH2 1 00V M2 00ms A CH3 3 04V amp CH3 2 00V 10 00 B CH3 2 00V 10 00 2 Figure 80 Autosequence Mode Turn On Behavior Buck Voltage 1 0 V Figure 83 Autosequence Mode Turn On Behavior Buck Voltage 1 0 V LDO Voltage 3 3 V Buck Load 500 mA LDO Load 100 mA LDO Voltage 3 3 V Buck Load 1 mA LDO Load 100 mA Rev 0 Page 23 of 32 ADP2140 BUCK OUTPUT LDO OUTPUT CH1 500mV CH2 500mV M40 0ps A CH3 JS 1 16V CH3 2 00V 10 00 Figure 84 Individual Activation Mode EN1 and EN2 Pins Tied Together POWER GOOD FUNCTION The ADP2140 power good PG pin indicates the state of the monitored output voltages The PG function is the logical AND of the state of both outputs The PG function
37. of 32 ADP2140 LDO CAPACITOR SELECTION Output Capacitor The ADP2140 LDO is designed for operation with small space saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken about the effective series resistance ESR value The ESR of the output capacitor affects stability of the LDO control loop A minimum of 0 70 uF capa citance with an ESR of 1 Q or less is recommended to ensure stability of the ADP2140 Transient response to changes in load current is also affected by output capacitance Using a larger value of output capacitance improves the transient response of the ADP2140 to large changes in load current Figure 87 shows the transient response for an output capacitance value of 1 uF LOAD CURRENT CH1 100mA CH2 100mV M40 0ps 10 40 Figure 87 Output Transient Response Vourz 1 8 V Cour 1 pi 1 mA to 300 mA Load Current Rise Time 200 ns A CH1 68mA lt M 07932 286 H Input Bypass Capacitor Connecting a 1 uF capacitor from VIN to GND reduces the cir cuit sensitivity to the PCB layout especially when long input traces or high source impedance are encountered If greater than 1 uF of output capacitance is required increase the input capacitor to match it Input and Output Capacitor Properties Use any good quality ceramic capacitors with the ADP2140 as long as they meet the minimum capacitance and maximum ESR requ
38. on the circuit board Rev 0 Page 6 of 32 ADP2140 TYPICAL PERFORMANCE CHARACTERISTICS BUCK OUTPUT Vu 4 V Vour 1 8 V our 10 mA Cr Cour 10 uF Ta 25 C unless otherwise noted T E s z ul 8 S e gt z E Ww 2 i E RW 5 LOAD CURRENT 1mA 8 9 LOAD CURRENT 10mA LOAD CURRENT 50mA LOAD CURRENT 100mA LOAD CURRENT 300mA LOAD CURRENT 600mA 23 2 8 3 3 3 8 43 4 8 53 40 5 25 85 125 E INPUT VOLTAGE V g JUNCTION TEMPERATURE C Figure 4 Quiescent Supply Current vs Input Voltage Different Temperatures Figure 7 Output Voltage vs Temperature Van 2 3 V Different Loads 1200 1150 1100 P z 1050 i E E 1000 o al amp p 9 a Lu g H 900 E 5 D O 850 800 750 700 e 2 3 2 8 3 3 3 8 4 3 4 8 5 3 S 60 40 20 0 20 40 60 80 100 120 140 8 INPUT VOLTAGE V JUNCTION TEMPERATURE C Figure 5 Switching Frequency vs Input Voltage Different Temperatures Figure 8 Current Limit vs Temperature Different Input Voltages f m E z 9 S Ww H 5 tt 8 tt uu 2 S o H f 60 40 20 0 20 40 60 80 100 120 140 E 3 50 3 75 400 3425 450 4 75 5 00 5 25 5 50 TEMPERATURE C INPUT VOLTAGE V g Figure 6 Switching Frequency vs Temperature Different Input Voltages Figure 9 PSM to PWM Mode
39. ons with high power dissipation and poor thermal resistance the maximum ambient temperature may need to be derated In applications with moderate power dissipation and low printed circuit board PCB thermal resistance the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits The junction temperature Ty of the device is dependent on the ambient temperature T4 the power dissipation of the device Pp and the junction to ambient thermal resistance of the package 074 Maximum junction temperature T is calculated from the ambient temperature T4 and power dissipation Pp using the formula T Ta bs Pp x Oa ADP2140 Junction to ambient thermal resistance 074 of the package is based on modeling and calculation using a 4 layer board The junction to ambient thermal resistance is highly dependent on the application and board layout In applications where high maximum power dissipation exists close attention to thermal board design is required The value of Du may vary depending on PCB material layout and environmental conditions The specified values of Du are based on a 4 layer 4 in x 3 in circuit board Refer to JESD 51 7 for detailed information on the board construction For more information see AN 772 Application Note A Design and Manufacturing Guide for the Lead Frame Chip Scale Package LFCSP Wis is the junction to board thermal characte
40. ore Suit 19 Control Scheme ose dee eere 19 PWNI Operation eee e ee eH 19 PSM Operation ee 19 Pulse Skipping Threshold sss 19 Selected FEATS aient deerit ia 20 REVISION HISTORY 6 10 Revision 0 Initial Version Short CircuitProtectiori orte tte etre ties 20 Unidervoltage Lockout etit tiet 20 Thermal Protection eate ee ede Reg 20 KO e PE E nian 20 Current Limit Jesse eese R ed eed rere e 20 Power Good Pii ote eee 20 ERR 20 Applications Information EEN 21 Power TE 21 Power Good Punction sees 24 External Component Selection sss 24 Selecting the Inductor eie aceti rte eite nibns 24 Output Capacitors isisisi siisi seas LEE ni 24 Input Capacitor e 24 TEEN EE 25 Recommended Buck External Components 25 LDO Capacitor Selection EEN 26 LDO as a Postregulator to Reduce Buck Output Noise 26 Thermal Considerations seen 28 PCB Layout Considerations sse 29 Outline Dimensions En 30 e at 30 Rev 0 Page 2 of 32 SPECIFICATIONS Vmi 3 6 V Vio Vour 0 3 V or 1 65 V whichever is greater 5 V ENI EN2 Vii Iovr 200 mA lou 10 mA Cn 10 uF ADP2140 Cour 10 uF Cour 1 uF Lour 1 uH T 40 C to 125 C for minimum maximum specifications and Ta 25 C for typical specifications unless otherwise noted Table 1 Parameter Symbol Test Conditions Comme
41. rization parameter with units of C W Yp of the package is based on modeling and calculation using a 4 layer board The JESD51 12 Guidelines for Reporting and Using Package Thermal Information states that thermal characterization parameters are not the same as thermal resistances Y measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance Os Therefore Vis thermal paths include convection from the top ofthe package as well as radiation from the package factors that make Wie more useful in real world applications Maximum junction temperature T is calculated from the board temperature Ts and power dissipation Pp using the formula Tj 2 Ts Pp x Vg Refer to JESD51 8 and JESD51 12 for more detailed information about Vj THERMAL RESISTANCE Dr and Ys are specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 4 Thermal Resistance Package Type Osa Wie Unit 10 Lead 3 mm x 3 mm LFCSP 35 3 16 9 C W ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality
42. s The LDO is a low quiescent current low dropout linear regulator designed to operate in a split supply mode with Vno as low as 1 65 V The low input voltage minimum allows the LDO to be powered from the output of the buck regulator increasing effi ciency and reducing power dissipation The ADP2140 runs from input voltages of 2 3 V to 5 5 V allowing single Li Li polymer Rev 0 Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners TYPICAL APPLICATION CIRCUITS Vint 3 6V ADP2140 TZ VIN1 PGND 22 PG swe I gt EN1 AGND I 77 EN2 2 VOUT2 VIN2 7 07932 001 Figure 1 ADP2140 with LDO Connected to Vin Vint 3 3V ADP2140 2VIN1 PGND CZ 72 PG 72 EN AGND lt r T gt ENZ FBC 72 VOUT2 VIN2 7 07932 002 Figure 2 ADP2140 with LDO Connected to Buck Output cell multiple alkaline NiMH cell PCMCIA and other standard power sources ADP2140 includes a power good pin soft start and internal compensation Numerous power sequencing options are user selectable through two enable input
43. s In autosequencing mode the highest voltage output enables on the rising edge of EN1 During logic controlled shutdown the input disconnects from the output and draws less than 300 nA from the input source Other key features include undervoltage lockout to prevent deep battery discharge soft start to prevent input current overshoot at startup and both short circuit protection and thermal overload protection circuits to prevent damage in adverse conditions When the ADP2140 is used with two 0603 capacitors one 0402 capacitor one 0402 resistor and one 0805 chip inductor the total solution size is approximately 90 mm resulting in the smallest foot print solution to meet a variety of portable applications One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2010 Analog Devices Inc All rights reserved ADP2140 TABLE OF CONTENTS TE 1 E E 1 General Descriptions ectetuer eet edet 1 Typical Application Circuits sse 1 REVISION History E 2 Sp cifications uet tette tt roten 3 Recommended Specifications Capacitors and Inductor 4 Absolute Maximum Ratings esent 5 Thermal Data aesti a ae RI EE 5 Thermal Resistance eei t EHE EIER 5 ESD Caution erae E 5 Pin Configuration and Function Descriptions 6 Typical Performance Characteristics een 7 e OU H LED O Outp t eU R 14 Theory GEDEELT 19 l
44. sses occur because the P channel switch cannot turn on or turn off instantaneously In the middle of an SW node transition the power switch provides all of the inductor current The source to drain voltage of the power switch is half the input voltage resulting in power loss Transition losses increase with both load current and input voltage and occur twice for each switching cycle Use the following equation to estimate transition losses Prran Vin 2 X Tour X t tf x fsw where t is the rise time of the SW node tris the fall time of the SW node RECOMMENDED BUCK EXTERNAL COMPONENTS The recommended buck external components for use with the ADP2140 are listed in Table 8 inductors and Table 9 capacitors Vun AEN ADP2140 gt VIN PGND CZ IIPG SW c 72 EN1 AGND c7 7 EN2 FBC T gt VOUT2 VIN2c 07932 076 Figure 86 Typical Application Circuit with LDO Connected to Input Voltage Vendor Model Case Size Dimensions ISAT mA DCR mQ Murata LQM21PN1ROMCOD 0805 2 0 mm x 1 25 mm x 0 5 mm 800 190 Murata LOM31PN1ROMOOL 1206 3 2 mm x 1 6 mm x 0 95 mm 1200 120 Murata LQM2HPN1ROMJO 1008 2 5 mm x 2 0 mm x 0 95 mm 1500 90 FDK MIPSA2520D1RO 2 5 mm x 2 0 mm x 1 0 mm 1200 90 Table 9 10 uF Capacitors Vendor Type Model Case Size Voltage Rating Murata X5R GRM219R60J106 0805 6 3V Taiyo Yuden X5R JMK212BJ106 0805 6 3V TDK X5R C1608X5R0J106 0603 6 3V Rev 0 Page 25
45. t case capacitor temperature coefficient TOL is the worst case component tolerance In this example the worst case temperature coefficient TEMPCO over 40 C to 85 C is assumed to be 15 for an X5R dielectric The tolerance of the capacitor TOL is assumed to be 10 and Cans is 0 94 uF at 1 8 V as shown in Figure 88 Substituting these values in Equation 1 yields Czrr 0 94 uF x 1 0 15 x 1 0 1 0 719 uF Therefore the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temper ature and tolerance at the chosen output voltage To guarantee the performance of the ADP2140 it is imperative that the effects of dc bias temperature and tolerances on the behavior of the capacitors are evaluated for each application LDO AS A POSTREGULATOR TO REDUCE BUCK OUTPUT NOISE The output of the buck regulator may not be suitable for many noise sensitive applications because of its inherent switching noise This is particularly true when the buck is operating in PSM mode because the switching noise may be in the audio range The ADP2140 LDO can greatly reduce the noise at the output of the buck at high efficiency because of the load dropout voltage of the LDO and the high PSRR of the LDO Figure 89 and Figure 90 show the noise reduction that is possible when the LDO is used as a post regulator Rev 0 Page 26 of 32 ADP2140 ae BUCK OUTPUT VOLTAGE colt OIN M YA amt DIN
46. und plane with several vias connected to the component side ground to reduce noise interference on sensitive circuit nodes e Use of 0402 or 0603 size capacitors achieves the smallest possible footprint solution on boards where area is limited 07932 083 Figure 96 PCB Layout Top 07932 084 Figure 97 PCB Layout Bottom Rev 0 Page 29 of 32 ADP2140 OUTLINE DIMENSIONS PIN 1 INDEX AREA 0 50 BSC 3 00 0 23 BSC SQ Uis 4 i 2 EXPOSED PAD BOTTOM VIEW Tag Y o A E e eo L LA eo AN eo eo 3 e eo PIN 1 TOP VIEW nos 0 80 MAX 0 80 0 55 NOM Sg 0 75 0 05 MAX 0 70 i ae NOM LL SEATING PLANE 0 20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO i THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION amp OF THIS DATA SHEET 8 Figure 98 10 Lead Lead Frame Chip Scale Package LFCSP_WD 3mm x 3 mm Body Very Very Thin Dual Lead CP 10 9 Dimensions shown in millimeters ORDERING GUIDE Buck Output LDO Output Package Model Voltage V Voltage V Temperature Range Package Description Option Branding ADP2140ACPZ1218R7 1 2 1 8 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LET ADP2140ACPZ1228R7 1 2 2 8 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LEO ADP2140ACPZ1233R7 1 2 3 3 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LER ADP2140ACPZ1528R7 1 5 2 8 40 C to 125 C 10 Lead LFCSP WD CP 10 9 LES ADP2
47. utput the switching frequency is reduced to 1 2 of the internal oscillator frequency The reduc tion in the switching frequency gives more time for the inductor to discharge preventing a runaway of output current UNDERVOLTAGE LOCKOUT To protect against battery discharge undervoltage lockout circuitry is integrated on the ADP2140 If the input voltage drops below the 2 15 V UVLO threshold the ADP2140 shuts down and both the power switch and synchronous rectifier turn off When the voltage rises again above the UVLO threshold the soft start period initiates and the part is enabled THERMAL PROTECTION In the event that the ADP2140 junction temperatures rises above 150 C the thermal shutdown circuit turns off the converter Extreme junction temperatures can be the result of high current operation poor circuit board design and or high ambient tem perature A 20 C hysteresis is included thus when thermal shutdown occurs the ADP2140 does not return to operation until the on chip temperature drops below 130 C When emerging from a thermal shutdown soft start initiates SOFT START The ADP2140 has an internal soft start function that ramps the output voltage in a controlled manner upon startup thereby limiting the inrush current This prevents possible input voltage drops when a battery or a high impedance power source is con nected to the input of the converter CURRENT LIMIT The ADP2140 has protection circuitry to limit t

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