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ANALOG DEVICES ADP221 handbook

1. 2 85 140 lLoAp 10HA ILoap 100 120 ILoap 1mA ILoap 10mA 5 lLoAp 100mA lt 100 ur ILoap 200mA 28 S E o gt 3 g 279 o 60 2 5 lLoAp 100A o 6 40 100 1 2 77 10mA 20 100mA 200mA 2 75 0 40 5 25 85 125 3 40 5 25 85 125 S JUNCTION TEMPERATURE C B JUNCTION TEMPERATURE C B Figure 4 Output Voltage vs Junction Temperature Figure 7 Ground Current vs Junction Temperature Single Output Loaded 2 85 120 Vour 2 8V 100 VN 3 3V 2 83 Ta 25 C T ur 80 9 2 81 2 3 60 gt 3 2 2 79 2 5 5 2 40 2 77 20 2 75 i 0 0 01 0 1 1 10 100 1k 8 0 01 0 1 1 10 100 1k amp LOAD CURRENT mA g LOAD CURRENT mA Figure 5 Output Voltage vs Load Current Figure 8 Ground Current vs Load Current Single Output Loaded 2 85 120 100A 100 1 100 2 83 10mA 100 T S LOAD T 200mA 80 Q 281 2 3 5 60 gt 3 a gt 279 o 40 a 2 100A 1 2 77 ILoap 10mA 20 100mA ILoap 200mA 2 75 0 33 35 37 39 41 43 45 47 49 51 53 55 33 35 37 39 41 43 45 47 49 51 53 55 INPUT VOLTAGE V B INPUT VOLTAGE V 8 Figure 6 Output Voltage
2. 12 Capacitor Selection ecce tet ta 12 Undervoltage Lockout see 13 Enable Featurez eui eee e 13 Current Limit and Thermal Overload Protection 14 Thermal Considerations seen 14 Printed Circuit Board PCB Layout Considerations 16 Outline Dimensions eese tentent nenne 17 Ordering Glide coetu 17 Changes to Figure 25 sse Changes to Enable Feature Section and Figure 32 Changes to Current Limit and Thermal Overland Protection Section and Thermal Considerations Section 14 Changes to Ordering Guide sse 17 3 09 Rev 0 to Rev A Changes to Fig re 15 sasssa 8 Chan ges to Figure 16 ure mea eir Oe dis 9 Changes to Ordering Guide sse 17 10 08 Revision 0 Initial Version Rev D Page 2 of 20 SPECIFICATIONS ADP220 ADP221 Vm 0 5 V or 2 5 V whichever is greater EN2 Vi 10 mA Cis Coun Cour 1 uF Ta 25 C unless otherwise noted Table 1 Parameter Symbol Conditions Min Typ Max Unit INPUT VOLTAGE RANGE Vin T 2 40 C to 125 C 2 5 5 5 V OPERATING SUPPLY CURRENT WITH len lout pA 60 HA BOTH REGULATORS ON lout 0 uA T 40 C to 125 C 120 HA lour 10 mA 70 HA lout 10 mA T 40 C to 125 C
3. 200mA 0 o 33 3 5 37 39 41 43 45 47 49 51 53 55 5 2 6 27 2 8 2 9 3 0 34 5 INPUT VOLTAGE V E INPUT VOLTAGE V B Figure 12 Ground Current vs Input Voltage Both Outputs Loaded Figure 15 Output Voltage vs Input Voltage In Dropout Rev D Page 8 of 20 ADP220 ADP221 VnippLg 50mV Vin 2 5V Vout 0 8V Cour 1HF T E a g o 2 o m d lLoAp 5mA 10mA 50mA ILoap 100mA lLoAp 200mA 3 10 100 1k 10k 100k 1M 10M 5 INPUT VOLTAGE V R FREQUENCY Hz B Figure 16 Ground Current vs Input Voltage In Dropout Figure 19 Power Supply Rejection Ratio vs Frequency 0 8 V 0 VrippLe 50mV 3 3VI200mA 0 8V 200mA 1 8V 200mA Vin 3 8V 10 Vour 2 8V 3 3 400 0 8V 1000A 1 8 100 Cour 2 2uF 20 30 T iJ iJ 4 50 o o a _60 70 80 90 100 E 10 100 1k 10k 100k 1M 10M 5 10 100 1k 10k 100k 1M 10M 3 FREQUENCY Hz E FREQUENCY Hz B Figure 17 Power Supply Rejection Ratio vs Frequency 2 8 V Figure 20 Power Supply Rejection Ratio vs Frequency at Various Output Voltages and Load Currents 10 VRIPPLE 50mV 3 3V Vin 4 3V E 2 8V uVN Hz Vour 3 3V E 0 8V uV Hz Cour 1uF z gt 5 1 a E a d 0 o 2 01 gt
4. ANALOG DEVICES FEATURES Input voltage range 2 5 V to 5 5 V Dual independent 200 mA low dropout voltage regulators Miniature 6 ball 1 0 mm x 1 5 mm WLCSP Initial accuracy 1 Stable with 1 pF ceramic output capacitors No noise bypass capacitor required Two independent logic controlled enables Overcurrent and thermal protection Active output pull down ADP221 Key specifications High PSRR 76 dB PSRR up to 1 kHz 70 dB PSRR at 10 kHz 60 dB PSRR at 100 kHz 40 dB PSRR at 1 MHz Low output noise 27 pV rms typical output noise at Vout 1 2 V 50 pV rms typical output noise at Vout 2 8 V Excellent transient response Low dropout voltage 150 mV 200 mA load 60 pA typical ground current at no load both LDOs enabled 100 us fast turn on circuit Guaranteed 200 mA output current per regulator 40 C to 125 C junction temperature APPLICATIONS Mobile phones Digital cameras and audio devices Portable and battery powered equipment Portable medical devices Post dc to dc regulation GENERAL DESCRIPTION The 200 mA dual output ADP220 ADP221 combine high PSRR low noise low quiescent current and low dropout voltage in a voltage regulator ideally suited for wireless applications with demanding performance and board space requirements The low quiescent current low dropout voltage and wide input voltage range of the ADP220 ADP221 extend the battery life of portable devices The ADP220 ADP221 maintain power supply rejection
5. 26235R7 40 C to 125 2 6 2 35 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 LOL ADP220ACBZ 2812R7 40 C to 125 C 2 8 1 2 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 L8X ADP220ACBZ 2818R7 40 C to 125 C 2 8 1 8 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 LEL ADP220ACBZ 2827R7 40 C to 125 2 8 2 7 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 L8Y ADP220ACBZ 2828R7 40 C to 125 2 8 2 8 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 L8W ADP220ACBZ275275R7 40 C to 125 2 75 2 75 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 L8Z ADP221ACBZ3033 R7 40 C to 125 3 0 3 3 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 LH4 ADP221ACBZ2828 R7 40 C to 125 C 2 8 2 8 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 L90 ADP220 2828 EVALZ 40 C to 125 C 2 8 2 8 2 8 V 2 8 V Evaluation Board ADP221 2828 EVALZ 40 C 125 C 2 8 2 8 2 8 V 2 8 V with Output Discharge Evaluation Board 17 RoHS Compliant Part For additional voltage options contact a local Analog Devices sales or distribution representative Rev D Page 17 of 20 ADP220 ADP221 NOTES Rev D Page 18 of 20 ADP220 ADP221 NOTES Rev D Page 19 of 20 ADP220 ADP221 NOTES 2008 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D07572 0 5 10 D
6. By CH2 5 00mV By 20 0 A CH1 4 46V CH3 5 00mV v By 10 00 Figure 26 Line Transient Response Vin 4 V to 5 V lop 200 lioap2 1 mA 4 y Vin CH2 Vovri CH3 Vovrz 5 00V By CH2 2 00V By M40 0us A CHI 2 10V CH3 2 00V By 9 80 Figure 27 Shutdown Response ADP221 07572 025 07572 026 07572 027 ADP220 ADP221 THEORY OF OPERATION The ADP220 ADP221 are low quiescent current low dropout linear regulators that operate from 2 5 V to 5 5 V and provide up to 200 mA of current from each output Drawing a low 120 uA quiescent current typical at full load makes the ADP220 ADP221 ideal for battery operated portable equipment Shut down current consumption is typically 100 nA Optimized for use with small 1 uF ceramic capacitors the ADP220 ADP221 provide excellent transient performance THERMAL CURRENT SHUTDOWN LIMIT CONTROL LOGIC AND ENABLE CURRENT LIMIT ADP220 VOUT2 Figure 28 Internal Block Diagram 07572 028 Internally the ADP220 ADP221 consist of a reference two error amplifiers two feedback voltage dividers and two PMOS pass transistors Output current is delivered via the PMOS pass device which is controlled by the error amplifier The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference If the feedback voltage is lower than the reference voltage the gate
7. DEVICES www analog com Rev D Page 20 of 20
8. vs Input Voltage Figure 9 Ground Current vs Input Voltage Single Output Loaded Rev D Page 7 of 20 ADP220 ADP221 160 140 z 120 5 E 5 100 E gt 80 2 60 9 i ira 3 o Loan 199p 40 1 ILoap 10 20 ILoap 100mA ILoap 200mA 0 e E 40 5 25 85 125 5 5 JUNCTION TEMPERATURE TEMPERATURE B Figure 10 Ground Current vs Junction Temperature Both Outputs Loaded Figure 13 Shutdown Current vs Temperature at Various Input Voltages 140 250 2 8V 120 3V 25 200 z q 100 t ul a Q 150 A E o 3 gt o 60 2 100 5 o 2 9 amp 40 a 50 20 0 2 0 0 01 0 1 1 10 100 1 5 1 10 100 1k 5 LOAD CURRRENT mA LOAD CURRENT mA B Figure 11 Ground Current vs Load Current Both Outputs Loaded Figure 14 Dropout Voltage vs Load Current and Output Voltage 140 120 q 100 2 80 E 8 gt o 60 5 3 lLoAp 10HA 2 49 100pA fa 1 o 1mA 5mA 10mA 10mA 20 100mA 50mA 200mA ILoap 100 ILoap
9. 125 115 105 95 JUNCTION TEMPERATURE C JUNCTION TEMPERATURE C 0 01 02 03 04 05 06 07 08 09 1 0 TOTAL POWER DISSIPATION W 0 01 02 03 04 05 06 0 7 08 09 1 0 TOTAL POWER DISSIPATION W 07572 035 07572 038 Figure 35 Junction Temperature vs Total Power Dissipation Ta 25 Figure 38 Junction Temperature vs Total Power Dissipation Ta 85 C 140 130 120 110 100 90 80 70 JUNCTION TEMPERATURE C JUNCTION TEMPERATURE C 60 50 0 01 02 03 04 05 06 0 7 08 09 1 0 TOTAL POWER DISSIPATION W 0 0 2 04 06 08 1 0 12 14 16 18 20 22 24 TOTAL POWER DISSIPATION W 07572 036 07572 039 Figure 36 Junction Temperature vs Total Power Dissipation Ta 50 C Figure 39 Junction Temperature vs Total Power Dissipation and Board Temperature 145 135 125 115 105 95 85 JUNCTION TEMPERATURE C 75 65 0 01 02 03 04 05 06 07 08 09 1 0 TOTAL POWER DISSIPATION W 07572 037 Figure 37 Junction Temperature vs Total Power Dissipation TA 65 C Rev D Page 15 of 20 ADP220 ADP221 PRINTED CIRCUIT BOARD PCB LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP220 ADP221 However a
10. 140 HA lour 200 mA 120 HA lout 200 mA T 40 C to 125 C 220 HA SHUTDOWN CURRENT lanD sD EN1 EN2 GND 0 1 HA EN1 EN2 GND T 40 C to 125 C 2 HA FIXED OUTPUT VOLTAGE ACCURACY Vout 1 1 100 pA lt lout lt 200 mA Vin Vout 0 5 V to 2 2 5 5 V Ty 40 C to 125 C LINE REGULATION AVour AV Vin Vout 0 5 V to 5 5 V 0 01 V Vin Vour 0 5 V to 5 5 V T 40 C to 125 C 0 03 40 03 V LOAD REGULATION AVour Alour lour 1 mA to 200 mA 0 001 96 mA lour 1 mA to 200 T 40 C to 125 C 0 003 mA DROPOUT VOLTAGE Voropour Vout 3 3 V mV lour 10 mA 7 5 mV lout 10 mA T 40 C to 125 C 12 mV lout 200 mA 150 mV lout 200 mA T 40 C to 125 C 230 mV START UP TIME tsrART UP Vout 3 3 V both initially off enable one 240 us Vout 0 8 V both initially off enable one 100 us Vout 3 3 V one initially on enable second 180 us Vout 0 8 V one initially on enable second 20 us ACTIVE PULL DOWN RESISTANCE tsHUTDOWN Vout 2 8 V Cour 1 UF ADP221 only 80 Q CURRENT LIMIT THRESHOLD limir 240 300 440 mA THERMAL SHUTDOWN Thermal Shutdown Threshold TSsp Ty rising 155 Thermal Shutdown Hysteresis TSsp nys 15 EN INPUT EN Input Logic High Vin 25V lt Vn lt 5 5V 1 2 V EN Input Logic Low Vit 2 5V lt Vn lt 5 5V 0 4 V EN Input Leakage Current VI LEAKAGE EN1 EN2 Vin or GND 0 1 HA EN1 EN2 Vin or GND T 40 C to 125 C 1 HA UND
11. 8 V to 3 3 V and offer overcur rent and thermal protection to prevent damage in adverse conditions One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2008 2010 Analog Devices Inc All rights reserved ADP220 ADP221 TABLE OF CONTENTS Feat 1 Applications eite ble tan eri SER CURE 1 Typical Application Circuits seen 1 General Description kiss sasssa sasssa 1 REVISION HistOby asian 2 Specifications oet em ttem oin 3 Input and Output Capacitor Recommended Specifications 4 Absolute Maximum Ratings seen 5 Thermal Data s s sasssa 5 Thermal Resistance serene tentent 5 ESD Catti nearen E E netten 5 Pin Configuration and Function 6 REVISION HISTORY 5 10 Rev C to Rev D Changes to Figure idee sasssa issi Changes to Ordering Guide 1 10 Rev B to Rev C Changes to Figure 24 iei aree ee ERA 10 10 09 Rev A to Rev B Changes to Features Section sse 1 Changes to Table 3 and Table 4 sss 5 Changes to Figure 4 Figure 6 Figure 7 and Figure 9 7 Changes to Figure 10 and Figure 12 sse 8 Changes t Figure 17 sues petitis 9 Typical Performance Characteristics see 7 Theory of Operation uie ote tte e ertet 11 Applications Information
12. DP220 ADP221 to large changes in the load current Figure 29 and Figure 30 show the transient responses for output capacitance values of 1 uF and 4 7 uF respectively D1 1mA 200mA ILoap2 1 Vour2 Cour 1 m y ns m 200mA QBw CH2 50 0mV By M200ns A CH1 132mA CH3 10 0mV By 26 60 07572 029 Figure 29 Output Transient Response 1 to 200 mA lioap2 1 mA CH1 hoap1 CH2 Vouri CH3 Vovrz Covr 1 UF y ILoap1 lLoAp1 1 TO 200mA l oApz 1mA Vout Vour2 Cour 4 7uF y 00us m 200mA OBy CH2 50 0mV By 1 00 A CH1 132mA CH3 10 0mV By 11 4096 07572 030 Figure 30 Output Transient Response Loap1 1 mA to 200 mA loup 1 mA CH1 hospi CH2 Vouri CH3 Vour2 Cour 4 7 UF Input Bypass Capacitor Connecting 1 uF capacitor from VIN to GND reduces the circuit sensitivity to the PCB layout especially when long input traces or high source impedance are encountered If an output capacitance greater than 1 uF is required the input capacitor should be increased to match it Input and Output Capacitor Properties Any good quality ceramic capacitor can be used with the ADP220 ADP221 as long as the capacitor meets the minimum capacit ance and maximum ESR requirements Ceramic capacitors are manufactured with a variety of dielectrics e
13. ERVOLTAGE LOCKOUT UVLO Input Voltage Rising UVLOrise 2 45 V Input Voltage Falling UVLOra 22 V Hysteresis UVLOnys 100 mV OUTPUT NOISE OUT noise 10 Hz to 100 kHz Vin 5 V Vout 3 3 V 56 rms 10 Hz to 100 kHz Vin 5 V Vout 2 8 V 50 rms 10 Hz to 100 kHz Vin 3 6 V Vout 2 5 V 45 rms 10 Hz to 100 kHz Vin 3 6 V Vout 1 2 V 27 rms Rev D Page 3 of 20 ADP220 ADP221 Parameter Symbol Conditions Min Typ Max Unit POWER SUPPLY REJECTION RATIO PSRR Vin 2 5 V Vour 0 8 V lour 100 mA 100 Hz 76 dB 1 kHz 76 dB 10 kHz 70 dB 100 kHz 60 dB 1 MHz 40 dB Vin 3 8 V Vout 2 8 V lour 100 mA 100 Hz 68 dB 1 kHz 68 dB 10 kHz 68 dB 100 kHz 60 dB 1 MHz 40 dB Based on an end point calculation using 1 mA and 200 mA loads Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage This applies only for output voltages above 2 5 V 3 Start up time is defined as the time between the rising edge of ENx to Vour being at 90 of its nominal value 4 Current limit threshold is defined as the current at which the output voltage drops to 90 of the specified typical value For example the current limit for a 3 0 V output voltage is defined as the current that causes the output voltage to drop to 9096 of 3 0 V or 2 7 V INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS Table 2 Parameter Symbol Cond
14. ach with a different behavior over temperature and applied voltage Capacitors must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions X5R or X7R dielectrics with a voltage rating of 6 3 V or 10 V are recommended Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics Figure 31 depicts the capacitance vs voltage bias characteristic of an 0402 1 uF 10 V X5R capacitor The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating In general a capacitor in a larger package or higher voltage rating exhibits better stability The temperature variation of the X5R dielectric is about 15 over the 40 C to 85 C tempera ture range and is not a function of the package or voltage rating 1 0 0 8 0 6 CAPACITANCE uF 0 4 0 2 0 2 4 6 8 10 VOLTAGE V 07572 031 Figure 31 Capacitance vs Voltage Bias Characteristic Rev D Page 12 of 20 ADP220 ADP221 Equation 1 can be used to determine the worst case capacitance accounting for capacitor variation over temperature compo nent tolerance and voltage Czrr 1 TEMPCO 1 TOL 1 where Caras is the effective capacitance at the operating voltage TEMPCO is the worst case capacitor temperature coefficient TOL is the worst case component tolerance In this example TEMPCO ov
15. ations that can occur due to noise on the ENx pins as it passes through the threshold points The active inactive thresholds of the ENx pins are derived from the VIN voltage Therefore these thresholds vary with changing input voltage Figure 33 shows typical ENx active inactive thresh olds when the input voltage varies from 2 5 V to 5 5 V ENx PINS THRESHOLD V INPUT VOLTAGE V 07572 033 Figure 33 Typical ENx Pins Thresholds vs Input Voltage The ADP220 ADP221 utilize an internal soft start to limit the inrush current when the output is enabled The start up time for the 2 8 V option is approximately 220 us from the time the ENx active threshold is crossed to when the output reaches 90 of its final value The start up time is somewhat dependent on the output voltage setting and increases slightly as the output voltage increases 5 00V By 2 2 00VBy M40 0us CH1 2 10V CH3 2 00V By 9 80 07572 034 Figure 34 Typical Start Up Time Rev D Page 13 of 20 ADP220 ADP221 CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION The ADP220 ADP221 are protected against damage due to excessive power dissipation by current and thermal overload protection circuits The ADP220 ADP221 are designed to current limit when the output load reaches 300 mA typical When the output load exceeds 300 mA the output voltage is reduced to maintain a constant current limit Thermal overloa
16. d protection is built in which limits the junction temperature to a maximum of 155 C typical Under extreme conditions that is high ambient temperature and power dissipation when the junction temperature starts to rise above 155 C the output is turned off reducing the output current to zero When the junction temperature drops below 140 C the output is turned on again and the output current is restored to its nominal value Consider the case where a hard short from VOUTx to GND occurs At first the ADP220 ADP221 current limit so that only 300 mA is conducted into the short If self heating of the junction is great enough to cause its temperature to rise above 155 C thermal shutdown activates turning off the output and reducing the output current to zero As the junction temperature cools and drops below 140 C the output turns on and conducts 300 mA into the short again causing the junction temperature to rise above 155 C This thermal oscillation between 140 C and 155 C causes a current oscillation between 0 mA and 300 mA that continues as long as the short remains at the output Current and thermal limit protections are intended to protect the device against accidental overload conditions For reliable operation device power dissipation must be externally limited so that junction temperatures do not exceed 125 C THERMAL CONSIDERATIONS In most applications the ADP220 ADP221 do not dissipate much heat due to high eff
17. er 40 C to 85 C is assumed to be 1596 for an X5R dielectric TOL is assumed to be 1096 and is 0 94 uF at 1 8 V from the graph in Figure 31 Substituting these values into Equation 1 yields 0 94 uF x 1 0 15 x 1 0 1 20 719 uF Therefore the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage To guarantee the performance of the ADP220 ADP221 it is imperative that the effects of dc bias temperature and toler ances on the behavior of the capacitors be evaluated for each application UNDERVOLTAGE LOCKOUT The ADP220 ADP221 have an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 2 2 V This ensures that the inputs of the ADP220 ADP221 and the output behave in a predictable manner during power up ENABLE FEATURE The ADP220 ADP221 use the ENx pins to enable and disable the VOUTx pins under normal operating conditions Figure 32 shows a rising voltage on ENx crossing the active threshold then Vour turns on When a falling voltage on ENx crosses the inactive threshold Vourx turns off Voutx 500mV By CH2 500mV By 10 0 A 2 J 1 76V 27 40 07572 032 Figure 32 Typical ENx Pin Operation As shown in Figure 32 the ENx pins have built in hysteresis This prevents on off oscill
18. g ambient temper ature does not guarantee that the junction temperature Tj is within the specified temperature limits In applications with high power dissipation and poor thermal resistance the maximum ambient temperature may have to be derated In applications with moderate power dissipation and low PCB thermal resistance the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits The junction temperature Tj of the device is dependent on the ambient temperature Ta the power dissipation of the device Pp and the junction to ambient thermal resistance of the package Maximum junction temperature is calculated from the ambient temperature Ta and power dissipation Pp using the following formula Ty Ta Pp x Oa Junction to ambient thermal resistance of the package is based on modeling and calculation using a 4 layer board The junction to ambient thermal resistance is highly dependent on the application and board layout In applications where high maximum power dissipation exists close attention to thermal board design is required The value of 0j4 may vary depending on PCB material layout and environmental conditions The specified values of are based on a four layer 4 inch x 3 inch circuit board Refer to JEDEC JESD 51 9 for detailed informa tion on the board construction For additional information see the AN 617 Applica
19. greater than 60 dB for frequencies as high as 100 kHz while operating with a low headroom voltage The ADP220 offers much lower noise performance than competing LDOs Rev D Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Dual 200 mA Low Noise High PSRR Voltage Regulator ADP220 ADP221 TYPICAL APPLICATION CIRCUITS GND VIN Ma Moz TOP VIEW Not to Scale m f S EN2 VOUT2 5 A amp D 6 5 CURRENT LIMIT CONTROL LOGIC AND ENABLE ADP220 CURRENT LIMIT 07572 002 Figure 2 Block Diagram of the ADP220 ADP221 without the need for a noise bypass capacitor The ADP221 also includes an active pull down to quickly discharge output loads The ADP220 ADP221 are available in a miniature 6 ball WLCSP package and is stable with tiny 1 uF 30 ceramic output capacitors resulting in the smallest possible board area for a wide variety of portable power needs The ADP220 ADP221 are available in many output voltage combinations ranging from 0
20. iciency However in applications with a high ambient temperature and high supply voltage to output voltage differential the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125 C When the junction temperature exceeds 155 C the converter enters thermal shutdown It recovers only after the junction temperature has decreased below 140 C to prevent any permanent damage Therefore thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions The junction temperature of the die is the sum of the ambient temperature of the environment and the tempera ture rise of the package due to the power dissipation as shown in Equation 2 To guarantee reliable operation the junction temperature of the ADP220 ADP221 must not exceed 125 C To ensure that the junction temperature stays below this maximum value the user needs to be aware of the parameters that contribute to junction temperature changes These parameters include ambient tem perature power dissipation in the power device and thermal resistances between the junction and ambient air The Oja number is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered on the PCB Table 6 shows typical values for the ADP220 ADP221 for various PCB copper sizes Table 6 T
21. itions Min Typ Max Unit MINIMUM INPUT AND OUTPUT CAPACITANCE Ta 40 to 125 0 70 uF CAPACITOR ESR Resr Ta 40 C to 125 C 0 001 1 Q 1 The minimum input and output capacitance should be greater than 0 70 uF over the full range of operating conditions The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met X7R and X5R type capacitors are recommended Y5V and Z5U capacitors are not recommended for use with LDOs Rev D Page 4 of 20 ADP220 ADP221 ABSOLUTE MAXIMUM RATINGS Table 3 Parameter Rating VIN to GND 0 3 V to 6 5 V VOUT1 VOUT2 to GND 0 3 V to VIN EN1 EN2 to GND 0 3 V to 6 5 V Storage Temperature Range 65 C to 150 C Operating Junction Temperature Range 40 C to 125 C Soldering Conditions JEDEC J STD 020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL DATA Absolute maximum ratings apply individually only not in combination The ADP220 ADP221 can be damaged when the junction temperature limits are exceeded Monitorin
22. n E 2 o z 0 01 10 100 1k 10k 100k 1M 10M 5 10 100 1k 10k 100k FREQUENCY Hz B FREQUENCY Hz Figure 18 Power Supply Rejection Ratio vs Frequency 3 3 V Figure 21 Output Noise Spectrum Vin 5 V lLoa 10 MA Rev D Page 9 of 20 ADP220 ADP221 60 NOISE rms 0 0 001 0 01 0 1 1 10 100 1k LOAD CURRENT mA 07572 022 Figure 22 Output Noise vs Load Current and Output Voltage Vn 5 V 200mA QBw CH2 50 0mV By M40 0us A 7 132mA CH3 10 0mV By 10 00 07572 023 Figure 23 Load Transient Response 1 1 MA to 200 mA lioap 1 MA CH1 lioan CH2 Vouri CH3 Vovr2 200mA QBw CH2 50 0mV By 40 0 A CH1 132mA CH3 10 0mV By 10 00 07572 024 Figure 24 Load Transient Response 1 mA to 200 MA 100 mA CH1 lioan CH2 Vouri CH3 Vour2 Rev D Page 10 of 20 Vin 4V TO 5V li 200mA ILoap2 100mA 1 00V By CH2 5 00mV By M20 0us A CH1 4 46V CH3 5 00mV v By 13 60 Figure 25 Line Transient Response Vin 4V to 5 V hoap1 200 lioap2 100 mA 9 CH1 Vin CH2 CH3 Vin 4V 5V 200 lj 1mA Vouri 1 00V
23. of the PMOS device is pulled lower allowing more current to flow and increasing the output voltage If the feedback voltage is higher than the reference voltage the gate of the PMOS device is pulled higher allowing less current to flow and decreasing the output voltage The ADP221 also includes an active pull down circuit to rapidly discharge the output load capacitance when each output is disabled The ADP220 ADP221 are available in multiple output voltage options ranging from 0 8 V to 3 3 V The ADP220 ADP221 use the EN1 EN2 pins to enable and disable the VOUT1 VOUT2 pins under normal operating conditions When EN1 EN2 are high VOUT1 VOUT2 turn on when EN1 EN2 are low VOUTI VOUT turn off For automatic startup EN1 EN2 can be tied to VIN Rev D Page 11 of 20 ADP220 ADP221 APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor The ADP220 ADP221 are designed for operation with small space saving ceramic capacitors but the parts function with most commonly used capacitors as long as care is taken with regards to the effective series resistance ESR value The ESR of the output capacitor affects stability of the LDO control loop A minimum of 0 70 uF capacitance with an ESR of 1 or less is recommended to ensure stability of the ADP220 ADP221 Transient response to changes in load current is also affected by output capacitance Using a larger value of output capacitance improves the transient response of the A
24. rgy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev D Page 5 of 20 ADP220 ADP221 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS f VOUT4 S wt PE x X I GND VIN ri X P d BPRS d EN2 VOUT2 ri M 4 P TOP VIEW BALL SIDE DOWN Not to Scale 07572 003 Figure 3 Pin Configuration Table 5 Pin Function Descriptions Pin No Mnemonic Description A1 EN1 Enable Input for Regulator 1 Drive EN1 high to turn on Regulator 1 drive it low to turn off Regulator 1 For automatic startup connect ENT to VIN B1 GND Ground Pin C1 EN2 Enable Input for Regulator 2 Drive EN2 high to turn on Regulator 2 drive it low to turn off Regulator 2 For automatic startup connect EN2 to VIN A2 VOUT1 Regulated Output Voltage 1 Connect a 1 uF or greater output capacitor between VOUT1 and GND B2 VIN Regulator Input Supply Bypass VIN to GND with a 1 pF or greater capacitor C2 VOUT2 Regulated Output Voltage 2 Connect a 1 uF or greater output capacitor between VOUT2 and GND Rev D Page 6 of 20 ADP220 ADP221 TYPICAL PERFORMANCE CHARACTERISTICS Vm 3 3 V Vouti Vourz 2 8 V Iour 10 mA Cm Coun Cour 1 uF Ta 25 C unless otherwise noted
25. s shown in Table 6 a point of diminishing returns eventually is reached beyond which an increase in the copper size does not yield significant heat dissipation benefits Place the input capacitor as close as possible to the VIN and GND pins Place the output capacitors as close as possible to the VOUT1 VOUT2 and GND pins Use 0402 or 0603 size capacitors and resistors to achieve the smallest possible footprint solution on boards where area is limited 07572 040 07572 041 Figure 41 Example of PCB Layout Bottom Side Rev D Page 16 of 20 ADP220 ADP221 OUTLINE DIMENSIONS 0 675 0 505 0 515 SEATING PLANE CORNER 0348 1 50 0295 145 i 0 245 B 1 40 j 0 075 VIEW 0 270 COPLANARITY BALL SIDE DOWN 0 240 0 50 BSC 0 210 BOTTOM VIEW BALL SIDE UP 2 Figure 42 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 Dimensions show in millimeters ORDERING GUIDE Temperature Output Package Model Range Voltage V Package Description Option Branding ADP220ACBZ 1118R7 40 C to 125 C 1 1 1 8 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 LFY ADP220ACBZ 1812R7 40 C to 125 1 8 1 2 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 LEK ADP220ACBZ 1827R7 40 C to 125 1 8 2 7 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 LEH ADP220ACBZ 2623R7 40 C to 125 2 6 2 3 6 Ball Wafer Level Chip Scale Package WLCSP CB 6 2 LGD ADP220ACBZ
26. tion Note MicroCSP Wafer Level Chip Scale Package Yn is the junction to board thermal characterization parameter with units of C W of the package is based on modeling and calculation using a 4 layer board The JESD51 12 Guidelines for Reporting and Using Package Thermal Information states that thermal characterization parameters are not the same as thermal resistances measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance Therefore thermal paths include convection from the top of the package as well as radiation from the package Factors that make more useful in real world applications Maximum junction temperature T is calculated from the board temperature Ts and power dissipation Pp using the following formula Ts Pp x Refer to JEDEC JESD51 8 and JESD51 12 for more detailed information on V THERMAL RESISTANCE and are specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 4 Package Type Osa Vs Unit 6 Ball 0 5 mm Pitch WLCSP 260 43 8 C W ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high ene
27. ypical Oj Values Copper Size mm ADP220 ADP221 C W 0 200 50 119 100 118 300 115 500 113 Device soldered to minimum size pin traces The junction temperature of the ADP220 ADP221 can be calculated from the following equation Ty Ta Pp x Oya 2 where Ta is the ambient temperature Ppis the power dissipation in the die given by Pp Vin Vout x SE X Vm x Ienn 3 where Iroan is the load current is the ground current Vin and Vour are input and output voltages respectively Power dissipation due to ground current is quite small and can be ignored Therefore the junction temperature equation simplifies to Ty Ta Z Vm Vout x Itoap x Oja 4 As shown in Equation 4 for a given ambient temperature input to output voltage differential and continuous load current there exists a minimum copper size requirement for the PCB to ensure the junction temperature does not rise above 125 C Figure 35 to Figure 39 show junction temperature calculations for different ambient temperatures total power dissipation and areas of PCB copper In cases where the board temperature is known the thermal characterization parameter can be used to estimate the junction temperature rise T is calculated from Ts and Pp using the formula T Ts Pp x Vy 5 The typical V value for the 6 ball WLCSP is 43 8 C W Rev D Page 14 of 20 ADP220 ADP221 135

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